* [Qemu-devel][PATCH 00/12] KVM Support for MIPS32 Processors
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
The following patchset implements KVM support for MIPS32 processors,
using Trap & Emulate, with basic runtime binary translation to improve
performance.
In KVM mode, CPU virtualization is handled via the kvm kernel module,
while system and I/O virtualization leverage the Malta model already present
in QEMU.
Both Guest kernel and Guest Userspace execute in UM. The Guest address space is
as folows:
Guest User address space: 0x00000000 -> 0x40000000
Guest Kernel Unmapped: 0x40000000 -> 0x60000000
Guest Kernel Mapped: 0x60000000 -> 0x80000000
As a result, Guest Usermode virtual memory is limited to 1GB.
The Malta model has been enhanced to support SMP guest kernels via support
for the CPS bootcode from MIPS which supports bootstrapping multiple cpus.
A model for the MIPS GIC has also been added to support IPIs.
This allows booting Linux in full SMP mode with a cluster of MIPS32R2 cpus.
There is a companion kernel patchset for KVM that has been posted on
the KVM/MIPS mailing lists.
--
Sanjay Lal (12):
KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
KVM/MIPS: GIC emulation for SMP guests.
KVM/MIPS: Add save/restore state APIs for saving/restoring KVM
guests.
KVM/MIPS: Do not start the periodic timer in KVM mode. Compare/Count
timer interrupts are handled in-kernel.
KVM/MIPS: In KVM mode, inject IRQ2 (I/O) interupts via ioctls().
COP0 emulation is in-kernel
KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest Physical
addresses.
KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the
build.
KVM/MIPS: set sigmask length to 16 for MIPS targets.
KVM/MIPS: Set page size to 16K in KVM mode.
KVM/MIPS: MIPS specfic APIs for KVM.
KVM/MIPS: General KVM support and support for SMP Guests
configure | 17 +-
hw/gt64xxx.c | 317 +++++++++++++++++++++++++++++
hw/mips/Makefile.objs | 2 +-
hw/mips_addr.c | 14 ++
hw/mips_cps_bootcode.h | 310 ++++++++++++++++++++++++++++
hw/mips_cpudevs.h | 4 +
hw/mips_gcmpregs.h | 122 +++++++++++
hw/mips_gic.c | 418 ++++++++++++++++++++++++++++++++++++++
hw/mips_gic.h | 378 ++++++++++++++++++++++++++++++++++
hw/mips_int.c | 15 ++
hw/mips_malta.c | 192 +++++++++++------
hw/mips_timer.c | 13 +-
kvm-all.c | 5 +
linux-headers/asm-mips/kvm.h | 94 +++++++++
linux-headers/asm-mips/kvm_para.h | 10 +
target-mips/Makefile.objs | 1 +
target-mips/kvm.c | 292 ++++++++++++++++++++++++++
target-mips/kvm_mips.h | 21 ++
target-mips/mips-defs.h | 5 +
19 files changed, 2157 insertions(+), 73 deletions(-)
create mode 100644 hw/mips_cps_bootcode.h
create mode 100644 hw/mips_gcmpregs.h
create mode 100644 hw/mips_gic.c
create mode 100644 hw/mips_gic.h
create mode 100644 linux-headers/asm-mips/kvm.h
create mode 100644 linux-headers/asm-mips/kvm_para.h
create mode 100644 target-mips/kvm.c
create mode 100644 target-mips/kvm_mips.h
--
1.7.11.3
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 00/12] KVM Support for MIPS32 Processors
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
The following patchset implements KVM support for MIPS32 processors,
using Trap & Emulate, with basic runtime binary translation to improve
performance.
In KVM mode, CPU virtualization is handled via the kvm kernel module,
while system and I/O virtualization leverage the Malta model already present
in QEMU.
Both Guest kernel and Guest Userspace execute in UM. The Guest address space is
as folows:
Guest User address space: 0x00000000 -> 0x40000000
Guest Kernel Unmapped: 0x40000000 -> 0x60000000
Guest Kernel Mapped: 0x60000000 -> 0x80000000
As a result, Guest Usermode virtual memory is limited to 1GB.
The Malta model has been enhanced to support SMP guest kernels via support
for the CPS bootcode from MIPS which supports bootstrapping multiple cpus.
A model for the MIPS GIC has also been added to support IPIs.
This allows booting Linux in full SMP mode with a cluster of MIPS32R2 cpus.
There is a companion kernel patchset for KVM that has been posted on
the KVM/MIPS mailing lists.
--
Sanjay Lal (12):
KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
KVM/MIPS: GIC emulation for SMP guests.
KVM/MIPS: Add save/restore state APIs for saving/restoring KVM
guests.
KVM/MIPS: Do not start the periodic timer in KVM mode. Compare/Count
timer interrupts are handled in-kernel.
KVM/MIPS: In KVM mode, inject IRQ2 (I/O) interupts via ioctls().
COP0 emulation is in-kernel
KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest Physical
addresses.
KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the
build.
KVM/MIPS: set sigmask length to 16 for MIPS targets.
KVM/MIPS: Set page size to 16K in KVM mode.
KVM/MIPS: MIPS specfic APIs for KVM.
KVM/MIPS: General KVM support and support for SMP Guests
configure | 17 +-
hw/gt64xxx.c | 317 +++++++++++++++++++++++++++++
hw/mips/Makefile.objs | 2 +-
hw/mips_addr.c | 14 ++
hw/mips_cps_bootcode.h | 310 ++++++++++++++++++++++++++++
hw/mips_cpudevs.h | 4 +
hw/mips_gcmpregs.h | 122 +++++++++++
hw/mips_gic.c | 418 ++++++++++++++++++++++++++++++++++++++
hw/mips_gic.h | 378 ++++++++++++++++++++++++++++++++++
hw/mips_int.c | 15 ++
hw/mips_malta.c | 192 +++++++++++------
hw/mips_timer.c | 13 +-
kvm-all.c | 5 +
linux-headers/asm-mips/kvm.h | 94 +++++++++
linux-headers/asm-mips/kvm_para.h | 10 +
target-mips/Makefile.objs | 1 +
target-mips/kvm.c | 292 ++++++++++++++++++++++++++
target-mips/kvm_mips.h | 21 ++
target-mips/mips-defs.h | 5 +
19 files changed, 2157 insertions(+), 73 deletions(-)
create mode 100644 hw/mips_cps_bootcode.h
create mode 100644 hw/mips_gcmpregs.h
create mode 100644 hw/mips_gic.c
create mode 100644 hw/mips_gic.h
create mode 100644 linux-headers/asm-mips/kvm.h
create mode 100644 linux-headers/asm-mips/kvm_para.h
create mode 100644 target-mips/kvm.c
create mode 100644 target-mips/kvm_mips.h
--
1.7.11.3
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/mips_cps_bootcode.h | 310 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 310 insertions(+)
create mode 100644 hw/mips_cps_bootcode.h
diff --git a/hw/mips_cps_bootcode.h b/hw/mips_cps_bootcode.h
new file mode 100644
index 0000000..40289a4
--- /dev/null
+++ b/hw/mips_cps_bootcode.h
@@ -0,0 +1,310 @@
+/* Sample boot code for 1004K CPS (Coherent Processing System.)
+ * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
+ *
+ * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
+ */
+
+#ifndef __MIPS_CPS_BOOTCODE_H__
+#define __MIPS_CPS_BOOTCODE_H__
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#error CPS bootcode for MIPS Big Endian target not available yet
+#else
+static unsigned char __boot_cps_data[] = {
+ 0x3f,0x01,0x00,0x10,0x00,0x48,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xdc,0xbb,0x1a,0x3c,
+ 0x80,0x02,0x5a,0x37,0x01,0x78,0x1b,0x40,0x00,0x48,0x7b,0x7f,0x20,0x00,0x7b,
+ 0x27,0x00,0x00,0x5b,0xaf,0x18,0x00,0x00,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xbf,0x18,
+ 0x3c,0x10,0x04,0x18,0x37,0x00,0xf8,0x84,0x40,0x00,0xc0,0x04,0x40,0x00,0x00,
+ 0x04,0xaf,0x00,0xf8,0x04,0x40,0xff,0xff,0x00,0x10,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+ 0x41,0x00,0x38,0xc1,0x41,0x00,0x40,0xc1,0x41,0x00,0x48,0xc1,0x41,0x00,0x50,
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+ 0xc1,0x41,0x00,0xd0,0xc1,0x41,0x00,0xd8,0xc1,0x41,0x00,0xe0,0xc1,0x41,0x00,
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+ 0x00,0xf8,0xc1,0x41,0xdc,0xff,0x00,0x10,0xff,0xff,0xde,0x23,0xff,0xff,0x01,
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+ 0xa4,0xac,0x80,0x01,0xa4,0xac,0x80,0x03,0xa4,0xac,0xff,0x00,0x04,0x24,0x04,
+ 0x03,0xa4,0xac,0x04,0x01,0xa4,0xac,0x84,0x01,0xa4,0xac,0x84,0x03,0xa4,0xac,
+ 0x01,0x00,0x04,0x24,0x00,0x23,0xa4,0xac,0x00,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0x20,0x23,0xa4,0xac,0x20,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x40,0x23,
+ 0xa4,0xac,0x40,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x60,0x23,0xa4,0xac,0x60,
+ 0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x80,0x23,0xa4,0xac,0x80,0x24,0xa4,0xac,
+ 0x40,0x20,0x04,0x00,0xa0,0x23,0xa4,0xac,0xa0,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0xc0,0x23,0xa4,0xac,0xc0,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0xe0,0x23,
+ 0xa4,0xac,0xe0,0x24,0xa4,0xac,0xdc,0xbb,0x05,0x3c,0x00,0x80,0xa5,0x34,0x00,
+ 0x00,0xa7,0x8c,0x40,0x00,0xe4,0x7c,0x04,0x00,0x80,0x10,0x00,0x00,0x00,0x00,
+ 0x00,0x80,0x04,0x3c,0x05,0x00,0x84,0x34,0x48,0x00,0xa4,0xac,0x80,0x00,0xe4,
+ 0x7c,0x04,0x00,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x80,0x04,0x3c,0x04,0x00,
+ 0x84,0x34,0x50,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xc0,
+ 0xbb,0x05,0x3c,0x0c,0x00,0xa4,0x8c,0x04,0x84,0x04,0x7c,0x0c,0x00,0xa4,0xac,
+ 0x00,0x01,0x04,0x24,0x04,0x00,0xa4,0xac,0x01,0x00,0x04,0x24,0x0c,0x00,0xa4,
+ 0xac,0x00,0x01,0x04,0x3c,0x01,0x01,0x84,0x34,0x10,0x00,0xa4,0xac,0x02,0x02,
+ 0x04,0x3c,0x00,0x02,0x84,0x34,0x14,0x00,0xa4,0xac,0x02,0x03,0x04,0x24,0x18,
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+ 0x00,0xa4,0xac,0x06,0x00,0x04,0x3c,0x06,0x27,0x84,0x34,0x50,0x00,0xa4,0xac,
+ 0x06,0x00,0x04,0x24,0x54,0x00,0xa4,0xac,0x14,0x00,0x04,0x24,0x58,0x00,0xa4,
+ 0xac,0x01,0x01,0x04,0x3c,0x01,0x01,0x84,0x34,0x60,0x00,0xa4,0xac,0x01,0x01,
+ 0x04,0x3c,0x64,0x00,0xa4,0xac,0x01,0x00,0x04,0x3c,0x00,0x01,0x84,0x34,0x68,
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+ 0x0c,0x00,0xa4,0x8c,0x04,0x84,0x24,0x7c,0x0c,0x00,0xa4,0xac,0x08,0x00,0xe0,
+ 0x03,0x00,0x00,0x00,0x00,0xc0,0xbf,0x05,0x3c,0x00,0x10,0xa5,0x24,0xc0,0xbf,
+ 0x06,0x3c,0x00,0x10,0xc6,0x24,0x44,0xef,0x26,0x7c,0xc0,0xbf,0x07,0x3c,0x18,
+ 0x11,0xe7,0x24,0x44,0xef,0x27,0x7c,0x06,0x00,0xc7,0x10,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0xa4,0x8c,0x00,0x00,0xc4,0xac,0x04,0x00,0xc6,0x24,0xfc,0xff,0xe6,
+ 0x14,0x04,0x00,0xa5,0x24,0xc0,0xbf,0x05,0x3c,0x18,0x11,0xa5,0x24,0x44,0xef,
+ 0x25,0x7c,0xc0,0xbf,0x07,0x3c,0x1c,0x11,0xe7,0x24,0x44,0xef,0x27,0x7c,0x05,
+ 0x00,0xa7,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0xac,0x04,0x00,0xa5,0x24,
+ 0xfd,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0x12,0x00,0x60,0x1a,0x01,0x00,0x07,0x24,0x0a,0x00,0xc0,0x13,0x00,0x00,
+ 0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,0x00,0x10,0x20,0xc4,0xaf,0x03,
+ 0x00,0x04,0x24,0x00,0x40,0xc4,0xaf,0xfa,0xff,0x67,0x16,0x01,0x00,0xe7,0x20,
+ 0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,
+ 0x00,0x18,0x20,0xc4,0xae,0x00,0x40,0xc0,0xae,0xfb,0xff,0x67,0x16,0x01,0x00,
+ 0xe7,0x20,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x0a,0x40,0xc0,
+ 0x14,0x4b,0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,
+ 0x04,0x58,0x6e,0x01,0x80,0x15,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,
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+ 0x0e,0x3c,0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,
+ 0x00,0xc8,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,
+ 0x44,0xef,0x1f,0x7c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x80,0x12,0x4b,
+ 0x7d,0x13,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
+ 0x6e,0x01,0x40,0x13,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0xc0,
+ 0x11,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,
+ 0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x02,0xe0,0x80,0x40,0x02,0xe8,0x80,
+ 0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xc9,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,
+ 0xe0,0x15,0x20,0x70,0xcb,0x01,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x13,
+ 0x00,0x60,0x10,0x00,0x00,0x00,0x00,0xbf,0xbf,0x05,0x3c,0x00,0x80,0xa5,0x34,
+ 0x02,0x00,0x04,0x24,0x04,0x20,0x64,0x02,0xff,0xff,0x84,0x24,0x20,0x00,0xa4,
+ 0xac,0x00,0x00,0xc4,0x8e,0x00,0x1a,0x84,0x7c,0x09,0x00,0x80,0x10,0xff,0xff,
+ 0x04,0x3c,0x90,0x00,0xa4,0xac,0x98,0x00,0xa4,0xac,0xa0,0x00,0xa4,0xac,0xa8,
+ 0x00,0xa4,0xac,0xb0,0x00,0xa4,0xac,0xb8,0x00,0xa4,0xac,0xc0,0x00,0xa4,0xac,
+ 0xc8,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x0f,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x01,0x00,0x09,0x24,0x04,0x48,0x69,0x02,0x40,0x48,0x09,0x00,0xff,
+ 0xff,0x29,0x25,0x08,0x20,0xc9,0xae,0xc0,0x00,0x00,0x00,0x21,0x38,0x00,0x00,
+ 0x00,0x24,0x07,0x00,0x18,0x20,0xc4,0xae,0x08,0x40,0xc4,0x8e,0xfe,0xff,0x80,
+ 0x10,0x00,0x00,0x00,0x00,0xfa,0xff,0xf3,0x14,0x01,0x00,0xe7,0x24,0x08,0x00,
+ 0xe0,0x03,0x00,0x00,0x00,0x00,0x12,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x08,
+ 0x00,0xc4,0x8e,0x50,0x00,0x07,0x24,0x04,0x38,0xe4,0x7c,0x08,0x00,0xc4,0xae,
+ 0x08,0x00,0xc4,0x8e,0x00,0x01,0x84,0x7c,0x36,0x00,0x80,0x14,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x2d,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x08,0x00,0xc4,0x8e,0x2a,0x00,0x00,0x16,0x00,0x01,0x84,0x7c,0x28,
+ 0x00,0x80,0x10,0x00,0x00,0x00,0x00,0x02,0x80,0x0a,0x40,0x00,0x19,0x4b,0x7d,
+ 0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,0x6e,
+ 0x01,0x00,0x1a,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0x00,0x18,
+ 0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,0x04,
+ 0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xcb,0xbd,
+ 0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x00,0x1d,0x4b,
+ 0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
+ 0x6e,0x01,0x00,0x1e,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0x00,
+ 0x1c,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,
+ 0x04,0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xca,
+ 0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x04,0x00,
+ 0x60,0x10,0x00,0x00,0x00,0x00,0x08,0x00,0xc4,0x8e,0x04,0x38,0x04,0x7c,0x08,
+ 0x00,0xc4,0xae,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x6b,0x00,0xa0,0x12,
+ 0x00,0x00,0x00,0x00,0x69,0x00,0x80,0x12,0x00,0x00,0x00,0x00,0x01,0x00,0x08,
+ 0x40,0x02,0x00,0x08,0x35,0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x02,0x00,
+ 0x08,0x40,0x00,0x38,0x0a,0x7d,0x80,0x1a,0x0b,0x7d,0x21,0x60,0x00,0x00,0x01,
+ 0x08,0x08,0x40,0x04,0x38,0x88,0x7d,0x01,0x08,0x88,0x40,0xc0,0x00,0x00,0x00,
+ 0x2f,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x24,0x04,0x10,0x88,
+ 0x41,0xc0,0x00,0x00,0x00,0x2a,0x48,0x6c,0x01,0x05,0x00,0x20,0x15,0x21,0x48,
+ 0x60,0x01,0x02,0x40,0x01,0x41,0x44,0xe5,0x88,0x7d,0x02,0x08,0x88,0x41,0x21,
+ 0x48,0x80,0x01,0x02,0x40,0x02,0x41,0x04,0x18,0x28,0x7d,0x02,0x10,0x88,0x41,
+ 0x00,0x04,0x08,0x24,0x01,0x10,0x88,0x41,0x20,0x08,0x80,0x41,0x20,0x10,0x80,
+ 0x41,0x20,0x18,0x80,0x41,0x20,0x20,0x80,0x41,0x20,0x28,0x80,0x41,0x20,0x30,
+ 0x80,0x41,0x20,0x38,0x80,0x41,0x20,0x40,0x80,0x41,0x20,0x48,0x80,0x41,0x20,
+ 0x50,0x80,0x41,0x20,0x58,0x80,0x41,0x20,0x60,0x80,0x41,0x20,0x68,0x80,0x41,
+ 0x20,0x70,0x80,0x41,0x20,0x78,0x80,0x41,0x20,0x80,0x80,0x41,0x20,0x88,0x80,
+ 0x41,0x20,0x90,0x80,0x41,0x20,0x98,0x80,0x41,0x20,0xa0,0x80,0x41,0x20,0xa8,
+ 0x80,0x41,0x20,0xb0,0x80,0x41,0x20,0xb8,0x80,0x41,0x20,0xc0,0x80,0x41,0x20,
+ 0xc8,0x80,0x41,0x20,0xd0,0x80,0x41,0x20,0xd8,0x80,0x41,0x20,0xe0,0x80,0x41,
+ 0x20,0xe8,0x80,0x41,0x20,0xf0,0x80,0x41,0x20,0xf8,0x80,0x41,0x2a,0x48,0x6c,
+ 0x01,0x21,0x00,0x20,0x15,0x00,0x00,0x00,0x00,0x01,0x40,0x01,0x41,0xc4,0x7b,
+ 0x08,0x7c,0x01,0x08,0x88,0x41,0x1c,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x02,
+ 0x40,0x01,0x41,0x04,0x00,0x08,0x7c,0x02,0x00,0x08,0x35,0x02,0x08,0x88,0x41,
+ 0x00,0x60,0x08,0x40,0x00,0x60,0x88,0x41,0x34,0x12,0x08,0x3c,0x78,0x56,0x08,
+ 0x35,0x00,0x70,0x88,0x41,0x00,0x68,0x80,0x41,0x00,0x80,0x08,0x40,0x00,0x80,
+ 0x88,0x41,0x01,0x40,0x0f,0x41,0x00,0x48,0x08,0x7d,0x20,0xb8,0x88,0x41,0xc0,
+ 0xbf,0x05,0x3c,0x00,0x00,0xa5,0x24,0x44,0xef,0x05,0x7c,0x03,0x10,0x85,0x41,
+ 0x01,0x40,0x02,0x41,0x84,0x52,0x08,0x7c,0x00,0x20,0x08,0x35,0x01,0x10,0x88,
+ 0x41,0x04,0x10,0x80,0x41,0x02,0x40,0x01,0x41,0x01,0x00,0x08,0x35,0x02,0x08,
+ 0x88,0x41,0x01,0x00,0x8c,0x25,0x2b,0x48,0x4c,0x01,0xa6,0xff,0x20,0x11,0x00,
+ 0x00,0x00,0x00,0x01,0x00,0x08,0x40,0x01,0x00,0x08,0x35,0x44,0x08,0x08,0x7c,
+ 0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0xf8,0xff,0xbd,0x27,0x1f,0x00,0x80,0x14,0x04,0x00,0xbf,0xaf,0x00,0x80,
+ 0x02,0x3c,0x00,0x0f,0x42,0x24,0x1c,0x00,0x43,0x8c,0x01,0x00,0x05,0x24,0x07,
+ 0x00,0x63,0x34,0x1c,0x00,0x43,0xac,0x10,0x80,0x83,0x8f,0x02,0x00,0x63,0x28,
+ 0x11,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x40,0x21,0x05,0x00,0x21,0x20,0x82,
+ 0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0xfc,
+ 0xff,0x60,0x10,0x00,0x00,0x00,0x00,0x10,0x80,0x83,0x8f,0x01,0x00,0xa5,0x24,
+ 0x2a,0x18,0xa3,0x00,0xf1,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x04,0x00,0xbf,
+ 0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x08,0x00,0xbd,0x27,0x00,0x80,
+ 0x02,0x3c,0x40,0x21,0x04,0x00,0x00,0x0f,0x42,0x24,0x21,0x20,0x44,0x00,0x00,
+ 0x00,0x80,0xac,0x04,0x00,0x80,0xac,0x08,0x00,0x80,0xac,0x0c,0x00,0x80,0xac,
+ 0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,0x1c,0x00,0x83,
+ 0x8c,0x02,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x1c,0x00,0x83,0x8c,0x02,0x00,0x63,0x30,0xfc,0xff,0x60,0x10,0x00,
+ 0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x04,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,
+ 0x00,0x00,0x83,0x8c,0x04,0x00,0x88,0x8c,0x08,0x00,0x89,0x8c,0x0c,0x00,0x8a,
+ 0x8c,0x21,0xf8,0x60,0x00,0x21,0xe0,0x00,0x01,0x21,0xe8,0x20,0x01,0x21,0x20,
+ 0x40,0x01,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,
+ 0x38,0x00,0x00,0x05,0x04,0xf0,0x0b,0x00,0x00,0x00,0x00,
+};
+
+#endif /* TARGET_WORDS_BIGENDIAN */
+
+#endif /* __MIPS_CPS_BOOTCODE_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/mips_cps_bootcode.h | 310 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 310 insertions(+)
create mode 100644 hw/mips_cps_bootcode.h
diff --git a/hw/mips_cps_bootcode.h b/hw/mips_cps_bootcode.h
new file mode 100644
index 0000000..40289a4
--- /dev/null
+++ b/hw/mips_cps_bootcode.h
@@ -0,0 +1,310 @@
+/* Sample boot code for 1004K CPS (Coherent Processing System.)
+ * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
+ *
+ * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
+ */
+
+#ifndef __MIPS_CPS_BOOTCODE_H__
+#define __MIPS_CPS_BOOTCODE_H__
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#error CPS bootcode for MIPS Big Endian target not available yet
+#else
+static unsigned char __boot_cps_data[] = {
+ 0x3f,0x01,0x00,0x10,0x00,0x48,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+ 0xa4,0xac,0x40,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x60,0x23,0xa4,0xac,0x60,
+ 0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x80,0x23,0xa4,0xac,0x80,0x24,0xa4,0xac,
+ 0x40,0x20,0x04,0x00,0xa0,0x23,0xa4,0xac,0xa0,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0xc0,0x23,0xa4,0xac,0xc0,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0xe0,0x23,
+ 0xa4,0xac,0xe0,0x24,0xa4,0xac,0xdc,0xbb,0x05,0x3c,0x00,0x80,0xa5,0x34,0x00,
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+ 0x00,0x80,0x04,0x3c,0x05,0x00,0x84,0x34,0x48,0x00,0xa4,0xac,0x80,0x00,0xe4,
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+ 0x84,0x34,0x50,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xc0,
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+ 0x00,0x00,0xa4,0x8c,0x00,0x00,0xc4,0xac,0x04,0x00,0xc6,0x24,0xfc,0xff,0xe6,
+ 0x14,0x04,0x00,0xa5,0x24,0xc0,0xbf,0x05,0x3c,0x18,0x11,0xa5,0x24,0x44,0xef,
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+ 0xfd,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
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+ 0x00,0x18,0x20,0xc4,0xae,0x00,0x40,0xc0,0xae,0xfb,0xff,0x67,0x16,0x01,0x00,
+ 0xe7,0x20,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x0a,0x40,0xc0,
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+ 0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x02,0xe0,0x80,0x40,0x02,0xe8,0x80,
+ 0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xc9,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,
+ 0xe0,0x15,0x20,0x70,0xcb,0x01,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x13,
+ 0x00,0x60,0x10,0x00,0x00,0x00,0x00,0xbf,0xbf,0x05,0x3c,0x00,0x80,0xa5,0x34,
+ 0x02,0x00,0x04,0x24,0x04,0x20,0x64,0x02,0xff,0xff,0x84,0x24,0x20,0x00,0xa4,
+ 0xac,0x00,0x00,0xc4,0x8e,0x00,0x1a,0x84,0x7c,0x09,0x00,0x80,0x10,0xff,0xff,
+ 0x04,0x3c,0x90,0x00,0xa4,0xac,0x98,0x00,0xa4,0xac,0xa0,0x00,0xa4,0xac,0xa8,
+ 0x00,0xa4,0xac,0xb0,0x00,0xa4,0xac,0xb8,0x00,0xa4,0xac,0xc0,0x00,0xa4,0xac,
+ 0xc8,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x0f,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x01,0x00,0x09,0x24,0x04,0x48,0x69,0x02,0x40,0x48,0x09,0x00,0xff,
+ 0xff,0x29,0x25,0x08,0x20,0xc9,0xae,0xc0,0x00,0x00,0x00,0x21,0x38,0x00,0x00,
+ 0x00,0x24,0x07,0x00,0x18,0x20,0xc4,0xae,0x08,0x40,0xc4,0x8e,0xfe,0xff,0x80,
+ 0x10,0x00,0x00,0x00,0x00,0xfa,0xff,0xf3,0x14,0x01,0x00,0xe7,0x24,0x08,0x00,
+ 0xe0,0x03,0x00,0x00,0x00,0x00,0x12,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x08,
+ 0x00,0xc4,0x8e,0x50,0x00,0x07,0x24,0x04,0x38,0xe4,0x7c,0x08,0x00,0xc4,0xae,
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+ 0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xcb,0xbd,
+ 0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x00,0x1d,0x4b,
+ 0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
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+ 0x04,0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xca,
+ 0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x04,0x00,
+ 0x60,0x10,0x00,0x00,0x00,0x00,0x08,0x00,0xc4,0x8e,0x04,0x38,0x04,0x7c,0x08,
+ 0x00,0xc4,0xae,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x6b,0x00,0xa0,0x12,
+ 0x00,0x00,0x00,0x00,0x69,0x00,0x80,0x12,0x00,0x00,0x00,0x00,0x01,0x00,0x08,
+ 0x40,0x02,0x00,0x08,0x35,0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x02,0x00,
+ 0x08,0x40,0x00,0x38,0x0a,0x7d,0x80,0x1a,0x0b,0x7d,0x21,0x60,0x00,0x00,0x01,
+ 0x08,0x08,0x40,0x04,0x38,0x88,0x7d,0x01,0x08,0x88,0x40,0xc0,0x00,0x00,0x00,
+ 0x2f,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x24,0x04,0x10,0x88,
+ 0x41,0xc0,0x00,0x00,0x00,0x2a,0x48,0x6c,0x01,0x05,0x00,0x20,0x15,0x21,0x48,
+ 0x60,0x01,0x02,0x40,0x01,0x41,0x44,0xe5,0x88,0x7d,0x02,0x08,0x88,0x41,0x21,
+ 0x48,0x80,0x01,0x02,0x40,0x02,0x41,0x04,0x18,0x28,0x7d,0x02,0x10,0x88,0x41,
+ 0x00,0x04,0x08,0x24,0x01,0x10,0x88,0x41,0x20,0x08,0x80,0x41,0x20,0x10,0x80,
+ 0x41,0x20,0x18,0x80,0x41,0x20,0x20,0x80,0x41,0x20,0x28,0x80,0x41,0x20,0x30,
+ 0x80,0x41,0x20,0x38,0x80,0x41,0x20,0x40,0x80,0x41,0x20,0x48,0x80,0x41,0x20,
+ 0x50,0x80,0x41,0x20,0x58,0x80,0x41,0x20,0x60,0x80,0x41,0x20,0x68,0x80,0x41,
+ 0x20,0x70,0x80,0x41,0x20,0x78,0x80,0x41,0x20,0x80,0x80,0x41,0x20,0x88,0x80,
+ 0x41,0x20,0x90,0x80,0x41,0x20,0x98,0x80,0x41,0x20,0xa0,0x80,0x41,0x20,0xa8,
+ 0x80,0x41,0x20,0xb0,0x80,0x41,0x20,0xb8,0x80,0x41,0x20,0xc0,0x80,0x41,0x20,
+ 0xc8,0x80,0x41,0x20,0xd0,0x80,0x41,0x20,0xd8,0x80,0x41,0x20,0xe0,0x80,0x41,
+ 0x20,0xe8,0x80,0x41,0x20,0xf0,0x80,0x41,0x20,0xf8,0x80,0x41,0x2a,0x48,0x6c,
+ 0x01,0x21,0x00,0x20,0x15,0x00,0x00,0x00,0x00,0x01,0x40,0x01,0x41,0xc4,0x7b,
+ 0x08,0x7c,0x01,0x08,0x88,0x41,0x1c,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x02,
+ 0x40,0x01,0x41,0x04,0x00,0x08,0x7c,0x02,0x00,0x08,0x35,0x02,0x08,0x88,0x41,
+ 0x00,0x60,0x08,0x40,0x00,0x60,0x88,0x41,0x34,0x12,0x08,0x3c,0x78,0x56,0x08,
+ 0x35,0x00,0x70,0x88,0x41,0x00,0x68,0x80,0x41,0x00,0x80,0x08,0x40,0x00,0x80,
+ 0x88,0x41,0x01,0x40,0x0f,0x41,0x00,0x48,0x08,0x7d,0x20,0xb8,0x88,0x41,0xc0,
+ 0xbf,0x05,0x3c,0x00,0x00,0xa5,0x24,0x44,0xef,0x05,0x7c,0x03,0x10,0x85,0x41,
+ 0x01,0x40,0x02,0x41,0x84,0x52,0x08,0x7c,0x00,0x20,0x08,0x35,0x01,0x10,0x88,
+ 0x41,0x04,0x10,0x80,0x41,0x02,0x40,0x01,0x41,0x01,0x00,0x08,0x35,0x02,0x08,
+ 0x88,0x41,0x01,0x00,0x8c,0x25,0x2b,0x48,0x4c,0x01,0xa6,0xff,0x20,0x11,0x00,
+ 0x00,0x00,0x00,0x01,0x00,0x08,0x40,0x01,0x00,0x08,0x35,0x44,0x08,0x08,0x7c,
+ 0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0xf8,0xff,0xbd,0x27,0x1f,0x00,0x80,0x14,0x04,0x00,0xbf,0xaf,0x00,0x80,
+ 0x02,0x3c,0x00,0x0f,0x42,0x24,0x1c,0x00,0x43,0x8c,0x01,0x00,0x05,0x24,0x07,
+ 0x00,0x63,0x34,0x1c,0x00,0x43,0xac,0x10,0x80,0x83,0x8f,0x02,0x00,0x63,0x28,
+ 0x11,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x40,0x21,0x05,0x00,0x21,0x20,0x82,
+ 0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0xfc,
+ 0xff,0x60,0x10,0x00,0x00,0x00,0x00,0x10,0x80,0x83,0x8f,0x01,0x00,0xa5,0x24,
+ 0x2a,0x18,0xa3,0x00,0xf1,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x04,0x00,0xbf,
+ 0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x08,0x00,0xbd,0x27,0x00,0x80,
+ 0x02,0x3c,0x40,0x21,0x04,0x00,0x00,0x0f,0x42,0x24,0x21,0x20,0x44,0x00,0x00,
+ 0x00,0x80,0xac,0x04,0x00,0x80,0xac,0x08,0x00,0x80,0xac,0x0c,0x00,0x80,0xac,
+ 0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,0x1c,0x00,0x83,
+ 0x8c,0x02,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x1c,0x00,0x83,0x8c,0x02,0x00,0x63,0x30,0xfc,0xff,0x60,0x10,0x00,
+ 0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x04,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,
+ 0x00,0x00,0x83,0x8c,0x04,0x00,0x88,0x8c,0x08,0x00,0x89,0x8c,0x0c,0x00,0x8a,
+ 0x8c,0x21,0xf8,0x60,0x00,0x21,0xe0,0x00,0x01,0x21,0xe8,0x20,0x01,0x21,0x20,
+ 0x40,0x01,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,
+ 0x38,0x00,0x00,0x05,0x04,0xf0,0x0b,0x00,0x00,0x00,0x00,
+};
+
+#endif /* TARGET_WORDS_BIGENDIAN */
+
+#endif /* __MIPS_CPS_BOOTCODE_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 01/12] MIPS: Bootcode for MIPS SMP configurations with a GCMP
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/mips_cps_bootcode.h | 310 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 310 insertions(+)
create mode 100644 hw/mips_cps_bootcode.h
diff --git a/hw/mips_cps_bootcode.h b/hw/mips_cps_bootcode.h
new file mode 100644
index 0000000..40289a4
--- /dev/null
+++ b/hw/mips_cps_bootcode.h
@@ -0,0 +1,310 @@
+/* Sample boot code for 1004K CPS (Coherent Processing System.)
+ * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
+ *
+ * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
+ */
+
+#ifndef __MIPS_CPS_BOOTCODE_H__
+#define __MIPS_CPS_BOOTCODE_H__
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#error CPS bootcode for MIPS Big Endian target not available yet
+#else
+static unsigned char __boot_cps_data[] = {
+ 0x3f,0x01,0x00,0x10,0x00,0x48,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xdc,0xbb,0x1a,0x3c,
+ 0x80,0x02,0x5a,0x37,0x01,0x78,0x1b,0x40,0x00,0x48,0x7b,0x7f,0x20,0x00,0x7b,
+ 0x27,0x00,0x00,0x5b,0xaf,0x18,0x00,0x00,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xbf,0x18,
+ 0x3c,0x10,0x04,0x18,0x37,0x00,0xf8,0x84,0x40,0x00,0xc0,0x04,0x40,0x00,0x00,
+ 0x04,0xaf,0x00,0xf8,0x04,0x40,0xff,0xff,0x00,0x10,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x04,0x40,0xc2,0x24,0x04,0x00,0x01,0x00,
+ 0x84,0x30,0x02,0x00,0x80,0x10,0x00,0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,
+ 0x80,0x04,0x40,0x82,0x22,0x04,0x00,0x18,0x00,0x87,0x30,0x02,0x00,0xe0,0x10,
+ 0x07,0x00,0x87,0x30,0x3f,0x00,0x00,0x70,0x02,0x00,0xe0,0x14,0x00,0x00,0x00,
+ 0x00,0x3f,0x00,0x00,0x70,0x2e,0x00,0x11,0x04,0x00,0x00,0x00,0x00,0x8f,0x00,
+ 0x11,0x04,0x00,0x00,0x00,0x00,0xbc,0x00,0x11,0x04,0x00,0x00,0x00,0x00,0xe2,
+ 0x00,0x11,0x04,0x00,0x00,0x00,0x00,0x1a,0x00,0x20,0x16,0x00,0x00,0x00,0x00,
+ 0x14,0x00,0x00,0x16,0x00,0x00,0x00,0x00,0xd0,0x00,0x11,0x04,0x00,0x00,0x00,
+ 0x00,0xc8,0x01,0x11,0x04,0x00,0x00,0x00,0x00,0x00,0x80,0x05,0x3c,0x00,0x0f,
+ 0xa5,0x24,0x5c,0x00,0xa0,0xac,0x7c,0x00,0xa0,0xac,0x9c,0x00,0xa0,0xac,0xbc,
+ 0x00,0xa0,0xac,0xdc,0x00,0xa0,0xac,0xfc,0x00,0xa0,0xac,0xc0,0xbf,0x05,0x3c,
+ 0x18,0x11,0xa5,0x24,0x44,0xef,0x25,0x7c,0x01,0x00,0x64,0x22,0x00,0x00,0xa4,
+ 0xac,0x76,0x01,0x11,0x04,0x00,0x00,0x00,0x00,0xcd,0x01,0x11,0x04,0x00,0x00,
+ 0x00,0x00,0xce,0x01,0x11,0x04,0x00,0x00,0x00,0x00,0x00,0x7c,0xe4,0x7f,0x00,
+ 0x24,0x04,0x00,0x21,0xf8,0x80,0x00,0x00,0x01,0xff,0x37,0x21,0x28,0x80,0x00,
+ 0x00,0x10,0xa5,0x34,0x00,0xf0,0x85,0x40,0x21,0x20,0xe0,0x02,0x21,0x28,0x00,
+ 0x02,0x21,0x30,0x20,0x02,0x01,0x00,0x87,0x26,0x18,0x00,0x00,0x42,0xad,0xde,
+ 0x01,0x3c,0xef,0xbe,0x21,0x34,0x02,0x60,0x1d,0x40,0x80,0x1e,0xbe,0x7f,0x84,
+ 0x49,0xdd,0x7f,0x02,0x60,0x9d,0x40,0x00,0x08,0xc1,0x41,0x00,0x10,0xc1,0x41,
+ 0x00,0x18,0xc1,0x41,0x00,0x20,0xc1,0x41,0x00,0x28,0xc1,0x41,0x00,0x30,0xc1,
+ 0x41,0x00,0x38,0xc1,0x41,0x00,0x40,0xc1,0x41,0x00,0x48,0xc1,0x41,0x00,0x50,
+ 0xc1,0x41,0x00,0x58,0xc1,0x41,0x00,0x60,0xc1,0x41,0x00,0x68,0xc1,0x41,0x00,
+ 0x70,0xc1,0x41,0x00,0x78,0xc1,0x41,0x00,0x80,0xc1,0x41,0x00,0x88,0xc1,0x41,
+ 0x00,0x90,0xc1,0x41,0x00,0x98,0xc1,0x41,0x00,0xa0,0xc1,0x41,0x00,0xa8,0xc1,
+ 0x41,0x00,0xb0,0xc1,0x41,0x00,0xb8,0xc1,0x41,0x00,0xc0,0xc1,0x41,0x00,0xc8,
+ 0xc1,0x41,0x00,0xd0,0xc1,0x41,0x00,0xd8,0xc1,0x41,0x00,0xe0,0xc1,0x41,0x00,
+ 0xe8,0xc1,0x41,0x05,0x00,0xc0,0x13,0x00,0x00,0x00,0x00,0x00,0xf0,0xc1,0x41,
+ 0x00,0xf8,0xc1,0x41,0xdc,0xff,0x00,0x10,0xff,0xff,0xde,0x23,0xff,0xff,0x01,
+ 0x24,0x01,0x78,0x04,0x40,0x00,0x18,0x97,0x7c,0x00,0xbf,0x18,0x3c,0x10,0x04,
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+ 0x10,0x00,0x00,0x02,0x24,0x01,0x00,0x02,0x24,0x02,0x10,0x04,0x40,0x00,0x18,
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+ 0x03,0xa4,0xac,0x04,0x01,0xa4,0xac,0x84,0x01,0xa4,0xac,0x84,0x03,0xa4,0xac,
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+ 0xa4,0xac,0x40,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x60,0x23,0xa4,0xac,0x60,
+ 0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x80,0x23,0xa4,0xac,0x80,0x24,0xa4,0xac,
+ 0x40,0x20,0x04,0x00,0xa0,0x23,0xa4,0xac,0xa0,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0xc0,0x23,0xa4,0xac,0xc0,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0xe0,0x23,
+ 0xa4,0xac,0xe0,0x24,0xa4,0xac,0xdc,0xbb,0x05,0x3c,0x00,0x80,0xa5,0x34,0x00,
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+ 0xac,0x01,0x01,0x04,0x3c,0x01,0x01,0x84,0x34,0x60,0x00,0xa4,0xac,0x01,0x01,
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+ 0x14,0x04,0x00,0xa5,0x24,0xc0,0xbf,0x05,0x3c,0x18,0x11,0xa5,0x24,0x44,0xef,
+ 0x25,0x7c,0xc0,0xbf,0x07,0x3c,0x1c,0x11,0xe7,0x24,0x44,0xef,0x27,0x7c,0x05,
+ 0x00,0xa7,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0xac,0x04,0x00,0xa5,0x24,
+ 0xfd,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
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+ 0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,0x00,0x10,0x20,0xc4,0xaf,0x03,
+ 0x00,0x04,0x24,0x00,0x40,0xc4,0xaf,0xfa,0xff,0x67,0x16,0x01,0x00,0xe7,0x20,
+ 0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,
+ 0x00,0x18,0x20,0xc4,0xae,0x00,0x40,0xc0,0xae,0xfb,0xff,0x67,0x16,0x01,0x00,
+ 0xe7,0x20,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x0a,0x40,0xc0,
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+ 0x00,0xc8,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,
+ 0x44,0xef,0x1f,0x7c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x80,0x12,0x4b,
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+ 0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x02,0xe0,0x80,0x40,0x02,0xe8,0x80,
+ 0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xc9,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,
+ 0xe0,0x15,0x20,0x70,0xcb,0x01,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x13,
+ 0x00,0x60,0x10,0x00,0x00,0x00,0x00,0xbf,0xbf,0x05,0x3c,0x00,0x80,0xa5,0x34,
+ 0x02,0x00,0x04,0x24,0x04,0x20,0x64,0x02,0xff,0xff,0x84,0x24,0x20,0x00,0xa4,
+ 0xac,0x00,0x00,0xc4,0x8e,0x00,0x1a,0x84,0x7c,0x09,0x00,0x80,0x10,0xff,0xff,
+ 0x04,0x3c,0x90,0x00,0xa4,0xac,0x98,0x00,0xa4,0xac,0xa0,0x00,0xa4,0xac,0xa8,
+ 0x00,0xa4,0xac,0xb0,0x00,0xa4,0xac,0xb8,0x00,0xa4,0xac,0xc0,0x00,0xa4,0xac,
+ 0xc8,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x0f,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x01,0x00,0x09,0x24,0x04,0x48,0x69,0x02,0x40,0x48,0x09,0x00,0xff,
+ 0xff,0x29,0x25,0x08,0x20,0xc9,0xae,0xc0,0x00,0x00,0x00,0x21,0x38,0x00,0x00,
+ 0x00,0x24,0x07,0x00,0x18,0x20,0xc4,0xae,0x08,0x40,0xc4,0x8e,0xfe,0xff,0x80,
+ 0x10,0x00,0x00,0x00,0x00,0xfa,0xff,0xf3,0x14,0x01,0x00,0xe7,0x24,0x08,0x00,
+ 0xe0,0x03,0x00,0x00,0x00,0x00,0x12,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x08,
+ 0x00,0xc4,0x8e,0x50,0x00,0x07,0x24,0x04,0x38,0xe4,0x7c,0x08,0x00,0xc4,0xae,
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+ 0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x2d,0x00,0x60,0x10,0x00,0x00,
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+ 0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,0x04,
+ 0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xcb,0xbd,
+ 0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x00,0x1d,0x4b,
+ 0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
+ 0x6e,0x01,0x00,0x1e,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0x00,
+ 0x1c,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,
+ 0x04,0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xca,
+ 0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x04,0x00,
+ 0x60,0x10,0x00,0x00,0x00,0x00,0x08,0x00,0xc4,0x8e,0x04,0x38,0x04,0x7c,0x08,
+ 0x00,0xc4,0xae,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x6b,0x00,0xa0,0x12,
+ 0x00,0x00,0x00,0x00,0x69,0x00,0x80,0x12,0x00,0x00,0x00,0x00,0x01,0x00,0x08,
+ 0x40,0x02,0x00,0x08,0x35,0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x02,0x00,
+ 0x08,0x40,0x00,0x38,0x0a,0x7d,0x80,0x1a,0x0b,0x7d,0x21,0x60,0x00,0x00,0x01,
+ 0x08,0x08,0x40,0x04,0x38,0x88,0x7d,0x01,0x08,0x88,0x40,0xc0,0x00,0x00,0x00,
+ 0x2f,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x24,0x04,0x10,0x88,
+ 0x41,0xc0,0x00,0x00,0x00,0x2a,0x48,0x6c,0x01,0x05,0x00,0x20,0x15,0x21,0x48,
+ 0x60,0x01,0x02,0x40,0x01,0x41,0x44,0xe5,0x88,0x7d,0x02,0x08,0x88,0x41,0x21,
+ 0x48,0x80,0x01,0x02,0x40,0x02,0x41,0x04,0x18,0x28,0x7d,0x02,0x10,0x88,0x41,
+ 0x00,0x04,0x08,0x24,0x01,0x10,0x88,0x41,0x20,0x08,0x80,0x41,0x20,0x10,0x80,
+ 0x41,0x20,0x18,0x80,0x41,0x20,0x20,0x80,0x41,0x20,0x28,0x80,0x41,0x20,0x30,
+ 0x80,0x41,0x20,0x38,0x80,0x41,0x20,0x40,0x80,0x41,0x20,0x48,0x80,0x41,0x20,
+ 0x50,0x80,0x41,0x20,0x58,0x80,0x41,0x20,0x60,0x80,0x41,0x20,0x68,0x80,0x41,
+ 0x20,0x70,0x80,0x41,0x20,0x78,0x80,0x41,0x20,0x80,0x80,0x41,0x20,0x88,0x80,
+ 0x41,0x20,0x90,0x80,0x41,0x20,0x98,0x80,0x41,0x20,0xa0,0x80,0x41,0x20,0xa8,
+ 0x80,0x41,0x20,0xb0,0x80,0x41,0x20,0xb8,0x80,0x41,0x20,0xc0,0x80,0x41,0x20,
+ 0xc8,0x80,0x41,0x20,0xd0,0x80,0x41,0x20,0xd8,0x80,0x41,0x20,0xe0,0x80,0x41,
+ 0x20,0xe8,0x80,0x41,0x20,0xf0,0x80,0x41,0x20,0xf8,0x80,0x41,0x2a,0x48,0x6c,
+ 0x01,0x21,0x00,0x20,0x15,0x00,0x00,0x00,0x00,0x01,0x40,0x01,0x41,0xc4,0x7b,
+ 0x08,0x7c,0x01,0x08,0x88,0x41,0x1c,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x02,
+ 0x40,0x01,0x41,0x04,0x00,0x08,0x7c,0x02,0x00,0x08,0x35,0x02,0x08,0x88,0x41,
+ 0x00,0x60,0x08,0x40,0x00,0x60,0x88,0x41,0x34,0x12,0x08,0x3c,0x78,0x56,0x08,
+ 0x35,0x00,0x70,0x88,0x41,0x00,0x68,0x80,0x41,0x00,0x80,0x08,0x40,0x00,0x80,
+ 0x88,0x41,0x01,0x40,0x0f,0x41,0x00,0x48,0x08,0x7d,0x20,0xb8,0x88,0x41,0xc0,
+ 0xbf,0x05,0x3c,0x00,0x00,0xa5,0x24,0x44,0xef,0x05,0x7c,0x03,0x10,0x85,0x41,
+ 0x01,0x40,0x02,0x41,0x84,0x52,0x08,0x7c,0x00,0x20,0x08,0x35,0x01,0x10,0x88,
+ 0x41,0x04,0x10,0x80,0x41,0x02,0x40,0x01,0x41,0x01,0x00,0x08,0x35,0x02,0x08,
+ 0x88,0x41,0x01,0x00,0x8c,0x25,0x2b,0x48,0x4c,0x01,0xa6,0xff,0x20,0x11,0x00,
+ 0x00,0x00,0x00,0x01,0x00,0x08,0x40,0x01,0x00,0x08,0x35,0x44,0x08,0x08,0x7c,
+ 0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0xf8,0xff,0xbd,0x27,0x1f,0x00,0x80,0x14,0x04,0x00,0xbf,0xaf,0x00,0x80,
+ 0x02,0x3c,0x00,0x0f,0x42,0x24,0x1c,0x00,0x43,0x8c,0x01,0x00,0x05,0x24,0x07,
+ 0x00,0x63,0x34,0x1c,0x00,0x43,0xac,0x10,0x80,0x83,0x8f,0x02,0x00,0x63,0x28,
+ 0x11,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x40,0x21,0x05,0x00,0x21,0x20,0x82,
+ 0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0xfc,
+ 0xff,0x60,0x10,0x00,0x00,0x00,0x00,0x10,0x80,0x83,0x8f,0x01,0x00,0xa5,0x24,
+ 0x2a,0x18,0xa3,0x00,0xf1,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x04,0x00,0xbf,
+ 0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x08,0x00,0xbd,0x27,0x00,0x80,
+ 0x02,0x3c,0x40,0x21,0x04,0x00,0x00,0x0f,0x42,0x24,0x21,0x20,0x44,0x00,0x00,
+ 0x00,0x80,0xac,0x04,0x00,0x80,0xac,0x08,0x00,0x80,0xac,0x0c,0x00,0x80,0xac,
+ 0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,0x1c,0x00,0x83,
+ 0x8c,0x02,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x1c,0x00,0x83,0x8c,0x02,0x00,0x63,0x30,0xfc,0xff,0x60,0x10,0x00,
+ 0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x04,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,
+ 0x00,0x00,0x83,0x8c,0x04,0x00,0x88,0x8c,0x08,0x00,0x89,0x8c,0x0c,0x00,0x8a,
+ 0x8c,0x21,0xf8,0x60,0x00,0x21,0xe0,0x00,0x01,0x21,0xe8,0x20,0x01,0x21,0x20,
+ 0x40,0x01,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,
+ 0x38,0x00,0x00,0x05,0x04,0xf0,0x0b,0x00,0x00,0x00,0x00,
+};
+
+#endif /* TARGET_WORDS_BIGENDIAN */
+
+#endif /* __MIPS_CPS_BOOTCODE_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 01/12] MIPS: Bootcode for MIPS SMP configurations with a GCMP
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/mips_cps_bootcode.h | 310 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 310 insertions(+)
create mode 100644 hw/mips_cps_bootcode.h
diff --git a/hw/mips_cps_bootcode.h b/hw/mips_cps_bootcode.h
new file mode 100644
index 0000000..40289a4
--- /dev/null
+++ b/hw/mips_cps_bootcode.h
@@ -0,0 +1,310 @@
+/* Sample boot code for 1004K CPS (Coherent Processing System.)
+ * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
+ *
+ * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
+ */
+
+#ifndef __MIPS_CPS_BOOTCODE_H__
+#define __MIPS_CPS_BOOTCODE_H__
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#error CPS bootcode for MIPS Big Endian target not available yet
+#else
+static unsigned char __boot_cps_data[] = {
+ 0x3f,0x01,0x00,0x10,0x00,0x48,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x3f,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xdc,0xbb,0x1a,0x3c,
+ 0x80,0x02,0x5a,0x37,0x01,0x78,0x1b,0x40,0x00,0x48,0x7b,0x7f,0x20,0x00,0x7b,
+ 0x27,0x00,0x00,0x5b,0xaf,0x18,0x00,0x00,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+ 0xa4,0xac,0x80,0x01,0xa4,0xac,0x80,0x03,0xa4,0xac,0xff,0x00,0x04,0x24,0x04,
+ 0x03,0xa4,0xac,0x04,0x01,0xa4,0xac,0x84,0x01,0xa4,0xac,0x84,0x03,0xa4,0xac,
+ 0x01,0x00,0x04,0x24,0x00,0x23,0xa4,0xac,0x00,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0x20,0x23,0xa4,0xac,0x20,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x40,0x23,
+ 0xa4,0xac,0x40,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x60,0x23,0xa4,0xac,0x60,
+ 0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0x80,0x23,0xa4,0xac,0x80,0x24,0xa4,0xac,
+ 0x40,0x20,0x04,0x00,0xa0,0x23,0xa4,0xac,0xa0,0x24,0xa4,0xac,0x40,0x20,0x04,
+ 0x00,0xc0,0x23,0xa4,0xac,0xc0,0x24,0xa4,0xac,0x40,0x20,0x04,0x00,0xe0,0x23,
+ 0xa4,0xac,0xe0,0x24,0xa4,0xac,0xdc,0xbb,0x05,0x3c,0x00,0x80,0xa5,0x34,0x00,
+ 0x00,0xa7,0x8c,0x40,0x00,0xe4,0x7c,0x04,0x00,0x80,0x10,0x00,0x00,0x00,0x00,
+ 0x00,0x80,0x04,0x3c,0x05,0x00,0x84,0x34,0x48,0x00,0xa4,0xac,0x80,0x00,0xe4,
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+ 0x84,0x34,0x50,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0xc0,
+ 0xbb,0x05,0x3c,0x0c,0x00,0xa4,0x8c,0x04,0x84,0x04,0x7c,0x0c,0x00,0xa4,0xac,
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+ 0xac,0x00,0x01,0x04,0x3c,0x01,0x01,0x84,0x34,0x10,0x00,0xa4,0xac,0x02,0x02,
+ 0x04,0x3c,0x00,0x02,0x84,0x34,0x14,0x00,0xa4,0xac,0x02,0x03,0x04,0x24,0x18,
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+ 0x00,0xa4,0xac,0x06,0x00,0x04,0x3c,0x06,0x27,0x84,0x34,0x50,0x00,0xa4,0xac,
+ 0x06,0x00,0x04,0x24,0x54,0x00,0xa4,0xac,0x14,0x00,0x04,0x24,0x58,0x00,0xa4,
+ 0xac,0x01,0x01,0x04,0x3c,0x01,0x01,0x84,0x34,0x60,0x00,0xa4,0xac,0x01,0x01,
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+ 0x00,0xa4,0xac,0x0f,0x0f,0x04,0x3c,0x02,0x00,0x84,0x34,0x6c,0x00,0xa4,0xac,
+ 0x0c,0x00,0xa4,0x8c,0x04,0x84,0x24,0x7c,0x0c,0x00,0xa4,0xac,0x08,0x00,0xe0,
+ 0x03,0x00,0x00,0x00,0x00,0xc0,0xbf,0x05,0x3c,0x00,0x10,0xa5,0x24,0xc0,0xbf,
+ 0x06,0x3c,0x00,0x10,0xc6,0x24,0x44,0xef,0x26,0x7c,0xc0,0xbf,0x07,0x3c,0x18,
+ 0x11,0xe7,0x24,0x44,0xef,0x27,0x7c,0x06,0x00,0xc7,0x10,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0xa4,0x8c,0x00,0x00,0xc4,0xac,0x04,0x00,0xc6,0x24,0xfc,0xff,0xe6,
+ 0x14,0x04,0x00,0xa5,0x24,0xc0,0xbf,0x05,0x3c,0x18,0x11,0xa5,0x24,0x44,0xef,
+ 0x25,0x7c,0xc0,0xbf,0x07,0x3c,0x1c,0x11,0xe7,0x24,0x44,0xef,0x27,0x7c,0x05,
+ 0x00,0xa7,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0xac,0x04,0x00,0xa5,0x24,
+ 0xfd,0xff,0xa7,0x14,0x00,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0x12,0x00,0x60,0x1a,0x01,0x00,0x07,0x24,0x0a,0x00,0xc0,0x13,0x00,0x00,
+ 0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,0x00,0x10,0x20,0xc4,0xaf,0x03,
+ 0x00,0x04,0x24,0x00,0x40,0xc4,0xaf,0xfa,0xff,0x67,0x16,0x01,0x00,0xe7,0x20,
+ 0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x21,0x20,0xe0,0x00,0x00,0x24,0x04,
+ 0x00,0x18,0x20,0xc4,0xae,0x00,0x40,0xc0,0xae,0xfb,0xff,0x67,0x16,0x01,0x00,
+ 0xe7,0x20,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x01,0x80,0x0a,0x40,0xc0,
+ 0x14,0x4b,0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,
+ 0x04,0x58,0x6e,0x01,0x80,0x15,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,
+ 0x01,0x00,0x14,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,
+ 0x0e,0x3c,0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,
+ 0x00,0xc8,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,
+ 0x44,0xef,0x1f,0x7c,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x80,0x12,0x4b,
+ 0x7d,0x13,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
+ 0x6e,0x01,0x40,0x13,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0xc0,
+ 0x11,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,
+ 0x00,0xe0,0x80,0x40,0x00,0xe8,0x80,0x40,0x02,0xe0,0x80,0x40,0x02,0xe8,0x80,
+ 0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xc9,0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,
+ 0xe0,0x15,0x20,0x70,0xcb,0x01,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x13,
+ 0x00,0x60,0x10,0x00,0x00,0x00,0x00,0xbf,0xbf,0x05,0x3c,0x00,0x80,0xa5,0x34,
+ 0x02,0x00,0x04,0x24,0x04,0x20,0x64,0x02,0xff,0xff,0x84,0x24,0x20,0x00,0xa4,
+ 0xac,0x00,0x00,0xc4,0x8e,0x00,0x1a,0x84,0x7c,0x09,0x00,0x80,0x10,0xff,0xff,
+ 0x04,0x3c,0x90,0x00,0xa4,0xac,0x98,0x00,0xa4,0xac,0xa0,0x00,0xa4,0xac,0xa8,
+ 0x00,0xa4,0xac,0xb0,0x00,0xa4,0xac,0xb8,0x00,0xa4,0xac,0xc0,0x00,0xa4,0xac,
+ 0xc8,0x00,0xa4,0xac,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x0f,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x01,0x00,0x09,0x24,0x04,0x48,0x69,0x02,0x40,0x48,0x09,0x00,0xff,
+ 0xff,0x29,0x25,0x08,0x20,0xc9,0xae,0xc0,0x00,0x00,0x00,0x21,0x38,0x00,0x00,
+ 0x00,0x24,0x07,0x00,0x18,0x20,0xc4,0xae,0x08,0x40,0xc4,0x8e,0xfe,0xff,0x80,
+ 0x10,0x00,0x00,0x00,0x00,0xfa,0xff,0xf3,0x14,0x01,0x00,0xe7,0x24,0x08,0x00,
+ 0xe0,0x03,0x00,0x00,0x00,0x00,0x12,0x00,0x60,0x10,0x00,0x00,0x00,0x00,0x08,
+ 0x00,0xc4,0x8e,0x50,0x00,0x07,0x24,0x04,0x38,0xe4,0x7c,0x08,0x00,0xc4,0xae,
+ 0x08,0x00,0xc4,0x8e,0x00,0x01,0x84,0x7c,0x36,0x00,0x80,0x14,0x00,0x00,0x00,
+ 0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x2d,0x00,0x60,0x10,0x00,0x00,
+ 0x00,0x00,0x08,0x00,0xc4,0x8e,0x2a,0x00,0x00,0x16,0x00,0x01,0x84,0x7c,0x28,
+ 0x00,0x80,0x10,0x00,0x00,0x00,0x00,0x02,0x80,0x0a,0x40,0x00,0x19,0x4b,0x7d,
+ 0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,0x6e,
+ 0x01,0x00,0x1a,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0x00,0x18,
+ 0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,0x04,
+ 0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xcb,0xbd,
+ 0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x00,0x1d,0x4b,
+ 0x7d,0x11,0x00,0x60,0x11,0x00,0x00,0x00,0x00,0x02,0x00,0x0e,0x24,0x04,0x58,
+ 0x6e,0x01,0x00,0x1e,0x4c,0x7d,0x40,0x00,0x0e,0x24,0x04,0x60,0x8e,0x01,0x00,
+ 0x1c,0x4d,0x7d,0x01,0x00,0xad,0x21,0x02,0x60,0x8d,0x71,0x00,0x80,0x0e,0x3c,
+ 0x04,0xe0,0x80,0x40,0x04,0xe8,0x80,0x40,0x21,0x78,0x80,0x01,0x00,0x00,0xca,
+ 0xbd,0xff,0xff,0xef,0x21,0xfd,0xff,0xe0,0x15,0x20,0x70,0xcb,0x01,0x04,0x00,
+ 0x60,0x10,0x00,0x00,0x00,0x00,0x08,0x00,0xc4,0x8e,0x04,0x38,0x04,0x7c,0x08,
+ 0x00,0xc4,0xae,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,0x00,0x6b,0x00,0xa0,0x12,
+ 0x00,0x00,0x00,0x00,0x69,0x00,0x80,0x12,0x00,0x00,0x00,0x00,0x01,0x00,0x08,
+ 0x40,0x02,0x00,0x08,0x35,0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x02,0x00,
+ 0x08,0x40,0x00,0x38,0x0a,0x7d,0x80,0x1a,0x0b,0x7d,0x21,0x60,0x00,0x00,0x01,
+ 0x08,0x08,0x40,0x04,0x38,0x88,0x7d,0x01,0x08,0x88,0x40,0xc0,0x00,0x00,0x00,
+ 0x2f,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x24,0x04,0x10,0x88,
+ 0x41,0xc0,0x00,0x00,0x00,0x2a,0x48,0x6c,0x01,0x05,0x00,0x20,0x15,0x21,0x48,
+ 0x60,0x01,0x02,0x40,0x01,0x41,0x44,0xe5,0x88,0x7d,0x02,0x08,0x88,0x41,0x21,
+ 0x48,0x80,0x01,0x02,0x40,0x02,0x41,0x04,0x18,0x28,0x7d,0x02,0x10,0x88,0x41,
+ 0x00,0x04,0x08,0x24,0x01,0x10,0x88,0x41,0x20,0x08,0x80,0x41,0x20,0x10,0x80,
+ 0x41,0x20,0x18,0x80,0x41,0x20,0x20,0x80,0x41,0x20,0x28,0x80,0x41,0x20,0x30,
+ 0x80,0x41,0x20,0x38,0x80,0x41,0x20,0x40,0x80,0x41,0x20,0x48,0x80,0x41,0x20,
+ 0x50,0x80,0x41,0x20,0x58,0x80,0x41,0x20,0x60,0x80,0x41,0x20,0x68,0x80,0x41,
+ 0x20,0x70,0x80,0x41,0x20,0x78,0x80,0x41,0x20,0x80,0x80,0x41,0x20,0x88,0x80,
+ 0x41,0x20,0x90,0x80,0x41,0x20,0x98,0x80,0x41,0x20,0xa0,0x80,0x41,0x20,0xa8,
+ 0x80,0x41,0x20,0xb0,0x80,0x41,0x20,0xb8,0x80,0x41,0x20,0xc0,0x80,0x41,0x20,
+ 0xc8,0x80,0x41,0x20,0xd0,0x80,0x41,0x20,0xd8,0x80,0x41,0x20,0xe0,0x80,0x41,
+ 0x20,0xe8,0x80,0x41,0x20,0xf0,0x80,0x41,0x20,0xf8,0x80,0x41,0x2a,0x48,0x6c,
+ 0x01,0x21,0x00,0x20,0x15,0x00,0x00,0x00,0x00,0x01,0x40,0x01,0x41,0xc4,0x7b,
+ 0x08,0x7c,0x01,0x08,0x88,0x41,0x1c,0x00,0x80,0x11,0x00,0x00,0x00,0x00,0x02,
+ 0x40,0x01,0x41,0x04,0x00,0x08,0x7c,0x02,0x00,0x08,0x35,0x02,0x08,0x88,0x41,
+ 0x00,0x60,0x08,0x40,0x00,0x60,0x88,0x41,0x34,0x12,0x08,0x3c,0x78,0x56,0x08,
+ 0x35,0x00,0x70,0x88,0x41,0x00,0x68,0x80,0x41,0x00,0x80,0x08,0x40,0x00,0x80,
+ 0x88,0x41,0x01,0x40,0x0f,0x41,0x00,0x48,0x08,0x7d,0x20,0xb8,0x88,0x41,0xc0,
+ 0xbf,0x05,0x3c,0x00,0x00,0xa5,0x24,0x44,0xef,0x05,0x7c,0x03,0x10,0x85,0x41,
+ 0x01,0x40,0x02,0x41,0x84,0x52,0x08,0x7c,0x00,0x20,0x08,0x35,0x01,0x10,0x88,
+ 0x41,0x04,0x10,0x80,0x41,0x02,0x40,0x01,0x41,0x01,0x00,0x08,0x35,0x02,0x08,
+ 0x88,0x41,0x01,0x00,0x8c,0x25,0x2b,0x48,0x4c,0x01,0xa6,0xff,0x20,0x11,0x00,
+ 0x00,0x00,0x00,0x01,0x00,0x08,0x40,0x01,0x00,0x08,0x35,0x44,0x08,0x08,0x7c,
+ 0x01,0x00,0x88,0x40,0xc0,0x00,0x00,0x00,0x08,0x00,0xe0,0x03,0x00,0x00,0x00,
+ 0x00,0xf8,0xff,0xbd,0x27,0x1f,0x00,0x80,0x14,0x04,0x00,0xbf,0xaf,0x00,0x80,
+ 0x02,0x3c,0x00,0x0f,0x42,0x24,0x1c,0x00,0x43,0x8c,0x01,0x00,0x05,0x24,0x07,
+ 0x00,0x63,0x34,0x1c,0x00,0x43,0xac,0x10,0x80,0x83,0x8f,0x02,0x00,0x63,0x28,
+ 0x11,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x40,0x21,0x05,0x00,0x21,0x20,0x82,
+ 0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x30,0xfc,
+ 0xff,0x60,0x10,0x00,0x00,0x00,0x00,0x10,0x80,0x83,0x8f,0x01,0x00,0xa5,0x24,
+ 0x2a,0x18,0xa3,0x00,0xf1,0xff,0x60,0x14,0x00,0x00,0x00,0x00,0x04,0x00,0xbf,
+ 0x8f,0x21,0x10,0x00,0x00,0x08,0x00,0xe0,0x03,0x08,0x00,0xbd,0x27,0x00,0x80,
+ 0x02,0x3c,0x40,0x21,0x04,0x00,0x00,0x0f,0x42,0x24,0x21,0x20,0x44,0x00,0x00,
+ 0x00,0x80,0xac,0x04,0x00,0x80,0xac,0x08,0x00,0x80,0xac,0x0c,0x00,0x80,0xac,
+ 0x1c,0x00,0x83,0x8c,0x01,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,0x1c,0x00,0x83,
+ 0x8c,0x02,0x00,0x63,0x30,0x06,0x00,0x60,0x14,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x1c,0x00,0x83,0x8c,0x02,0x00,0x63,0x30,0xfc,0xff,0x60,0x10,0x00,
+ 0x00,0x00,0x00,0x1c,0x00,0x83,0x8c,0x04,0x00,0x63,0x34,0x1c,0x00,0x83,0xac,
+ 0x00,0x00,0x83,0x8c,0x04,0x00,0x88,0x8c,0x08,0x00,0x89,0x8c,0x0c,0x00,0x8a,
+ 0x8c,0x21,0xf8,0x60,0x00,0x21,0xe0,0x00,0x01,0x21,0xe8,0x20,0x01,0x21,0x20,
+ 0x40,0x01,0x21,0x28,0x00,0x00,0x21,0x30,0x00,0x00,0x08,0x00,0xe0,0x03,0x21,
+ 0x38,0x00,0x00,0x05,0x04,0xf0,0x0b,0x00,0x00,0x00,0x00,
+};
+
+#endif /* TARGET_WORDS_BIGENDIAN */
+
+#endif /* __MIPS_CPS_BOOTCODE_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 02/12] KVM/MIPS: GIC emulation for SMP guests.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/mips_gcmpregs.h | 122 ++++++++++++++++
hw/mips_gic.c | 418 +++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/mips_gic.h | 378 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 918 insertions(+)
create mode 100644 hw/mips_gcmpregs.h
create mode 100644 hw/mips_gic.c
create mode 100644 hw/mips_gic.h
diff --git a/hw/mips_gcmpregs.h b/hw/mips_gcmpregs.h
new file mode 100644
index 0000000..933a5c2
--- /dev/null
+++ b/hw/mips_gcmpregs.h
@@ -0,0 +1,122 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * Multiprocessor Subsystem Register Definitions
+ *
+ */
+#ifndef _ASM_GCMPREGS_H
+#define _ASM_GCMPREGS_H
+
+
+/* Offsets to major blocks within GCMP from GCMP base */
+#define GCMP_GCB_OFS 0x0000 /* Global Control Block */
+#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */
+#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */
+#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
+
+/* Offsets to individual GCMP registers from GCMP base */
+#define GCMPOFS(block, tag, reg) \
+ (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFSn(block, tag, reg, n) \
+ (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
+
+#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
+#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
+#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
+#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
+#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
+
+/* GCMP register access */
+#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
+#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
+#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
+#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
+
+/* Mask generation */
+#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF)
+#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits)
+#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits)
+#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits)
+
+/* GCB registers */
+#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */
+#define GCMP_GCB_GC_NUMIOCU_SHF 8
+#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4)
+#define GCMP_GCB_GC_NUMCORES_SHF 0
+#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8)
+#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */
+#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15
+#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
+#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
+#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
+#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
+#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
+#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
+#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
+#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
+#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
+#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8)
+#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */
+#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */
+#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */
+#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27
+#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
+#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0
+#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27)
+#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */
+#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */
+#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0
+#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5)
+#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */
+#define GCMP_GCB_GICBA_BASE_SHF 17
+#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15)
+#define GCMP_GCB_GICBA_EN_SHF 0
+#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1)
+
+/* GCB Regions */
+#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */
+#define GCMP_GCB_CMxBASE_BASE_SHF 16
+#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16)
+#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */
+#define GCMP_GCB_CMxMASK_MASK_SHF 16
+#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16)
+#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0
+#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
+#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0
+#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1
+#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
+#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
+
+
+/* Core local/Core other control block registers */
+#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */
+#define GCMP_CCB_RESETR_INRESET_SHF 0
+#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16)
+#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */
+#define GCMP_CCB_COHCTL_DOMAIN_SHF 0
+#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8)
+#define GCMP_CCB_CFG_OFS 0x0010 /* Config */
+#define GCMP_CCB_CFG_IOCUTYPE_SHF 10
+#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2)
+#define GCMP_CCB_CFG_IOCUTYPE_CPU 0
+#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1
+#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2
+#define GCMP_CCB_CFG_NUMVPE_SHF 0
+#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10)
+#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */
+#define GCMP_CCB_OTHER_CORENUM_SHF 16
+#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16)
+#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */
+#define GCMP_CCB_RESETBASE_BEV_SHF 12
+#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20)
+#define GCMP_CCB_ID_OFS 0x0028 /* Identification */
+#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */
+#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
+
+#endif /* _ASM_GCMPREGS_H */
diff --git a/hw/mips_gic.c b/hw/mips_gic.c
new file mode 100644
index 0000000..b477b7a
--- /dev/null
+++ b/hw/mips_gic.c
@@ -0,0 +1,418 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#include "hw.h"
+#include "qemu/bitmap.h"
+#include "exec/memory.h"
+#include "sysemu/sysemu.h"
+
+#ifdef CONFIG_KVM
+#include "sysemu/kvm.h"
+#include "kvm_mips.h"
+#endif
+
+#include "mips_gic.h"
+#include "mips_gcmpregs.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+/* Support upto 4 VPEs */
+#define NUMVPES 4
+
+/* XXXKYMA: Spoof a bit of the GCR as well, just enough to get Linux to detect it */
+typedef struct gic_t
+{
+ CPUMIPSState *env[NR_CPUS];
+ MemoryRegion gcr_mem, gic_mem;
+
+ qemu_irq *irqs;
+
+ /* GCR Registers */
+ uint32_t gcr_gic_base_reg;
+
+ /* Shared Section Registers */
+ uint32_t gic_gl_intr_pol_reg[8];
+ uint32_t gic_gl_intr_trigtype_reg[8];
+ uint32_t gic_gl_intr_pending_reg[8];
+ uint32_t gic_gl_intr_mask_reg[8];
+
+ uint32_t gic_gl_map_pin[256];
+
+ /* Sparse array, need a better way */
+ uint32_t gic_gl_map_vpe[0x7fa];
+
+ /* VPE Local Section Registers */
+ /* VPE Other Section Registers, aliased to local, use the other field to access the correct instance */
+ uint32_t gic_local_vpe_regs[NUMVPES][0x1000];
+
+ /* User Mode Visible Section Registers */
+} gic_t;
+
+
+static uint64_t
+gic_read(void *opaque, hwaddr addr, unsigned size)
+{
+ int reg;
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", size: %#x\n", addr, size);
+
+ switch (addr) {
+ case GIC_SH_CONFIG_OFS:
+ return 0x8040000 | ((NUMVPES - 1) & GIC_SH_CONFIG_NUMVPES_MSK);
+ break;
+
+ case GIC_SH_POL_31_0_OFS:
+ case GIC_SH_POL_63_32_OFS:
+ case GIC_SH_POL_95_64_OFS:
+ case GIC_SH_POL_127_96_OFS:
+ case GIC_SH_POL_159_128_OFS:
+ case GIC_SH_POL_191_160_OFS:
+ case GIC_SH_POL_223_192_OFS:
+ case GIC_SH_POL_255_224_OFS:
+ reg = (addr - GIC_SH_POL_31_0_OFS) / 4;
+ return gic->gic_gl_intr_pol_reg[reg];
+ break;
+
+ case GIC_SH_TRIG_31_0_OFS:
+ case GIC_SH_TRIG_63_32_OFS:
+ case GIC_SH_TRIG_95_64_OFS:
+ case GIC_SH_TRIG_127_96_OFS:
+ case GIC_SH_TRIG_159_128_OFS:
+ case GIC_SH_TRIG_191_160_OFS:
+ case GIC_SH_TRIG_223_192_OFS:
+ case GIC_SH_TRIG_255_224_OFS:
+ reg = (addr - GIC_SH_TRIG_31_0_OFS) / 4;
+ return gic->gic_gl_intr_trigtype_reg[reg];
+ break;
+
+ case GIC_SH_RMASK_31_0_OFS:
+ case GIC_SH_RMASK_63_32_OFS:
+ case GIC_SH_RMASK_95_64_OFS:
+ case GIC_SH_RMASK_127_96_OFS:
+ case GIC_SH_RMASK_159_128_OFS:
+ case GIC_SH_RMASK_191_160_OFS:
+ case GIC_SH_RMASK_223_192_OFS:
+ case GIC_SH_RMASK_255_224_OFS:
+ break;
+
+ case GIC_SH_PEND_31_0_OFS:
+ case GIC_SH_PEND_63_32_OFS:
+ case GIC_SH_PEND_95_64_OFS:
+ case GIC_SH_PEND_127_96_OFS:
+ case GIC_SH_PEND_159_128_OFS:
+ case GIC_SH_PEND_191_160_OFS:
+ case GIC_SH_PEND_223_192_OFS:
+ case GIC_SH_PEND_255_224_OFS:
+ reg = (addr - GIC_SH_PEND_31_0_OFS) / 4;
+ DPRINTF("pending[%d]: %#" PRIx32 "\n", reg, gic->gic_gl_intr_pending_reg[reg]);
+ return gic->gic_gl_intr_pending_reg[reg];
+ break;
+
+ case GIC_SH_MASK_31_0_OFS:
+ case GIC_SH_MASK_63_32_OFS:
+ case GIC_SH_MASK_95_64_OFS:
+ case GIC_SH_MASK_127_96_OFS:
+ case GIC_SH_MASK_159_128_OFS:
+ case GIC_SH_MASK_191_160_OFS:
+ case GIC_SH_MASK_223_192_OFS:
+ case GIC_SH_MASK_255_224_OFS:
+ reg = (addr - GIC_SH_MASK_31_0_OFS) / 4;
+ return gic->gic_gl_intr_mask_reg[reg];
+ break;
+
+ default:
+ break;
+ }
+
+ /* Other cases */
+ if (addr >= GIC_SH_INTR_MAP_TO_PIN_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_PIN(255)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_PIN_BASE_OFS) / 4;
+ return gic->gic_gl_map_pin[reg];
+ }
+
+ if (addr >= GIC_SH_INTR_MAP_TO_VPE_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_VPE_REG_OFF(255, 63)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4;
+ return gic->gic_gl_map_vpe[reg];
+ }
+
+ if (addr >= GIC_VPELOCAL_BASE_ADDR && addr < GIC_VPEOTHER_BASE_ADDR) {
+ }
+
+ if (addr >= GIC_VPEOTHER_BASE_ADDR && addr < GIC_USERMODE_BASE_ADDR) {
+ }
+
+ DPRINTF("%s: unimplemented register @ %#" PRIx64 "\n", __func__, addr);
+ return 0ULL;
+}
+
+static void
+gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
+{
+ int reg, intr;
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr, data,
+ size);
+
+ switch (addr) {
+ case GIC_SH_POL_31_0_OFS:
+ case GIC_SH_POL_63_32_OFS:
+ case GIC_SH_POL_95_64_OFS:
+ case GIC_SH_POL_127_96_OFS:
+ case GIC_SH_POL_159_128_OFS:
+ case GIC_SH_POL_191_160_OFS:
+ case GIC_SH_POL_223_192_OFS:
+ case GIC_SH_POL_255_224_OFS:
+ reg = (addr - GIC_SH_POL_31_0_OFS) / 4;
+ gic->gic_gl_intr_pol_reg[reg] = data;
+ break;
+
+ case GIC_SH_TRIG_31_0_OFS:
+ case GIC_SH_TRIG_63_32_OFS:
+ case GIC_SH_TRIG_95_64_OFS:
+ case GIC_SH_TRIG_127_96_OFS:
+ case GIC_SH_TRIG_159_128_OFS:
+ case GIC_SH_TRIG_191_160_OFS:
+ case GIC_SH_TRIG_223_192_OFS:
+ case GIC_SH_TRIG_255_224_OFS:
+ reg = (addr - GIC_SH_TRIG_31_0_OFS) / 4;
+ gic->gic_gl_intr_trigtype_reg[reg] = data;
+ break;
+
+ case GIC_SH_RMASK_31_0_OFS:
+ case GIC_SH_RMASK_63_32_OFS:
+ case GIC_SH_RMASK_95_64_OFS:
+ case GIC_SH_RMASK_127_96_OFS:
+ case GIC_SH_RMASK_159_128_OFS:
+ case GIC_SH_RMASK_191_160_OFS:
+ case GIC_SH_RMASK_223_192_OFS:
+ case GIC_SH_RMASK_255_224_OFS:
+ reg = (addr - GIC_SH_RMASK_31_0_OFS) / 4;
+ gic->gic_gl_intr_mask_reg[reg] &= ~data;
+ break;
+
+ case GIC_SH_WEDGE_OFS:
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr,
+ data, size);
+
+ /* Figure out which VPE/HW Interrupt this maps to */
+ intr = data & 0x7FFFFFFF;
+
+ /* XXXSL Mask/Enabled Checks */
+ if (data & 0x80000000)
+ qemu_set_irq(gic->irqs[intr], 1);
+ else
+ qemu_set_irq(gic->irqs[intr], 0);
+
+ break;
+
+ case GIC_SH_PEND_31_0_OFS:
+ case GIC_SH_PEND_63_32_OFS:
+ case GIC_SH_PEND_95_64_OFS:
+ case GIC_SH_PEND_127_96_OFS:
+ case GIC_SH_PEND_159_128_OFS:
+ case GIC_SH_PEND_191_160_OFS:
+ case GIC_SH_PEND_223_192_OFS:
+ case GIC_SH_PEND_255_224_OFS:
+ break;
+
+ case GIC_SH_SMASK_31_0_OFS:
+ case GIC_SH_SMASK_63_32_OFS:
+ case GIC_SH_SMASK_95_64_OFS:
+ case GIC_SH_SMASK_127_96_OFS:
+ case GIC_SH_SMASK_159_128_OFS:
+ case GIC_SH_SMASK_191_160_OFS:
+ case GIC_SH_SMASK_223_192_OFS:
+ case GIC_SH_SMASK_255_224_OFS:
+ reg = (addr - GIC_SH_SMASK_31_0_OFS) / 4;
+ gic->gic_gl_intr_mask_reg[reg] |= data;
+ break;
+
+ default:
+ break;
+ }
+
+ /* Other cases */
+ if (addr >= GIC_SH_INTR_MAP_TO_PIN_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_PIN(255)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_PIN_BASE_OFS) / 4;
+ gic->gic_gl_map_pin[reg] = data;
+ }
+ if (addr >= GIC_SH_INTR_MAP_TO_VPE_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_VPE_REG_OFF(255, 63)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4;
+ gic->gic_gl_map_vpe[reg] = data;
+ }
+
+ if (addr >= GIC_VPELOCAL_BASE_ADDR && addr < GIC_VPEOTHER_BASE_ADDR) {
+ }
+
+ if (addr >= GIC_VPEOTHER_BASE_ADDR && addr < GIC_USERMODE_BASE_ADDR) {
+ }
+}
+
+static uint64_t
+gcr_read(void *opaque, hwaddr addr, unsigned size)
+{
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", size: %#x\n", addr, size);
+
+ switch (addr) {
+ case GCMP_GCB_GC_OFS:
+ /* Set PCORES to # cores - 1 */
+ return smp_cpus - 1;
+ break;
+
+ case GCMP_GCB_GCMPB_OFS:
+ return GCMP_BASE_ADDR;
+ break;
+
+ case GCMP_GCB_GICBA_OFS:
+ return gic->gcr_gic_base_reg;
+ break;
+
+ default:
+ DPRINTF("Unsupported Reg Read @ offset %#" PRIx64 "\n", addr);
+ return 0;
+ }
+
+ return 0ULL;
+}
+
+static void
+gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
+{
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr, data,
+ size);
+
+ switch (addr) {
+ case GCMP_GCB_GICBA_OFS:
+ gic->gcr_gic_base_reg = data;
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+
+static void
+gic_set_irq(void *opaque, int n_IRQ, int level)
+{
+ int vpe = -1, pin = -1, i;
+ gic_t *gic = (gic_t *) opaque;
+
+ pin = gic->gic_gl_map_pin[n_IRQ] & 0x7;
+
+ for (i = 0; i < NUMVPES; i++) {
+ vpe = gic-> gic_gl_map_vpe[(GIC_SH_MAP_TO_VPE_REG_OFF(n_IRQ, i) - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4];
+ if (vpe & GIC_SH_MAP_TO_VPE_REG_BIT(i)) {
+ vpe = i;
+ break;
+ }
+ }
+
+ if (pin >= 0 && vpe >= 0) {
+ int offset;
+ DPRINTF("[%s] INTR %d maps to PIN %d on VPE %d\n", (level ? "ASSERT" : "DEASSERT"), n_IRQ, pin, vpe);
+ /* Set the Global PEND register */
+ offset = GIC_INTR_OFS(n_IRQ) / 4;
+ if (level)
+ gic->gic_gl_intr_pending_reg[offset] |= (1 << GIC_INTR_BIT(n_IRQ));
+ else
+ gic->gic_gl_intr_pending_reg[offset] &= ~(1 << GIC_INTR_BIT(n_IRQ));
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled()) {
+ kvm_mips_set_ipi_interrupt (gic->env[vpe], pin+2, level);
+ }
+#endif
+
+ qemu_set_irq(gic->env[vpe]->irq[pin+2], level);
+ }
+}
+
+static void
+gic_reset(void *opaque)
+{
+ int i;
+ gic_t *gic = (gic_t *) opaque;
+
+ /* Rest value is map to pin */
+ for (i = 0; i < 256; i++)
+ gic->gic_gl_map_pin[i] = GIC_MAP_TO_PIN_MSK;
+
+}
+
+static const MemoryRegionOps gic_ops = {
+ .read = gic_read,
+ .write = gic_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps gcr_ops = {
+ .read = gcr_read,
+ .write = gcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+qemu_irq *
+gic_init(uint32_t ncpus, CPUMIPSState *env, MemoryRegion * address_space)
+{
+ CPUMIPSState *next_env;
+ gic_t *gic;
+ uint32_t x;
+
+ if (ncpus > NUMVPES) {
+ fprintf(stderr, "Unable to initialize GIC - ncpus %d > NUMVPES!", ncpus);
+ return NULL;
+ }
+
+ gic = (gic_t *) g_malloc0(sizeof(gic_t));
+
+ /* Register the CPU env for all cpus with the GIC */
+ next_env = env;
+ for (x = 0; x < ncpus; x++) {
+ if (next_env != NULL) {
+ gic->env[x] = next_env;
+ next_env = next_env->next_cpu;
+ } else {
+ fprintf(stderr, "Unable to initialize GIC - CPUMIPSState for CPU #%d not valid!", x);
+ return NULL;
+ }
+ }
+
+ /* Register GCR & GIC regions */
+ memory_region_init_io(&gic->gcr_mem, &gcr_ops, gic, "GCR",
+ GCMP_ADDRSPACE_SZ);
+ memory_region_init_io(&gic->gic_mem, &gic_ops, gic, "GIC",
+ GIC_ADDRSPACE_SZ);
+
+ memory_region_add_subregion(address_space, GCMP_BASE_ADDR, &gic->gcr_mem);
+ memory_region_add_subregion(address_space, GIC_BASE_ADDR, &gic->gic_mem);
+
+ qemu_register_reset(gic_reset, gic);
+
+ gic->irqs = qemu_allocate_irqs(gic_set_irq, gic, GIC_NUM_INTRS);
+
+ return (gic->irqs);
+}
diff --git a/hw/mips_gic.h b/hw/mips_gic.h
new file mode 100644
index 0000000..4a2c828
--- /dev/null
+++ b/hw/mips_gic.h
@@ -0,0 +1,378 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * GIC Register Definitions
+ *
+ */
+#ifndef _ASM_GICREGS_H
+#define _ASM_GICREGS_H
+
+#undef GICISBYTELITTLEENDIAN
+
+#define NR_CPUS 8
+/*
+ * GCMP Specific definitions
+ */
+
+/* XXXKYMA: Malta Specific base address */
+#define GCMP_BASE_ADDR 0x1fbf8000ULL
+#define GCMP_ADDRSPACE_SZ (256 * 1024)
+
+/*
+ * GIC Specific definitions
+ */
+
+/* XXXKYMA: Malta Specific base address */
+#define GIC_BASE_ADDR 0x1bdc0000ULL
+#define GIC_ADDRSPACE_SZ (128 * 1024)
+
+/* GIC Address Space Offsets */
+#define GIC_SHARED_BASE_ADDR 0x0000
+#define GIC_VPELOCAL_BASE_ADDR 0x8000
+#define GIC_VPEOTHER_BASE_ADDR 0xC000
+#define GIC_USERMODE_BASE_ADDR 0x10000
+
+/* Shared Section Offsets */
+#define GIC_G_INTR_POLARITY_REG0 0x0100
+#define GIC_G_INTR_POLARITY_REG1 0x0104
+#define GIC_G_INTR_TRIGTYPE_REG0 0x0180
+#define GIC_G_INTR_TRIGTYPE_REG1 0x0184
+#define GIC_G_INTR_RESETMASK_REG0 0x0300
+#define GIC_G_INTR_RESETMASK_REG1 0x0304
+#define GIC_G_INTR_SETMASK_REG0 0x0380
+
+/*
+ * MSC01 BIU Specific definitions
+ * FIXME : These should be elsewhere ?
+ */
+#define MSC01_BIU_REG_BASE 0x1bc80000
+#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
+#define MSC01_SC_CFG_OFS 0x0110
+#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
+#define MSC01_SC_CFG_GICPRES_SHF 2
+#define MSC01_SC_CFG_GICENA_SHF 3
+
+/* Constants */
+#define GIC_POL_POS 1
+#define GIC_POL_NEG 0
+#define GIC_TRIG_EDGE 1
+#define GIC_TRIG_LEVEL 0
+
+#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
+
+#define MSK(n) ((1 << (n)) - 1)
+#define REG32(addr) (*(volatile unsigned int *) (addr))
+#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
+#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
+
+/* Accessors */
+#define GIC_REG(segment, offset) \
+ REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ADDR(segment, offset) \
+ REG32(_gic_base + segment##_##SECTION_OFS + offset)
+
+#define GIC_ABS_REG(segment, offset) \
+ (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ABS_ADDR(segment, offset) \
+ (_gic_base + segment##_##SECTION_OFS + offset)
+
+#ifdef GICISBYTELITTLEENDIAN
+#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
+#define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
+#define GICBIS(reg, bits) \
+ ({unsigned int data; \
+ GICREAD(reg, data); \
+ data |= bits; \
+ GICWRITE(reg, data); \
+ })
+
+#else
+#define GICREAD(reg, data) (data) = (reg)
+#define GICWRITE(reg, data) (reg) = (data)
+#define GICBIS(reg, bits) (reg) |= (bits)
+#endif
+
+
+/* GIC Address Space */
+#define SHARED_SECTION_OFS 0x0000
+#define SHARED_SECTION_SIZE 0x8000
+#define VPE_LOCAL_SECTION_OFS 0x8000
+#define VPE_LOCAL_SECTION_SIZE 0x4000
+#define VPE_OTHER_SECTION_OFS 0xc000
+#define VPE_OTHER_SECTION_SIZE 0x4000
+#define USM_VISIBLE_SECTION_OFS 0x10000
+#define USM_VISIBLE_SECTION_SIZE 0x10000
+
+/* Register Map for Shared Section */
+
+#define GIC_SH_CONFIG_OFS 0x0000
+
+/* Shared Global Counter */
+#define GIC_SH_COUNTER_31_00_OFS 0x0010
+#define GIC_SH_COUNTER_63_32_OFS 0x0014
+#define GIC_SH_REVISIONID_OFS 0x0020
+
+/* Interrupt Polarity */
+#define GIC_SH_POL_31_0_OFS 0x0100
+#define GIC_SH_POL_63_32_OFS 0x0104
+#define GIC_SH_POL_95_64_OFS 0x0108
+#define GIC_SH_POL_127_96_OFS 0x010c
+#define GIC_SH_POL_159_128_OFS 0x0110
+#define GIC_SH_POL_191_160_OFS 0x0114
+#define GIC_SH_POL_223_192_OFS 0x0118
+#define GIC_SH_POL_255_224_OFS 0x011c
+
+/* Edge/Level Triggering */
+#define GIC_SH_TRIG_31_0_OFS 0x0180
+#define GIC_SH_TRIG_63_32_OFS 0x0184
+#define GIC_SH_TRIG_95_64_OFS 0x0188
+#define GIC_SH_TRIG_127_96_OFS 0x018c
+#define GIC_SH_TRIG_159_128_OFS 0x0190
+#define GIC_SH_TRIG_191_160_OFS 0x0194
+#define GIC_SH_TRIG_223_192_OFS 0x0198
+#define GIC_SH_TRIG_255_224_OFS 0x019c
+
+/* Dual Edge Triggering */
+#define GIC_SH_DUAL_31_0_OFS 0x0200
+#define GIC_SH_DUAL_63_32_OFS 0x0204
+#define GIC_SH_DUAL_95_64_OFS 0x0208
+#define GIC_SH_DUAL_127_96_OFS 0x020c
+#define GIC_SH_DUAL_159_128_OFS 0x0210
+#define GIC_SH_DUAL_191_160_OFS 0x0214
+#define GIC_SH_DUAL_223_192_OFS 0x0218
+#define GIC_SH_DUAL_255_224_OFS 0x021c
+
+/* Set/Clear corresponding bit in Edge Detect Register */
+#define GIC_SH_WEDGE_OFS 0x0280
+
+/* Reset Mask - Disables Interrupt */
+#define GIC_SH_RMASK_31_0_OFS 0x0300
+#define GIC_SH_RMASK_63_32_OFS 0x0304
+#define GIC_SH_RMASK_95_64_OFS 0x0308
+#define GIC_SH_RMASK_127_96_OFS 0x030c
+#define GIC_SH_RMASK_159_128_OFS 0x0310
+#define GIC_SH_RMASK_191_160_OFS 0x0314
+#define GIC_SH_RMASK_223_192_OFS 0x0318
+#define GIC_SH_RMASK_255_224_OFS 0x031c
+
+/* Set Mask (WO) - Enables Interrupt */
+#define GIC_SH_SMASK_31_0_OFS 0x0380
+#define GIC_SH_SMASK_63_32_OFS 0x0384
+#define GIC_SH_SMASK_95_64_OFS 0x0388
+#define GIC_SH_SMASK_127_96_OFS 0x038c
+#define GIC_SH_SMASK_159_128_OFS 0x0390
+#define GIC_SH_SMASK_191_160_OFS 0x0394
+#define GIC_SH_SMASK_223_192_OFS 0x0398
+#define GIC_SH_SMASK_255_224_OFS 0x039c
+
+/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
+#define GIC_SH_MASK_31_0_OFS 0x0400
+#define GIC_SH_MASK_63_32_OFS 0x0404
+#define GIC_SH_MASK_95_64_OFS 0x0408
+#define GIC_SH_MASK_127_96_OFS 0x040c
+#define GIC_SH_MASK_159_128_OFS 0x0410
+#define GIC_SH_MASK_191_160_OFS 0x0414
+#define GIC_SH_MASK_223_192_OFS 0x0418
+#define GIC_SH_MASK_255_224_OFS 0x041c
+
+/* Pending Global Interrupts (RO) */
+#define GIC_SH_PEND_31_0_OFS 0x0480
+#define GIC_SH_PEND_63_32_OFS 0x0484
+#define GIC_SH_PEND_95_64_OFS 0x0488
+#define GIC_SH_PEND_127_96_OFS 0x048c
+#define GIC_SH_PEND_159_128_OFS 0x0490
+#define GIC_SH_PEND_191_160_OFS 0x0494
+#define GIC_SH_PEND_223_192_OFS 0x0498
+#define GIC_SH_PEND_255_224_OFS 0x049c
+
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
+
+/* Maps Interrupt X to a Pin */
+#define GIC_SH_MAP_TO_PIN(intr) \
+ (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
+
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
+
+/* Maps Interrupt X to a VPE */
+#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
+ (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
+#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
+
+/* Convert an interrupt number to a byte offset/bit for multi-word registers */
+#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
+#define GIC_INTR_BIT(intr) ((intr) % 32)
+
+/* Polarity : Reset Value is always 0 */
+#define GIC_SH_SET_POLARITY_OFS 0x0100
+#define GIC_SET_POLARITY(intr, pol) \
+ GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
+ GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
+
+/* Triggering : Reset Value is always 0 */
+#define GIC_SH_SET_TRIGGER_OFS 0x0180
+#define GIC_SET_TRIGGER(intr, trig) \
+ GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
+ GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
+
+/* Mask manipulation */
+#define GIC_SH_SMASK_OFS 0x0380
+#define GIC_SET_INTR_MASK(intr) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
+ GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
+#define GIC_SH_RMASK_OFS 0x0300
+#define GIC_CLR_INTR_MASK(intr) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
+ GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
+
+/* Register Map for Local Section */
+#define GIC_VPE_CTL_OFS 0x0000
+#define GIC_VPE_PEND_OFS 0x0004
+#define GIC_VPE_MASK_OFS 0x0008
+#define GIC_VPE_RMASK_OFS 0x000c
+#define GIC_VPE_SMASK_OFS 0x0010
+#define GIC_VPE_WD_MAP_OFS 0x0040
+#define GIC_VPE_COMPARE_MAP_OFS 0x0044
+#define GIC_VPE_TIMER_MAP_OFS 0x0048
+#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
+#define GIC_VPE_SWINT0_MAP_OFS 0x0054
+#define GIC_VPE_SWINT1_MAP_OFS 0x0058
+#define GIC_VPE_OTHER_ADDR_OFS 0x0080
+#define GIC_VPE_WD_CONFIG0_OFS 0x0090
+#define GIC_VPE_WD_COUNT0_OFS 0x0094
+#define GIC_VPE_WD_INITIAL0_OFS 0x0098
+#define GIC_VPE_COMPARE_LO_OFS 0x00a0
+#define GIC_VPE_COMPARE_HI 0x00a4
+
+#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
+#define GIC_VPE_EIC_SS(intr) \
+ (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+
+#define GIC_VPE_EIC_VEC_BASE 0x0800
+#define GIC_VPE_EIC_VEC(intr) \
+ (GIC_VPE_EIC_VEC_BASE + (4 * intr))
+
+#define GIC_VPE_TENABLE_NMI_OFS 0x1000
+#define GIC_VPE_TENABLE_YQ_OFS 0x1004
+#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
+#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
+
+/* User Mode Visible Section Register Map */
+#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
+#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
+
+/* Masks */
+#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
+#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
+
+#define GIC_SH_CONFIG_COUNTBITS_SHF 24
+#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
+
+#define GIC_SH_CONFIG_NUMINTRS_SHF 16
+#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
+
+#define GIC_SH_CONFIG_NUMVPES_SHF 0
+#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
+
+#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
+#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
+
+#define GIC_MAP_TO_PIN_SHF 31
+#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
+#define GIC_MAP_TO_NMI_SHF 30
+#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
+#define GIC_MAP_TO_YQ_SHF 29
+#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
+#define GIC_MAP_SHF 0
+#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
+
+/* GIC_VPE_CTL Masks */
+#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
+#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
+#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
+#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
+#define GIC_VPE_CTL_EIC_MODE_SHF 0
+#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
+
+/* GIC_VPE_PEND Masks */
+#define GIC_VPE_PEND_WD_SHF 0
+#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
+#define GIC_VPE_PEND_CMP_SHF 1
+#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
+#define GIC_VPE_PEND_TIMER_SHF 2
+#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
+#define GIC_VPE_PEND_PERFCOUNT_SHF 3
+#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
+#define GIC_VPE_PEND_SWINT0_SHF 4
+#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
+#define GIC_VPE_PEND_SWINT1_SHF 5
+#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
+
+/* GIC_VPE_RMASK Masks */
+#define GIC_VPE_RMASK_WD_SHF 0
+#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
+#define GIC_VPE_RMASK_CMP_SHF 1
+#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
+#define GIC_VPE_RMASK_TIMER_SHF 2
+#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
+#define GIC_VPE_RMASK_PERFCNT_SHF 3
+#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
+#define GIC_VPE_RMASK_SWINT0_SHF 4
+#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
+#define GIC_VPE_RMASK_SWINT1_SHF 5
+#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
+
+/* GIC_VPE_SMASK Masks */
+#define GIC_VPE_SMASK_WD_SHF 0
+#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
+#define GIC_VPE_SMASK_CMP_SHF 1
+#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
+#define GIC_VPE_SMASK_TIMER_SHF 2
+#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
+#define GIC_VPE_SMASK_PERFCNT_SHF 3
+#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
+#define GIC_VPE_SMASK_SWINT0_SHF 4
+#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
+#define GIC_VPE_SMASK_SWINT1_SHF 5
+#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
+
+/*
+ * Set the Mapping of Interrupt X to a VPE.
+ */
+#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
+ GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
+
+struct gic_pcpu_mask {
+ DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
+};
+
+struct gic_pending_regs {
+ DECLARE_BITMAP(pending, GIC_NUM_INTRS);
+};
+
+struct gic_intrmask_regs {
+ DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
+};
+
+/*
+ * Interrupt Meta-data specification. The ipiflag helps
+ * in building ipi_map.
+ */
+struct gic_intr_map {
+ unsigned int cpunum; /* Directed to this CPU */
+#define GIC_UNUSED 0xdead /* Dummy data */
+ unsigned int pin; /* Directed to this Pin */
+ unsigned int polarity; /* Polarity : +/- */
+ unsigned int trigtype; /* Trigger : Edge/Levl */
+ unsigned int flags; /* Misc flags */
+#define GIC_FLAG_IPI 0x01
+#define GIC_FLAG_TRANSPARENT 0x02
+};
+
+qemu_irq *gic_init (uint32_t ncpus, CPUMIPSState *env, MemoryRegion *address_space);
+
+#endif /* _ASM_GICREGS_H */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 02/12] KVM/MIPS: GIC emulation for SMP guests.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/mips_gcmpregs.h | 122 ++++++++++++++++
hw/mips_gic.c | 418 +++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/mips_gic.h | 378 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 918 insertions(+)
create mode 100644 hw/mips_gcmpregs.h
create mode 100644 hw/mips_gic.c
create mode 100644 hw/mips_gic.h
diff --git a/hw/mips_gcmpregs.h b/hw/mips_gcmpregs.h
new file mode 100644
index 0000000..933a5c2
--- /dev/null
+++ b/hw/mips_gcmpregs.h
@@ -0,0 +1,122 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * Multiprocessor Subsystem Register Definitions
+ *
+ */
+#ifndef _ASM_GCMPREGS_H
+#define _ASM_GCMPREGS_H
+
+
+/* Offsets to major blocks within GCMP from GCMP base */
+#define GCMP_GCB_OFS 0x0000 /* Global Control Block */
+#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */
+#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */
+#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
+
+/* Offsets to individual GCMP registers from GCMP base */
+#define GCMPOFS(block, tag, reg) \
+ (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFSn(block, tag, reg, n) \
+ (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
+
+#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
+#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
+#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
+#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
+#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
+
+/* GCMP register access */
+#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
+#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
+#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
+#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
+
+/* Mask generation */
+#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF)
+#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits)
+#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits)
+#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits)
+
+/* GCB registers */
+#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */
+#define GCMP_GCB_GC_NUMIOCU_SHF 8
+#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4)
+#define GCMP_GCB_GC_NUMCORES_SHF 0
+#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8)
+#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */
+#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15
+#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
+#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
+#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
+#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
+#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
+#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
+#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
+#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
+#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
+#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8)
+#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */
+#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */
+#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */
+#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27
+#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
+#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0
+#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27)
+#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */
+#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */
+#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0
+#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5)
+#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */
+#define GCMP_GCB_GICBA_BASE_SHF 17
+#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15)
+#define GCMP_GCB_GICBA_EN_SHF 0
+#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1)
+
+/* GCB Regions */
+#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */
+#define GCMP_GCB_CMxBASE_BASE_SHF 16
+#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16)
+#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */
+#define GCMP_GCB_CMxMASK_MASK_SHF 16
+#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16)
+#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0
+#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
+#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0
+#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1
+#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
+#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
+
+
+/* Core local/Core other control block registers */
+#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */
+#define GCMP_CCB_RESETR_INRESET_SHF 0
+#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16)
+#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */
+#define GCMP_CCB_COHCTL_DOMAIN_SHF 0
+#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8)
+#define GCMP_CCB_CFG_OFS 0x0010 /* Config */
+#define GCMP_CCB_CFG_IOCUTYPE_SHF 10
+#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2)
+#define GCMP_CCB_CFG_IOCUTYPE_CPU 0
+#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1
+#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2
+#define GCMP_CCB_CFG_NUMVPE_SHF 0
+#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10)
+#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */
+#define GCMP_CCB_OTHER_CORENUM_SHF 16
+#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16)
+#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */
+#define GCMP_CCB_RESETBASE_BEV_SHF 12
+#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20)
+#define GCMP_CCB_ID_OFS 0x0028 /* Identification */
+#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */
+#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
+
+#endif /* _ASM_GCMPREGS_H */
diff --git a/hw/mips_gic.c b/hw/mips_gic.c
new file mode 100644
index 0000000..b477b7a
--- /dev/null
+++ b/hw/mips_gic.c
@@ -0,0 +1,418 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#include "hw.h"
+#include "qemu/bitmap.h"
+#include "exec/memory.h"
+#include "sysemu/sysemu.h"
+
+#ifdef CONFIG_KVM
+#include "sysemu/kvm.h"
+#include "kvm_mips.h"
+#endif
+
+#include "mips_gic.h"
+#include "mips_gcmpregs.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+/* Support upto 4 VPEs */
+#define NUMVPES 4
+
+/* XXXKYMA: Spoof a bit of the GCR as well, just enough to get Linux to detect it */
+typedef struct gic_t
+{
+ CPUMIPSState *env[NR_CPUS];
+ MemoryRegion gcr_mem, gic_mem;
+
+ qemu_irq *irqs;
+
+ /* GCR Registers */
+ uint32_t gcr_gic_base_reg;
+
+ /* Shared Section Registers */
+ uint32_t gic_gl_intr_pol_reg[8];
+ uint32_t gic_gl_intr_trigtype_reg[8];
+ uint32_t gic_gl_intr_pending_reg[8];
+ uint32_t gic_gl_intr_mask_reg[8];
+
+ uint32_t gic_gl_map_pin[256];
+
+ /* Sparse array, need a better way */
+ uint32_t gic_gl_map_vpe[0x7fa];
+
+ /* VPE Local Section Registers */
+ /* VPE Other Section Registers, aliased to local, use the other field to access the correct instance */
+ uint32_t gic_local_vpe_regs[NUMVPES][0x1000];
+
+ /* User Mode Visible Section Registers */
+} gic_t;
+
+
+static uint64_t
+gic_read(void *opaque, hwaddr addr, unsigned size)
+{
+ int reg;
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", size: %#x\n", addr, size);
+
+ switch (addr) {
+ case GIC_SH_CONFIG_OFS:
+ return 0x8040000 | ((NUMVPES - 1) & GIC_SH_CONFIG_NUMVPES_MSK);
+ break;
+
+ case GIC_SH_POL_31_0_OFS:
+ case GIC_SH_POL_63_32_OFS:
+ case GIC_SH_POL_95_64_OFS:
+ case GIC_SH_POL_127_96_OFS:
+ case GIC_SH_POL_159_128_OFS:
+ case GIC_SH_POL_191_160_OFS:
+ case GIC_SH_POL_223_192_OFS:
+ case GIC_SH_POL_255_224_OFS:
+ reg = (addr - GIC_SH_POL_31_0_OFS) / 4;
+ return gic->gic_gl_intr_pol_reg[reg];
+ break;
+
+ case GIC_SH_TRIG_31_0_OFS:
+ case GIC_SH_TRIG_63_32_OFS:
+ case GIC_SH_TRIG_95_64_OFS:
+ case GIC_SH_TRIG_127_96_OFS:
+ case GIC_SH_TRIG_159_128_OFS:
+ case GIC_SH_TRIG_191_160_OFS:
+ case GIC_SH_TRIG_223_192_OFS:
+ case GIC_SH_TRIG_255_224_OFS:
+ reg = (addr - GIC_SH_TRIG_31_0_OFS) / 4;
+ return gic->gic_gl_intr_trigtype_reg[reg];
+ break;
+
+ case GIC_SH_RMASK_31_0_OFS:
+ case GIC_SH_RMASK_63_32_OFS:
+ case GIC_SH_RMASK_95_64_OFS:
+ case GIC_SH_RMASK_127_96_OFS:
+ case GIC_SH_RMASK_159_128_OFS:
+ case GIC_SH_RMASK_191_160_OFS:
+ case GIC_SH_RMASK_223_192_OFS:
+ case GIC_SH_RMASK_255_224_OFS:
+ break;
+
+ case GIC_SH_PEND_31_0_OFS:
+ case GIC_SH_PEND_63_32_OFS:
+ case GIC_SH_PEND_95_64_OFS:
+ case GIC_SH_PEND_127_96_OFS:
+ case GIC_SH_PEND_159_128_OFS:
+ case GIC_SH_PEND_191_160_OFS:
+ case GIC_SH_PEND_223_192_OFS:
+ case GIC_SH_PEND_255_224_OFS:
+ reg = (addr - GIC_SH_PEND_31_0_OFS) / 4;
+ DPRINTF("pending[%d]: %#" PRIx32 "\n", reg, gic->gic_gl_intr_pending_reg[reg]);
+ return gic->gic_gl_intr_pending_reg[reg];
+ break;
+
+ case GIC_SH_MASK_31_0_OFS:
+ case GIC_SH_MASK_63_32_OFS:
+ case GIC_SH_MASK_95_64_OFS:
+ case GIC_SH_MASK_127_96_OFS:
+ case GIC_SH_MASK_159_128_OFS:
+ case GIC_SH_MASK_191_160_OFS:
+ case GIC_SH_MASK_223_192_OFS:
+ case GIC_SH_MASK_255_224_OFS:
+ reg = (addr - GIC_SH_MASK_31_0_OFS) / 4;
+ return gic->gic_gl_intr_mask_reg[reg];
+ break;
+
+ default:
+ break;
+ }
+
+ /* Other cases */
+ if (addr >= GIC_SH_INTR_MAP_TO_PIN_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_PIN(255)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_PIN_BASE_OFS) / 4;
+ return gic->gic_gl_map_pin[reg];
+ }
+
+ if (addr >= GIC_SH_INTR_MAP_TO_VPE_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_VPE_REG_OFF(255, 63)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4;
+ return gic->gic_gl_map_vpe[reg];
+ }
+
+ if (addr >= GIC_VPELOCAL_BASE_ADDR && addr < GIC_VPEOTHER_BASE_ADDR) {
+ }
+
+ if (addr >= GIC_VPEOTHER_BASE_ADDR && addr < GIC_USERMODE_BASE_ADDR) {
+ }
+
+ DPRINTF("%s: unimplemented register @ %#" PRIx64 "\n", __func__, addr);
+ return 0ULL;
+}
+
+static void
+gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
+{
+ int reg, intr;
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr, data,
+ size);
+
+ switch (addr) {
+ case GIC_SH_POL_31_0_OFS:
+ case GIC_SH_POL_63_32_OFS:
+ case GIC_SH_POL_95_64_OFS:
+ case GIC_SH_POL_127_96_OFS:
+ case GIC_SH_POL_159_128_OFS:
+ case GIC_SH_POL_191_160_OFS:
+ case GIC_SH_POL_223_192_OFS:
+ case GIC_SH_POL_255_224_OFS:
+ reg = (addr - GIC_SH_POL_31_0_OFS) / 4;
+ gic->gic_gl_intr_pol_reg[reg] = data;
+ break;
+
+ case GIC_SH_TRIG_31_0_OFS:
+ case GIC_SH_TRIG_63_32_OFS:
+ case GIC_SH_TRIG_95_64_OFS:
+ case GIC_SH_TRIG_127_96_OFS:
+ case GIC_SH_TRIG_159_128_OFS:
+ case GIC_SH_TRIG_191_160_OFS:
+ case GIC_SH_TRIG_223_192_OFS:
+ case GIC_SH_TRIG_255_224_OFS:
+ reg = (addr - GIC_SH_TRIG_31_0_OFS) / 4;
+ gic->gic_gl_intr_trigtype_reg[reg] = data;
+ break;
+
+ case GIC_SH_RMASK_31_0_OFS:
+ case GIC_SH_RMASK_63_32_OFS:
+ case GIC_SH_RMASK_95_64_OFS:
+ case GIC_SH_RMASK_127_96_OFS:
+ case GIC_SH_RMASK_159_128_OFS:
+ case GIC_SH_RMASK_191_160_OFS:
+ case GIC_SH_RMASK_223_192_OFS:
+ case GIC_SH_RMASK_255_224_OFS:
+ reg = (addr - GIC_SH_RMASK_31_0_OFS) / 4;
+ gic->gic_gl_intr_mask_reg[reg] &= ~data;
+ break;
+
+ case GIC_SH_WEDGE_OFS:
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr,
+ data, size);
+
+ /* Figure out which VPE/HW Interrupt this maps to */
+ intr = data & 0x7FFFFFFF;
+
+ /* XXXSL Mask/Enabled Checks */
+ if (data & 0x80000000)
+ qemu_set_irq(gic->irqs[intr], 1);
+ else
+ qemu_set_irq(gic->irqs[intr], 0);
+
+ break;
+
+ case GIC_SH_PEND_31_0_OFS:
+ case GIC_SH_PEND_63_32_OFS:
+ case GIC_SH_PEND_95_64_OFS:
+ case GIC_SH_PEND_127_96_OFS:
+ case GIC_SH_PEND_159_128_OFS:
+ case GIC_SH_PEND_191_160_OFS:
+ case GIC_SH_PEND_223_192_OFS:
+ case GIC_SH_PEND_255_224_OFS:
+ break;
+
+ case GIC_SH_SMASK_31_0_OFS:
+ case GIC_SH_SMASK_63_32_OFS:
+ case GIC_SH_SMASK_95_64_OFS:
+ case GIC_SH_SMASK_127_96_OFS:
+ case GIC_SH_SMASK_159_128_OFS:
+ case GIC_SH_SMASK_191_160_OFS:
+ case GIC_SH_SMASK_223_192_OFS:
+ case GIC_SH_SMASK_255_224_OFS:
+ reg = (addr - GIC_SH_SMASK_31_0_OFS) / 4;
+ gic->gic_gl_intr_mask_reg[reg] |= data;
+ break;
+
+ default:
+ break;
+ }
+
+ /* Other cases */
+ if (addr >= GIC_SH_INTR_MAP_TO_PIN_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_PIN(255)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_PIN_BASE_OFS) / 4;
+ gic->gic_gl_map_pin[reg] = data;
+ }
+ if (addr >= GIC_SH_INTR_MAP_TO_VPE_BASE_OFS
+ && addr <= GIC_SH_MAP_TO_VPE_REG_OFF(255, 63)) {
+ reg = (addr - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4;
+ gic->gic_gl_map_vpe[reg] = data;
+ }
+
+ if (addr >= GIC_VPELOCAL_BASE_ADDR && addr < GIC_VPEOTHER_BASE_ADDR) {
+ }
+
+ if (addr >= GIC_VPEOTHER_BASE_ADDR && addr < GIC_USERMODE_BASE_ADDR) {
+ }
+}
+
+static uint64_t
+gcr_read(void *opaque, hwaddr addr, unsigned size)
+{
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", size: %#x\n", addr, size);
+
+ switch (addr) {
+ case GCMP_GCB_GC_OFS:
+ /* Set PCORES to # cores - 1 */
+ return smp_cpus - 1;
+ break;
+
+ case GCMP_GCB_GCMPB_OFS:
+ return GCMP_BASE_ADDR;
+ break;
+
+ case GCMP_GCB_GICBA_OFS:
+ return gic->gcr_gic_base_reg;
+ break;
+
+ default:
+ DPRINTF("Unsupported Reg Read @ offset %#" PRIx64 "\n", addr);
+ return 0;
+ }
+
+ return 0ULL;
+}
+
+static void
+gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
+{
+ gic_t *gic = (gic_t *) opaque;
+
+ DPRINTF("addr: %#" PRIx64 ", data: %#" PRIx64 ", size: %#x\n", addr, data,
+ size);
+
+ switch (addr) {
+ case GCMP_GCB_GICBA_OFS:
+ gic->gcr_gic_base_reg = data;
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+
+static void
+gic_set_irq(void *opaque, int n_IRQ, int level)
+{
+ int vpe = -1, pin = -1, i;
+ gic_t *gic = (gic_t *) opaque;
+
+ pin = gic->gic_gl_map_pin[n_IRQ] & 0x7;
+
+ for (i = 0; i < NUMVPES; i++) {
+ vpe = gic-> gic_gl_map_vpe[(GIC_SH_MAP_TO_VPE_REG_OFF(n_IRQ, i) - GIC_SH_INTR_MAP_TO_VPE_BASE_OFS) / 4];
+ if (vpe & GIC_SH_MAP_TO_VPE_REG_BIT(i)) {
+ vpe = i;
+ break;
+ }
+ }
+
+ if (pin >= 0 && vpe >= 0) {
+ int offset;
+ DPRINTF("[%s] INTR %d maps to PIN %d on VPE %d\n", (level ? "ASSERT" : "DEASSERT"), n_IRQ, pin, vpe);
+ /* Set the Global PEND register */
+ offset = GIC_INTR_OFS(n_IRQ) / 4;
+ if (level)
+ gic->gic_gl_intr_pending_reg[offset] |= (1 << GIC_INTR_BIT(n_IRQ));
+ else
+ gic->gic_gl_intr_pending_reg[offset] &= ~(1 << GIC_INTR_BIT(n_IRQ));
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled()) {
+ kvm_mips_set_ipi_interrupt (gic->env[vpe], pin+2, level);
+ }
+#endif
+
+ qemu_set_irq(gic->env[vpe]->irq[pin+2], level);
+ }
+}
+
+static void
+gic_reset(void *opaque)
+{
+ int i;
+ gic_t *gic = (gic_t *) opaque;
+
+ /* Rest value is map to pin */
+ for (i = 0; i < 256; i++)
+ gic->gic_gl_map_pin[i] = GIC_MAP_TO_PIN_MSK;
+
+}
+
+static const MemoryRegionOps gic_ops = {
+ .read = gic_read,
+ .write = gic_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const MemoryRegionOps gcr_ops = {
+ .read = gcr_read,
+ .write = gcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+qemu_irq *
+gic_init(uint32_t ncpus, CPUMIPSState *env, MemoryRegion * address_space)
+{
+ CPUMIPSState *next_env;
+ gic_t *gic;
+ uint32_t x;
+
+ if (ncpus > NUMVPES) {
+ fprintf(stderr, "Unable to initialize GIC - ncpus %d > NUMVPES!", ncpus);
+ return NULL;
+ }
+
+ gic = (gic_t *) g_malloc0(sizeof(gic_t));
+
+ /* Register the CPU env for all cpus with the GIC */
+ next_env = env;
+ for (x = 0; x < ncpus; x++) {
+ if (next_env != NULL) {
+ gic->env[x] = next_env;
+ next_env = next_env->next_cpu;
+ } else {
+ fprintf(stderr, "Unable to initialize GIC - CPUMIPSState for CPU #%d not valid!", x);
+ return NULL;
+ }
+ }
+
+ /* Register GCR & GIC regions */
+ memory_region_init_io(&gic->gcr_mem, &gcr_ops, gic, "GCR",
+ GCMP_ADDRSPACE_SZ);
+ memory_region_init_io(&gic->gic_mem, &gic_ops, gic, "GIC",
+ GIC_ADDRSPACE_SZ);
+
+ memory_region_add_subregion(address_space, GCMP_BASE_ADDR, &gic->gcr_mem);
+ memory_region_add_subregion(address_space, GIC_BASE_ADDR, &gic->gic_mem);
+
+ qemu_register_reset(gic_reset, gic);
+
+ gic->irqs = qemu_allocate_irqs(gic_set_irq, gic, GIC_NUM_INTRS);
+
+ return (gic->irqs);
+}
diff --git a/hw/mips_gic.h b/hw/mips_gic.h
new file mode 100644
index 0000000..4a2c828
--- /dev/null
+++ b/hw/mips_gic.h
@@ -0,0 +1,378 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * GIC Register Definitions
+ *
+ */
+#ifndef _ASM_GICREGS_H
+#define _ASM_GICREGS_H
+
+#undef GICISBYTELITTLEENDIAN
+
+#define NR_CPUS 8
+/*
+ * GCMP Specific definitions
+ */
+
+/* XXXKYMA: Malta Specific base address */
+#define GCMP_BASE_ADDR 0x1fbf8000ULL
+#define GCMP_ADDRSPACE_SZ (256 * 1024)
+
+/*
+ * GIC Specific definitions
+ */
+
+/* XXXKYMA: Malta Specific base address */
+#define GIC_BASE_ADDR 0x1bdc0000ULL
+#define GIC_ADDRSPACE_SZ (128 * 1024)
+
+/* GIC Address Space Offsets */
+#define GIC_SHARED_BASE_ADDR 0x0000
+#define GIC_VPELOCAL_BASE_ADDR 0x8000
+#define GIC_VPEOTHER_BASE_ADDR 0xC000
+#define GIC_USERMODE_BASE_ADDR 0x10000
+
+/* Shared Section Offsets */
+#define GIC_G_INTR_POLARITY_REG0 0x0100
+#define GIC_G_INTR_POLARITY_REG1 0x0104
+#define GIC_G_INTR_TRIGTYPE_REG0 0x0180
+#define GIC_G_INTR_TRIGTYPE_REG1 0x0184
+#define GIC_G_INTR_RESETMASK_REG0 0x0300
+#define GIC_G_INTR_RESETMASK_REG1 0x0304
+#define GIC_G_INTR_SETMASK_REG0 0x0380
+
+/*
+ * MSC01 BIU Specific definitions
+ * FIXME : These should be elsewhere ?
+ */
+#define MSC01_BIU_REG_BASE 0x1bc80000
+#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
+#define MSC01_SC_CFG_OFS 0x0110
+#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
+#define MSC01_SC_CFG_GICPRES_SHF 2
+#define MSC01_SC_CFG_GICENA_SHF 3
+
+/* Constants */
+#define GIC_POL_POS 1
+#define GIC_POL_NEG 0
+#define GIC_TRIG_EDGE 1
+#define GIC_TRIG_LEVEL 0
+
+#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
+
+#define MSK(n) ((1 << (n)) - 1)
+#define REG32(addr) (*(volatile unsigned int *) (addr))
+#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
+#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
+
+/* Accessors */
+#define GIC_REG(segment, offset) \
+ REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ADDR(segment, offset) \
+ REG32(_gic_base + segment##_##SECTION_OFS + offset)
+
+#define GIC_ABS_REG(segment, offset) \
+ (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ABS_ADDR(segment, offset) \
+ (_gic_base + segment##_##SECTION_OFS + offset)
+
+#ifdef GICISBYTELITTLEENDIAN
+#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
+#define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
+#define GICBIS(reg, bits) \
+ ({unsigned int data; \
+ GICREAD(reg, data); \
+ data |= bits; \
+ GICWRITE(reg, data); \
+ })
+
+#else
+#define GICREAD(reg, data) (data) = (reg)
+#define GICWRITE(reg, data) (reg) = (data)
+#define GICBIS(reg, bits) (reg) |= (bits)
+#endif
+
+
+/* GIC Address Space */
+#define SHARED_SECTION_OFS 0x0000
+#define SHARED_SECTION_SIZE 0x8000
+#define VPE_LOCAL_SECTION_OFS 0x8000
+#define VPE_LOCAL_SECTION_SIZE 0x4000
+#define VPE_OTHER_SECTION_OFS 0xc000
+#define VPE_OTHER_SECTION_SIZE 0x4000
+#define USM_VISIBLE_SECTION_OFS 0x10000
+#define USM_VISIBLE_SECTION_SIZE 0x10000
+
+/* Register Map for Shared Section */
+
+#define GIC_SH_CONFIG_OFS 0x0000
+
+/* Shared Global Counter */
+#define GIC_SH_COUNTER_31_00_OFS 0x0010
+#define GIC_SH_COUNTER_63_32_OFS 0x0014
+#define GIC_SH_REVISIONID_OFS 0x0020
+
+/* Interrupt Polarity */
+#define GIC_SH_POL_31_0_OFS 0x0100
+#define GIC_SH_POL_63_32_OFS 0x0104
+#define GIC_SH_POL_95_64_OFS 0x0108
+#define GIC_SH_POL_127_96_OFS 0x010c
+#define GIC_SH_POL_159_128_OFS 0x0110
+#define GIC_SH_POL_191_160_OFS 0x0114
+#define GIC_SH_POL_223_192_OFS 0x0118
+#define GIC_SH_POL_255_224_OFS 0x011c
+
+/* Edge/Level Triggering */
+#define GIC_SH_TRIG_31_0_OFS 0x0180
+#define GIC_SH_TRIG_63_32_OFS 0x0184
+#define GIC_SH_TRIG_95_64_OFS 0x0188
+#define GIC_SH_TRIG_127_96_OFS 0x018c
+#define GIC_SH_TRIG_159_128_OFS 0x0190
+#define GIC_SH_TRIG_191_160_OFS 0x0194
+#define GIC_SH_TRIG_223_192_OFS 0x0198
+#define GIC_SH_TRIG_255_224_OFS 0x019c
+
+/* Dual Edge Triggering */
+#define GIC_SH_DUAL_31_0_OFS 0x0200
+#define GIC_SH_DUAL_63_32_OFS 0x0204
+#define GIC_SH_DUAL_95_64_OFS 0x0208
+#define GIC_SH_DUAL_127_96_OFS 0x020c
+#define GIC_SH_DUAL_159_128_OFS 0x0210
+#define GIC_SH_DUAL_191_160_OFS 0x0214
+#define GIC_SH_DUAL_223_192_OFS 0x0218
+#define GIC_SH_DUAL_255_224_OFS 0x021c
+
+/* Set/Clear corresponding bit in Edge Detect Register */
+#define GIC_SH_WEDGE_OFS 0x0280
+
+/* Reset Mask - Disables Interrupt */
+#define GIC_SH_RMASK_31_0_OFS 0x0300
+#define GIC_SH_RMASK_63_32_OFS 0x0304
+#define GIC_SH_RMASK_95_64_OFS 0x0308
+#define GIC_SH_RMASK_127_96_OFS 0x030c
+#define GIC_SH_RMASK_159_128_OFS 0x0310
+#define GIC_SH_RMASK_191_160_OFS 0x0314
+#define GIC_SH_RMASK_223_192_OFS 0x0318
+#define GIC_SH_RMASK_255_224_OFS 0x031c
+
+/* Set Mask (WO) - Enables Interrupt */
+#define GIC_SH_SMASK_31_0_OFS 0x0380
+#define GIC_SH_SMASK_63_32_OFS 0x0384
+#define GIC_SH_SMASK_95_64_OFS 0x0388
+#define GIC_SH_SMASK_127_96_OFS 0x038c
+#define GIC_SH_SMASK_159_128_OFS 0x0390
+#define GIC_SH_SMASK_191_160_OFS 0x0394
+#define GIC_SH_SMASK_223_192_OFS 0x0398
+#define GIC_SH_SMASK_255_224_OFS 0x039c
+
+/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
+#define GIC_SH_MASK_31_0_OFS 0x0400
+#define GIC_SH_MASK_63_32_OFS 0x0404
+#define GIC_SH_MASK_95_64_OFS 0x0408
+#define GIC_SH_MASK_127_96_OFS 0x040c
+#define GIC_SH_MASK_159_128_OFS 0x0410
+#define GIC_SH_MASK_191_160_OFS 0x0414
+#define GIC_SH_MASK_223_192_OFS 0x0418
+#define GIC_SH_MASK_255_224_OFS 0x041c
+
+/* Pending Global Interrupts (RO) */
+#define GIC_SH_PEND_31_0_OFS 0x0480
+#define GIC_SH_PEND_63_32_OFS 0x0484
+#define GIC_SH_PEND_95_64_OFS 0x0488
+#define GIC_SH_PEND_127_96_OFS 0x048c
+#define GIC_SH_PEND_159_128_OFS 0x0490
+#define GIC_SH_PEND_191_160_OFS 0x0494
+#define GIC_SH_PEND_223_192_OFS 0x0498
+#define GIC_SH_PEND_255_224_OFS 0x049c
+
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
+
+/* Maps Interrupt X to a Pin */
+#define GIC_SH_MAP_TO_PIN(intr) \
+ (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
+
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
+
+/* Maps Interrupt X to a VPE */
+#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
+ (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
+#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
+
+/* Convert an interrupt number to a byte offset/bit for multi-word registers */
+#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
+#define GIC_INTR_BIT(intr) ((intr) % 32)
+
+/* Polarity : Reset Value is always 0 */
+#define GIC_SH_SET_POLARITY_OFS 0x0100
+#define GIC_SET_POLARITY(intr, pol) \
+ GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
+ GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
+
+/* Triggering : Reset Value is always 0 */
+#define GIC_SH_SET_TRIGGER_OFS 0x0180
+#define GIC_SET_TRIGGER(intr, trig) \
+ GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
+ GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
+
+/* Mask manipulation */
+#define GIC_SH_SMASK_OFS 0x0380
+#define GIC_SET_INTR_MASK(intr) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
+ GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
+#define GIC_SH_RMASK_OFS 0x0300
+#define GIC_CLR_INTR_MASK(intr) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
+ GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
+
+/* Register Map for Local Section */
+#define GIC_VPE_CTL_OFS 0x0000
+#define GIC_VPE_PEND_OFS 0x0004
+#define GIC_VPE_MASK_OFS 0x0008
+#define GIC_VPE_RMASK_OFS 0x000c
+#define GIC_VPE_SMASK_OFS 0x0010
+#define GIC_VPE_WD_MAP_OFS 0x0040
+#define GIC_VPE_COMPARE_MAP_OFS 0x0044
+#define GIC_VPE_TIMER_MAP_OFS 0x0048
+#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
+#define GIC_VPE_SWINT0_MAP_OFS 0x0054
+#define GIC_VPE_SWINT1_MAP_OFS 0x0058
+#define GIC_VPE_OTHER_ADDR_OFS 0x0080
+#define GIC_VPE_WD_CONFIG0_OFS 0x0090
+#define GIC_VPE_WD_COUNT0_OFS 0x0094
+#define GIC_VPE_WD_INITIAL0_OFS 0x0098
+#define GIC_VPE_COMPARE_LO_OFS 0x00a0
+#define GIC_VPE_COMPARE_HI 0x00a4
+
+#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
+#define GIC_VPE_EIC_SS(intr) \
+ (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+
+#define GIC_VPE_EIC_VEC_BASE 0x0800
+#define GIC_VPE_EIC_VEC(intr) \
+ (GIC_VPE_EIC_VEC_BASE + (4 * intr))
+
+#define GIC_VPE_TENABLE_NMI_OFS 0x1000
+#define GIC_VPE_TENABLE_YQ_OFS 0x1004
+#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
+#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
+
+/* User Mode Visible Section Register Map */
+#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
+#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
+
+/* Masks */
+#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
+#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
+
+#define GIC_SH_CONFIG_COUNTBITS_SHF 24
+#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
+
+#define GIC_SH_CONFIG_NUMINTRS_SHF 16
+#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
+
+#define GIC_SH_CONFIG_NUMVPES_SHF 0
+#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
+
+#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
+#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
+
+#define GIC_MAP_TO_PIN_SHF 31
+#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
+#define GIC_MAP_TO_NMI_SHF 30
+#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
+#define GIC_MAP_TO_YQ_SHF 29
+#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
+#define GIC_MAP_SHF 0
+#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
+
+/* GIC_VPE_CTL Masks */
+#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
+#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
+#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
+#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
+#define GIC_VPE_CTL_EIC_MODE_SHF 0
+#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
+
+/* GIC_VPE_PEND Masks */
+#define GIC_VPE_PEND_WD_SHF 0
+#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
+#define GIC_VPE_PEND_CMP_SHF 1
+#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
+#define GIC_VPE_PEND_TIMER_SHF 2
+#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
+#define GIC_VPE_PEND_PERFCOUNT_SHF 3
+#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
+#define GIC_VPE_PEND_SWINT0_SHF 4
+#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
+#define GIC_VPE_PEND_SWINT1_SHF 5
+#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
+
+/* GIC_VPE_RMASK Masks */
+#define GIC_VPE_RMASK_WD_SHF 0
+#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
+#define GIC_VPE_RMASK_CMP_SHF 1
+#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
+#define GIC_VPE_RMASK_TIMER_SHF 2
+#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
+#define GIC_VPE_RMASK_PERFCNT_SHF 3
+#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
+#define GIC_VPE_RMASK_SWINT0_SHF 4
+#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
+#define GIC_VPE_RMASK_SWINT1_SHF 5
+#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
+
+/* GIC_VPE_SMASK Masks */
+#define GIC_VPE_SMASK_WD_SHF 0
+#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
+#define GIC_VPE_SMASK_CMP_SHF 1
+#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
+#define GIC_VPE_SMASK_TIMER_SHF 2
+#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
+#define GIC_VPE_SMASK_PERFCNT_SHF 3
+#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
+#define GIC_VPE_SMASK_SWINT0_SHF 4
+#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
+#define GIC_VPE_SMASK_SWINT1_SHF 5
+#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
+
+/*
+ * Set the Mapping of Interrupt X to a VPE.
+ */
+#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
+ GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
+ GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
+
+struct gic_pcpu_mask {
+ DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
+};
+
+struct gic_pending_regs {
+ DECLARE_BITMAP(pending, GIC_NUM_INTRS);
+};
+
+struct gic_intrmask_regs {
+ DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
+};
+
+/*
+ * Interrupt Meta-data specification. The ipiflag helps
+ * in building ipi_map.
+ */
+struct gic_intr_map {
+ unsigned int cpunum; /* Directed to this CPU */
+#define GIC_UNUSED 0xdead /* Dummy data */
+ unsigned int pin; /* Directed to this Pin */
+ unsigned int polarity; /* Polarity : +/- */
+ unsigned int trigtype; /* Trigger : Edge/Levl */
+ unsigned int flags; /* Misc flags */
+#define GIC_FLAG_IPI 0x01
+#define GIC_FLAG_TRANSPARENT 0x02
+};
+
+qemu_irq *gic_init (uint32_t ncpus, CPUMIPSState *env, MemoryRegion *address_space);
+
+#endif /* _ASM_GICREGS_H */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/gt64xxx.c | 317 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 317 insertions(+)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 977a2c5..3583ca8 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -31,6 +31,8 @@
//#define DEBUG
+#define GT64XXX_VM_VERSION 1
+
#ifdef DEBUG
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
@@ -1092,6 +1094,317 @@ static void gt64120_reset(void *opaque)
gt64120_pci_mapping(s);
}
+static void gt64xxx_save(QEMUFile *f, void *opaque)
+{
+ GT64120State *s = opaque;
+
+ /* CPU Configuration */
+ qemu_put_be32s(f, &s->regs[GT_CPU]);
+ qemu_put_be32s(f, &s->regs[GT_MULTI]);
+
+ /* CPU Address decode */
+ qemu_put_be32s(f, &s->regs[GT_SCS10LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS10HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS20LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS20HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTLD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTHD]);
+
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOLD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOHD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0HD]);
+ qemu_put_be32s(f, &s->regs[GT_ISD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1HD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOLD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOHD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0HD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1HD]);
+
+ qemu_put_be32s(f, &s->regs[GT_SCS10AR]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32AR]);
+ qemu_put_be32s(f, &s->regs[GT_CS20R]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTR]);
+
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOREMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOREMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1REMAP]);
+
+ /* CPU Error Report */
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRLO]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRHI]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_DATALO]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_DATAHI]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_PARITY]);
+
+ /* CPU Sync Barrier */
+ qemu_put_be32s(f, &s->regs[GT_PCI0SYNC]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1SYNC]);
+
+ /* SDRAM and Device Address Decode */
+ qemu_put_be32s(f, &s->regs[GT_SCS0LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS0HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS1LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS1HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS2LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS2HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS3LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS3HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS0LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS0HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS1LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS1HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS2LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS2HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3HD]);
+ qemu_put_be32s(f, &s->regs[GT_BOOTLD]);
+ qemu_put_be32s(f, &s->regs[GT_BOOTHD]);
+ qemu_put_be32s(f, &s->regs[GT_ADERR]);
+
+ /* SDRAM Configuration */
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_CFG]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_OPMODE]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_BM]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_ADDRDECODE]);
+
+ /* SDRAM Parameters */
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B0]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B1]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B2]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B3]);
+
+ /* ECC */
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATALO]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATAHI]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_MEM]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_CALC]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRADDR]);
+
+ /* Device Parameters */
+ qemu_put_be32s(f, &s->regs[GT_DEV_B0]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B1]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B2]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B3]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_BOOT]);
+
+ /* DMA registers are all zeroed at reset */
+
+ /* Timer/Counter */
+ qemu_put_be32s(f, &s->regs[GT_TC0]);
+ qemu_put_be32s(f, &s->regs[GT_TC1]);
+ qemu_put_be32s(f, &s->regs[GT_TC2]);
+ qemu_put_be32s(f, &s->regs[GT_TC3]);
+ qemu_put_be32s(f, &s->regs[GT_TC_CONTROL]);
+
+ /* PCI Internal */
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_TOR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_SCS10]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_SCS32]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_CS20]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_CS3BT]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_IACK]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_IACK]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BARE]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_PREFMBR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CS20_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SSCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SSCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_TOR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_SCS10]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_SCS32]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_CS20]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_CS3BT]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BARE]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_PREFMBR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CS20_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SSCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SSCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CFGADDR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CFGDATA]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CFGADDR]);
+
+ return;
+}
+
+static int gt64xxx_load(QEMUFile *f, void *opaque, int version_id)
+{
+ GT64120State *s = opaque;
+
+ if (version_id != GT64XXX_VM_VERSION)
+ return -EINVAL;
+
+ /* CPU Configuration */
+ qemu_get_be32s(f, &s->regs[GT_CPU]);
+ qemu_get_be32s(f, &s->regs[GT_MULTI]);
+
+ /* CPU Address decode */
+ qemu_get_be32s(f, &s->regs[GT_SCS10LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS10HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS20LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS20HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTLD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTHD]);
+
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOLD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOHD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0HD]);
+ qemu_get_be32s(f, &s->regs[GT_ISD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1HD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOLD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOHD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0HD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1HD]);
+
+ qemu_get_be32s(f, &s->regs[GT_SCS10AR]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32AR]);
+ qemu_get_be32s(f, &s->regs[GT_CS20R]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTR]);
+
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOREMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOREMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1REMAP]);
+
+ /* CPU Error Report */
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_ADDRLO]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_ADDRHI]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_DATALO]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_DATAHI]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_PARITY]);
+
+ /* CPU Sync Barrier */
+ qemu_get_be32s(f, &s->regs[GT_PCI0SYNC]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1SYNC]);
+
+ /* SDRAM and Device Address Decode */
+ qemu_get_be32s(f, &s->regs[GT_SCS0LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS0HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS1LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS1HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS2LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS2HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS3LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS3HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS0LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS0HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS1LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS1HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS2LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS2HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3HD]);
+ qemu_get_be32s(f, &s->regs[GT_BOOTLD]);
+ qemu_get_be32s(f, &s->regs[GT_BOOTHD]);
+ qemu_get_be32s(f, &s->regs[GT_ADERR]);
+
+ /* SDRAM Configuration */
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_CFG]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_OPMODE]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_BM]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_ADDRDECODE]);
+
+ /* SDRAM Parameters */
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B0]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B1]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B2]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B3]);
+
+ /* ECC */
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRDATALO]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRDATAHI]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_MEM]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_CALC]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRADDR]);
+
+ /* Device Parameters */
+ qemu_get_be32s(f, &s->regs[GT_DEV_B0]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B1]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B2]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B3]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_BOOT]);
+
+ /* DMA registers are all zeroed at reset */
+
+ /* Timer/Counter */
+ qemu_get_be32s(f, &s->regs[GT_TC0]);
+ qemu_get_be32s(f, &s->regs[GT_TC1]);
+ qemu_get_be32s(f, &s->regs[GT_TC2]);
+ qemu_get_be32s(f, &s->regs[GT_TC3]);
+ qemu_get_be32s(f, &s->regs[GT_TC_CONTROL]);
+
+ /* PCI Internal */
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_TOR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_SCS10]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_SCS32]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_CS20]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_CS3BT]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_IACK]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_IACK]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BARE]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_PREFMBR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CS20_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SSCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SSCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_TOR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_SCS10]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_SCS32]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_CS20]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_CS3BT]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BARE]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_PREFMBR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CS20_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SSCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SSCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CFGADDR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CFGDATA]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CFGADDR]);
+
+ gt64120_isd_mapping(s);
+ gt64120_pci_mapping(s);
+
+ return 0;
+}
+
+
PCIBus *gt64120_register(qemu_irq *pic)
{
GT64120State *d;
@@ -1111,6 +1424,10 @@ PCIBus *gt64120_register(qemu_irq *pic)
memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
+
+ register_savevm(dev, "gt64xxx", -1, GT64XXX_VM_VERSION,
+ gt64xxx_save, gt64xxx_load, d);
+
return phb->bus;
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/gt64xxx.c | 317 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 317 insertions(+)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 977a2c5..3583ca8 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -31,6 +31,8 @@
//#define DEBUG
+#define GT64XXX_VM_VERSION 1
+
#ifdef DEBUG
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
@@ -1092,6 +1094,317 @@ static void gt64120_reset(void *opaque)
gt64120_pci_mapping(s);
}
+static void gt64xxx_save(QEMUFile *f, void *opaque)
+{
+ GT64120State *s = opaque;
+
+ /* CPU Configuration */
+ qemu_put_be32s(f, &s->regs[GT_CPU]);
+ qemu_put_be32s(f, &s->regs[GT_MULTI]);
+
+ /* CPU Address decode */
+ qemu_put_be32s(f, &s->regs[GT_SCS10LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS10HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS20LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS20HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTLD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTHD]);
+
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOLD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOHD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0HD]);
+ qemu_put_be32s(f, &s->regs[GT_ISD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1HD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOLD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOHD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0HD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1LD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1HD]);
+
+ qemu_put_be32s(f, &s->regs[GT_SCS10AR]);
+ qemu_put_be32s(f, &s->regs[GT_SCS32AR]);
+ qemu_put_be32s(f, &s->regs[GT_CS20R]);
+ qemu_put_be32s(f, &s->regs[GT_CS3BOOTR]);
+
+ qemu_put_be32s(f, &s->regs[GT_PCI0IOREMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M0REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0M1REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1IOREMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M0REMAP]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1M1REMAP]);
+
+ /* CPU Error Report */
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRLO]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRHI]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_DATALO]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_DATAHI]);
+ qemu_put_be32s(f, &s->regs[GT_CPUERR_PARITY]);
+
+ /* CPU Sync Barrier */
+ qemu_put_be32s(f, &s->regs[GT_PCI0SYNC]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1SYNC]);
+
+ /* SDRAM and Device Address Decode */
+ qemu_put_be32s(f, &s->regs[GT_SCS0LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS0HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS1LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS1HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS2LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS2HD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS3LD]);
+ qemu_put_be32s(f, &s->regs[GT_SCS3HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS0LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS0HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS1LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS1HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS2LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS2HD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3LD]);
+ qemu_put_be32s(f, &s->regs[GT_CS3HD]);
+ qemu_put_be32s(f, &s->regs[GT_BOOTLD]);
+ qemu_put_be32s(f, &s->regs[GT_BOOTHD]);
+ qemu_put_be32s(f, &s->regs[GT_ADERR]);
+
+ /* SDRAM Configuration */
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_CFG]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_OPMODE]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_BM]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_ADDRDECODE]);
+
+ /* SDRAM Parameters */
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B0]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B1]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B2]);
+ qemu_put_be32s(f, &s->regs[GT_SDRAM_B3]);
+
+ /* ECC */
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATALO]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATAHI]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_MEM]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_CALC]);
+ qemu_put_be32s(f, &s->regs[GT_ECC_ERRADDR]);
+
+ /* Device Parameters */
+ qemu_put_be32s(f, &s->regs[GT_DEV_B0]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B1]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B2]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_B3]);
+ qemu_put_be32s(f, &s->regs[GT_DEV_BOOT]);
+
+ /* DMA registers are all zeroed at reset */
+
+ /* Timer/Counter */
+ qemu_put_be32s(f, &s->regs[GT_TC0]);
+ qemu_put_be32s(f, &s->regs[GT_TC1]);
+ qemu_put_be32s(f, &s->regs[GT_TC2]);
+ qemu_put_be32s(f, &s->regs[GT_TC3]);
+ qemu_put_be32s(f, &s->regs[GT_TC_CONTROL]);
+
+ /* PCI Internal */
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_TOR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_SCS10]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_SCS32]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_CS20]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BS_CS3BT]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_IACK]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_IACK]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_BARE]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_PREFMBR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CS20_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SSCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SSCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_SCS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CMD]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_TOR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_SCS10]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_SCS32]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_CS20]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BS_CS3BT]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_BARE]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_PREFMBR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CS20_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SSCS10_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SSCS32_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_SCS3BT_BAR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CFGADDR]);
+ qemu_put_be32s(f, &s->regs[GT_PCI1_CFGDATA]);
+ qemu_put_be32s(f, &s->regs[GT_PCI0_CFGADDR]);
+
+ return;
+}
+
+static int gt64xxx_load(QEMUFile *f, void *opaque, int version_id)
+{
+ GT64120State *s = opaque;
+
+ if (version_id != GT64XXX_VM_VERSION)
+ return -EINVAL;
+
+ /* CPU Configuration */
+ qemu_get_be32s(f, &s->regs[GT_CPU]);
+ qemu_get_be32s(f, &s->regs[GT_MULTI]);
+
+ /* CPU Address decode */
+ qemu_get_be32s(f, &s->regs[GT_SCS10LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS10HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS20LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS20HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTLD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTHD]);
+
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOLD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOHD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0HD]);
+ qemu_get_be32s(f, &s->regs[GT_ISD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1HD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOLD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOHD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0HD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1LD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1HD]);
+
+ qemu_get_be32s(f, &s->regs[GT_SCS10AR]);
+ qemu_get_be32s(f, &s->regs[GT_SCS32AR]);
+ qemu_get_be32s(f, &s->regs[GT_CS20R]);
+ qemu_get_be32s(f, &s->regs[GT_CS3BOOTR]);
+
+ qemu_get_be32s(f, &s->regs[GT_PCI0IOREMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M0REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0M1REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1IOREMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M0REMAP]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1M1REMAP]);
+
+ /* CPU Error Report */
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_ADDRLO]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_ADDRHI]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_DATALO]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_DATAHI]);
+ qemu_get_be32s(f, &s->regs[GT_CPUERR_PARITY]);
+
+ /* CPU Sync Barrier */
+ qemu_get_be32s(f, &s->regs[GT_PCI0SYNC]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1SYNC]);
+
+ /* SDRAM and Device Address Decode */
+ qemu_get_be32s(f, &s->regs[GT_SCS0LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS0HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS1LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS1HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS2LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS2HD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS3LD]);
+ qemu_get_be32s(f, &s->regs[GT_SCS3HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS0LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS0HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS1LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS1HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS2LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS2HD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3LD]);
+ qemu_get_be32s(f, &s->regs[GT_CS3HD]);
+ qemu_get_be32s(f, &s->regs[GT_BOOTLD]);
+ qemu_get_be32s(f, &s->regs[GT_BOOTHD]);
+ qemu_get_be32s(f, &s->regs[GT_ADERR]);
+
+ /* SDRAM Configuration */
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_CFG]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_OPMODE]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_BM]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_ADDRDECODE]);
+
+ /* SDRAM Parameters */
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B0]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B1]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B2]);
+ qemu_get_be32s(f, &s->regs[GT_SDRAM_B3]);
+
+ /* ECC */
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRDATALO]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRDATAHI]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_MEM]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_CALC]);
+ qemu_get_be32s(f, &s->regs[GT_ECC_ERRADDR]);
+
+ /* Device Parameters */
+ qemu_get_be32s(f, &s->regs[GT_DEV_B0]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B1]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B2]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_B3]);
+ qemu_get_be32s(f, &s->regs[GT_DEV_BOOT]);
+
+ /* DMA registers are all zeroed at reset */
+
+ /* Timer/Counter */
+ qemu_get_be32s(f, &s->regs[GT_TC0]);
+ qemu_get_be32s(f, &s->regs[GT_TC1]);
+ qemu_get_be32s(f, &s->regs[GT_TC2]);
+ qemu_get_be32s(f, &s->regs[GT_TC3]);
+ qemu_get_be32s(f, &s->regs[GT_TC_CONTROL]);
+
+ /* PCI Internal */
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_TOR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_SCS10]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_SCS32]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_CS20]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BS_CS3BT]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_IACK]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_IACK]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_BARE]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_PREFMBR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CS20_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SSCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SSCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_SCS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CMD]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_TOR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_SCS10]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_SCS32]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_CS20]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BS_CS3BT]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_BARE]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_PREFMBR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CS20_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SSCS10_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SSCS32_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_SCS3BT_BAR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CFGADDR]);
+ qemu_get_be32s(f, &s->regs[GT_PCI1_CFGDATA]);
+ qemu_get_be32s(f, &s->regs[GT_PCI0_CFGADDR]);
+
+ gt64120_isd_mapping(s);
+ gt64120_pci_mapping(s);
+
+ return 0;
+}
+
+
PCIBus *gt64120_register(qemu_irq *pic)
{
GT64120State *d;
@@ -1111,6 +1424,10 @@ PCIBus *gt64120_register(qemu_irq *pic)
memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
+
+ register_savevm(dev, "gt64xxx", -1, GT64XXX_VM_VERSION,
+ gt64xxx_save, gt64xxx_load, d);
+
return phb->bus;
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 04/12] KVM/MIPS: Do not start the periodic timer in KVM mode. Compare/Count timer interrupts are handled in-kernel.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/mips_timer.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 83c400c..0c86a3b 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -19,11 +19,13 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-
#include "hw.h"
#include "mips_cpudevs.h"
#include "qemu/timer.h"
+#include "sysemu/kvm.h"
+
+
#define TIMER_FREQ 100 * 1000 * 1000
/* XXX: do not use a global */
@@ -141,7 +143,10 @@ static void mips_timer_cb (void *opaque)
void cpu_mips_clock_init (CPUMIPSState *env)
{
- env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
- env->CP0_Compare = 0;
- cpu_mips_store_count(env, 1);
+ /* If we're in KVM mode, don't start the periodic timer, that is handled in kernel */
+ if (!kvm_enabled()) {
+ env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
+ env->CP0_Compare = 0;
+ cpu_mips_store_count(env, 1);
+ }
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 04/12] KVM/MIPS: Do not start the periodic timer in KVM mode. Compare/Count timer interrupts are handled in-kernel.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/mips_timer.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 83c400c..0c86a3b 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -19,11 +19,13 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-
#include "hw.h"
#include "mips_cpudevs.h"
#include "qemu/timer.h"
+#include "sysemu/kvm.h"
+
+
#define TIMER_FREQ 100 * 1000 * 1000
/* XXX: do not use a global */
@@ -141,7 +143,10 @@ static void mips_timer_cb (void *opaque)
void cpu_mips_clock_init (CPUMIPSState *env)
{
- env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
- env->CP0_Compare = 0;
- cpu_mips_store_count(env, 1);
+ /* If we're in KVM mode, don't start the periodic timer, that is handled in kernel */
+ if (!kvm_enabled()) {
+ env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
+ env->CP0_Compare = 0;
+ cpu_mips_store_count(env, 1);
+ }
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 05/12] KVM/MIPS: In KVM mode, inject IRQ2 (I/O) interupts via ioctls(). COP0 emulation is in-kernel
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
hw/mips_int.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/mips_int.c b/hw/mips_int.c
index 6423fd0..6c655af 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -23,6 +23,8 @@
#include "hw.h"
#include "mips_cpudevs.h"
#include "cpu.h"
+#include "sysemu/kvm.h"
+#include "kvm_mips.h"
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
@@ -33,8 +35,21 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled() && irq == 2) {
+ kvm_mips_set_interrupt (env, irq, level);
+ }
+#endif
+
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled() && irq == 2) {
+ kvm_mips_set_interrupt (env, irq, level);
+ }
+#endif
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 05/12] KVM/MIPS: In KVM mode, inject IRQ2 (I/O) interupts via ioctls(). COP0 emulation is in-kernel
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
hw/mips_int.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/mips_int.c b/hw/mips_int.c
index 6423fd0..6c655af 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -23,6 +23,8 @@
#include "hw.h"
#include "mips_cpudevs.h"
#include "cpu.h"
+#include "sysemu/kvm.h"
+#include "kvm_mips.h"
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
@@ -33,8 +35,21 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled() && irq == 2) {
+ kvm_mips_set_interrupt (env, irq, level);
+ }
+#endif
+
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
+
+#ifdef CONFIG_KVM
+ if (kvm_enabled() && irq == 2) {
+ kvm_mips_set_interrupt (env, irq, level);
+ }
+#endif
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 06/12] KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest Physical addresses.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
In trap and emulate mode both the guest kernel and guest userspace execute in UM:
Guest User address space: 0x00000000 -> 0x40000000
Guest Kernel Unmapped: 0x40000000 -> 0x60000000
Guest Kernel Mapped: 0x60000000 -> 0x80000000
---
hw/mips_addr.c | 14 ++++++++++++++
hw/mips_cpudevs.h | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/hw/mips_addr.c b/hw/mips_addr.c
index aa1c7d8..c24d2d9 100644
--- a/hw/mips_addr.c
+++ b/hw/mips_addr.c
@@ -22,13 +22,27 @@
#include "hw.h"
#include "mips_cpudevs.h"
+#include "sysemu/kvm.h"
+
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
{
return addr & 0x7fffffffll;
}
+
+uint64_t cpu_mips_kvm_um_kseg0_to_phys(void *opaque, uint64_t addr)
+{
+ return addr & 0x3fffffffll;
+}
+
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr)
{
return addr | ~0x7fffffffll;
}
+
+
+uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
+{
+ return addr | 0x40000000ll;
+}
diff --git a/hw/mips_cpudevs.h b/hw/mips_cpudevs.h
index 6bea24b..9e5af37 100644
--- a/hw/mips_cpudevs.h
+++ b/hw/mips_cpudevs.h
@@ -6,6 +6,10 @@
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kvm_um_kseg0_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+
+
/* mips_int.c */
void cpu_mips_irq_init_cpu(CPUMIPSState *env);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 06/12] KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest Physical addresses.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
In trap and emulate mode both the guest kernel and guest userspace execute in UM:
Guest User address space: 0x00000000 -> 0x40000000
Guest Kernel Unmapped: 0x40000000 -> 0x60000000
Guest Kernel Mapped: 0x60000000 -> 0x80000000
---
hw/mips_addr.c | 14 ++++++++++++++
hw/mips_cpudevs.h | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/hw/mips_addr.c b/hw/mips_addr.c
index aa1c7d8..c24d2d9 100644
--- a/hw/mips_addr.c
+++ b/hw/mips_addr.c
@@ -22,13 +22,27 @@
#include "hw.h"
#include "mips_cpudevs.h"
+#include "sysemu/kvm.h"
+
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
{
return addr & 0x7fffffffll;
}
+
+uint64_t cpu_mips_kvm_um_kseg0_to_phys(void *opaque, uint64_t addr)
+{
+ return addr & 0x3fffffffll;
+}
+
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr)
{
return addr | ~0x7fffffffll;
}
+
+
+uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
+{
+ return addr | 0x40000000ll;
+}
diff --git a/hw/mips_cpudevs.h b/hw/mips_cpudevs.h
index 6bea24b..9e5af37 100644
--- a/hw/mips_cpudevs.h
+++ b/hw/mips_cpudevs.h
@@ -6,6 +6,10 @@
uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kvm_um_kseg0_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+
+
/* mips_int.c */
void cpu_mips_irq_init_cpu(CPUMIPSState *env);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 07/12] KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
| 94 +++++++++++++++++++++++++++++++++++++++
| 10 +++++
2 files changed, 104 insertions(+)
create mode 100644 linux-headers/asm-mips/kvm.h
create mode 100644 linux-headers/asm-mips/kvm_para.h
--git a/linux-headers/asm-mips/kvm.h b/linux-headers/asm-mips/kvm.h
new file mode 100644
index 0000000..6d37e5c
--- /dev/null
+++ b/linux-headers/asm-mips/kvm.h
@@ -0,0 +1,94 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
+
+#ifndef __LINUX_KVM_MIPS_H
+#define __LINUX_KVM_MIPS_H
+
+#include <linux/types.h>
+
+#define __KVM_MIPS
+
+#define N_MIPS_COPROC_REGS 32
+#define N_MIPS_COPROC_SEL 8
+
+/*
+ * Coprocessor 0 register names
+ */
+#define MIPS_CP0_TLB_INDEX 0
+#define MIPS_CP0_TLB_RANDOM 1
+#define MIPS_CP0_TLB_LOW 2
+#define MIPS_CP0_TLB_LO0 2
+#define MIPS_CP0_TLB_LO1 3
+#define MIPS_CP0_TLB_CONTEXT 4
+#define MIPS_CP0_TLB_PG_MASK 5
+#define MIPS_CP0_TLB_WIRED 6
+#define MIPS_CP0_HWRENA 7
+#define MIPS_CP0_BAD_VADDR 8
+#define MIPS_CP0_COUNT 9
+#define MIPS_CP0_TLB_HI 10
+#define MIPS_CP0_COMPARE 11
+#define MIPS_CP0_STATUS 12
+#define MIPS_CP0_CAUSE 13
+#define MIPS_CP0_EXC_PC 14
+#define MIPS_CP0_PRID 15
+#define MIPS_CP0_CONFIG 16
+#define MIPS_CP0_LLADDR 17
+#define MIPS_CP0_WATCH_LO 18
+#define MIPS_CP0_WATCH_HI 19
+#define MIPS_CP0_TLB_XCONTEXT 20
+#define MIPS_CP0_ECC 26
+#define MIPS_CP0_CACHE_ERR 27
+#define MIPS_CP0_TAG_LO 28
+#define MIPS_CP0_TAG_HI 29
+#define MIPS_CP0_ERROR_PC 30
+#define MIPS_CP0_DEBUG 23
+#define MIPS_CP0_DEPC 24
+#define MIPS_CP0_PERFCNT 25
+#define MIPS_CP0_ERRCTL 26
+#define MIPS_CP0_DATA_LO 28
+#define MIPS_CP0_DATA_HI 29
+#define MIPS_CP0_DESAVE 31
+
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+ __u32 gprs[32];
+ __u32 hi;
+ __u32 lo;
+ __u32 pc;
+
+ ulong cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+struct kvm_mips_interrupt {
+ /* in */
+ __u32 cpu;
+ __u32 irq;
+};
+
+#endif /* __LINUX_KVM_MIPS_H */
--git a/linux-headers/asm-mips/kvm_para.h b/linux-headers/asm-mips/kvm_para.h
new file mode 100644
index 0000000..d1058b4
--- /dev/null
+++ b/linux-headers/asm-mips/kvm_para.h
@@ -0,0 +1,10 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
+
+
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 07/12] KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
| 94 +++++++++++++++++++++++++++++++++++++++
| 10 +++++
2 files changed, 104 insertions(+)
create mode 100644 linux-headers/asm-mips/kvm.h
create mode 100644 linux-headers/asm-mips/kvm_para.h
--git a/linux-headers/asm-mips/kvm.h b/linux-headers/asm-mips/kvm.h
new file mode 100644
index 0000000..6d37e5c
--- /dev/null
+++ b/linux-headers/asm-mips/kvm.h
@@ -0,0 +1,94 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
+
+#ifndef __LINUX_KVM_MIPS_H
+#define __LINUX_KVM_MIPS_H
+
+#include <linux/types.h>
+
+#define __KVM_MIPS
+
+#define N_MIPS_COPROC_REGS 32
+#define N_MIPS_COPROC_SEL 8
+
+/*
+ * Coprocessor 0 register names
+ */
+#define MIPS_CP0_TLB_INDEX 0
+#define MIPS_CP0_TLB_RANDOM 1
+#define MIPS_CP0_TLB_LOW 2
+#define MIPS_CP0_TLB_LO0 2
+#define MIPS_CP0_TLB_LO1 3
+#define MIPS_CP0_TLB_CONTEXT 4
+#define MIPS_CP0_TLB_PG_MASK 5
+#define MIPS_CP0_TLB_WIRED 6
+#define MIPS_CP0_HWRENA 7
+#define MIPS_CP0_BAD_VADDR 8
+#define MIPS_CP0_COUNT 9
+#define MIPS_CP0_TLB_HI 10
+#define MIPS_CP0_COMPARE 11
+#define MIPS_CP0_STATUS 12
+#define MIPS_CP0_CAUSE 13
+#define MIPS_CP0_EXC_PC 14
+#define MIPS_CP0_PRID 15
+#define MIPS_CP0_CONFIG 16
+#define MIPS_CP0_LLADDR 17
+#define MIPS_CP0_WATCH_LO 18
+#define MIPS_CP0_WATCH_HI 19
+#define MIPS_CP0_TLB_XCONTEXT 20
+#define MIPS_CP0_ECC 26
+#define MIPS_CP0_CACHE_ERR 27
+#define MIPS_CP0_TAG_LO 28
+#define MIPS_CP0_TAG_HI 29
+#define MIPS_CP0_ERROR_PC 30
+#define MIPS_CP0_DEBUG 23
+#define MIPS_CP0_DEPC 24
+#define MIPS_CP0_PERFCNT 25
+#define MIPS_CP0_ERRCTL 26
+#define MIPS_CP0_DATA_LO 28
+#define MIPS_CP0_DATA_HI 29
+#define MIPS_CP0_DESAVE 31
+
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+ __u32 gprs[32];
+ __u32 hi;
+ __u32 lo;
+ __u32 pc;
+
+ ulong cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+struct kvm_mips_interrupt {
+ /* in */
+ __u32 cpu;
+ __u32 irq;
+};
+
+#endif /* __LINUX_KVM_MIPS_H */
--git a/linux-headers/asm-mips/kvm_para.h b/linux-headers/asm-mips/kvm_para.h
new file mode 100644
index 0000000..d1058b4
--- /dev/null
+++ b/linux-headers/asm-mips/kvm_para.h
@@ -0,0 +1,10 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
+
+
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
configure | 17 +++++++++++++++--
hw/mips/Makefile.objs | 2 +-
target-mips/Makefile.objs | 1 +
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/configure b/configure
index bf5970f..5447661 100755
--- a/configure
+++ b/configure
@@ -1370,7 +1370,12 @@ case "$cpu" in
bigendian=yes
fi
;;
- hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
+ mips|mips64)
+ if check_define __MIPSEB__; then
+ bigendian=yes
+ fi
+ ;;
+ hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
bigendian=yes
;;
esac
@@ -3844,6 +3849,9 @@ if test "$linux" = "yes" ; then
# For most CPUs the kernel architecture name and QEMU CPU name match.
linux_arch="$cpu"
;;
+ mips|mips64)
+ symlink "$source_path/linux-headers/asm-mips" linux-headers/asm
+ ;;
esac
# For non-KVM architectures we will not have asm headers
if [ -e "$source_path/linux-headers/asm-$linux_arch" ]; then
@@ -4074,7 +4082,7 @@ case "$target_arch2" in
echo "CONFIG_NO_XEN=y" >> $config_target_mak
esac
case "$target_arch2" in
- i386|x86_64|ppcemb|ppc|ppc64|s390x)
+ i386|x86_64|ppcemb|ppc|ppc64|s390x|mipsel|mips)
# Make sure the target and host cpus are compatible
if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \
\( "$target_arch2" = "$cpu" -o \
@@ -4082,6 +4090,8 @@ case "$target_arch2" in
\( "$target_arch2" = "ppc64" -a "$cpu" = "ppc" \) -o \
\( "$target_arch2" = "ppc" -a "$cpu" = "ppc64" \) -o \
\( "$target_arch2" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
+ \( "$target_arch2" = "mipsel" -a "$cpu" = "mips" \) -o \
+ \( "$target_arch2" = "mips" -a "$cpu" = "mips" \) -o \
\( "$target_arch2" = "x86_64" -a "$cpu" = "i386" \) -o \
\( "$target_arch2" = "i386" -a "$cpu" = "x86_64" \) \) ; then
echo "CONFIG_KVM=y" >> $config_target_mak
@@ -4285,6 +4295,9 @@ if test "$target_linux_user" = "yes" -o "$target_bsd_user" = "yes" ; then
*)
ldflags="$linker_script $ldflags"
;;
+ mips|mipsel|mipseb|mips64)
+ symlink $source_path/linux-headers/asm-mips linux-headers/asm
+ ;;
esac
fi
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 29a5d0d..c013bac 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -1,6 +1,6 @@
obj-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-y += mips_addr.o mips_timer.o mips_int.o
-obj-y += gt64xxx.o mc146818rtc.o
+obj-y += gt64xxx.o mc146818rtc.o mips_gic.o
obj-$(CONFIG_FULONG) += bonito.o vt82c686.o mips_fulong2e.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs
index 119c816..1956190 100644
--- a/target-mips/Makefile.objs
+++ b/target-mips/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_KVM) += kvm.o
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
configure | 17 +++++++++++++++--
hw/mips/Makefile.objs | 2 +-
target-mips/Makefile.objs | 1 +
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/configure b/configure
index bf5970f..5447661 100755
--- a/configure
+++ b/configure
@@ -1370,7 +1370,12 @@ case "$cpu" in
bigendian=yes
fi
;;
- hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
+ mips|mips64)
+ if check_define __MIPSEB__; then
+ bigendian=yes
+ fi
+ ;;
+ hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
bigendian=yes
;;
esac
@@ -3844,6 +3849,9 @@ if test "$linux" = "yes" ; then
# For most CPUs the kernel architecture name and QEMU CPU name match.
linux_arch="$cpu"
;;
+ mips|mips64)
+ symlink "$source_path/linux-headers/asm-mips" linux-headers/asm
+ ;;
esac
# For non-KVM architectures we will not have asm headers
if [ -e "$source_path/linux-headers/asm-$linux_arch" ]; then
@@ -4074,7 +4082,7 @@ case "$target_arch2" in
echo "CONFIG_NO_XEN=y" >> $config_target_mak
esac
case "$target_arch2" in
- i386|x86_64|ppcemb|ppc|ppc64|s390x)
+ i386|x86_64|ppcemb|ppc|ppc64|s390x|mipsel|mips)
# Make sure the target and host cpus are compatible
if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \
\( "$target_arch2" = "$cpu" -o \
@@ -4082,6 +4090,8 @@ case "$target_arch2" in
\( "$target_arch2" = "ppc64" -a "$cpu" = "ppc" \) -o \
\( "$target_arch2" = "ppc" -a "$cpu" = "ppc64" \) -o \
\( "$target_arch2" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
+ \( "$target_arch2" = "mipsel" -a "$cpu" = "mips" \) -o \
+ \( "$target_arch2" = "mips" -a "$cpu" = "mips" \) -o \
\( "$target_arch2" = "x86_64" -a "$cpu" = "i386" \) -o \
\( "$target_arch2" = "i386" -a "$cpu" = "x86_64" \) \) ; then
echo "CONFIG_KVM=y" >> $config_target_mak
@@ -4285,6 +4295,9 @@ if test "$target_linux_user" = "yes" -o "$target_bsd_user" = "yes" ; then
*)
ldflags="$linker_script $ldflags"
;;
+ mips|mipsel|mipseb|mips64)
+ symlink $source_path/linux-headers/asm-mips linux-headers/asm
+ ;;
esac
fi
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 29a5d0d..c013bac 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -1,6 +1,6 @@
obj-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-y += mips_addr.o mips_timer.o mips_int.o
-obj-y += gt64xxx.o mc146818rtc.o
+obj-y += gt64xxx.o mc146818rtc.o mips_gic.o
obj-$(CONFIG_FULONG) += bonito.o vt82c686.o mips_fulong2e.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs
index 119c816..1956190 100644
--- a/target-mips/Makefile.objs
+++ b/target-mips/Makefile.objs
@@ -1,2 +1,3 @@
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_KVM) += kvm.o
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 09/12] KVM/MIPS: set sigmask length to 16 for MIPS targets.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
kvm-all.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 4decfdc..2ac9e88 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1966,7 +1966,12 @@ int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
sigmask = g_malloc(sizeof(*sigmask) + sizeof(*sigset));
+#ifdef TARGET_MIPS
+ /* seems to be 16 for MIPS */
+ sigmask->len = 16;
+#else
sigmask->len = 8;
+#endif
memcpy(sigmask->sigset, sigset, sizeof(*sigset));
r = kvm_vcpu_ioctl(cpu, KVM_SET_SIGNAL_MASK, sigmask);
g_free(sigmask);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 09/12] KVM/MIPS: set sigmask length to 16 for MIPS targets.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
kvm-all.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 4decfdc..2ac9e88 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1966,7 +1966,12 @@ int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
sigmask = g_malloc(sizeof(*sigmask) + sizeof(*sigset));
+#ifdef TARGET_MIPS
+ /* seems to be 16 for MIPS */
+ sigmask->len = 16;
+#else
sigmask->len = 8;
+#endif
memcpy(sigmask->sigset, sigset, sizeof(*sigset));
r = kvm_vcpu_ioctl(cpu, KVM_SET_SIGNAL_MASK, sigmask);
g_free(sigmask);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 10/12] KVM/MIPS: Set page size to 16K in KVM mode.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
target-mips/mips-defs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..473ddf8 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -5,7 +5,12 @@
//#define USE_HOST_FLOAT_REGS
/* Real pages are variable size... */
+#ifdef CONFIG_KVM
+/* For KVM/MIPS the minimum page size is 16K due to cache aliasing issues */
+#define TARGET_PAGE_BITS 14
+#else
#define TARGET_PAGE_BITS 12
+#endif
#define MIPS_TLB_MAX 128
#if defined(TARGET_MIPS64)
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 10/12] KVM/MIPS: Set page size to 16K in KVM mode.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
target-mips/mips-defs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..473ddf8 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -5,7 +5,12 @@
//#define USE_HOST_FLOAT_REGS
/* Real pages are variable size... */
+#ifdef CONFIG_KVM
+/* For KVM/MIPS the minimum page size is 16K due to cache aliasing issues */
+#define TARGET_PAGE_BITS 14
+#else
#define TARGET_PAGE_BITS 12
+#endif
#define MIPS_TLB_MAX 128
#if defined(TARGET_MIPS64)
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
---
target-mips/kvm.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++++
target-mips/kvm_mips.h | 21 ++++
2 files changed, 313 insertions(+)
create mode 100644 target-mips/kvm.c
create mode 100644 target-mips/kvm_mips.h
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
new file mode 100644
index 0000000..7c01c76
--- /dev/null
+++ b/target-mips/kvm.c
@@ -0,0 +1,292 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * KVM/MIPS: MIPS specific KVM APIs
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "cpu.h"
+#include "sysemu/cpus.h"
+#include "kvm_mips.h"
+
+//#define DEBUG_KVM
+
+#ifdef DEBUG_KVM
+#define dprintf(fmt, ...) \
+ do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
+#else
+#define dprintf(fmt, ...) \
+ do { } while (0)
+#endif
+
+extern int64_t g_kernel_entry;
+
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_LAST_INFO
+};
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+ return cpu->cpu_index;
+}
+
+int kvm_arch_init(KVMState *s)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+int kvm_arch_init_vcpu(CPUState *env)
+{
+ int ret = 0;
+ dprintf("%s\n", __func__);
+ return ret;
+}
+
+void kvm_arch_reset_vcpu(CPUState *env)
+{
+ dprintf("%s\n", __func__);
+#ifdef notyet
+ int ret;
+
+ ret = kvm_vcpu_ioctl(env, KVM_NMI);
+ if (ret < 0) {
+ fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
+ strerror(-ret));
+ }
+#endif
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ struct kvm_regs regs;
+ int ret;
+ int i;
+
+ /* Get the current register set as KVM seems it */
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
+ if (ret < 0)
+ return ret;
+
+ /* Now set the registers based on QEMU's view of things */
+ for (i = 0;i < 32; i++)
+ regs.gprs[i] = env->active_tc.gpr[i];
+
+ regs.hi = env->active_tc.HI[0];
+ regs.lo = env->active_tc.LO[0];
+ regs.pc = env->active_tc.PC;
+
+ regs.cp0reg[MIPS_CP0_TLB_INDEX][0] = env->CP0_Index;
+ regs.cp0reg[MIPS_CP0_TLB_CONTEXT][0] = env->CP0_Context;
+ regs.cp0reg[MIPS_CP0_BAD_VADDR][0] = env->CP0_BadVAddr;
+ regs.cp0reg[MIPS_CP0_TLB_HI][0] = env->CP0_EntryHi;
+ regs.cp0reg[MIPS_CP0_EXC_PC][0] = env->CP0_EPC;
+
+ regs.cp0reg[MIPS_CP0_STATUS][0] = env->CP0_Status;
+ regs.cp0reg[MIPS_CP0_CAUSE][0] = env->CP0_Cause;
+ regs.cp0reg[MIPS_CP0_TLB_PG_MASK][0] = env->CP0_PageMask;
+ regs.cp0reg[MIPS_CP0_TLB_WIRED][0] = env->CP0_Wired;
+
+ regs.cp0reg[MIPS_CP0_ERROR_PC][0] = env->CP0_ErrorEPC;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
+
+ if (ret < 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ int ret = 0;
+ struct kvm_regs regs;
+ int i;
+
+ /* Get the current register set as KVM seems it */
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
+
+ if (ret < 0)
+ return ret;
+
+ for (i = 0;i < 32; i++)
+ env->active_tc.gpr[i] = regs.gprs[i];
+
+ env->active_tc.HI[0] = regs.hi;
+ env->active_tc.LO[0] = regs.lo;
+ env->active_tc.PC = regs.pc;
+
+ env->CP0_Index = regs.cp0reg[MIPS_CP0_TLB_INDEX][0];
+ env->CP0_Context = regs.cp0reg[MIPS_CP0_TLB_CONTEXT][0];
+ env->CP0_BadVAddr = regs.cp0reg[MIPS_CP0_BAD_VADDR][0];
+ env->CP0_EntryHi = regs.cp0reg[MIPS_CP0_TLB_HI][0];
+ env->CP0_EPC = regs.cp0reg[MIPS_CP0_EXC_PC][0];
+
+ env->CP0_Status = regs.cp0reg[MIPS_CP0_STATUS][0];
+ env->CP0_Cause = regs.cp0reg[MIPS_CP0_CAUSE][0];
+ env->CP0_PageMask = regs.cp0reg[MIPS_CP0_TLB_PG_MASK][0];
+ env->CP0_Wired = regs.cp0reg[MIPS_CP0_TLB_WIRED][0];
+ env->CP0_ErrorEPC= regs.cp0reg[MIPS_CP0_ERROR_PC][0];
+
+ return ret;
+}
+
+int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+static inline int cpu_mips_io_interrupts_pending(CPUArchState *env)
+{
+ dprintf("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
+ return(env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)));
+}
+
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ int r;
+ struct kvm_mips_interrupt intr;
+
+ if (env->interrupt_request & CPU_INTERRUPT_HARD &&
+ cpu_mips_io_interrupts_pending(env))
+ {
+ intr.cpu = -1;
+ intr.irq = 2;
+ r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+ if (r < 0)
+ printf("cpu %d fail inject %x\n", cs->cpu_index, intr.irq);
+ }
+ /* If we have an interrupt but the guest is not ready to receive an
+ * interrupt, request an interrupt window exit. This will
+ * cause a return to userspace as soon as the guest is ready to
+ * receive interrupts.
+ */
+ if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ run->request_interrupt_window = 1;
+ } else {
+ run->request_interrupt_window = 0;
+ }
+}
+
+void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
+{
+ dprintf("%s\n", __func__);
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ dprintf("%s\n", __func__);
+ return env->halted;
+}
+
+int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
+{
+ int ret;
+
+ printf("kvm_arch_handle_exit()\n");
+ switch (run->exit_reason) {
+ default:
+ fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *env)
+{
+ dprintf("%s\n", __func__);
+ return true;
+}
+
+int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+{
+ dprintf("%s\n", __func__);
+ return 1;
+}
+
+int kvm_arch_on_sigbus(int code, void *addr)
+{
+ dprintf("%s\n", __func__);
+ return 1;
+}
+
+int kvm_mips_set_interrupt(CPUMIPSState *env, int irq, int level)
+{
+ CPUState *cs = ENV_GET_CPU(env);
+ struct kvm_mips_interrupt intr;
+
+ if (!kvm_enabled()) {
+ return 0;
+ }
+
+ intr.cpu = -1;
+
+ if (level)
+ intr.irq = irq;
+ else
+ intr.irq = -irq;
+
+ kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+
+ return 0;
+}
+
+int kvm_mips_set_ipi_interrupt(CPUArchState *env, int irq, int level)
+{
+ CPUState *cs = ENV_GET_CPU(cpu_single_env);
+ struct kvm_mips_interrupt intr;
+
+ if (!kvm_enabled()) {
+ return 0;
+ }
+
+ intr.cpu = cs->cpu_index;
+
+ if (level)
+ intr.irq = irq;
+ else
+ intr.irq = -irq;
+
+ dprintf("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
+
+ kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+
+ return 0;
+}
+
+
diff --git a/target-mips/kvm_mips.h b/target-mips/kvm_mips.h
new file mode 100644
index 0000000..20c3f8c
--- /dev/null
+++ b/target-mips/kvm_mips.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * KVM/MIPS: MIPS specific KVM APIs
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#ifndef __KVM_MIPS_H__
+#define __KVM_MIPS_H__
+
+
+int kvm_mips_set_interrupt(CPUMIPSState *env, int irq, int level);
+
+int kvm_mips_set_ipi_interrupt(CPUArchState *env, int irq, int level);
+
+
+#endif /* __KVM_MIPS_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
---
target-mips/kvm.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++++
target-mips/kvm_mips.h | 21 ++++
2 files changed, 313 insertions(+)
create mode 100644 target-mips/kvm.c
create mode 100644 target-mips/kvm_mips.h
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
new file mode 100644
index 0000000..7c01c76
--- /dev/null
+++ b/target-mips/kvm.c
@@ -0,0 +1,292 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * KVM/MIPS: MIPS specific KVM APIs
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "cpu.h"
+#include "sysemu/cpus.h"
+#include "kvm_mips.h"
+
+//#define DEBUG_KVM
+
+#ifdef DEBUG_KVM
+#define dprintf(fmt, ...) \
+ do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
+#else
+#define dprintf(fmt, ...) \
+ do { } while (0)
+#endif
+
+extern int64_t g_kernel_entry;
+
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_LAST_INFO
+};
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+ return cpu->cpu_index;
+}
+
+int kvm_arch_init(KVMState *s)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+int kvm_arch_init_vcpu(CPUState *env)
+{
+ int ret = 0;
+ dprintf("%s\n", __func__);
+ return ret;
+}
+
+void kvm_arch_reset_vcpu(CPUState *env)
+{
+ dprintf("%s\n", __func__);
+#ifdef notyet
+ int ret;
+
+ ret = kvm_vcpu_ioctl(env, KVM_NMI);
+ if (ret < 0) {
+ fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
+ strerror(-ret));
+ }
+#endif
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ struct kvm_regs regs;
+ int ret;
+ int i;
+
+ /* Get the current register set as KVM seems it */
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
+ if (ret < 0)
+ return ret;
+
+ /* Now set the registers based on QEMU's view of things */
+ for (i = 0;i < 32; i++)
+ regs.gprs[i] = env->active_tc.gpr[i];
+
+ regs.hi = env->active_tc.HI[0];
+ regs.lo = env->active_tc.LO[0];
+ regs.pc = env->active_tc.PC;
+
+ regs.cp0reg[MIPS_CP0_TLB_INDEX][0] = env->CP0_Index;
+ regs.cp0reg[MIPS_CP0_TLB_CONTEXT][0] = env->CP0_Context;
+ regs.cp0reg[MIPS_CP0_BAD_VADDR][0] = env->CP0_BadVAddr;
+ regs.cp0reg[MIPS_CP0_TLB_HI][0] = env->CP0_EntryHi;
+ regs.cp0reg[MIPS_CP0_EXC_PC][0] = env->CP0_EPC;
+
+ regs.cp0reg[MIPS_CP0_STATUS][0] = env->CP0_Status;
+ regs.cp0reg[MIPS_CP0_CAUSE][0] = env->CP0_Cause;
+ regs.cp0reg[MIPS_CP0_TLB_PG_MASK][0] = env->CP0_PageMask;
+ regs.cp0reg[MIPS_CP0_TLB_WIRED][0] = env->CP0_Wired;
+
+ regs.cp0reg[MIPS_CP0_ERROR_PC][0] = env->CP0_ErrorEPC;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
+
+ if (ret < 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ int ret = 0;
+ struct kvm_regs regs;
+ int i;
+
+ /* Get the current register set as KVM seems it */
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
+
+ if (ret < 0)
+ return ret;
+
+ for (i = 0;i < 32; i++)
+ env->active_tc.gpr[i] = regs.gprs[i];
+
+ env->active_tc.HI[0] = regs.hi;
+ env->active_tc.LO[0] = regs.lo;
+ env->active_tc.PC = regs.pc;
+
+ env->CP0_Index = regs.cp0reg[MIPS_CP0_TLB_INDEX][0];
+ env->CP0_Context = regs.cp0reg[MIPS_CP0_TLB_CONTEXT][0];
+ env->CP0_BadVAddr = regs.cp0reg[MIPS_CP0_BAD_VADDR][0];
+ env->CP0_EntryHi = regs.cp0reg[MIPS_CP0_TLB_HI][0];
+ env->CP0_EPC = regs.cp0reg[MIPS_CP0_EXC_PC][0];
+
+ env->CP0_Status = regs.cp0reg[MIPS_CP0_STATUS][0];
+ env->CP0_Cause = regs.cp0reg[MIPS_CP0_CAUSE][0];
+ env->CP0_PageMask = regs.cp0reg[MIPS_CP0_TLB_PG_MASK][0];
+ env->CP0_Wired = regs.cp0reg[MIPS_CP0_TLB_WIRED][0];
+ env->CP0_ErrorEPC= regs.cp0reg[MIPS_CP0_ERROR_PC][0];
+
+ return ret;
+}
+
+int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+{
+ dprintf("%s\n", __func__);
+ return 0;
+}
+
+static inline int cpu_mips_io_interrupts_pending(CPUArchState *env)
+{
+ dprintf("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
+ return(env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)));
+}
+
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ int r;
+ struct kvm_mips_interrupt intr;
+
+ if (env->interrupt_request & CPU_INTERRUPT_HARD &&
+ cpu_mips_io_interrupts_pending(env))
+ {
+ intr.cpu = -1;
+ intr.irq = 2;
+ r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+ if (r < 0)
+ printf("cpu %d fail inject %x\n", cs->cpu_index, intr.irq);
+ }
+ /* If we have an interrupt but the guest is not ready to receive an
+ * interrupt, request an interrupt window exit. This will
+ * cause a return to userspace as soon as the guest is ready to
+ * receive interrupts.
+ */
+ if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ run->request_interrupt_window = 1;
+ } else {
+ run->request_interrupt_window = 0;
+ }
+}
+
+void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
+{
+ dprintf("%s\n", __func__);
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ dprintf("%s\n", __func__);
+ return env->halted;
+}
+
+int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
+{
+ int ret;
+
+ printf("kvm_arch_handle_exit()\n");
+ switch (run->exit_reason) {
+ default:
+ fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *env)
+{
+ dprintf("%s\n", __func__);
+ return true;
+}
+
+int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+{
+ dprintf("%s\n", __func__);
+ return 1;
+}
+
+int kvm_arch_on_sigbus(int code, void *addr)
+{
+ dprintf("%s\n", __func__);
+ return 1;
+}
+
+int kvm_mips_set_interrupt(CPUMIPSState *env, int irq, int level)
+{
+ CPUState *cs = ENV_GET_CPU(env);
+ struct kvm_mips_interrupt intr;
+
+ if (!kvm_enabled()) {
+ return 0;
+ }
+
+ intr.cpu = -1;
+
+ if (level)
+ intr.irq = irq;
+ else
+ intr.irq = -irq;
+
+ kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+
+ return 0;
+}
+
+int kvm_mips_set_ipi_interrupt(CPUArchState *env, int irq, int level)
+{
+ CPUState *cs = ENV_GET_CPU(cpu_single_env);
+ struct kvm_mips_interrupt intr;
+
+ if (!kvm_enabled()) {
+ return 0;
+ }
+
+ intr.cpu = cs->cpu_index;
+
+ if (level)
+ intr.irq = irq;
+ else
+ intr.irq = -irq;
+
+ dprintf("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
+
+ kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+
+ return 0;
+}
+
+
diff --git a/target-mips/kvm_mips.h b/target-mips/kvm_mips.h
new file mode 100644
index 0000000..20c3f8c
--- /dev/null
+++ b/target-mips/kvm_mips.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * KVM/MIPS: MIPS specific KVM APIs
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#ifndef __KVM_MIPS_H__
+#define __KVM_MIPS_H__
+
+
+int kvm_mips_set_interrupt(CPUMIPSState *env, int irq, int level);
+
+int kvm_mips_set_ipi_interrupt(CPUArchState *env, int irq, int level);
+
+
+#endif /* __KVM_MIPS_H__ */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel][PATCH 12/12] KVM/MIPS: General KVM support and support for SMP Guests
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:18 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti, Sanjay Lal
- In KVM mode the bootrom is loaded and executed from the last 1MB of DRAM.
- Use the CPS bootrom from MIPS in KVM mode. This allows bootstrapping of multiple cores.
- Add suport for MIPS GIC emulation for SMP Guests.
---
hw/mips_malta.c | 192 +++++++++++++++++++++++++++++++++++++-------------------
1 file changed, 126 insertions(+), 66 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 2a150df..e04aa4a 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -48,6 +48,13 @@
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
#include "sysbus.h" /* SysBusDevice */
+#include "qemu/bitmap.h"
+#include "mips_gic.h"
+#include "sysemu/kvm.h"
+#include "linux/kvm.h"
+#include "kvm_mips.h"
+
+#include "mips_cps_bootcode.h"
//#define DEBUG_BOARD_INIT
@@ -514,27 +521,36 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
/* Small bootloader */
p = (uint32_t *)base;
- stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
- stl_raw(p++, 0x00000000); /* nop */
- /* YAMON service vector */
- stl_raw(base + 0x500, 0xbfc00580); /* start: */
- stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
- stl_raw(base + 0x520, 0xbfc00580); /* start: */
- stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
- stl_raw(base + 0x534, 0xbfc00808); /* print: */
- stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
- stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
- stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
- stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
- stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
- stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
- stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
- stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
+ if (kvm_enabled()) {
+ memcpy((void *)base, (void *)__boot_cps_data, sizeof(__boot_cps_data));
+ /* Second part of the bootloader */
+ p = (uint32_t *) (base + 0x100);
+ }
+ else {
+ stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
+ stl_raw(p++, 0x00000000); /* nop */
+
+ /* YAMON service vector */
+ stl_raw(base + 0x500, 0xbfc00580); /* start: */
+ stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
+ stl_raw(base + 0x520, 0xbfc00580); /* start: */
+ stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
+ stl_raw(base + 0x534, 0xbfc00808); /* print: */
+ stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
+ stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
+ stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
+ stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
+ stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
+ stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
+ stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
+ stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
+
+ p = (uint32_t *) (base + 0x580);
+ }
/* Second part of the bootloader */
- p = (uint32_t *) (base + 0x580);
stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
@@ -603,48 +619,49 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
stl_raw(p++, 0x00000000); /* nop */
/* YAMON subroutines */
- p = (uint32_t *) (base + 0x800);
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x24020000); /* li v0,0 */
- /* 808 YAMON print */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x10800005); /* beqz a0,834 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x08000205); /* j 814 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
- /* 0x83c YAMON print_count */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x00c06021); /* move t4,a2 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
- stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
- /* 0x870 */
- stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
- stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
- stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
- stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
-
+ if (!kvm_enabled()) {
+ p = (uint32_t *) (base + 0x800);
+ stl_raw(p++, 0x03e00008); /* jr ra */
+ stl_raw(p++, 0x24020000); /* li v0,0 */
+ /* 808 YAMON print */
+ stl_raw(p++, 0x03e06821); /* move t5,ra */
+ stl_raw(p++, 0x00805821); /* move t3,a0 */
+ stl_raw(p++, 0x00a05021); /* move t2,a1 */
+ stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_raw(p++, 0x10800005); /* beqz a0,834 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x0ff0021c); /* jal 870 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x08000205); /* j 814 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x01a00008); /* jr t5 */
+ stl_raw(p++, 0x01602021); /* move a0,t3 */
+ /* 0x83c YAMON print_count */
+ stl_raw(p++, 0x03e06821); /* move t5,ra */
+ stl_raw(p++, 0x00805821); /* move t3,a0 */
+ stl_raw(p++, 0x00a05021); /* move t2,a1 */
+ stl_raw(p++, 0x00c06021); /* move t4,a2 */
+ stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_raw(p++, 0x0ff0021c); /* jal 870 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
+ stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x01a00008); /* jr t5 */
+ stl_raw(p++, 0x01602021); /* move a0,t3 */
+ /* 0x870 */
+ stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
+ stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
+ stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
+ stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x03e00008); /* jr ra */
+ stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
+ }
}
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
@@ -670,7 +687,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
}
/* Kernel */
-static int64_t load_kernel (void)
+static int64_t load_kernel (CPUMIPSState *env)
{
int64_t kernel_entry, kernel_high;
long initrd_size;
@@ -679,6 +696,9 @@ static int64_t load_kernel (void)
uint32_t *prom_buf;
long prom_size;
int prom_index = 0;
+ uint64_t (*xlate_to_phys) (void *opaque, uint64_t addr);
+ uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
+
#ifdef TARGET_WORDS_BIGENDIAN
big_endian = 1;
@@ -686,7 +706,15 @@ static int64_t load_kernel (void)
big_endian = 0;
#endif
- if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
+ if (kvm_enabled()) {
+ xlate_to_phys = cpu_mips_kvm_um_kseg0_to_phys;
+ xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
+ } else {
+ xlate_to_phys = cpu_mips_kseg0_to_phys;
+ xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
+ }
+
+ if (load_elf(loaderparams.kernel_filename, xlate_to_phys, NULL,
(uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
big_endian, ELF_MACHINE, 1) < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
@@ -725,20 +753,24 @@ static int64_t load_kernel (void)
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
- cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
+ xlate_to_kseg0(NULL, initrd_offset), initrd_size,
loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
}
prom_set(prom_buf, prom_index++, "memsize");
- prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
+ if (kvm_enabled())
+ prom_set(prom_buf, prom_index++, "%i", (loaderparams.ram_size - 0x100000));
+ else
+ prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
+
prom_set(prom_buf, prom_index++, "modetty0");
prom_set(prom_buf, prom_index++, "38400n8r");
prom_set(prom_buf, prom_index++, NULL);
rom_add_blob_fixed("prom", prom_buf, prom_size,
- cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
+ xlate_to_phys(NULL, ENVP_ADDR));
return kernel_entry;
}
@@ -767,6 +799,23 @@ static void main_cpu_reset(void *opaque)
}
malta_mips_config(cpu);
+
+ if (kvm_enabled()) {
+
+ /* Start running @ the point where the bootrom configures the north bridge BARs */
+ env->active_tc.PC = 0x40000000 + ((loaderparams.ram_size - 0x100000));
+
+
+ /* a0 - number of kernel arguments
+ * a1 - 32-bit address of the kernel arguments table
+ * a2 - 32-bit address of the environment variables table
+ * a3 - RAM size in bytes
+ */
+ env->active_tc.gpr[4] = 0x2;
+ env->active_tc.gpr[5] = 0x80002000;
+ env->active_tc.gpr[6] = 0x80002008;
+ env->active_tc.gpr[7] = loaderparams.ram_size - 0x100000;
+ }
}
static void cpu_request_exit(void *opaque, int irq, int level)
@@ -776,6 +825,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
if (env && level) {
cpu_exit(env);
}
+
}
static
@@ -797,7 +847,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
ISABus *isa_bus;
MIPSCPU *cpu;
CPUMIPSState *env;
- qemu_irq *isa_irq;
+ qemu_irq *isa_irq, *gic_irq = NULL;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
i2c_bus *smbus;
@@ -889,8 +939,13 @@ void mips_malta_init(QEMUMachineInitArgs *args)
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
- kernel_entry = load_kernel();
+ kernel_entry = load_kernel(env);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
+ if (kvm_enabled()) {
+ /* Write the bootloader code @ the end of RAM, 1MB reserved */
+ printf("Writing bootloader to final 1MB of RAM\n");
+ write_bootloader(env, memory_region_get_ram_ptr(ram) + loaderparams.ram_size - 0x100000, kernel_entry);
+ }
} else {
/* Load firmware from flash. */
if (!dinfo) {
@@ -940,6 +995,11 @@ void mips_malta_init(QEMUMachineInitArgs *args)
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ /* GCR/GIC */
+ if (kvm_enabled() && smp_cpus > 1) {
+ gic_irq = gic_init(smp_cpus, env, system_memory);
+ }
+
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Qemu-devel] [PATCH 12/12] KVM/MIPS: General KVM support and support for SMP Guests
@ 2013-03-02 15:18 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-02 15:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Sanjay Lal, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
- In KVM mode the bootrom is loaded and executed from the last 1MB of DRAM.
- Use the CPS bootrom from MIPS in KVM mode. This allows bootstrapping of multiple cores.
- Add suport for MIPS GIC emulation for SMP Guests.
---
hw/mips_malta.c | 192 +++++++++++++++++++++++++++++++++++++-------------------
1 file changed, 126 insertions(+), 66 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 2a150df..e04aa4a 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -48,6 +48,13 @@
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
#include "sysbus.h" /* SysBusDevice */
+#include "qemu/bitmap.h"
+#include "mips_gic.h"
+#include "sysemu/kvm.h"
+#include "linux/kvm.h"
+#include "kvm_mips.h"
+
+#include "mips_cps_bootcode.h"
//#define DEBUG_BOARD_INIT
@@ -514,27 +521,36 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
/* Small bootloader */
p = (uint32_t *)base;
- stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
- stl_raw(p++, 0x00000000); /* nop */
- /* YAMON service vector */
- stl_raw(base + 0x500, 0xbfc00580); /* start: */
- stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
- stl_raw(base + 0x520, 0xbfc00580); /* start: */
- stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
- stl_raw(base + 0x534, 0xbfc00808); /* print: */
- stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
- stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
- stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
- stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
- stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
- stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
- stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
- stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
+ if (kvm_enabled()) {
+ memcpy((void *)base, (void *)__boot_cps_data, sizeof(__boot_cps_data));
+ /* Second part of the bootloader */
+ p = (uint32_t *) (base + 0x100);
+ }
+ else {
+ stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
+ stl_raw(p++, 0x00000000); /* nop */
+
+ /* YAMON service vector */
+ stl_raw(base + 0x500, 0xbfc00580); /* start: */
+ stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
+ stl_raw(base + 0x520, 0xbfc00580); /* start: */
+ stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
+ stl_raw(base + 0x534, 0xbfc00808); /* print: */
+ stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
+ stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
+ stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
+ stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
+ stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
+ stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
+ stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
+ stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
+
+ p = (uint32_t *) (base + 0x580);
+ }
/* Second part of the bootloader */
- p = (uint32_t *) (base + 0x580);
stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
@@ -603,48 +619,49 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
stl_raw(p++, 0x00000000); /* nop */
/* YAMON subroutines */
- p = (uint32_t *) (base + 0x800);
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0x24020000); /* li v0,0 */
- /* 808 YAMON print */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x10800005); /* beqz a0,834 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x08000205); /* j 814 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
- /* 0x83c YAMON print_count */
- stl_raw(p++, 0x03e06821); /* move t5,ra */
- stl_raw(p++, 0x00805821); /* move t3,a0 */
- stl_raw(p++, 0x00a05021); /* move t2,a1 */
- stl_raw(p++, 0x00c06021); /* move t4,a2 */
- stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
- stl_raw(p++, 0x0ff0021c); /* jal 870 */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
- stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
- stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x01a00008); /* jr t5 */
- stl_raw(p++, 0x01602021); /* move a0,t3 */
- /* 0x870 */
- stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
- stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
- stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
- stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
- stl_raw(p++, 0x00000000); /* nop */
- stl_raw(p++, 0x03e00008); /* jr ra */
- stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
-
+ if (!kvm_enabled()) {
+ p = (uint32_t *) (base + 0x800);
+ stl_raw(p++, 0x03e00008); /* jr ra */
+ stl_raw(p++, 0x24020000); /* li v0,0 */
+ /* 808 YAMON print */
+ stl_raw(p++, 0x03e06821); /* move t5,ra */
+ stl_raw(p++, 0x00805821); /* move t3,a0 */
+ stl_raw(p++, 0x00a05021); /* move t2,a1 */
+ stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_raw(p++, 0x10800005); /* beqz a0,834 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x0ff0021c); /* jal 870 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x08000205); /* j 814 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x01a00008); /* jr t5 */
+ stl_raw(p++, 0x01602021); /* move a0,t3 */
+ /* 0x83c YAMON print_count */
+ stl_raw(p++, 0x03e06821); /* move t5,ra */
+ stl_raw(p++, 0x00805821); /* move t3,a0 */
+ stl_raw(p++, 0x00a05021); /* move t2,a1 */
+ stl_raw(p++, 0x00c06021); /* move t4,a2 */
+ stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
+ stl_raw(p++, 0x0ff0021c); /* jal 870 */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
+ stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
+ stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x01a00008); /* jr t5 */
+ stl_raw(p++, 0x01602021); /* move a0,t3 */
+ /* 0x870 */
+ stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
+ stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
+ stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
+ stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
+ stl_raw(p++, 0x00000000); /* nop */
+ stl_raw(p++, 0x03e00008); /* jr ra */
+ stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
+ }
}
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
@@ -670,7 +687,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
}
/* Kernel */
-static int64_t load_kernel (void)
+static int64_t load_kernel (CPUMIPSState *env)
{
int64_t kernel_entry, kernel_high;
long initrd_size;
@@ -679,6 +696,9 @@ static int64_t load_kernel (void)
uint32_t *prom_buf;
long prom_size;
int prom_index = 0;
+ uint64_t (*xlate_to_phys) (void *opaque, uint64_t addr);
+ uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
+
#ifdef TARGET_WORDS_BIGENDIAN
big_endian = 1;
@@ -686,7 +706,15 @@ static int64_t load_kernel (void)
big_endian = 0;
#endif
- if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
+ if (kvm_enabled()) {
+ xlate_to_phys = cpu_mips_kvm_um_kseg0_to_phys;
+ xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
+ } else {
+ xlate_to_phys = cpu_mips_kseg0_to_phys;
+ xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
+ }
+
+ if (load_elf(loaderparams.kernel_filename, xlate_to_phys, NULL,
(uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
big_endian, ELF_MACHINE, 1) < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
@@ -725,20 +753,24 @@ static int64_t load_kernel (void)
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
- cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
+ xlate_to_kseg0(NULL, initrd_offset), initrd_size,
loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
}
prom_set(prom_buf, prom_index++, "memsize");
- prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
+ if (kvm_enabled())
+ prom_set(prom_buf, prom_index++, "%i", (loaderparams.ram_size - 0x100000));
+ else
+ prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
+
prom_set(prom_buf, prom_index++, "modetty0");
prom_set(prom_buf, prom_index++, "38400n8r");
prom_set(prom_buf, prom_index++, NULL);
rom_add_blob_fixed("prom", prom_buf, prom_size,
- cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
+ xlate_to_phys(NULL, ENVP_ADDR));
return kernel_entry;
}
@@ -767,6 +799,23 @@ static void main_cpu_reset(void *opaque)
}
malta_mips_config(cpu);
+
+ if (kvm_enabled()) {
+
+ /* Start running @ the point where the bootrom configures the north bridge BARs */
+ env->active_tc.PC = 0x40000000 + ((loaderparams.ram_size - 0x100000));
+
+
+ /* a0 - number of kernel arguments
+ * a1 - 32-bit address of the kernel arguments table
+ * a2 - 32-bit address of the environment variables table
+ * a3 - RAM size in bytes
+ */
+ env->active_tc.gpr[4] = 0x2;
+ env->active_tc.gpr[5] = 0x80002000;
+ env->active_tc.gpr[6] = 0x80002008;
+ env->active_tc.gpr[7] = loaderparams.ram_size - 0x100000;
+ }
}
static void cpu_request_exit(void *opaque, int irq, int level)
@@ -776,6 +825,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
if (env && level) {
cpu_exit(env);
}
+
}
static
@@ -797,7 +847,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
ISABus *isa_bus;
MIPSCPU *cpu;
CPUMIPSState *env;
- qemu_irq *isa_irq;
+ qemu_irq *isa_irq, *gic_irq = NULL;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
i2c_bus *smbus;
@@ -889,8 +939,13 @@ void mips_malta_init(QEMUMachineInitArgs *args)
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
- kernel_entry = load_kernel();
+ kernel_entry = load_kernel(env);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
+ if (kvm_enabled()) {
+ /* Write the bootloader code @ the end of RAM, 1MB reserved */
+ printf("Writing bootloader to final 1MB of RAM\n");
+ write_bootloader(env, memory_region_get_ram_ptr(ram) + loaderparams.ram_size - 0x100000, kernel_entry);
+ }
} else {
/* Load firmware from flash. */
if (!dinfo) {
@@ -940,6 +995,11 @@ void mips_malta_init(QEMUMachineInitArgs *args)
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ /* GCR/GIC */
+ if (kvm_enabled() && smp_cpus > 1) {
+ gic_irq = gic_init(smp_cpus, env, system_memory);
+ }
+
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
--
1.7.11.3
^ permalink raw reply related [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:27 ` Peter Maydell
-1 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:27 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
2013/3/2 Sanjay Lal <sanjayl@kymasys.com>:
> +static void gt64xxx_save(QEMUFile *f, void *opaque)
> +{
> + GT64120State *s = opaque;
> +
> + /* CPU Configuration */
> + qemu_put_be32s(f, &s->regs[GT_CPU]);
> + qemu_put_be32s(f, &s->regs[GT_MULTI]);
Definitely no new save/load functions like this in new code,
please. Use a VMState struct.
thanks
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
@ 2013-03-02 15:27 ` Peter Maydell
0 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:27 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
2013/3/2 Sanjay Lal <sanjayl@kymasys.com>:
> +static void gt64xxx_save(QEMUFile *f, void *opaque)
> +{
> + GT64120State *s = opaque;
> +
> + /* CPU Configuration */
> + qemu_put_be32s(f, &s->regs[GT_CPU]);
> + qemu_put_be32s(f, &s->regs[GT_MULTI]);
Definitely no new save/load functions like this in new code,
please. Use a VMState struct.
thanks
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:42 ` Peter Maydell
-1 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:42 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> ---
> configure | 17 +++++++++++++++--
> hw/mips/Makefile.objs | 2 +-
> target-mips/Makefile.objs | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/configure b/configure
> index bf5970f..5447661 100755
> --- a/configure
> +++ b/configure
> @@ -1370,7 +1370,12 @@ case "$cpu" in
> bigendian=yes
> fi
> ;;
> - hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
> + mips|mips64)
> + if check_define __MIPSEB__; then
> + bigendian=yes
> + fi
> + ;;
> + hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
> bigendian=yes
> ;;
> esac
> @@ -3844,6 +3849,9 @@ if test "$linux" = "yes" ; then
> # For most CPUs the kernel architecture name and QEMU CPU name match.
> linux_arch="$cpu"
> ;;
> + mips|mips64)
> + symlink "$source_path/linux-headers/asm-mips" linux-headers/asm
> + ;;
Above the default case, not below it, please. And just set linux_arch
like the other cases; don't do the symlink yourself.
> esac
> # For non-KVM architectures we will not have asm headers
> if [ -e "$source_path/linux-headers/asm-$linux_arch" ]; then
> @@ -4074,7 +4082,7 @@ case "$target_arch2" in
> echo "CONFIG_NO_XEN=y" >> $config_target_mak
> esac
> case "$target_arch2" in
> - i386|x86_64|ppcemb|ppc|ppc64|s390x)
> + i386|x86_64|ppcemb|ppc|ppc64|s390x|mipsel|mips)
> # Make sure the target and host cpus are compatible
> if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \
> \( "$target_arch2" = "$cpu" -o \
> @@ -4082,6 +4090,8 @@ case "$target_arch2" in
> \( "$target_arch2" = "ppc64" -a "$cpu" = "ppc" \) -o \
> \( "$target_arch2" = "ppc" -a "$cpu" = "ppc64" \) -o \
> \( "$target_arch2" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
> + \( "$target_arch2" = "mipsel" -a "$cpu" = "mips" \) -o \
> + \( "$target_arch2" = "mips" -a "$cpu" = "mips" \) -o \
Pointless check because we've already tested for target_arch2 == cpu.
Or did you mean one of these 'mips' to be 'mipsel' ?
> \( "$target_arch2" = "x86_64" -a "$cpu" = "i386" \) -o \
> \( "$target_arch2" = "i386" -a "$cpu" = "x86_64" \) \) ; then
> echo "CONFIG_KVM=y" >> $config_target_mak
> @@ -4285,6 +4295,9 @@ if test "$target_linux_user" = "yes" -o "$target_bsd_user" = "yes" ; then
> *)
> ldflags="$linker_script $ldflags"
> ;;
> + mips|mipsel|mipseb|mips64)
> + symlink $source_path/linux-headers/asm-mips linux-headers/asm
> + ;;
> esac
> fi
?? Looks like the result of a bad merge conflict resolution.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
@ 2013-03-02 15:42 ` Peter Maydell
0 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:42 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> ---
> configure | 17 +++++++++++++++--
> hw/mips/Makefile.objs | 2 +-
> target-mips/Makefile.objs | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/configure b/configure
> index bf5970f..5447661 100755
> --- a/configure
> +++ b/configure
> @@ -1370,7 +1370,12 @@ case "$cpu" in
> bigendian=yes
> fi
> ;;
> - hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
> + mips|mips64)
> + if check_define __MIPSEB__; then
> + bigendian=yes
> + fi
> + ;;
> + hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
> bigendian=yes
> ;;
> esac
> @@ -3844,6 +3849,9 @@ if test "$linux" = "yes" ; then
> # For most CPUs the kernel architecture name and QEMU CPU name match.
> linux_arch="$cpu"
> ;;
> + mips|mips64)
> + symlink "$source_path/linux-headers/asm-mips" linux-headers/asm
> + ;;
Above the default case, not below it, please. And just set linux_arch
like the other cases; don't do the symlink yourself.
> esac
> # For non-KVM architectures we will not have asm headers
> if [ -e "$source_path/linux-headers/asm-$linux_arch" ]; then
> @@ -4074,7 +4082,7 @@ case "$target_arch2" in
> echo "CONFIG_NO_XEN=y" >> $config_target_mak
> esac
> case "$target_arch2" in
> - i386|x86_64|ppcemb|ppc|ppc64|s390x)
> + i386|x86_64|ppcemb|ppc|ppc64|s390x|mipsel|mips)
> # Make sure the target and host cpus are compatible
> if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \
> \( "$target_arch2" = "$cpu" -o \
> @@ -4082,6 +4090,8 @@ case "$target_arch2" in
> \( "$target_arch2" = "ppc64" -a "$cpu" = "ppc" \) -o \
> \( "$target_arch2" = "ppc" -a "$cpu" = "ppc64" \) -o \
> \( "$target_arch2" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
> + \( "$target_arch2" = "mipsel" -a "$cpu" = "mips" \) -o \
> + \( "$target_arch2" = "mips" -a "$cpu" = "mips" \) -o \
Pointless check because we've already tested for target_arch2 == cpu.
Or did you mean one of these 'mips' to be 'mipsel' ?
> \( "$target_arch2" = "x86_64" -a "$cpu" = "i386" \) -o \
> \( "$target_arch2" = "i386" -a "$cpu" = "x86_64" \) \) ; then
> echo "CONFIG_KVM=y" >> $config_target_mak
> @@ -4285,6 +4295,9 @@ if test "$target_linux_user" = "yes" -o "$target_bsd_user" = "yes" ; then
> *)
> ldflags="$linker_script $ldflags"
> ;;
> + mips|mipsel|mipseb|mips64)
> + symlink $source_path/linux-headers/asm-mips linux-headers/asm
> + ;;
> esac
> fi
?? Looks like the result of a bad merge conflict resolution.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 07/12] KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:44 ` Peter Maydell
-1 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:44 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> ---
> linux-headers/asm-mips/kvm.h | 94 +++++++++++++++++++++++++++++++++++++++
> linux-headers/asm-mips/kvm_para.h | 10 +++++
Please don't supply QEMU patches that update the linux-header files
without specifying which kernel tree and git revision the headers
have come from. In particular, if the headers have not yet hit
upstream kvm-next or mainline then the whole patchset must be marked
as RFC since it can't be committed until the ABI has stabilised.
thanks
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 07/12] KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
@ 2013-03-02 15:44 ` Peter Maydell
0 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:44 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> ---
> linux-headers/asm-mips/kvm.h | 94 +++++++++++++++++++++++++++++++++++++++
> linux-headers/asm-mips/kvm_para.h | 10 +++++
Please don't supply QEMU patches that update the linux-header files
without specifying which kernel tree and git revision the headers
have come from. In particular, if the headers have not yet hit
upstream kvm-next or mainline then the whole patchset must be marked
as RFC since it can't be committed until the ABI has stabilised.
thanks
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 15:45 ` Peter Maydell
-1 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:45 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> + /* If we have an interrupt but the guest is not ready to receive an
> + * interrupt, request an interrupt window exit. This will
> + * cause a return to userspace as soon as the guest is ready to
> + * receive interrupts.
> + */
> + if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
> + run->request_interrupt_window = 1;
> + } else {
> + run->request_interrupt_window = 0;
> + }
> +}
Does MIPS really need x86-style fully-synchronised delivery
of interrupts from userspace to the kernel? Don't copy x86
unless you know it's really what your architecture requires.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
@ 2013-03-02 15:45 ` Peter Maydell
0 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 15:45 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> + /* If we have an interrupt but the guest is not ready to receive an
> + * interrupt, request an interrupt window exit. This will
> + * cause a return to userspace as soon as the guest is ready to
> + * receive interrupts.
> + */
> + if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
> + run->request_interrupt_window = 1;
> + } else {
> + run->request_interrupt_window = 0;
> + }
> +}
Does MIPS really need x86-style fully-synchronised delivery
of interrupts from userspace to the kernel? Don't copy x86
unless you know it's really what your architecture requires.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-02 20:03 ` Peter Maydell
-1 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 20:03 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> --- /dev/null
> +++ b/hw/mips_cps_bootcode.h
> @@ -0,0 +1,310 @@
> +/* Sample boot code for 1004K CPS (Coherent Processing System.)
> + * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
> + *
> + * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
> + */
(a) "All rights reserved" means "you can't put this in QEMU".
(b) huge binary blob in a hex array? Yuck.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
@ 2013-03-02 20:03 ` Peter Maydell
0 siblings, 0 replies; 50+ messages in thread
From: Peter Maydell @ 2013-03-02 20:03 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
> --- /dev/null
> +++ b/hw/mips_cps_bootcode.h
> @@ -0,0 +1,310 @@
> +/* Sample boot code for 1004K CPS (Coherent Processing System.)
> + * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
> + *
> + * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
> + */
(a) "All rights reserved" means "you can't put this in QEMU".
(b) huge binary blob in a hex array? Yuck.
-- PMM
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Qemu-devel][PATCH 00/12] KVM Support for MIPS32 Processors
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-04 1:21 ` Zhang, Yang Z
-1 siblings, 0 replies; 50+ messages in thread
From: Zhang, Yang Z @ 2013-03-04 1:21 UTC (permalink / raw)
To: Sanjay Lal, qemu-devel; +Cc: kvm, Aurelien Jarno, Gleb Natapov, Marcelo Tosatti
Sanjay Lal wrote on 2013-03-02:
> The following patchset implements KVM support for MIPS32 processors,
> using Trap & Emulate, with basic runtime binary translation to improve
> performance.
>
> In KVM mode, CPU virtualization is handled via the kvm kernel module,
> while system and I/O virtualization leverage the Malta model already present
> in QEMU.
One question(maybe stupid):
I don't see any changes to mips32 kernel. But you said cpu virtualization is handled via kvm kernel module. How it handle it?
> Both Guest kernel and Guest Userspace execute in UM. The Guest address
> space is
> as folows:
> Guest User address space: 0x00000000 -> 0x40000000
> Guest Kernel Unmapped: 0x40000000 -> 0x60000000
> Guest Kernel Mapped: 0x60000000 -> 0x80000000
>
> As a result, Guest Usermode virtual memory is limited to 1GB.
>
> The Malta model has been enhanced to support SMP guest kernels via support
> for the CPS bootcode from MIPS which supports bootstrapping multiple cpus.
> A model for the MIPS GIC has also been added to support IPIs.
> This allows booting Linux in full SMP mode with a cluster of MIPS32R2 cpus.
>
> There is a companion kernel patchset for KVM that has been posted on
> the KVM/MIPS mailing lists.
>
> --
> Sanjay Lal (12):
> KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
> KVM/MIPS: GIC emulation for SMP guests.
> KVM/MIPS: Add save/restore state APIs for saving/restoring KVM
> guests. KVM/MIPS: Do not start the periodic timer in KVM mode.
> Compare/Count timer interrupts are handled in-kernel. KVM/MIPS: In
> KVM mode, inject IRQ2 (I/O) interupts via ioctls(). COP0 emulation
> is in-kernel KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest
> Physical addresses.
> KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
> KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the
> build.
> KVM/MIPS: set sigmask length to 16 for MIPS targets.
> KVM/MIPS: Set page size to 16K in KVM mode.
> KVM/MIPS: MIPS specfic APIs for KVM.
> KVM/MIPS: General KVM support and support for SMP Guests
> configure | 17 +- hw/gt64xxx.c
> | 317 +++++++++++++++++++++++++++++ hw/mips/Makefile.objs
> | 2 +- hw/mips_addr.c | 14 ++
> hw/mips_cps_bootcode.h | 310 ++++++++++++++++++++++++++++
> hw/mips_cpudevs.h | 4 + hw/mips_gcmpregs.h
> | 122 +++++++++++ hw/mips_gic.c | 418
> ++++++++++++++++++++++++++++++++++++++ hw/mips_gic.h
> | 378 ++++++++++++++++++++++++++++++++++ hw/mips_int.c
> | 15 ++ hw/mips_malta.c | 192 +++++++++++------
> hw/mips_timer.c | 13 +- kvm-all.c
> | 5 + linux-headers/asm-mips/kvm.h | 94 +++++++++
> linux-headers/asm-mips/kvm_para.h | 10 + target-mips/Makefile.objs
> | 1 + target-mips/kvm.c | 292
> ++++++++++++++++++++++++++ target-mips/kvm_mips.h | 21 ++
> target-mips/mips-defs.h | 5 + 19 files changed, 2157
> insertions(+), 73 deletions(-) create mode 100644
> hw/mips_cps_bootcode.h create mode 100644 hw/mips_gcmpregs.h create
> mode 100644 hw/mips_gic.c create mode 100644 hw/mips_gic.h create mode
> 100644 linux-headers/asm-mips/kvm.h create mode 100644
> linux-headers/asm-mips/kvm_para.h create mode 100644 target-mips/kvm.c
> create mode 100644 target-mips/kvm_mips.h
> --
> 1.7.11.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Best regards,
Yang
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] KVM Support for MIPS32 Processors
@ 2013-03-04 1:21 ` Zhang, Yang Z
0 siblings, 0 replies; 50+ messages in thread
From: Zhang, Yang Z @ 2013-03-04 1:21 UTC (permalink / raw)
To: Sanjay Lal, qemu-devel; +Cc: Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
Sanjay Lal wrote on 2013-03-02:
> The following patchset implements KVM support for MIPS32 processors,
> using Trap & Emulate, with basic runtime binary translation to improve
> performance.
>
> In KVM mode, CPU virtualization is handled via the kvm kernel module,
> while system and I/O virtualization leverage the Malta model already present
> in QEMU.
One question(maybe stupid):
I don't see any changes to mips32 kernel. But you said cpu virtualization is handled via kvm kernel module. How it handle it?
> Both Guest kernel and Guest Userspace execute in UM. The Guest address
> space is
> as folows:
> Guest User address space: 0x00000000 -> 0x40000000
> Guest Kernel Unmapped: 0x40000000 -> 0x60000000
> Guest Kernel Mapped: 0x60000000 -> 0x80000000
>
> As a result, Guest Usermode virtual memory is limited to 1GB.
>
> The Malta model has been enhanced to support SMP guest kernels via support
> for the CPS bootcode from MIPS which supports bootstrapping multiple cpus.
> A model for the MIPS GIC has also been added to support IPIs.
> This allows booting Linux in full SMP mode with a cluster of MIPS32R2 cpus.
>
> There is a companion kernel patchset for KVM that has been posted on
> the KVM/MIPS mailing lists.
>
> --
> Sanjay Lal (12):
> KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
> KVM/MIPS: GIC emulation for SMP guests.
> KVM/MIPS: Add save/restore state APIs for saving/restoring KVM
> guests. KVM/MIPS: Do not start the periodic timer in KVM mode.
> Compare/Count timer interrupts are handled in-kernel. KVM/MIPS: In
> KVM mode, inject IRQ2 (I/O) interupts via ioctls(). COP0 emulation
> is in-kernel KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest
> Physical addresses.
> KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS
> KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the
> build.
> KVM/MIPS: set sigmask length to 16 for MIPS targets.
> KVM/MIPS: Set page size to 16K in KVM mode.
> KVM/MIPS: MIPS specfic APIs for KVM.
> KVM/MIPS: General KVM support and support for SMP Guests
> configure | 17 +- hw/gt64xxx.c
> | 317 +++++++++++++++++++++++++++++ hw/mips/Makefile.objs
> | 2 +- hw/mips_addr.c | 14 ++
> hw/mips_cps_bootcode.h | 310 ++++++++++++++++++++++++++++
> hw/mips_cpudevs.h | 4 + hw/mips_gcmpregs.h
> | 122 +++++++++++ hw/mips_gic.c | 418
> ++++++++++++++++++++++++++++++++++++++ hw/mips_gic.h
> | 378 ++++++++++++++++++++++++++++++++++ hw/mips_int.c
> | 15 ++ hw/mips_malta.c | 192 +++++++++++------
> hw/mips_timer.c | 13 +- kvm-all.c
> | 5 + linux-headers/asm-mips/kvm.h | 94 +++++++++
> linux-headers/asm-mips/kvm_para.h | 10 + target-mips/Makefile.objs
> | 1 + target-mips/kvm.c | 292
> ++++++++++++++++++++++++++ target-mips/kvm_mips.h | 21 ++
> target-mips/mips-defs.h | 5 + 19 files changed, 2157
> insertions(+), 73 deletions(-) create mode 100644
> hw/mips_cps_bootcode.h create mode 100644 hw/mips_gcmpregs.h create
> mode 100644 hw/mips_gic.c create mode 100644 hw/mips_gic.h create mode
> 100644 linux-headers/asm-mips/kvm.h create mode 100644
> linux-headers/asm-mips/kvm_para.h create mode 100644 target-mips/kvm.c
> create mode 100644 target-mips/kvm_mips.h
> --
> 1.7.11.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Best regards,
Yang
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-04 11:27 ` Andreas Färber
-1 siblings, 0 replies; 50+ messages in thread
From: Andreas Färber @ 2013-03-04 11:27 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
Am 02.03.2013 16:18, schrieb Sanjay Lal:
> ---
> configure | 17 +++++++++++++++--
> hw/mips/Makefile.objs | 2 +-
> target-mips/Makefile.objs | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/configure b/configure
> index bf5970f..5447661 100755
> --- a/configure
> +++ b/configure
> @@ -1370,7 +1370,12 @@ case "$cpu" in
> bigendian=yes
> fi
> ;;
> - hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
> + mips|mips64)
> + if check_define __MIPSEB__; then
> + bigendian=yes
> + fi
> + ;;
> + hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
> bigendian=yes
> ;;
> esac
[snip]
If this is needed it should be a patch on its own. But we already
support mipsel I thought, so I don't understand why the change is needed
without proper commit message.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build.
@ 2013-03-04 11:27 ` Andreas Färber
0 siblings, 0 replies; 50+ messages in thread
From: Andreas Färber @ 2013-03-04 11:27 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
Am 02.03.2013 16:18, schrieb Sanjay Lal:
> ---
> configure | 17 +++++++++++++++--
> hw/mips/Makefile.objs | 2 +-
> target-mips/Makefile.objs | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/configure b/configure
> index bf5970f..5447661 100755
> --- a/configure
> +++ b/configure
> @@ -1370,7 +1370,12 @@ case "$cpu" in
> bigendian=yes
> fi
> ;;
> - hppa|m68k|mips|mips64|ppc|ppc64|s390|s390x|sparc|sparc64)
> + mips|mips64)
> + if check_define __MIPSEB__; then
> + bigendian=yes
> + fi
> + ;;
> + hppa|m68k|ppc|ppc64|s390|s390x|sparc|sparc64)
> bigendian=yes
> ;;
> esac
[snip]
If this is needed it should be a patch on its own. But we already
support mipsel I thought, so I don't understand why the change is needed
without proper commit message.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] KVM Support for MIPS32 Processors
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
@ 2013-03-04 11:55 ` Andreas Färber
-1 siblings, 0 replies; 50+ messages in thread
From: Andreas Färber @ 2013-03-04 11:55 UTC (permalink / raw)
To: Sanjay Lal; +Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
Hello,
Am 02.03.2013 16:18, schrieb Sanjay Lal:
> The following patchset implements KVM support for MIPS32 processors,
> using Trap & Emulate, with basic runtime binary translation to improve
> performance.
[snip]
Please see http://wiki.qemu.org/Contribute/SubmitAPatch for some hints
on how to improve submission of your QEMU patchset. In particular we
require Signed-off-bys just like Linux, subjects should use
"target-mips: " or similar based on file/directory names, subject line
should be one short statement and commit message should give further
explanations of what the patch is doing and why, where appropriate.
Also a fair warning: I am refactoring the core CPU code, so you should
be tracking qemu.git and/or mailing list for possible conflicts and
rebasing necessary.
In that context please prefer use of MIPSCPU over CPUMIPSState (e.g., in
GIC state and functions).
Please adopt our Coding Style, which among other things asks for
CamelCase struct naming (e.g., MIPSGICState rather than gic_t).
Please learn about QOM usage and its conventions. Your GIC should
probably be a SysBusDevice, not a pre-qdev collection of manually
allocated state.
http://wiki.qemu.org/QOMConventions
There's also an ongoing discussion about DPRINTF()s defined as no-op "do
{} while(0)" leading to format string breakages over time. Recommended
replacement is a macro using "do { if (FOO) { ... } } while (0)", with
FOO evaluating to 0 in the no-debug case, so that everything gets
compile-tested but optimized out.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] KVM Support for MIPS32 Processors
@ 2013-03-04 11:55 ` Andreas Färber
0 siblings, 0 replies; 50+ messages in thread
From: Andreas Färber @ 2013-03-04 11:55 UTC (permalink / raw)
To: Sanjay Lal; +Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
Hello,
Am 02.03.2013 16:18, schrieb Sanjay Lal:
> The following patchset implements KVM support for MIPS32 processors,
> using Trap & Emulate, with basic runtime binary translation to improve
> performance.
[snip]
Please see http://wiki.qemu.org/Contribute/SubmitAPatch for some hints
on how to improve submission of your QEMU patchset. In particular we
require Signed-off-bys just like Linux, subjects should use
"target-mips: " or similar based on file/directory names, subject line
should be one short statement and commit message should give further
explanations of what the patch is doing and why, where appropriate.
Also a fair warning: I am refactoring the core CPU code, so you should
be tracking qemu.git and/or mailing list for possible conflicts and
rebasing necessary.
In that context please prefer use of MIPSCPU over CPUMIPSState (e.g., in
GIC state and functions).
Please adopt our Coding Style, which among other things asks for
CamelCase struct naming (e.g., MIPSGICState rather than gic_t).
Please learn about QOM usage and its conventions. Your GIC should
probably be a SysBusDevice, not a pre-qdev collection of manually
allocated state.
http://wiki.qemu.org/QOMConventions
There's also an ongoing discussion about DPRINTF()s defined as no-op "do
{} while(0)" leading to format string breakages over time. Recommended
replacement is a macro using "do { if (FOO) { ... } } while (0)", with
FOO evaluating to 0 in the no-debug case, so that everything gets
compile-tested but optimized out.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
2013-03-02 15:45 ` Peter Maydell
@ 2013-03-06 19:43 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:43 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On Mar 2, 2013, at 7:45 AM, Peter Maydell wrote:
> On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
>> + /* If we have an interrupt but the guest is not ready to receive an
>> + * interrupt, request an interrupt window exit. This will
>> + * cause a return to userspace as soon as the guest is ready to
>> + * receive interrupts.
>> + */
>> + if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
>> + run->request_interrupt_window = 1;
>> + } else {
>> + run->request_interrupt_window = 0;
>> + }
>> +}
>
> Does MIPS really need x86-style fully-synchronised delivery
> of interrupts from userspace to the kernel? Don't copy x86
> unless you know it's really what your architecture requires.
>
> -- PMM
>
Sorry my bad, this was from an older snapshot of the code. The whole request_interrupt_window code has been deprecated and will be removed from the v2 of patch set.
Regards
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM.
@ 2013-03-06 19:43 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:43 UTC (permalink / raw)
To: Peter Maydell
Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On Mar 2, 2013, at 7:45 AM, Peter Maydell wrote:
> On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
>> + /* If we have an interrupt but the guest is not ready to receive an
>> + * interrupt, request an interrupt window exit. This will
>> + * cause a return to userspace as soon as the guest is ready to
>> + * receive interrupts.
>> + */
>> + if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
>> + run->request_interrupt_window = 1;
>> + } else {
>> + run->request_interrupt_window = 0;
>> + }
>> +}
>
> Does MIPS really need x86-style fully-synchronised delivery
> of interrupts from userspace to the kernel? Don't copy x86
> unless you know it's really what your architecture requires.
>
> -- PMM
>
Sorry my bad, this was from an older snapshot of the code. The whole request_interrupt_window code has been deprecated and will be removed from the v2 of patch set.
Regards
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
2013-03-02 20:03 ` Peter Maydell
@ 2013-03-06 19:44 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:44 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On Mar 2, 2013, at 12:03 PM, Peter Maydell wrote:
> On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
>> --- /dev/null
>> +++ b/hw/mips_cps_bootcode.h
>> @@ -0,0 +1,310 @@
>> +/* Sample boot code for 1004K CPS (Coherent Processing System.)
>> + * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
>> + *
>> + * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
>> + */
>
> (a) "All rights reserved" means "you can't put this in QEMU".
> (b) huge binary blob in a hex array? Yuck.
>
Would it be better to release the boot code as a binary ROM image? That would address both (a) and (b)?
Regards and thanks
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP
@ 2013-03-06 19:44 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:44 UTC (permalink / raw)
To: Peter Maydell
Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On Mar 2, 2013, at 12:03 PM, Peter Maydell wrote:
> On 2 March 2013 15:18, Sanjay Lal <sanjayl@kymasys.com> wrote:
>> --- /dev/null
>> +++ b/hw/mips_cps_bootcode.h
>> @@ -0,0 +1,310 @@
>> +/* Sample boot code for 1004K CPS (Coherent Processing System.)
>> + * Not Generic for all Release 2 or higher MIPS32 or MIPS64 processors
>> + *
>> + * Copyright (c) 2006,2008 MIPS Technologies, Inc. All rights reserved.
>> + */
>
> (a) "All rights reserved" means "you can't put this in QEMU".
> (b) huge binary blob in a hex array? Yuck.
>
Would it be better to release the boot code as a binary ROM image? That would address both (a) and (b)?
Regards and thanks
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
2013-03-02 15:27 ` Peter Maydell
@ 2013-03-06 19:45 ` Sanjay Lal
-1 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:45 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Gleb Natapov, Marcelo Tosatti, Aurelien Jarno, kvm
On Mar 2, 2013, at 7:27 AM, Peter Maydell wrote:
> 2013/3/2 Sanjay Lal <sanjayl@kymasys.com>:
>> +static void gt64xxx_save(QEMUFile *f, void *opaque)
>> +{
>> + GT64120State *s = opaque;
>> +
>> + /* CPU Configuration */
>> + qemu_put_be32s(f, &s->regs[GT_CPU]);
>> + qemu_put_be32s(f, &s->regs[GT_MULTI]);
>
>
> Definitely no new save/load functions like this in new code,
> please. Use a VMState struct.
>
> thanks
> -- PMM
>
Will do for v2 of the patch set.
Regards
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.
@ 2013-03-06 19:45 ` Sanjay Lal
0 siblings, 0 replies; 50+ messages in thread
From: Sanjay Lal @ 2013-03-06 19:45 UTC (permalink / raw)
To: Peter Maydell
Cc: Aurelien Jarno, Marcelo Tosatti, qemu-devel, Gleb Natapov, kvm
On Mar 2, 2013, at 7:27 AM, Peter Maydell wrote:
> 2013/3/2 Sanjay Lal <sanjayl@kymasys.com>:
>> +static void gt64xxx_save(QEMUFile *f, void *opaque)
>> +{
>> + GT64120State *s = opaque;
>> +
>> + /* CPU Configuration */
>> + qemu_put_be32s(f, &s->regs[GT_CPU]);
>> + qemu_put_be32s(f, &s->regs[GT_MULTI]);
>
>
> Definitely no new save/load functions like this in new code,
> please. Use a VMState struct.
>
> thanks
> -- PMM
>
Will do for v2 of the patch set.
Regards
Sanjay
^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2013-03-06 20:06 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-03-02 15:18 [Qemu-devel][PATCH 00/12] KVM Support for MIPS32 Processors Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 01/12] KVM/MIPS: Bootcode for MIPS SMP configurations with a GCMP Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 20:03 ` Peter Maydell
2013-03-02 20:03 ` Peter Maydell
2013-03-06 19:44 ` Sanjay Lal
2013-03-06 19:44 ` Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 01/12] MIPS: " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 02/12] KVM/MIPS: GIC emulation for SMP guests Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:27 ` Peter Maydell
2013-03-02 15:27 ` Peter Maydell
2013-03-06 19:45 ` Sanjay Lal
2013-03-06 19:45 ` Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 04/12] KVM/MIPS: Do not start the periodic timer in KVM mode. Compare/Count timer interrupts are handled in-kernel Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 05/12] KVM/MIPS: In KVM mode, inject IRQ2 (I/O) interupts via ioctls(). COP0 emulation is in-kernel Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 06/12] KVM/MIPS: Define APIs to convert Guest KSEG0 <-> Guest Physical addresses Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 07/12] KVM/MIPS: QEMU <-> Kernel interface for KVM/MIPS Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:44 ` Peter Maydell
2013-03-02 15:44 ` Peter Maydell
2013-03-02 15:18 ` [Qemu-devel][PATCH 08/12] KVM/MIPS: Enable KVM/MIPS for MIPS targets. Add MIPS GIC code to the build Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:42 ` Peter Maydell
2013-03-02 15:42 ` Peter Maydell
2013-03-04 11:27 ` Andreas Färber
2013-03-04 11:27 ` Andreas Färber
2013-03-02 15:18 ` [Qemu-devel][PATCH 09/12] KVM/MIPS: set sigmask length to 16 for MIPS targets Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 10/12] KVM/MIPS: Set page size to 16K in KVM mode Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 11/12] KVM/MIPS: MIPS specfic APIs for KVM Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-02 15:45 ` Peter Maydell
2013-03-02 15:45 ` Peter Maydell
2013-03-06 19:43 ` Sanjay Lal
2013-03-06 19:43 ` Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel][PATCH 12/12] KVM/MIPS: General KVM support and support for SMP Guests Sanjay Lal
2013-03-02 15:18 ` [Qemu-devel] [PATCH " Sanjay Lal
2013-03-04 1:21 ` [Qemu-devel][PATCH 00/12] KVM Support for MIPS32 Processors Zhang, Yang Z
2013-03-04 1:21 ` [Qemu-devel] [PATCH " Zhang, Yang Z
2013-03-04 11:55 ` Andreas Färber
2013-03-04 11:55 ` Andreas Färber
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