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From: Stephen Boyd <sboyd@codeaurora.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	Will Deacon <will.deacon@arm.com>,
	Stepan Moskovchenko <stepanm@codeaurora.org>
Subject: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs
Date: Tue, 12 Mar 2013 18:32:01 -0700	[thread overview]
Message-ID: <1363138321-27849-4-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1363138321-27849-1-git-send-email-sboyd@codeaurora.org>

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the detection code
to indicate support in both modes.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bd27a70..34ec24e 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -362,6 +362,14 @@ static void __init idiv_setup(void)
 
 	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
 
+	/*
+	 * Some Krait processors don't indicate support for SDIV and UDIV
+	 * instructions in the ARM instruction set, even though they actually
+	 * do support them.
+	 */
+	if ((read_cpuid_id() & 0xff0ffc00) == 0x510f0400)
+		divide_instrs = 2;
+
 	switch (divide_instrs) {
 	case 2:
 		elf_hwcap |= HWCAP_IDIVA;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs
Date: Tue, 12 Mar 2013 18:32:01 -0700	[thread overview]
Message-ID: <1363138321-27849-4-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1363138321-27849-1-git-send-email-sboyd@codeaurora.org>

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the detection code
to indicate support in both modes.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bd27a70..34ec24e 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -362,6 +362,14 @@ static void __init idiv_setup(void)
 
 	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
 
+	/*
+	 * Some Krait processors don't indicate support for SDIV and UDIV
+	 * instructions in the ARM instruction set, even though they actually
+	 * do support them.
+	 */
+	if ((read_cpuid_id() & 0xff0ffc00) == 0x510f0400)
+		divide_instrs = 2;
+
 	switch (divide_instrs) {
 	case 2:
 		elf_hwcap |= HWCAP_IDIVA;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

  parent reply	other threads:[~2013-03-13  1:32 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-13  1:31 [PATCH 0/3] Detect UDIV/SDIV support from ISAR0 Stephen Boyd
2013-03-13  1:31 ` Stephen Boyd
2013-03-13  1:31 ` [PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n Stephen Boyd
2013-03-13  1:31   ` Stephen Boyd
2013-03-13  1:31   ` Stephen Boyd
2013-03-17 14:29   ` Will Deacon
2013-03-17 14:29     ` Will Deacon
2013-03-17 14:29     ` Will Deacon
2013-03-13  1:32 ` [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register Stephen Boyd
2013-03-13  1:32   ` Stephen Boyd
2013-03-17 14:36   ` Will Deacon
2013-03-17 14:36     ` Will Deacon
2013-03-17 14:36     ` Will Deacon
2013-03-18 17:13     ` Stephen Boyd
2013-03-18 17:13       ` Stephen Boyd
2013-03-18 17:13       ` Stephen Boyd
2013-03-13  1:32 ` Stephen Boyd [this message]
2013-03-13  1:32   ` [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs Stephen Boyd
2013-03-17 14:28   ` Will Deacon
2013-03-17 14:28     ` Will Deacon
2013-03-17 14:28     ` Will Deacon
2013-03-18 17:03     ` Stephen Boyd
2013-03-18 17:03       ` Stephen Boyd
2013-03-18 17:03       ` Stephen Boyd
2013-03-18 18:19       ` Will Deacon
2013-03-18 18:19         ` Will Deacon
2013-03-18 18:19         ` Will Deacon

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