[U-Boot] [PATCH v2 00/13] tegra114 SPI driver

[U-Boot] [PATCH v2 00/13] tegra114 SPI driver

[Allen Martin]

This series pulls fdt functionality from the existing tegra20 and
tegra30 SPI drivers into a new common fdt SPI driver front end,
then adds a new tegra114 SPI driver as an additional client of
the fdt SPI driver.

Changes in v2:
 - Added a patch to remove SPI/UART switch support, this was only
   useful for seaboard, which was never manufactured
 - Renamed tegra_sflash and tegra_slink to tegra20_sflash and
   tegra20_slink 
 - Moved SPI register definitions from header files into SPI driver
   files, since those are the only users of those registers.
 - Removed patch to add CAR node to dt, equivalent patch was already
   upstreamed.

Allen Martin (13):
  tegra: remove support for UART SPI switch
  tegra: spi: rename tegra SPI drivers
  tegra: spi: remove non fdt support
  tegra: spi: pull register structs out of headers
  tegra20: spi: move fdt probe to spi_init
  spi: add common fdt SPI driver interface
  sf: winbond: add W25Q32DW
  tegra114: fdt: add compatible string for tegra114 SPI ctrl
  tegra114: fdt: add apbdma block
  tegra114: fdt: add SPI blocks
  tegra114: dalmore: fdt: enable dalmore SPI controller
  tegra114: add SPI driver
  tegra114: dalmore: config: enable SPI

 arch/arm/dts/tegra114.dtsi                         |  109 ++++++
 arch/arm/include/asm/arch-tegra/board.h            |    3 +-
 arch/arm/include/asm/arch-tegra/tegra_slink.h      |   84 ----
 arch/arm/include/asm/arch-tegra/tegra_spi.h        |   75 ----
 arch/arm/include/asm/arch-tegra114/tegra114_spi.h  |   41 ++
 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h |   41 ++
 arch/arm/include/asm/arch-tegra20/tegra20_slink.h  |   41 ++
 .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 ---
 board/nvidia/common/board.c                        |    5 +-
 board/nvidia/common/common.mk                      |    1 -
 board/nvidia/common/uart-spi-switch.c              |  125 ------
 board/nvidia/dts/tegra114-dalmore.dts              |    5 +
 board/nvidia/seaboard/seaboard.c                   |    2 +-
 drivers/mtd/spi/winbond.c                          |    5 +
 drivers/spi/Makefile                               |    6 +-
 drivers/spi/fdt_spi.c                              |  186 +++++++++
 drivers/spi/tegra114_spi.c                         |  405 ++++++++++++++++++++
 drivers/spi/{tegra_spi.c => tegra20_sflash.c}      |  215 ++++++-----
 drivers/spi/{tegra_slink.c => tegra20_slink.c}     |  128 ++++---
 include/configs/cardhu.h                           |    2 +-
 include/configs/dalmore.h                          |   11 +
 include/configs/tegra-common-post.h                |    4 +
 include/configs/trimslice.h                        |    2 +-
 include/fdtdec.h                                   |    1 +
 lib/fdtdec.c                                       |    1 +
 25 files changed, 1054 insertions(+), 490 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
 delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h
 create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
 create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
 create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_slink.h
 delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
 delete mode 100644 board/nvidia/common/uart-spi-switch.c
 create mode 100644 drivers/spi/fdt_spi.c
 create mode 100644 drivers/spi/tegra114_spi.c
 rename drivers/spi/{tegra_spi.c => tegra20_sflash.c} (57%)
 rename drivers/spi/{tegra_slink.c => tegra20_slink.c} (72%)

-- 
1.7.10.4

[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch

[Allen Martin]

This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins.  These boards were never manufactured, so
remove this support to clean up SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/include/asm/arch-tegra/board.h            |    3 +-
 .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 -------
 board/nvidia/common/board.c                        |    3 -
 board/nvidia/common/common.mk                      |    1 -
 board/nvidia/common/uart-spi-switch.c              |  125 --------------------
 board/nvidia/seaboard/seaboard.c                   |    2 +-
 drivers/spi/tegra_spi.c                            |   25 +---
 7 files changed, 3 insertions(+), 202 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
 delete mode 100644 board/nvidia/common/uart-spi-switch.c

diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 3db0d93..1a66990 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -25,8 +25,7 @@
 #define _TEGRA_BOARD_H_
 
 /* Set up pinmux to make UART usable */
-void gpio_config_uart(void);      /* CONFIG_SPI_UART_SWITCH */
-void gpio_early_init_uart(void);  /*!CONFIG_SPI_UART_SWITCH */
+void gpio_early_init_uart(void);
 
 /* Set up early UART output */
 void board_init_uart_f(void);
diff --git a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
deleted file mode 100644
index 82ac180..0000000
--- a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _UART_SPI_SWITCH_H
-#define _UART_SPI_SWITCH_H
-
-#if defined(CONFIG_SPI_UART_SWITCH)
-/*
- * Signal that we are about to use the UART. This unfortunate hack is
- * required by Seaboard, which cannot use its console and SPI at the same
- * time! If the board file provides this, the board config will declare it.
- * Let this be a lesson for others.
- */
-void pinmux_select_uart(void);
-
-/*
- * Signal that we are about the use the SPI bus.
- */
-void pinmux_select_spi(void);
-
-#else /* not CONFIG_SPI_UART_SWITCH */
-
-static inline void pinmux_select_uart(void) {}
-static inline void pinmux_select_spi(void) {}
-
-#endif
-
-#endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 7d9f361..b6e6566 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -132,9 +132,6 @@ int board_init(void)
 	clock_init();
 	clock_verify();
 
-#ifdef CONFIG_SPI_UART_SWITCH
-	gpio_config_uart();
-#endif
 #if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
 	pin_mux_spi();
 	spi_init();
diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk
index bd6202c..d9bcb85 100644
--- a/board/nvidia/common/common.mk
+++ b/board/nvidia/common/common.mk
@@ -1,4 +1,3 @@
 # common options for all tegra boards
 COBJS-y	+= ../../nvidia/common/board.o
-COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o
 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c
deleted file mode 100644
index e9d445d..0000000
--- a/board/nvidia/common/uart-spi-switch.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/tegra_spi.h>
-#include <asm/arch-tegra/board.h>
-
-/* position of the UART/SPI select switch */
-enum spi_uart_switch {
-	SWITCH_UNKNOWN,
-	SWITCH_SPI,
-	SWITCH_UART,
-	SWITCH_BOTH
-};
-
-/* Information about the spi/uart switch */
-struct spi_uart {
-	int gpio;                       /* GPIO to control switch */
-	u32 port;                       /* Port number of UART affected */
-};
-
-static struct spi_uart local;
-static enum spi_uart_switch switch_pos; /* Current switch position */
-
-
-static void get_config(struct spi_uart *config)
-{
-#if defined CONFIG_SPI_CORRUPTS_UART
-	config->gpio = CONFIG_UART_DISABLE_GPIO;
-	config->port = CONFIG_SPI_CORRUPTS_UART_NR;
-#else
-	config->gpio = -1;
-#endif
-}
-
-/*
- * Init the UART / SPI switch. This can be called before relocation so we must
- * not access BSS.
- */
-void gpio_early_init_uart(void)
-{
-	struct spi_uart config;
-
-	get_config(&config);
-	if (config.gpio != -1) {
-		/* Cannot provide a label prior to relocation */
-		gpio_request(config.gpio, NULL);
-		gpio_direction_output(config.gpio, 0);
-	}
-}
-
-/*
- * Configure the UART / SPI switch.
- */
-void gpio_config_uart(void)
-{
-	get_config(&local);
-	if (local.gpio != -1) {
-		gpio_direction_output(local.gpio, 0);
-		switch_pos = SWITCH_UART;
-	} else {
-		/*
-		 * If we're here we don't have a SPI switch; go ahead and
-		 * enable the SPI now.  We didn't in spi_init() so we wouldn't
-		 * kill the UART.
-		 */
-		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
-		switch_pos = SWITCH_BOTH;
-	}
-}
-
-static void spi_uart_switch(struct spi_uart *config,
-			      enum spi_uart_switch new_pos)
-{
-	if (switch_pos == SWITCH_BOTH || new_pos == switch_pos)
-		return;
-
-	/* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */
-	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
-
-	/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
-	pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ?
-				PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD);
-
-	/*
-	 * On Seaboard, MOSI/MISO are shared w/UART.
-	 * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
-	 * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
-	 */
-	gpio_direction_output(config->gpio, new_pos == SWITCH_SPI);
-	switch_pos = new_pos;
-}
-
-void pinmux_select_uart(void)
-{
-		spi_uart_switch(&local, SWITCH_UART);
-}
-
-void pinmux_select_spi(void)
-{
-	spi_uart_switch(&local, SWITCH_SPI);
-}
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index e581fdd..498e513 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -31,7 +31,7 @@
 #include <asm/gpio.h>
 
 /* TODO: Remove this code when the SPI switch is working */
-#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
+#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
index ce19095..2662923 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
@@ -28,7 +28,6 @@
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch/uart-spi-switch.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/tegra_spi.h>
 #include <spi.h>
@@ -36,12 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SPI_CORRUPTS_UART)
- #define corrupt_delay()	udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
-#else
- #define corrupt_delay()
-#endif
-
 struct tegra_spi_slave {
 	struct spi_slave slave;
 	struct spi_tegra *regs;
@@ -175,16 +168,8 @@ int spi_claim_bus(struct spi_slave *slave)
 	 */
 	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
 	pinmux_tristate_disable(PINGRP_LSPI);
+	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
 
-#ifndef CONFIG_SPI_UART_SWITCH
-	/*
-	 * NOTE:
-	 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
-	 * SPI UART switch or subsequent UART data won't go out!  See
-	 * spi_uart_switch().
-	 */
-	/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
-#endif
 	return 0;
 }
 
@@ -202,24 +187,16 @@ void spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 
-	pinmux_select_spi();
-
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
 	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-
-	corrupt_delay();		/* Let UART settle */
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 
-	pinmux_select_uart();
-
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
 	clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-
-	corrupt_delay();		/* Let SPI settle */
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-- 
1.7.10.4

[U-Boot] [PATCH v2 02/13] tegra: spi: rename tegra SPI drivers

[Allen Martin]

Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 .../{arch-tegra/tegra_spi.h => arch-tegra20/tegra20_sflash.h}    |    6 +++---
 .../{arch-tegra/tegra_slink.h => arch-tegra20/tegra20_slink.h}   |    6 +++---
 board/nvidia/common/board.c                                      |    2 +-
 drivers/spi/Makefile                                             |    4 ++--
 drivers/spi/{tegra_spi.c => tegra20_sflash.c}                    |    2 +-
 drivers/spi/{tegra_slink.c => tegra20_slink.c}                   |    2 +-
 include/configs/cardhu.h                                         |    2 +-
 include/configs/trimslice.h                                      |    2 +-
 8 files changed, 13 insertions(+), 13 deletions(-)
 rename arch/arm/include/asm/{arch-tegra/tegra_spi.h => arch-tegra20/tegra20_sflash.h} (96%)
 rename arch/arm/include/asm/{arch-tegra/tegra_slink.h => arch-tegra20/tegra20_slink.h} (97%)
 rename drivers/spi/{tegra_spi.c => tegra20_sflash.c} (99%)
 rename drivers/spi/{tegra_slink.c => tegra20_slink.c} (99%)

diff --git a/arch/arm/include/asm/arch-tegra/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
similarity index 96%
rename from arch/arm/include/asm/arch-tegra/tegra_spi.h
rename to arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
index d53a93f..26a8402 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_spi.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -22,8 +22,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA_SPI_H_
-#define _TEGRA_SPI_H_
+#ifndef _TEGRA20_SPI_H_
+#define _TEGRA20_SPI_H_
 
 #include <asm/types.h>
 
@@ -72,4 +72,4 @@ struct spi_tegra {
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
 
-#endif	/* _TEGRA_SPI_H_ */
+#endif	/* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
similarity index 97%
rename from arch/arm/include/asm/arch-tegra/tegra_slink.h
rename to arch/arm/include/asm/arch-tegra20/tegra20_slink.h
index 74804b5..afa9b36 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_slink.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -22,8 +22,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA_SLINK_H_
-#define _TEGRA_SLINK_H_
+#ifndef _TEGRA30_SPI_H_
+#define _TEGRA30_SPI_H_
 
 #include <asm/types.h>
 
@@ -81,4 +81,4 @@ struct slink_tegra {
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
 
-#endif	/* _TEGRA_SLINK_H_ */
+#endif	/* _TEGRA30_SPI_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index b6e6566..87a418b 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -132,7 +132,7 @@ int board_init(void)
 	clock_init();
 	clock_verify();
 
-#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
 	pin_mux_spi();
 	spi_init();
 #endif
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 83abcbd..8470c34 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -45,8 +45,8 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
-COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
+COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
+COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra20_sflash.c
similarity index 99%
rename from drivers/spi/tegra_spi.c
rename to drivers/spi/tegra20_sflash.c
index 2662923..c6af30f 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -29,7 +29,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/tegra_spi.h>
+#include <asm/arch-tegra20/tegra20_sflash.h>
 #include <spi.h>
 #include <fdtdec.h>
 
diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra20_slink.c
similarity index 99%
rename from drivers/spi/tegra_slink.c
rename to drivers/spi/tegra20_slink.c
index 2c41fab..a6de4ce 100644
--- a/drivers/spi/tegra_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -27,7 +27,7 @@
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/tegra_slink.h>
+#include <asm/arch-tegra20/tegra20_slink.h>
 #include <spi.h>
 #include <fdtdec.h>
 
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 55dc83d..6a99175 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -60,7 +60,7 @@
 #define CONFIG_SYS_MMC_ENV_PART		2
 
 /* SPI */
-#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA20_SLINK
 #define CONFIG_TEGRA_SLINK_CTRLS       6
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_WINBOND
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 0644f7a..b925314 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -46,7 +46,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* SPI */
-#define CONFIG_TEGRA_SPI
+#define CONFIG_TEGRA20_SFLASH
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-- 
1.7.10.4

[U-Boot] [PATCH v2 03/13] tegra: spi: remove non fdt support

[Allen Martin]

Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 drivers/spi/tegra20_sflash.c |   12 ++++--------
 drivers/spi/tegra20_slink.c  |   29 -----------------------------
 2 files changed, 4 insertions(+), 37 deletions(-)

diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index c6af30f..3b1b6f8 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -61,6 +61,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	struct tegra_spi_slave *spi;
+	int node;
 
 	if (!spi_cs_is_valid(bus, cs)) {
 		printf("SPI error: unsupported bus %d / chip select %d\n",
@@ -81,9 +82,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	}
 	spi->slave.bus = bus;
 	spi->slave.cs = cs;
-#ifdef CONFIG_OF_CONTROL
-	int node = fdtdec_next_compatible(gd->fdt_blob, 0,
-					  COMPAT_NVIDIA_TEGRA20_SFLASH);
+
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+				      COMPAT_NVIDIA_TEGRA20_SFLASH);
 	if (node < 0) {
 		debug("%s: cannot locate sflash node\n", __func__);
 		return NULL;
@@ -108,11 +109,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		debug("%s: could not decode periph id\n", __func__);
 		return NULL;
 	}
-#else
-	spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
-	spi->freq = TEGRA_SPI_MAX_FREQ;
-	spi->periph_id = PERIPH_ID_SPI1;
-#endif
 	if (max_hz < spi->freq) {
 		debug("%s: limiting frequency from %u to %u\n", __func__,
 		      spi->freq, max_hz);
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index a6de4ce..c794054 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -116,7 +116,6 @@ void spi_init(void)
 {
 	struct tegra_spi_ctrl *ctrl;
 	int i;
-#ifdef CONFIG_OF_CONTROL
 	int node = 0;
 	int count;
 	int node_list[CONFIG_TEGRA_SLINK_CTRLS];
@@ -152,34 +151,6 @@ void spi_init(void)
 		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
 		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
 	}
-#else
-	for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
-		ctrl = &spi_ctrls[i];
-		u32 base_regs[] = {
-			NV_PA_SLINK1_BASE,
-			NV_PA_SLINK2_BASE,
-			NV_PA_SLINK3_BASE,
-			NV_PA_SLINK4_BASE,
-			NV_PA_SLINK5_BASE,
-			NV_PA_SLINK6_BASE,
-		};
-		int periph_ids[] = {
-			PERIPH_ID_SBC1,
-			PERIPH_ID_SBC2,
-			PERIPH_ID_SBC3,
-			PERIPH_ID_SBC4,
-			PERIPH_ID_SBC5,
-			PERIPH_ID_SBC6,
-		};
-		ctrl->regs = (struct slink_tegra *)base_regs[i];
-		ctrl->freq = TEGRA_SPI_MAX_FREQ;
-		ctrl->periph_id = periph_ids[i];
-		ctrl->valid = 1;
-
-		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-	}
-#endif
 }
 
 int spi_claim_bus(struct spi_slave *slave)
-- 
1.7.10.4

[U-Boot] [PATCH v2 04/13] tegra: spi: pull register structs out of headers

[Allen Martin]

Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h |   45 -------------
 arch/arm/include/asm/arch-tegra20/tegra20_slink.h  |   54 ----------------
 drivers/spi/tegra20_sflash.c                       |   53 +++++++++++++--
 drivers/spi/tegra20_slink.c                        |   68 ++++++++++++++++++--
 4 files changed, 110 insertions(+), 110 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
index 26a8402..28775db 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -27,49 +27,4 @@
 
 #include <asm/types.h>
 
-struct spi_tegra {
-	u32 command;	/* SPI_COMMAND_0 register  */
-	u32 status;	/* SPI_STATUS_0 register */
-	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
-	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
-	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
-	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
-	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
-};
-
-#define SPI_CMD_GO			(1 << 30)
-#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
-#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA			(1 << 21)
-#define SPI_CMD_ACTIVE_SDA_SHIFT	18
-#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL			(1 << 16)
-#define SPI_CMD_TXEN			(1 << 15)
-#define SPI_CMD_RXEN			(1 << 14)
-#define SPI_CMD_CS_VAL			(1 << 13)
-#define SPI_CMD_CS_SOFT			(1 << 12)
-#define SPI_CMD_CS_DELAY		(1 << 9)
-#define SPI_CMD_CS3_EN			(1 << 8)
-#define SPI_CMD_CS2_EN			(1 << 7)
-#define SPI_CMD_CS1_EN			(1 << 6)
-#define SPI_CMD_CS0_EN			(1 << 5)
-#define SPI_CMD_BIT_LENGTH		(1 << 4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
-
-#define SPI_STAT_BSY			(1 << 31)
-#define SPI_STAT_RDY			(1 << 30)
-#define SPI_STAT_RXF_FLUSH		(1 << 29)
-#define SPI_STAT_TXF_FLUSH		(1 << 28)
-#define SPI_STAT_RXF_UNR		(1 << 27)
-#define SPI_STAT_TXF_OVF		(1 << 26)
-#define SPI_STAT_RXF_EMPTY		(1 << 25)
-#define SPI_STAT_RXF_FULL		(1 << 24)
-#define SPI_STAT_TXF_EMPTY		(1 << 23)
-#define SPI_STAT_TXF_FULL		(1 << 22)
-#define SPI_STAT_SEL_TXRX_N		(1 << 16)
-#define SPI_STAT_CUR_BLKCNT		(1 << 15)
-
-#define SPI_TIMEOUT		1000
-#define TEGRA_SPI_MAX_FREQ	52000000
-
 #endif	/* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
index afa9b36..fe8b534 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -27,58 +27,4 @@
 
 #include <asm/types.h>
 
-struct slink_tegra {
-	u32 command;	/* SLINK_COMMAND_0 register  */
-	u32 command2;	/* SLINK_COMMAND2_0 reg */
-	u32 status;	/* SLINK_STATUS_0 register */
-	u32 reserved;	/* Reserved offset 0C */
-	u32 mas_data;	/* SLINK_MAS_DATA_0 reg */
-	u32 slav_data;	/* SLINK_SLAVE_DATA_0 reg */
-	u32 dma_ctl;	/* SLINK_DMA_CTL_0 register */
-	u32 status2;	/* SLINK_STATUS2_0 reg */
-	u32 rsvd[56];	/* 0x20 to 0xFF reserved */
-	u32 tx_fifo;	/* SLINK_TX_FIFO_0 reg off 100h */
-	u32 rsvd2[31];	/* 0x104 to 0x17F reserved */
-	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
-};
-
-/* COMMAND */
-#define SLINK_CMD_ENB			(1 << 31)
-#define SLINK_CMD_GO			(1 << 30)
-#define SLINK_CMD_M_S			(1 << 28)
-#define SLINK_CMD_CK_SDA		(1 << 21)
-#define SLINK_CMD_CS_POL		(1 << 13)
-#define SLINK_CMD_CS_VAL		(1 << 12)
-#define SLINK_CMD_CS_SOFT		(1 << 11)
-#define SLINK_CMD_BIT_LENGTH		(1 << 4)
-#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
-/* COMMAND2 */
-#define SLINK_CMD2_TXEN			(1 << 30)
-#define SLINK_CMD2_RXEN			(1 << 31)
-#define SLINK_CMD2_SS_EN		(1 << 18)
-#define SLINK_CMD2_SS_EN_SHIFT		18
-#define SLINK_CMD2_SS_EN_MASK		0x000C0000
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
-/* STATUS */
-#define SLINK_STAT_BSY			(1 << 31)
-#define SLINK_STAT_RDY			(1 << 30)
-#define SLINK_STAT_ERR			(1 << 29)
-#define SLINK_STAT_RXF_FLUSH		(1 << 27)
-#define SLINK_STAT_TXF_FLUSH		(1 << 26)
-#define SLINK_STAT_RXF_OVF		(1 << 25)
-#define SLINK_STAT_TXF_UNR		(1 << 24)
-#define SLINK_STAT_RXF_EMPTY		(1 << 23)
-#define SLINK_STAT_RXF_FULL		(1 << 22)
-#define SLINK_STAT_TXF_EMPTY		(1 << 21)
-#define SLINK_STAT_TXF_FULL		(1 << 20)
-#define SLINK_STAT_TXF_OVF		(1 << 19)
-#define SLINK_STAT_RXF_UNR		(1 << 18)
-#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
-/* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
-#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
-
-#define SPI_TIMEOUT		1000
-#define TEGRA_SPI_MAX_FREQ	52000000
-
 #endif	/* _TEGRA30_SPI_H_ */
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 3b1b6f8..6e72c8e 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -35,9 +35,54 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
+#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT	18
+#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL			(1 << 16)
+#define SPI_CMD_TXEN			(1 << 15)
+#define SPI_CMD_RXEN			(1 << 14)
+#define SPI_CMD_CS_VAL			(1 << 13)
+#define SPI_CMD_CS_SOFT			(1 << 12)
+#define SPI_CMD_CS_DELAY		(1 << 9)
+#define SPI_CMD_CS3_EN			(1 << 8)
+#define SPI_CMD_CS2_EN			(1 << 7)
+#define SPI_CMD_CS1_EN			(1 << 6)
+#define SPI_CMD_CS0_EN			(1 << 5)
+#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+
+#define SPI_STAT_BSY			(1 << 31)
+#define SPI_STAT_RDY			(1 << 30)
+#define SPI_STAT_RXF_FLUSH		(1 << 29)
+#define SPI_STAT_TXF_FLUSH		(1 << 28)
+#define SPI_STAT_RXF_UNR		(1 << 27)
+#define SPI_STAT_TXF_OVF		(1 << 26)
+#define SPI_STAT_RXF_EMPTY		(1 << 25)
+#define SPI_STAT_RXF_FULL		(1 << 24)
+#define SPI_STAT_TXF_EMPTY		(1 << 23)
+#define SPI_STAT_TXF_FULL		(1 << 22)
+#define SPI_STAT_SEL_TXRX_N		(1 << 16)
+#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA_SPI_MAX_FREQ	52000000
+
+struct spi_regs {
+	u32 command;	/* SPI_COMMAND_0 register  */
+	u32 status;	/* SPI_STATUS_0 register */
+	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
+	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
+	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
+	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
+	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
+};
+
 struct tegra_spi_slave {
 	struct spi_slave slave;
-	struct spi_tegra *regs;
+	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
@@ -93,7 +138,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		debug("%s: sflash is disabled\n", __func__);
 		return NULL;
 	}
-	spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
+	spi->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
 							node, "reg");
 	if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
 		debug("%s: no sflash register found\n", __func__);
@@ -136,7 +181,7 @@ void spi_init(void)
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_tegra *regs = spi->regs;
+	struct spi_regs *regs = spi->regs;
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
@@ -199,7 +244,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *data_out, void *data_in, unsigned long flags)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_tegra *regs = spi->regs;
+	struct spi_regs *regs = spi->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index c794054..f3b0964 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -33,8 +33,62 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* COMMAND */
+#define SLINK_CMD_ENB			(1 << 31)
+#define SLINK_CMD_GO			(1 << 30)
+#define SLINK_CMD_M_S			(1 << 28)
+#define SLINK_CMD_CK_SDA		(1 << 21)
+#define SLINK_CMD_CS_POL		(1 << 13)
+#define SLINK_CMD_CS_VAL		(1 << 12)
+#define SLINK_CMD_CS_SOFT		(1 << 11)
+#define SLINK_CMD_BIT_LENGTH		(1 << 4)
+#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN			(1 << 30)
+#define SLINK_CMD2_RXEN			(1 << 31)
+#define SLINK_CMD2_SS_EN		(1 << 18)
+#define SLINK_CMD2_SS_EN_SHIFT		18
+#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
+/* STATUS */
+#define SLINK_STAT_BSY			(1 << 31)
+#define SLINK_STAT_RDY			(1 << 30)
+#define SLINK_STAT_ERR			(1 << 29)
+#define SLINK_STAT_RXF_FLUSH		(1 << 27)
+#define SLINK_STAT_TXF_FLUSH		(1 << 26)
+#define SLINK_STAT_RXF_OVF		(1 << 25)
+#define SLINK_STAT_TXF_UNR		(1 << 24)
+#define SLINK_STAT_RXF_EMPTY		(1 << 23)
+#define SLINK_STAT_RXF_FULL		(1 << 22)
+#define SLINK_STAT_TXF_EMPTY		(1 << 21)
+#define SLINK_STAT_TXF_FULL		(1 << 20)
+#define SLINK_STAT_TXF_OVF		(1 << 19)
+#define SLINK_STAT_RXF_UNR		(1 << 18)
+#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
+#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA_SPI_MAX_FREQ	52000000
+
+struct spi_regs {
+	u32 command;	/* SLINK_COMMAND_0 register  */
+	u32 command2;	/* SLINK_COMMAND2_0 reg */
+	u32 status;	/* SLINK_STATUS_0 register */
+	u32 reserved;	/* Reserved offset 0C */
+	u32 mas_data;	/* SLINK_MAS_DATA_0 reg */
+	u32 slav_data;	/* SLINK_SLAVE_DATA_0 reg */
+	u32 dma_ctl;	/* SLINK_DMA_CTL_0 register */
+	u32 status2;	/* SLINK_STATUS2_0 reg */
+	u32 rsvd[56];	/* 0x20 to 0xFF reserved */
+	u32 tx_fifo;	/* SLINK_TX_FIFO_0 reg off 100h */
+	u32 rsvd2[31];	/* 0x104 to 0x17F reserved */
+	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
+};
+
 struct tegra_spi_ctrl {
-	struct slink_tegra *regs;
+	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
@@ -128,8 +182,8 @@ void spi_init(void)
 		ctrl = &spi_ctrls[i];
 		node = node_list[i];
 
-		ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
-								   node, "reg");
+		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
+								node, "reg");
 		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
 			debug("%s: no slink register found\n", __func__);
 			continue;
@@ -156,7 +210,7 @@ void spi_init(void)
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct slink_tegra *regs = spi->ctrl->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
@@ -185,7 +239,7 @@ void spi_release_bus(struct spi_slave *slave)
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct slink_tegra *regs = spi->ctrl->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
 	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
@@ -194,7 +248,7 @@ void spi_cs_activate(struct spi_slave *slave)
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct slink_tegra *regs = spi->ctrl->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
 	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
@@ -204,7 +258,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *data_out, void *data_in, unsigned long flags)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct slink_tegra *regs = spi->ctrl->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
-- 
1.7.10.4

[U-Boot] [PATCH v2 05/13] tegra20: spi: move fdt probe to spi_init

[Allen Martin]

Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 drivers/spi/tegra20_sflash.c |  110 +++++++++++++++++++++++++-----------------
 1 file changed, 67 insertions(+), 43 deletions(-)

diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 6e72c8e..bb1e57d 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012 NVIDIA Corporation
+ * Copyright (c) 2010-2013 NVIDIA Corporation
  * With help from the mpc8xxx SPI driver
  * With more help from omap3_spi SPI driver
  *
@@ -80,14 +80,22 @@ struct spi_regs {
 	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
 };
 
-struct tegra_spi_slave {
-	struct spi_slave slave;
+struct tegra_spi_ctrl {
 	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
+	int valid;
+};
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct tegra_spi_ctrl *ctrl;
 };
 
+/* tegra20 only supports one SFLASH controller */
+static struct tegra_spi_ctrl spi_ctrls[1];
+
 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
 {
 	return container_of(slave, struct tegra_spi_slave, slave);
@@ -106,7 +114,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	struct tegra_spi_slave *spi;
-	int node;
 
 	if (!spi_cs_is_valid(bus, cs)) {
 		printf("SPI error: unsupported bus %d / chip select %d\n",
@@ -127,41 +134,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	}
 	spi->slave.bus = bus;
 	spi->slave.cs = cs;
-
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-				      COMPAT_NVIDIA_TEGRA20_SFLASH);
-	if (node < 0) {
-		debug("%s: cannot locate sflash node\n", __func__);
-		return NULL;
-	}
-	if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
-		debug("%s: sflash is disabled\n", __func__);
-		return NULL;
-	}
-	spi->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
-							node, "reg");
-	if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
-		debug("%s: no sflash register found\n", __func__);
+	spi->ctrl = &spi_ctrls[bus];
+	if (!spi->ctrl) {
+		printf("SPI error: could not find controller for bus %d\n",
+		       bus);
 		return NULL;
 	}
-	spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
-	if (!spi->freq) {
-		debug("%s: no sflash max frequency found\n", __func__);
-		return NULL;
-	}
-	spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-	if (spi->periph_id == PERIPH_ID_NONE) {
-		debug("%s: could not decode periph id\n", __func__);
-		return NULL;
-	}
-	if (max_hz < spi->freq) {
+
+	if (max_hz < spi->ctrl->freq) {
 		debug("%s: limiting frequency from %u to %u\n", __func__,
-		      spi->freq, max_hz);
-		spi->freq = max_hz;
+		      spi->ctrl->freq, max_hz);
+		spi->ctrl->freq = max_hz;
 	}
-	debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
-	      __func__, spi->regs, spi->freq, spi->periph_id);
-	spi->mode = mode;
+	spi->ctrl->mode = mode;
 
 	return &spi->slave;
 }
@@ -175,17 +160,54 @@ void spi_free_slave(struct spi_slave *slave)
 
 void spi_init(void)
 {
-	/* do nothing */
+	struct tegra_spi_ctrl *ctrl;
+	int i;
+	int node = 0;
+	int count;
+	int node_list[1];
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
+					   COMPAT_NVIDIA_TEGRA20_SFLASH,
+					   node_list,
+					   1);
+	for (i = 0; i < count; i++) {
+		ctrl = &spi_ctrls[i];
+		node = node_list[i];
+
+		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
+								node, "reg");
+		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
+			debug("%s: no slink register found\n", __func__);
+			continue;
+		}
+		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
+					    "spi-max-frequency", 0);
+		if (!ctrl->freq) {
+			debug("%s: no slink max frequency found\n", __func__);
+			continue;
+		}
+
+		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+		if (ctrl->periph_id == PERIPH_ID_NONE) {
+			debug("%s: could not decode periph id\n", __func__);
+			continue;
+		}
+		ctrl->valid = 1;
+
+		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+	}
 }
 
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
+	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
+			       spi->ctrl->freq);
 
 	/* Clear stale status here */
 	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
@@ -196,8 +218,8 @@ int spi_claim_bus(struct spi_slave *slave)
 	/*
 	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
 	 */
-	reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
-	if (spi->mode & 2)
+	reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+	if (spi->ctrl->mode & 2)
 		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
 	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
 		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
@@ -227,24 +249,26 @@ void spi_release_bus(struct spi_slave *slave)
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
 
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
-	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+	setbits_le32(&regs->command, SPI_CMD_CS_VAL);
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
 
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
-	clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+	clrbits_le32(&regs->command, SPI_CMD_CS_VAL);
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *data_out, void *data_in, unsigned long flags)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->regs;
+	struct spi_regs *regs = spi->ctrl->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
-- 
1.7.10.4

[U-Boot] [PATCH v2 06/13] spi: add common fdt SPI driver interface

[Allen Martin]

Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h |   11 ++
 arch/arm/include/asm/arch-tegra20/tegra20_slink.h  |   11 ++
 board/nvidia/common/board.c                        |    2 +-
 drivers/spi/Makefile                               |    1 +
 drivers/spi/fdt_spi.c                              |  171 ++++++++++++++++++++
 drivers/spi/tegra20_sflash.c                       |   41 ++---
 drivers/spi/tegra20_slink.c                        |   29 ++--
 include/configs/tegra-common-post.h                |    4 +
 8 files changed, 224 insertions(+), 46 deletions(-)
 create mode 100644 drivers/spi/fdt_spi.c

diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
index 28775db..e8cc68c 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -27,4 +27,15 @@
 
 #include <asm/types.h>
 
+int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra20_spi_free_slave(struct spi_slave *slave);
+int tegra20_spi_init(int *node_list, int count);
+int tegra20_spi_claim_bus(struct spi_slave *slave);
+void tegra20_spi_cs_activate(struct spi_slave *slave);
+void tegra20_spi_cs_deactivate(struct spi_slave *slave);
+int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *data_out, void *data_in, unsigned long flags);
+
 #endif	/* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
index fe8b534..5aa74dd 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -27,4 +27,15 @@
 
 #include <asm/types.h>
 
+int tegra30_spi_init(int *node_list, int count);
+int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra30_spi_free_slave(struct spi_slave *slave);
+int tegra30_spi_claim_bus(struct spi_slave *slave);
+void tegra30_spi_cs_activate(struct spi_slave *slave);
+void tegra30_spi_cs_deactivate(struct spi_slave *slave);
+int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		     const void *data_out, void *data_in, unsigned long flags);
+
 #endif	/* _TEGRA30_SPI_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 87a418b..8d7a227 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -132,7 +132,7 @@ int board_init(void)
 	clock_init();
 	clock_verify();
 
-#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
+#ifdef CONFIG_FDT_SPI
 	pin_mux_spi();
 	spi_init();
 #endif
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8470c34..3527729 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -45,6 +45,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
+COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
new file mode 100644
index 0000000..c6ae719
--- /dev/null
+++ b/drivers/spi/fdt_spi.c
@@ -0,0 +1,171 @@
+/*
+ * Common fdt based SPI driver front end
+ *
+ * Copyright (c) 2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra20/tegra20_sflash.h>
+#include <asm/arch-tegra20/tegra20_slink.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fdt_spi_driver {
+	int compat;
+	int max_ctrls;
+	int (*init)(int *node_list, int count);
+	int (*claim_bus)(struct spi_slave *slave);
+	int (*release_bus)(struct spi_slave *slave);
+	int (*cs_is_valid)(unsigned int bus, unsigned int cs);
+	struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs,
+					unsigned int max_hz, unsigned int mode);
+	void (*free_slave)(struct spi_slave *slave);
+	void (*cs_activate)(struct spi_slave *slave);
+	void (*cs_deactivate)(struct spi_slave *slave);
+	int (*xfer)(struct spi_slave *slave, unsigned int bitlen,
+		    const void *data_out, void *data_in, unsigned long flags);
+};
+
+static struct fdt_spi_driver fdt_spi_drivers[] = {
+#ifdef CONFIG_TEGRA20_SFLASH
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA20_SFLASH,
+		.max_ctrls	= 1,
+		.init		= tegra20_spi_init,
+		.claim_bus	= tegra20_spi_claim_bus,
+		.cs_is_valid	= tegra20_spi_cs_is_valid,
+		.setup_slave	= tegra20_spi_setup_slave,
+		.free_slave	= tegra20_spi_free_slave,
+		.cs_activate	= tegra20_spi_cs_activate,
+		.cs_deactivate	= tegra20_spi_cs_deactivate,
+		.xfer		= tegra20_spi_xfer,
+	},
+#endif
+#ifdef CONFIG_TEGRA20_SLINK
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA20_SLINK,
+		.max_ctrls	= CONFIG_TEGRA_SLINK_CTRLS,
+		.init		= tegra30_spi_init,
+		.claim_bus	= tegra30_spi_claim_bus,
+		.cs_is_valid	= tegra30_spi_cs_is_valid,
+		.setup_slave	= tegra30_spi_setup_slave,
+		.free_slave	= tegra30_spi_free_slave,
+		.cs_activate	= tegra30_spi_cs_activate,
+		.cs_deactivate	= tegra30_spi_cs_deactivate,
+		.xfer		= tegra30_spi_xfer,
+	},
+#endif
+};
+
+static struct fdt_spi_driver *driver;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	if (!driver)
+		return 0;
+	else if (!driver->cs_is_valid)
+		return 1;
+	else
+		return driver->cs_is_valid(bus, cs);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	if (!driver || !driver->setup_slave)
+		return NULL;
+
+	return driver->setup_slave(bus, cs, max_hz, mode);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	if (driver && driver->free_slave)
+		return driver->free_slave(slave);
+}
+
+static int spi_init_driver(struct fdt_spi_driver *driver)
+{
+	int count;
+	int node_list[driver->max_ctrls];
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
+					   driver->compat,
+					   node_list,
+					   driver->max_ctrls);
+	return driver->init(node_list, count);
+}
+
+void spi_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) {
+		driver = &fdt_spi_drivers[i];
+		if (!spi_init_driver(driver))
+			break;
+	}
+	if (i == ARRAY_SIZE(fdt_spi_drivers))
+		driver = NULL;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	if (!driver)
+		return 1;
+	if (!driver->claim_bus)
+		return 0;
+
+	return driver->claim_bus(slave);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	if (driver && driver->release_bus)
+		driver->release_bus(slave);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	if (driver && driver->cs_activate)
+		driver->cs_activate(slave);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	if (driver && driver->cs_deactivate)
+		driver->cs_deactivate(slave);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *data_out, void *data_in, unsigned long flags)
+{
+	if (!driver || !driver->xfer)
+		return -1;
+
+	return driver->xfer(slave, bitlen, data_out, data_in, flags);
+}
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index bb1e57d..a4e6c9a 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -101,7 +101,7 @@ static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
 	return container_of(slave, struct tegra_spi_slave, slave);
 }
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
 	if (bus != 0 || cs != 0)
@@ -110,8 +110,8 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 		return 1;
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
+struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
 {
 	struct tegra_spi_slave *spi;
 
@@ -151,25 +151,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	return &spi->slave;
 }
 
-void spi_free_slave(struct spi_slave *slave)
+void tegra20_spi_free_slave(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 
 	free(spi);
 }
 
-void spi_init(void)
+int tegra20_spi_init(int *node_list, int count)
 {
 	struct tegra_spi_ctrl *ctrl;
 	int i;
 	int node = 0;
-	int count;
-	int node_list[1];
+	int found = 0;
 
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
-					   COMPAT_NVIDIA_TEGRA20_SFLASH,
-					   node_list,
-					   1);
 	for (i = 0; i < count; i++) {
 		ctrl = &spi_ctrls[i];
 		node = node_list[i];
@@ -193,13 +188,15 @@ void spi_init(void)
 			continue;
 		}
 		ctrl->valid = 1;
+		found = 1;
 
 		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
 		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
 	}
+	return !found;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+int tegra20_spi_claim_bus(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -213,7 +210,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
 		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
 	writel(reg, &regs->status);
-	debug("spi_init: STATUS = %08x\n", readl(&regs->status));
+	debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
 
 	/*
 	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
@@ -223,7 +220,7 @@ int spi_claim_bus(struct spi_slave *slave)
 		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
 	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
 		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
-	debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
+	debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
 
 	/*
 	 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
@@ -236,17 +233,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	return 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
-{
-	/*
-	 * We can't release UART_DISABLE and set pinmux to UART4 here since
-	 * some code (e,g, spi_flash_probe) uses printf() while the SPI
-	 * bus is held. That is arguably bad, but it has the advantage of
-	 * already being in the source tree.
-	 */
-}
-
-void spi_cs_activate(struct spi_slave *slave)
+void tegra20_spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -255,7 +242,7 @@ void spi_cs_activate(struct spi_slave *slave)
 	setbits_le32(&regs->command, SPI_CMD_CS_VAL);
 }
 
-void spi_cs_deactivate(struct spi_slave *slave)
+void tegra20_spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -264,7 +251,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	clrbits_le32(&regs->command, SPI_CMD_CS_VAL);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *data_out, void *data_in, unsigned long flags)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index f3b0964..2ef2eb8 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -107,7 +107,7 @@ static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
 	return container_of(slave, struct tegra_spi_slave, slave);
 }
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
 		return 0;
@@ -115,7 +115,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 		return 1;
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	struct tegra_spi_slave *spi;
@@ -159,25 +159,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	return &spi->slave;
 }
 
-void spi_free_slave(struct spi_slave *slave)
+void tegra30_spi_free_slave(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 
 	free(spi);
 }
 
-void spi_init(void)
+int tegra30_spi_init(int *node_list, int count)
 {
 	struct tegra_spi_ctrl *ctrl;
 	int i;
 	int node = 0;
-	int count;
-	int node_list[CONFIG_TEGRA_SLINK_CTRLS];
+	int found = 0;
 
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
-					   COMPAT_NVIDIA_TEGRA20_SLINK,
-					   node_list,
-					   CONFIG_TEGRA_SLINK_CTRLS);
 	for (i = 0; i < count; i++) {
 		ctrl = &spi_ctrls[i];
 		node = node_list[i];
@@ -201,13 +196,15 @@ void spi_init(void)
 			continue;
 		}
 		ctrl->valid = 1;
+		found = 1;
 
 		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
 		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
 	}
+	return !found;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+int tegra30_spi_claim_bus(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -232,11 +229,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	return 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-void spi_cs_activate(struct spi_slave *slave)
+void tegra30_spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -245,7 +238,7 @@ void spi_cs_activate(struct spi_slave *slave)
 	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
 }
 
-void spi_cs_deactivate(struct spi_slave *slave)
+void tegra30_spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 	struct spi_regs *regs = spi->ctrl->regs;
@@ -254,7 +247,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *data_out, void *data_in, unsigned long flags)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index f2a70b1..d967a75 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -150,6 +150,10 @@
 	MEM_LAYOUT_ENV_SETTINGS \
 	BOOTCMDS_COMMON
 
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
+#define CONFIG_FDT_SPI
+#endif
+
 /* overrides for SPL build here */
 #ifdef CONFIG_SPL_BUILD
 
-- 
1.7.10.4

[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW

[Allen Martin]

Add support for Winbond W25Q32DW 32Mbit part

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 drivers/mtd/spi/winbond.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index 4418302..3560fcb 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.name			= "W25Q80",
 	},
 	{
+		.id			= 0x6016,
+		.nr_blocks		= 512,
+		.name			= "W25Q32DW",
+	},
+	{
 		.id			= 0x6017,
 		.nr_blocks		= 128,
 		.name			= "W25Q64DW",
-- 
1.7.10.4

[U-Boot] [PATCH v2 08/13] tegra114: fdt: add compatible string for tegra114 SPI ctrl

[Allen Martin]

Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 include/fdtdec.h |    1 +
 lib/fdtdec.c     |    1 +
 2 files changed, 2 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 2189483..19c9707 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -75,6 +75,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
 	COMPAT_NVIDIA_TEGRA20_SLINK,	/* Tegra 2 SPI SLINK controller */
+	COMPAT_NVIDIA_TEGRA114_SPI,	/* Tegra 114 SPI controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
 	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 43f29f5..c56f7d4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -50,6 +50,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
 	COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
+	COMPAT(NVIDIA_TEGRA114_SPI, "nvidia,tegra114-spi"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
 	COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
-- 
1.7.10.4

[U-Boot] [PATCH v2 09/13] tegra114: fdt: add apbdma block

[Allen Martin]

Add node for apbdma controller hardware.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/dts/tegra114.dtsi |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index dfeac53..92e69f6 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -17,6 +17,43 @@
 		#clock-cells = <1>;
 	};
 
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
 	gpio: gpio {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-- 
1.7.10.4

[U-Boot] [PATCH v2 10/13] tegra114: fdt: add SPI blocks

[Allen Martin]

Add nodes for t114 SPI controller hardware

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/dts/tegra114.dtsi |   72 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 92e69f6..64e2e083 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -120,4 +120,76 @@
 		clocks = <&tegra_car 47>;
 		status = "disabled";
 	};
+
+	spi at 7000d400 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
+	};
+
+	spi at 7000d600 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
+	};
+
+	spi at 7000d800 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
+	};
+
+	spi at 7000da00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
+	};
+
+	spi at 7000dc00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
+	};
+
+	spi at 7000de00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
+	};
 };
-- 
1.7.10.4

[U-Boot] [PATCH v2 11/13] tegra114: dalmore: fdt: enable dalmore SPI controller

[Allen Martin]

Dalmore has a SPI flash part attached to controller 4, so enable
controller 4 and set to 25MHz.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 board/nvidia/dts/tegra114-dalmore.dts |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
index 3e1e1ea..a446713 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -35,4 +35,9 @@
 		status = "okay";
 		clock-frequency = <400000>;
 	};
+
+	spi at 7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
 };
-- 
1.7.10.4

[U-Boot] [PATCH v2 12/13] tegra114: add SPI driver

[Allen Martin]

Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/include/asm/arch-tegra114/tegra114_spi.h |   41 +++
 drivers/spi/Makefile                              |    1 +
 drivers/spi/fdt_spi.c                             |   15 +
 drivers/spi/tegra114_spi.c                        |  405 +++++++++++++++++++++
 include/configs/tegra-common-post.h               |    2 +-
 5 files changed, 463 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
 create mode 100644 drivers/spi/tegra114_spi.c

diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
new file mode 100644
index 0000000..48197bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
@@ -0,0 +1,41 @@
+/*
+ * NVIDIA Tegra SPI controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA114_SPI_H_
+#define _TEGRA114_SPI_H_
+
+#include <asm/types.h>
+
+int tegra114_spi_init(int *node_list, int count);
+int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra114_spi_free_slave(struct spi_slave *slave);
+int tegra114_spi_claim_bus(struct spi_slave *slave);
+void tegra114_spi_cs_activate(struct spi_slave *slave);
+void tegra114_spi_cs_deactivate(struct spi_slave *slave);
+int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		     const void *data_out, void *data_in, unsigned long flags);
+
+#endif	/* _TEGRA114_SPI_H_ */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3527729..57802ae 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -48,6 +48,7 @@ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
index c6ae719..58f139a 100644
--- a/drivers/spi/fdt_spi.c
+++ b/drivers/spi/fdt_spi.c
@@ -29,6 +29,7 @@
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra20/tegra20_sflash.h>
 #include <asm/arch-tegra20/tegra20_slink.h>
+#include <asm/arch-tegra114/tegra114_spi.h>
 #include <spi.h>
 #include <fdtdec.h>
 
@@ -79,6 +80,20 @@ static struct fdt_spi_driver fdt_spi_drivers[] = {
 		.xfer		= tegra30_spi_xfer,
 	},
 #endif
+#ifdef CONFIG_TEGRA114_SPI
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA114_SPI,
+		.max_ctrls	= CONFIG_TEGRA114_SPI_CTRLS,
+		.init		= tegra114_spi_init,
+		.claim_bus	= tegra114_spi_claim_bus,
+		.cs_is_valid	= tegra114_spi_cs_is_valid,
+		.setup_slave	= tegra114_spi_setup_slave,
+		.free_slave	= tegra114_spi_free_slave,
+		.cs_activate	= tegra114_spi_cs_activate,
+		.cs_deactivate	= tegra114_spi_cs_deactivate,
+		.xfer		= tegra114_spi_xfer,
+	},
+#endif
 };
 
 static struct fdt_spi_driver *driver;
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
new file mode 100644
index 0000000..b11a0a1
--- /dev/null
+++ b/drivers/spi/tegra114_spi.c
@@ -0,0 +1,405 @@
+/*
+ * NVIDIA Tegra SPI controller (T114 and later)
+ *
+ * Copyright (c) 2010-2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra114/tegra114_spi.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* COMMAND1 */
+#define SPI_CMD1_GO			(1 << 31)
+#define SPI_CMD1_M_S			(1 << 30)
+#define SPI_CMD1_MODE_MASK		0x3
+#define SPI_CMD1_MODE_SHIFT		28
+#define SPI_CMD1_CS_SEL_MASK		0x3
+#define SPI_CMD1_CS_SEL_SHIFT		26
+#define SPI_CMD1_CS_POL_INACTIVE3	(1 << 25)
+#define SPI_CMD1_CS_POL_INACTIVE2	(1 << 24)
+#define SPI_CMD1_CS_POL_INACTIVE1	(1 << 23)
+#define SPI_CMD1_CS_POL_INACTIVE0	(1 << 22)
+#define SPI_CMD1_CS_SW_HW		(1 << 21)
+#define SPI_CMD1_CS_SW_VAL		(1 << 20)
+#define SPI_CMD1_IDLE_SDA_MASK		0x3
+#define SPI_CMD1_IDLE_SDA_SHIFT		18
+#define SPI_CMD1_BIDIR			(1 << 17)
+#define SPI_CMD1_LSBI_FE		(1 << 16)
+#define SPI_CMD1_LSBY_FE		(1 << 15)
+#define SPI_CMD1_BOTH_EN_BIT		(1 << 14)
+#define SPI_CMD1_BOTH_EN_BYTE		(1 << 13)
+#define SPI_CMD1_RX_EN			(1 << 12)
+#define SPI_CMD1_TX_EN			(1 << 11)
+#define SPI_CMD1_PACKED			(1 << 5)
+#define SPI_CMD1_BIT_LEN_MASK		0x1F
+#define SPI_CMD1_BIT_LEN_SHIFT		0
+
+/* COMMAND2 */
+#define SPI_CMD2_TX_CLK_TAP_DELAY	(1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
+#define SPI_CMD2_RX_CLK_TAP_DELAY	(1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
+
+/* TRANSFER STATUS */
+#define SPI_XFER_STS_RDY		(1 << 30)
+
+/* FIFO STATUS */
+#define SPI_FIFO_STS_CS_INACTIVE	(1 << 31)
+#define SPI_FIFO_STS_FRAME_END		(1 << 30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH	(1 << 15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH	(1 << 14)
+#define SPI_FIFO_STS_ERR		(1 << 8)
+#define SPI_FIFO_STS_TX_FIFO_OVF	(1 << 7)
+#define SPI_FIFO_STS_TX_FIFO_UNR	(1 << 6)
+#define SPI_FIFO_STS_RX_FIFO_OVF	(1 << 5)
+#define SPI_FIFO_STS_RX_FIFO_UNR	(1 << 4)
+#define SPI_FIFO_STS_TX_FIFO_FULL	(1 << 3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY	(1 << 2)
+#define SPI_FIFO_STS_RX_FIFO_FULL	(1 << 1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY	(1 << 0)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA_SPI_MAX_FREQ	52000000
+
+struct spi_regs {
+	u32 command1;	/* 000:SPI_COMMAND1 register */
+	u32 command2;	/* 004:SPI_COMMAND2 register */
+	u32 timing1;	/* 008:SPI_CS_TIM1 register */
+	u32 timing2;	/* 00c:SPI_CS_TIM2 register */
+	u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
+	u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
+	u32 tx_data;	/* 018:SPI_TX_DATA register */
+	u32 rx_data;	/* 01c:SPI_RX_DATA register */
+	u32 dma_ctl;	/* 020:SPI_DMA_CTL register */
+	u32 dma_blk;	/* 024:SPI_DMA_BLK register */
+	u32 rsvd[56];	/* 028-107 reserved */
+	u32 tx_fifo;	/* 108:SPI_FIFO1 register */
+	u32 rsvd2[31];	/* 10c-187 reserved */
+	u32 rx_fifo;	/* 188:SPI_FIFO2 register */
+	u32 spare_ctl;	/* 18c:SPI_SPARE_CTRL register */
+};
+
+struct tegra_spi_ctrl {
+	struct spi_regs *regs;
+	unsigned int freq;
+	unsigned int mode;
+	int periph_id;
+	int valid;
+};
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct tegra_spi_ctrl *ctrl;
+};
+
+static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
+		return 0;
+	else
+		return 1;
+}
+
+struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct tegra_spi_slave *spi;
+
+	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
+		bus, cs, max_hz, mode);
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		printf("SPI error: unsupported bus %d / chip select %d\n",
+		       bus, cs);
+		return NULL;
+	}
+
+	if (max_hz > TEGRA_SPI_MAX_FREQ) {
+		printf("SPI error: unsupported frequency %d Hz. Max frequency"
+			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
+		return NULL;
+	}
+
+	spi = malloc(sizeof(struct tegra_spi_slave));
+	if (!spi) {
+		printf("SPI error: malloc of SPI structure failed\n");
+		return NULL;
+	}
+	spi->slave.bus = bus;
+	spi->slave.cs = cs;
+	spi->ctrl = &spi_ctrls[bus];
+	if (!spi->ctrl) {
+		printf("SPI error: could not find controller for bus %d\n",
+		       bus);
+		return NULL;
+	}
+
+	if (max_hz < spi->ctrl->freq) {
+		debug("%s: limiting frequency from %u to %u\n", __func__,
+		      spi->ctrl->freq, max_hz);
+		spi->ctrl->freq = max_hz;
+	}
+	spi->ctrl->mode = mode;
+
+	return &spi->slave;
+}
+
+void tegra114_spi_free_slave(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	free(spi);
+}
+
+int tegra114_spi_init(int *node_list, int count)
+{
+	struct tegra_spi_ctrl *ctrl;
+	int i;
+	int node = 0;
+	int found = 0;
+
+	for (i = 0; i < count; i++) {
+		ctrl = &spi_ctrls[i];
+		node = node_list[i];
+
+		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
+								 node, "reg");
+		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
+			debug("%s: no spi register found\n", __func__);
+			continue;
+		}
+		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
+					    "spi-max-frequency", 0);
+		if (!ctrl->freq) {
+			debug("%s: no spi max frequency found\n", __func__);
+			continue;
+		}
+
+		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+		if (ctrl->periph_id == PERIPH_ID_NONE) {
+			debug("%s: could not decode periph id\n", __func__);
+			continue;
+		}
+		ctrl->valid = 1;
+		found = 1;
+
+		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+	}
+
+	return !found;
+}
+
+int tegra114_spi_claim_bus(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
+
+	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
+	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
+			       spi->ctrl->freq);
+
+	/* Clear stale status here */
+	setbits_le32(&regs->fifo_status,
+		     SPI_FIFO_STS_ERR		|
+		     SPI_FIFO_STS_TX_FIFO_OVF	|
+		     SPI_FIFO_STS_TX_FIFO_UNR	|
+		     SPI_FIFO_STS_RX_FIFO_OVF	|
+		     SPI_FIFO_STS_RX_FIFO_UNR	|
+		     SPI_FIFO_STS_TX_FIFO_FULL	|
+		     SPI_FIFO_STS_TX_FIFO_EMPTY	|
+		     SPI_FIFO_STS_RX_FIFO_FULL	|
+		     SPI_FIFO_STS_RX_FIFO_EMPTY);
+	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
+
+	/* Set master mode and sw controlled CS */
+	setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
+		     (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
+	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
+
+	return 0;
+}
+
+void tegra114_spi_cs_activate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
+
+	clrbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+}
+
+void tegra114_spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
+
+	setbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+}
+
+int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *data_out, void *data_in, unsigned long flags)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_regs *regs = spi->ctrl->regs;
+	u32 reg, tmpdout, tmpdin = 0;
+	const u8 *dout = data_out;
+	u8 *din = data_in;
+	int num_bytes;
+	int ret;
+
+	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+	      __func__, slave->bus, slave->cs, dout, din, bitlen);
+	if (bitlen % 8)
+		return -1;
+	num_bytes = bitlen / 8;
+
+	ret = 0;
+
+	/* clear all error status bits */
+	reg = readl(&regs->fifo_status);
+	writel(reg, &regs->fifo_status);
+
+	/* clear ready bit */
+	setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
+
+	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
+			SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
+			(slave->cs << SPI_CMD1_CS_SEL_SHIFT));
+
+	/* set xfer size to 1 block (32 bits) */
+	writel(0, &regs->dma_blk);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* handle data in 32-bit chunks */
+	while (num_bytes > 0) {
+		int bytes;
+		int is_read = 0;
+		int tm, i;
+
+		tmpdout = 0;
+		bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+		if (dout != NULL) {
+			for (i = 0; i < bytes; ++i)
+				tmpdout = (tmpdout << 8) | dout[i];
+			dout += bytes;
+		}
+
+		num_bytes -= bytes;
+
+		clrsetbits_le32(&regs->command1,
+				SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
+				(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
+		writel(tmpdout, &regs->tx_fifo);
+		setbits_le32(&regs->command1, SPI_CMD1_GO);
+
+		/*
+		 * Wait for SPI transmit FIFO to empty, or to time out.
+		 * The RX FIFO status will be read and cleared last
+		 */
+		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+			u32 fifo_status, xfer_status;
+
+			fifo_status = readl(&regs->fifo_status);
+
+			/* We can exit when we've had both RX and TX activity */
+			if (is_read &&
+			    (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY))
+				break;
+
+			xfer_status = readl(&regs->xfer_status);
+			if (!(xfer_status & SPI_XFER_STS_RDY))
+				continue;
+
+			if (fifo_status & SPI_FIFO_STS_ERR) {
+				debug("%s: got a fifo error: ", __func__);
+				if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
+					debug("tx FIFO overflow ");
+				if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
+					debug("tx FIFO underrun ");
+				if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
+					debug("rx FIFO overflow ");
+				if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
+					debug("rx FIFO underrun ");
+				if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
+					debug("tx FIFO full ");
+				if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
+					debug("tx FIFO empty ");
+				if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
+					debug("rx FIFO full ");
+				if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
+					debug("rx FIFO empty ");
+				debug("\n");
+				break;
+			}
+
+			if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
+				tmpdin = readl(&regs->rx_fifo);
+				is_read = 1;
+
+				/* swap bytes read in */
+				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						din[i] = tmpdin & 0xff;
+						tmpdin >>= 8;
+					}
+					din += bytes;
+				}
+			}
+		}
+
+		if (tm >= SPI_TIMEOUT)
+			ret = tm;
+
+		/* clear ACK RDY, etc. bits */
+		writel(readl(&regs->fifo_status), &regs->fifo_status);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
+	      __func__, tmpdin, readl(&regs->fifo_status));
+
+	if (ret) {
+		printf("%s: timeout during SPI transfer, tm %d\n",
+		       __func__, ret);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index d967a75..bf18699 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -150,7 +150,7 @@
 	MEM_LAYOUT_ENV_SETTINGS \
 	BOOTCMDS_COMMON
 
-#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
 #define CONFIG_FDT_SPI
 #endif
 
-- 
1.7.10.4

[U-Boot] [PATCH v2 13/13] tegra114: dalmore: config: enable SPI

[Allen Martin]

Turn on SPI in dalmore config file

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 include/configs/dalmore.h |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index b1a6e34..c7deea5 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -54,6 +54,17 @@
 
 #define MACH_TYPE_DALMORE	4304	/* not yet in mach-types.h */
 
+/* SPI */
+#define CONFIG_TEGRA114_SPI
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
-- 
1.7.10.4

[U-Boot] [PATCH v2 00/13] tegra114 SPI driver

[Tom Warren]

Allen,

> -----Original Message-----
> From: Allen Martin [mailto:amartin at nvidia.com]
> Sent: Saturday, March 16, 2013 9:58 PM
> To: Tom Warren; swarren at wwwdotorg.org; sjg at chromium.org
> Cc: u-boot at lists.denx.de; Allen Martin
> Subject: [PATCH v2 00/13] tegra114 SPI driver
> 
> This series pulls fdt functionality from the existing tegra20 and
> tegra30 SPI drivers into a new common fdt SPI driver front end, then adds a
> new tegra114 SPI driver as an additional client of the fdt SPI driver.

Applies cleanly to current u-boot-tegra/next. All Tegra boards build OK.
Tested on Seaboard, Cardhu and Dalmore AOK (no more 'sf' or 'sspi' on Seaboard).

For the series:
Tested-by: Tom Warren <twarren@nvidia.com>

I'll apply this to u-boot-tegra/next under the assumption that it won't require any more work.

Thanks,

Tom
> 
> Changes in v2:
>  - Added a patch to remove SPI/UART switch support, this was only
>    useful for seaboard, which was never manufactured
>  - Renamed tegra_sflash and tegra_slink to tegra20_sflash and
>    tegra20_slink
>  - Moved SPI register definitions from header files into SPI driver
>    files, since those are the only users of those registers.
>  - Removed patch to add CAR node to dt, equivalent patch was already
>    upstreamed.
> 
> Allen Martin (13):
>   tegra: remove support for UART SPI switch
>   tegra: spi: rename tegra SPI drivers
>   tegra: spi: remove non fdt support
>   tegra: spi: pull register structs out of headers
>   tegra20: spi: move fdt probe to spi_init
>   spi: add common fdt SPI driver interface
>   sf: winbond: add W25Q32DW
>   tegra114: fdt: add compatible string for tegra114 SPI ctrl
>   tegra114: fdt: add apbdma block
>   tegra114: fdt: add SPI blocks
>   tegra114: dalmore: fdt: enable dalmore SPI controller
>   tegra114: add SPI driver
>   tegra114: dalmore: config: enable SPI
> 
>  arch/arm/dts/tegra114.dtsi                         |  109 ++++++
>  arch/arm/include/asm/arch-tegra/board.h            |    3 +-
>  arch/arm/include/asm/arch-tegra/tegra_slink.h      |   84 ----
>  arch/arm/include/asm/arch-tegra/tegra_spi.h        |   75 ----
>  arch/arm/include/asm/arch-tegra114/tegra114_spi.h  |   41 ++
>  arch/arm/include/asm/arch-tegra20/tegra20_sflash.h |   41 ++
>  arch/arm/include/asm/arch-tegra20/tegra20_slink.h  |   41 ++
>  .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 ---
>  board/nvidia/common/board.c                        |    5 +-
>  board/nvidia/common/common.mk                      |    1 -
>  board/nvidia/common/uart-spi-switch.c              |  125 ------
>  board/nvidia/dts/tegra114-dalmore.dts              |    5 +
>  board/nvidia/seaboard/seaboard.c                   |    2 +-
>  drivers/mtd/spi/winbond.c                          |    5 +
>  drivers/spi/Makefile                               |    6 +-
>  drivers/spi/fdt_spi.c                              |  186 +++++++++
>  drivers/spi/tegra114_spi.c                         |  405 ++++++++++++++++++++
>  drivers/spi/{tegra_spi.c => tegra20_sflash.c}      |  215 ++++++-----
>  drivers/spi/{tegra_slink.c => tegra20_slink.c}     |  128 ++++---
>  include/configs/cardhu.h                           |    2 +-
>  include/configs/dalmore.h                          |   11 +
>  include/configs/tegra-common-post.h                |    4 +
>  include/configs/trimslice.h                        |    2 +-
>  include/fdtdec.h                                   |    1 +
>  lib/fdtdec.c                                       |    1 +
>  25 files changed, 1054 insertions(+), 490 deletions(-)  delete mode 100644
> arch/arm/include/asm/arch-tegra/tegra_slink.h
>  delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h
>  create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
>  create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
>  create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_slink.h
>  delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
>  delete mode 100644 board/nvidia/common/uart-spi-switch.c
>  create mode 100644 drivers/spi/fdt_spi.c  create mode 100644
> drivers/spi/tegra114_spi.c  rename drivers/spi/{tegra_spi.c =>
> tegra20_sflash.c} (57%)  rename drivers/spi/{tegra_slink.c => tegra20_slink.c}
> (72%)
> 
> --
> 1.7.10.4

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[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch

[Stephen Warren]

On 03/16/2013 10:58 PM, Allen Martin wrote:
> This feature was only used for tegra20 seaboard that had a pinmux
> conflict on the SPI pins.  These boards were never manufactured, so
> remove this support to clean up SPI driver.

> diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c

> @@ -175,16 +168,8 @@ int spi_claim_bus(struct spi_slave *slave)
>  	 */
>  	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
>  	pinmux_tristate_disable(PINGRP_LSPI);
> +	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);

As a note for future cleanup, all this pinmux stuff should be moved out
of the SPI driver into the board file's initialization functions.

[U-Boot] [PATCH v2 00/13] tegra114 SPI driver

[Stephen Warren]

On 03/16/2013 10:58 PM, Allen Martin wrote:
> This series pulls fdt functionality from the existing tegra20 and
> tegra30 SPI drivers into a new common fdt SPI driver front end,
> then adds a new tegra114 SPI driver as an additional client of
> the fdt SPI driver.

The series,

Reviewed-by: Stephen Warren <swarren@nvidia.com>

There were quite a few places in commit descriptions and perhaps
comments where we should s/{t,tegra}(\d+)/Tegra\1/i though.

[U-Boot] [PATCH v2 06/13] spi: add common fdt SPI driver interface

[Stephen Warren]

On 03/16/2013 10:58 PM, Allen Martin wrote:
> Add a common interface to fdt based SPI drivers.  Each driver is
> represented by a table entry in fdt_spi_drivers[].  If there are
> multiple SPI drivers in the table, the first driver to return success
> from spi_init() will be registered as the SPI driver.

> diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c

> +static struct fdt_spi_driver fdt_spi_drivers[] = {
> +#ifdef CONFIG_TEGRA20_SFLASH
> +	{
> +		.compat		= COMPAT_NVIDIA_TEGRA20_SFLASH,
> +		.max_ctrls	= 1,
> +		.init		= tegra20_spi_init,
> +		.claim_bus	= tegra20_spi_claim_bus,
> +		.cs_is_valid	= tegra20_spi_cs_is_valid,
> +		.setup_slave	= tegra20_spi_setup_slave,
> +		.free_slave	= tegra20_spi_free_slave,
> +		.cs_activate	= tegra20_spi_cs_activate,
> +		.cs_deactivate	= tegra20_spi_cs_deactivate,
> +		.xfer		= tegra20_spi_xfer,
> +	},
> +#endif
> +#ifdef CONFIG_TEGRA20_SLINK
> +	{
> +		.compat		= COMPAT_NVIDIA_TEGRA20_SLINK,
> +		.max_ctrls	= CONFIG_TEGRA_SLINK_CTRLS,
> +		.init		= tegra30_spi_init,
> +		.claim_bus	= tegra30_spi_claim_bus,
> +		.cs_is_valid	= tegra30_spi_cs_is_valid,
> +		.setup_slave	= tegra30_spi_setup_slave,
> +		.free_slave	= tegra30_spi_free_slave,
> +		.cs_activate	= tegra30_spi_cs_activate,
> +		.cs_deactivate	= tegra30_spi_cs_deactivate,
> +		.xfer		= tegra30_spi_xfer,
> +	},
> +#endif
> +};

In the future, it would be nice if we could build up that table
automatically, with each driver providing its own struct inside the
driver file, and using e.g. linker scripts to piece together the structs
into one large table. That would avoid the need to list each one here,
and to prototype all those functions in a header file.

It'd also be nice to allow multiple driver to be active at once.

Still, that's certainly all something that's quite suitable for
follow-on patches later; not something that needs to be addressed in
this series.

[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch

[Simon Glass]

Hi Allen,

On Sat, Mar 16, 2013 at 9:58 PM, Allen Martin <amartin@nvidia.com> wrote:
> This feature was only used for tegra20 seaboard that had a pinmux
> conflict on the SPI pins.  These boards were never manufactured, so
> remove this support to clean up SPI driver.
>
> Signed-off-by: Allen Martin <amartin@nvidia.com>
> ---
>  arch/arm/include/asm/arch-tegra/board.h            |    3 +-
>  .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 -------
>  board/nvidia/common/board.c                        |    3 -
>  board/nvidia/common/common.mk                      |    1 -
>  board/nvidia/common/uart-spi-switch.c              |  125 --------------------
>  board/nvidia/seaboard/seaboard.c                   |    2 +-
>  drivers/spi/tegra_spi.c                            |   25 +---
>  7 files changed, 3 insertions(+), 202 deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
>  delete mode 100644 board/nvidia/common/uart-spi-switch.c

OK, maybe I need to get the T114 booting and stop using the seaboard?

Regards,
Simon

[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch

[Stephen Warren]

On 03/19/2013 01:01 PM, Simon Glass wrote:
> Hi Allen,
> 
> On Sat, Mar 16, 2013 at 9:58 PM, Allen Martin <amartin@nvidia.com> wrote:
>> This feature was only used for tegra20 seaboard that had a pinmux
>> conflict on the SPI pins.  These boards were never manufactured, so
>> remove this support to clean up SPI driver.
>>
>> Signed-off-by: Allen Martin <amartin@nvidia.com>
>> ---
>>  arch/arm/include/asm/arch-tegra/board.h            |    3 +-
>>  .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 -------
>>  board/nvidia/common/board.c                        |    3 -
>>  board/nvidia/common/common.mk                      |    1 -
>>  board/nvidia/common/uart-spi-switch.c              |  125 --------------------
>>  board/nvidia/seaboard/seaboard.c                   |    2 +-
>>  drivers/spi/tegra_spi.c                            |   25 +---
>>  7 files changed, 3 insertions(+), 202 deletions(-)
>>  delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
>>  delete mode 100644 board/nvidia/common/uart-spi-switch.c
> 
> OK, maybe I need to get the T114 booting and stop using the seaboard?

Seaboard still works perfectly after this patch (or should; I assume
Allen tested it!). The only issue is that you can't use SPI; the
assumption being that you store the BCT/bootloader in eMMC rather than
SPI and hence have no need to use SPI. SPI can be tested on other
Tegra20 board designs, such as TrimSlice (or perhaps Kaen/Aebl if
they're still around!)

[U-Boot] [PATCH v2 12/13] tegra114: add SPI driver

[Simon Glass]

Hi Allen,

On Sat, Mar 16, 2013 at 9:58 PM, Allen Martin <amartin@nvidia.com> wrote:
> Add driver for tegra114 SPI controller.  This controller is not
> compatible with either the tegra20 or tegra30 controllers, so it
> requires a new driver.
>
> Signed-off-by: Allen Martin <amartin@nvidia.com>
> ---
>  arch/arm/include/asm/arch-tegra114/tegra114_spi.h |   41 +++
>  drivers/spi/Makefile                              |    1 +
>  drivers/spi/fdt_spi.c                             |   15 +
>  drivers/spi/tegra114_spi.c                        |  405 +++++++++++++++++++++
>  include/configs/tegra-common-post.h               |    2 +-
>  5 files changed, 463 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
>  create mode 100644 drivers/spi/tegra114_spi.c
>

Assuming that my SPI patches are picked up you might want to look at:

http://patchwork.ozlabs.org/bundle/sjg/spi/

I've only had a brief look at this series, but it seems like a
reasonable thing to do. Arguable we should be using something like
driver model to implement this more generally, but that doesn't exist
so...

Regards,
Simon

[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch

[Simon Glass]

Hi Stephen,

On Tue, Mar 19, 2013 at 12:13 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 03/19/2013 01:01 PM, Simon Glass wrote:
>> Hi Allen,
>>
>> On Sat, Mar 16, 2013 at 9:58 PM, Allen Martin <amartin@nvidia.com> wrote:
>>> This feature was only used for tegra20 seaboard that had a pinmux
>>> conflict on the SPI pins.  These boards were never manufactured, so
>>> remove this support to clean up SPI driver.
>>>
>>> Signed-off-by: Allen Martin <amartin@nvidia.com>
>>> ---
>>>  arch/arm/include/asm/arch-tegra/board.h            |    3 +-
>>>  .../arm/include/asm/arch-tegra20/uart-spi-switch.h |   46 -------
>>>  board/nvidia/common/board.c                        |    3 -
>>>  board/nvidia/common/common.mk                      |    1 -
>>>  board/nvidia/common/uart-spi-switch.c              |  125 --------------------
>>>  board/nvidia/seaboard/seaboard.c                   |    2 +-
>>>  drivers/spi/tegra_spi.c                            |   25 +---
>>>  7 files changed, 3 insertions(+), 202 deletions(-)
>>>  delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
>>>  delete mode 100644 board/nvidia/common/uart-spi-switch.c
>>
>> OK, maybe I need to get the T114 booting and stop using the seaboard?
>
> Seaboard still works perfectly after this patch (or should; I assume
> Allen tested it!). The only issue is that you can't use SPI; the
> assumption being that you store the BCT/bootloader in eMMC rather than
> SPI and hence have no need to use SPI. SPI can be tested on other
> Tegra20 board designs, such as TrimSlice (or perhaps Kaen/Aebl if
> they're still around!)

OK that's no problem I think.

Regards,
Simon

[U-Boot] [PATCH v2 06/13] spi: add common fdt SPI driver interface

[Simon Glass]

Hi Stephen,

On Tue, Mar 19, 2013 at 11:24 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 03/16/2013 10:58 PM, Allen Martin wrote:
>> Add a common interface to fdt based SPI drivers.  Each driver is
>> represented by a table entry in fdt_spi_drivers[].  If there are
>> multiple SPI drivers in the table, the first driver to return success
>> from spi_init() will be registered as the SPI driver.
>
>> diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
>
>> +static struct fdt_spi_driver fdt_spi_drivers[] = {
>> +#ifdef CONFIG_TEGRA20_SFLASH
>> +     {
>> +             .compat         = COMPAT_NVIDIA_TEGRA20_SFLASH,
>> +             .max_ctrls      = 1,
>> +             .init           = tegra20_spi_init,
>> +             .claim_bus      = tegra20_spi_claim_bus,
>> +             .cs_is_valid    = tegra20_spi_cs_is_valid,
>> +             .setup_slave    = tegra20_spi_setup_slave,
>> +             .free_slave     = tegra20_spi_free_slave,
>> +             .cs_activate    = tegra20_spi_cs_activate,
>> +             .cs_deactivate  = tegra20_spi_cs_deactivate,
>> +             .xfer           = tegra20_spi_xfer,
>> +     },
>> +#endif
>> +#ifdef CONFIG_TEGRA20_SLINK
>> +     {
>> +             .compat         = COMPAT_NVIDIA_TEGRA20_SLINK,
>> +             .max_ctrls      = CONFIG_TEGRA_SLINK_CTRLS,
>> +             .init           = tegra30_spi_init,
>> +             .claim_bus      = tegra30_spi_claim_bus,
>> +             .cs_is_valid    = tegra30_spi_cs_is_valid,
>> +             .setup_slave    = tegra30_spi_setup_slave,
>> +             .free_slave     = tegra30_spi_free_slave,
>> +             .cs_activate    = tegra30_spi_cs_activate,
>> +             .cs_deactivate  = tegra30_spi_cs_deactivate,
>> +             .xfer           = tegra30_spi_xfer,
>> +     },
>> +#endif
>> +};
>
> In the future, it would be nice if we could build up that table
> automatically, with each driver providing its own struct inside the
> driver file, and using e.g. linker scripts to piece together the structs
> into one large table. That would avoid the need to list each one here,
> and to prototype all those functions in a header file.
>
> It'd also be nice to allow multiple driver to be active at once.
>
> Still, that's certainly all something that's quite suitable for
> follow-on patches later; not something that needs to be addressed in
> this series.

Agreed. This fits more with the driver model work, where the above
structure could be used as the SPI subsystem interface perhaps.

Regards,
Simon

[U-Boot] [PATCH v2 00/13] tegra114 SPI driver

[Simon Glass]

Hi,

On Tue, Mar 19, 2013 at 11:23 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 03/16/2013 10:58 PM, Allen Martin wrote:
>> This series pulls fdt functionality from the existing tegra20 and
>> tegra30 SPI drivers into a new common fdt SPI driver front end,
>> then adds a new tegra114 SPI driver as an additional client of
>> the fdt SPI driver.
>
> The series,
>
> Reviewed-by: Stephen Warren <swarren@nvidia.com>
>
> There were quite a few places in commit descriptions and perhaps
> comments where we should s/{t,tegra}(\d+)/Tegra\1/i though.

Just one request - I submitted a series (now in mainline) which adds a
function to allocate a new SPI controller. Could you please check that
your patch applies on top of that? I got a conflict on
tegra20_sflash.c I think.

Regards,
Simon

[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW

[Jagan Teki]

Hi Allen,

On Sun, Mar 17, 2013 at 10:28 AM, Allen Martin <amartin@nvidia.com> wrote:
> Add support for Winbond W25Q32DW 32Mbit part
>
> Signed-off-by: Allen Martin <amartin@nvidia.com>
> ---
>  drivers/mtd/spi/winbond.c |    5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
> index 4418302..3560fcb 100644
> --- a/drivers/mtd/spi/winbond.c
> +++ b/drivers/mtd/spi/winbond.c
> @@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
>                 .name                   = "W25Q80",
>         },
>         {
> +               .id                     = 0x6016,
> +               .nr_blocks              = 512,

nr_blocks here should have 64 instead of 512.
please let me know, I will add correction-patch for this.

Thanks,
Jagan.

> +               .name                   = "W25Q32DW",
> +       },
> +       {
>                 .id                     = 0x6017,
>                 .nr_blocks              = 128,
>                 .name                   = "W25Q64DW",
> --
> 1.7.10.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW

[Jagan Teki]

Hi,

Any update on this.

Thanks,
Jagan.

On Thu, May 23, 2013 at 1:15 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> Hi Allen,
>
> On Sun, Mar 17, 2013 at 10:28 AM, Allen Martin <amartin@nvidia.com> wrote:
>> Add support for Winbond W25Q32DW 32Mbit part
>>
>> Signed-off-by: Allen Martin <amartin@nvidia.com>
>> ---
>>  drivers/mtd/spi/winbond.c |    5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
>> index 4418302..3560fcb 100644
>> --- a/drivers/mtd/spi/winbond.c
>> +++ b/drivers/mtd/spi/winbond.c
>> @@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
>>                 .name                   = "W25Q80",
>>         },
>>         {
>> +               .id                     = 0x6016,
>> +               .nr_blocks              = 512,
>
> nr_blocks here should have 64 instead of 512.
> please let me know, I will add correction-patch for this.
>
> Thanks,
> Jagan.
>
>> +               .name                   = "W25Q32DW",
>> +       },
>> +       {
>>                 .id                     = 0x6017,
>>                 .nr_blocks              = 128,
>>                 .name                   = "W25Q64DW",
>> --
>> 1.7.10.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW

[Allen Martin]

On Fri, May 24, 2013 at 01:39:51PM -0700, Jagan Teki wrote:
> Hi,
> 
> Any update on this.
> 
> Thanks,
> Jagan.
> 
> On Thu, May 23, 2013 at 1:15 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> > Hi Allen,
> >
> > On Sun, Mar 17, 2013 at 10:28 AM, Allen Martin <amartin@nvidia.com> wrote:
> >> Add support for Winbond W25Q32DW 32Mbit part
> >>
> >> Signed-off-by: Allen Martin <amartin@nvidia.com>
> >> ---
> >>  drivers/mtd/spi/winbond.c |    5 +++++
> >>  1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
> >> index 4418302..3560fcb 100644
> >> --- a/drivers/mtd/spi/winbond.c
> >> +++ b/drivers/mtd/spi/winbond.c
> >> @@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
> >>                 .name                   = "W25Q80",
> >>         },
> >>         {
> >> +               .id                     = 0x6016,
> >> +               .nr_blocks              = 512,
> >
> > nr_blocks here should have 64 instead of 512.
> > please let me know, I will add correction-patch for this.

You're right, it's a 32Mbit part, so nr_blocks should be 64, thanks
for finding this.


-Allen
-- 
nvpublic

[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW

[Jagan Teki]

On Wed, May 29, 2013 at 5:58 AM, Allen Martin <amartin@nvidia.com> wrote:
> On Fri, May 24, 2013 at 01:39:51PM -0700, Jagan Teki wrote:
>> Hi,
>>
>> Any update on this.
>>
>> Thanks,
>> Jagan.
>>
>> On Thu, May 23, 2013 at 1:15 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>> > Hi Allen,
>> >
>> > On Sun, Mar 17, 2013 at 10:28 AM, Allen Martin <amartin@nvidia.com> wrote:
>> >> Add support for Winbond W25Q32DW 32Mbit part
>> >>
>> >> Signed-off-by: Allen Martin <amartin@nvidia.com>
>> >> ---
>> >>  drivers/mtd/spi/winbond.c |    5 +++++
>> >>  1 file changed, 5 insertions(+)
>> >>
>> >> diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
>> >> index 4418302..3560fcb 100644
>> >> --- a/drivers/mtd/spi/winbond.c
>> >> +++ b/drivers/mtd/spi/winbond.c
>> >> @@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
>> >>                 .name                   = "W25Q80",
>> >>         },
>> >>         {
>> >> +               .id                     = 0x6016,
>> >> +               .nr_blocks              = 512,
>> >
>> > nr_blocks here should have 64 instead of 512.
>> > please let me know, I will add correction-patch for this.
>
> You're right, it's a 32Mbit part, so nr_blocks should be 64, thanks
> for finding this.

Thanks for your response.
I just updated on the patch http://patchwork.ozlabs.org/patch/246654/

Please let me know for any issues.

--
Thanks,
Jagan.