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* [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error
@ 2013-03-19  9:16 Shaohui Xie
  0 siblings, 0 replies; 5+ messages in thread
From: Shaohui Xie @ 2013-03-19  9:16 UTC (permalink / raw)
  To: u-boot

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
Sorry! 
I have to resent since I still cannot find the patch in patch work.

 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |  3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       | 10 ++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |  4 ++++
 3 files changed, 17 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5d72f4c..671c205 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..c43be5e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -592,6 +592,16 @@ skip_l2:
 		}
 	}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	/*
+	 * On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+	 * ECC error, which causes call trace in kernel, so software should
+	 * disable the ECC error reported from eLBC by setting bit 15 in
+	 * the register at DCSRBASE + 0x0002_0520.
+	 */
+#define DCFG_ECC	(CONFIG_SYS_DCSRBAR + 0x20520)
+	setbits_be32((void *)DCFG_ECC, 1 << (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..926316d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
-- 
1.8.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error
@ 2013-03-19  8:51 Shaohui Xie
  0 siblings, 0 replies; 5+ messages in thread
From: Shaohui Xie @ 2013-03-19  8:51 UTC (permalink / raw)
  To: u-boot

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
resent due to patch work did not capture the patch.

 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |  3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       | 10 ++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |  4 ++++
 3 files changed, 17 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5d72f4c..671c205 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..c43be5e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -592,6 +592,16 @@ skip_l2:
 		}
 	}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	/*
+	 * On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+	 * ECC error, which causes call trace in kernel, so software should
+	 * disable the ECC error reported from eLBC by setting bit 15 in
+	 * the register at DCSRBASE + 0x0002_0520.
+	 */
+#define DCFG_ECC	(CONFIG_SYS_DCSRBAR + 0x20520)
+	setbits_be32((void *)DCFG_ECC, 1 << (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..926316d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
-- 
1.8.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error
  2013-01-29 20:02 ` Scott Wood
@ 2013-01-30  2:47   ` Xie Shaohui-B21989
  0 siblings, 0 replies; 5+ messages in thread
From: Xie Shaohui-B21989 @ 2013-01-30  2:47 UTC (permalink / raw)
  To: u-boot

> On 01/28/2013 01:16:53 AM, Shaohui Xie wrote:
> > diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> > b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> > index e5ecf5d..f26d608 100644
> > --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> > +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> > @@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag,
> > int argc, char * const argv[])  #ifdef
> > CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
> >  	puts("Work-around for Erratum NMG_LBC103 enabled\n");  #endif
> > +#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
> > +	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n"); #endif
> 
> Is there still no erratum number for this?
[S.H] Yes, I did not find any update from validation for this erratum. It even does not described in any errata doc.

Best Regards, 
Shaohui Xie

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error
  2013-01-28  7:16 Shaohui Xie
@ 2013-01-29 20:02 ` Scott Wood
  2013-01-30  2:47   ` Xie Shaohui-B21989
  0 siblings, 1 reply; 5+ messages in thread
From: Scott Wood @ 2013-01-29 20:02 UTC (permalink / raw)
  To: u-boot

On 01/28/2013 01:16:53 AM, Shaohui Xie wrote:
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c  
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index e5ecf5d..f26d608 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag,  
> int argc, char * const argv[])
>  #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
>  	puts("Work-around for Erratum NMG_LBC103 enabled\n");
>  #endif
> +#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
> +	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n");
> +#endif

Is there still no erratum number for this?

-Scott

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error
@ 2013-01-28  7:16 Shaohui Xie
  2013-01-29 20:02 ` Scott Wood
  0 siblings, 1 reply; 5+ messages in thread
From: Shaohui Xie @ 2013-01-28  7:16 UTC (permalink / raw)
  To: u-boot

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       |   10 ++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |    4 ++++
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e5ecf5d..f26d608 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d1155e8..5d6f996 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,6 +564,16 @@ skip_l2:
 		}
 	}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	/*
+	 * On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+	 * ECC error, which causes call trace in kernel, so software should
+	 * disable the ECC error reported from eLBC by setting bit 15 in
+	 * the register at DCSRBASE + 0x0002_0520.
+	 */
+#define DCFG_ECC	(CONFIG_SYS_DCSRBAR + 0x20520)
+	setbits_be32((void *)DCFG_ECC, 1 << (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 0b9638b..8f8aea7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
-- 
1.6.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-03-19  9:16 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2013-03-19  9:16 [U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error Shaohui Xie
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2013-03-19  8:51 Shaohui Xie
2013-01-28  7:16 Shaohui Xie
2013-01-29 20:02 ` Scott Wood
2013-01-30  2:47   ` Xie Shaohui-B21989

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