[GIT PULL v2] Renesas ARM and SH based SoC pinmux updates for v3.10

[GIT PULL v2] Renesas ARM and SH based SoC pinmux updates for v3.10

[Simon Horman]

Hi Olof, Hi Arnd,

The following changes since commit 809609a5d8427b0025304dbb69a84a692d11c4f9:

  Merge branch 'soc' into pinmux-base (2013-04-02 11:08:34 +0900)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux2-for-v3.10

for you to fetch changes up to 202ac6a21a79500ef5aab4cd8665be2597e9345c:

  sh-pfc: r8a73a4: Remove unused GPIO bias data (2013-04-03 10:30:43 +0900)

----------------------------------------------------------------
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10

Highlights:

* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC

This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10

----------------------------------------------------------------
Laurent Pinchart (14):
      sh-pfc: Fix compiler warning when BUG()
      sh: sh7269: Fix compilation by adding missing includes
      sh-pfc: r8a7779: Remove function GPIOs
      sh-pfc: r8a7779: Don't use GPIO enum entries
      ARM: shmobile: r8a7779: Remove all GPIOs
      gpio-rcar: Add pinctrl support
      ARM: shmobile: marzen: Add GPIO LEDs
      sh-pfc: Make function GPIOs support optional
      sh-pfc: Make GPIO support optional
      sh-pfc: Skip gpiochip registration when no GPIO resource is found
      sh-pfc: Configure pins as GPIOs at request time when handled externally
      ARM: shmobile: r8a7779: Register GPIO devices
      sh-pfc: r8a7779: Remove GPIO data
      sh-pfc: r8a7779: Split DU input and output pixel clocks

Magnus Damm (14):
      gpio: Renesas R-Car GPIO driver V3
      sh-pfc: Add r8a73a4 pinmux support
      sh-pfc: r8a73a4: Support sparse GPIO numbers
      sh-pfc: r8a73a4: GPIO IRQ support
      sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a73a4: Add SCIF pin groups and functions
      sh-pfc: r8a73a4: Add IRQC pin groups and functions
      sh-pfc: r8a73a4: Remove SCIF function GPIOS
      sh-pfc: r8a73a4: Remove IRQC function GPIOS
      ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
      ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
      sh-pfc: r8a73a4: Remove function GPIOs
      ARM: shmobile: r8a73a4: Remove all GPIO enums
      sh-pfc: r8a73a4: Remove unused GPIO bias data

 arch/arm/mach-shmobile/board-marzen.c         |   32 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  317 ---
 arch/arm/mach-shmobile/setup-r8a7779.c        |   58 +-
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c       |    2 +
 drivers/gpio/Kconfig                          |    6 +
 drivers/gpio/Makefile                         |    1 +
 drivers/gpio/gpio-rcar.c                      |  396 ++++
 drivers/pinctrl/sh-pfc/Kconfig                |    5 +
 drivers/pinctrl/sh-pfc/Makefile               |    1 +
 drivers/pinctrl/sh-pfc/core.c                 |   41 +-
 drivers/pinctrl/sh-pfc/core.h                 |    1 +
 drivers/pinctrl/sh-pfc/gpio.c                 |   45 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          | 2587 +++++++++++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c          |  479 +----
 drivers/pinctrl/sh-pfc/pinctrl.c              |   11 +
 include/linux/platform_data/gpio-rcar.h       |   26 +
 16 files changed, 3274 insertions(+), 734 deletions(-)
 create mode 100644 drivers/gpio/gpio-rcar.c
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
 create mode 100644 include/linux/platform_data/gpio-rcar.h

[GIT PULL v2] Renesas ARM and SH based SoC pinmux updates for v3.10

[Simon Horman]

Hi Olof, Hi Arnd,

The following changes since commit 809609a5d8427b0025304dbb69a84a692d11c4f9:

  Merge branch 'soc' into pinmux-base (2013-04-02 11:08:34 +0900)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux2-for-v3.10

for you to fetch changes up to 202ac6a21a79500ef5aab4cd8665be2597e9345c:

  sh-pfc: r8a73a4: Remove unused GPIO bias data (2013-04-03 10:30:43 +0900)

----------------------------------------------------------------
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10

Highlights:

* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC

This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10

----------------------------------------------------------------
Laurent Pinchart (14):
      sh-pfc: Fix compiler warning when BUG()
      sh: sh7269: Fix compilation by adding missing includes
      sh-pfc: r8a7779: Remove function GPIOs
      sh-pfc: r8a7779: Don't use GPIO enum entries
      ARM: shmobile: r8a7779: Remove all GPIOs
      gpio-rcar: Add pinctrl support
      ARM: shmobile: marzen: Add GPIO LEDs
      sh-pfc: Make function GPIOs support optional
      sh-pfc: Make GPIO support optional
      sh-pfc: Skip gpiochip registration when no GPIO resource is found
      sh-pfc: Configure pins as GPIOs at request time when handled externally
      ARM: shmobile: r8a7779: Register GPIO devices
      sh-pfc: r8a7779: Remove GPIO data
      sh-pfc: r8a7779: Split DU input and output pixel clocks

Magnus Damm (14):
      gpio: Renesas R-Car GPIO driver V3
      sh-pfc: Add r8a73a4 pinmux support
      sh-pfc: r8a73a4: Support sparse GPIO numbers
      sh-pfc: r8a73a4: GPIO IRQ support
      sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a73a4: Add SCIF pin groups and functions
      sh-pfc: r8a73a4: Add IRQC pin groups and functions
      sh-pfc: r8a73a4: Remove SCIF function GPIOS
      sh-pfc: r8a73a4: Remove IRQC function GPIOS
      ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
      ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
      sh-pfc: r8a73a4: Remove function GPIOs
      ARM: shmobile: r8a73a4: Remove all GPIO enums
      sh-pfc: r8a73a4: Remove unused GPIO bias data

 arch/arm/mach-shmobile/board-marzen.c         |   32 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  317 ---
 arch/arm/mach-shmobile/setup-r8a7779.c        |   58 +-
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c       |    2 +
 drivers/gpio/Kconfig                          |    6 +
 drivers/gpio/Makefile                         |    1 +
 drivers/gpio/gpio-rcar.c                      |  396 ++++
 drivers/pinctrl/sh-pfc/Kconfig                |    5 +
 drivers/pinctrl/sh-pfc/Makefile               |    1 +
 drivers/pinctrl/sh-pfc/core.c                 |   41 +-
 drivers/pinctrl/sh-pfc/core.h                 |    1 +
 drivers/pinctrl/sh-pfc/gpio.c                 |   45 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          | 2587 +++++++++++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c          |  479 +----
 drivers/pinctrl/sh-pfc/pinctrl.c              |   11 +
 include/linux/platform_data/gpio-rcar.h       |   26 +
 16 files changed, 3274 insertions(+), 734 deletions(-)
 create mode 100644 drivers/gpio/gpio-rcar.c
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
 create mode 100644 include/linux/platform_data/gpio-rcar.h

[PATCH 01/28] sh-pfc: Fix compiler warning when BUG()

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/core.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index feef897..97e6ea3 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -72,6 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
 	}
 
 	BUG();
+	return NULL;
 }
 
 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
-- 
1.7.10.4

[PATCH 01/28] sh-pfc: Fix compiler warning when BUG()

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/core.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index feef897..97e6ea3 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -72,6 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
 	}
 
 	BUG();
+	return NULL;
 }
 
 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
-- 
1.7.10.4

[PATCH 02/28] sh: sh7269: Fix compilation by adding missing includes

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

struct resource is defined in linux/ioport.h. Include it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index 1825b0b..4c17fb6 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,7 +9,9 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
+#include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <cpu/pfc.h>
 
-- 
1.7.10.4

[PATCH 02/28] sh: sh7269: Fix compilation by adding missing includes

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

struct resource is defined in linux/ioport.h. Include it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index 1825b0b..4c17fb6 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,7 +9,9 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
+#include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <cpu/pfc.h>
 
-- 
1.7.10.4

[PATCH 03/28] sh-pfc: r8a7779: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |  271 ----------------------------------
 1 file changed, 271 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 1d7b0df..4db9944 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2670,274 +2670,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb2),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
-	GPIO_FN(A19),
-
-	/* IPSR0 */
-	GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
-	GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
-	GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
-	GPIO_FN(HCTS1), GPIO_FN(A0),
-	GPIO_FN(FD3), GPIO_FN(A20),
-	GPIO_FN(A21),
-	GPIO_FN(A22),
-	GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
-	GPIO_FN(VI1_R1), GPIO_FN(A24),
-	GPIO_FN(FD4),	GPIO_FN(VI1_R2),
-	GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
-	GPIO_FN(FD5), GPIO_FN(VI1_R3),
-	GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
-	GPIO_FN(PWM0_B),
-	GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
-	GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
-
-	/* IPSR1 */
-	GPIO_FN(FD6), GPIO_FN(FD7),
-	GPIO_FN(FALE),
-	GPIO_FN(ATACS00),
-	GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
-	GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
-	GPIO_FN(SSI_SDATA9),
-	GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
-	GPIO_FN(HTX1),
-	GPIO_FN(SSI_SCK9),
-	GPIO_FN(FD1),	GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
-	GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
-	GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
-	GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
-	GPIO_FN(HTX0), GPIO_FN(SDATA),
-	GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
-	GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
-	GPIO_FN(CC5_STATE34),
-
-	/* IPSR2 */
-	GPIO_FN(HRX0), GPIO_FN(SCKZ),
-	GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
-	GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
-	GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
-	GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
-	GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
-	GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
-	GPIO_FN(STM), GPIO_FN(PWM0_D),
-	GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
-	GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
-	GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
-	GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
-	GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
-	GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
-	GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
-	GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
-	GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
-	GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
-	GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
-	GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
-	GPIO_FN(AUDATA2),
-
-	/* IPSR3 */
-	GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
-	GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
-	GPIO_FN(LCDOUT11),
-	GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
-	GPIO_FN(LCDOUT14),
-	GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
-	GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
-	GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
-	GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
-	GPIO_FN(LCDOUT18),
-	GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
-	GPIO_FN(LCDOUT21),
-	GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
-	GPIO_FN(QSTVA_QVS),
-	GPIO_FN(SCL3_B), GPIO_FN(QCLK),
-	GPIO_FN(QSTVB_QVE),
-	GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
-	GPIO_FN(QSTH_QHS),
-	GPIO_FN(QSTB_QHE),
-	GPIO_FN(QCPV_QDE),
-	GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
-
-	/* IPSR4 */
-	GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
-	GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
-	GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
-	GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
-	GPIO_FN(AUDCK),
-	GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
-	GPIO_FN(PWM0),
-	GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
-	GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
-	GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
-	GPIO_FN(VI2_G5),
-	GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
-	GPIO_FN(AUDATA6),
-	GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
-	GPIO_FN(AUDATA7),
-	GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
-	GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
-	GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
-	GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
-
-	/* IPSR5 */
-	GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
-	GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
-	GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
-	GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
-	GPIO_FN(VI2_CLKENB),
-	GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
-	GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
-	GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
-	GPIO_FN(VI3_VSYNC),
-	GPIO_FN(VI2_CLK),
-	GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
-	GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
-	GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
-	GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
-	GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
-	GPIO_FN(VI2_DATA7_VI2_B7),
-	GPIO_FN(VI1_FIELD),
-	GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
-	GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
-	GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
-	GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
-
-	/* IPSR6 */
-	GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
-	GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
-	GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
-	GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
-	GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
-	GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
-	GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
-	GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
-	GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
-	GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
-	GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
-	GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
-	GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
-	GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
-	GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
-	GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
-	GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
-
-	/* IPSR7 */
-	GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
-	GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
-	GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
-	GPIO_FN(SSI_SCK9_B),
-	GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
-	GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
-	GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
-	GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
-	GPIO_FN(ATACS01), GPIO_FN(ATACS11),
-	GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
-	GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
-	GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
-	GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
-	GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
-	GPIO_FN(DACK2),
-
-	/* IPSR8 */
-	GPIO_FN(AD_CLK),
-	GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
-	GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
-	GPIO_FN(AD_DI),
-	GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
-	GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
-	GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
-	GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
-	GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
-	GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
-	GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
-	GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
-	GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
-	GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
-	GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
-	GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
-	GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
-	GPIO_FN(HSCK1_B),
-	GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
-	GPIO_FN(PWMFSW0_C),
-
-	/* IPSR9 */
-	GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
-	GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
-	GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
-	GPIO_FN(VI0_DATA4_VI0_B4),
-	GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
-	GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
-	GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
-	GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
-	GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
-	GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
-	GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
-	GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
-	GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
-	GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
-	GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
-	GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
-	GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
-	GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
-
-	/* IPSR10 */
-	GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
-	GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
-	GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
-	GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
-	GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
-	GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
-	GPIO_FN(ARM_TRACEDATA_13),
-	GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
-	GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
-	GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
-	GPIO_FN(ARM_TRACEDATA_15),
-	GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
-	GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
-	GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
-	GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
-	GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
-	GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
-	GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
-	GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
-	GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
-	GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
-
-	/* IPSR11 */
-	GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
-	GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
-	GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
-	GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
-	GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
-	GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
-	GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
-	GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
-	GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
-	GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
-	GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
-	GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
-	GPIO_FN(VI1_DATA7_VI1_B7),
-	GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
-	GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
-	GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
-	GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
-	GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
-	GPIO_FN(HRTS0_B),
-
-	/* IPSR12 */
-	GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
-	GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
-	GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
-	GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
-	GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
-	GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
-	GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
-	GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
-	GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
-	GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
 		GP_0_31_FN, FN_IP3_31_29,
@@ -3831,9 +3563,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs = pinmux_config_regs,
 	.data_regs = pinmux_data_regs,
 
-- 
1.7.10.4

[PATCH 03/28] sh-pfc: r8a7779: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |  271 ----------------------------------
 1 file changed, 271 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 1d7b0df..4db9944 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2670,274 +2670,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb2),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
-	GPIO_FN(A19),
-
-	/* IPSR0 */
-	GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
-	GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
-	GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
-	GPIO_FN(HCTS1), GPIO_FN(A0),
-	GPIO_FN(FD3), GPIO_FN(A20),
-	GPIO_FN(A21),
-	GPIO_FN(A22),
-	GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
-	GPIO_FN(VI1_R1), GPIO_FN(A24),
-	GPIO_FN(FD4),	GPIO_FN(VI1_R2),
-	GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
-	GPIO_FN(FD5), GPIO_FN(VI1_R3),
-	GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
-	GPIO_FN(PWM0_B),
-	GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
-	GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
-
-	/* IPSR1 */
-	GPIO_FN(FD6), GPIO_FN(FD7),
-	GPIO_FN(FALE),
-	GPIO_FN(ATACS00),
-	GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
-	GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
-	GPIO_FN(SSI_SDATA9),
-	GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
-	GPIO_FN(HTX1),
-	GPIO_FN(SSI_SCK9),
-	GPIO_FN(FD1),	GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
-	GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
-	GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
-	GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
-	GPIO_FN(HTX0), GPIO_FN(SDATA),
-	GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
-	GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
-	GPIO_FN(CC5_STATE34),
-
-	/* IPSR2 */
-	GPIO_FN(HRX0), GPIO_FN(SCKZ),
-	GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
-	GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
-	GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
-	GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
-	GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
-	GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
-	GPIO_FN(STM), GPIO_FN(PWM0_D),
-	GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
-	GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
-	GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
-	GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
-	GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
-	GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
-	GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
-	GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
-	GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
-	GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
-	GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
-	GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
-	GPIO_FN(AUDATA2),
-
-	/* IPSR3 */
-	GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
-	GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
-	GPIO_FN(LCDOUT11),
-	GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
-	GPIO_FN(LCDOUT14),
-	GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
-	GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
-	GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
-	GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
-	GPIO_FN(LCDOUT18),
-	GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
-	GPIO_FN(LCDOUT21),
-	GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
-	GPIO_FN(QSTVA_QVS),
-	GPIO_FN(SCL3_B), GPIO_FN(QCLK),
-	GPIO_FN(QSTVB_QVE),
-	GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
-	GPIO_FN(QSTH_QHS),
-	GPIO_FN(QSTB_QHE),
-	GPIO_FN(QCPV_QDE),
-	GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
-
-	/* IPSR4 */
-	GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
-	GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
-	GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
-	GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
-	GPIO_FN(AUDCK),
-	GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
-	GPIO_FN(PWM0),
-	GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
-	GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
-	GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
-	GPIO_FN(VI2_G5),
-	GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
-	GPIO_FN(AUDATA6),
-	GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
-	GPIO_FN(AUDATA7),
-	GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
-	GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
-	GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
-	GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
-
-	/* IPSR5 */
-	GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
-	GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
-	GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
-	GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
-	GPIO_FN(VI2_CLKENB),
-	GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
-	GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
-	GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
-	GPIO_FN(VI3_VSYNC),
-	GPIO_FN(VI2_CLK),
-	GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
-	GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
-	GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
-	GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
-	GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
-	GPIO_FN(VI2_DATA7_VI2_B7),
-	GPIO_FN(VI1_FIELD),
-	GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
-	GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
-	GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
-	GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
-
-	/* IPSR6 */
-	GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
-	GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
-	GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
-	GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
-	GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
-	GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
-	GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
-	GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
-	GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
-	GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
-	GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
-	GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
-	GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
-	GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
-	GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
-	GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
-	GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
-
-	/* IPSR7 */
-	GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
-	GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
-	GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
-	GPIO_FN(SSI_SCK9_B),
-	GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
-	GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
-	GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
-	GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
-	GPIO_FN(ATACS01), GPIO_FN(ATACS11),
-	GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
-	GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
-	GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
-	GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
-	GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
-	GPIO_FN(DACK2),
-
-	/* IPSR8 */
-	GPIO_FN(AD_CLK),
-	GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
-	GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
-	GPIO_FN(AD_DI),
-	GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
-	GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
-	GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
-	GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
-	GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
-	GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
-	GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
-	GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
-	GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
-	GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
-	GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
-	GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
-	GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
-	GPIO_FN(HSCK1_B),
-	GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
-	GPIO_FN(PWMFSW0_C),
-
-	/* IPSR9 */
-	GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
-	GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
-	GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
-	GPIO_FN(VI0_DATA4_VI0_B4),
-	GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
-	GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
-	GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
-	GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
-	GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
-	GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
-	GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
-	GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
-	GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
-	GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
-	GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
-	GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
-	GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
-	GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
-
-	/* IPSR10 */
-	GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
-	GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
-	GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
-	GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
-	GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
-	GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
-	GPIO_FN(ARM_TRACEDATA_13),
-	GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
-	GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
-	GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
-	GPIO_FN(ARM_TRACEDATA_15),
-	GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
-	GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
-	GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
-	GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
-	GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
-	GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
-	GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
-	GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
-	GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
-	GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
-
-	/* IPSR11 */
-	GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
-	GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
-	GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
-	GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
-	GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
-	GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
-	GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
-	GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
-	GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
-	GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
-	GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
-	GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
-	GPIO_FN(VI1_DATA7_VI1_B7),
-	GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
-	GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
-	GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
-	GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
-	GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
-	GPIO_FN(HRTS0_B),
-
-	/* IPSR12 */
-	GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
-	GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
-	GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
-	GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
-	GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
-	GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
-	GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
-	GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
-	GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
-	GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
 		GP_0_31_FN, FN_IP3_31_29,
@@ -3831,9 +3563,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs = pinmux_config_regs,
 	.data_regs = pinmux_data_regs,
 
-- 
1.7.10.4

[PATCH 04/28] sh-pfc: r8a7779: Don't use GPIO enum entries

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |  104 ++++++++++++++++++++++++----------
 1 file changed, 74 insertions(+), 30 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 4db9944..41d8bda 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,39 +19,83 @@
  */
 
 #include <linux/kernel.h>
-#include <mach/r8a7779.h>
 
 #include "sh_pfc.h"
 
-#define CPU_32_PORT6(fn, pfx, sfx)				\
-	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
-	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
-	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
-	PORT_1(fn, pfx##8, sfx)
-
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	PORT_32(fn, pfx##_0_, sfx),				\
-	PORT_32(fn, pfx##_1_, sfx),				\
-	PORT_32(fn, pfx##_2_, sfx),				\
-	PORT_32(fn, pfx##_3_, sfx),				\
-	PORT_32(fn, pfx##_4_, sfx),				\
-	PORT_32(fn, pfx##_5_, sfx),				\
-	CPU_32_PORT6(fn, pfx##_6_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
-				       GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
-
-#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
+	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
+	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
+	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_9(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),	\
+	PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),	\
+	PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),	\
+	PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),	\
+	PORT_GP_1(bank, 8, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)					\
+	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
+	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
+	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
+	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
+	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
+	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
+	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
+	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
+	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
+	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
+	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
+	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
+	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
+	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
+	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
+	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_GP_32(0, fn, sfx),						\
+	PORT_GP_32(1, fn, sfx),						\
+	PORT_GP_32(2, fn, sfx),						\
+	PORT_GP_32(3, fn, sfx),						\
+	PORT_GP_32(4, fn, sfx),						\
+	PORT_GP_32(5, fn, sfx),						\
+	PORT_GP_32_9(6, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)	name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)					\
+	[(bank * 32) + pin] = {						\
+		.name = __stringify(_name),				\
+		.enum_id = _name##_DATA,				\
+	}
+
+#define _GP_DATA(bank, pin, name, sfx)					\
+	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
+
+#define _GP_INOUTSEL(bank, pin, name, sfx)	name##_IN, name##_OUT
+#define _GP_INDT(bank, pin, name, sfx)		name##_DATA
+
+#define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
+
+#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
+#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
 
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-- 
1.7.10.4

[PATCH 04/28] sh-pfc: r8a7779: Don't use GPIO enum entries

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |  104 ++++++++++++++++++++++++----------
 1 file changed, 74 insertions(+), 30 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 4db9944..41d8bda 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,39 +19,83 @@
  */
 
 #include <linux/kernel.h>
-#include <mach/r8a7779.h>
 
 #include "sh_pfc.h"
 
-#define CPU_32_PORT6(fn, pfx, sfx)				\
-	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
-	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
-	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
-	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
-	PORT_1(fn, pfx##8, sfx)
-
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	PORT_32(fn, pfx##_0_, sfx),				\
-	PORT_32(fn, pfx##_1_, sfx),				\
-	PORT_32(fn, pfx##_2_, sfx),				\
-	PORT_32(fn, pfx##_3_, sfx),				\
-	PORT_32(fn, pfx##_4_, sfx),				\
-	PORT_32(fn, pfx##_5_, sfx),				\
-	CPU_32_PORT6(fn, pfx##_6_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
-				       GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
-
-#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
+	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
+	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
+	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_9(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),	\
+	PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),	\
+	PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),	\
+	PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),	\
+	PORT_GP_1(bank, 8, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)					\
+	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
+	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
+	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
+	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
+	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
+	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
+	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
+	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
+	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
+	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
+	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
+	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
+	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
+	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
+	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
+	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_GP_32(0, fn, sfx),						\
+	PORT_GP_32(1, fn, sfx),						\
+	PORT_GP_32(2, fn, sfx),						\
+	PORT_GP_32(3, fn, sfx),						\
+	PORT_GP_32(4, fn, sfx),						\
+	PORT_GP_32(5, fn, sfx),						\
+	PORT_GP_32_9(6, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)	name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)					\
+	[(bank * 32) + pin] = {						\
+		.name = __stringify(_name),				\
+		.enum_id = _name##_DATA,				\
+	}
+
+#define _GP_DATA(bank, pin, name, sfx)					\
+	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
+
+#define _GP_INOUTSEL(bank, pin, name, sfx)	name##_IN, name##_OUT
+#define _GP_INDT(bank, pin, name, sfx)		name##_DATA
+
+#define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
+
+#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
+#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
 
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-- 
1.7.10.4

[PATCH 05/28] ARM: shmobile: r8a7779: Remove all GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  317 -------------------------
 1 file changed, 317 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 68c3b2d..945299e 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,323 +4,6 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
-	GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
-
-	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
-	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
-	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
-	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
-	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
-	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
-	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
-	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
-	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
-	GPIO_GP_6_8,
-
-	GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
-	GPIO_FN_A19,
-
-	/* IPSR0 */
-	GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
-	GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
-	GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
-	GPIO_FN_HCTS1, GPIO_FN_A0,
-	GPIO_FN_FD3, GPIO_FN_A20,
-	GPIO_FN_A21,
-	GPIO_FN_A22, GPIO_FN_VI1_R0,
-	GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
-	GPIO_FN_A24, GPIO_FN_FD4,
-	GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
-	GPIO_FN_FD5,
-	GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
-	GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
-	GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
-	GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
-
-	/* IPSR1 */
-	GPIO_FN_FD6, GPIO_FN_FD7,
-	GPIO_FN_FALE,
-	GPIO_FN_ATACS00,
-	GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
-	GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
-	GPIO_FN_SSI_SDATA9,
-	GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
-	GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
-	GPIO_FN_FD1,
-	GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
-	GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
-	GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
-	GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
-	GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
-	GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
-	GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
-
-	/* IPSR2 */
-	GPIO_FN_HRX0, GPIO_FN_SCKZ,
-	GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
-	GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
-	GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
-	GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
-	GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
-	GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
-	GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
-	GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
-	GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
-	GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
-	GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
-	GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
-	GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
-	GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
-	GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
-	GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
-	GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
-	GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
-	GPIO_FN_AUDATA2,
-
-	/* IPSR3 */
-	GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
-	GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
-	GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
-	GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
-	GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
-	GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
-	GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
-	GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
-	GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
-	GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
-	GPIO_FN_LCDOUT23,
-	GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
-	GPIO_FN_QCLK,
-	GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
-	GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
-	GPIO_FN_QSTH_QHS,
-	GPIO_FN_QSTB_QHE,
-	GPIO_FN_QCPV_QDE,
-	GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
-
-	/* IPSR4 */
-	GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
-	GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
-	GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
-	GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
-	GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
-	GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
-	GPIO_FN_AUDSYNC,
-	GPIO_FN_VI2_G0,
-	GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
-	GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
-	GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
-	GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
-	GPIO_FN_VI2_DATA3_VI2_B3,
-	GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
-	GPIO_FN_VI2_G6,
-	GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
-	GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
-	GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
-	GPIO_FN_SCL2_B,
-
-	/* IPSR5 */
-	GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
-	GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
-	GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
-	GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
-	GPIO_FN_VI2_CLKENB,
-	GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
-	GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
-	GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
-	GPIO_FN_VI3_VSYNC,
-	GPIO_FN_VI2_CLK,
-	GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
-	GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
-	GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
-	GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
-	GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
-	GPIO_FN_VI2_DATA7_VI2_B7,
-	GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
-	GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
-	GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
-	GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
-	GPIO_FN_MOUT0,
-
-	/* IPSR6 */
-	GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
-	GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
-	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
-	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
-	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
-	GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
-	GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
-	GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
-	GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
-	GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
-	GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
-	GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
-	GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
-	GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
-	GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
-	GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
-
-	/* IPSR7 */
-	GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
-	GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
-	GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
-	GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
-	GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
-	GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
-	GPIO_FN_TCLK1_C,
-	GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
-	GPIO_FN_ATACS01,
-	GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
-	GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
-	GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
-	GPIO_FN_ATARD1,	GPIO_FN_CC5_TCK,
-	GPIO_FN_ATAWR1,	GPIO_FN_CC5_TDI,
-	GPIO_FN_DREQ2,	GPIO_FN_DACK2,
-
-	/* IPSR8 */
-	GPIO_FN_AD_CLK,
-	GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
-	GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
-	GPIO_FN_AD_DI,
-	GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
-	GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
-	GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
-	GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
-	GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
-	GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
-	GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
-	GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
-	GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
-	GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
-	GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
-	GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
-	GPIO_FN_HSCK1_B,
-	GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
-	GPIO_FN_PWMFSW0_C,
-
-	/* IPSR9 */
-	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
-	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
-	GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
-	GPIO_FN_VI0_DATA4_VI0_B4,
-	GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
-	GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
-	GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
-	GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
-	GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
-	GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
-	GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
-	GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
-	GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
-	GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
-	GPIO_FN_VI0_G5,	GPIO_FN_ETH_RX_ER,
-	GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
-	GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
-	GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
-
-	/* IPSR10 */
-	GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
-	GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
-	GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
-	GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
-	GPIO_FN_ARM_TRACEDATA_12,
-	GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
-	GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
-	GPIO_FN_ARM_TRACEDATA_14,
-	GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
-	GPIO_FN_ARM_TRACEDATA_15,
-	GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
-	GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
-	GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
-	GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
-	GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
-	GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
-	GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
-	GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
-	GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
-
-	/* IPSR11 */
-	GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
-	GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
-	GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
-	GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
-	GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
-	GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
-	GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
-	GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
-	GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
-	GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
-	GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
-	GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
-	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
-	GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
-	GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
-	GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
-	GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
-	GPIO_FN_HRTS0_B,
-
-	/* IPSR12 */
-	GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
-	GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
-	GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
-	GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
-	GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
-	GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
-	GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
-	GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
-	GPIO_FN_GPS_MAG, GPIO_FN_FCE,
-};
-
 struct platform_device;
 
 struct r8a7779_pm_ch {
-- 
1.7.10.4

[PATCH 05/28] ARM: shmobile: r8a7779: Remove all GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  317 -------------------------
 1 file changed, 317 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 68c3b2d..945299e 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,323 +4,6 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
-	GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
-
-	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
-	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
-	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
-	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
-	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
-	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
-	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
-	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
-	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
-	GPIO_GP_6_8,
-
-	GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
-	GPIO_FN_A19,
-
-	/* IPSR0 */
-	GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
-	GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
-	GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
-	GPIO_FN_HCTS1, GPIO_FN_A0,
-	GPIO_FN_FD3, GPIO_FN_A20,
-	GPIO_FN_A21,
-	GPIO_FN_A22, GPIO_FN_VI1_R0,
-	GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
-	GPIO_FN_A24, GPIO_FN_FD4,
-	GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
-	GPIO_FN_FD5,
-	GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
-	GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
-	GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
-	GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
-
-	/* IPSR1 */
-	GPIO_FN_FD6, GPIO_FN_FD7,
-	GPIO_FN_FALE,
-	GPIO_FN_ATACS00,
-	GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
-	GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
-	GPIO_FN_SSI_SDATA9,
-	GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
-	GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
-	GPIO_FN_FD1,
-	GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
-	GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
-	GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
-	GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
-	GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
-	GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
-	GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
-
-	/* IPSR2 */
-	GPIO_FN_HRX0, GPIO_FN_SCKZ,
-	GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
-	GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
-	GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
-	GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
-	GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
-	GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
-	GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
-	GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
-	GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
-	GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
-	GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
-	GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
-	GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
-	GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
-	GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
-	GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
-	GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
-	GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
-	GPIO_FN_AUDATA2,
-
-	/* IPSR3 */
-	GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
-	GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
-	GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
-	GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
-	GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
-	GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
-	GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
-	GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
-	GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
-	GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
-	GPIO_FN_LCDOUT23,
-	GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
-	GPIO_FN_QCLK,
-	GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
-	GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
-	GPIO_FN_QSTH_QHS,
-	GPIO_FN_QSTB_QHE,
-	GPIO_FN_QCPV_QDE,
-	GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
-
-	/* IPSR4 */
-	GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
-	GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
-	GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
-	GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
-	GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
-	GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
-	GPIO_FN_AUDSYNC,
-	GPIO_FN_VI2_G0,
-	GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
-	GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
-	GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
-	GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
-	GPIO_FN_VI2_DATA3_VI2_B3,
-	GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
-	GPIO_FN_VI2_G6,
-	GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
-	GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
-	GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
-	GPIO_FN_SCL2_B,
-
-	/* IPSR5 */
-	GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
-	GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
-	GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
-	GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
-	GPIO_FN_VI2_CLKENB,
-	GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
-	GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
-	GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
-	GPIO_FN_VI3_VSYNC,
-	GPIO_FN_VI2_CLK,
-	GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
-	GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
-	GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
-	GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
-	GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
-	GPIO_FN_VI2_DATA7_VI2_B7,
-	GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
-	GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
-	GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
-	GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
-	GPIO_FN_MOUT0,
-
-	/* IPSR6 */
-	GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
-	GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
-	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
-	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
-	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
-	GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
-	GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
-	GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
-	GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
-	GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
-	GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
-	GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
-	GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
-	GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
-	GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
-	GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
-
-	/* IPSR7 */
-	GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
-	GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
-	GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
-	GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
-	GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
-	GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
-	GPIO_FN_TCLK1_C,
-	GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
-	GPIO_FN_ATACS01,
-	GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
-	GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
-	GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
-	GPIO_FN_ATARD1,	GPIO_FN_CC5_TCK,
-	GPIO_FN_ATAWR1,	GPIO_FN_CC5_TDI,
-	GPIO_FN_DREQ2,	GPIO_FN_DACK2,
-
-	/* IPSR8 */
-	GPIO_FN_AD_CLK,
-	GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
-	GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
-	GPIO_FN_AD_DI,
-	GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
-	GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
-	GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
-	GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
-	GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
-	GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
-	GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
-	GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
-	GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
-	GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
-	GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
-	GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
-	GPIO_FN_HSCK1_B,
-	GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
-	GPIO_FN_PWMFSW0_C,
-
-	/* IPSR9 */
-	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
-	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
-	GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
-	GPIO_FN_VI0_DATA4_VI0_B4,
-	GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
-	GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
-	GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
-	GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
-	GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
-	GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
-	GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
-	GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
-	GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
-	GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
-	GPIO_FN_VI0_G5,	GPIO_FN_ETH_RX_ER,
-	GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
-	GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
-	GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
-
-	/* IPSR10 */
-	GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
-	GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
-	GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
-	GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
-	GPIO_FN_ARM_TRACEDATA_12,
-	GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
-	GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
-	GPIO_FN_ARM_TRACEDATA_14,
-	GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
-	GPIO_FN_ARM_TRACEDATA_15,
-	GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
-	GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
-	GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
-	GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
-	GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
-	GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
-	GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
-	GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
-	GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
-
-	/* IPSR11 */
-	GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
-	GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
-	GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
-	GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
-	GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
-	GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
-	GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
-	GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
-	GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
-	GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
-	GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
-	GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
-	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
-	GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
-	GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
-	GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
-	GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
-	GPIO_FN_HRTS0_B,
-
-	/* IPSR12 */
-	GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
-	GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
-	GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
-	GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
-	GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
-	GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
-	GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
-	GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
-	GPIO_FN_GPS_MAG, GPIO_FN_FCE,
-};
-
 struct platform_device;
 
 struct r8a7779_pm_ch {
-- 
1.7.10.4

[PATCH 06/28] gpio: Renesas R-Car GPIO driver V3

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.

In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.

At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.

Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/Kconfig                    |    6 +
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/gpio-rcar.c                |  373 +++++++++++++++++++++++++++++++
 include/linux/platform_data/gpio-rcar.h |   25 +++
 4 files changed, 405 insertions(+)
 create mode 100644 drivers/gpio/gpio-rcar.c
 create mode 100644 include/linux/platform_data/gpio-rcar.h

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf..d766e3c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -204,6 +204,12 @@ config GPIO_PXA
 	help
 	  Say yes here to support the PXA GPIO device
 
+config GPIO_RCAR
+	tristate "Renesas R-Car GPIO"
+	depends on ARM
+	help
+	  Say yes here to support GPIO on Renesas R-Car SoCs.
+
 config GPIO_SPEAR_SPICS
 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
 	depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc..b41c74d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o
 obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RC5T583)	+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
+obj-$(CONFIG_GPIO_RCAR)		+= gpio-rcar.o
 obj-$(CONFIG_PLAT_SAMSUNG)	+= gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)	+= gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)		+= gpio-sch.o
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
new file mode 100644
index 0000000..581ba56
--- /dev/null
+++ b/drivers/gpio/gpio-rcar.c
@@ -0,0 +1,373 @@
+/*
+ * Renesas R-Car GPIO Support
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+struct gpio_rcar_priv {
+	void __iomem *base;
+	spinlock_t lock;
+	struct gpio_rcar_config config;
+	struct platform_device *pdev;
+	struct gpio_chip gpio_chip;
+	struct irq_chip irq_chip;
+	struct irq_domain *irq_domain;
+};
+
+#define IOINTSEL 0x00
+#define INOUTSEL 0x04
+#define OUTDT 0x08
+#define INDT 0x0c
+#define INTDT 0x10
+#define INTCLR 0x14
+#define INTMSK 0x18
+#define MSKCLR 0x1c
+#define POSNEG 0x20
+#define EDGLEVEL 0x24
+#define FILONOFF 0x28
+
+static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
+{
+	return ioread32(p->base + offs);
+}
+
+static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
+				   u32 value)
+{
+	iowrite32(value, p->base + offs);
+}
+
+static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
+				 int bit, bool value)
+{
+	u32 tmp = gpio_rcar_read(p, offs);
+
+	if (value)
+		tmp |= BIT(bit);
+	else
+		tmp &= ~BIT(bit);
+
+	gpio_rcar_write(p, offs, tmp);
+}
+
+static void gpio_rcar_irq_disable(struct irq_data *d)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_irq_enable(struct irq_data *d)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
+						  unsigned int hwirq,
+						  bool active_high_rising_edge,
+						  bool level_trigger)
+{
+	unsigned long flags;
+
+	/* follow steps in the GPIO documentation for
+	 * "Setting Edge-Sensitive Interrupt Input Mode" and
+	 * "Setting Level-Sensitive Interrupt Input Mode"
+	 */
+
+	spin_lock_irqsave(&p->lock, flags);
+
+	/* Configure postive or negative logic in POSNEG */
+	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
+
+	/* Configure edge or level trigger in EDGLEVEL */
+	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
+
+	/* Select "Interrupt Input Mode" in IOINTSEL */
+	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
+
+	/* Write INTCLR in case of edge trigger */
+	if (!level_trigger)
+		gpio_rcar_write(p, INTCLR, BIT(hwirq));
+
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+	unsigned int hwirq = irqd_to_hwirq(d);
+
+	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
+{
+	struct gpio_rcar_priv *p = dev_id;
+	u32 pending;
+	unsigned int offset, irqs_handled = 0;
+
+	while ((pending = gpio_rcar_read(p, INTDT))) {
+		offset = __ffs(pending);
+		gpio_rcar_write(p, INTCLR, BIT(offset));
+		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+		irqs_handled++;
+	}
+
+	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
+}
+
+static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
+						       unsigned int gpio,
+						       bool output)
+{
+	struct gpio_rcar_priv *p = gpio_to_priv(chip);
+	unsigned long flags;
+
+	/* follow steps in the GPIO documentation for
+	 * "Setting General Output Mode" and
+	 * "Setting General Input Mode"
+	 */
+
+	spin_lock_irqsave(&p->lock, flags);
+
+	/* Configure postive logic in POSNEG */
+	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
+
+	/* Select "General Input/Output Mode" in IOINTSEL */
+	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
+
+	/* Select Input Mode or Output Mode in INOUTSEL */
+	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
+
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	gpio_rcar_config_general_input_output_mode(chip, offset, false);
+	return 0;
+}
+
+static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
+{
+	return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
+}
+
+static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	struct gpio_rcar_priv *p = gpio_to_priv(chip);
+	unsigned long flags;
+
+	spin_lock_irqsave(&p->lock, flags);
+	gpio_rcar_modify_bit(p, OUTDT, offset, value);
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
+				      int value)
+{
+	/* write GPIO value to output before selecting output mode of pin */
+	gpio_rcar_set(chip, offset, value);
+	gpio_rcar_config_general_input_output_mode(chip, offset, true);
+	return 0;
+}
+
+static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
+}
+
+static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
+				 irq_hw_number_t hw)
+{
+	struct gpio_rcar_priv *p = h->host_data;
+
+	dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
+
+	irq_set_chip_data(virq, h->host_data);
+	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID); /* kill me now */
+	return 0;
+}
+
+static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
+	.map	= gpio_rcar_irq_domain_map,
+};
+
+static int gpio_rcar_probe(struct platform_device *pdev)
+{
+	struct gpio_rcar_config *pdata = pdev->dev.platform_data;
+	struct gpio_rcar_priv *p;
+	struct resource *io, *irq;
+	struct gpio_chip *gpio_chip;
+	struct irq_chip *irq_chip;
+	const char *name = dev_name(&pdev->dev);
+	int ret;
+
+	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+	if (!p) {
+		dev_err(&pdev->dev, "failed to allocate driver data\n");
+		ret = -ENOMEM;
+		goto err0;
+	}
+
+	/* deal with driver instance configuration */
+	if (pdata)
+		p->config = *pdata;
+
+	p->pdev = pdev;
+	platform_set_drvdata(pdev, p);
+	spin_lock_init(&p->lock);
+
+	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+	if (!io || !irq) {
+		dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
+		ret = -EINVAL;
+		goto err0;
+	}
+
+	p->base = devm_ioremap_nocache(&pdev->dev, io->start,
+				       resource_size(io));
+	if (!p->base) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		ret = -ENXIO;
+		goto err0;
+	}
+
+	gpio_chip = &p->gpio_chip;
+	gpio_chip->direction_input = gpio_rcar_direction_input;
+	gpio_chip->get = gpio_rcar_get;
+	gpio_chip->direction_output = gpio_rcar_direction_output;
+	gpio_chip->set = gpio_rcar_set;
+	gpio_chip->to_irq = gpio_rcar_to_irq;
+	gpio_chip->label = name;
+	gpio_chip->owner = THIS_MODULE;
+	gpio_chip->base = p->config.gpio_base;
+	gpio_chip->ngpio = p->config.number_of_pins;
+
+	irq_chip = &p->irq_chip;
+	irq_chip->name = name;
+	irq_chip->irq_mask = gpio_rcar_irq_disable;
+	irq_chip->irq_unmask = gpio_rcar_irq_enable;
+	irq_chip->irq_enable = gpio_rcar_irq_enable;
+	irq_chip->irq_disable = gpio_rcar_irq_disable;
+	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
+	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
+
+	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
+					      p->config.number_of_pins,
+					      p->config.irq_base,
+					      &gpio_rcar_irq_domain_ops, p);
+	if (!p->irq_domain) {
+		ret = -ENXIO;
+		dev_err(&pdev->dev, "cannot initialize irq domain\n");
+		goto err1;
+	}
+
+	if (devm_request_irq(&pdev->dev, irq->start,
+			     gpio_rcar_irq_handler, 0, name, p)) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		ret = -ENOENT;
+		goto err1;
+	}
+
+	ret = gpiochip_add(gpio_chip);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add GPIO controller\n");
+		goto err1;
+	}
+
+	dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
+
+	/* warn in case of mismatch if irq base is specified */
+	if (p->config.irq_base) {
+		ret = irq_find_mapping(p->irq_domain, 0);
+		if (p->config.irq_base != ret)
+			dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
+				 p->config.irq_base, ret);
+	}
+
+	return 0;
+
+err1:
+	irq_domain_remove(p->irq_domain);
+err0:
+	return ret;
+}
+
+static int gpio_rcar_remove(struct platform_device *pdev)
+{
+	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = gpiochip_remove(&p->gpio_chip);
+	if (ret)
+		return ret;
+
+	irq_domain_remove(p->irq_domain);
+	return 0;
+}
+
+static struct platform_driver gpio_rcar_device_driver = {
+	.probe		= gpio_rcar_probe,
+	.remove		= gpio_rcar_remove,
+	.driver		= {
+		.name	= "gpio_rcar",
+	}
+};
+
+module_platform_driver(gpio_rcar_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
new file mode 100644
index 0000000..bebfcd8
--- /dev/null
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -0,0 +1,25 @@
+/*
+ * Renesas R-Car GPIO Support
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __GPIO_RCAR_H__
+#define __GPIO_RCAR_H__
+
+struct gpio_rcar_config {
+	unsigned int gpio_base;
+	unsigned int irq_base;
+	unsigned int number_of_pins;
+};
+
+#endif /* __GPIO_RCAR_H__ */
-- 
1.7.10.4

[PATCH 06/28] gpio: Renesas R-Car GPIO driver V3

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.

In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.

At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.

Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/Kconfig                    |    6 +
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/gpio-rcar.c                |  373 +++++++++++++++++++++++++++++++
 include/linux/platform_data/gpio-rcar.h |   25 +++
 4 files changed, 405 insertions(+)
 create mode 100644 drivers/gpio/gpio-rcar.c
 create mode 100644 include/linux/platform_data/gpio-rcar.h

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf..d766e3c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -204,6 +204,12 @@ config GPIO_PXA
 	help
 	  Say yes here to support the PXA GPIO device
 
+config GPIO_RCAR
+	tristate "Renesas R-Car GPIO"
+	depends on ARM
+	help
+	  Say yes here to support GPIO on Renesas R-Car SoCs.
+
 config GPIO_SPEAR_SPICS
 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
 	depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc..b41c74d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o
 obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RC5T583)	+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
+obj-$(CONFIG_GPIO_RCAR)		+= gpio-rcar.o
 obj-$(CONFIG_PLAT_SAMSUNG)	+= gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)	+= gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)		+= gpio-sch.o
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
new file mode 100644
index 0000000..581ba56
--- /dev/null
+++ b/drivers/gpio/gpio-rcar.c
@@ -0,0 +1,373 @@
+/*
+ * Renesas R-Car GPIO Support
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+struct gpio_rcar_priv {
+	void __iomem *base;
+	spinlock_t lock;
+	struct gpio_rcar_config config;
+	struct platform_device *pdev;
+	struct gpio_chip gpio_chip;
+	struct irq_chip irq_chip;
+	struct irq_domain *irq_domain;
+};
+
+#define IOINTSEL 0x00
+#define INOUTSEL 0x04
+#define OUTDT 0x08
+#define INDT 0x0c
+#define INTDT 0x10
+#define INTCLR 0x14
+#define INTMSK 0x18
+#define MSKCLR 0x1c
+#define POSNEG 0x20
+#define EDGLEVEL 0x24
+#define FILONOFF 0x28
+
+static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
+{
+	return ioread32(p->base + offs);
+}
+
+static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
+				   u32 value)
+{
+	iowrite32(value, p->base + offs);
+}
+
+static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
+				 int bit, bool value)
+{
+	u32 tmp = gpio_rcar_read(p, offs);
+
+	if (value)
+		tmp |= BIT(bit);
+	else
+		tmp &= ~BIT(bit);
+
+	gpio_rcar_write(p, offs, tmp);
+}
+
+static void gpio_rcar_irq_disable(struct irq_data *d)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_irq_enable(struct irq_data *d)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
+						  unsigned int hwirq,
+						  bool active_high_rising_edge,
+						  bool level_trigger)
+{
+	unsigned long flags;
+
+	/* follow steps in the GPIO documentation for
+	 * "Setting Edge-Sensitive Interrupt Input Mode" and
+	 * "Setting Level-Sensitive Interrupt Input Mode"
+	 */
+
+	spin_lock_irqsave(&p->lock, flags);
+
+	/* Configure postive or negative logic in POSNEG */
+	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
+
+	/* Configure edge or level trigger in EDGLEVEL */
+	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
+
+	/* Select "Interrupt Input Mode" in IOINTSEL */
+	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
+
+	/* Write INTCLR in case of edge trigger */
+	if (!level_trigger)
+		gpio_rcar_write(p, INTCLR, BIT(hwirq));
+
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+	unsigned int hwirq = irqd_to_hwirq(d);
+
+	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
+{
+	struct gpio_rcar_priv *p = dev_id;
+	u32 pending;
+	unsigned int offset, irqs_handled = 0;
+
+	while ((pending = gpio_rcar_read(p, INTDT))) {
+		offset = __ffs(pending);
+		gpio_rcar_write(p, INTCLR, BIT(offset));
+		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+		irqs_handled++;
+	}
+
+	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
+}
+
+static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
+						       unsigned int gpio,
+						       bool output)
+{
+	struct gpio_rcar_priv *p = gpio_to_priv(chip);
+	unsigned long flags;
+
+	/* follow steps in the GPIO documentation for
+	 * "Setting General Output Mode" and
+	 * "Setting General Input Mode"
+	 */
+
+	spin_lock_irqsave(&p->lock, flags);
+
+	/* Configure postive logic in POSNEG */
+	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
+
+	/* Select "General Input/Output Mode" in IOINTSEL */
+	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
+
+	/* Select Input Mode or Output Mode in INOUTSEL */
+	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
+
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	gpio_rcar_config_general_input_output_mode(chip, offset, false);
+	return 0;
+}
+
+static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
+{
+	return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
+}
+
+static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	struct gpio_rcar_priv *p = gpio_to_priv(chip);
+	unsigned long flags;
+
+	spin_lock_irqsave(&p->lock, flags);
+	gpio_rcar_modify_bit(p, OUTDT, offset, value);
+	spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
+				      int value)
+{
+	/* write GPIO value to output before selecting output mode of pin */
+	gpio_rcar_set(chip, offset, value);
+	gpio_rcar_config_general_input_output_mode(chip, offset, true);
+	return 0;
+}
+
+static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
+}
+
+static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
+				 irq_hw_number_t hw)
+{
+	struct gpio_rcar_priv *p = h->host_data;
+
+	dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
+
+	irq_set_chip_data(virq, h->host_data);
+	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID); /* kill me now */
+	return 0;
+}
+
+static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
+	.map	= gpio_rcar_irq_domain_map,
+};
+
+static int gpio_rcar_probe(struct platform_device *pdev)
+{
+	struct gpio_rcar_config *pdata = pdev->dev.platform_data;
+	struct gpio_rcar_priv *p;
+	struct resource *io, *irq;
+	struct gpio_chip *gpio_chip;
+	struct irq_chip *irq_chip;
+	const char *name = dev_name(&pdev->dev);
+	int ret;
+
+	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+	if (!p) {
+		dev_err(&pdev->dev, "failed to allocate driver data\n");
+		ret = -ENOMEM;
+		goto err0;
+	}
+
+	/* deal with driver instance configuration */
+	if (pdata)
+		p->config = *pdata;
+
+	p->pdev = pdev;
+	platform_set_drvdata(pdev, p);
+	spin_lock_init(&p->lock);
+
+	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+	if (!io || !irq) {
+		dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
+		ret = -EINVAL;
+		goto err0;
+	}
+
+	p->base = devm_ioremap_nocache(&pdev->dev, io->start,
+				       resource_size(io));
+	if (!p->base) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		ret = -ENXIO;
+		goto err0;
+	}
+
+	gpio_chip = &p->gpio_chip;
+	gpio_chip->direction_input = gpio_rcar_direction_input;
+	gpio_chip->get = gpio_rcar_get;
+	gpio_chip->direction_output = gpio_rcar_direction_output;
+	gpio_chip->set = gpio_rcar_set;
+	gpio_chip->to_irq = gpio_rcar_to_irq;
+	gpio_chip->label = name;
+	gpio_chip->owner = THIS_MODULE;
+	gpio_chip->base = p->config.gpio_base;
+	gpio_chip->ngpio = p->config.number_of_pins;
+
+	irq_chip = &p->irq_chip;
+	irq_chip->name = name;
+	irq_chip->irq_mask = gpio_rcar_irq_disable;
+	irq_chip->irq_unmask = gpio_rcar_irq_enable;
+	irq_chip->irq_enable = gpio_rcar_irq_enable;
+	irq_chip->irq_disable = gpio_rcar_irq_disable;
+	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
+	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
+
+	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
+					      p->config.number_of_pins,
+					      p->config.irq_base,
+					      &gpio_rcar_irq_domain_ops, p);
+	if (!p->irq_domain) {
+		ret = -ENXIO;
+		dev_err(&pdev->dev, "cannot initialize irq domain\n");
+		goto err1;
+	}
+
+	if (devm_request_irq(&pdev->dev, irq->start,
+			     gpio_rcar_irq_handler, 0, name, p)) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		ret = -ENOENT;
+		goto err1;
+	}
+
+	ret = gpiochip_add(gpio_chip);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add GPIO controller\n");
+		goto err1;
+	}
+
+	dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
+
+	/* warn in case of mismatch if irq base is specified */
+	if (p->config.irq_base) {
+		ret = irq_find_mapping(p->irq_domain, 0);
+		if (p->config.irq_base != ret)
+			dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
+				 p->config.irq_base, ret);
+	}
+
+	return 0;
+
+err1:
+	irq_domain_remove(p->irq_domain);
+err0:
+	return ret;
+}
+
+static int gpio_rcar_remove(struct platform_device *pdev)
+{
+	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = gpiochip_remove(&p->gpio_chip);
+	if (ret)
+		return ret;
+
+	irq_domain_remove(p->irq_domain);
+	return 0;
+}
+
+static struct platform_driver gpio_rcar_device_driver = {
+	.probe		= gpio_rcar_probe,
+	.remove		= gpio_rcar_remove,
+	.driver		= {
+		.name	= "gpio_rcar",
+	}
+};
+
+module_platform_driver(gpio_rcar_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
new file mode 100644
index 0000000..bebfcd8
--- /dev/null
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -0,0 +1,25 @@
+/*
+ * Renesas R-Car GPIO Support
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __GPIO_RCAR_H__
+#define __GPIO_RCAR_H__
+
+struct gpio_rcar_config {
+	unsigned int gpio_base;
+	unsigned int irq_base;
+	unsigned int number_of_pins;
+};
+
+#endif /* __GPIO_RCAR_H__ */
-- 
1.7.10.4

[PATCH 07/28] gpio-rcar: Add pinctrl support

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/gpio-rcar.c                |   23 +++++++++++++++++++++++
 include/linux/platform_data/gpio-rcar.h |    1 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 581ba56..b4ca450 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -22,6 +22,7 @@
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
@@ -190,6 +191,21 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 	spin_unlock_irqrestore(&p->lock, flags);
 }
 
+static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
+{
+	return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
+{
+	pinctrl_free_gpio(chip->base + offset);
+
+	/* Set the GPIO as an input to ensure that the next GPIO request won't
+	 * drive the GPIO pin as an output.
+	 */
+	gpio_rcar_config_general_input_output_mode(chip, offset, false);
+}
+
 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
@@ -285,6 +301,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	}
 
 	gpio_chip = &p->gpio_chip;
+	gpio_chip->request = gpio_rcar_request;
+	gpio_chip->free = gpio_rcar_free;
 	gpio_chip->direction_input = gpio_rcar_direction_input;
 	gpio_chip->get = gpio_rcar_get;
 	gpio_chip->direction_output = gpio_rcar_direction_output;
@@ -337,6 +355,11 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 				 p->config.irq_base, ret);
 	}
 
+	ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
+				     gpio_chip->base, gpio_chip->ngpio);
+	if (ret < 0)
+		dev_warn(&pdev->dev, "failed to add pin range\n");
+
 	return 0;
 
 err1:
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index bebfcd8..b253f77 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -20,6 +20,7 @@ struct gpio_rcar_config {
 	unsigned int gpio_base;
 	unsigned int irq_base;
 	unsigned int number_of_pins;
+	const char *pctl_name;
 };
 
 #endif /* __GPIO_RCAR_H__ */
-- 
1.7.10.4

[PATCH 07/28] gpio-rcar: Add pinctrl support

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/gpio-rcar.c                |   23 +++++++++++++++++++++++
 include/linux/platform_data/gpio-rcar.h |    1 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 581ba56..b4ca450 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -22,6 +22,7 @@
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
@@ -190,6 +191,21 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 	spin_unlock_irqrestore(&p->lock, flags);
 }
 
+static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
+{
+	return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
+{
+	pinctrl_free_gpio(chip->base + offset);
+
+	/* Set the GPIO as an input to ensure that the next GPIO request won't
+	 * drive the GPIO pin as an output.
+	 */
+	gpio_rcar_config_general_input_output_mode(chip, offset, false);
+}
+
 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
@@ -285,6 +301,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	}
 
 	gpio_chip = &p->gpio_chip;
+	gpio_chip->request = gpio_rcar_request;
+	gpio_chip->free = gpio_rcar_free;
 	gpio_chip->direction_input = gpio_rcar_direction_input;
 	gpio_chip->get = gpio_rcar_get;
 	gpio_chip->direction_output = gpio_rcar_direction_output;
@@ -337,6 +355,11 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 				 p->config.irq_base, ret);
 	}
 
+	ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
+				     gpio_chip->base, gpio_chip->ngpio);
+	if (ret < 0)
+		dev_warn(&pdev->dev, "failed to add pin range\n");
+
 	return 0;
 
 err1:
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index bebfcd8..b253f77 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -20,6 +20,7 @@ struct gpio_rcar_config {
 	unsigned int gpio_base;
 	unsigned int irq_base;
 	unsigned int number_of_pins;
+	const char *pctl_name;
 };
 
 #endif /* __GPIO_RCAR_H__ */
-- 
1.7.10.4

[PATCH 08/28] ARM: shmobile: marzen: Add GPIO LEDs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The board has 3 LEDs connected to GPIOs. Add a led-gpio device to
support them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 5852331..a88f7f3 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,6 +25,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
 	.num_resources	= ARRAY_SIZE(usb_phy_resources),
 };
 
+/* LEDS */
+static struct gpio_led marzen_leds[] = {
+	{
+		.name		= "led2",
+		.gpio		= 157,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	}, {
+		.name		= "led3",
+		.gpio		= 158,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	}, {
+		.name		= "led4",
+		.gpio		= 159,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	},
+};
+
+static struct gpio_led_platform_data marzen_leds_pdata = {
+	.leds		= marzen_leds,
+	.num_leds	= ARRAY_SIZE(marzen_leds),
+};
+
+static struct platform_device leds_device = {
+	.name	= "leds-gpio",
+	.id	= 0,
+	.dev	= {
+		.platform_data  = &marzen_leds_pdata,
+	},
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
 	&sdhi0_device,
 	&thermal_device,
 	&hspi_device,
 	&usb_phy_device,
+	&leds_device,
 };
 
 /* USB */
-- 
1.7.10.4

[PATCH 08/28] ARM: shmobile: marzen: Add GPIO LEDs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The board has 3 LEDs connected to GPIOs. Add a led-gpio device to
support them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 5852331..a88f7f3 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,6 +25,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
 	.num_resources	= ARRAY_SIZE(usb_phy_resources),
 };
 
+/* LEDS */
+static struct gpio_led marzen_leds[] = {
+	{
+		.name		= "led2",
+		.gpio		= 157,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	}, {
+		.name		= "led3",
+		.gpio		= 158,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	}, {
+		.name		= "led4",
+		.gpio		= 159,
+		.default_state	= LEDS_GPIO_DEFSTATE_ON,
+	},
+};
+
+static struct gpio_led_platform_data marzen_leds_pdata = {
+	.leds		= marzen_leds,
+	.num_leds	= ARRAY_SIZE(marzen_leds),
+};
+
+static struct platform_device leds_device = {
+	.name	= "leds-gpio",
+	.id	= 0,
+	.dev	= {
+		.platform_data  = &marzen_leds_pdata,
+	},
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
 	&sdhi0_device,
 	&thermal_device,
 	&hspi_device,
 	&usb_phy_device,
+	&leds_device,
 };
 
 /* USB */
-- 
1.7.10.4

[PATCH 09/28] sh-pfc: Make function GPIOs support optional

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index d7acb06..7a54ec7 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -384,6 +384,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	}
 
 	/* Register the function GPIOs chip. */
+	if (pfc->info->nr_func_gpios = 0)
+		return 0;
+
 	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
-- 
1.7.10.4

[PATCH 09/28] sh-pfc: Make function GPIOs support optional

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index d7acb06..7a54ec7 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -384,6 +384,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	}
 
 	/* Register the function GPIOs chip. */
+	if (pfc->info->nr_func_gpios == 0)
+		return 0;
+
 	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
-- 
1.7.10.4

[PATCH 10/28] sh-pfc: Make GPIO support optional

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.

If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 7a54ec7..317cebb 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -354,6 +354,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	unsigned int i;
 	int ret;
 
+	if (pfc->info->data_regs = NULL)
+		return 0;
+
 	/* Register the real GPIOs chip. */
 	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
 	if (IS_ERR(chip))
-- 
1.7.10.4

[PATCH 10/28] sh-pfc: Make GPIO support optional

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.

If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 7a54ec7..317cebb 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -354,6 +354,9 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	unsigned int i;
 	int ret;
 
+	if (pfc->info->data_regs == NULL)
+		return 0;
+
 	/* Register the real GPIOs chip. */
 	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
 	if (IS_ERR(chip))
-- 
1.7.10.4

[PATCH 11/28] sh-pfc: Skip gpiochip registration when no GPIO resource is found

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.

This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |   39 +++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 317cebb..d37efa7 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -101,24 +101,9 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
 {
 	struct sh_pfc *pfc = chip->pfc;
-	unsigned long addr = pfc->info->data_regs[0].reg;
 	const struct pinmux_data_reg *dreg;
 	unsigned int i;
 
-	/* Find the window that contain the GPIO registers. */
-	for (i = 0; i < pfc->num_windows; ++i) {
-		struct sh_pfc_window *window = &pfc->window[i];
-
-		if (addr >= window->phys && addr < window->phys + window->size)
-			break;
-	}
-
-	if (i = pfc->num_windows)
-		return -EINVAL;
-
-	/* GPIO data registers must be in the first memory resource. */
-	chip->mem = &pfc->window[i];
-
 	/* Count the number of data registers, allocate memory and initialize
 	 * them.
 	 */
@@ -319,7 +304,8 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
  */
 
 static struct sh_pfc_chip *
-sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
+		    struct sh_pfc_window *mem)
 {
 	struct sh_pfc_chip *chip;
 	int ret;
@@ -328,6 +314,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
 	if (unlikely(!chip))
 		return ERR_PTR(-ENOMEM);
 
+	chip->mem = mem;
 	chip->pfc = pfc;
 
 	ret = setup(chip);
@@ -357,8 +344,24 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	if (pfc->info->data_regs = NULL)
 		return 0;
 
+	/* Find the memory window that contain the GPIO registers. Boards that
+	 * register a separate GPIO device will not supply a memory resource
+	 * that covers the data registers. In that case don't try to handle
+	 * GPIOs.
+	 */
+	for (i = 0; i < pfc->num_windows; ++i) {
+		struct sh_pfc_window *window = &pfc->window[i];
+
+		if (pfc->info->data_regs[0].reg >= window->phys &&
+		    pfc->info->data_regs[0].reg < window->phys + window->size)
+			break;
+	}
+
+	if (i = pfc->num_windows)
+		return 0;
+
 	/* Register the real GPIOs chip. */
-	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
+	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 
@@ -390,7 +393,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	if (pfc->info->nr_func_gpios = 0)
 		return 0;
 
-	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
+	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 
-- 
1.7.10.4

[PATCH 11/28] sh-pfc: Skip gpiochip registration when no GPIO resource is found

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.

This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/gpio.c |   39 +++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 317cebb..d37efa7 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -101,24 +101,9 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
 {
 	struct sh_pfc *pfc = chip->pfc;
-	unsigned long addr = pfc->info->data_regs[0].reg;
 	const struct pinmux_data_reg *dreg;
 	unsigned int i;
 
-	/* Find the window that contain the GPIO registers. */
-	for (i = 0; i < pfc->num_windows; ++i) {
-		struct sh_pfc_window *window = &pfc->window[i];
-
-		if (addr >= window->phys && addr < window->phys + window->size)
-			break;
-	}
-
-	if (i == pfc->num_windows)
-		return -EINVAL;
-
-	/* GPIO data registers must be in the first memory resource. */
-	chip->mem = &pfc->window[i];
-
 	/* Count the number of data registers, allocate memory and initialize
 	 * them.
 	 */
@@ -319,7 +304,8 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
  */
 
 static struct sh_pfc_chip *
-sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
+		    struct sh_pfc_window *mem)
 {
 	struct sh_pfc_chip *chip;
 	int ret;
@@ -328,6 +314,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
 	if (unlikely(!chip))
 		return ERR_PTR(-ENOMEM);
 
+	chip->mem = mem;
 	chip->pfc = pfc;
 
 	ret = setup(chip);
@@ -357,8 +344,24 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	if (pfc->info->data_regs == NULL)
 		return 0;
 
+	/* Find the memory window that contain the GPIO registers. Boards that
+	 * register a separate GPIO device will not supply a memory resource
+	 * that covers the data registers. In that case don't try to handle
+	 * GPIOs.
+	 */
+	for (i = 0; i < pfc->num_windows; ++i) {
+		struct sh_pfc_window *window = &pfc->window[i];
+
+		if (pfc->info->data_regs[0].reg >= window->phys &&
+		    pfc->info->data_regs[0].reg < window->phys + window->size)
+			break;
+	}
+
+	if (i == pfc->num_windows)
+		return 0;
+
 	/* Register the real GPIOs chip. */
-	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
+	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 
@@ -390,7 +393,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 	if (pfc->info->nr_func_gpios == 0)
 		return 0;
 
-	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
+	chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 
-- 
1.7.10.4

[PATCH 12/28] sh-pfc: Configure pins as GPIOs at request time when handled externally

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/core.c    |   37 ++++++++++++++++---------------------
 drivers/pinctrl/sh-pfc/pinctrl.c |   11 +++++++++++
 2 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 97e6ea3..ced9a95 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -268,7 +268,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	int ret;
 
 	switch (pinmux_type) {
-
+	case PINMUX_TYPE_GPIO:
 	case PINMUX_TYPE_FUNCTION:
 		range = NULL;
 		break;
@@ -297,6 +297,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	enum_id = 0;
 	field = 0;
 	value = 0;
+
+	/* Iterate over all the configuration fields we need to update. */
 	while (1) {
 		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 		if (pos < 0)
@@ -305,18 +307,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 		if (!enum_id)
 			break;
 
-		/* first check if this is a function enum */
+		/* Check if the configuration field selects a function. If it
+		 * doesn't, skip the field if it's not applicable to the
+		 * requested pinmux type.
+		 */
 		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 		if (!in_range) {
-			/* not a function enum */
-			if (range) {
-				/*
-				 * other range exists, so this pin is
-				 * a regular GPIO pin that now is being
-				 * bound to a specific direction.
-				 *
-				 * for this case we only allow function enums
-				 * and the enums that match the other range.
+			if (pinmux_type = PINMUX_TYPE_FUNCTION) {
+				/* Functions are allowed to modify all
+				 * fields.
+				 */
+				in_range = 1;
+			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
+				/* Input/output types can only modify fields
+				 * that correspond to their respective ranges.
 				 */
 				in_range = sh_pfc_enum_in_range(enum_id, range);
 
@@ -327,17 +331,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 				 */
 				if (in_range && enum_id = range->force)
 					continue;
-			} else {
-				/*
-				 * no other range exists, so this pin
-				 * must then be of the function type.
-				 *
-				 * allow function type pins to select
-				 * any combination of function/in/out
-				 * in their MARK lists.
-				 */
-				in_range = 1;
 			}
+			/* GPIOs are only allowed to modify function fields. */
 		}
 
 		if (!in_range)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index aef268b..3492ec9 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -182,6 +182,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
 		goto done;
 	}
 
+	if (!pfc->gpio) {
+		/* If GPIOs are handled externally the pin mux type need to be
+		 * set to GPIO here.
+		 */
+		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+
+		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
+		if (ret < 0)
+			goto done;
+	}
+
 	cfg->type = PINMUX_TYPE_GPIO;
 
 	ret = 0;
-- 
1.7.10.4

[PATCH 12/28] sh-pfc: Configure pins as GPIOs at request time when handled externally

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/core.c    |   37 ++++++++++++++++---------------------
 drivers/pinctrl/sh-pfc/pinctrl.c |   11 +++++++++++
 2 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 97e6ea3..ced9a95 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -268,7 +268,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	int ret;
 
 	switch (pinmux_type) {
-
+	case PINMUX_TYPE_GPIO:
 	case PINMUX_TYPE_FUNCTION:
 		range = NULL;
 		break;
@@ -297,6 +297,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 	enum_id = 0;
 	field = 0;
 	value = 0;
+
+	/* Iterate over all the configuration fields we need to update. */
 	while (1) {
 		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 		if (pos < 0)
@@ -305,18 +307,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 		if (!enum_id)
 			break;
 
-		/* first check if this is a function enum */
+		/* Check if the configuration field selects a function. If it
+		 * doesn't, skip the field if it's not applicable to the
+		 * requested pinmux type.
+		 */
 		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 		if (!in_range) {
-			/* not a function enum */
-			if (range) {
-				/*
-				 * other range exists, so this pin is
-				 * a regular GPIO pin that now is being
-				 * bound to a specific direction.
-				 *
-				 * for this case we only allow function enums
-				 * and the enums that match the other range.
+			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
+				/* Functions are allowed to modify all
+				 * fields.
+				 */
+				in_range = 1;
+			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
+				/* Input/output types can only modify fields
+				 * that correspond to their respective ranges.
 				 */
 				in_range = sh_pfc_enum_in_range(enum_id, range);
 
@@ -327,17 +331,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 				 */
 				if (in_range && enum_id == range->force)
 					continue;
-			} else {
-				/*
-				 * no other range exists, so this pin
-				 * must then be of the function type.
-				 *
-				 * allow function type pins to select
-				 * any combination of function/in/out
-				 * in their MARK lists.
-				 */
-				in_range = 1;
 			}
+			/* GPIOs are only allowed to modify function fields. */
 		}
 
 		if (!in_range)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index aef268b..3492ec9 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -182,6 +182,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
 		goto done;
 	}
 
+	if (!pfc->gpio) {
+		/* If GPIOs are handled externally the pin mux type need to be
+		 * set to GPIO here.
+		 */
+		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+
+		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
+		if (ret < 0)
+			goto done;
+	}
+
 	cfg->type = PINMUX_TYPE_GPIO;
 
 	ret = 0;
-- 
1.7.10.4

[PATCH 13/28] ARM: shmobile: r8a7779: Register GPIO devices

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Move GPIOs handling from the PFC device to separate GPIO devices.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7779.c |   58 ++++++++++++++++++++++++++++----
 1 file changed, 52 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35..a460ba3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
 		.end	= 0xfffc023b,
 		.flags	= IORESOURCE_MEM,
 	},
-	[1] = {
-		.start	= 0xffc40000,
-		.end	= 0xffc46fff,
-		.flags	= IORESOURCE_MEM,
-	}
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
 	.num_resources	= ARRAY_SIZE(r8a7779_pfc_resources),
 };
 
+#define R8A7779_GPIO(idx, npins) \
+static struct resource r8a7779_gpio##idx##_resources[] = {		\
+	[0] = {								\
+		.start	= 0xffc40000 + 0x1000 * (idx),			\
+		.end	= 0xffc4002b + 0x1000 * (idx),			\
+		.flags	= IORESOURCE_MEM,				\
+	},								\
+	[1] = {								\
+		.start	= gic_iid(0xad + (idx)),			\
+		.flags	= IORESOURCE_IRQ,				\
+	}								\
+};									\
+									\
+static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {	\
+	.gpio_base	= 32 * (idx),					\
+	.irq_base	= 0,						\
+	.number_of_pins	= npins,					\
+	.pctl_name	= "pfc-r8a7779",				\
+};									\
+									\
+static struct platform_device r8a7779_gpio##idx##_device = {		\
+	.name		= "gpio_rcar",					\
+	.id		= idx,						\
+	.resource	= r8a7779_gpio##idx##_resources,		\
+	.num_resources	= ARRAY_SIZE(r8a7779_gpio##idx##_resources),	\
+	.dev		= {						\
+		.platform_data	= &r8a7779_gpio##idx##_platform_data,	\
+	},								\
+}
+
+R8A7779_GPIO(0, 32);
+R8A7779_GPIO(1, 32);
+R8A7779_GPIO(2, 32);
+R8A7779_GPIO(3, 32);
+R8A7779_GPIO(4, 32);
+R8A7779_GPIO(5, 32);
+R8A7779_GPIO(6, 9);
+
+static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
+	&r8a7779_pfc_device,
+	&r8a7779_gpio0_device,
+	&r8a7779_gpio1_device,
+	&r8a7779_gpio2_device,
+	&r8a7779_gpio3_device,
+	&r8a7779_gpio4_device,
+	&r8a7779_gpio5_device,
+	&r8a7779_gpio6_device,
+};
+
 void __init r8a7779_pinmux_init(void)
 {
-	platform_device_register(&r8a7779_pfc_device);
+	platform_add_devices(r8a7779_pinctrl_devices,
+			    ARRAY_SIZE(r8a7779_pinctrl_devices));
 }
 
 static struct plat_sci_port scif0_platform_data = {
-- 
1.7.10.4

[PATCH 13/28] ARM: shmobile: r8a7779: Register GPIO devices

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Move GPIOs handling from the PFC device to separate GPIO devices.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7779.c |   58 ++++++++++++++++++++++++++++----
 1 file changed, 52 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35..a460ba3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
 		.end	= 0xfffc023b,
 		.flags	= IORESOURCE_MEM,
 	},
-	[1] = {
-		.start	= 0xffc40000,
-		.end	= 0xffc46fff,
-		.flags	= IORESOURCE_MEM,
-	}
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
 	.num_resources	= ARRAY_SIZE(r8a7779_pfc_resources),
 };
 
+#define R8A7779_GPIO(idx, npins) \
+static struct resource r8a7779_gpio##idx##_resources[] = {		\
+	[0] = {								\
+		.start	= 0xffc40000 + 0x1000 * (idx),			\
+		.end	= 0xffc4002b + 0x1000 * (idx),			\
+		.flags	= IORESOURCE_MEM,				\
+	},								\
+	[1] = {								\
+		.start	= gic_iid(0xad + (idx)),			\
+		.flags	= IORESOURCE_IRQ,				\
+	}								\
+};									\
+									\
+static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {	\
+	.gpio_base	= 32 * (idx),					\
+	.irq_base	= 0,						\
+	.number_of_pins	= npins,					\
+	.pctl_name	= "pfc-r8a7779",				\
+};									\
+									\
+static struct platform_device r8a7779_gpio##idx##_device = {		\
+	.name		= "gpio_rcar",					\
+	.id		= idx,						\
+	.resource	= r8a7779_gpio##idx##_resources,		\
+	.num_resources	= ARRAY_SIZE(r8a7779_gpio##idx##_resources),	\
+	.dev		= {						\
+		.platform_data	= &r8a7779_gpio##idx##_platform_data,	\
+	},								\
+}
+
+R8A7779_GPIO(0, 32);
+R8A7779_GPIO(1, 32);
+R8A7779_GPIO(2, 32);
+R8A7779_GPIO(3, 32);
+R8A7779_GPIO(4, 32);
+R8A7779_GPIO(5, 32);
+R8A7779_GPIO(6, 9);
+
+static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
+	&r8a7779_pfc_device,
+	&r8a7779_gpio0_device,
+	&r8a7779_gpio1_device,
+	&r8a7779_gpio2_device,
+	&r8a7779_gpio3_device,
+	&r8a7779_gpio4_device,
+	&r8a7779_gpio5_device,
+	&r8a7779_gpio6_device,
+};
+
 void __init r8a7779_pinmux_init(void)
 {
-	platform_device_register(&r8a7779_pfc_device);
+	platform_add_devices(r8a7779_pinctrl_devices,
+			    ARRAY_SIZE(r8a7779_pinctrl_devices));
 }
 
 static struct plat_sci_port scif0_platform_data = {
-- 
1.7.10.4

[PATCH 14/28] sh-pfc: r8a7779: Remove GPIO data

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   58 +---------------------------------
 1 file changed, 1 insertion(+), 57 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 41d8bda..e448ff1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -85,18 +85,12 @@
 	}
 
 #define _GP_DATA(bank, pin, name, sfx)					\
-	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
-
-#define _GP_INOUTSEL(bank, pin, name, sfx)	name##_IN, name##_OUT
-#define _GP_INDT(bank, pin, name, sfx)		name##_DATA
+	PINMUX_DATA(name##_DATA, name##_FN)
 
 #define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
 #define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
 #define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
 
-#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
-#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
-
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
 							  FN_##ipsr, FN_##fn)
@@ -108,14 +102,6 @@ enum {
 	GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
 	PINMUX_DATA_END,
 
-	PINMUX_INPUT_BEGIN,
-	GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
-	PINMUX_OUTPUT_END,
-
 	PINMUX_FUNCTION_BEGIN,
 	GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
 
@@ -3549,45 +3535,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	    /* SEL_I2C1 [2] */
 	    FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
 	},
-	{ PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
-	{ PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
-	{ PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
-	{ PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
-	{ PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
-	{ PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
-	{ PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_8_IN, GP_6_8_OUT,
-		GP_6_7_IN, GP_6_7_OUT,
-		GP_6_6_IN, GP_6_6_OUT,
-		GP_6_5_IN, GP_6_5_OUT,
-		GP_6_4_IN, GP_6_4_OUT,
-		GP_6_3_IN, GP_6_3_OUT,
-		GP_6_2_IN, GP_6_2_OUT,
-		GP_6_1_IN, GP_6_1_OUT,
-		GP_6_0_IN, GP_6_0_OUT, }
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
-	{ PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
-	{ PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
-	{ PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
-	{ PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
-	{ PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
-	{ PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
-		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
-		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
-	},
 	{ },
 };
 
@@ -3596,8 +3543,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 
 	.unlock_reg = 0xfffc0000, /* PMMR */
 
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
 	.pins = pinmux_pins,
@@ -3608,7 +3553,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
 	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
 
 	.gpio_data = pinmux_data,
 	.gpio_data_size = ARRAY_SIZE(pinmux_data),
-- 
1.7.10.4

[PATCH 14/28] sh-pfc: r8a7779: Remove GPIO data

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   58 +---------------------------------
 1 file changed, 1 insertion(+), 57 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 41d8bda..e448ff1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -85,18 +85,12 @@
 	}
 
 #define _GP_DATA(bank, pin, name, sfx)					\
-	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
-
-#define _GP_INOUTSEL(bank, pin, name, sfx)	name##_IN, name##_OUT
-#define _GP_INDT(bank, pin, name, sfx)		name##_DATA
+	PINMUX_DATA(name##_DATA, name##_FN)
 
 #define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
 #define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
 #define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
 
-#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
-#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
-
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
 							  FN_##ipsr, FN_##fn)
@@ -108,14 +102,6 @@ enum {
 	GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
 	PINMUX_DATA_END,
 
-	PINMUX_INPUT_BEGIN,
-	GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
-	PINMUX_OUTPUT_END,
-
 	PINMUX_FUNCTION_BEGIN,
 	GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
 
@@ -3549,45 +3535,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	    /* SEL_I2C1 [2] */
 	    FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
 	},
-	{ PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
-	{ PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
-	{ PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
-	{ PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
-	{ PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
-	{ PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
-	{ PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		GP_6_8_IN, GP_6_8_OUT,
-		GP_6_7_IN, GP_6_7_OUT,
-		GP_6_6_IN, GP_6_6_OUT,
-		GP_6_5_IN, GP_6_5_OUT,
-		GP_6_4_IN, GP_6_4_OUT,
-		GP_6_3_IN, GP_6_3_OUT,
-		GP_6_2_IN, GP_6_2_OUT,
-		GP_6_1_IN, GP_6_1_OUT,
-		GP_6_0_IN, GP_6_0_OUT, }
-	},
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
-	{ PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
-	{ PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
-	{ PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
-	{ PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
-	{ PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
-	{ PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
-		0, 0, 0, 0, 0, 0, 0, 0,	0, 0, 0, 0, 0, 0, 0, 0,
-		0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
-		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
-		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
-	},
 	{ },
 };
 
@@ -3596,8 +3543,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 
 	.unlock_reg = 0xfffc0000, /* PMMR */
 
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
 	.pins = pinmux_pins,
@@ -3608,7 +3553,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
 	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
 
 	.gpio_data = pinmux_data,
 	.gpio_data_size = ARRAY_SIZE(pinmux_data),
-- 
1.7.10.4

[PATCH 15/28] sh-pfc: r8a7779: Split DU input and output pixel clocks

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   60 ++++++++++++++++++++++------------
 1 file changed, 39 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index e448ff1..62dcdcd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1498,19 +1498,26 @@ static const unsigned int du0_rgb888_mux[] = {
 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
 	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
 };
-static const unsigned int du0_clk_0_pins[] = {
-	/* CLKIN, CLKOUT */
-	29, 180,
+static const unsigned int du0_clk_in_pins[] = {
+	/* CLKIN */
+	29,
 };
-static const unsigned int du0_clk_0_mux[] = {
-	DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
+static const unsigned int du0_clk_in_mux[] = {
+	DU0_DOTCLKIN_MARK,
 };
-static const unsigned int du0_clk_1_pins[] = {
-	/* CLKIN, CLKOUT */
-	29, 30,
+static const unsigned int du0_clk_out_0_pins[] = {
+	/* CLKOUT */
+	180,
 };
-static const unsigned int du0_clk_1_mux[] = {
-	DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
+static const unsigned int du0_clk_out_0_mux[] = {
+	DU0_DOTCLKOUT0_MARK,
+};
+static const unsigned int du0_clk_out_1_pins[] = {
+	/* CLKOUT */
+	30,
+};
+static const unsigned int du0_clk_out_1_mux[] = {
+	DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
@@ -1571,12 +1578,19 @@ static const unsigned int du1_rgb888_mux[] = {
 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
 	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
 };
-static const unsigned int du1_clk_pins[] = {
-	/* CLKIN, CLKOUT */
-	58, 59,
+static const unsigned int du1_clk_in_pins[] = {
+	/* CLKIN */
+	58,
+};
+static const unsigned int du1_clk_in_mux[] = {
+	DU1_DOTCLKIN_MARK,
+};
+static const unsigned int du1_clk_out_pins[] = {
+	/* CLKOUT */
+	59,
 };
-static const unsigned int du1_clk_mux[] = {
-	DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
+static const unsigned int du1_clk_out_mux[] = {
+	DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
@@ -2369,15 +2383,17 @@ static const unsigned int usb2_mux[] = {
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(du0_rgb666),
 	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk_0),
-	SH_PFC_PIN_GROUP(du0_clk_1),
+	SH_PFC_PIN_GROUP(du0_clk_in),
+	SH_PFC_PIN_GROUP(du0_clk_out_0),
+	SH_PFC_PIN_GROUP(du0_clk_out_1),
 	SH_PFC_PIN_GROUP(du0_sync_0),
 	SH_PFC_PIN_GROUP(du0_sync_1),
 	SH_PFC_PIN_GROUP(du0_oddf),
 	SH_PFC_PIN_GROUP(du0_cde),
 	SH_PFC_PIN_GROUP(du1_rgb666),
 	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk),
+	SH_PFC_PIN_GROUP(du1_clk_in),
+	SH_PFC_PIN_GROUP(du1_clk_out),
 	SH_PFC_PIN_GROUP(du1_sync_0),
 	SH_PFC_PIN_GROUP(du1_sync_1),
 	SH_PFC_PIN_GROUP(du1_oddf),
@@ -2492,8 +2508,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 static const char * const du0_groups[] = {
 	"du0_rgb666",
 	"du0_rgb888",
-	"du0_clk_0",
-	"du0_clk_1",
+	"du0_clk_in",
+	"du0_clk_out_0",
+	"du0_clk_out_1",
 	"du0_sync_0",
 	"du0_sync_1",
 	"du0_oddf",
@@ -2503,7 +2520,8 @@ static const char * const du0_groups[] = {
 static const char * const du1_groups[] = {
 	"du1_rgb666",
 	"du1_rgb888",
-	"du1_clk",
+	"du1_clk_in",
+	"du1_clk_out",
 	"du1_sync_0",
 	"du1_sync_1",
 	"du1_oddf",
-- 
1.7.10.4

[PATCH 15/28] sh-pfc: r8a7779: Split DU input and output pixel clocks

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c |   60 ++++++++++++++++++++++------------
 1 file changed, 39 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index e448ff1..62dcdcd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1498,19 +1498,26 @@ static const unsigned int du0_rgb888_mux[] = {
 	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
 	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
 };
-static const unsigned int du0_clk_0_pins[] = {
-	/* CLKIN, CLKOUT */
-	29, 180,
+static const unsigned int du0_clk_in_pins[] = {
+	/* CLKIN */
+	29,
 };
-static const unsigned int du0_clk_0_mux[] = {
-	DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
+static const unsigned int du0_clk_in_mux[] = {
+	DU0_DOTCLKIN_MARK,
 };
-static const unsigned int du0_clk_1_pins[] = {
-	/* CLKIN, CLKOUT */
-	29, 30,
+static const unsigned int du0_clk_out_0_pins[] = {
+	/* CLKOUT */
+	180,
 };
-static const unsigned int du0_clk_1_mux[] = {
-	DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
+static const unsigned int du0_clk_out_0_mux[] = {
+	DU0_DOTCLKOUT0_MARK,
+};
+static const unsigned int du0_clk_out_1_pins[] = {
+	/* CLKOUT */
+	30,
+};
+static const unsigned int du0_clk_out_1_mux[] = {
+	DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
@@ -1571,12 +1578,19 @@ static const unsigned int du1_rgb888_mux[] = {
 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
 	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
 };
-static const unsigned int du1_clk_pins[] = {
-	/* CLKIN, CLKOUT */
-	58, 59,
+static const unsigned int du1_clk_in_pins[] = {
+	/* CLKIN */
+	58,
+};
+static const unsigned int du1_clk_in_mux[] = {
+	DU1_DOTCLKIN_MARK,
+};
+static const unsigned int du1_clk_out_pins[] = {
+	/* CLKOUT */
+	59,
 };
-static const unsigned int du1_clk_mux[] = {
-	DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
+static const unsigned int du1_clk_out_mux[] = {
+	DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
@@ -2369,15 +2383,17 @@ static const unsigned int usb2_mux[] = {
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(du0_rgb666),
 	SH_PFC_PIN_GROUP(du0_rgb888),
-	SH_PFC_PIN_GROUP(du0_clk_0),
-	SH_PFC_PIN_GROUP(du0_clk_1),
+	SH_PFC_PIN_GROUP(du0_clk_in),
+	SH_PFC_PIN_GROUP(du0_clk_out_0),
+	SH_PFC_PIN_GROUP(du0_clk_out_1),
 	SH_PFC_PIN_GROUP(du0_sync_0),
 	SH_PFC_PIN_GROUP(du0_sync_1),
 	SH_PFC_PIN_GROUP(du0_oddf),
 	SH_PFC_PIN_GROUP(du0_cde),
 	SH_PFC_PIN_GROUP(du1_rgb666),
 	SH_PFC_PIN_GROUP(du1_rgb888),
-	SH_PFC_PIN_GROUP(du1_clk),
+	SH_PFC_PIN_GROUP(du1_clk_in),
+	SH_PFC_PIN_GROUP(du1_clk_out),
 	SH_PFC_PIN_GROUP(du1_sync_0),
 	SH_PFC_PIN_GROUP(du1_sync_1),
 	SH_PFC_PIN_GROUP(du1_oddf),
@@ -2492,8 +2508,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 static const char * const du0_groups[] = {
 	"du0_rgb666",
 	"du0_rgb888",
-	"du0_clk_0",
-	"du0_clk_1",
+	"du0_clk_in",
+	"du0_clk_out_0",
+	"du0_clk_out_1",
 	"du0_sync_0",
 	"du0_sync_1",
 	"du0_oddf",
@@ -2503,7 +2520,8 @@ static const char * const du0_groups[] = {
 static const char * const du1_groups[] = {
 	"du1_rgb666",
 	"du1_rgb888",
-	"du1_clk",
+	"du1_clk_in",
+	"du1_clk_out",
 	"du1_sync_0",
 	"du1_sync_1",
 	"du1_oddf",
-- 
1.7.10.4

[PATCH 16/28] sh-pfc: Add r8a73a4 pinmux support

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Add initial PFC support for the r8a73a4 SoC.

At this point only GPIO interface is supported, move to newer interfaces
planned as incremental changes.

Original authors are Morimoto-san with help from Yoshii-san, thanks to
them for the heavy lifting. Adjusted by Magnus to work together with
updated code in drivers/pinctrl.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |  918 ++++++++
 drivers/pinctrl/sh-pfc/Kconfig                |    5 +
 drivers/pinctrl/sh-pfc/Makefile               |    1 +
 drivers/pinctrl/sh-pfc/core.c                 |    3 +
 drivers/pinctrl/sh-pfc/core.h                 |    1 +
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          | 2826 +++++++++++++++++++++++++
 6 files changed, 3754 insertions(+)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103..f0b1b4a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -1,6 +1,924 @@
 #ifndef __ASM_R8A73A4_H__
 #define __ASM_R8A73A4_H__
 
+/*
+ * Pin Function Controller:
+ *	GPIO_FN_xx - GPIO used to select pin function
+ *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+
+	/* PORT */
+	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+	GPIO_PORT30, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+	GPIO_PORT40, GPIO_PORT64,
+	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+	GPIO_PORT85, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+	GPIO_PORT125, GPIO_PORT126, GPIO_PORT128, GPIO_PORT129,
+
+	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+
+	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178,
+
+	GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+	GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+	GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+	GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT224,
+	GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+	GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+	GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+	GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+	GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+	GPIO_PORT250, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+	GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+	GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+	GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+	GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+	GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, GPIO_PORT283,
+	GPIO_PORT288, GPIO_PORT289,
+
+	GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+	GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+	GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+	GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308,
+
+	GPIO_PORT320, GPIO_PORT321, GPIO_PORT322, GPIO_PORT323, GPIO_PORT324,
+	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
+
+	/* Port0 */
+	GPIO_FN_LCDD0,
+	GPIO_FN_PDM2_CLK_0,
+	GPIO_FN_DU0_DR0,
+	GPIO_FN_IRQ0,
+
+	/* Port1 */
+	GPIO_FN_LCDD1,
+	GPIO_FN_PDM2_DATA_1,
+	GPIO_FN_DU0_DR19,
+	GPIO_FN_IRQ1,
+
+	/* Port2 */
+	GPIO_FN_LCDD2,
+	GPIO_FN_PDM3_CLK_2,
+	GPIO_FN_DU0_DR2,
+	GPIO_FN_IRQ2,
+
+	/* Port3 */
+	GPIO_FN_LCDD3,
+	GPIO_FN_PDM3_DATA_3,
+	GPIO_FN_DU0_DR3,
+	GPIO_FN_IRQ3,
+
+	/* Port4 */
+	GPIO_FN_LCDD4,
+	GPIO_FN_PDM4_CLK_4,
+	GPIO_FN_DU0_DR4,
+	GPIO_FN_IRQ4,
+
+	/* Port5 */
+	GPIO_FN_LCDD5,
+	GPIO_FN_PDM4_DATA_5,
+	GPIO_FN_DU0_DR5,
+	GPIO_FN_IRQ5,
+
+	/* Port6 */
+	GPIO_FN_LCDD6,
+	GPIO_FN_PDM0_OUTCLK_6,
+	GPIO_FN_DU0_DR6,
+	GPIO_FN_IRQ6,
+
+	/* Port7 */
+	GPIO_FN_LCDD7,
+	GPIO_FN_PDM0_OUTDATA_7,
+	GPIO_FN_DU0_DR7,
+	GPIO_FN_IRQ7,
+
+	/* Port8 */
+	GPIO_FN_LCDD8,
+	GPIO_FN_PDM1_OUTCLK_8,
+	GPIO_FN_DU0_DG0,
+	GPIO_FN_IRQ8,
+
+	/* Port9 */
+	GPIO_FN_LCDD9,
+	GPIO_FN_PDM1_OUTDATA_9,
+	GPIO_FN_DU0_DG1,
+	GPIO_FN_IRQ9,
+
+	/* Port10 */
+	GPIO_FN_LCDD10,
+	GPIO_FN_FSICCK,
+	GPIO_FN_DU0_DG2,
+	GPIO_FN_IRQ10,
+
+	/* Port11 */
+	GPIO_FN_LCDD11,
+	GPIO_FN_FSICISLD,
+	GPIO_FN_DU0_DG3,
+	GPIO_FN_IRQ11,
+
+	/* Port12 */
+	GPIO_FN_LCDD12,
+	GPIO_FN_FSICOMC,
+	GPIO_FN_DU0_DG4,
+	GPIO_FN_IRQ12,
+
+	/* Port13 */
+	GPIO_FN_LCDD13,
+	GPIO_FN_FSICOLR,
+	GPIO_FN_FSICILR,
+	GPIO_FN_DU0_DG5,
+	GPIO_FN_IRQ13,
+
+	/* Port14 */
+	GPIO_FN_LCDD14,
+	GPIO_FN_FSICOBT,
+	GPIO_FN_FSICIBT,
+	GPIO_FN_DU0_DG6,
+	GPIO_FN_IRQ14,
+
+	/* Port15 */
+	GPIO_FN_LCDD15,
+	GPIO_FN_FSICOSLD,
+	GPIO_FN_DU0_DG7,
+	GPIO_FN_IRQ15,
+
+	/* Port16 */
+	GPIO_FN_LCDD16,
+	GPIO_FN_TPU1TO1,
+	GPIO_FN_DU0_DB0,
+
+	/* Port17 */
+	GPIO_FN_LCDD17,
+	GPIO_FN_SF_IRQ_00,
+	GPIO_FN_DU0_DB1,
+
+	/* Port18 */
+	GPIO_FN_LCDD18,
+	GPIO_FN_SF_IRQ_01,
+	GPIO_FN_DU0_DB2,
+
+	/* Port19 */
+	GPIO_FN_LCDD19,
+	GPIO_FN_SCIFB3_RTS_19,
+	GPIO_FN_DU0_DB3,
+
+	/* Port20 */
+	GPIO_FN_LCDD20,
+	GPIO_FN_SCIFB3_CTS_20,
+	GPIO_FN_DU0_DB4,
+
+	/* Port21 */
+	GPIO_FN_LCDD21,
+	GPIO_FN_SCIFB3_TXD_21,
+	GPIO_FN_DU0_DB5,
+
+	/* Port22 */
+	GPIO_FN_LCDD22,
+	GPIO_FN_SCIFB3_RXD_22,
+	GPIO_FN_DU0_DB6,
+
+	/* Port23 */
+	GPIO_FN_LCDD23,
+	GPIO_FN_SCIFB3_SCK_23,
+	GPIO_FN_DU0_DB7,
+
+	/* Port24 */
+	GPIO_FN_LCDHSYN,
+	GPIO_FN_LCDCS,
+	GPIO_FN_SCIFB1_RTS_24,
+	GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N,
+
+	/* Port25 */
+	GPIO_FN_LCDVSYN,
+	GPIO_FN_SCIFB1_CTS_25,
+	GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N,
+
+	/* Port26 */
+	GPIO_FN_LCDDCK,
+	GPIO_FN_LCDWR,
+	GPIO_FN_SCIFB1_TXD_26,
+	GPIO_FN_DU0_DOTCLKIN,
+
+	/* Port27 */
+	GPIO_FN_LCDDISP,
+	GPIO_FN_LCDRS,
+	GPIO_FN_SCIFB1_RXD_27,
+	GPIO_FN_DU0_DOTCLKOUT,
+
+	/* Port28 */
+	GPIO_FN_LCDRD_N,
+	GPIO_FN_SCIFB1_SCK_28,
+	GPIO_FN_DU0_DOTCLKOUTB,
+
+	/* Port29 */
+	GPIO_FN_LCDLCLK,
+	GPIO_FN_SF_IRQ_02,
+	GPIO_FN_DU0_DISP_CSYNC_N_DE,
+
+	/* Port30 */
+	GPIO_FN_LCDDON,
+	GPIO_FN_SF_IRQ_03,
+	GPIO_FN_DU0_ODDF_N_CLAMP,
+
+	/* Port32 */
+	GPIO_FN_SCIFA0_RTS,
+	GPIO_FN_SIM0_DET,
+	GPIO_FN_CSCIF0_RTS,
+
+	/* Port33 */
+	GPIO_FN_SCIFA0_CTS,
+	GPIO_FN_SIM1_DET,
+	GPIO_FN_CSCIF0_CTS,
+
+	/* Port34 */
+	GPIO_FN_SCIFA0_SCK,
+	GPIO_FN_SIM0_PWRON,
+	GPIO_FN_CSCIF0_SCK,
+
+	/* Port35 */
+	GPIO_FN_SCIFA1_RTS,
+	GPIO_FN_CSCIF1_RTS,
+
+	/* Port36 */
+	GPIO_FN_SCIFA1_CTS,
+	GPIO_FN_CSCIF1_CTS,
+
+	/* Port37 */
+	GPIO_FN_SCIFA1_SCK,
+	GPIO_FN_CSCIF1_SCK,
+
+	/* Port38 */
+	GPIO_FN_SCIFB0_RTS,
+	GPIO_FN_TPU0TO1,
+	GPIO_FN_SCIFB3_RTS_38,
+	GPIO_FN_CHSCIF0_HRTS,
+
+	/* Port39 */
+	GPIO_FN_SCIFB0_CTS,
+	GPIO_FN_TPU0TO2,
+	GPIO_FN_SCIFB3_CTS_39,
+	GPIO_FN_CHSCIF0_HCTS,
+
+	/* Port40 */
+	GPIO_FN_SCIFB0_SCK,
+	GPIO_FN_TPU0TO3,
+	GPIO_FN_SCIFB3_SCK_40,
+	GPIO_FN_CHSCIF0_HSCK,
+
+	/* Port64 */
+	GPIO_FN_PDM0_DATA,
+
+	/* Port65 */
+	GPIO_FN_PDM1_DATA,
+
+	/* Port66 */
+	GPIO_FN_HSI_RX_WAKE,
+	GPIO_FN_SCIFB2_CTS_66,
+	GPIO_FN_MSIOF3_SYNC,
+	GPIO_FN_GenIO4,
+	GPIO_FN_IRQ40,
+
+	/* Port67 */
+	GPIO_FN_HSI_RX_READY,
+	GPIO_FN_SCIFB1_TXD_67,
+	GPIO_FN_GIO_OUT3_67,
+	GPIO_FN_CHSCIF1_HTX,
+
+	/* Port68 */
+	GPIO_FN_HSI_RX_FLAG,
+	GPIO_FN_SCIFB2_TXD_68,
+	GPIO_FN_MSIOF3_TXD,
+	GPIO_FN_GIO_OUT4_68,
+
+	/* Port69 */
+	GPIO_FN_HSI_RX_DATA,
+	GPIO_FN_SCIFB2_RXD_69,
+	GPIO_FN_MSIOF3_RXD,
+	GPIO_FN_GIO_OUT5_69,
+
+	/* Port70 */
+	GPIO_FN_HSI_TX_FLAG,
+	GPIO_FN_SCIFB1_RTS_70,
+	GPIO_FN_GIO_OUT1_70,
+	GPIO_FN_HSIC_TSTCLK0,
+	GPIO_FN_CHSCIF1_HRTS,
+
+	/* Port71 */
+	GPIO_FN_HSI_TX_DATA,
+	GPIO_FN_SCIFB1_CTS_71,
+	GPIO_FN_GIO_OUT2_71,
+	GPIO_FN_HSIC_TSTCLK1,
+	GPIO_FN_CHSCIF1_HCTS,
+
+	/* Port72 */
+	GPIO_FN_HSI_TX_WAKE,
+	GPIO_FN_SCIFB1_RXD_72,
+	GPIO_FN_GenIO8,
+	GPIO_FN_CHSCIF1_HRX,
+
+	/* Port73 */
+	GPIO_FN_HSI_TX_READY,
+	GPIO_FN_SCIFB2_RTS_73,
+	GPIO_FN_MSIOF3_SCK,
+	GPIO_FN_GIO_OUT0_73,
+
+	/* Port74 - Port85 */
+	GPIO_FN_IRDA_OUT,
+	GPIO_FN_IRDA_IN,
+	GPIO_FN_IRDA_FIRSEL,
+	GPIO_FN_TPU0TO0,
+	GPIO_FN_DIGRFEN,
+	GPIO_FN_GPS_TIMESTAMP,
+	GPIO_FN_TXP,
+	GPIO_FN_TXP2,
+	GPIO_FN_COEX_0,
+	GPIO_FN_COEX_1,
+	GPIO_FN_IRQ19,
+	GPIO_FN_IRQ18,
+
+	/* Port96 - Port101 */
+	GPIO_FN_KEYIN0,
+	GPIO_FN_KEYIN1,
+	GPIO_FN_KEYIN2,
+	GPIO_FN_KEYIN3,
+	GPIO_FN_KEYIN4,
+	GPIO_FN_KEYIN5,
+
+	/* Port102 */
+	GPIO_FN_KEYIN6,
+	GPIO_FN_IRQ41,
+
+	/* Port103 */
+	GPIO_FN_KEYIN7,
+	GPIO_FN_IRQ42,
+
+	/* Port104 - Port108 */
+	GPIO_FN_KEYOUT0,
+	GPIO_FN_KEYOUT1,
+	GPIO_FN_KEYOUT2,
+	GPIO_FN_KEYOUT3,
+	GPIO_FN_KEYOUT4,
+
+	/* Port109 */
+	GPIO_FN_KEYOUT5,
+	GPIO_FN_IRQ43,
+
+	/* Port110 */
+	GPIO_FN_KEYOUT6,
+	GPIO_FN_IRQ44,
+
+	/* Port111 */
+	GPIO_FN_KEYOUT7,
+	GPIO_FN_RFANAEN,
+	GPIO_FN_IRQ45,
+
+	/* Port112 */
+	GPIO_FN_KEYIN8,
+	GPIO_FN_KEYOUT8,
+	GPIO_FN_SF_IRQ_04,
+	GPIO_FN_IRQ46,
+
+	/* Port113 */
+	GPIO_FN_KEYIN9,
+	GPIO_FN_KEYOUT9,
+	GPIO_FN_SF_IRQ_05,
+	GPIO_FN_IRQ47,
+
+	/* Port114 */
+	GPIO_FN_KEYIN10,
+	GPIO_FN_KEYOUT10,
+	GPIO_FN_SF_IRQ_06,
+	GPIO_FN_IRQ48,
+
+	/* Port115 */
+	GPIO_FN_KEYIN11,
+	GPIO_FN_KEYOUT11,
+	GPIO_FN_SF_IRQ_07,
+	GPIO_FN_IRQ49,
+
+	/* Port116 */
+	GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_CSCIF0_TX,
+
+	/* Port117 */
+	GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_CSCIF0_RX,
+
+	/* Port118 */
+	GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_CSCIF1_TX,
+
+	/* Port119 */
+	GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_CSCIF1_RX,
+
+	/* Port120 */
+	GPIO_FN_SF_PORT_1_120,
+	GPIO_FN_SCIFB3_RXD_120,
+	GPIO_FN_DU0_CDE,
+
+	/* Port121 */
+	GPIO_FN_SF_PORT_0_121,
+	GPIO_FN_SCIFB3_TXD_121,
+
+	/* Port122 */
+	GPIO_FN_SCIFB0_TXD,
+	GPIO_FN_CHSCIF0_HTX,
+
+	/* Port123 */
+	GPIO_FN_SCIFB0_RXD,
+	GPIO_FN_CHSCIF0_HRX,
+
+	/* Port124 */
+	GPIO_FN_ISP_STROBE_124,
+
+	/* Port125 */
+	GPIO_FN_STP_ISD_0,
+	GPIO_FN_PDM4_CLK_125,
+	GPIO_FN_MSIOF2_TXD,
+	GPIO_FN_SIM0_VOLTSEL0,
+
+	/* Port126 */
+	GPIO_FN_TS_SDEN,
+	GPIO_FN_MSIOF7_SYNC,
+	GPIO_FN_STP_ISEN_1,
+
+	/* Port128 */
+	GPIO_FN_STP_ISEN_0,
+	GPIO_FN_PDM1_OUTDATA_128,
+	GPIO_FN_MSIOF2_SYNC,
+	GPIO_FN_SIM1_VOLTSEL1,
+
+	/* Port129 */
+	GPIO_FN_TS_SPSYNC,
+	GPIO_FN_MSIOF7_RXD,
+	GPIO_FN_STP_ISSYNC_1,
+
+	/* Port130 */
+	GPIO_FN_STP_ISSYNC_0,
+	GPIO_FN_PDM4_DATA_130,
+	GPIO_FN_MSIOF2_RXD,
+	GPIO_FN_SIM0_VOLTSEL1,
+
+	/* Port131 */
+	GPIO_FN_STP_OPWM_0,
+	GPIO_FN_SIM1_PWRON,
+
+	/* Port132 */
+	GPIO_FN_TS_SCK,
+	GPIO_FN_MSIOF7_SCK,
+	GPIO_FN_STP_ISCLK_1,
+
+	/* Port133 */
+	GPIO_FN_STP_ISCLK_0,
+	GPIO_FN_PDM1_OUTCLK_133,
+	GPIO_FN_MSIOF2_SCK,
+	GPIO_FN_SIM1_VOLTSEL0,
+
+	/* Port134 */
+	GPIO_FN_TS_SDAT,
+	GPIO_FN_MSIOF7_TXD,
+	GPIO_FN_STP_ISD_1,
+
+	/* Port160 - Port178 */
+	GPIO_FN_IRQ20,
+	GPIO_FN_IRQ21,
+	GPIO_FN_IRQ22,
+	GPIO_FN_IRQ23,
+	GPIO_FN_MMCD0_0,
+	GPIO_FN_MMCD0_1,
+	GPIO_FN_MMCD0_2,
+	GPIO_FN_MMCD0_3,
+	GPIO_FN_MMCD0_4,
+	GPIO_FN_MMCD0_5,
+	GPIO_FN_MMCD0_6,
+	GPIO_FN_MMCD0_7,
+	GPIO_FN_MMCCMD0,
+	GPIO_FN_MMCCLK0,
+	GPIO_FN_MMCRST,
+	GPIO_FN_IRQ24,
+	GPIO_FN_IRQ25,
+	GPIO_FN_IRQ26,
+	GPIO_FN_IRQ27,
+
+	/* Port192 - Port200 FN1 */
+	GPIO_FN_A10,
+	GPIO_FN_A9,
+	GPIO_FN_A8,
+	GPIO_FN_A7,
+	GPIO_FN_A6,
+	GPIO_FN_A5,
+	GPIO_FN_A4,
+	GPIO_FN_A3,
+	GPIO_FN_A2,
+
+	/* Port192 - Port200 FN2 */
+	GPIO_FN_MMCD1_7,
+	GPIO_FN_MMCD1_6,
+	GPIO_FN_MMCD1_5,
+	GPIO_FN_MMCD1_4,
+	GPIO_FN_MMCD1_3,
+	GPIO_FN_MMCD1_2,
+	GPIO_FN_MMCD1_1,
+	GPIO_FN_MMCD1_0,
+	GPIO_FN_MMCCMD1,
+
+	/* Port192 - Port200 IRQ */
+	GPIO_FN_IRQ31,
+	GPIO_FN_IRQ32,
+	GPIO_FN_IRQ33,
+	GPIO_FN_IRQ34,
+	GPIO_FN_IRQ35,
+	GPIO_FN_IRQ36,
+	GPIO_FN_IRQ37,
+	GPIO_FN_IRQ38,
+	GPIO_FN_IRQ39,
+
+	/* Port201 */
+	GPIO_FN_A1,
+
+	/* Port202 */
+	GPIO_FN_A0,
+	GPIO_FN_BS,
+
+	/* Port203 */
+	GPIO_FN_CKO,
+	GPIO_FN_MMCCLK1,
+
+	/* Port204 */
+	GPIO_FN_CS0_N,
+	GPIO_FN_SIM0_GPO1,
+
+	/* Port205 */
+	GPIO_FN_CS2_N,
+	GPIO_FN_SIM0_GPO2,
+
+	/* Port206 */
+	GPIO_FN_CS4_N,
+	GPIO_FN_VIO_VD,
+	GPIO_FN_SIM1_GPO0,
+
+	/* Port207 - Port212 FN1 */
+	GPIO_FN_D15,
+	GPIO_FN_D14,
+	GPIO_FN_D13,
+	GPIO_FN_D12,
+	GPIO_FN_D11,
+	GPIO_FN_D10,
+
+	/* Port207 - Port212 FN5 */
+	GPIO_FN_GIO_OUT15,
+	GPIO_FN_GIO_OUT14,
+	GPIO_FN_GIO_OUT13,
+	GPIO_FN_GIO_OUT12,
+	GPIO_FN_WGM_TXP2,
+	GPIO_FN_WGM_GPS_TIMEM_ASK_RFCLK,
+
+	/* Port213 - Port222 FN1 */
+	GPIO_FN_D9,
+	GPIO_FN_D8,
+	GPIO_FN_D7,
+	GPIO_FN_D6,
+	GPIO_FN_D5,
+	GPIO_FN_D4,
+	GPIO_FN_D3,
+	GPIO_FN_D2,
+	GPIO_FN_D1,
+	GPIO_FN_D0,
+
+	/* Port213 - Port222 FN2 */
+	GPIO_FN_VIO_D9,
+	GPIO_FN_VIO_D8,
+	GPIO_FN_VIO_D7,
+	GPIO_FN_VIO_D6,
+	GPIO_FN_VIO_D5,
+	GPIO_FN_VIO_D4,
+	GPIO_FN_VIO_D3,
+	GPIO_FN_VIO_D2,
+	GPIO_FN_VIO_D1,
+	GPIO_FN_VIO_D0,
+
+	/* Port213 - Port222 FN5 */
+	GPIO_FN_GIO_OUT9,
+	GPIO_FN_GIO_OUT8,
+	GPIO_FN_GIO_OUT7,
+	GPIO_FN_GIO_OUT6,
+	GPIO_FN_GIO_OUT5_217,
+	GPIO_FN_GIO_OUT4_218,
+	GPIO_FN_GIO_OUT3_219,
+	GPIO_FN_GIO_OUT2_220,
+	GPIO_FN_GIO_OUT1_221,
+	GPIO_FN_GIO_OUT0_222,
+
+	/* Port224 */
+	GPIO_FN_RDWR_224,
+	GPIO_FN_VIO_HD,
+	GPIO_FN_SIM1_GPO2,
+
+	/* Port225 */
+	GPIO_FN_RD_N,
+
+	/* Port226 */
+	GPIO_FN_WAIT_N,
+	GPIO_FN_VIO_CLK,
+	GPIO_FN_SIM1_GPO1,
+
+	/* Port227 */
+	GPIO_FN_WE0_N,
+	GPIO_FN_RDWR_227,
+
+	/* Port228 */
+	GPIO_FN_WE1_N,
+	GPIO_FN_SIM0_GPO0,
+
+	/* Port229 */
+	GPIO_FN_PWMO,
+	GPIO_FN_VIO_CKO1_229,
+
+	/* Port230 */
+	GPIO_FN_SLIM_CLK,
+	GPIO_FN_VIO_CKO4_230,
+
+	/* Port231 */
+	GPIO_FN_SLIM_DATA,
+	GPIO_FN_VIO_CKO5_231,
+
+	/* Port232 */
+	GPIO_FN_VIO_CKO2_232,
+	GPIO_FN_SF_PORT_0_232,
+
+	/* Port233 */
+	GPIO_FN_VIO_CKO3_233,
+	GPIO_FN_SF_PORT_1_233,
+
+	/* Port234 */
+	GPIO_FN_FSIACK,
+	GPIO_FN_PDM3_CLK_234,
+	GPIO_FN_ISP_IRIS1_234,
+
+	/* Port235 */
+	GPIO_FN_FSIAISLD,
+	GPIO_FN_PDM3_DATA_235,
+
+	/* Port236 */
+	GPIO_FN_FSIAOMC,
+	GPIO_FN_PDM0_OUTCLK_236,
+	GPIO_FN_ISP_IRIS0_236,
+
+	/* Port237 */
+	GPIO_FN_FSIAOLR,
+	GPIO_FN_FSIAILR,
+
+	/* Port238 */
+	GPIO_FN_FSIAOBT,
+	GPIO_FN_FSIAIBT,
+
+	/* Port239 */
+	GPIO_FN_FSIAOSLD,
+	GPIO_FN_PDM0_OUTDATA_239,
+
+	/* Port240 */
+	GPIO_FN_FSIBISLD,
+
+	/* Port241 */
+	GPIO_FN_FSIBOLR,
+	GPIO_FN_FSIBILR,
+
+	/* Port242 */
+	GPIO_FN_FSIBOMC,
+	GPIO_FN_ISP_SHUTTER1_242,
+
+	/* Port243 */
+	GPIO_FN_FSIBOBT,
+	GPIO_FN_FSIBIBT,
+
+	/* Port244 */
+	GPIO_FN_FSIBOSLD,
+	GPIO_FN_FSIASPDIF,
+
+	/* Port245 */
+	GPIO_FN_FSIBCK,
+	GPIO_FN_ISP_SHUTTER0_245,
+
+	/* Port246 - Port250 FN1 */
+	GPIO_FN_ISP_IRIS1_246,
+	GPIO_FN_ISP_IRIS0_247,
+	GPIO_FN_ISP_SHUTTER1_248,
+	GPIO_FN_ISP_SHUTTER0_249,
+	GPIO_FN_ISP_STROBE_250,
+
+	/* Port256 - Port258 */
+	GPIO_FN_MSIOF0_SYNC,
+	GPIO_FN_MSIOF0_RXD,
+	GPIO_FN_MSIOF0_SCK,
+
+	/* Port259 */
+	GPIO_FN_MSIOF0_SS2,
+	GPIO_FN_VIO_CKO3_259,
+
+	/* Port260 */
+	GPIO_FN_MSIOF0_TXD,
+
+	/* Port261 */
+	GPIO_FN_SCIFB1_SCK_261,
+	GPIO_FN_CHSCIF1_HSCK,
+
+	/* Port262 */
+	GPIO_FN_SCIFB2_SCK_262,
+
+	/* Port263 - Port266 FN1 */
+	GPIO_FN_MSIOF1_SS2,
+	GPIO_FN_MSIOF1_TXD,
+	GPIO_FN_MSIOF1_RXD,
+	GPIO_FN_MSIOF1_SS1,
+
+	/* Port263 - Port266 FN4 */
+	GPIO_FN_MSIOF5_SS2,
+	GPIO_FN_MSIOF5_TXD,
+	GPIO_FN_MSIOF5_RXD,
+	GPIO_FN_MSIOF5_SS1,
+
+	/* Port267 */
+	GPIO_FN_MSIOF0_SS1,
+
+	/* Port268 */
+	GPIO_FN_MSIOF1_SCK,
+	GPIO_FN_MSIOF5_SCK,
+
+	/* Port269 */
+	GPIO_FN_MSIOF1_SYNC,
+	GPIO_FN_MSIOF5_SYNC,
+
+	/* Port270 - Port273 FN1 */
+	GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_MSIOF2_SS2,
+	GPIO_FN_MSIOF3_SS2,
+	GPIO_FN_MSIOF3_SS1,
+
+	/* Port270 - Port273 FN3 */
+	GPIO_FN_VIO_CKO5_270,
+	GPIO_FN_VIO_CKO2_271,
+	GPIO_FN_VIO_CKO1_272,
+	GPIO_FN_VIO_CKO4_273,
+
+	/* Port274 */
+	GPIO_FN_MSIOF4_SS2,
+	GPIO_FN_TPU1TO0,
+
+	/* Port275 - Port280 */
+	GPIO_FN_IC_DP,
+	GPIO_FN_SIM0_RST,
+	GPIO_FN_IC_DM,
+	GPIO_FN_SIM0_BSICOMP,
+	GPIO_FN_SIM0_CLK,
+	GPIO_FN_SIM0_IO,
+
+	/* Port281 */
+	GPIO_FN_SIM1_IO,
+	GPIO_FN_PDM2_DATA_281,
+
+	/* Port282 */
+	GPIO_FN_SIM1_CLK,
+	GPIO_FN_PDM2_CLK_282,
+
+	/* Port283 */
+	GPIO_FN_SIM1_RST,
+
+	/* Port289 */
+	GPIO_FN_SDHID1_0,
+	GPIO_FN_STMDATA0_2,
+
+	/* Port290 */
+	GPIO_FN_SDHID1_1,
+	GPIO_FN_STMDATA1_2,
+	GPIO_FN_IRQ51,
+
+	/* Port291 - Port294 FN1 */
+	GPIO_FN_SDHID1_2,
+	GPIO_FN_SDHID1_3,
+	GPIO_FN_SDHICLK1,
+	GPIO_FN_SDHICMD1,
+
+	/* Port291 - Port294 FN3 */
+	GPIO_FN_STMDATA2_2,
+	GPIO_FN_STMDATA3_2,
+	GPIO_FN_STMCLK_2,
+	GPIO_FN_STMSIDI_2,
+
+	/* Port295 */
+	GPIO_FN_SDHID2_0,
+	GPIO_FN_MSIOF4_TXD,
+	GPIO_FN_SCIFB2_TXD_295,
+	GPIO_FN_MSIOF6_TXD,
+
+	/* Port296 */
+	GPIO_FN_SDHID2_1,
+	GPIO_FN_MSIOF6_SS2,
+	GPIO_FN_IRQ52,
+
+	/* Port297 - Port300 FN1 */
+	GPIO_FN_SDHID2_2,
+	GPIO_FN_SDHID2_3,
+	GPIO_FN_SDHICLK2,
+	GPIO_FN_SDHICMD2,
+
+	/* Port297 - Port300 FN2 */
+	GPIO_FN_MSIOF4_RXD,
+	GPIO_FN_MSIOF4_SYNC,
+	GPIO_FN_MSIOF4_SCK,
+	GPIO_FN_MSIOF4_SS1,
+
+	/* Port297 - Port300 FN3 */
+	GPIO_FN_SCIFB2_RXD_297,
+	GPIO_FN_SCIFB2_CTS_298,
+	GPIO_FN_SCIFB2_SCK_299,
+	GPIO_FN_SCIFB2_RTS_300,
+
+	/* Port297 - Port300 FN4 */
+	GPIO_FN_MSIOF6_RXD,
+	GPIO_FN_MSIOF6_SYNC,
+	GPIO_FN_MSIOF6_SCK,
+	GPIO_FN_MSIOF6_SS1,
+
+	/* Port301 */
+	GPIO_FN_SDHICD0,
+	GPIO_FN_IRQ50,
+
+	/* Port302 - Port306 FN1 */
+	GPIO_FN_SDHID0_0,
+	GPIO_FN_SDHID0_1,
+	GPIO_FN_SDHID0_2,
+	GPIO_FN_SDHID0_3,
+	GPIO_FN_SDHICMD0,
+
+	/* Port302 - Port306 FN3 */
+	GPIO_FN_STMDATA0_1,
+	GPIO_FN_STMDATA1_1,
+	GPIO_FN_STMDATA2_1,
+	GPIO_FN_STMDATA3_1,
+	GPIO_FN_STMSIDI_1,
+
+	/* Port307 */
+	GPIO_FN_SDHIWP0,
+
+	/* Port308 */
+	GPIO_FN_SDHICLK0,
+	GPIO_FN_STMCLK_1,
+
+	/* Port320 - Port329 */
+	GPIO_FN_IRQ16,
+	GPIO_FN_IRQ17,
+	GPIO_FN_IRQ28,
+	GPIO_FN_IRQ29,
+	GPIO_FN_IRQ30,
+	GPIO_FN_IRQ53,
+	GPIO_FN_IRQ54,
+	GPIO_FN_IRQ55,
+	GPIO_FN_IRQ56,
+	GPIO_FN_IRQ57,
+};
+
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index af16f8f..0e1f99c 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -22,6 +22,11 @@ config GPIO_SH_PFC
 	  This enables support for GPIOs within the SoC's pin function
 	  controller.
 
+config PINCTRL_PFC_R8A73A4
+	def_bool y
+	depends on ARCH_R8A73A4
+	select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7740
 	def_bool y
 	depends on ARCH_R8A7740
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index e8b9562..211cd8e 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
 sh-pfc-objs			+= gpio.o
 endif
 obj-$(CONFIG_PINCTRL_SH_PFC)	+= sh-pfc.o
+obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)	+= pfc-r8a7779.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index ced9a95..b551336 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -418,6 +418,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 }
 
 static const struct platform_device_id sh_pfc_id_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A73A4
+	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 763d717..89cb428 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -54,6 +54,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
+extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
new file mode 100644
index 0000000..47d75d5
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -0,0 +1,2826 @@
+/*
+ * Copyright (C) 2012-2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <mach/irqs.h>
+#include <mach/r8a73a4.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, pfx, sfx)					\
+	/*  Port0 - Port30 */						\
+	PORT_10(fn, pfx, sfx),						\
+	PORT_10(fn, pfx##1, sfx),					\
+	PORT_10(fn, pfx##2, sfx),					\
+	PORT_1(fn,  pfx##30, sfx),					\
+	/* Port32 - Port40 */						\
+	PORT_1(fn,  pfx##32, sfx),	PORT_1(fn,  pfx##33, sfx),	\
+	PORT_1(fn,  pfx##34, sfx),	PORT_1(fn,  pfx##35, sfx),	\
+	PORT_1(fn,  pfx##36, sfx),	PORT_1(fn,  pfx##37, sfx),	\
+	PORT_1(fn,  pfx##38, sfx),	PORT_1(fn,  pfx##39, sfx),	\
+	PORT_1(fn,  pfx##40, sfx),					\
+	/* Port64  - Port85 */						\
+	PORT_1(fn, pfx##64, sfx),	PORT_1(fn, pfx##65, sfx),	\
+	PORT_1(fn, pfx##66, sfx),	PORT_1(fn, pfx##67, sfx),	\
+	PORT_1(fn, pfx##68, sfx),	PORT_1(fn, pfx##69, sfx),	\
+	PORT_10(fn, pfx##7, sfx),					\
+	PORT_1(fn, pfx##80, sfx),	PORT_1(fn, pfx##81, sfx),	\
+	PORT_1(fn, pfx##82, sfx),	PORT_1(fn, pfx##83, sfx),	\
+	PORT_1(fn, pfx##84, sfx),	PORT_1(fn, pfx##85, sfx),	\
+	/* Port96  - Port126 */						\
+	PORT_1(fn, pfx##96, sfx),	PORT_1(fn, pfx##97, sfx),	\
+	PORT_1(fn, pfx##98, sfx),	PORT_1(fn, pfx##99, sfx),	\
+	PORT_10(fn, pfx##10, sfx),					\
+	PORT_10(fn, pfx##11, sfx),					\
+	PORT_1(fn, pfx##120, sfx),	PORT_1(fn, pfx##121, sfx),	\
+	PORT_1(fn, pfx##122, sfx),	PORT_1(fn, pfx##123, sfx),	\
+	PORT_1(fn, pfx##124, sfx),	PORT_1(fn, pfx##125, sfx),	\
+	PORT_1(fn, pfx##126, sfx),					\
+	/* Port128 - Port134 */						\
+	PORT_1(fn, pfx##128, sfx),	PORT_1(fn, pfx##129, sfx),	\
+	PORT_1(fn, pfx##130, sfx),	PORT_1(fn, pfx##131, sfx),	\
+	PORT_1(fn, pfx##132, sfx),	PORT_1(fn, pfx##133, sfx),	\
+	PORT_1(fn, pfx##134, sfx),					\
+	/* Port160 - Port178 */						\
+	PORT_10(fn, pfx##16, sfx),					\
+	PORT_1(fn, pfx##170, sfx),	PORT_1(fn, pfx##171, sfx),	\
+	PORT_1(fn, pfx##172, sfx),	PORT_1(fn, pfx##173, sfx),	\
+	PORT_1(fn, pfx##174, sfx),	PORT_1(fn, pfx##175, sfx),	\
+	PORT_1(fn, pfx##176, sfx),	PORT_1(fn, pfx##177, sfx),	\
+	PORT_1(fn, pfx##178, sfx),					\
+	/* Port192 - Port222 */						\
+	PORT_1(fn, pfx##192, sfx),	PORT_1(fn, pfx##193, sfx),	\
+	PORT_1(fn, pfx##194, sfx),	PORT_1(fn, pfx##195, sfx),	\
+	PORT_1(fn, pfx##196, sfx),	PORT_1(fn, pfx##197, sfx),	\
+	PORT_1(fn, pfx##198, sfx),	PORT_1(fn, pfx##199, sfx),	\
+	PORT_10(fn, pfx##20, sfx),					\
+	PORT_10(fn, pfx##21, sfx),					\
+	PORT_1(fn, pfx##220, sfx),	PORT_1(fn, pfx##221, sfx),	\
+	PORT_1(fn, pfx##222, sfx),					\
+	/* Port224 - Port250 */						\
+	PORT_1(fn, pfx##224, sfx),	PORT_1(fn, pfx##225, sfx),	\
+	PORT_1(fn, pfx##226, sfx),	PORT_1(fn, pfx##227, sfx),	\
+	PORT_1(fn, pfx##228, sfx),	PORT_1(fn, pfx##229, sfx),	\
+	PORT_10(fn, pfx##23, sfx),					\
+	PORT_10(fn, pfx##24, sfx),					\
+	PORT_1(fn, pfx##250, sfx),					\
+	/* Port256 - Port283 */						\
+	PORT_1(fn, pfx##256, sfx),	PORT_1(fn, pfx##257, sfx),	\
+	PORT_1(fn, pfx##258, sfx),	PORT_1(fn, pfx##259, sfx),	\
+	PORT_10(fn, pfx##26, sfx),					\
+	PORT_10(fn, pfx##27, sfx),					\
+	PORT_1(fn, pfx##280, sfx),	PORT_1(fn, pfx##281, sfx),	\
+	PORT_1(fn, pfx##282, sfx),	PORT_1(fn, pfx##283, sfx),	\
+	/* Port288 - Port308 */						\
+	PORT_1(fn, pfx##288, sfx),	PORT_1(fn, pfx##289, sfx),	\
+	PORT_10(fn, pfx##29, sfx),					\
+	PORT_1(fn, pfx##300, sfx),	PORT_1(fn, pfx##301, sfx),	\
+	PORT_1(fn, pfx##302, sfx),	PORT_1(fn, pfx##303, sfx),	\
+	PORT_1(fn, pfx##304, sfx),	PORT_1(fn, pfx##305, sfx),	\
+	PORT_1(fn, pfx##306, sfx),	PORT_1(fn, pfx##307, sfx),	\
+	PORT_1(fn, pfx##308, sfx),					\
+	/* Port320 - Port329 */						\
+	PORT_10(fn, pfx##32, sfx)
+
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	/* PORT0_DATA -> PORT329_DATA */
+	PINMUX_DATA_BEGIN,
+	PORT_ALL(DATA),
+	PINMUX_DATA_END,
+
+	/* PORT0_IN -> PORT329_IN */
+	PINMUX_INPUT_BEGIN,
+	PORT_ALL(IN),
+	PINMUX_INPUT_END,
+
+	/* PORT0_IN_PU -> PORT329_IN_PU */
+	PINMUX_INPUT_PULLUP_BEGIN,
+	PORT_ALL(IN_PU),
+	PINMUX_INPUT_PULLUP_END,
+
+	/* PORT0_IN_PD -> PORT329_IN_PD */
+	PINMUX_INPUT_PULLDOWN_BEGIN,
+	PORT_ALL(IN_PD),
+	PINMUX_INPUT_PULLDOWN_END,
+
+	/* PORT0_OUT -> PORT329_OUT */
+	PINMUX_OUTPUT_BEGIN,
+	PORT_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
+	PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
+	PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
+	PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
+	PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
+	PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
+	PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
+	PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
+	PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
+	PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
+
+	MSEL1CR_31_0, MSEL1CR_31_1,
+	MSEL1CR_27_0, MSEL1CR_27_1,
+	MSEL1CR_25_0, MSEL1CR_25_1,
+	MSEL1CR_24_0, MSEL1CR_24_1,
+	MSEL1CR_22_0, MSEL1CR_22_1,
+	MSEL1CR_21_0, MSEL1CR_21_1,
+	MSEL1CR_20_0, MSEL1CR_20_1,
+	MSEL1CR_19_0, MSEL1CR_19_1,
+	MSEL1CR_18_0, MSEL1CR_18_1,
+	MSEL1CR_17_0, MSEL1CR_17_1,
+	MSEL1CR_16_0, MSEL1CR_16_1,
+	MSEL1CR_15_0, MSEL1CR_15_1,
+	MSEL1CR_14_0, MSEL1CR_14_1,
+	MSEL1CR_13_0, MSEL1CR_13_1,
+	MSEL1CR_12_0, MSEL1CR_12_1,
+	MSEL1CR_11_0, MSEL1CR_11_1,
+	MSEL1CR_10_0, MSEL1CR_10_1,
+	MSEL1CR_09_0, MSEL1CR_09_1,
+	MSEL1CR_08_0, MSEL1CR_08_1,
+	MSEL1CR_07_0, MSEL1CR_07_1,
+	MSEL1CR_06_0, MSEL1CR_06_1,
+	MSEL1CR_05_0, MSEL1CR_05_1,
+	MSEL1CR_04_0, MSEL1CR_04_1,
+	MSEL1CR_03_0, MSEL1CR_03_1,
+	MSEL1CR_02_0, MSEL1CR_02_1,
+	MSEL1CR_01_0, MSEL1CR_01_1,
+	MSEL1CR_00_0, MSEL1CR_00_1,
+
+	MSEL3CR_31_0, MSEL3CR_31_1,
+	MSEL3CR_28_0, MSEL3CR_28_1,
+	MSEL3CR_27_0, MSEL3CR_27_1,
+	MSEL3CR_26_0, MSEL3CR_26_1,
+	MSEL3CR_23_0, MSEL3CR_23_1,
+	MSEL3CR_22_0, MSEL3CR_22_1,
+	MSEL3CR_21_0, MSEL3CR_21_1,
+	MSEL3CR_20_0, MSEL3CR_20_1,
+	MSEL3CR_19_0, MSEL3CR_19_1,
+	MSEL3CR_18_0, MSEL3CR_18_1,
+	MSEL3CR_17_0, MSEL3CR_17_1,
+	MSEL3CR_16_0, MSEL3CR_16_1,
+	MSEL3CR_15_0, MSEL3CR_15_1,
+	MSEL3CR_12_0, MSEL3CR_12_1,
+	MSEL3CR_11_0, MSEL3CR_11_1,
+	MSEL3CR_10_0, MSEL3CR_10_1,
+	MSEL3CR_09_0, MSEL3CR_09_1,
+	MSEL3CR_06_0, MSEL3CR_06_1,
+	MSEL3CR_03_0, MSEL3CR_03_1,
+	MSEL3CR_01_0, MSEL3CR_01_1,
+	MSEL3CR_00_0, MSEL3CR_00_1,
+
+	MSEL4CR_30_0, MSEL4CR_30_1,
+	MSEL4CR_29_0, MSEL4CR_29_1,
+	MSEL4CR_28_0, MSEL4CR_28_1,
+	MSEL4CR_27_0, MSEL4CR_27_1,
+	MSEL4CR_26_0, MSEL4CR_26_1,
+	MSEL4CR_25_0, MSEL4CR_25_1,
+	MSEL4CR_24_0, MSEL4CR_24_1,
+	MSEL4CR_23_0, MSEL4CR_23_1,
+	MSEL4CR_22_0, MSEL4CR_22_1,
+	MSEL4CR_21_0, MSEL4CR_21_1,
+	MSEL4CR_20_0, MSEL4CR_20_1,
+	MSEL4CR_19_0, MSEL4CR_19_1,
+	MSEL4CR_18_0, MSEL4CR_18_1,
+	MSEL4CR_17_0, MSEL4CR_17_1,
+	MSEL4CR_16_0, MSEL4CR_16_1,
+	MSEL4CR_15_0, MSEL4CR_15_1,
+	MSEL4CR_14_0, MSEL4CR_14_1,
+	MSEL4CR_13_0, MSEL4CR_13_1,
+	MSEL4CR_12_0, MSEL4CR_12_1,
+	MSEL4CR_11_0, MSEL4CR_11_1,
+	MSEL4CR_10_0, MSEL4CR_10_1,
+	MSEL4CR_09_0, MSEL4CR_09_1,
+	MSEL4CR_07_0, MSEL4CR_07_1,
+	MSEL4CR_04_0, MSEL4CR_04_1,
+	MSEL4CR_01_0, MSEL4CR_01_1,
+
+	MSEL5CR_31_0, MSEL5CR_31_1,
+	MSEL5CR_30_0, MSEL5CR_30_1,
+	MSEL5CR_29_0, MSEL5CR_29_1,
+	MSEL5CR_28_0, MSEL5CR_28_1,
+	MSEL5CR_27_0, MSEL5CR_27_1,
+	MSEL5CR_26_0, MSEL5CR_26_1,
+	MSEL5CR_25_0, MSEL5CR_25_1,
+	MSEL5CR_24_0, MSEL5CR_24_1,
+	MSEL5CR_23_0, MSEL5CR_23_1,
+	MSEL5CR_22_0, MSEL5CR_22_1,
+	MSEL5CR_21_0, MSEL5CR_21_1,
+	MSEL5CR_20_0, MSEL5CR_20_1,
+	MSEL5CR_19_0, MSEL5CR_19_1,
+	MSEL5CR_18_0, MSEL5CR_18_1,
+	MSEL5CR_17_0, MSEL5CR_17_1,
+	MSEL5CR_16_0, MSEL5CR_16_1,
+	MSEL5CR_15_0, MSEL5CR_15_1,
+	MSEL5CR_14_0, MSEL5CR_14_1,
+	MSEL5CR_13_0, MSEL5CR_13_1,
+	MSEL5CR_12_0, MSEL5CR_12_1,
+	MSEL5CR_11_0, MSEL5CR_11_1,
+	MSEL5CR_10_0, MSEL5CR_10_1,
+	MSEL5CR_09_0, MSEL5CR_09_1,
+	MSEL5CR_08_0, MSEL5CR_08_1,
+	MSEL5CR_07_0, MSEL5CR_07_1,
+	MSEL5CR_06_0, MSEL5CR_06_1,
+
+	MSEL8CR_16_0, MSEL8CR_16_1,
+	MSEL8CR_01_0, MSEL8CR_01_1,
+	MSEL8CR_00_0, MSEL8CR_00_1,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+
+#define F1(a)	a##_MARK
+#define F2(a)	a##_MARK
+#define F3(a)	a##_MARK
+#define F4(a)	a##_MARK
+#define F5(a)	a##_MARK
+#define F6(a)	a##_MARK
+#define F7(a)	a##_MARK
+#define IRQ(a)	IRQ##a##_MARK
+
+	F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
+	F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
+	F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
+	F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
+	F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
+	F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
+	F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
+	F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
+	F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
+	F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
+	F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
+	F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
+	F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
+	F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
+	F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
+	F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
+	F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
+	F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
+	F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
+	F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
+	F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
+	F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
+	F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
+	F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
+	F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
+	F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
+	F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
+	F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
+	F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
+	F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
+	F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
+	F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
+
+	F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
+	F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
+	F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
+	F1(SCIFA1_RTS), F7(CSCIF1_RTS),
+	F1(SCIFA1_CTS), F7(CSCIF1_CTS),
+	F1(SCIFA1_SCK), F7(CSCIF1_SCK),
+	F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
+	F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
+	F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
+	F7(CHSCIF0_HSCK), /* Port40 */
+
+	F1(PDM0_DATA), /* Port64 */
+	F1(PDM1_DATA),
+	F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
+	IRQ(40),
+	F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
+	F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
+	F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
+	F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
+	F7(CHSCIF1_HRTS), /* Port70 */
+	F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
+	F7(CHSCIF1_HCTS),
+	F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
+	F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
+	F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
+	F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
+	F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
+
+	F1(KEYIN0), /* Port96 */
+	F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
+	F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
+	F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
+	F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
+	F2(KEYOUT7), F5(RFANAEN), IRQ(45),
+	F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
+	F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
+	F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
+	F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
+	F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
+	F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
+	F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
+	F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
+	F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
+	F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
+	F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
+	F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
+	F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
+	F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
+	F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
+	F5(SIM0_VOLTSEL1), /* Port130 */
+	F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
+	F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
+	F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
+	IRQ(20), /* Port160 */
+	IRQ(21), IRQ(22), IRQ(23),
+	F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
+	F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
+	F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
+	IRQ(24), IRQ(25), IRQ(26), IRQ(27),
+	F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
+	F1(A9), F2(MMCD1_6), IRQ(32),
+	F1(A8), F2(MMCD1_5), IRQ(33),
+	F1(A7), F2(MMCD1_4), IRQ(34),
+	F1(A6), F2(MMCD1_3), IRQ(35),
+	F1(A5), F2(MMCD1_2), IRQ(36),
+	F1(A4), F2(MMCD1_1), IRQ(37),
+	F1(A3), F2(MMCD1_0), IRQ(38),
+	F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
+	F1(A1),
+	F1(A0), F2(BS),
+	F1(CKO), F2(MMCCLK1),
+	F1(CS0_N), F5(SIM0_GPO1),
+	F1(CS2_N), F5(SIM0_GPO2),
+	F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
+	F1(D15), F5(GIO_OUT15),
+	F1(D14), F5(GIO_OUT14),
+	F1(D13), F5(GIO_OUT13),
+	F1(D12), F5(GIO_OUT12), /* Port210 */
+	F1(D11), F5(WGM_TXP2),
+	F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
+	F1(D9), F2(VIO_D9), F5(GIO_OUT9),
+	F1(D8), F2(VIO_D8), F5(GIO_OUT8),
+	F1(D7), F2(VIO_D7), F5(GIO_OUT7),
+	F1(D6), F2(VIO_D6), F5(GIO_OUT6),
+	F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
+	F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
+	F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
+	F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
+	F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
+	F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
+	F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
+	F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
+	F1(WE0_N), F2(RDWR_227),
+	F1(WE1_N), F5(SIM0_GPO0),
+	F1(PWMO), F2(VIO_CKO1_229),
+	F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
+	F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
+	F2(VIO_CKO3_233), F4(SF_PORT_1_233),
+	F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
+	F1(FSIAISLD), F2(PDM3_DATA_235),
+	F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
+	F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
+	F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
+	F1(FSIBISLD), /* Port240 */
+	F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
+	F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
+	F1(FSIBCK), F3(ISP_SHUTTER0_245),
+	F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
+	F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
+	F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
+	F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
+	F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
+	F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
+	F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
+	F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
+	F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
+	F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
+	F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
+	F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
+	F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
+	F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
+	F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
+	F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
+	F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
+	F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
+	F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
+	F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
+	F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
+	F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
+	F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
+	F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
+	F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
+	F4(MSIOF6_SS1), /* Port300 */
+	F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
+	F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
+	F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
+	F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
+	IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
+	IRQ(55), IRQ(56), IRQ(57),
+	PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+	/* specify valid pin states for each pin in GPIO mode */
+
+	PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
+	PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
+	PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
+	PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
+	PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
+
+	PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
+	PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
+	PORT_DATA_IO_PU_PD(14),	PORT_DATA_IO_PU_PD(15),
+	PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
+	PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
+
+	PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
+	PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
+	PORT_DATA_IO_PU_PD(24),	PORT_DATA_IO_PU_PD(25),
+	PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
+	PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
+
+	PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
+	PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
+	PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
+	PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
+	PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
+
+	PORT_DATA_IO_PU_PD(64),	PORT_DATA_IO_PU_PD(65),
+	PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
+	PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
+
+	PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
+	PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
+	PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
+	PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
+	PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
+
+	PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
+	PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
+	PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
+
+	PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
+	PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
+
+	PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
+	PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
+	PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
+	PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
+	PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
+
+	PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
+	PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
+	PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
+	PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
+	PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
+
+	PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
+	PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
+	PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
+	PORT_DATA_IO_PU_PD(126),
+	PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
+
+	PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
+	PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
+	PORT_DATA_IO_PU_PD(134),
+
+	PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
+	PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
+	PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
+	PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
+	PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
+
+	PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
+	PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
+	PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
+	PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
+	PORT_DATA_IO_PU_PD(178),
+
+	PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
+	PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
+	PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
+	PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
+
+	PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
+	PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
+	PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
+	PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
+	PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
+
+	PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
+	PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
+	PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
+	PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
+	PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
+
+	PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
+	PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
+	PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
+	PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
+	PORT_DATA_IO_PU_PD(229),
+
+	PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
+	PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
+	PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
+	PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
+	PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
+
+	PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
+	PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
+	PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
+	PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
+	PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
+
+	PORT_DATA_IO_PU_PD(250),
+	PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
+	PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
+
+	PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
+	PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
+	PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
+	PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
+	PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
+
+	PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
+	PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
+	PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
+	PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
+	PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
+
+	PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
+	PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
+	PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
+
+	PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
+	PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
+	PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
+	PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
+	PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
+
+	PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
+	PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
+	PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
+	PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
+	PORT_DATA_IO_PU_PD(308),
+
+	PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
+	PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
+	PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
+	PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
+	PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
+
+	/* Port0 */
+	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
+	PINMUX_DATA(PDM2_CLK_0_MARK,	PORT0_FN3),
+	PINMUX_DATA(DU0_DR0_MARK,	PORT0_FN7),
+	PINMUX_DATA(IRQ0_MARK,		PORT0_FN0),
+
+	/* Port1 */
+	PINMUX_DATA(LCDD1_MARK,		PORT1_FN1),
+	PINMUX_DATA(PDM2_DATA_1_MARK,	PORT1_FN3,	MSEL3CR_12_0),
+	PINMUX_DATA(DU0_DR19_MARK,	PORT1_FN7),
+	PINMUX_DATA(IRQ1_MARK,		PORT1_FN0),
+
+	/* Port2 */
+	PINMUX_DATA(LCDD2_MARK,		PORT2_FN1),
+	PINMUX_DATA(PDM3_CLK_2_MARK,	PORT2_FN3),
+	PINMUX_DATA(DU0_DR2_MARK,	PORT2_FN7),
+	PINMUX_DATA(IRQ2_MARK,		PORT2_FN0),
+
+	/* Port3 */
+	PINMUX_DATA(LCDD3_MARK,		PORT3_FN1),
+	PINMUX_DATA(PDM3_DATA_3_MARK,	PORT3_FN3,	MSEL3CR_12_0),
+	PINMUX_DATA(DU0_DR3_MARK,	PORT3_FN7),
+	PINMUX_DATA(IRQ3_MARK,		PORT3_FN0),
+
+	/* Port4 */
+	PINMUX_DATA(LCDD4_MARK,		PORT4_FN1),
+	PINMUX_DATA(PDM4_CLK_4_MARK,	PORT4_FN3),
+	PINMUX_DATA(DU0_DR4_MARK,	PORT4_FN7),
+	PINMUX_DATA(IRQ4_MARK,		PORT4_FN0),
+
+	/* Port5 */
+	PINMUX_DATA(LCDD5_MARK,		PORT5_FN1),
+	PINMUX_DATA(PDM4_DATA_5_MARK,	PORT5_FN3,	MSEL3CR_12_0),
+	PINMUX_DATA(DU0_DR5_MARK,	PORT5_FN7),
+	PINMUX_DATA(IRQ5_MARK,		PORT5_FN0),
+
+	/* Port6 */
+	PINMUX_DATA(LCDD6_MARK,		PORT6_FN1),
+	PINMUX_DATA(PDM0_OUTCLK_6_MARK,	PORT6_FN3),
+	PINMUX_DATA(DU0_DR6_MARK,	PORT6_FN7),
+	PINMUX_DATA(IRQ6_MARK,		PORT6_FN0),
+
+	/* Port7 */
+	PINMUX_DATA(LCDD7_MARK,			PORT7_FN1),
+	PINMUX_DATA(PDM0_OUTDATA_7_MARK,	PORT7_FN3),
+	PINMUX_DATA(DU0_DR7_MARK,		PORT7_FN7),
+	PINMUX_DATA(IRQ7_MARK,			PORT7_FN0),
+
+	/* Port8 */
+	PINMUX_DATA(LCDD8_MARK,		PORT8_FN1),
+	PINMUX_DATA(PDM1_OUTCLK_8_MARK,	PORT8_FN3),
+	PINMUX_DATA(DU0_DG0_MARK,	PORT8_FN7),
+	PINMUX_DATA(IRQ8_MARK,		PORT8_FN0),
+
+	/* Port9 */
+	PINMUX_DATA(LCDD9_MARK,		PORT9_FN1),
+	PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
+	PINMUX_DATA(DU0_DG1_MARK,	PORT9_FN7),
+	PINMUX_DATA(IRQ9_MARK,		PORT9_FN0),
+
+	/* Port10 */
+	PINMUX_DATA(LCDD10_MARK,		PORT10_FN1),
+	PINMUX_DATA(FSICCK_MARK,		PORT10_FN3),
+	PINMUX_DATA(DU0_DG2_MARK,		PORT10_FN7),
+	PINMUX_DATA(IRQ10_MARK,			PORT10_FN0),
+
+	/* Port11 */
+	PINMUX_DATA(LCDD11_MARK,		PORT11_FN1),
+	PINMUX_DATA(FSICISLD_MARK,		PORT11_FN3),
+	PINMUX_DATA(DU0_DG3_MARK,		PORT11_FN7),
+	PINMUX_DATA(IRQ11_MARK,			PORT11_FN0),
+
+	/* Port12 */
+	PINMUX_DATA(LCDD12_MARK,		PORT12_FN1),
+	PINMUX_DATA(FSICOMC_MARK,		PORT12_FN3),
+	PINMUX_DATA(DU0_DG4_MARK,		PORT12_FN7),
+	PINMUX_DATA(IRQ12_MARK,			PORT12_FN0),
+
+	/* Port13 */
+	PINMUX_DATA(LCDD13_MARK,		PORT13_FN1),
+	PINMUX_DATA(FSICOLR_MARK,		PORT13_FN3),
+	PINMUX_DATA(FSICILR_MARK,		PORT13_FN4),
+	PINMUX_DATA(DU0_DG5_MARK,		PORT13_FN7),
+	PINMUX_DATA(IRQ13_MARK,			PORT13_FN0),
+
+	/* Port14 */
+	PINMUX_DATA(LCDD14_MARK,		PORT14_FN1),
+	PINMUX_DATA(FSICOBT_MARK,		PORT14_FN3),
+	PINMUX_DATA(FSICIBT_MARK,		PORT14_FN4),
+	PINMUX_DATA(DU0_DG6_MARK,		PORT14_FN7),
+	PINMUX_DATA(IRQ14_MARK,			PORT14_FN0),
+
+	/* Port15 */
+	PINMUX_DATA(LCDD15_MARK,		PORT15_FN1),
+	PINMUX_DATA(FSICOSLD_MARK,		PORT15_FN3),
+	PINMUX_DATA(DU0_DG7_MARK,		PORT15_FN7),
+	PINMUX_DATA(IRQ15_MARK,			PORT15_FN0),
+
+	/* Port16 */
+	PINMUX_DATA(LCDD16_MARK,		PORT16_FN1),
+	PINMUX_DATA(TPU1TO1_MARK,		PORT16_FN4),
+	PINMUX_DATA(DU0_DB0_MARK,		PORT16_FN7),
+
+	/* Port17 */
+	PINMUX_DATA(LCDD17_MARK,		PORT17_FN1),
+	PINMUX_DATA(SF_IRQ_00_MARK,		PORT17_FN4),
+	PINMUX_DATA(DU0_DB1_MARK,		PORT17_FN7),
+
+	/* Port18 */
+	PINMUX_DATA(LCDD18_MARK,		PORT18_FN1),
+	PINMUX_DATA(SF_IRQ_01_MARK,		PORT18_FN4),
+	PINMUX_DATA(DU0_DB2_MARK,		PORT18_FN7),
+
+	/* Port19 */
+	PINMUX_DATA(LCDD19_MARK,		PORT19_FN1),
+	PINMUX_DATA(SCIFB3_RTS_19_MARK,		PORT19_FN3),
+	PINMUX_DATA(DU0_DB3_MARK,		PORT19_FN7),
+
+	/* Port20 */
+	PINMUX_DATA(LCDD20_MARK,		PORT20_FN1),
+	PINMUX_DATA(SCIFB3_CTS_20_MARK,		PORT20_FN3,	MSEL3CR_09_0),
+	PINMUX_DATA(DU0_DB4_MARK,		PORT20_FN7),
+
+	/* Port21 */
+	PINMUX_DATA(LCDD21_MARK,		PORT21_FN1),
+	PINMUX_DATA(SCIFB3_TXD_21_MARK,		PORT21_FN3,	MSEL3CR_09_0),
+	PINMUX_DATA(DU0_DB5_MARK,		PORT21_FN7),
+
+	/* Port22 */
+	PINMUX_DATA(LCDD22_MARK,		PORT22_FN1),
+	PINMUX_DATA(SCIFB3_RXD_22_MARK,		PORT22_FN3,	MSEL3CR_09_0),
+	PINMUX_DATA(DU0_DB6_MARK,		PORT22_FN7),
+
+	/* Port23 */
+	PINMUX_DATA(LCDD23_MARK,		PORT23_FN1),
+	PINMUX_DATA(SCIFB3_SCK_23_MARK,		PORT23_FN3),
+	PINMUX_DATA(DU0_DB7_MARK,		PORT23_FN7),
+
+	/* Port24 */
+	PINMUX_DATA(LCDHSYN_MARK,			PORT24_FN1),
+	PINMUX_DATA(LCDCS_MARK,				PORT24_FN2),
+	PINMUX_DATA(SCIFB1_RTS_24_MARK,			PORT24_FN3),
+	PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK,	PORT24_FN7),
+
+	/* Port25 */
+	PINMUX_DATA(LCDVSYN_MARK,			PORT25_FN1),
+	PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
+	PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK,	PORT25_FN7),
+
+	/* Port26 */
+	PINMUX_DATA(LCDDCK_MARK,		PORT26_FN1),
+	PINMUX_DATA(LCDWR_MARK,			PORT26_FN2),
+	PINMUX_DATA(SCIFB1_TXD_26_MARK,		PORT26_FN3,	MSEL3CR_11_0),
+	PINMUX_DATA(DU0_DOTCLKIN_MARK,		PORT26_FN7),
+
+	/* Port27 */
+	PINMUX_DATA(LCDDISP_MARK,		PORT27_FN1),
+	PINMUX_DATA(LCDRS_MARK,			PORT27_FN2),
+	PINMUX_DATA(SCIFB1_RXD_27_MARK,		PORT27_FN3,	MSEL3CR_11_0),
+	PINMUX_DATA(DU0_DOTCLKOUT_MARK,		PORT27_FN7),
+
+	/* Port28 */
+	PINMUX_DATA(LCDRD_N_MARK,		PORT28_FN1),
+	PINMUX_DATA(SCIFB1_SCK_28_MARK,		PORT28_FN3),
+	PINMUX_DATA(DU0_DOTCLKOUTB_MARK,	PORT28_FN7),
+
+	/* Port29 */
+	PINMUX_DATA(LCDLCLK_MARK,		PORT29_FN1),
+	PINMUX_DATA(SF_IRQ_02_MARK,		PORT29_FN4),
+	PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,	PORT29_FN7),
+
+	/* Port30 */
+	PINMUX_DATA(LCDDON_MARK,		PORT30_FN1),
+	PINMUX_DATA(SF_IRQ_03_MARK,		PORT30_FN4),
+	PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,	PORT30_FN7),
+
+	/* Port32 */
+	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT32_FN1),
+	PINMUX_DATA(SIM0_DET_MARK,		PORT32_FN5),
+	PINMUX_DATA(CSCIF0_RTS_MARK,		PORT32_FN7),
+
+	/* Port33 */
+	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT33_FN1),
+	PINMUX_DATA(SIM1_DET_MARK,		PORT33_FN5),
+	PINMUX_DATA(CSCIF0_CTS_MARK,		PORT33_FN7),
+
+	/* Port34 */
+	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT34_FN1),
+	PINMUX_DATA(SIM0_PWRON_MARK,		PORT34_FN5),
+	PINMUX_DATA(CSCIF0_SCK_MARK,		PORT34_FN7),
+
+	/* Port35 */
+	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT35_FN1),
+	PINMUX_DATA(CSCIF1_RTS_MARK,		PORT35_FN7),
+
+	/* Port36 */
+	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT36_FN1),
+	PINMUX_DATA(CSCIF1_CTS_MARK,		PORT36_FN7),
+
+	/* Port37 */
+	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT37_FN1),
+	PINMUX_DATA(CSCIF1_SCK_MARK,		PORT37_FN7),
+
+	/* Port38 */
+	PINMUX_DATA(SCIFB0_RTS_MARK,		PORT38_FN1),
+	PINMUX_DATA(TPU0TO1_MARK,		PORT38_FN3),
+	PINMUX_DATA(SCIFB3_RTS_38_MARK,		PORT38_FN4),
+	PINMUX_DATA(CHSCIF0_HRTS_MARK,		PORT38_FN7),
+
+	/* Port39 */
+	PINMUX_DATA(SCIFB0_CTS_MARK,		PORT39_FN1),
+	PINMUX_DATA(TPU0TO2_MARK,		PORT39_FN3),
+	PINMUX_DATA(SCIFB3_CTS_39_MARK,		PORT39_FN4,	MSEL3CR_09_1),
+	PINMUX_DATA(CHSCIF0_HCTS_MARK,		PORT39_FN7),
+
+	/* Port40 */
+	PINMUX_DATA(SCIFB0_SCK_MARK,		PORT40_FN1),
+	PINMUX_DATA(TPU0TO3_MARK,		PORT40_FN3),
+	PINMUX_DATA(SCIFB3_SCK_40_MARK,		PORT40_FN4),
+	PINMUX_DATA(CHSCIF0_HSCK_MARK,		PORT40_FN7),
+
+	/* Port64 */
+	PINMUX_DATA(PDM0_DATA_MARK,		PORT64_FN1),
+
+	/* Port65 */
+	PINMUX_DATA(PDM1_DATA_MARK,		PORT65_FN1),
+
+	/* Port66 */
+	PINMUX_DATA(HSI_RX_WAKE_MARK,		PORT66_FN1),
+	PINMUX_DATA(SCIFB2_CTS_66_MARK,		PORT66_FN2,	MSEL3CR_10_0),
+	PINMUX_DATA(MSIOF3_SYNC_MARK,		PORT66_FN3),
+	PINMUX_DATA(GenIO4_MARK,		PORT66_FN5),
+	PINMUX_DATA(IRQ40_MARK,			PORT66_FN0),
+
+	/* Port67 */
+	PINMUX_DATA(HSI_RX_READY_MARK,		PORT67_FN1),
+	PINMUX_DATA(SCIFB1_TXD_67_MARK,		PORT67_FN2,	MSEL3CR_11_1),
+	PINMUX_DATA(GIO_OUT3_67_MARK,		PORT67_FN5),
+	PINMUX_DATA(CHSCIF1_HTX_MARK,		PORT67_FN7),
+
+	/* Port68 */
+	PINMUX_DATA(HSI_RX_FLAG_MARK,		PORT68_FN1),
+	PINMUX_DATA(SCIFB2_TXD_68_MARK,		PORT68_FN2,	MSEL3CR_10_0),
+	PINMUX_DATA(MSIOF3_TXD_MARK,		PORT68_FN3),
+	PINMUX_DATA(GIO_OUT4_68_MARK,		PORT68_FN5),
+
+	/* Port69 */
+	PINMUX_DATA(HSI_RX_DATA_MARK,		PORT69_FN1),
+	PINMUX_DATA(SCIFB2_RXD_69_MARK,		PORT69_FN2,	MSEL3CR_10_0),
+	PINMUX_DATA(MSIOF3_RXD_MARK,		PORT69_FN3),
+	PINMUX_DATA(GIO_OUT5_69_MARK,		PORT69_FN5),
+
+	/* Port70 */
+	PINMUX_DATA(HSI_TX_FLAG_MARK,		PORT70_FN1),
+	PINMUX_DATA(SCIFB1_RTS_70_MARK,		PORT70_FN2),
+	PINMUX_DATA(GIO_OUT1_70_MARK,		PORT70_FN5),
+	PINMUX_DATA(HSIC_TSTCLK0_MARK,		PORT70_FN6),
+	PINMUX_DATA(CHSCIF1_HRTS_MARK,		PORT70_FN7),
+
+	/* Port71 */
+	PINMUX_DATA(HSI_TX_DATA_MARK,		PORT71_FN1),
+	PINMUX_DATA(SCIFB1_CTS_71_MARK,		PORT71_FN2,	MSEL3CR_11_1),
+	PINMUX_DATA(GIO_OUT2_71_MARK,		PORT71_FN5),
+	PINMUX_DATA(HSIC_TSTCLK1_MARK,		PORT71_FN6),
+	PINMUX_DATA(CHSCIF1_HCTS_MARK,		PORT71_FN7),
+
+	/* Port72 */
+	PINMUX_DATA(HSI_TX_WAKE_MARK,		PORT72_FN1),
+	PINMUX_DATA(SCIFB1_RXD_72_MARK,		PORT72_FN2,	MSEL3CR_11_1),
+	PINMUX_DATA(GenIO8_MARK,		PORT72_FN5),
+	PINMUX_DATA(CHSCIF1_HRX_MARK,		PORT72_FN7),
+
+	/* Port73 */
+	PINMUX_DATA(HSI_TX_READY_MARK,		PORT73_FN1),
+	PINMUX_DATA(SCIFB2_RTS_73_MARK,		PORT73_FN2),
+	PINMUX_DATA(MSIOF3_SCK_MARK,		PORT73_FN3),
+	PINMUX_DATA(GIO_OUT0_73_MARK,		PORT73_FN5),
+
+	/* Port74 - Port85 */
+	PINMUX_DATA(IRDA_OUT_MARK,		PORT74_FN1),
+	PINMUX_DATA(IRDA_IN_MARK,		PORT75_FN1),
+	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT76_FN1),
+	PINMUX_DATA(TPU0TO0_MARK,		PORT77_FN1),
+	PINMUX_DATA(DIGRFEN_MARK,		PORT78_FN1),
+	PINMUX_DATA(GPS_TIMESTAMP_MARK,		PORT79_FN1),
+	PINMUX_DATA(TXP_MARK,			PORT80_FN1),
+	PINMUX_DATA(TXP2_MARK,			PORT81_FN1),
+	PINMUX_DATA(COEX_0_MARK,		PORT82_FN1),
+	PINMUX_DATA(COEX_1_MARK,		PORT83_FN1),
+	PINMUX_DATA(IRQ19_MARK,			PORT84_FN0),
+	PINMUX_DATA(IRQ18_MARK,			PORT85_FN0),
+
+	/* Port96 - Port101 */
+	PINMUX_DATA(KEYIN0_MARK,		PORT96_FN1),
+	PINMUX_DATA(KEYIN1_MARK,		PORT97_FN1),
+	PINMUX_DATA(KEYIN2_MARK,		PORT98_FN1),
+	PINMUX_DATA(KEYIN3_MARK,		PORT99_FN1),
+	PINMUX_DATA(KEYIN4_MARK,		PORT100_FN1),
+	PINMUX_DATA(KEYIN5_MARK,		PORT101_FN1),
+
+	/* Port102 */
+	PINMUX_DATA(KEYIN6_MARK,		PORT102_FN1),
+	PINMUX_DATA(IRQ41_MARK,			PORT102_FN0),
+
+	/* Port103 */
+	PINMUX_DATA(KEYIN7_MARK,		PORT103_FN1),
+	PINMUX_DATA(IRQ42_MARK,			PORT103_FN0),
+
+	/* Port104 - Port108 */
+	PINMUX_DATA(KEYOUT0_MARK,		PORT104_FN2),
+	PINMUX_DATA(KEYOUT1_MARK,		PORT105_FN2),
+	PINMUX_DATA(KEYOUT2_MARK,		PORT106_FN2),
+	PINMUX_DATA(KEYOUT3_MARK,		PORT107_FN2),
+	PINMUX_DATA(KEYOUT4_MARK,		PORT108_FN2),
+
+	/* Port109 */
+	PINMUX_DATA(KEYOUT5_MARK,		PORT109_FN2),
+	PINMUX_DATA(IRQ43_MARK,			PORT109_FN0),
+
+	/* Port110 */
+	PINMUX_DATA(KEYOUT6_MARK,		PORT110_FN2),
+	PINMUX_DATA(IRQ44_MARK,			PORT110_FN0),
+
+	/* Port111 */
+	PINMUX_DATA(KEYOUT7_MARK,		PORT111_FN2),
+	PINMUX_DATA(RFANAEN_MARK,		PORT111_FN5),
+	PINMUX_DATA(IRQ45_MARK,			PORT111_FN0),
+
+	/* Port112 */
+	PINMUX_DATA(KEYIN8_MARK,		PORT112_FN1),
+	PINMUX_DATA(KEYOUT8_MARK,		PORT112_FN2),
+	PINMUX_DATA(SF_IRQ_04_MARK,		PORT112_FN4),
+	PINMUX_DATA(IRQ46_MARK,			PORT112_FN0),
+
+	/* Port113 */
+	PINMUX_DATA(KEYIN9_MARK,		PORT113_FN1),
+	PINMUX_DATA(KEYOUT9_MARK,		PORT113_FN2),
+	PINMUX_DATA(SF_IRQ_05_MARK,		PORT113_FN4),
+	PINMUX_DATA(IRQ47_MARK,			PORT113_FN0),
+
+	/* Port114 */
+	PINMUX_DATA(KEYIN10_MARK,		PORT114_FN1),
+	PINMUX_DATA(KEYOUT10_MARK,		PORT114_FN2),
+	PINMUX_DATA(SF_IRQ_06_MARK,		PORT114_FN4),
+	PINMUX_DATA(IRQ48_MARK,			PORT114_FN0),
+
+	/* Port115 */
+	PINMUX_DATA(KEYIN11_MARK,		PORT115_FN1),
+	PINMUX_DATA(KEYOUT11_MARK,		PORT115_FN2),
+	PINMUX_DATA(SF_IRQ_07_MARK,		PORT115_FN4),
+	PINMUX_DATA(IRQ49_MARK,			PORT115_FN0),
+
+	/* Port116 */
+	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT116_FN1),
+	PINMUX_DATA(CSCIF0_TX_MARK,		PORT116_FN7),
+
+	/* Port117 */
+	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT117_FN1),
+	PINMUX_DATA(CSCIF0_RX_MARK,		PORT117_FN7),
+
+	/* Port118 */
+	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT118_FN1),
+	PINMUX_DATA(CSCIF1_TX_MARK,		PORT118_FN7),
+
+	/* Port119 */
+	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT119_FN1),
+	PINMUX_DATA(CSCIF1_RX_MARK,		PORT119_FN7),
+
+	/* Port120 */
+	PINMUX_DATA(SF_PORT_1_120_MARK,		PORT120_FN3),
+	PINMUX_DATA(SCIFB3_RXD_120_MARK,	PORT120_FN4,	MSEL3CR_09_1),
+	PINMUX_DATA(DU0_CDE_MARK,		PORT120_FN7),
+
+	/* Port121 */
+	PINMUX_DATA(SF_PORT_0_121_MARK,		PORT121_FN3),
+	PINMUX_DATA(SCIFB3_TXD_121_MARK,	PORT121_FN4,	MSEL3CR_09_1),
+
+	/* Port122 */
+	PINMUX_DATA(SCIFB0_TXD_MARK,		PORT122_FN1),
+	PINMUX_DATA(CHSCIF0_HTX_MARK,		PORT122_FN7),
+
+	/* Port123 */
+	PINMUX_DATA(SCIFB0_RXD_MARK,		PORT123_FN1),
+	PINMUX_DATA(CHSCIF0_HRX_MARK,		PORT123_FN7),
+
+	/* Port124 */
+	PINMUX_DATA(ISP_STROBE_124_MARK,	PORT124_FN3),
+
+	/* Port125 */
+	PINMUX_DATA(STP_ISD_0_MARK,		PORT125_FN1),
+	PINMUX_DATA(PDM4_CLK_125_MARK,		PORT125_FN2),
+	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT125_FN3),
+	PINMUX_DATA(SIM0_VOLTSEL0_MARK,		PORT125_FN5),
+
+	/* Port126 */
+	PINMUX_DATA(TS_SDEN_MARK,		PORT126_FN1),
+	PINMUX_DATA(MSIOF7_SYNC_MARK,		PORT126_FN2),
+	PINMUX_DATA(STP_ISEN_1_MARK,		PORT126_FN3),
+
+	/* Port128 */
+	PINMUX_DATA(STP_ISEN_0_MARK,		PORT128_FN1),
+	PINMUX_DATA(PDM1_OUTDATA_128_MARK,	PORT128_FN2),
+	PINMUX_DATA(MSIOF2_SYNC_MARK,		PORT128_FN3),
+	PINMUX_DATA(SIM1_VOLTSEL1_MARK,		PORT128_FN5),
+
+	/* Port129 */
+	PINMUX_DATA(TS_SPSYNC_MARK,		PORT129_FN1),
+	PINMUX_DATA(MSIOF7_RXD_MARK,		PORT129_FN2),
+	PINMUX_DATA(STP_ISSYNC_1_MARK,		PORT129_FN3),
+
+	/* Port130 */
+	PINMUX_DATA(STP_ISSYNC_0_MARK,		PORT130_FN1),
+	PINMUX_DATA(PDM4_DATA_130_MARK,		PORT130_FN2,	MSEL3CR_12_1),
+	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT130_FN3),
+	PINMUX_DATA(SIM0_VOLTSEL1_MARK,		PORT130_FN5),
+
+	/* Port131 */
+	PINMUX_DATA(STP_OPWM_0_MARK,		PORT131_FN1),
+	PINMUX_DATA(SIM1_PWRON_MARK,		PORT131_FN5),
+
+	/* Port132 */
+	PINMUX_DATA(TS_SCK_MARK,		PORT132_FN1),
+	PINMUX_DATA(MSIOF7_SCK_MARK,		PORT132_FN2),
+	PINMUX_DATA(STP_ISCLK_1_MARK,		PORT132_FN3),
+
+	/* Port133 */
+	PINMUX_DATA(STP_ISCLK_0_MARK,		PORT133_FN1),
+	PINMUX_DATA(PDM1_OUTCLK_133_MARK,	PORT133_FN2),
+	PINMUX_DATA(MSIOF2_SCK_MARK,		PORT133_FN3),
+	PINMUX_DATA(SIM1_VOLTSEL0_MARK,		PORT133_FN5),
+
+	/* Port134 */
+	PINMUX_DATA(TS_SDAT_MARK,		PORT134_FN1),
+	PINMUX_DATA(MSIOF7_TXD_MARK,		PORT134_FN2),
+	PINMUX_DATA(STP_ISD_1_MARK,		PORT134_FN3),
+
+	/* Port160 - Port178 */
+	PINMUX_DATA(IRQ20_MARK,			PORT160_FN0),
+	PINMUX_DATA(IRQ21_MARK,			PORT161_FN0),
+	PINMUX_DATA(IRQ22_MARK,			PORT162_FN0),
+	PINMUX_DATA(IRQ23_MARK,			PORT163_FN0),
+	PINMUX_DATA(MMCD0_0_MARK,		PORT164_FN1),
+	PINMUX_DATA(MMCD0_1_MARK,		PORT165_FN1),
+	PINMUX_DATA(MMCD0_2_MARK,		PORT166_FN1),
+	PINMUX_DATA(MMCD0_3_MARK,		PORT167_FN1),
+	PINMUX_DATA(MMCD0_4_MARK,		PORT168_FN1),
+	PINMUX_DATA(MMCD0_5_MARK,		PORT169_FN1),
+	PINMUX_DATA(MMCD0_6_MARK,		PORT170_FN1),
+	PINMUX_DATA(MMCD0_7_MARK,		PORT171_FN1),
+	PINMUX_DATA(MMCCMD0_MARK,		PORT172_FN1),
+	PINMUX_DATA(MMCCLK0_MARK,		PORT173_FN1),
+	PINMUX_DATA(MMCRST_MARK,		PORT174_FN1),
+	PINMUX_DATA(IRQ24_MARK,			PORT175_FN0),
+	PINMUX_DATA(IRQ25_MARK,			PORT176_FN0),
+	PINMUX_DATA(IRQ26_MARK,			PORT177_FN0),
+	PINMUX_DATA(IRQ27_MARK,			PORT178_FN0),
+
+	/* Port192 - Port200 FN1 */
+	PINMUX_DATA(A10_MARK,		PORT192_FN1),
+	PINMUX_DATA(A9_MARK,		PORT193_FN1),
+	PINMUX_DATA(A8_MARK,		PORT194_FN1),
+	PINMUX_DATA(A7_MARK,		PORT195_FN1),
+	PINMUX_DATA(A6_MARK,		PORT196_FN1),
+	PINMUX_DATA(A5_MARK,		PORT197_FN1),
+	PINMUX_DATA(A4_MARK,		PORT198_FN1),
+	PINMUX_DATA(A3_MARK,		PORT199_FN1),
+	PINMUX_DATA(A2_MARK,		PORT200_FN1),
+
+	/* Port192 - Port200 FN2 */
+	PINMUX_DATA(MMCD1_7_MARK,		PORT192_FN2),
+	PINMUX_DATA(MMCD1_6_MARK,		PORT193_FN2),
+	PINMUX_DATA(MMCD1_5_MARK,		PORT194_FN2),
+	PINMUX_DATA(MMCD1_4_MARK,		PORT195_FN2),
+	PINMUX_DATA(MMCD1_3_MARK,		PORT196_FN2),
+	PINMUX_DATA(MMCD1_2_MARK,		PORT197_FN2),
+	PINMUX_DATA(MMCD1_1_MARK,		PORT198_FN2),
+	PINMUX_DATA(MMCD1_0_MARK,		PORT199_FN2),
+	PINMUX_DATA(MMCCMD1_MARK,		PORT200_FN2),
+
+	/* Port192 - Port200 IRQ */
+	PINMUX_DATA(IRQ31_MARK,			PORT192_FN0),
+	PINMUX_DATA(IRQ32_MARK,			PORT193_FN0),
+	PINMUX_DATA(IRQ33_MARK,			PORT194_FN0),
+	PINMUX_DATA(IRQ34_MARK,			PORT195_FN0),
+	PINMUX_DATA(IRQ35_MARK,			PORT196_FN0),
+	PINMUX_DATA(IRQ36_MARK,			PORT197_FN0),
+	PINMUX_DATA(IRQ37_MARK,			PORT198_FN0),
+	PINMUX_DATA(IRQ38_MARK,			PORT199_FN0),
+	PINMUX_DATA(IRQ39_MARK,			PORT200_FN0),
+
+	/* Port201 */
+	PINMUX_DATA(A1_MARK,		PORT201_FN1),
+
+	/* Port202 */
+	PINMUX_DATA(A0_MARK,		PORT202_FN1),
+	PINMUX_DATA(BS_MARK,		PORT202_FN2),
+
+	/* Port203 */
+	PINMUX_DATA(CKO_MARK,		PORT203_FN1),
+	PINMUX_DATA(MMCCLK1_MARK,	PORT203_FN2),
+
+	/* Port204 */
+	PINMUX_DATA(CS0_N_MARK,		PORT204_FN1),
+	PINMUX_DATA(SIM0_GPO1_MARK,	PORT204_FN5),
+
+	/* Port205 */
+	PINMUX_DATA(CS2_N_MARK,		PORT205_FN1),
+	PINMUX_DATA(SIM0_GPO2_MARK,	PORT205_FN5),
+
+	/* Port206 */
+	PINMUX_DATA(CS4_N_MARK,		PORT206_FN1),
+	PINMUX_DATA(VIO_VD_MARK,	PORT206_FN2),
+	PINMUX_DATA(SIM1_GPO0_MARK,	PORT206_FN5),
+
+	/* Port207 - Port212 FN1 */
+	PINMUX_DATA(D15_MARK,		PORT207_FN1),
+	PINMUX_DATA(D14_MARK,		PORT208_FN1),
+	PINMUX_DATA(D13_MARK,		PORT209_FN1),
+	PINMUX_DATA(D12_MARK,		PORT210_FN1),
+	PINMUX_DATA(D11_MARK,		PORT211_FN1),
+	PINMUX_DATA(D10_MARK,		PORT212_FN1),
+
+	/* Port207 - Port212 FN5 */
+	PINMUX_DATA(GIO_OUT15_MARK,			PORT207_FN5),
+	PINMUX_DATA(GIO_OUT14_MARK,			PORT208_FN5),
+	PINMUX_DATA(GIO_OUT13_MARK,			PORT209_FN5),
+	PINMUX_DATA(GIO_OUT12_MARK,			PORT210_FN5),
+	PINMUX_DATA(WGM_TXP2_MARK,			PORT211_FN5),
+	PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,	PORT212_FN5),
+
+	/* Port213 - Port222 FN1 */
+	PINMUX_DATA(D9_MARK,		PORT213_FN1),
+	PINMUX_DATA(D8_MARK,		PORT214_FN1),
+	PINMUX_DATA(D7_MARK,		PORT215_FN1),
+	PINMUX_DATA(D6_MARK,		PORT216_FN1),
+	PINMUX_DATA(D5_MARK,		PORT217_FN1),
+	PINMUX_DATA(D4_MARK,		PORT218_FN1),
+	PINMUX_DATA(D3_MARK,		PORT219_FN1),
+	PINMUX_DATA(D2_MARK,		PORT220_FN1),
+	PINMUX_DATA(D1_MARK,		PORT221_FN1),
+	PINMUX_DATA(D0_MARK,		PORT222_FN1),
+
+	/* Port213 - Port222 FN2 */
+	PINMUX_DATA(VIO_D9_MARK,	PORT213_FN2),
+	PINMUX_DATA(VIO_D8_MARK,	PORT214_FN2),
+	PINMUX_DATA(VIO_D7_MARK,	PORT215_FN2),
+	PINMUX_DATA(VIO_D6_MARK,	PORT216_FN2),
+	PINMUX_DATA(VIO_D5_MARK,	PORT217_FN2),
+	PINMUX_DATA(VIO_D4_MARK,	PORT218_FN2),
+	PINMUX_DATA(VIO_D3_MARK,	PORT219_FN2),
+	PINMUX_DATA(VIO_D2_MARK,	PORT220_FN2),
+	PINMUX_DATA(VIO_D1_MARK,	PORT221_FN2),
+	PINMUX_DATA(VIO_D0_MARK,	PORT222_FN2),
+
+	/* Port213 - Port222 FN5 */
+	PINMUX_DATA(GIO_OUT9_MARK,	PORT213_FN5),
+	PINMUX_DATA(GIO_OUT8_MARK,	PORT214_FN5),
+	PINMUX_DATA(GIO_OUT7_MARK,	PORT215_FN5),
+	PINMUX_DATA(GIO_OUT6_MARK,	PORT216_FN5),
+	PINMUX_DATA(GIO_OUT5_217_MARK,	PORT217_FN5),
+	PINMUX_DATA(GIO_OUT4_218_MARK,	PORT218_FN5),
+	PINMUX_DATA(GIO_OUT3_219_MARK,	PORT219_FN5),
+	PINMUX_DATA(GIO_OUT2_220_MARK,	PORT220_FN5),
+	PINMUX_DATA(GIO_OUT1_221_MARK,	PORT221_FN5),
+	PINMUX_DATA(GIO_OUT0_222_MARK,	PORT222_FN5),
+
+	/* Port224 */
+	PINMUX_DATA(RDWR_224_MARK,	PORT224_FN1),
+	PINMUX_DATA(VIO_HD_MARK,	PORT224_FN2),
+	PINMUX_DATA(SIM1_GPO2_MARK,	PORT224_FN5),
+
+	/* Port225 */
+	PINMUX_DATA(RD_N_MARK,		PORT225_FN1),
+
+	/* Port226 */
+	PINMUX_DATA(WAIT_N_MARK,	PORT226_FN1),
+	PINMUX_DATA(VIO_CLK_MARK,	PORT226_FN2),
+	PINMUX_DATA(SIM1_GPO1_MARK,	PORT226_FN5),
+
+	/* Port227 */
+	PINMUX_DATA(WE0_N_MARK,		PORT227_FN1),
+	PINMUX_DATA(RDWR_227_MARK,	PORT227_FN2),
+
+	/* Port228 */
+	PINMUX_DATA(WE1_N_MARK,		PORT228_FN1),
+	PINMUX_DATA(SIM0_GPO0_MARK,	PORT228_FN5),
+
+	/* Port229 */
+	PINMUX_DATA(PWMO_MARK,		PORT229_FN1),
+	PINMUX_DATA(VIO_CKO1_229_MARK,	PORT229_FN2),
+
+	/* Port230 */
+	PINMUX_DATA(SLIM_CLK_MARK,	PORT230_FN1),
+	PINMUX_DATA(VIO_CKO4_230_MARK,	PORT230_FN2),
+
+	/* Port231 */
+	PINMUX_DATA(SLIM_DATA_MARK,	PORT231_FN1),
+	PINMUX_DATA(VIO_CKO5_231_MARK,	PORT231_FN2),
+
+	/* Port232 */
+	PINMUX_DATA(VIO_CKO2_232_MARK,	PORT232_FN2),
+	PINMUX_DATA(SF_PORT_0_232_MARK,	PORT232_FN4),
+
+	/* Port233 */
+	PINMUX_DATA(VIO_CKO3_233_MARK,	PORT233_FN2),
+	PINMUX_DATA(SF_PORT_1_233_MARK,	PORT233_FN4),
+
+	/* Port234 */
+	PINMUX_DATA(FSIACK_MARK,	PORT234_FN1),
+	PINMUX_DATA(PDM3_CLK_234_MARK,	PORT234_FN2),
+	PINMUX_DATA(ISP_IRIS1_234_MARK,	PORT234_FN3),
+
+	/* Port235 */
+	PINMUX_DATA(FSIAISLD_MARK,	PORT235_FN1),
+	PINMUX_DATA(PDM3_DATA_235_MARK,	PORT235_FN2,	MSEL3CR_12_1),
+
+	/* Port236 */
+	PINMUX_DATA(FSIAOMC_MARK,		PORT236_FN1),
+	PINMUX_DATA(PDM0_OUTCLK_236_MARK,	PORT236_FN2),
+	PINMUX_DATA(ISP_IRIS0_236_MARK,		PORT236_FN3),
+
+	/* Port237 */
+	PINMUX_DATA(FSIAOLR_MARK,	PORT237_FN1),
+	PINMUX_DATA(FSIAILR_MARK,	PORT237_FN2),
+
+	/* Port238 */
+	PINMUX_DATA(FSIAOBT_MARK,	PORT238_FN1),
+	PINMUX_DATA(FSIAIBT_MARK,	PORT238_FN2),
+
+	/* Port239 */
+	PINMUX_DATA(FSIAOSLD_MARK,		PORT239_FN1),
+	PINMUX_DATA(PDM0_OUTDATA_239_MARK,	PORT239_FN2),
+
+	/* Port240 */
+	PINMUX_DATA(FSIBISLD_MARK,	PORT240_FN1),
+
+	/* Port241 */
+	PINMUX_DATA(FSIBOLR_MARK,	PORT241_FN1),
+	PINMUX_DATA(FSIBILR_MARK,	PORT241_FN2),
+
+	/* Port242 */
+	PINMUX_DATA(FSIBOMC_MARK,		PORT242_FN1),
+	PINMUX_DATA(ISP_SHUTTER1_242_MARK,	PORT242_FN3),
+
+	/* Port243 */
+	PINMUX_DATA(FSIBOBT_MARK,	PORT243_FN1),
+	PINMUX_DATA(FSIBIBT_MARK,	PORT243_FN2),
+
+	/* Port244 */
+	PINMUX_DATA(FSIBOSLD_MARK,	PORT244_FN1),
+	PINMUX_DATA(FSIASPDIF_MARK,	PORT244_FN2),
+
+	/* Port245 */
+	PINMUX_DATA(FSIBCK_MARK,		PORT245_FN1),
+	PINMUX_DATA(ISP_SHUTTER0_245_MARK,	PORT245_FN3),
+
+	/* Port246 - Port250 FN1 */
+	PINMUX_DATA(ISP_IRIS1_246_MARK,		PORT246_FN1),
+	PINMUX_DATA(ISP_IRIS0_247_MARK,		PORT247_FN1),
+	PINMUX_DATA(ISP_SHUTTER1_248_MARK,	PORT248_FN1),
+	PINMUX_DATA(ISP_SHUTTER0_249_MARK,	PORT249_FN1),
+	PINMUX_DATA(ISP_STROBE_250_MARK,	PORT250_FN1),
+
+	/* Port256 - Port258 */
+	PINMUX_DATA(MSIOF0_SYNC_MARK,		PORT256_FN1),
+	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT257_FN1),
+	PINMUX_DATA(MSIOF0_SCK_MARK,		PORT258_FN1),
+
+	/* Port259 */
+	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT259_FN1),
+	PINMUX_DATA(VIO_CKO3_259_MARK,		PORT259_FN3),
+
+	/* Port260 */
+	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT260_FN1),
+
+	/* Port261 */
+	PINMUX_DATA(SCIFB1_SCK_261_MARK,	PORT261_FN2),
+	PINMUX_DATA(CHSCIF1_HSCK_MARK,		PORT261_FN7),
+
+	/* Port262 */
+	PINMUX_DATA(SCIFB2_SCK_262_MARK,	PORT262_FN2),
+
+	/* Port263 - Port266 FN1 */
+	PINMUX_DATA(MSIOF1_SS2_MARK,		PORT263_FN1),
+	PINMUX_DATA(MSIOF1_TXD_MARK,		PORT264_FN1),
+	PINMUX_DATA(MSIOF1_RXD_MARK,		PORT265_FN1),
+	PINMUX_DATA(MSIOF1_SS1_MARK,		PORT266_FN1),
+
+	/* Port263 - Port266 FN4 */
+	PINMUX_DATA(MSIOF5_SS2_MARK,		PORT263_FN4),
+	PINMUX_DATA(MSIOF5_TXD_MARK,		PORT264_FN4),
+	PINMUX_DATA(MSIOF5_RXD_MARK,		PORT265_FN4),
+	PINMUX_DATA(MSIOF5_SS1_MARK,		PORT266_FN4),
+
+	/* Port267 */
+	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT267_FN1),
+
+	/* Port268 */
+	PINMUX_DATA(MSIOF1_SCK_MARK,		PORT268_FN1),
+	PINMUX_DATA(MSIOF5_SCK_MARK,		PORT268_FN4),
+
+	/* Port269 */
+	PINMUX_DATA(MSIOF1_SYNC_MARK,		PORT269_FN1),
+	PINMUX_DATA(MSIOF5_SYNC_MARK,		PORT269_FN4),
+
+	/* Port270 - Port273 FN1 */
+	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT270_FN1),
+	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT271_FN1),
+	PINMUX_DATA(MSIOF3_SS2_MARK,		PORT272_FN1),
+	PINMUX_DATA(MSIOF3_SS1_MARK,		PORT273_FN1),
+
+	/* Port270 - Port273 FN3 */
+	PINMUX_DATA(VIO_CKO5_270_MARK,		PORT270_FN3),
+	PINMUX_DATA(VIO_CKO2_271_MARK,		PORT271_FN3),
+	PINMUX_DATA(VIO_CKO1_272_MARK,		PORT272_FN3),
+	PINMUX_DATA(VIO_CKO4_273_MARK,		PORT273_FN3),
+
+	/* Port274 */
+	PINMUX_DATA(MSIOF4_SS2_MARK,		PORT274_FN1),
+	PINMUX_DATA(TPU1TO0_MARK,		PORT274_FN4),
+
+	/* Port275 - Port280 */
+	PINMUX_DATA(IC_DP_MARK,			PORT275_FN1),
+	PINMUX_DATA(SIM0_RST_MARK,		PORT276_FN1),
+	PINMUX_DATA(IC_DM_MARK,			PORT277_FN1),
+	PINMUX_DATA(SIM0_BSICOMP_MARK,		PORT278_FN1),
+	PINMUX_DATA(SIM0_CLK_MARK,		PORT279_FN1),
+	PINMUX_DATA(SIM0_IO_MARK,		PORT280_FN1),
+
+	/* Port281 */
+	PINMUX_DATA(SIM1_IO_MARK,		PORT281_FN1),
+	PINMUX_DATA(PDM2_DATA_281_MARK,		PORT281_FN2,	MSEL3CR_12_1),
+
+	/* Port282 */
+	PINMUX_DATA(SIM1_CLK_MARK,		PORT282_FN1),
+	PINMUX_DATA(PDM2_CLK_282_MARK,		PORT282_FN2),
+
+	/* Port283 */
+	PINMUX_DATA(SIM1_RST_MARK,		PORT283_FN1),
+
+	/* Port289 */
+	PINMUX_DATA(SDHID1_0_MARK,		PORT289_FN1),
+	PINMUX_DATA(STMDATA0_2_MARK,		PORT289_FN3),
+
+	/* Port290 */
+	PINMUX_DATA(SDHID1_1_MARK,		PORT290_FN1),
+	PINMUX_DATA(STMDATA1_2_MARK,		PORT290_FN3),
+	PINMUX_DATA(IRQ51_MARK,			PORT290_FN0),
+
+	/* Port291 - Port294 FN1 */
+	PINMUX_DATA(SDHID1_2_MARK,		PORT291_FN1),
+	PINMUX_DATA(SDHID1_3_MARK,		PORT292_FN1),
+	PINMUX_DATA(SDHICLK1_MARK,		PORT293_FN1),
+	PINMUX_DATA(SDHICMD1_MARK,		PORT294_FN1),
+
+	/* Port291 - Port294 FN3 */
+	PINMUX_DATA(STMDATA2_2_MARK,		PORT291_FN3),
+	PINMUX_DATA(STMDATA3_2_MARK,		PORT292_FN3),
+	PINMUX_DATA(STMCLK_2_MARK,		PORT293_FN3),
+	PINMUX_DATA(STMSIDI_2_MARK,		PORT294_FN3),
+
+	/* Port295 */
+	PINMUX_DATA(SDHID2_0_MARK,		PORT295_FN1),
+	PINMUX_DATA(MSIOF4_TXD_MARK,		PORT295_FN2),
+	PINMUX_DATA(SCIFB2_TXD_295_MARK,	PORT295_FN3,	MSEL3CR_10_1),
+	PINMUX_DATA(MSIOF6_TXD_MARK,		PORT295_FN4),
+
+	/* Port296 */
+	PINMUX_DATA(SDHID2_1_MARK,		PORT296_FN1),
+	PINMUX_DATA(MSIOF6_SS2_MARK,		PORT296_FN4),
+	PINMUX_DATA(IRQ52_MARK,			PORT296_FN0),
+
+	/* Port297 - Port300 FN1 */
+	PINMUX_DATA(SDHID2_2_MARK,		PORT297_FN1),
+	PINMUX_DATA(SDHID2_3_MARK,		PORT298_FN1),
+	PINMUX_DATA(SDHICLK2_MARK,		PORT299_FN1),
+	PINMUX_DATA(SDHICMD2_MARK,		PORT300_FN1),
+
+	/* Port297 - Port300 FN2 */
+	PINMUX_DATA(MSIOF4_RXD_MARK,		PORT297_FN2),
+	PINMUX_DATA(MSIOF4_SYNC_MARK,		PORT298_FN2),
+	PINMUX_DATA(MSIOF4_SCK_MARK,		PORT299_FN2),
+	PINMUX_DATA(MSIOF4_SS1_MARK,		PORT300_FN2),
+
+	/* Port297 - Port300 FN3 */
+	PINMUX_DATA(SCIFB2_RXD_297_MARK,	PORT297_FN3,	MSEL3CR_10_1),
+	PINMUX_DATA(SCIFB2_CTS_298_MARK,	PORT298_FN3,	MSEL3CR_10_1),
+	PINMUX_DATA(SCIFB2_SCK_299_MARK,	PORT299_FN3),
+	PINMUX_DATA(SCIFB2_RTS_300_MARK,	PORT300_FN3),
+
+	/* Port297 - Port300 FN4 */
+	PINMUX_DATA(MSIOF6_RXD_MARK,		PORT297_FN4),
+	PINMUX_DATA(MSIOF6_SYNC_MARK,		PORT298_FN4),
+	PINMUX_DATA(MSIOF6_SCK_MARK,		PORT299_FN4),
+	PINMUX_DATA(MSIOF6_SS1_MARK,		PORT300_FN4),
+
+	/* Port301 */
+	PINMUX_DATA(SDHICD0_MARK,		PORT301_FN1),
+	PINMUX_DATA(IRQ50_MARK,			PORT301_FN0),
+
+	/* Port302 - Port306 FN1 */
+	PINMUX_DATA(SDHID0_0_MARK,		PORT302_FN1),
+	PINMUX_DATA(SDHID0_1_MARK,		PORT303_FN1),
+	PINMUX_DATA(SDHID0_2_MARK,		PORT304_FN1),
+	PINMUX_DATA(SDHID0_3_MARK,		PORT305_FN1),
+	PINMUX_DATA(SDHICMD0_MARK,		PORT306_FN1),
+
+	/* Port302 - Port306 FN3 */
+	PINMUX_DATA(STMDATA0_1_MARK,		PORT302_FN3),
+	PINMUX_DATA(STMDATA1_1_MARK,		PORT303_FN3),
+	PINMUX_DATA(STMDATA2_1_MARK,		PORT304_FN3),
+	PINMUX_DATA(STMDATA3_1_MARK,		PORT305_FN3),
+	PINMUX_DATA(STMSIDI_1_MARK,		PORT306_FN3),
+
+	/* Port307 */
+	PINMUX_DATA(SDHIWP0_MARK,		PORT307_FN1),
+
+	/* Port308 */
+	PINMUX_DATA(SDHICLK0_MARK,		PORT308_FN1),
+	PINMUX_DATA(STMCLK_1_MARK,		PORT308_FN3),
+
+	/* Port320 - Port329 */
+	PINMUX_DATA(IRQ16_MARK,			PORT320_FN0),
+	PINMUX_DATA(IRQ17_MARK,			PORT321_FN0),
+	PINMUX_DATA(IRQ28_MARK,			PORT322_FN0),
+	PINMUX_DATA(IRQ29_MARK,			PORT323_FN0),
+	PINMUX_DATA(IRQ30_MARK,			PORT324_FN0),
+	PINMUX_DATA(IRQ53_MARK,			PORT325_FN0),
+	PINMUX_DATA(IRQ54_MARK,			PORT326_FN0),
+	PINMUX_DATA(IRQ55_MARK,			PORT327_FN0),
+	PINMUX_DATA(IRQ56_MARK,			PORT328_FN0),
+	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+	GPIO_PORT_ALL(),
+};
+
+#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
+	/* Port0 */
+	GPIO_FN(LCDD0),
+	GPIO_FN(PDM2_CLK_0),
+	GPIO_FN(DU0_DR0),
+	GPIO_FN(IRQ0),
+
+	/* Port1 */
+	GPIO_FN(LCDD1),
+	GPIO_FN(PDM2_DATA_1),
+	GPIO_FN(DU0_DR19),
+	GPIO_FN(IRQ1),
+
+	/* Port2 */
+	GPIO_FN(LCDD2),
+	GPIO_FN(PDM3_CLK_2),
+	GPIO_FN(DU0_DR2),
+	GPIO_FN(IRQ2),
+
+	/* Port3 */
+	GPIO_FN(LCDD3),
+	GPIO_FN(PDM3_DATA_3),
+	GPIO_FN(DU0_DR3),
+	GPIO_FN(IRQ3),
+
+	/* Port4 */
+	GPIO_FN(LCDD4),
+	GPIO_FN(PDM4_CLK_4),
+	GPIO_FN(DU0_DR4),
+	GPIO_FN(IRQ4),
+
+	/* Port5 */
+	GPIO_FN(LCDD5),
+	GPIO_FN(PDM4_DATA_5),
+	GPIO_FN(DU0_DR5),
+	GPIO_FN(IRQ5),
+
+	/* Port6 */
+	GPIO_FN(LCDD6),
+	GPIO_FN(PDM0_OUTCLK_6),
+	GPIO_FN(DU0_DR6),
+	GPIO_FN(IRQ6),
+
+	/* Port7 */
+	GPIO_FN(LCDD7),
+	GPIO_FN(PDM0_OUTDATA_7),
+	GPIO_FN(DU0_DR7),
+	GPIO_FN(IRQ7),
+
+	/* Port8 */
+	GPIO_FN(LCDD8),
+	GPIO_FN(PDM1_OUTCLK_8),
+	GPIO_FN(DU0_DG0),
+	GPIO_FN(IRQ8),
+
+	/* Port9 */
+	GPIO_FN(LCDD9),
+	GPIO_FN(PDM1_OUTDATA_9),
+	GPIO_FN(DU0_DG1),
+	GPIO_FN(IRQ9),
+
+	/* Port10 */
+	GPIO_FN(LCDD10),
+	GPIO_FN(FSICCK),
+	GPIO_FN(DU0_DG2),
+	GPIO_FN(IRQ10),
+
+	/* Port11 */
+	GPIO_FN(LCDD11),
+	GPIO_FN(FSICISLD),
+	GPIO_FN(DU0_DG3),
+	GPIO_FN(IRQ11),
+
+	/* Port12 */
+	GPIO_FN(LCDD12),
+	GPIO_FN(FSICOMC),
+	GPIO_FN(DU0_DG4),
+	GPIO_FN(IRQ12),
+
+	/* Port13 */
+	GPIO_FN(LCDD13),
+	GPIO_FN(FSICOLR),
+	GPIO_FN(FSICILR),
+	GPIO_FN(DU0_DG5),
+	GPIO_FN(IRQ13),
+
+	/* Port14 */
+	GPIO_FN(LCDD14),
+	GPIO_FN(FSICOBT),
+	GPIO_FN(FSICIBT),
+	GPIO_FN(DU0_DG6),
+	GPIO_FN(IRQ14),
+
+	/* Port15 */
+	GPIO_FN(LCDD15),
+	GPIO_FN(FSICOSLD),
+	GPIO_FN(DU0_DG7),
+	GPIO_FN(IRQ15),
+
+	/* Port16 */
+	GPIO_FN(LCDD16),
+	GPIO_FN(TPU1TO1),
+	GPIO_FN(DU0_DB0),
+
+	/* Port17 */
+	GPIO_FN(LCDD17),
+	GPIO_FN(SF_IRQ_00),
+	GPIO_FN(DU0_DB1),
+
+	/* Port18 */
+	GPIO_FN(LCDD18),
+	GPIO_FN(SF_IRQ_01),
+	GPIO_FN(DU0_DB2),
+
+	/* Port19 */
+	GPIO_FN(LCDD19),
+	GPIO_FN(SCIFB3_RTS_19),
+	GPIO_FN(DU0_DB3),
+
+	/* Port20 */
+	GPIO_FN(LCDD20),
+	GPIO_FN(SCIFB3_CTS_20),
+	GPIO_FN(DU0_DB4),
+
+	/* Port21 */
+	GPIO_FN(LCDD21),
+	GPIO_FN(SCIFB3_TXD_21),
+	GPIO_FN(DU0_DB5),
+
+	/* Port22 */
+	GPIO_FN(LCDD22),
+	GPIO_FN(SCIFB3_RXD_22),
+	GPIO_FN(DU0_DB6),
+
+	/* Port23 */
+	GPIO_FN(LCDD23),
+	GPIO_FN(SCIFB3_SCK_23),
+	GPIO_FN(DU0_DB7),
+
+	/* Port24 */
+	GPIO_FN(LCDHSYN),
+	GPIO_FN(LCDCS),
+	GPIO_FN(SCIFB1_RTS_24),
+	GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
+
+	/* Port25 */
+	GPIO_FN(LCDVSYN),
+	GPIO_FN(SCIFB1_CTS_25),
+	GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
+
+	/* Port26 */
+	GPIO_FN(LCDDCK),
+	GPIO_FN(LCDWR),
+	GPIO_FN(SCIFB1_TXD_26),
+	GPIO_FN(DU0_DOTCLKIN),
+
+	/* Port27 */
+	GPIO_FN(LCDDISP),
+	GPIO_FN(LCDRS),
+	GPIO_FN(SCIFB1_RXD_27),
+	GPIO_FN(DU0_DOTCLKOUT),
+
+	/* Port28 */
+	GPIO_FN(LCDRD_N),
+	GPIO_FN(SCIFB1_SCK_28),
+	GPIO_FN(DU0_DOTCLKOUTB),
+
+	/* Port29 */
+	GPIO_FN(LCDLCLK),
+	GPIO_FN(SF_IRQ_02),
+	GPIO_FN(DU0_DISP_CSYNC_N_DE),
+
+	/* Port30 */
+	GPIO_FN(LCDDON),
+	GPIO_FN(SF_IRQ_03),
+	GPIO_FN(DU0_ODDF_N_CLAMP),
+
+	/* Port32 */
+	GPIO_FN(SCIFA0_RTS),
+	GPIO_FN(SIM0_DET),
+	GPIO_FN(CSCIF0_RTS),
+
+	/* Port33 */
+	GPIO_FN(SCIFA0_CTS),
+	GPIO_FN(SIM1_DET),
+	GPIO_FN(CSCIF0_CTS),
+
+	/* Port34 */
+	GPIO_FN(SCIFA0_SCK),
+	GPIO_FN(SIM0_PWRON),
+	GPIO_FN(CSCIF0_SCK),
+
+	/* Port35 */
+	GPIO_FN(SCIFA1_RTS),
+	GPIO_FN(CSCIF1_RTS),
+
+	/* Port36 */
+	GPIO_FN(SCIFA1_CTS),
+	GPIO_FN(CSCIF1_CTS),
+
+	/* Port37 */
+	GPIO_FN(SCIFA1_SCK),
+	GPIO_FN(CSCIF1_SCK),
+
+	/* Port38 */
+	GPIO_FN(SCIFB0_RTS),
+	GPIO_FN(TPU0TO1),
+	GPIO_FN(SCIFB3_RTS_38),
+	GPIO_FN(CHSCIF0_HRTS),
+
+	/* Port39 */
+	GPIO_FN(SCIFB0_CTS),
+	GPIO_FN(TPU0TO2),
+	GPIO_FN(SCIFB3_CTS_39),
+	GPIO_FN(CHSCIF0_HCTS),
+
+	/* Port40 */
+	GPIO_FN(SCIFB0_SCK),
+	GPIO_FN(TPU0TO3),
+	GPIO_FN(SCIFB3_SCK_40),
+	GPIO_FN(CHSCIF0_HSCK),
+
+	/* Port64 */
+	GPIO_FN(PDM0_DATA),
+
+	/* Port65 */
+	GPIO_FN(PDM1_DATA),
+
+	/* Port66 */
+	GPIO_FN(HSI_RX_WAKE),
+	GPIO_FN(SCIFB2_CTS_66),
+	GPIO_FN(MSIOF3_SYNC),
+	GPIO_FN(GenIO4),
+	GPIO_FN(IRQ40),
+
+	/* Port67 */
+	GPIO_FN(HSI_RX_READY),
+	GPIO_FN(SCIFB1_TXD_67),
+	GPIO_FN(GIO_OUT3_67),
+	GPIO_FN(CHSCIF1_HTX),
+
+	/* Port68 */
+	GPIO_FN(HSI_RX_FLAG),
+	GPIO_FN(SCIFB2_TXD_68),
+	GPIO_FN(MSIOF3_TXD),
+	GPIO_FN(GIO_OUT4_68),
+
+	/* Port69 */
+	GPIO_FN(HSI_RX_DATA),
+	GPIO_FN(SCIFB2_RXD_69),
+	GPIO_FN(MSIOF3_RXD),
+	GPIO_FN(GIO_OUT5_69),
+
+	/* Port70 */
+	GPIO_FN(HSI_TX_FLAG),
+	GPIO_FN(SCIFB1_RTS_70),
+	GPIO_FN(GIO_OUT1_70),
+	GPIO_FN(HSIC_TSTCLK0),
+	GPIO_FN(CHSCIF1_HRTS),
+
+	/* Port71 */
+	GPIO_FN(HSI_TX_DATA),
+	GPIO_FN(SCIFB1_CTS_71),
+	GPIO_FN(GIO_OUT2_71),
+	GPIO_FN(HSIC_TSTCLK1),
+	GPIO_FN(CHSCIF1_HCTS),
+
+	/* Port72 */
+	GPIO_FN(HSI_TX_WAKE),
+	GPIO_FN(SCIFB1_RXD_72),
+	GPIO_FN(GenIO8),
+	GPIO_FN(CHSCIF1_HRX),
+
+	/* Port73 */
+	GPIO_FN(HSI_TX_READY),
+	GPIO_FN(SCIFB2_RTS_73),
+	GPIO_FN(MSIOF3_SCK),
+	GPIO_FN(GIO_OUT0_73),
+
+	/* Port74 - Port85 */
+	GPIO_FN(IRDA_OUT),
+	GPIO_FN(IRDA_IN),
+	GPIO_FN(IRDA_FIRSEL),
+	GPIO_FN(TPU0TO0),
+	GPIO_FN(DIGRFEN),
+	GPIO_FN(GPS_TIMESTAMP),
+	GPIO_FN(TXP),
+	GPIO_FN(TXP2),
+	GPIO_FN(COEX_0),
+	GPIO_FN(COEX_1),
+	GPIO_FN(IRQ19),
+	GPIO_FN(IRQ18),
+
+	/* Port96 - Port101 */
+	GPIO_FN(KEYIN0),
+	GPIO_FN(KEYIN1),
+	GPIO_FN(KEYIN2),
+	GPIO_FN(KEYIN3),
+	GPIO_FN(KEYIN4),
+	GPIO_FN(KEYIN5),
+
+	/* Port102 */
+	GPIO_FN(KEYIN6),
+	GPIO_FN(IRQ41),
+
+	/* Port103 */
+	GPIO_FN(KEYIN7),
+	GPIO_FN(IRQ42),
+
+	/* Port104 - Port108 */
+	GPIO_FN(KEYOUT0),
+	GPIO_FN(KEYOUT1),
+	GPIO_FN(KEYOUT2),
+	GPIO_FN(KEYOUT3),
+	GPIO_FN(KEYOUT4),
+
+	/* Port109 */
+	GPIO_FN(KEYOUT5),
+	GPIO_FN(IRQ43),
+
+	/* Port110 */
+	GPIO_FN(KEYOUT6),
+	GPIO_FN(IRQ44),
+
+	/* Port111 */
+	GPIO_FN(KEYOUT7),
+	GPIO_FN(RFANAEN),
+	GPIO_FN(IRQ45),
+
+	/* Port112 */
+	GPIO_FN(KEYIN8),
+	GPIO_FN(KEYOUT8),
+	GPIO_FN(SF_IRQ_04),
+	GPIO_FN(IRQ46),
+
+	/* Port113 */
+	GPIO_FN(KEYIN9),
+	GPIO_FN(KEYOUT9),
+	GPIO_FN(SF_IRQ_05),
+	GPIO_FN(IRQ47),
+
+	/* Port114 */
+	GPIO_FN(KEYIN10),
+	GPIO_FN(KEYOUT10),
+	GPIO_FN(SF_IRQ_06),
+	GPIO_FN(IRQ48),
+
+	/* Port115 */
+	GPIO_FN(KEYIN11),
+	GPIO_FN(KEYOUT11),
+	GPIO_FN(SF_IRQ_07),
+	GPIO_FN(IRQ49),
+
+	/* Port116 */
+	GPIO_FN(SCIFA0_TXD),
+	GPIO_FN(CSCIF0_TX),
+
+	/* Port117 */
+	GPIO_FN(SCIFA0_RXD),
+	GPIO_FN(CSCIF0_RX),
+
+	/* Port118 */
+	GPIO_FN(SCIFA1_TXD),
+	GPIO_FN(CSCIF1_TX),
+
+	/* Port119 */
+	GPIO_FN(SCIFA1_RXD),
+	GPIO_FN(CSCIF1_RX),
+
+	/* Port120 */
+	GPIO_FN(SF_PORT_1_120),
+	GPIO_FN(SCIFB3_RXD_120),
+	GPIO_FN(DU0_CDE),
+
+	/* Port121 */
+	GPIO_FN(SF_PORT_0_121),
+	GPIO_FN(SCIFB3_TXD_121),
+
+	/* Port122 */
+	GPIO_FN(SCIFB0_TXD),
+	GPIO_FN(CHSCIF0_HTX),
+
+	/* Port123 */
+	GPIO_FN(SCIFB0_RXD),
+	GPIO_FN(CHSCIF0_HRX),
+
+	/* Port124 */
+	GPIO_FN(ISP_STROBE_124),
+
+	/* Port125 */
+	GPIO_FN(STP_ISD_0),
+	GPIO_FN(PDM4_CLK_125),
+	GPIO_FN(MSIOF2_TXD),
+	GPIO_FN(SIM0_VOLTSEL0),
+
+	/* Port126 */
+	GPIO_FN(TS_SDEN),
+	GPIO_FN(MSIOF7_SYNC),
+	GPIO_FN(STP_ISEN_1),
+
+	/* Port128 */
+	GPIO_FN(STP_ISEN_0),
+	GPIO_FN(PDM1_OUTDATA_128),
+	GPIO_FN(MSIOF2_SYNC),
+	GPIO_FN(SIM1_VOLTSEL1),
+
+	/* Port129 */
+	GPIO_FN(TS_SPSYNC),
+	GPIO_FN(MSIOF7_RXD),
+	GPIO_FN(STP_ISSYNC_1),
+
+	/* Port130 */
+	GPIO_FN(STP_ISSYNC_0),
+	GPIO_FN(PDM4_DATA_130),
+	GPIO_FN(MSIOF2_RXD),
+	GPIO_FN(SIM0_VOLTSEL1),
+
+	/* Port131 */
+	GPIO_FN(STP_OPWM_0),
+	GPIO_FN(SIM1_PWRON),
+
+	/* Port132 */
+	GPIO_FN(TS_SCK),
+	GPIO_FN(MSIOF7_SCK),
+	GPIO_FN(STP_ISCLK_1),
+
+	/* Port133 */
+	GPIO_FN(STP_ISCLK_0),
+	GPIO_FN(PDM1_OUTCLK_133),
+	GPIO_FN(MSIOF2_SCK),
+	GPIO_FN(SIM1_VOLTSEL0),
+
+	/* Port134 */
+	GPIO_FN(TS_SDAT),
+	GPIO_FN(MSIOF7_TXD),
+	GPIO_FN(STP_ISD_1),
+
+	/* Port160 - Port178 */
+	GPIO_FN(IRQ20),
+	GPIO_FN(IRQ21),
+	GPIO_FN(IRQ22),
+	GPIO_FN(IRQ23),
+	GPIO_FN(MMCD0_0),
+	GPIO_FN(MMCD0_1),
+	GPIO_FN(MMCD0_2),
+	GPIO_FN(MMCD0_3),
+	GPIO_FN(MMCD0_4),
+	GPIO_FN(MMCD0_5),
+	GPIO_FN(MMCD0_6),
+	GPIO_FN(MMCD0_7),
+	GPIO_FN(MMCCMD0),
+	GPIO_FN(MMCCLK0),
+	GPIO_FN(MMCRST),
+	GPIO_FN(IRQ24),
+	GPIO_FN(IRQ25),
+	GPIO_FN(IRQ26),
+	GPIO_FN(IRQ27),
+
+	/* Port192 - Port200 FN1 */
+	GPIO_FN(A10),
+	GPIO_FN(A9),
+	GPIO_FN(A8),
+	GPIO_FN(A7),
+	GPIO_FN(A6),
+	GPIO_FN(A5),
+	GPIO_FN(A4),
+	GPIO_FN(A3),
+	GPIO_FN(A2),
+
+	/* Port192 - Port200 FN2 */
+	GPIO_FN(MMCD1_7),
+	GPIO_FN(MMCD1_6),
+	GPIO_FN(MMCD1_5),
+	GPIO_FN(MMCD1_4),
+	GPIO_FN(MMCD1_3),
+	GPIO_FN(MMCD1_2),
+	GPIO_FN(MMCD1_1),
+	GPIO_FN(MMCD1_0),
+	GPIO_FN(MMCCMD1),
+
+	/* Port192 - Port200 IRQ */
+	GPIO_FN(IRQ31),
+	GPIO_FN(IRQ32),
+	GPIO_FN(IRQ33),
+	GPIO_FN(IRQ34),
+	GPIO_FN(IRQ35),
+	GPIO_FN(IRQ36),
+	GPIO_FN(IRQ37),
+	GPIO_FN(IRQ38),
+	GPIO_FN(IRQ39),
+
+	/* Port201 */
+	GPIO_FN(A1),
+
+	/* Port202 */
+	GPIO_FN(A0),
+	GPIO_FN(BS),
+
+	/* Port203 */
+	GPIO_FN(CKO),
+	GPIO_FN(MMCCLK1),
+
+	/* Port204 */
+	GPIO_FN(CS0_N),
+	GPIO_FN(SIM0_GPO1),
+
+	/* Port205 */
+	GPIO_FN(CS2_N),
+	GPIO_FN(SIM0_GPO2),
+
+	/* Port206 */
+	GPIO_FN(CS4_N),
+	GPIO_FN(VIO_VD),
+	GPIO_FN(SIM1_GPO0),
+
+	/* Port207 - Port212 FN1 */
+	GPIO_FN(D15),
+	GPIO_FN(D14),
+	GPIO_FN(D13),
+	GPIO_FN(D12),
+	GPIO_FN(D11),
+	GPIO_FN(D10),
+
+	/* Port207 - Port212 FN5 */
+	GPIO_FN(GIO_OUT15),
+	GPIO_FN(GIO_OUT14),
+	GPIO_FN(GIO_OUT13),
+	GPIO_FN(GIO_OUT12),
+	GPIO_FN(WGM_TXP2),
+	GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK),
+
+	/* Port213 - Port222 FN1 */
+	GPIO_FN(D9),
+	GPIO_FN(D8),
+	GPIO_FN(D7),
+	GPIO_FN(D6),
+	GPIO_FN(D5),
+	GPIO_FN(D4),
+	GPIO_FN(D3),
+	GPIO_FN(D2),
+	GPIO_FN(D1),
+	GPIO_FN(D0),
+
+	/* Port213 - Port222 FN2 */
+	GPIO_FN(VIO_D9),
+	GPIO_FN(VIO_D8),
+	GPIO_FN(VIO_D7),
+	GPIO_FN(VIO_D6),
+	GPIO_FN(VIO_D5),
+	GPIO_FN(VIO_D4),
+	GPIO_FN(VIO_D3),
+	GPIO_FN(VIO_D2),
+	GPIO_FN(VIO_D1),
+	GPIO_FN(VIO_D0),
+
+	/* Port213 - Port222 FN5 */
+	GPIO_FN(GIO_OUT9),
+	GPIO_FN(GIO_OUT8),
+	GPIO_FN(GIO_OUT7),
+	GPIO_FN(GIO_OUT6),
+	GPIO_FN(GIO_OUT5_217),
+	GPIO_FN(GIO_OUT4_218),
+	GPIO_FN(GIO_OUT3_219),
+	GPIO_FN(GIO_OUT2_220),
+	GPIO_FN(GIO_OUT1_221),
+	GPIO_FN(GIO_OUT0_222),
+
+	/* Port224 */
+	GPIO_FN(RDWR_224),
+	GPIO_FN(VIO_HD),
+	GPIO_FN(SIM1_GPO2),
+
+	/* Port225 */
+	GPIO_FN(RD_N),
+
+	/* Port226 */
+	GPIO_FN(WAIT_N),
+	GPIO_FN(VIO_CLK),
+	GPIO_FN(SIM1_GPO1),
+
+	/* Port227 */
+	GPIO_FN(WE0_N),
+	GPIO_FN(RDWR_227),
+
+	/* Port228 */
+	GPIO_FN(WE1_N),
+	GPIO_FN(SIM0_GPO0),
+
+	/* Port229 */
+	GPIO_FN(PWMO),
+	GPIO_FN(VIO_CKO1_229),
+
+	/* Port230 */
+	GPIO_FN(SLIM_CLK),
+	GPIO_FN(VIO_CKO4_230),
+
+	/* Port231 */
+	GPIO_FN(SLIM_DATA),
+	GPIO_FN(VIO_CKO5_231),
+
+	/* Port232 */
+	GPIO_FN(VIO_CKO2_232),
+	GPIO_FN(SF_PORT_0_232),
+
+	/* Port233 */
+	GPIO_FN(VIO_CKO3_233),
+	GPIO_FN(SF_PORT_1_233),
+
+	/* Port234 */
+	GPIO_FN(FSIACK),
+	GPIO_FN(PDM3_CLK_234),
+	GPIO_FN(ISP_IRIS1_234),
+
+	/* Port235 */
+	GPIO_FN(FSIAISLD),
+	GPIO_FN(PDM3_DATA_235),
+
+	/* Port236 */
+	GPIO_FN(FSIAOMC),
+	GPIO_FN(PDM0_OUTCLK_236),
+	GPIO_FN(ISP_IRIS0_236),
+
+	/* Port237 */
+	GPIO_FN(FSIAOLR),
+	GPIO_FN(FSIAILR),
+
+	/* Port238 */
+	GPIO_FN(FSIAOBT),
+	GPIO_FN(FSIAIBT),
+
+	/* Port239 */
+	GPIO_FN(FSIAOSLD),
+	GPIO_FN(PDM0_OUTDATA_239),
+
+	/* Port240 */
+	GPIO_FN(FSIBISLD),
+
+	/* Port241 */
+	GPIO_FN(FSIBOLR),
+	GPIO_FN(FSIBILR),
+
+	/* Port242 */
+	GPIO_FN(FSIBOMC),
+	GPIO_FN(ISP_SHUTTER1_242),
+
+	/* Port243 */
+	GPIO_FN(FSIBOBT),
+	GPIO_FN(FSIBIBT),
+
+	/* Port244 */
+	GPIO_FN(FSIBOSLD),
+	GPIO_FN(FSIASPDIF),
+
+	/* Port245 */
+	GPIO_FN(FSIBCK),
+	GPIO_FN(ISP_SHUTTER0_245),
+
+	/* Port246 - Port250 FN1 */
+	GPIO_FN(ISP_IRIS1_246),
+	GPIO_FN(ISP_IRIS0_247),
+	GPIO_FN(ISP_SHUTTER1_248),
+	GPIO_FN(ISP_SHUTTER0_249),
+	GPIO_FN(ISP_STROBE_250),
+
+	/* Port256 - Port258 */
+	GPIO_FN(MSIOF0_SYNC),
+	GPIO_FN(MSIOF0_RXD),
+	GPIO_FN(MSIOF0_SCK),
+
+	/* Port259 */
+	GPIO_FN(MSIOF0_SS2),
+	GPIO_FN(VIO_CKO3_259),
+
+	/* Port260 */
+	GPIO_FN(MSIOF0_TXD),
+
+	/* Port261 */
+	GPIO_FN(SCIFB1_SCK_261),
+	GPIO_FN(CHSCIF1_HSCK),
+
+	/* Port262 */
+	GPIO_FN(SCIFB2_SCK_262),
+
+	/* Port263 - Port266 FN1 */
+	GPIO_FN(MSIOF1_SS2),
+	GPIO_FN(MSIOF1_TXD),
+	GPIO_FN(MSIOF1_RXD),
+	GPIO_FN(MSIOF1_SS1),
+
+	/* Port263 - Port266 FN4 */
+	GPIO_FN(MSIOF5_SS2),
+	GPIO_FN(MSIOF5_TXD),
+	GPIO_FN(MSIOF5_RXD),
+	GPIO_FN(MSIOF5_SS1),
+
+	/* Port267 */
+	GPIO_FN(MSIOF0_SS1),
+
+	/* Port268 */
+	GPIO_FN(MSIOF1_SCK),
+	GPIO_FN(MSIOF5_SCK),
+
+	/* Port269 */
+	GPIO_FN(MSIOF1_SYNC),
+	GPIO_FN(MSIOF5_SYNC),
+
+	/* Port270 - Port273 FN1 */
+	GPIO_FN(MSIOF2_SS1),
+	GPIO_FN(MSIOF2_SS2),
+	GPIO_FN(MSIOF3_SS2),
+	GPIO_FN(MSIOF3_SS1),
+
+	/* Port270 - Port273 FN3 */
+	GPIO_FN(VIO_CKO5_270),
+	GPIO_FN(VIO_CKO2_271),
+	GPIO_FN(VIO_CKO1_272),
+	GPIO_FN(VIO_CKO4_273),
+
+	/* Port274 */
+	GPIO_FN(MSIOF4_SS2),
+	GPIO_FN(TPU1TO0),
+
+	/* Port275 - Port280 */
+	GPIO_FN(IC_DP),
+	GPIO_FN(SIM0_RST),
+	GPIO_FN(IC_DM),
+	GPIO_FN(SIM0_BSICOMP),
+	GPIO_FN(SIM0_CLK),
+	GPIO_FN(SIM0_IO),
+
+	/* Port281 */
+	GPIO_FN(SIM1_IO),
+	GPIO_FN(PDM2_DATA_281),
+
+	/* Port282 */
+	GPIO_FN(SIM1_CLK),
+	GPIO_FN(PDM2_CLK_282),
+
+	/* Port283 */
+	GPIO_FN(SIM1_RST),
+
+	/* Port289 */
+	GPIO_FN(SDHID1_0),
+	GPIO_FN(STMDATA0_2),
+
+	/* Port290 */
+	GPIO_FN(SDHID1_1),
+	GPIO_FN(STMDATA1_2),
+	GPIO_FN(IRQ51),
+
+	/* Port291 - Port294 FN1 */
+	GPIO_FN(SDHID1_2),
+	GPIO_FN(SDHID1_3),
+	GPIO_FN(SDHICLK1),
+	GPIO_FN(SDHICMD1),
+
+	/* Port291 - Port294 FN3 */
+	GPIO_FN(STMDATA2_2),
+	GPIO_FN(STMDATA3_2),
+	GPIO_FN(STMCLK_2),
+	GPIO_FN(STMSIDI_2),
+
+	/* Port295 */
+	GPIO_FN(SDHID2_0),
+	GPIO_FN(MSIOF4_TXD),
+	GPIO_FN(SCIFB2_TXD_295),
+	GPIO_FN(MSIOF6_TXD),
+
+	/* Port296 */
+	GPIO_FN(SDHID2_1),
+	GPIO_FN(MSIOF6_SS2),
+	GPIO_FN(IRQ52),
+
+	/* Port297 - Port300 FN1 */
+	GPIO_FN(SDHID2_2),
+	GPIO_FN(SDHID2_3),
+	GPIO_FN(SDHICLK2),
+	GPIO_FN(SDHICMD2),
+
+	/* Port297 - Port300 FN2 */
+	GPIO_FN(MSIOF4_RXD),
+	GPIO_FN(MSIOF4_SYNC),
+	GPIO_FN(MSIOF4_SCK),
+	GPIO_FN(MSIOF4_SS1),
+
+	/* Port297 - Port300 FN3 */
+	GPIO_FN(SCIFB2_RXD_297),
+	GPIO_FN(SCIFB2_CTS_298),
+	GPIO_FN(SCIFB2_SCK_299),
+	GPIO_FN(SCIFB2_RTS_300),
+
+	/* Port297 - Port300 FN4 */
+	GPIO_FN(MSIOF6_RXD),
+	GPIO_FN(MSIOF6_SYNC),
+	GPIO_FN(MSIOF6_SCK),
+	GPIO_FN(MSIOF6_SS1),
+
+	/* Port301 */
+	GPIO_FN(SDHICD0),
+	GPIO_FN(IRQ50),
+
+	/* Port302 - Port306 FN1 */
+	GPIO_FN(SDHID0_0),
+	GPIO_FN(SDHID0_1),
+	GPIO_FN(SDHID0_2),
+	GPIO_FN(SDHID0_3),
+	GPIO_FN(SDHICMD0),
+
+	/* Port302 - Port306 FN3 */
+	GPIO_FN(STMDATA0_1),
+	GPIO_FN(STMDATA1_1),
+	GPIO_FN(STMDATA2_1),
+	GPIO_FN(STMDATA3_1),
+	GPIO_FN(STMSIDI_1),
+
+	/* Port307 */
+	GPIO_FN(SDHIWP0),
+
+	/* Port308 */
+	GPIO_FN(SDHICLK0),
+	GPIO_FN(STMCLK_1),
+
+	/* Port320 - Port329 */
+	GPIO_FN(IRQ16),
+	GPIO_FN(IRQ17),
+	GPIO_FN(IRQ28),
+	GPIO_FN(IRQ29),
+	GPIO_FN(IRQ30),
+	GPIO_FN(IRQ53),
+	GPIO_FN(IRQ54),
+	GPIO_FN(IRQ55),
+	GPIO_FN(IRQ56),
+	GPIO_FN(IRQ57),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+
+	PORTCR(0, 0xe6050000),
+	PORTCR(1, 0xe6050001),
+	PORTCR(2, 0xe6050002),
+	PORTCR(3, 0xe6050003),
+	PORTCR(4, 0xe6050004),
+	PORTCR(5, 0xe6050005),
+	PORTCR(6, 0xe6050006),
+	PORTCR(7, 0xe6050007),
+	PORTCR(8, 0xe6050008),
+	PORTCR(9, 0xe6050009),
+	PORTCR(10, 0xe605000A),
+	PORTCR(11, 0xe605000B),
+	PORTCR(12, 0xe605000C),
+	PORTCR(13, 0xe605000D),
+	PORTCR(14, 0xe605000E),
+	PORTCR(15, 0xe605000F),
+	PORTCR(16, 0xe6050010),
+	PORTCR(17, 0xe6050011),
+	PORTCR(18, 0xe6050012),
+	PORTCR(19, 0xe6050013),
+	PORTCR(20, 0xe6050014),
+	PORTCR(21, 0xe6050015),
+	PORTCR(22, 0xe6050016),
+	PORTCR(23, 0xe6050017),
+	PORTCR(24, 0xe6050018),
+	PORTCR(25, 0xe6050019),
+	PORTCR(26, 0xe605001A),
+	PORTCR(27, 0xe605001B),
+	PORTCR(28, 0xe605001C),
+	PORTCR(29, 0xe605001D),
+	PORTCR(30, 0xe605001E),
+	PORTCR(32, 0xe6051020),
+	PORTCR(33, 0xe6051021),
+	PORTCR(34, 0xe6051022),
+	PORTCR(35, 0xe6051023),
+	PORTCR(36, 0xe6051024),
+	PORTCR(37, 0xe6051025),
+	PORTCR(38, 0xe6051026),
+	PORTCR(39, 0xe6051027),
+	PORTCR(40, 0xe6051028),
+	PORTCR(64, 0xe6050040),
+	PORTCR(65, 0xe6050041),
+	PORTCR(66, 0xe6050042),
+	PORTCR(67, 0xe6050043),
+	PORTCR(68, 0xe6050044),
+	PORTCR(69, 0xe6050045),
+	PORTCR(70, 0xe6050046),
+	PORTCR(71, 0xe6050047),
+	PORTCR(72, 0xe6050048),
+	PORTCR(73, 0xe6050049),
+	PORTCR(74, 0xe605004A),
+	PORTCR(75, 0xe605004B),
+	PORTCR(76, 0xe605004C),
+	PORTCR(77, 0xe605004D),
+	PORTCR(78, 0xe605004E),
+	PORTCR(79, 0xe605004F),
+	PORTCR(80, 0xe6050050),
+	PORTCR(81, 0xe6050051),
+	PORTCR(82, 0xe6050052),
+	PORTCR(83, 0xe6050053),
+	PORTCR(84, 0xe6050054),
+	PORTCR(85, 0xe6050055),
+	PORTCR(96, 0xe6051060),
+	PORTCR(97, 0xe6051061),
+	PORTCR(98, 0xe6051062),
+	PORTCR(99, 0xe6051063),
+	PORTCR(100, 0xe6051064),
+	PORTCR(101, 0xe6051065),
+	PORTCR(102, 0xe6051066),
+	PORTCR(103, 0xe6051067),
+	PORTCR(104, 0xe6051068),
+	PORTCR(105, 0xe6051069),
+	PORTCR(106, 0xe605106A),
+	PORTCR(107, 0xe605106B),
+	PORTCR(108, 0xe605106C),
+	PORTCR(109, 0xe605106D),
+	PORTCR(110, 0xe605106E),
+	PORTCR(111, 0xe605106F),
+	PORTCR(112, 0xe6051070),
+	PORTCR(113, 0xe6051071),
+	PORTCR(114, 0xe6051072),
+	PORTCR(115, 0xe6051073),
+	PORTCR(116, 0xe6051074),
+	PORTCR(117, 0xe6051075),
+	PORTCR(118, 0xe6051076),
+	PORTCR(119, 0xe6051077),
+	PORTCR(120, 0xe6051078),
+	PORTCR(121, 0xe6051079),
+	PORTCR(122, 0xe605107A),
+	PORTCR(123, 0xe605107B),
+	PORTCR(124, 0xe605107C),
+	PORTCR(125, 0xe605107D),
+	PORTCR(126, 0xe605107E),
+	PORTCR(128, 0xe6051080),
+	PORTCR(129, 0xe6051081),
+	PORTCR(130, 0xe6051082),
+	PORTCR(131, 0xe6051083),
+	PORTCR(132, 0xe6051084),
+	PORTCR(133, 0xe6051085),
+	PORTCR(134, 0xe6051086),
+	PORTCR(160, 0xe60520A0),
+	PORTCR(161, 0xe60520A1),
+	PORTCR(162, 0xe60520A2),
+	PORTCR(163, 0xe60520A3),
+	PORTCR(164, 0xe60520A4),
+	PORTCR(165, 0xe60520A5),
+	PORTCR(166, 0xe60520A6),
+	PORTCR(167, 0xe60520A7),
+	PORTCR(168, 0xe60520A8),
+	PORTCR(169, 0xe60520A9),
+	PORTCR(170, 0xe60520AA),
+	PORTCR(171, 0xe60520AB),
+	PORTCR(172, 0xe60520AC),
+	PORTCR(173, 0xe60520AD),
+	PORTCR(174, 0xe60520AE),
+	PORTCR(175, 0xe60520AF),
+	PORTCR(176, 0xe60520B0),
+	PORTCR(177, 0xe60520B1),
+	PORTCR(178, 0xe60520B2),
+	PORTCR(192, 0xe60520C0),
+	PORTCR(193, 0xe60520C1),
+	PORTCR(194, 0xe60520C2),
+	PORTCR(195, 0xe60520C3),
+	PORTCR(196, 0xe60520C4),
+	PORTCR(197, 0xe60520C5),
+	PORTCR(198, 0xe60520C6),
+	PORTCR(199, 0xe60520C7),
+	PORTCR(200, 0xe60520C8),
+	PORTCR(201, 0xe60520C9),
+	PORTCR(202, 0xe60520CA),
+	PORTCR(203, 0xe60520CB),
+	PORTCR(204, 0xe60520CC),
+	PORTCR(205, 0xe60520CD),
+	PORTCR(206, 0xe60520CE),
+	PORTCR(207, 0xe60520CF),
+	PORTCR(208, 0xe60520D0),
+	PORTCR(209, 0xe60520D1),
+	PORTCR(210, 0xe60520D2),
+	PORTCR(211, 0xe60520D3),
+	PORTCR(212, 0xe60520D4),
+	PORTCR(213, 0xe60520D5),
+	PORTCR(214, 0xe60520D6),
+	PORTCR(215, 0xe60520D7),
+	PORTCR(216, 0xe60520D8),
+	PORTCR(217, 0xe60520D9),
+	PORTCR(218, 0xe60520DA),
+	PORTCR(219, 0xe60520DB),
+	PORTCR(220, 0xe60520DC),
+	PORTCR(221, 0xe60520DD),
+	PORTCR(222, 0xe60520DE),
+	PORTCR(224, 0xe60520E0),
+	PORTCR(225, 0xe60520E1),
+	PORTCR(226, 0xe60520E2),
+	PORTCR(227, 0xe60520E3),
+	PORTCR(228, 0xe60520E4),
+	PORTCR(229, 0xe60520E5),
+	PORTCR(230, 0xe60520e6),
+	PORTCR(231, 0xe60520E7),
+	PORTCR(232, 0xe60520E8),
+	PORTCR(233, 0xe60520E9),
+	PORTCR(234, 0xe60520EA),
+	PORTCR(235, 0xe60520EB),
+	PORTCR(236, 0xe60520EC),
+	PORTCR(237, 0xe60520ED),
+	PORTCR(238, 0xe60520EE),
+	PORTCR(239, 0xe60520EF),
+	PORTCR(240, 0xe60520F0),
+	PORTCR(241, 0xe60520F1),
+	PORTCR(242, 0xe60520F2),
+	PORTCR(243, 0xe60520F3),
+	PORTCR(244, 0xe60520F4),
+	PORTCR(245, 0xe60520F5),
+	PORTCR(246, 0xe60520F6),
+	PORTCR(247, 0xe60520F7),
+	PORTCR(248, 0xe60520F8),
+	PORTCR(249, 0xe60520F9),
+	PORTCR(250, 0xe60520FA),
+	PORTCR(256, 0xe6052100),
+	PORTCR(257, 0xe6052101),
+	PORTCR(258, 0xe6052102),
+	PORTCR(259, 0xe6052103),
+	PORTCR(260, 0xe6052104),
+	PORTCR(261, 0xe6052105),
+	PORTCR(262, 0xe6052106),
+	PORTCR(263, 0xe6052107),
+	PORTCR(264, 0xe6052108),
+	PORTCR(265, 0xe6052109),
+	PORTCR(266, 0xe605210A),
+	PORTCR(267, 0xe605210B),
+	PORTCR(268, 0xe605210C),
+	PORTCR(269, 0xe605210D),
+	PORTCR(270, 0xe605210E),
+	PORTCR(271, 0xe605210F),
+	PORTCR(272, 0xe6052110),
+	PORTCR(273, 0xe6052111),
+	PORTCR(274, 0xe6052112),
+	PORTCR(275, 0xe6052113),
+	PORTCR(276, 0xe6052114),
+	PORTCR(277, 0xe6052115),
+	PORTCR(278, 0xe6052116),
+	PORTCR(279, 0xe6052117),
+	PORTCR(280, 0xe6052118),
+	PORTCR(281, 0xe6052119),
+	PORTCR(282, 0xe605211A),
+	PORTCR(283, 0xe605211B),
+	PORTCR(288, 0xe6053120),
+	PORTCR(289, 0xe6053121),
+	PORTCR(290, 0xe6053122),
+	PORTCR(291, 0xe6053123),
+	PORTCR(292, 0xe6053124),
+	PORTCR(293, 0xe6053125),
+	PORTCR(294, 0xe6053126),
+	PORTCR(295, 0xe6053127),
+	PORTCR(296, 0xe6053128),
+	PORTCR(297, 0xe6053129),
+	PORTCR(298, 0xe605312A),
+	PORTCR(299, 0xe605312B),
+	PORTCR(300, 0xe605312C),
+	PORTCR(301, 0xe605312D),
+	PORTCR(302, 0xe605312E),
+	PORTCR(303, 0xe605312F),
+	PORTCR(304, 0xe6053130),
+	PORTCR(305, 0xe6053131),
+	PORTCR(306, 0xe6053132),
+	PORTCR(307, 0xe6053133),
+	PORTCR(308, 0xe6053134),
+	PORTCR(320, 0xe6053140),
+	PORTCR(321, 0xe6053141),
+	PORTCR(322, 0xe6053142),
+	PORTCR(323, 0xe6053143),
+	PORTCR(324, 0xe6053144),
+	PORTCR(325, 0xe6053145),
+	PORTCR(326, 0xe6053146),
+	PORTCR(327, 0xe6053147),
+	PORTCR(328, 0xe6053148),
+	PORTCR(329, 0xe6053149),
+
+	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+			MSEL1CR_31_0, MSEL1CR_31_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL1CR_27_0, MSEL1CR_27_1,
+			0, 0,
+			MSEL1CR_25_0, MSEL1CR_25_1,
+			MSEL1CR_24_0, MSEL1CR_24_1,
+			0, 0,
+			MSEL1CR_22_0, MSEL1CR_22_1,
+			MSEL1CR_21_0, MSEL1CR_21_1,
+			MSEL1CR_20_0, MSEL1CR_20_1,
+			MSEL1CR_19_0, MSEL1CR_19_1,
+			MSEL1CR_18_0, MSEL1CR_18_1,
+			MSEL1CR_17_0, MSEL1CR_17_1,
+			MSEL1CR_16_0, MSEL1CR_16_1,
+			MSEL1CR_15_0, MSEL1CR_15_1,
+			MSEL1CR_14_0, MSEL1CR_14_1,
+			MSEL1CR_13_0, MSEL1CR_13_1,
+			MSEL1CR_12_0, MSEL1CR_12_1,
+			MSEL1CR_11_0, MSEL1CR_11_1,
+			MSEL1CR_10_0, MSEL1CR_10_1,
+			MSEL1CR_09_0, MSEL1CR_09_1,
+			MSEL1CR_08_0, MSEL1CR_08_1,
+			MSEL1CR_07_0, MSEL1CR_07_1,
+			MSEL1CR_06_0, MSEL1CR_06_1,
+			MSEL1CR_05_0, MSEL1CR_05_1,
+			MSEL1CR_04_0, MSEL1CR_04_1,
+			MSEL1CR_03_0, MSEL1CR_03_1,
+			MSEL1CR_02_0, MSEL1CR_02_1,
+			MSEL1CR_01_0, MSEL1CR_01_1,
+			MSEL1CR_00_0, MSEL1CR_00_1,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+			MSEL3CR_31_0, MSEL3CR_31_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_28_0, MSEL3CR_28_1,
+			MSEL3CR_27_0, MSEL3CR_27_1,
+			MSEL3CR_26_0, MSEL3CR_26_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_23_0, MSEL3CR_23_1,
+			MSEL3CR_22_0, MSEL3CR_22_1,
+			MSEL3CR_21_0, MSEL3CR_21_1,
+			MSEL3CR_20_0, MSEL3CR_20_1,
+			MSEL3CR_19_0, MSEL3CR_19_1,
+			MSEL3CR_18_0, MSEL3CR_18_1,
+			MSEL3CR_17_0, MSEL3CR_17_1,
+			MSEL3CR_16_0, MSEL3CR_16_1,
+			MSEL3CR_15_0, MSEL3CR_15_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_12_0, MSEL3CR_12_1,
+			MSEL3CR_11_0, MSEL3CR_11_1,
+			MSEL3CR_10_0, MSEL3CR_10_1,
+			MSEL3CR_09_0, MSEL3CR_09_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_06_0, MSEL3CR_06_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_03_0, MSEL3CR_03_1,
+			0, 0,
+			MSEL3CR_01_0, MSEL3CR_01_1,
+			MSEL3CR_00_0, MSEL3CR_00_1,
+			}
+	},
+	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+			0, 0,
+			MSEL4CR_30_0, MSEL4CR_30_1,
+			MSEL4CR_29_0, MSEL4CR_29_1,
+			MSEL4CR_28_0, MSEL4CR_28_1,
+			MSEL4CR_27_0, MSEL4CR_27_1,
+			MSEL4CR_26_0, MSEL4CR_26_1,
+			MSEL4CR_25_0, MSEL4CR_25_1,
+			MSEL4CR_24_0, MSEL4CR_24_1,
+			MSEL4CR_23_0, MSEL4CR_23_1,
+			MSEL4CR_22_0, MSEL4CR_22_1,
+			MSEL4CR_21_0, MSEL4CR_21_1,
+			MSEL4CR_20_0, MSEL4CR_20_1,
+			MSEL4CR_19_0, MSEL4CR_19_1,
+			MSEL4CR_18_0, MSEL4CR_18_1,
+			MSEL4CR_17_0, MSEL4CR_17_1,
+			MSEL4CR_16_0, MSEL4CR_16_1,
+			MSEL4CR_15_0, MSEL4CR_15_1,
+			MSEL4CR_14_0, MSEL4CR_14_1,
+			MSEL4CR_13_0, MSEL4CR_13_1,
+			MSEL4CR_12_0, MSEL4CR_12_1,
+			MSEL4CR_11_0, MSEL4CR_11_1,
+			MSEL4CR_10_0, MSEL4CR_10_1,
+			MSEL4CR_09_0, MSEL4CR_09_1,
+			0, 0,
+			MSEL4CR_07_0, MSEL4CR_07_1,
+			0, 0,
+			0, 0,
+			MSEL4CR_04_0, MSEL4CR_04_1,
+			0, 0,
+			0, 0,
+			MSEL4CR_01_0, MSEL4CR_01_1,
+			0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
+			MSEL5CR_31_0, MSEL5CR_31_1,
+			MSEL5CR_30_0, MSEL5CR_30_1,
+			MSEL5CR_29_0, MSEL5CR_29_1,
+			MSEL5CR_28_0, MSEL5CR_28_1,
+			MSEL5CR_27_0, MSEL5CR_27_1,
+			MSEL5CR_26_0, MSEL5CR_26_1,
+			MSEL5CR_25_0, MSEL5CR_25_1,
+			MSEL5CR_24_0, MSEL5CR_24_1,
+			MSEL5CR_23_0, MSEL5CR_23_1,
+			MSEL5CR_22_0, MSEL5CR_22_1,
+			MSEL5CR_21_0, MSEL5CR_21_1,
+			MSEL5CR_20_0, MSEL5CR_20_1,
+			MSEL5CR_19_0, MSEL5CR_19_1,
+			MSEL5CR_18_0, MSEL5CR_18_1,
+			MSEL5CR_17_0, MSEL5CR_17_1,
+			MSEL5CR_16_0, MSEL5CR_16_1,
+			MSEL5CR_15_0, MSEL5CR_15_1,
+			MSEL5CR_14_0, MSEL5CR_14_1,
+			MSEL5CR_13_0, MSEL5CR_13_1,
+			MSEL5CR_12_0, MSEL5CR_12_1,
+			MSEL5CR_11_0, MSEL5CR_11_1,
+			MSEL5CR_10_0, MSEL5CR_10_1,
+			MSEL5CR_09_0, MSEL5CR_09_1,
+			MSEL5CR_08_0, MSEL5CR_08_1,
+			MSEL5CR_07_0, MSEL5CR_07_1,
+			MSEL5CR_06_0, MSEL5CR_06_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL8CR_16_0, MSEL8CR_16_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL8CR_01_0, MSEL8CR_01_1,
+			MSEL8CR_00_0, MSEL8CR_00_1,
+		}
+	},
+	{ },
+};
+
+static const struct pinmux_data_reg pinmux_data_regs[] = {
+
+	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+			0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, PORT40_DATA,
+			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, PORT85_DATA, PORT84_DATA,
+			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
+			0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+			PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+			PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+			PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+			PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+			PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
+			0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
+			0, 0, 0, 0,
+			0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
+			0, 0, 0, 0,
+			PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, PORT308_DATA,
+			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
+		}
+	},
+	{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, PORT329_DATA, PORT328_DATA,
+			PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
+			PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
+		}
+	},
+	{ },
+};
+
+const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
+	.name		= "r8a73a4_pfc",
+
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.func_gpios = pinmux_func_gpios,
+	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
+
+	.cfg_regs	= pinmux_config_regs,
+	.data_regs	= pinmux_data_regs,
+
+	.gpio_data	= pinmux_data,
+	.gpio_data_size	= ARRAY_SIZE(pinmux_data),
+};
-- 
1.7.10.4

[PATCH 17/28] sh-pfc: r8a73a4: Support sparse GPIO numbers

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          |   16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f0b1b4a..2d4af4a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -86,7 +86,7 @@ enum {
 	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
 
 	/* Port0 */
-	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
 	GPIO_FN_IRQ0,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 47d75d5..5dd68fb9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1424,6 +1424,20 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+static const struct pinmux_range pinmux_ranges[] = {
+	{.begin = 0, .end = 30,},
+	{.begin = 32, .end = 40,},
+	{.begin = 64, .end = 85,},
+	{.begin = 96, .end = 126,},
+	{.begin = 128, .end = 134,},
+	{.begin = 160, .end = 178,},
+	{.begin = 192, .end = 222,},
+	{.begin = 224, .end = 250,},
+	{.begin = 256, .end = 283,},
+	{.begin = 288, .end = 308,},
+	{.begin = 320, .end = 329,},
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -2815,6 +2829,8 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.ranges = pinmux_ranges,
+	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4

[PATCH 17/28] sh-pfc: r8a73a4: Support sparse GPIO numbers

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          |   16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f0b1b4a..2d4af4a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -86,7 +86,7 @@ enum {
 	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
 
 	/* Port0 */
-	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
 	GPIO_FN_IRQ0,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 47d75d5..5dd68fb9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1424,6 +1424,20 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+static const struct pinmux_range pinmux_ranges[] = {
+	{.begin = 0, .end = 30,},
+	{.begin = 32, .end = 40,},
+	{.begin = 64, .end = 85,},
+	{.begin = 96, .end = 126,},
+	{.begin = 128, .end = 134,},
+	{.begin = 160, .end = 178,},
+	{.begin = 192, .end = 222,},
+	{.begin = 224, .end = 250,},
+	{.begin = 256, .end = 283,},
+	{.begin = 288, .end = 308,},
+	{.begin = 320, .end = 329,},
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -2815,6 +2829,8 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.ranges = pinmux_ranges,
+	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4

[PATCH 18/28] sh-pfc: r8a73a4: GPIO IRQ support

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   63 ++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 5dd68fb9..0177329 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2818,6 +2818,66 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 	{ },
 };
 
+static const struct pinmux_irq pinmux_irqs[] = {
+	PINMUX_IRQ(irq_pin(0), 0),
+	PINMUX_IRQ(irq_pin(1), 1),
+	PINMUX_IRQ(irq_pin(2), 2),
+	PINMUX_IRQ(irq_pin(3), 3),
+	PINMUX_IRQ(irq_pin(4), 4),
+	PINMUX_IRQ(irq_pin(5), 5),
+	PINMUX_IRQ(irq_pin(6), 6),
+	PINMUX_IRQ(irq_pin(7), 7),
+	PINMUX_IRQ(irq_pin(8), 8),
+	PINMUX_IRQ(irq_pin(9), 9),
+	PINMUX_IRQ(irq_pin(10), 10),
+	PINMUX_IRQ(irq_pin(11), 11),
+	PINMUX_IRQ(irq_pin(12), 12),
+	PINMUX_IRQ(irq_pin(13), 13),
+	PINMUX_IRQ(irq_pin(14), 14),
+	PINMUX_IRQ(irq_pin(15), 15),
+	PINMUX_IRQ(irq_pin(16), 320),
+	PINMUX_IRQ(irq_pin(17), 321),
+	PINMUX_IRQ(irq_pin(18), 85),
+	PINMUX_IRQ(irq_pin(19), 84),
+	PINMUX_IRQ(irq_pin(20), 160),
+	PINMUX_IRQ(irq_pin(21), 161),
+	PINMUX_IRQ(irq_pin(22), 162),
+	PINMUX_IRQ(irq_pin(23), 163),
+	PINMUX_IRQ(irq_pin(24), 175),
+	PINMUX_IRQ(irq_pin(25), 176),
+	PINMUX_IRQ(irq_pin(26), 177),
+	PINMUX_IRQ(irq_pin(27), 178),
+	PINMUX_IRQ(irq_pin(28), 322),
+	PINMUX_IRQ(irq_pin(29), 323),
+	PINMUX_IRQ(irq_pin(30), 324),
+	PINMUX_IRQ(irq_pin(31), 192),
+	PINMUX_IRQ(irq_pin(32), 193),
+	PINMUX_IRQ(irq_pin(33), 194),
+	PINMUX_IRQ(irq_pin(34), 195),
+	PINMUX_IRQ(irq_pin(35), 196),
+	PINMUX_IRQ(irq_pin(36), 197),
+	PINMUX_IRQ(irq_pin(37), 198),
+	PINMUX_IRQ(irq_pin(38), 199),
+	PINMUX_IRQ(irq_pin(39), 200),
+	PINMUX_IRQ(irq_pin(40), 66),
+	PINMUX_IRQ(irq_pin(41), 102),
+	PINMUX_IRQ(irq_pin(42), 103),
+	PINMUX_IRQ(irq_pin(43), 109),
+	PINMUX_IRQ(irq_pin(44), 110),
+	PINMUX_IRQ(irq_pin(45), 111),
+	PINMUX_IRQ(irq_pin(46), 112),
+	PINMUX_IRQ(irq_pin(47), 113),
+	PINMUX_IRQ(irq_pin(48), 114),
+	PINMUX_IRQ(irq_pin(49), 115),
+	PINMUX_IRQ(irq_pin(50), 301),
+	PINMUX_IRQ(irq_pin(51), 290),
+	PINMUX_IRQ(irq_pin(52), 296),
+	PINMUX_IRQ(irq_pin(53), 325),
+	PINMUX_IRQ(irq_pin(54), 326),
+	PINMUX_IRQ(irq_pin(55), 327),
+	PINMUX_IRQ(irq_pin(56), 328),
+	PINMUX_IRQ(irq_pin(57), 329),
+};
 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.name		= "r8a73a4_pfc",
 
@@ -2839,4 +2899,7 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.gpio_data	= pinmux_data,
 	.gpio_data_size	= ARRAY_SIZE(pinmux_data),
+
+	.gpio_irq = pinmux_irqs,
+	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
 };
-- 
1.7.10.4

[PATCH 18/28] sh-pfc: r8a73a4: GPIO IRQ support

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   63 ++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 5dd68fb9..0177329 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2818,6 +2818,66 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 	{ },
 };
 
+static const struct pinmux_irq pinmux_irqs[] = {
+	PINMUX_IRQ(irq_pin(0), 0),
+	PINMUX_IRQ(irq_pin(1), 1),
+	PINMUX_IRQ(irq_pin(2), 2),
+	PINMUX_IRQ(irq_pin(3), 3),
+	PINMUX_IRQ(irq_pin(4), 4),
+	PINMUX_IRQ(irq_pin(5), 5),
+	PINMUX_IRQ(irq_pin(6), 6),
+	PINMUX_IRQ(irq_pin(7), 7),
+	PINMUX_IRQ(irq_pin(8), 8),
+	PINMUX_IRQ(irq_pin(9), 9),
+	PINMUX_IRQ(irq_pin(10), 10),
+	PINMUX_IRQ(irq_pin(11), 11),
+	PINMUX_IRQ(irq_pin(12), 12),
+	PINMUX_IRQ(irq_pin(13), 13),
+	PINMUX_IRQ(irq_pin(14), 14),
+	PINMUX_IRQ(irq_pin(15), 15),
+	PINMUX_IRQ(irq_pin(16), 320),
+	PINMUX_IRQ(irq_pin(17), 321),
+	PINMUX_IRQ(irq_pin(18), 85),
+	PINMUX_IRQ(irq_pin(19), 84),
+	PINMUX_IRQ(irq_pin(20), 160),
+	PINMUX_IRQ(irq_pin(21), 161),
+	PINMUX_IRQ(irq_pin(22), 162),
+	PINMUX_IRQ(irq_pin(23), 163),
+	PINMUX_IRQ(irq_pin(24), 175),
+	PINMUX_IRQ(irq_pin(25), 176),
+	PINMUX_IRQ(irq_pin(26), 177),
+	PINMUX_IRQ(irq_pin(27), 178),
+	PINMUX_IRQ(irq_pin(28), 322),
+	PINMUX_IRQ(irq_pin(29), 323),
+	PINMUX_IRQ(irq_pin(30), 324),
+	PINMUX_IRQ(irq_pin(31), 192),
+	PINMUX_IRQ(irq_pin(32), 193),
+	PINMUX_IRQ(irq_pin(33), 194),
+	PINMUX_IRQ(irq_pin(34), 195),
+	PINMUX_IRQ(irq_pin(35), 196),
+	PINMUX_IRQ(irq_pin(36), 197),
+	PINMUX_IRQ(irq_pin(37), 198),
+	PINMUX_IRQ(irq_pin(38), 199),
+	PINMUX_IRQ(irq_pin(39), 200),
+	PINMUX_IRQ(irq_pin(40), 66),
+	PINMUX_IRQ(irq_pin(41), 102),
+	PINMUX_IRQ(irq_pin(42), 103),
+	PINMUX_IRQ(irq_pin(43), 109),
+	PINMUX_IRQ(irq_pin(44), 110),
+	PINMUX_IRQ(irq_pin(45), 111),
+	PINMUX_IRQ(irq_pin(46), 112),
+	PINMUX_IRQ(irq_pin(47), 113),
+	PINMUX_IRQ(irq_pin(48), 114),
+	PINMUX_IRQ(irq_pin(49), 115),
+	PINMUX_IRQ(irq_pin(50), 301),
+	PINMUX_IRQ(irq_pin(51), 290),
+	PINMUX_IRQ(irq_pin(52), 296),
+	PINMUX_IRQ(irq_pin(53), 325),
+	PINMUX_IRQ(irq_pin(54), 326),
+	PINMUX_IRQ(irq_pin(55), 327),
+	PINMUX_IRQ(irq_pin(56), 328),
+	PINMUX_IRQ(irq_pin(57), 329),
+};
 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.name		= "r8a73a4_pfc",
 
@@ -2839,4 +2899,7 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.gpio_data	= pinmux_data,
 	.gpio_data_size	= ARRAY_SIZE(pinmux_data),
+
+	.gpio_irq = pinmux_irqs,
+	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
 };
-- 
1.7.10.4

[PATCH 19/28] sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  197 +++++++++++++++++++++++++++++++++-
 1 file changed, 196 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 0177329..86a5fd3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -17,10 +17,13 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)					\
@@ -1420,8 +1423,143 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
 };
 
+#define R8A73A4_PIN(pin, cfgs)			\
+	{					\
+		.name = __stringify(PORT##pin),	\
+		.enum_id = PORT##pin##_DATA,	\
+		.configs = cfgs,		\
+	}
+
+#define __O	(SH_PFC_PIN_CFG_OUTPUT)
+#define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PUD	(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A73A4_PIN_IO_PU_PD(pin)       R8A73A4_PIN(pin, __IO | __PUD)
+#define R8A73A4_PIN_O(pin)              R8A73A4_PIN(pin, __O)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-	GPIO_PORT_ALL(),
+	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
+	R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
+	R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
+	R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
+	R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
+	R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
+	R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
+	R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
+	R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
+	R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
+	R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
+	R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
+	R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
+	R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
+	R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
+	R8A73A4_PIN_IO_PU_PD(30),
+	R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
+	R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
+	R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
+	R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
+	R8A73A4_PIN_IO_PU_PD(40),
+	R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
+	R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
+	R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
+	R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
+	R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
+	R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
+	R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
+	R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
+	R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
+	R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
+	R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
+	R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
+	R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
+	R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
+	R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
+	R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
+	R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
+	R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
+	R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
+	R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
+	R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
+	R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
+	R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
+	R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
+	R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
+	R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
+	R8A73A4_PIN_IO_PU_PD(126),
+	R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
+	R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
+	R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
+	R8A73A4_PIN_IO_PU_PD(134),
+	R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
+	R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
+	R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
+	R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
+	R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
+	R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
+	R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
+	R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
+	R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
+	R8A73A4_PIN_IO_PU_PD(178),
+	R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
+	R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
+	R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
+	R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
+	R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
+	R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
+	R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
+	R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
+	R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
+	R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
+	R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
+	R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
+	R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
+	R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
+	R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
+	R8A73A4_PIN_IO_PU_PD(222),
+	R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
+	R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
+	R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
+	R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
+	R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
+	R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
+	R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
+	R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
+	R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
+	R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
+	R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
+	R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
+	R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
+	R8A73A4_PIN_IO_PU_PD(250),
+	R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
+	R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
+	R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
+	R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
+	R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
+	R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
+	R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
+	R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
+	R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
+	R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
+	R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
+	R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
+	R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
+	R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
+	R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
+	R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
+	R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
+	R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
+	R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
+	R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
+	R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
+	R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
+	R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
+	R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
+	R8A73A4_PIN_IO_PU_PD(308),
+	R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
+	R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
+	R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
+	R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
+	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
 };
 
 static const struct pinmux_range pinmux_ranges[] = {
@@ -2878,8 +3016,65 @@ static const struct pinmux_irq pinmux_irqs[] = {
 	PINMUX_IRQ(irq_pin(56), 328),
 	PINMUX_IRQ(irq_pin(57), 329),
 };
+
+#define PORTCR_PULMD_OFF (0 << 6)
+#define PORTCR_PULMD_DOWN (2 << 6)
+#define PORTCR_PULMD_UP (3 << 6)
+#define PORTCR_PULMD_MASK (3 << 6)
+
+static const unsigned int r8a73a4_portcr_offsets[] = {
+	0x00000000, 0x00001000, 0x00000000, 0x00001000,
+	0x00001000, 0x00002000, 0x00002000, 0x00002000,
+	0x00002000, 0x00003000, 0x00003000,
+};
+
+static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
+					    unsigned int pin)
+{
+	void __iomem *addr;
+
+	addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+
+	switch (ioread8(addr) & PORTCR_PULMD_MASK) {
+	case PORTCR_PULMD_UP:
+		return PIN_CONFIG_BIAS_PULL_UP;
+	case PORTCR_PULMD_DOWN:
+		return PIN_CONFIG_BIAS_PULL_DOWN;
+	case PORTCR_PULMD_OFF:
+	default:
+		return PIN_CONFIG_BIAS_DISABLE;
+	}
+}
+
+static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+				   unsigned int bias)
+{
+	void __iomem *addr;
+	u32 value;
+
+	addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+	value = ioread8(addr) & ~PORTCR_PULMD_MASK;
+
+	switch (bias) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+		value |= PORTCR_PULMD_UP;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		value |= PORTCR_PULMD_DOWN;
+		break;
+	}
+
+	iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
+	.get_bias = r8a73a4_pinmux_get_bias,
+	.set_bias = r8a73a4_pinmux_set_bias,
+};
+
 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.name		= "r8a73a4_pfc",
+	.ops		= &r8a73a4_pinmux_ops,
 
 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
 	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-- 
1.7.10.4

[PATCH 19/28] sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  197 +++++++++++++++++++++++++++++++++-
 1 file changed, 196 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 0177329..86a5fd3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -17,10 +17,13 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)					\
@@ -1420,8 +1423,143 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
 };
 
+#define R8A73A4_PIN(pin, cfgs)			\
+	{					\
+		.name = __stringify(PORT##pin),	\
+		.enum_id = PORT##pin##_DATA,	\
+		.configs = cfgs,		\
+	}
+
+#define __O	(SH_PFC_PIN_CFG_OUTPUT)
+#define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PUD	(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A73A4_PIN_IO_PU_PD(pin)       R8A73A4_PIN(pin, __IO | __PUD)
+#define R8A73A4_PIN_O(pin)              R8A73A4_PIN(pin, __O)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-	GPIO_PORT_ALL(),
+	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
+	R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
+	R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
+	R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
+	R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
+	R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
+	R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
+	R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
+	R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
+	R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
+	R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
+	R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
+	R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
+	R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
+	R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
+	R8A73A4_PIN_IO_PU_PD(30),
+	R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
+	R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
+	R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
+	R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
+	R8A73A4_PIN_IO_PU_PD(40),
+	R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
+	R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
+	R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
+	R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
+	R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
+	R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
+	R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
+	R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
+	R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
+	R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
+	R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
+	R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
+	R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
+	R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
+	R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
+	R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
+	R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
+	R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
+	R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
+	R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
+	R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
+	R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
+	R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
+	R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
+	R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
+	R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
+	R8A73A4_PIN_IO_PU_PD(126),
+	R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
+	R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
+	R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
+	R8A73A4_PIN_IO_PU_PD(134),
+	R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
+	R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
+	R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
+	R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
+	R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
+	R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
+	R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
+	R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
+	R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
+	R8A73A4_PIN_IO_PU_PD(178),
+	R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
+	R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
+	R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
+	R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
+	R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
+	R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
+	R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
+	R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
+	R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
+	R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
+	R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
+	R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
+	R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
+	R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
+	R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
+	R8A73A4_PIN_IO_PU_PD(222),
+	R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
+	R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
+	R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
+	R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
+	R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
+	R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
+	R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
+	R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
+	R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
+	R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
+	R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
+	R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
+	R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
+	R8A73A4_PIN_IO_PU_PD(250),
+	R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
+	R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
+	R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
+	R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
+	R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
+	R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
+	R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
+	R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
+	R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
+	R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
+	R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
+	R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
+	R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
+	R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
+	R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
+	R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
+	R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
+	R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
+	R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
+	R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
+	R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
+	R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
+	R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
+	R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
+	R8A73A4_PIN_IO_PU_PD(308),
+	R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
+	R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
+	R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
+	R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
+	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
 };
 
 static const struct pinmux_range pinmux_ranges[] = {
@@ -2878,8 +3016,65 @@ static const struct pinmux_irq pinmux_irqs[] = {
 	PINMUX_IRQ(irq_pin(56), 328),
 	PINMUX_IRQ(irq_pin(57), 329),
 };
+
+#define PORTCR_PULMD_OFF (0 << 6)
+#define PORTCR_PULMD_DOWN (2 << 6)
+#define PORTCR_PULMD_UP (3 << 6)
+#define PORTCR_PULMD_MASK (3 << 6)
+
+static const unsigned int r8a73a4_portcr_offsets[] = {
+	0x00000000, 0x00001000, 0x00000000, 0x00001000,
+	0x00001000, 0x00002000, 0x00002000, 0x00002000,
+	0x00002000, 0x00003000, 0x00003000,
+};
+
+static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
+					    unsigned int pin)
+{
+	void __iomem *addr;
+
+	addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+
+	switch (ioread8(addr) & PORTCR_PULMD_MASK) {
+	case PORTCR_PULMD_UP:
+		return PIN_CONFIG_BIAS_PULL_UP;
+	case PORTCR_PULMD_DOWN:
+		return PIN_CONFIG_BIAS_PULL_DOWN;
+	case PORTCR_PULMD_OFF:
+	default:
+		return PIN_CONFIG_BIAS_DISABLE;
+	}
+}
+
+static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+				   unsigned int bias)
+{
+	void __iomem *addr;
+	u32 value;
+
+	addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+	value = ioread8(addr) & ~PORTCR_PULMD_MASK;
+
+	switch (bias) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+		value |= PORTCR_PULMD_UP;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		value |= PORTCR_PULMD_DOWN;
+		break;
+	}
+
+	iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
+	.get_bias = r8a73a4_pinmux_get_bias,
+	.set_bias = r8a73a4_pinmux_set_bias,
+};
+
 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.name		= "r8a73a4_pfc",
+	.ops		= &r8a73a4_pinmux_ops,
 
 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
 	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-- 
1.7.10.4

[PATCH 20/28] sh-pfc: r8a73a4: Add SCIF pin groups and functions

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and
SCIFB0->SCIFB3.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  287 ++++++++++++++++++++++++++++++++++
 1 file changed, 287 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 86a5fd3..cd5c5fd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1576,6 +1576,286 @@ static const struct pinmux_range pinmux_ranges[] = {
 	{.begin = 320, .end = 329,},
 };
 
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+	/* SCIFA0_RXD, SCIFA0_TXD */
+	117, 116,
+};
+static const unsigned int scifa0_data_mux[] = {
+	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+	/* SCIFA0_SCK */
+	34,
+};
+static const unsigned int scifa0_clk_mux[] = {
+	SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+	/* SCIFA0_RTS, SCIFA0_CTS */
+	32, 33,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+	/* SCIFA1_RXD, SCIFA1_TXD */
+	119, 118,
+};
+static const unsigned int scifa1_data_mux[] = {
+	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+	/* SCIFA1_SCK */
+	37,
+};
+static const unsigned int scifa1_clk_mux[] = {
+	SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+	/* SCIFA1_RTS, SCIFA1_CTS */
+	35, 36,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+	/* SCIFB0_RXD, SCIFB0_TXD */
+	123, 122,
+};
+static const unsigned int scifb0_data_mux[] = {
+	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+	/* SCIFB0_SCK */
+	40,
+};
+static const unsigned int scifb0_clk_mux[] = {
+	SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+	/* SCIFB0_RTS, SCIFB0_CTS */
+	38, 39,
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+	SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+	/* SCIFB1_RXD, SCIFB1_TXD */
+	27, 26,
+};
+static const unsigned int scifb1_data_mux[] = {
+	SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+	/* SCIFB1_SCK */
+	28,
+};
+static const unsigned int scifb1_clk_mux[] = {
+	SCIFB1_SCK_28_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+	/* SCIFB1_RTS, SCIFB1_CTS */
+	24, 25,
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+	SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+	/* SCIFB1_RXD, SCIFB1_TXD */
+	72, 67,
+};
+static const unsigned int scifb1_data_b_mux[] = {
+	SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+	/* SCIFB1_SCK */
+	261,
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+	SCIFB1_SCK_261_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+	/* SCIFB1_RTS, SCIFB1_CTS */
+	70, 71,
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+	SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+	/* SCIFB2_RXD, SCIFB2_TXD */
+	69, 68,
+};
+static const unsigned int scifb2_data_mux[] = {
+	SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+	/* SCIFB2_SCK */
+	262,
+};
+static const unsigned int scifb2_clk_mux[] = {
+	SCIFB2_SCK_262_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+	/* SCIFB2_RTS, SCIFB2_CTS */
+	73, 66,
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+	SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+	/* SCIFB2_RXD, SCIFB2_TXD */
+	297, 295,
+};
+static const unsigned int scifb2_data_b_mux[] = {
+	SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+	/* SCIFB2_SCK */
+	299,
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+	SCIFB2_SCK_299_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+	/* SCIFB2_RTS, SCIFB2_CTS */
+	300, 298,
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+	SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
+};
+/* - SCIFB3 ----------------------------------------------------------------- */
+static const unsigned int scifb3_data_pins[] = {
+	/* SCIFB3_RXD, SCIFB3_TXD */
+	22, 21,
+};
+static const unsigned int scifb3_data_mux[] = {
+	SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
+};
+static const unsigned int scifb3_clk_pins[] = {
+	/* SCIFB3_SCK */
+	23,
+};
+static const unsigned int scifb3_clk_mux[] = {
+	SCIFB3_SCK_23_MARK,
+};
+static const unsigned int scifb3_ctrl_pins[] = {
+	/* SCIFB3_RTS, SCIFB3_CTS */
+	19, 20,
+};
+static const unsigned int scifb3_ctrl_mux[] = {
+	SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
+};
+static const unsigned int scifb3_data_b_pins[] = {
+	/* SCIFB3_RXD, SCIFB3_TXD */
+	120, 121,
+};
+static const unsigned int scifb3_data_b_mux[] = {
+	SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
+};
+static const unsigned int scifb3_clk_b_pins[] = {
+	/* SCIFB3_SCK */
+	40,
+};
+static const unsigned int scifb3_clk_b_mux[] = {
+	SCIFB3_SCK_40_MARK,
+};
+static const unsigned int scifb3_ctrl_b_pins[] = {
+	/* SCIFB3_RTS, SCIFB3_CTS */
+	38, 39,
+};
+static const unsigned int scifb3_ctrl_b_mux[] = {
+	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(scifa0_data),
+	SH_PFC_PIN_GROUP(scifa0_clk),
+	SH_PFC_PIN_GROUP(scifa0_ctrl),
+	SH_PFC_PIN_GROUP(scifa1_data),
+	SH_PFC_PIN_GROUP(scifa1_clk),
+	SH_PFC_PIN_GROUP(scifa1_ctrl),
+	SH_PFC_PIN_GROUP(scifb0_data),
+	SH_PFC_PIN_GROUP(scifb0_clk),
+	SH_PFC_PIN_GROUP(scifb0_ctrl),
+	SH_PFC_PIN_GROUP(scifb1_data),
+	SH_PFC_PIN_GROUP(scifb1_clk),
+	SH_PFC_PIN_GROUP(scifb1_ctrl),
+	SH_PFC_PIN_GROUP(scifb1_data_b),
+	SH_PFC_PIN_GROUP(scifb1_clk_b),
+	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb2_data),
+	SH_PFC_PIN_GROUP(scifb2_clk),
+	SH_PFC_PIN_GROUP(scifb2_ctrl),
+	SH_PFC_PIN_GROUP(scifb2_data_b),
+	SH_PFC_PIN_GROUP(scifb2_clk_b),
+	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb3_data),
+	SH_PFC_PIN_GROUP(scifb3_clk),
+	SH_PFC_PIN_GROUP(scifb3_ctrl),
+	SH_PFC_PIN_GROUP(scifb3_data_b),
+	SH_PFC_PIN_GROUP(scifb3_clk_b),
+	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
+};
+
+static const char * const scifa0_groups[] = {
+	"scifa0_data",
+	"scifa0_clk",
+	"scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+	"scifa1_data",
+	"scifa1_clk",
+	"scifa1_ctrl",
+};
+
+static const char * const scifb0_groups[] = {
+	"scifb0_data",
+	"scifb0_clk",
+	"scifb0_ctrl",
+};
+
+static const char * const scifb1_groups[] = {
+	"scifb1_data",
+	"scifb1_clk",
+	"scifb1_ctrl",
+	"scifb1_data_b",
+	"scifb1_clk_b",
+	"scifb1_ctrl_b",
+};
+
+static const char * const scifb2_groups[] = {
+	"scifb2_data",
+	"scifb2_clk",
+	"scifb2_ctrl",
+	"scifb2_data_b",
+	"scifb2_clk_b",
+	"scifb2_ctrl_b",
+};
+
+static const char * const scifb3_groups[] = {
+	"scifb3_data",
+	"scifb3_clk",
+	"scifb3_ctrl",
+	"scifb3_data_b",
+	"scifb3_clk_b",
+	"scifb3_ctrl_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scifa0),
+	SH_PFC_FUNCTION(scifa1),
+	SH_PFC_FUNCTION(scifb0),
+	SH_PFC_FUNCTION(scifb1),
+	SH_PFC_FUNCTION(scifb2),
+	SH_PFC_FUNCTION(scifb3),
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -3084,8 +3364,15 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+
 	.ranges = pinmux_ranges,
 	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
+
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4

[PATCH 20/28] sh-pfc: r8a73a4: Add SCIF pin groups and functions

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and
SCIFB0->SCIFB3.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  287 ++++++++++++++++++++++++++++++++++
 1 file changed, 287 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 86a5fd3..cd5c5fd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1576,6 +1576,286 @@ static const struct pinmux_range pinmux_ranges[] = {
 	{.begin = 320, .end = 329,},
 };
 
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+	/* SCIFA0_RXD, SCIFA0_TXD */
+	117, 116,
+};
+static const unsigned int scifa0_data_mux[] = {
+	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+	/* SCIFA0_SCK */
+	34,
+};
+static const unsigned int scifa0_clk_mux[] = {
+	SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+	/* SCIFA0_RTS, SCIFA0_CTS */
+	32, 33,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+	/* SCIFA1_RXD, SCIFA1_TXD */
+	119, 118,
+};
+static const unsigned int scifa1_data_mux[] = {
+	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+	/* SCIFA1_SCK */
+	37,
+};
+static const unsigned int scifa1_clk_mux[] = {
+	SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+	/* SCIFA1_RTS, SCIFA1_CTS */
+	35, 36,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+	/* SCIFB0_RXD, SCIFB0_TXD */
+	123, 122,
+};
+static const unsigned int scifb0_data_mux[] = {
+	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+	/* SCIFB0_SCK */
+	40,
+};
+static const unsigned int scifb0_clk_mux[] = {
+	SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+	/* SCIFB0_RTS, SCIFB0_CTS */
+	38, 39,
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+	SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+	/* SCIFB1_RXD, SCIFB1_TXD */
+	27, 26,
+};
+static const unsigned int scifb1_data_mux[] = {
+	SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+	/* SCIFB1_SCK */
+	28,
+};
+static const unsigned int scifb1_clk_mux[] = {
+	SCIFB1_SCK_28_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+	/* SCIFB1_RTS, SCIFB1_CTS */
+	24, 25,
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+	SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+	/* SCIFB1_RXD, SCIFB1_TXD */
+	72, 67,
+};
+static const unsigned int scifb1_data_b_mux[] = {
+	SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+	/* SCIFB1_SCK */
+	261,
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+	SCIFB1_SCK_261_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+	/* SCIFB1_RTS, SCIFB1_CTS */
+	70, 71,
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+	SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+	/* SCIFB2_RXD, SCIFB2_TXD */
+	69, 68,
+};
+static const unsigned int scifb2_data_mux[] = {
+	SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+	/* SCIFB2_SCK */
+	262,
+};
+static const unsigned int scifb2_clk_mux[] = {
+	SCIFB2_SCK_262_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+	/* SCIFB2_RTS, SCIFB2_CTS */
+	73, 66,
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+	SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+	/* SCIFB2_RXD, SCIFB2_TXD */
+	297, 295,
+};
+static const unsigned int scifb2_data_b_mux[] = {
+	SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+	/* SCIFB2_SCK */
+	299,
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+	SCIFB2_SCK_299_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+	/* SCIFB2_RTS, SCIFB2_CTS */
+	300, 298,
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+	SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
+};
+/* - SCIFB3 ----------------------------------------------------------------- */
+static const unsigned int scifb3_data_pins[] = {
+	/* SCIFB3_RXD, SCIFB3_TXD */
+	22, 21,
+};
+static const unsigned int scifb3_data_mux[] = {
+	SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
+};
+static const unsigned int scifb3_clk_pins[] = {
+	/* SCIFB3_SCK */
+	23,
+};
+static const unsigned int scifb3_clk_mux[] = {
+	SCIFB3_SCK_23_MARK,
+};
+static const unsigned int scifb3_ctrl_pins[] = {
+	/* SCIFB3_RTS, SCIFB3_CTS */
+	19, 20,
+};
+static const unsigned int scifb3_ctrl_mux[] = {
+	SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
+};
+static const unsigned int scifb3_data_b_pins[] = {
+	/* SCIFB3_RXD, SCIFB3_TXD */
+	120, 121,
+};
+static const unsigned int scifb3_data_b_mux[] = {
+	SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
+};
+static const unsigned int scifb3_clk_b_pins[] = {
+	/* SCIFB3_SCK */
+	40,
+};
+static const unsigned int scifb3_clk_b_mux[] = {
+	SCIFB3_SCK_40_MARK,
+};
+static const unsigned int scifb3_ctrl_b_pins[] = {
+	/* SCIFB3_RTS, SCIFB3_CTS */
+	38, 39,
+};
+static const unsigned int scifb3_ctrl_b_mux[] = {
+	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(scifa0_data),
+	SH_PFC_PIN_GROUP(scifa0_clk),
+	SH_PFC_PIN_GROUP(scifa0_ctrl),
+	SH_PFC_PIN_GROUP(scifa1_data),
+	SH_PFC_PIN_GROUP(scifa1_clk),
+	SH_PFC_PIN_GROUP(scifa1_ctrl),
+	SH_PFC_PIN_GROUP(scifb0_data),
+	SH_PFC_PIN_GROUP(scifb0_clk),
+	SH_PFC_PIN_GROUP(scifb0_ctrl),
+	SH_PFC_PIN_GROUP(scifb1_data),
+	SH_PFC_PIN_GROUP(scifb1_clk),
+	SH_PFC_PIN_GROUP(scifb1_ctrl),
+	SH_PFC_PIN_GROUP(scifb1_data_b),
+	SH_PFC_PIN_GROUP(scifb1_clk_b),
+	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb2_data),
+	SH_PFC_PIN_GROUP(scifb2_clk),
+	SH_PFC_PIN_GROUP(scifb2_ctrl),
+	SH_PFC_PIN_GROUP(scifb2_data_b),
+	SH_PFC_PIN_GROUP(scifb2_clk_b),
+	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb3_data),
+	SH_PFC_PIN_GROUP(scifb3_clk),
+	SH_PFC_PIN_GROUP(scifb3_ctrl),
+	SH_PFC_PIN_GROUP(scifb3_data_b),
+	SH_PFC_PIN_GROUP(scifb3_clk_b),
+	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
+};
+
+static const char * const scifa0_groups[] = {
+	"scifa0_data",
+	"scifa0_clk",
+	"scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+	"scifa1_data",
+	"scifa1_clk",
+	"scifa1_ctrl",
+};
+
+static const char * const scifb0_groups[] = {
+	"scifb0_data",
+	"scifb0_clk",
+	"scifb0_ctrl",
+};
+
+static const char * const scifb1_groups[] = {
+	"scifb1_data",
+	"scifb1_clk",
+	"scifb1_ctrl",
+	"scifb1_data_b",
+	"scifb1_clk_b",
+	"scifb1_ctrl_b",
+};
+
+static const char * const scifb2_groups[] = {
+	"scifb2_data",
+	"scifb2_clk",
+	"scifb2_ctrl",
+	"scifb2_data_b",
+	"scifb2_clk_b",
+	"scifb2_ctrl_b",
+};
+
+static const char * const scifb3_groups[] = {
+	"scifb3_data",
+	"scifb3_clk",
+	"scifb3_ctrl",
+	"scifb3_data_b",
+	"scifb3_clk_b",
+	"scifb3_ctrl_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scifa0),
+	SH_PFC_FUNCTION(scifa1),
+	SH_PFC_FUNCTION(scifb0),
+	SH_PFC_FUNCTION(scifb1),
+	SH_PFC_FUNCTION(scifb2),
+	SH_PFC_FUNCTION(scifb3),
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -3084,8 +3364,15 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+
 	.ranges = pinmux_ranges,
 	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
+
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4

[PATCH 21/28] sh-pfc: r8a73a4: Add IRQC pin groups and functions

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  186 ++++++++++++++++++++++++++++++++++
 1 file changed, 186 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index cd5c5fd..8a5288c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1576,6 +1576,72 @@ static const struct pinmux_range pinmux_ranges[] = {
 	{.begin = 320, .end = 329,},
 };
 
+/* - IRQC ------------------------------------------------------------------- */
+#define IRQC_PINS_MUX(pin, irq_mark)				\
+static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
+	pin,							\
+};								\
+static const unsigned int irqc_irq##irq_mark##_mux[] = {	\
+	IRQ##irq_mark##_MARK,					\
+}
+IRQC_PINS_MUX(0, 0);
+IRQC_PINS_MUX(1, 1);
+IRQC_PINS_MUX(2, 2);
+IRQC_PINS_MUX(3, 3);
+IRQC_PINS_MUX(4, 4);
+IRQC_PINS_MUX(5, 5);
+IRQC_PINS_MUX(6, 6);
+IRQC_PINS_MUX(7, 7);
+IRQC_PINS_MUX(8, 8);
+IRQC_PINS_MUX(9, 9);
+IRQC_PINS_MUX(10, 10);
+IRQC_PINS_MUX(11, 11);
+IRQC_PINS_MUX(12, 12);
+IRQC_PINS_MUX(13, 13);
+IRQC_PINS_MUX(14, 14);
+IRQC_PINS_MUX(15, 15);
+IRQC_PINS_MUX(66, 40);
+IRQC_PINS_MUX(84, 19);
+IRQC_PINS_MUX(85, 18);
+IRQC_PINS_MUX(102, 41);
+IRQC_PINS_MUX(103, 42);
+IRQC_PINS_MUX(109, 43);
+IRQC_PINS_MUX(110, 44);
+IRQC_PINS_MUX(111, 45);
+IRQC_PINS_MUX(112, 46);
+IRQC_PINS_MUX(113, 47);
+IRQC_PINS_MUX(114, 48);
+IRQC_PINS_MUX(115, 49);
+IRQC_PINS_MUX(160, 20);
+IRQC_PINS_MUX(161, 21);
+IRQC_PINS_MUX(162, 22);
+IRQC_PINS_MUX(163, 23);
+IRQC_PINS_MUX(175, 24);
+IRQC_PINS_MUX(176, 25);
+IRQC_PINS_MUX(177, 26);
+IRQC_PINS_MUX(178, 27);
+IRQC_PINS_MUX(192, 31);
+IRQC_PINS_MUX(193, 32);
+IRQC_PINS_MUX(194, 33);
+IRQC_PINS_MUX(195, 34);
+IRQC_PINS_MUX(196, 35);
+IRQC_PINS_MUX(197, 36);
+IRQC_PINS_MUX(198, 37);
+IRQC_PINS_MUX(199, 38);
+IRQC_PINS_MUX(200, 39);
+IRQC_PINS_MUX(290, 51);
+IRQC_PINS_MUX(296, 52);
+IRQC_PINS_MUX(301, 50);
+IRQC_PINS_MUX(320, 16);
+IRQC_PINS_MUX(321, 17);
+IRQC_PINS_MUX(322, 28);
+IRQC_PINS_MUX(323, 29);
+IRQC_PINS_MUX(324, 30);
+IRQC_PINS_MUX(325, 53);
+IRQC_PINS_MUX(326, 54);
+IRQC_PINS_MUX(327, 55);
+IRQC_PINS_MUX(328, 56);
+IRQC_PINS_MUX(329, 57);
 /* - SCIFA0 ----------------------------------------------------------------- */
 static const unsigned int scifa0_data_pins[] = {
 	/* SCIFA0_RXD, SCIFA0_TXD */
@@ -1773,6 +1839,64 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(irqc_irq0),
+	SH_PFC_PIN_GROUP(irqc_irq1),
+	SH_PFC_PIN_GROUP(irqc_irq2),
+	SH_PFC_PIN_GROUP(irqc_irq3),
+	SH_PFC_PIN_GROUP(irqc_irq4),
+	SH_PFC_PIN_GROUP(irqc_irq5),
+	SH_PFC_PIN_GROUP(irqc_irq6),
+	SH_PFC_PIN_GROUP(irqc_irq7),
+	SH_PFC_PIN_GROUP(irqc_irq8),
+	SH_PFC_PIN_GROUP(irqc_irq9),
+	SH_PFC_PIN_GROUP(irqc_irq10),
+	SH_PFC_PIN_GROUP(irqc_irq11),
+	SH_PFC_PIN_GROUP(irqc_irq12),
+	SH_PFC_PIN_GROUP(irqc_irq13),
+	SH_PFC_PIN_GROUP(irqc_irq14),
+	SH_PFC_PIN_GROUP(irqc_irq15),
+	SH_PFC_PIN_GROUP(irqc_irq16),
+	SH_PFC_PIN_GROUP(irqc_irq17),
+	SH_PFC_PIN_GROUP(irqc_irq18),
+	SH_PFC_PIN_GROUP(irqc_irq19),
+	SH_PFC_PIN_GROUP(irqc_irq20),
+	SH_PFC_PIN_GROUP(irqc_irq21),
+	SH_PFC_PIN_GROUP(irqc_irq22),
+	SH_PFC_PIN_GROUP(irqc_irq23),
+	SH_PFC_PIN_GROUP(irqc_irq24),
+	SH_PFC_PIN_GROUP(irqc_irq25),
+	SH_PFC_PIN_GROUP(irqc_irq26),
+	SH_PFC_PIN_GROUP(irqc_irq27),
+	SH_PFC_PIN_GROUP(irqc_irq28),
+	SH_PFC_PIN_GROUP(irqc_irq29),
+	SH_PFC_PIN_GROUP(irqc_irq30),
+	SH_PFC_PIN_GROUP(irqc_irq31),
+	SH_PFC_PIN_GROUP(irqc_irq32),
+	SH_PFC_PIN_GROUP(irqc_irq33),
+	SH_PFC_PIN_GROUP(irqc_irq34),
+	SH_PFC_PIN_GROUP(irqc_irq35),
+	SH_PFC_PIN_GROUP(irqc_irq36),
+	SH_PFC_PIN_GROUP(irqc_irq37),
+	SH_PFC_PIN_GROUP(irqc_irq38),
+	SH_PFC_PIN_GROUP(irqc_irq39),
+	SH_PFC_PIN_GROUP(irqc_irq40),
+	SH_PFC_PIN_GROUP(irqc_irq41),
+	SH_PFC_PIN_GROUP(irqc_irq42),
+	SH_PFC_PIN_GROUP(irqc_irq43),
+	SH_PFC_PIN_GROUP(irqc_irq44),
+	SH_PFC_PIN_GROUP(irqc_irq45),
+	SH_PFC_PIN_GROUP(irqc_irq46),
+	SH_PFC_PIN_GROUP(irqc_irq47),
+	SH_PFC_PIN_GROUP(irqc_irq48),
+	SH_PFC_PIN_GROUP(irqc_irq49),
+	SH_PFC_PIN_GROUP(irqc_irq50),
+	SH_PFC_PIN_GROUP(irqc_irq51),
+	SH_PFC_PIN_GROUP(irqc_irq52),
+	SH_PFC_PIN_GROUP(irqc_irq53),
+	SH_PFC_PIN_GROUP(irqc_irq54),
+	SH_PFC_PIN_GROUP(irqc_irq55),
+	SH_PFC_PIN_GROUP(irqc_irq56),
+	SH_PFC_PIN_GROUP(irqc_irq57),
 	SH_PFC_PIN_GROUP(scifa0_data),
 	SH_PFC_PIN_GROUP(scifa0_clk),
 	SH_PFC_PIN_GROUP(scifa0_ctrl),
@@ -1802,6 +1926,67 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
 };
 
+static const char * const irqc_groups[] = {
+	"irqc_irq0",
+	"irqc_irq1",
+	"irqc_irq2",
+	"irqc_irq3",
+	"irqc_irq4",
+	"irqc_irq5",
+	"irqc_irq6",
+	"irqc_irq7",
+	"irqc_irq8",
+	"irqc_irq9",
+	"irqc_irq10",
+	"irqc_irq11",
+	"irqc_irq12",
+	"irqc_irq13",
+	"irqc_irq14",
+	"irqc_irq15",
+	"irqc_irq16",
+	"irqc_irq17",
+	"irqc_irq18",
+	"irqc_irq19",
+	"irqc_irq20",
+	"irqc_irq21",
+	"irqc_irq22",
+	"irqc_irq23",
+	"irqc_irq24",
+	"irqc_irq25",
+	"irqc_irq26",
+	"irqc_irq27",
+	"irqc_irq28",
+	"irqc_irq29",
+	"irqc_irq30",
+	"irqc_irq31",
+	"irqc_irq32",
+	"irqc_irq33",
+	"irqc_irq34",
+	"irqc_irq35",
+	"irqc_irq36",
+	"irqc_irq37",
+	"irqc_irq38",
+	"irqc_irq39",
+	"irqc_irq40",
+	"irqc_irq41",
+	"irqc_irq42",
+	"irqc_irq43",
+	"irqc_irq44",
+	"irqc_irq45",
+	"irqc_irq46",
+	"irqc_irq47",
+	"irqc_irq48",
+	"irqc_irq49",
+	"irqc_irq50",
+	"irqc_irq51",
+	"irqc_irq52",
+	"irqc_irq53",
+	"irqc_irq54",
+	"irqc_irq55",
+	"irqc_irq56",
+	"irqc_irq57",
+};
+
 static const char * const scifa0_groups[] = {
 	"scifa0_data",
 	"scifa0_clk",
@@ -1848,6 +2033,7 @@ static const char * const scifb3_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(irqc),
 	SH_PFC_FUNCTION(scifa0),
 	SH_PFC_FUNCTION(scifa1),
 	SH_PFC_FUNCTION(scifb0),
-- 
1.7.10.4

[PATCH 21/28] sh-pfc: r8a73a4: Add IRQC pin groups and functions

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  186 ++++++++++++++++++++++++++++++++++
 1 file changed, 186 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index cd5c5fd..8a5288c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1576,6 +1576,72 @@ static const struct pinmux_range pinmux_ranges[] = {
 	{.begin = 320, .end = 329,},
 };
 
+/* - IRQC ------------------------------------------------------------------- */
+#define IRQC_PINS_MUX(pin, irq_mark)				\
+static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
+	pin,							\
+};								\
+static const unsigned int irqc_irq##irq_mark##_mux[] = {	\
+	IRQ##irq_mark##_MARK,					\
+}
+IRQC_PINS_MUX(0, 0);
+IRQC_PINS_MUX(1, 1);
+IRQC_PINS_MUX(2, 2);
+IRQC_PINS_MUX(3, 3);
+IRQC_PINS_MUX(4, 4);
+IRQC_PINS_MUX(5, 5);
+IRQC_PINS_MUX(6, 6);
+IRQC_PINS_MUX(7, 7);
+IRQC_PINS_MUX(8, 8);
+IRQC_PINS_MUX(9, 9);
+IRQC_PINS_MUX(10, 10);
+IRQC_PINS_MUX(11, 11);
+IRQC_PINS_MUX(12, 12);
+IRQC_PINS_MUX(13, 13);
+IRQC_PINS_MUX(14, 14);
+IRQC_PINS_MUX(15, 15);
+IRQC_PINS_MUX(66, 40);
+IRQC_PINS_MUX(84, 19);
+IRQC_PINS_MUX(85, 18);
+IRQC_PINS_MUX(102, 41);
+IRQC_PINS_MUX(103, 42);
+IRQC_PINS_MUX(109, 43);
+IRQC_PINS_MUX(110, 44);
+IRQC_PINS_MUX(111, 45);
+IRQC_PINS_MUX(112, 46);
+IRQC_PINS_MUX(113, 47);
+IRQC_PINS_MUX(114, 48);
+IRQC_PINS_MUX(115, 49);
+IRQC_PINS_MUX(160, 20);
+IRQC_PINS_MUX(161, 21);
+IRQC_PINS_MUX(162, 22);
+IRQC_PINS_MUX(163, 23);
+IRQC_PINS_MUX(175, 24);
+IRQC_PINS_MUX(176, 25);
+IRQC_PINS_MUX(177, 26);
+IRQC_PINS_MUX(178, 27);
+IRQC_PINS_MUX(192, 31);
+IRQC_PINS_MUX(193, 32);
+IRQC_PINS_MUX(194, 33);
+IRQC_PINS_MUX(195, 34);
+IRQC_PINS_MUX(196, 35);
+IRQC_PINS_MUX(197, 36);
+IRQC_PINS_MUX(198, 37);
+IRQC_PINS_MUX(199, 38);
+IRQC_PINS_MUX(200, 39);
+IRQC_PINS_MUX(290, 51);
+IRQC_PINS_MUX(296, 52);
+IRQC_PINS_MUX(301, 50);
+IRQC_PINS_MUX(320, 16);
+IRQC_PINS_MUX(321, 17);
+IRQC_PINS_MUX(322, 28);
+IRQC_PINS_MUX(323, 29);
+IRQC_PINS_MUX(324, 30);
+IRQC_PINS_MUX(325, 53);
+IRQC_PINS_MUX(326, 54);
+IRQC_PINS_MUX(327, 55);
+IRQC_PINS_MUX(328, 56);
+IRQC_PINS_MUX(329, 57);
 /* - SCIFA0 ----------------------------------------------------------------- */
 static const unsigned int scifa0_data_pins[] = {
 	/* SCIFA0_RXD, SCIFA0_TXD */
@@ -1773,6 +1839,64 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(irqc_irq0),
+	SH_PFC_PIN_GROUP(irqc_irq1),
+	SH_PFC_PIN_GROUP(irqc_irq2),
+	SH_PFC_PIN_GROUP(irqc_irq3),
+	SH_PFC_PIN_GROUP(irqc_irq4),
+	SH_PFC_PIN_GROUP(irqc_irq5),
+	SH_PFC_PIN_GROUP(irqc_irq6),
+	SH_PFC_PIN_GROUP(irqc_irq7),
+	SH_PFC_PIN_GROUP(irqc_irq8),
+	SH_PFC_PIN_GROUP(irqc_irq9),
+	SH_PFC_PIN_GROUP(irqc_irq10),
+	SH_PFC_PIN_GROUP(irqc_irq11),
+	SH_PFC_PIN_GROUP(irqc_irq12),
+	SH_PFC_PIN_GROUP(irqc_irq13),
+	SH_PFC_PIN_GROUP(irqc_irq14),
+	SH_PFC_PIN_GROUP(irqc_irq15),
+	SH_PFC_PIN_GROUP(irqc_irq16),
+	SH_PFC_PIN_GROUP(irqc_irq17),
+	SH_PFC_PIN_GROUP(irqc_irq18),
+	SH_PFC_PIN_GROUP(irqc_irq19),
+	SH_PFC_PIN_GROUP(irqc_irq20),
+	SH_PFC_PIN_GROUP(irqc_irq21),
+	SH_PFC_PIN_GROUP(irqc_irq22),
+	SH_PFC_PIN_GROUP(irqc_irq23),
+	SH_PFC_PIN_GROUP(irqc_irq24),
+	SH_PFC_PIN_GROUP(irqc_irq25),
+	SH_PFC_PIN_GROUP(irqc_irq26),
+	SH_PFC_PIN_GROUP(irqc_irq27),
+	SH_PFC_PIN_GROUP(irqc_irq28),
+	SH_PFC_PIN_GROUP(irqc_irq29),
+	SH_PFC_PIN_GROUP(irqc_irq30),
+	SH_PFC_PIN_GROUP(irqc_irq31),
+	SH_PFC_PIN_GROUP(irqc_irq32),
+	SH_PFC_PIN_GROUP(irqc_irq33),
+	SH_PFC_PIN_GROUP(irqc_irq34),
+	SH_PFC_PIN_GROUP(irqc_irq35),
+	SH_PFC_PIN_GROUP(irqc_irq36),
+	SH_PFC_PIN_GROUP(irqc_irq37),
+	SH_PFC_PIN_GROUP(irqc_irq38),
+	SH_PFC_PIN_GROUP(irqc_irq39),
+	SH_PFC_PIN_GROUP(irqc_irq40),
+	SH_PFC_PIN_GROUP(irqc_irq41),
+	SH_PFC_PIN_GROUP(irqc_irq42),
+	SH_PFC_PIN_GROUP(irqc_irq43),
+	SH_PFC_PIN_GROUP(irqc_irq44),
+	SH_PFC_PIN_GROUP(irqc_irq45),
+	SH_PFC_PIN_GROUP(irqc_irq46),
+	SH_PFC_PIN_GROUP(irqc_irq47),
+	SH_PFC_PIN_GROUP(irqc_irq48),
+	SH_PFC_PIN_GROUP(irqc_irq49),
+	SH_PFC_PIN_GROUP(irqc_irq50),
+	SH_PFC_PIN_GROUP(irqc_irq51),
+	SH_PFC_PIN_GROUP(irqc_irq52),
+	SH_PFC_PIN_GROUP(irqc_irq53),
+	SH_PFC_PIN_GROUP(irqc_irq54),
+	SH_PFC_PIN_GROUP(irqc_irq55),
+	SH_PFC_PIN_GROUP(irqc_irq56),
+	SH_PFC_PIN_GROUP(irqc_irq57),
 	SH_PFC_PIN_GROUP(scifa0_data),
 	SH_PFC_PIN_GROUP(scifa0_clk),
 	SH_PFC_PIN_GROUP(scifa0_ctrl),
@@ -1802,6 +1926,67 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
 };
 
+static const char * const irqc_groups[] = {
+	"irqc_irq0",
+	"irqc_irq1",
+	"irqc_irq2",
+	"irqc_irq3",
+	"irqc_irq4",
+	"irqc_irq5",
+	"irqc_irq6",
+	"irqc_irq7",
+	"irqc_irq8",
+	"irqc_irq9",
+	"irqc_irq10",
+	"irqc_irq11",
+	"irqc_irq12",
+	"irqc_irq13",
+	"irqc_irq14",
+	"irqc_irq15",
+	"irqc_irq16",
+	"irqc_irq17",
+	"irqc_irq18",
+	"irqc_irq19",
+	"irqc_irq20",
+	"irqc_irq21",
+	"irqc_irq22",
+	"irqc_irq23",
+	"irqc_irq24",
+	"irqc_irq25",
+	"irqc_irq26",
+	"irqc_irq27",
+	"irqc_irq28",
+	"irqc_irq29",
+	"irqc_irq30",
+	"irqc_irq31",
+	"irqc_irq32",
+	"irqc_irq33",
+	"irqc_irq34",
+	"irqc_irq35",
+	"irqc_irq36",
+	"irqc_irq37",
+	"irqc_irq38",
+	"irqc_irq39",
+	"irqc_irq40",
+	"irqc_irq41",
+	"irqc_irq42",
+	"irqc_irq43",
+	"irqc_irq44",
+	"irqc_irq45",
+	"irqc_irq46",
+	"irqc_irq47",
+	"irqc_irq48",
+	"irqc_irq49",
+	"irqc_irq50",
+	"irqc_irq51",
+	"irqc_irq52",
+	"irqc_irq53",
+	"irqc_irq54",
+	"irqc_irq55",
+	"irqc_irq56",
+	"irqc_irq57",
+};
+
 static const char * const scifa0_groups[] = {
 	"scifa0_data",
 	"scifa0_clk",
@@ -1848,6 +2033,7 @@ static const char * const scifb3_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(irqc),
 	SH_PFC_FUNCTION(scifa0),
 	SH_PFC_FUNCTION(scifa1),
 	SH_PFC_FUNCTION(scifb0),
-- 
1.7.10.4

[PATCH 22/28] sh-pfc: r8a73a4: Remove SCIF function GPIOS

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   45 ----------------------------------
 1 file changed, 45 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 8a5288c..470b18f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2160,55 +2160,45 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port19 */
 	GPIO_FN(LCDD19),
-	GPIO_FN(SCIFB3_RTS_19),
 	GPIO_FN(DU0_DB3),
 
 	/* Port20 */
 	GPIO_FN(LCDD20),
-	GPIO_FN(SCIFB3_CTS_20),
 	GPIO_FN(DU0_DB4),
 
 	/* Port21 */
 	GPIO_FN(LCDD21),
-	GPIO_FN(SCIFB3_TXD_21),
 	GPIO_FN(DU0_DB5),
 
 	/* Port22 */
 	GPIO_FN(LCDD22),
-	GPIO_FN(SCIFB3_RXD_22),
 	GPIO_FN(DU0_DB6),
 
 	/* Port23 */
 	GPIO_FN(LCDD23),
-	GPIO_FN(SCIFB3_SCK_23),
 	GPIO_FN(DU0_DB7),
 
 	/* Port24 */
 	GPIO_FN(LCDHSYN),
 	GPIO_FN(LCDCS),
-	GPIO_FN(SCIFB1_RTS_24),
 	GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
 
 	/* Port25 */
 	GPIO_FN(LCDVSYN),
-	GPIO_FN(SCIFB1_CTS_25),
 	GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
 
 	/* Port26 */
 	GPIO_FN(LCDDCK),
 	GPIO_FN(LCDWR),
-	GPIO_FN(SCIFB1_TXD_26),
 	GPIO_FN(DU0_DOTCLKIN),
 
 	/* Port27 */
 	GPIO_FN(LCDDISP),
 	GPIO_FN(LCDRS),
-	GPIO_FN(SCIFB1_RXD_27),
 	GPIO_FN(DU0_DOTCLKOUT),
 
 	/* Port28 */
 	GPIO_FN(LCDRD_N),
-	GPIO_FN(SCIFB1_SCK_28),
 	GPIO_FN(DU0_DOTCLKOUTB),
 
 	/* Port29 */
@@ -2222,48 +2212,36 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(DU0_ODDF_N_CLAMP),
 
 	/* Port32 */
-	GPIO_FN(SCIFA0_RTS),
 	GPIO_FN(SIM0_DET),
 	GPIO_FN(CSCIF0_RTS),
 
 	/* Port33 */
-	GPIO_FN(SCIFA0_CTS),
 	GPIO_FN(SIM1_DET),
 	GPIO_FN(CSCIF0_CTS),
 
 	/* Port34 */
-	GPIO_FN(SCIFA0_SCK),
 	GPIO_FN(SIM0_PWRON),
 	GPIO_FN(CSCIF0_SCK),
 
 	/* Port35 */
-	GPIO_FN(SCIFA1_RTS),
 	GPIO_FN(CSCIF1_RTS),
 
 	/* Port36 */
-	GPIO_FN(SCIFA1_CTS),
 	GPIO_FN(CSCIF1_CTS),
 
 	/* Port37 */
-	GPIO_FN(SCIFA1_SCK),
 	GPIO_FN(CSCIF1_SCK),
 
 	/* Port38 */
-	GPIO_FN(SCIFB0_RTS),
 	GPIO_FN(TPU0TO1),
-	GPIO_FN(SCIFB3_RTS_38),
 	GPIO_FN(CHSCIF0_HRTS),
 
 	/* Port39 */
-	GPIO_FN(SCIFB0_CTS),
 	GPIO_FN(TPU0TO2),
-	GPIO_FN(SCIFB3_CTS_39),
 	GPIO_FN(CHSCIF0_HCTS),
 
 	/* Port40 */
-	GPIO_FN(SCIFB0_SCK),
 	GPIO_FN(TPU0TO3),
-	GPIO_FN(SCIFB3_SCK_40),
 	GPIO_FN(CHSCIF0_HSCK),
 
 	/* Port64 */
@@ -2274,52 +2252,44 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port66 */
 	GPIO_FN(HSI_RX_WAKE),
-	GPIO_FN(SCIFB2_CTS_66),
 	GPIO_FN(MSIOF3_SYNC),
 	GPIO_FN(GenIO4),
 	GPIO_FN(IRQ40),
 
 	/* Port67 */
 	GPIO_FN(HSI_RX_READY),
-	GPIO_FN(SCIFB1_TXD_67),
 	GPIO_FN(GIO_OUT3_67),
 	GPIO_FN(CHSCIF1_HTX),
 
 	/* Port68 */
 	GPIO_FN(HSI_RX_FLAG),
-	GPIO_FN(SCIFB2_TXD_68),
 	GPIO_FN(MSIOF3_TXD),
 	GPIO_FN(GIO_OUT4_68),
 
 	/* Port69 */
 	GPIO_FN(HSI_RX_DATA),
-	GPIO_FN(SCIFB2_RXD_69),
 	GPIO_FN(MSIOF3_RXD),
 	GPIO_FN(GIO_OUT5_69),
 
 	/* Port70 */
 	GPIO_FN(HSI_TX_FLAG),
-	GPIO_FN(SCIFB1_RTS_70),
 	GPIO_FN(GIO_OUT1_70),
 	GPIO_FN(HSIC_TSTCLK0),
 	GPIO_FN(CHSCIF1_HRTS),
 
 	/* Port71 */
 	GPIO_FN(HSI_TX_DATA),
-	GPIO_FN(SCIFB1_CTS_71),
 	GPIO_FN(GIO_OUT2_71),
 	GPIO_FN(HSIC_TSTCLK1),
 	GPIO_FN(CHSCIF1_HCTS),
 
 	/* Port72 */
 	GPIO_FN(HSI_TX_WAKE),
-	GPIO_FN(SCIFB1_RXD_72),
 	GPIO_FN(GenIO8),
 	GPIO_FN(CHSCIF1_HRX),
 
 	/* Port73 */
 	GPIO_FN(HSI_TX_READY),
-	GPIO_FN(SCIFB2_RTS_73),
 	GPIO_FN(MSIOF3_SCK),
 	GPIO_FN(GIO_OUT0_73),
 
@@ -2398,36 +2368,28 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(IRQ49),
 
 	/* Port116 */
-	GPIO_FN(SCIFA0_TXD),
 	GPIO_FN(CSCIF0_TX),
 
 	/* Port117 */
-	GPIO_FN(SCIFA0_RXD),
 	GPIO_FN(CSCIF0_RX),
 
 	/* Port118 */
-	GPIO_FN(SCIFA1_TXD),
 	GPIO_FN(CSCIF1_TX),
 
 	/* Port119 */
-	GPIO_FN(SCIFA1_RXD),
 	GPIO_FN(CSCIF1_RX),
 
 	/* Port120 */
 	GPIO_FN(SF_PORT_1_120),
-	GPIO_FN(SCIFB3_RXD_120),
 	GPIO_FN(DU0_CDE),
 
 	/* Port121 */
 	GPIO_FN(SF_PORT_0_121),
-	GPIO_FN(SCIFB3_TXD_121),
 
 	/* Port122 */
-	GPIO_FN(SCIFB0_TXD),
 	GPIO_FN(CHSCIF0_HTX),
 
 	/* Port123 */
-	GPIO_FN(SCIFB0_RXD),
 	GPIO_FN(CHSCIF0_HRX),
 
 	/* Port124 */
@@ -2721,11 +2683,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MSIOF0_TXD),
 
 	/* Port261 */
-	GPIO_FN(SCIFB1_SCK_261),
 	GPIO_FN(CHSCIF1_HSCK),
 
 	/* Port262 */
-	GPIO_FN(SCIFB2_SCK_262),
 
 	/* Port263 - Port266 FN1 */
 	GPIO_FN(MSIOF1_SS2),
@@ -2809,7 +2769,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port295 */
 	GPIO_FN(SDHID2_0),
 	GPIO_FN(MSIOF4_TXD),
-	GPIO_FN(SCIFB2_TXD_295),
 	GPIO_FN(MSIOF6_TXD),
 
 	/* Port296 */
@@ -2830,10 +2789,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MSIOF4_SS1),
 
 	/* Port297 - Port300 FN3 */
-	GPIO_FN(SCIFB2_RXD_297),
-	GPIO_FN(SCIFB2_CTS_298),
-	GPIO_FN(SCIFB2_SCK_299),
-	GPIO_FN(SCIFB2_RTS_300),
 
 	/* Port297 - Port300 FN4 */
 	GPIO_FN(MSIOF6_RXD),
-- 
1.7.10.4

[PATCH 22/28] sh-pfc: r8a73a4: Remove SCIF function GPIOS

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   45 ----------------------------------
 1 file changed, 45 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 8a5288c..470b18f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2160,55 +2160,45 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port19 */
 	GPIO_FN(LCDD19),
-	GPIO_FN(SCIFB3_RTS_19),
 	GPIO_FN(DU0_DB3),
 
 	/* Port20 */
 	GPIO_FN(LCDD20),
-	GPIO_FN(SCIFB3_CTS_20),
 	GPIO_FN(DU0_DB4),
 
 	/* Port21 */
 	GPIO_FN(LCDD21),
-	GPIO_FN(SCIFB3_TXD_21),
 	GPIO_FN(DU0_DB5),
 
 	/* Port22 */
 	GPIO_FN(LCDD22),
-	GPIO_FN(SCIFB3_RXD_22),
 	GPIO_FN(DU0_DB6),
 
 	/* Port23 */
 	GPIO_FN(LCDD23),
-	GPIO_FN(SCIFB3_SCK_23),
 	GPIO_FN(DU0_DB7),
 
 	/* Port24 */
 	GPIO_FN(LCDHSYN),
 	GPIO_FN(LCDCS),
-	GPIO_FN(SCIFB1_RTS_24),
 	GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
 
 	/* Port25 */
 	GPIO_FN(LCDVSYN),
-	GPIO_FN(SCIFB1_CTS_25),
 	GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
 
 	/* Port26 */
 	GPIO_FN(LCDDCK),
 	GPIO_FN(LCDWR),
-	GPIO_FN(SCIFB1_TXD_26),
 	GPIO_FN(DU0_DOTCLKIN),
 
 	/* Port27 */
 	GPIO_FN(LCDDISP),
 	GPIO_FN(LCDRS),
-	GPIO_FN(SCIFB1_RXD_27),
 	GPIO_FN(DU0_DOTCLKOUT),
 
 	/* Port28 */
 	GPIO_FN(LCDRD_N),
-	GPIO_FN(SCIFB1_SCK_28),
 	GPIO_FN(DU0_DOTCLKOUTB),
 
 	/* Port29 */
@@ -2222,48 +2212,36 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(DU0_ODDF_N_CLAMP),
 
 	/* Port32 */
-	GPIO_FN(SCIFA0_RTS),
 	GPIO_FN(SIM0_DET),
 	GPIO_FN(CSCIF0_RTS),
 
 	/* Port33 */
-	GPIO_FN(SCIFA0_CTS),
 	GPIO_FN(SIM1_DET),
 	GPIO_FN(CSCIF0_CTS),
 
 	/* Port34 */
-	GPIO_FN(SCIFA0_SCK),
 	GPIO_FN(SIM0_PWRON),
 	GPIO_FN(CSCIF0_SCK),
 
 	/* Port35 */
-	GPIO_FN(SCIFA1_RTS),
 	GPIO_FN(CSCIF1_RTS),
 
 	/* Port36 */
-	GPIO_FN(SCIFA1_CTS),
 	GPIO_FN(CSCIF1_CTS),
 
 	/* Port37 */
-	GPIO_FN(SCIFA1_SCK),
 	GPIO_FN(CSCIF1_SCK),
 
 	/* Port38 */
-	GPIO_FN(SCIFB0_RTS),
 	GPIO_FN(TPU0TO1),
-	GPIO_FN(SCIFB3_RTS_38),
 	GPIO_FN(CHSCIF0_HRTS),
 
 	/* Port39 */
-	GPIO_FN(SCIFB0_CTS),
 	GPIO_FN(TPU0TO2),
-	GPIO_FN(SCIFB3_CTS_39),
 	GPIO_FN(CHSCIF0_HCTS),
 
 	/* Port40 */
-	GPIO_FN(SCIFB0_SCK),
 	GPIO_FN(TPU0TO3),
-	GPIO_FN(SCIFB3_SCK_40),
 	GPIO_FN(CHSCIF0_HSCK),
 
 	/* Port64 */
@@ -2274,52 +2252,44 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port66 */
 	GPIO_FN(HSI_RX_WAKE),
-	GPIO_FN(SCIFB2_CTS_66),
 	GPIO_FN(MSIOF3_SYNC),
 	GPIO_FN(GenIO4),
 	GPIO_FN(IRQ40),
 
 	/* Port67 */
 	GPIO_FN(HSI_RX_READY),
-	GPIO_FN(SCIFB1_TXD_67),
 	GPIO_FN(GIO_OUT3_67),
 	GPIO_FN(CHSCIF1_HTX),
 
 	/* Port68 */
 	GPIO_FN(HSI_RX_FLAG),
-	GPIO_FN(SCIFB2_TXD_68),
 	GPIO_FN(MSIOF3_TXD),
 	GPIO_FN(GIO_OUT4_68),
 
 	/* Port69 */
 	GPIO_FN(HSI_RX_DATA),
-	GPIO_FN(SCIFB2_RXD_69),
 	GPIO_FN(MSIOF3_RXD),
 	GPIO_FN(GIO_OUT5_69),
 
 	/* Port70 */
 	GPIO_FN(HSI_TX_FLAG),
-	GPIO_FN(SCIFB1_RTS_70),
 	GPIO_FN(GIO_OUT1_70),
 	GPIO_FN(HSIC_TSTCLK0),
 	GPIO_FN(CHSCIF1_HRTS),
 
 	/* Port71 */
 	GPIO_FN(HSI_TX_DATA),
-	GPIO_FN(SCIFB1_CTS_71),
 	GPIO_FN(GIO_OUT2_71),
 	GPIO_FN(HSIC_TSTCLK1),
 	GPIO_FN(CHSCIF1_HCTS),
 
 	/* Port72 */
 	GPIO_FN(HSI_TX_WAKE),
-	GPIO_FN(SCIFB1_RXD_72),
 	GPIO_FN(GenIO8),
 	GPIO_FN(CHSCIF1_HRX),
 
 	/* Port73 */
 	GPIO_FN(HSI_TX_READY),
-	GPIO_FN(SCIFB2_RTS_73),
 	GPIO_FN(MSIOF3_SCK),
 	GPIO_FN(GIO_OUT0_73),
 
@@ -2398,36 +2368,28 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(IRQ49),
 
 	/* Port116 */
-	GPIO_FN(SCIFA0_TXD),
 	GPIO_FN(CSCIF0_TX),
 
 	/* Port117 */
-	GPIO_FN(SCIFA0_RXD),
 	GPIO_FN(CSCIF0_RX),
 
 	/* Port118 */
-	GPIO_FN(SCIFA1_TXD),
 	GPIO_FN(CSCIF1_TX),
 
 	/* Port119 */
-	GPIO_FN(SCIFA1_RXD),
 	GPIO_FN(CSCIF1_RX),
 
 	/* Port120 */
 	GPIO_FN(SF_PORT_1_120),
-	GPIO_FN(SCIFB3_RXD_120),
 	GPIO_FN(DU0_CDE),
 
 	/* Port121 */
 	GPIO_FN(SF_PORT_0_121),
-	GPIO_FN(SCIFB3_TXD_121),
 
 	/* Port122 */
-	GPIO_FN(SCIFB0_TXD),
 	GPIO_FN(CHSCIF0_HTX),
 
 	/* Port123 */
-	GPIO_FN(SCIFB0_RXD),
 	GPIO_FN(CHSCIF0_HRX),
 
 	/* Port124 */
@@ -2721,11 +2683,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MSIOF0_TXD),
 
 	/* Port261 */
-	GPIO_FN(SCIFB1_SCK_261),
 	GPIO_FN(CHSCIF1_HSCK),
 
 	/* Port262 */
-	GPIO_FN(SCIFB2_SCK_262),
 
 	/* Port263 - Port266 FN1 */
 	GPIO_FN(MSIOF1_SS2),
@@ -2809,7 +2769,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port295 */
 	GPIO_FN(SDHID2_0),
 	GPIO_FN(MSIOF4_TXD),
-	GPIO_FN(SCIFB2_TXD_295),
 	GPIO_FN(MSIOF6_TXD),
 
 	/* Port296 */
@@ -2830,10 +2789,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MSIOF4_SS1),
 
 	/* Port297 - Port300 FN3 */
-	GPIO_FN(SCIFB2_RXD_297),
-	GPIO_FN(SCIFB2_CTS_298),
-	GPIO_FN(SCIFB2_SCK_299),
-	GPIO_FN(SCIFB2_RTS_300),
 
 	/* Port297 - Port300 FN4 */
 	GPIO_FN(MSIOF6_RXD),
-- 
1.7.10.4

[PATCH 23/28] sh-pfc: r8a73a4: Remove IRQC function GPIOS

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 board support will use the pinctrl API to control the
external IRQ pins so remove the unused function GPIOS.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   58 ----------------------------------
 1 file changed, 58 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 470b18f..66fc747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2049,99 +2049,83 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(LCDD0),
 	GPIO_FN(PDM2_CLK_0),
 	GPIO_FN(DU0_DR0),
-	GPIO_FN(IRQ0),
 
 	/* Port1 */
 	GPIO_FN(LCDD1),
 	GPIO_FN(PDM2_DATA_1),
 	GPIO_FN(DU0_DR19),
-	GPIO_FN(IRQ1),
 
 	/* Port2 */
 	GPIO_FN(LCDD2),
 	GPIO_FN(PDM3_CLK_2),
 	GPIO_FN(DU0_DR2),
-	GPIO_FN(IRQ2),
 
 	/* Port3 */
 	GPIO_FN(LCDD3),
 	GPIO_FN(PDM3_DATA_3),
 	GPIO_FN(DU0_DR3),
-	GPIO_FN(IRQ3),
 
 	/* Port4 */
 	GPIO_FN(LCDD4),
 	GPIO_FN(PDM4_CLK_4),
 	GPIO_FN(DU0_DR4),
-	GPIO_FN(IRQ4),
 
 	/* Port5 */
 	GPIO_FN(LCDD5),
 	GPIO_FN(PDM4_DATA_5),
 	GPIO_FN(DU0_DR5),
-	GPIO_FN(IRQ5),
 
 	/* Port6 */
 	GPIO_FN(LCDD6),
 	GPIO_FN(PDM0_OUTCLK_6),
 	GPIO_FN(DU0_DR6),
-	GPIO_FN(IRQ6),
 
 	/* Port7 */
 	GPIO_FN(LCDD7),
 	GPIO_FN(PDM0_OUTDATA_7),
 	GPIO_FN(DU0_DR7),
-	GPIO_FN(IRQ7),
 
 	/* Port8 */
 	GPIO_FN(LCDD8),
 	GPIO_FN(PDM1_OUTCLK_8),
 	GPIO_FN(DU0_DG0),
-	GPIO_FN(IRQ8),
 
 	/* Port9 */
 	GPIO_FN(LCDD9),
 	GPIO_FN(PDM1_OUTDATA_9),
 	GPIO_FN(DU0_DG1),
-	GPIO_FN(IRQ9),
 
 	/* Port10 */
 	GPIO_FN(LCDD10),
 	GPIO_FN(FSICCK),
 	GPIO_FN(DU0_DG2),
-	GPIO_FN(IRQ10),
 
 	/* Port11 */
 	GPIO_FN(LCDD11),
 	GPIO_FN(FSICISLD),
 	GPIO_FN(DU0_DG3),
-	GPIO_FN(IRQ11),
 
 	/* Port12 */
 	GPIO_FN(LCDD12),
 	GPIO_FN(FSICOMC),
 	GPIO_FN(DU0_DG4),
-	GPIO_FN(IRQ12),
 
 	/* Port13 */
 	GPIO_FN(LCDD13),
 	GPIO_FN(FSICOLR),
 	GPIO_FN(FSICILR),
 	GPIO_FN(DU0_DG5),
-	GPIO_FN(IRQ13),
 
 	/* Port14 */
 	GPIO_FN(LCDD14),
 	GPIO_FN(FSICOBT),
 	GPIO_FN(FSICIBT),
 	GPIO_FN(DU0_DG6),
-	GPIO_FN(IRQ14),
 
 	/* Port15 */
 	GPIO_FN(LCDD15),
 	GPIO_FN(FSICOSLD),
 	GPIO_FN(DU0_DG7),
-	GPIO_FN(IRQ15),
 
 	/* Port16 */
 	GPIO_FN(LCDD16),
@@ -2254,7 +2238,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(HSI_RX_WAKE),
 	GPIO_FN(MSIOF3_SYNC),
 	GPIO_FN(GenIO4),
-	GPIO_FN(IRQ40),
 
 	/* Port67 */
 	GPIO_FN(HSI_RX_READY),
@@ -2304,8 +2287,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(TXP2),
 	GPIO_FN(COEX_0),
 	GPIO_FN(COEX_1),
-	GPIO_FN(IRQ19),
-	GPIO_FN(IRQ18),
 
 	/* Port96 - Port101 */
 	GPIO_FN(KEYIN0),
@@ -2317,11 +2298,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port102 */
 	GPIO_FN(KEYIN6),
-	GPIO_FN(IRQ41),
 
 	/* Port103 */
 	GPIO_FN(KEYIN7),
-	GPIO_FN(IRQ42),
 
 	/* Port104 - Port108 */
 	GPIO_FN(KEYOUT0),
@@ -2332,40 +2311,33 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port109 */
 	GPIO_FN(KEYOUT5),
-	GPIO_FN(IRQ43),
 
 	/* Port110 */
 	GPIO_FN(KEYOUT6),
-	GPIO_FN(IRQ44),
 
 	/* Port111 */
 	GPIO_FN(KEYOUT7),
 	GPIO_FN(RFANAEN),
-	GPIO_FN(IRQ45),
 
 	/* Port112 */
 	GPIO_FN(KEYIN8),
 	GPIO_FN(KEYOUT8),
 	GPIO_FN(SF_IRQ_04),
-	GPIO_FN(IRQ46),
 
 	/* Port113 */
 	GPIO_FN(KEYIN9),
 	GPIO_FN(KEYOUT9),
 	GPIO_FN(SF_IRQ_05),
-	GPIO_FN(IRQ47),
 
 	/* Port114 */
 	GPIO_FN(KEYIN10),
 	GPIO_FN(KEYOUT10),
 	GPIO_FN(SF_IRQ_06),
-	GPIO_FN(IRQ48),
 
 	/* Port115 */
 	GPIO_FN(KEYIN11),
 	GPIO_FN(KEYOUT11),
 	GPIO_FN(SF_IRQ_07),
-	GPIO_FN(IRQ49),
 
 	/* Port116 */
 	GPIO_FN(CSCIF0_TX),
@@ -2444,10 +2416,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(STP_ISD_1),
 
 	/* Port160 - Port178 */
-	GPIO_FN(IRQ20),
-	GPIO_FN(IRQ21),
-	GPIO_FN(IRQ22),
-	GPIO_FN(IRQ23),
 	GPIO_FN(MMCD0_0),
 	GPIO_FN(MMCD0_1),
 	GPIO_FN(MMCD0_2),
@@ -2459,10 +2427,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MMCCMD0),
 	GPIO_FN(MMCCLK0),
 	GPIO_FN(MMCRST),
-	GPIO_FN(IRQ24),
-	GPIO_FN(IRQ25),
-	GPIO_FN(IRQ26),
-	GPIO_FN(IRQ27),
 
 	/* Port192 - Port200 FN1 */
 	GPIO_FN(A10),
@@ -2487,15 +2451,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MMCCMD1),
 
 	/* Port192 - Port200 IRQ */
-	GPIO_FN(IRQ31),
-	GPIO_FN(IRQ32),
-	GPIO_FN(IRQ33),
-	GPIO_FN(IRQ34),
-	GPIO_FN(IRQ35),
-	GPIO_FN(IRQ36),
-	GPIO_FN(IRQ37),
-	GPIO_FN(IRQ38),
-	GPIO_FN(IRQ39),
 
 	/* Port201 */
 	GPIO_FN(A1),
@@ -2752,7 +2707,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port290 */
 	GPIO_FN(SDHID1_1),
 	GPIO_FN(STMDATA1_2),
-	GPIO_FN(IRQ51),
 
 	/* Port291 - Port294 FN1 */
 	GPIO_FN(SDHID1_2),
@@ -2774,7 +2728,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port296 */
 	GPIO_FN(SDHID2_1),
 	GPIO_FN(MSIOF6_SS2),
-	GPIO_FN(IRQ52),
 
 	/* Port297 - Port300 FN1 */
 	GPIO_FN(SDHID2_2),
@@ -2798,7 +2751,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port301 */
 	GPIO_FN(SDHICD0),
-	GPIO_FN(IRQ50),
 
 	/* Port302 - Port306 FN1 */
 	GPIO_FN(SDHID0_0),
@@ -2822,16 +2774,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(STMCLK_1),
 
 	/* Port320 - Port329 */
-	GPIO_FN(IRQ16),
-	GPIO_FN(IRQ17),
-	GPIO_FN(IRQ28),
-	GPIO_FN(IRQ29),
-	GPIO_FN(IRQ30),
-	GPIO_FN(IRQ53),
-	GPIO_FN(IRQ54),
-	GPIO_FN(IRQ55),
-	GPIO_FN(IRQ56),
-	GPIO_FN(IRQ57),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.7.10.4

[PATCH 23/28] sh-pfc: r8a73a4: Remove IRQC function GPIOS

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 board support will use the pinctrl API to control the
external IRQ pins so remove the unused function GPIOS.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |   58 ----------------------------------
 1 file changed, 58 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 470b18f..66fc747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2049,99 +2049,83 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(LCDD0),
 	GPIO_FN(PDM2_CLK_0),
 	GPIO_FN(DU0_DR0),
-	GPIO_FN(IRQ0),
 
 	/* Port1 */
 	GPIO_FN(LCDD1),
 	GPIO_FN(PDM2_DATA_1),
 	GPIO_FN(DU0_DR19),
-	GPIO_FN(IRQ1),
 
 	/* Port2 */
 	GPIO_FN(LCDD2),
 	GPIO_FN(PDM3_CLK_2),
 	GPIO_FN(DU0_DR2),
-	GPIO_FN(IRQ2),
 
 	/* Port3 */
 	GPIO_FN(LCDD3),
 	GPIO_FN(PDM3_DATA_3),
 	GPIO_FN(DU0_DR3),
-	GPIO_FN(IRQ3),
 
 	/* Port4 */
 	GPIO_FN(LCDD4),
 	GPIO_FN(PDM4_CLK_4),
 	GPIO_FN(DU0_DR4),
-	GPIO_FN(IRQ4),
 
 	/* Port5 */
 	GPIO_FN(LCDD5),
 	GPIO_FN(PDM4_DATA_5),
 	GPIO_FN(DU0_DR5),
-	GPIO_FN(IRQ5),
 
 	/* Port6 */
 	GPIO_FN(LCDD6),
 	GPIO_FN(PDM0_OUTCLK_6),
 	GPIO_FN(DU0_DR6),
-	GPIO_FN(IRQ6),
 
 	/* Port7 */
 	GPIO_FN(LCDD7),
 	GPIO_FN(PDM0_OUTDATA_7),
 	GPIO_FN(DU0_DR7),
-	GPIO_FN(IRQ7),
 
 	/* Port8 */
 	GPIO_FN(LCDD8),
 	GPIO_FN(PDM1_OUTCLK_8),
 	GPIO_FN(DU0_DG0),
-	GPIO_FN(IRQ8),
 
 	/* Port9 */
 	GPIO_FN(LCDD9),
 	GPIO_FN(PDM1_OUTDATA_9),
 	GPIO_FN(DU0_DG1),
-	GPIO_FN(IRQ9),
 
 	/* Port10 */
 	GPIO_FN(LCDD10),
 	GPIO_FN(FSICCK),
 	GPIO_FN(DU0_DG2),
-	GPIO_FN(IRQ10),
 
 	/* Port11 */
 	GPIO_FN(LCDD11),
 	GPIO_FN(FSICISLD),
 	GPIO_FN(DU0_DG3),
-	GPIO_FN(IRQ11),
 
 	/* Port12 */
 	GPIO_FN(LCDD12),
 	GPIO_FN(FSICOMC),
 	GPIO_FN(DU0_DG4),
-	GPIO_FN(IRQ12),
 
 	/* Port13 */
 	GPIO_FN(LCDD13),
 	GPIO_FN(FSICOLR),
 	GPIO_FN(FSICILR),
 	GPIO_FN(DU0_DG5),
-	GPIO_FN(IRQ13),
 
 	/* Port14 */
 	GPIO_FN(LCDD14),
 	GPIO_FN(FSICOBT),
 	GPIO_FN(FSICIBT),
 	GPIO_FN(DU0_DG6),
-	GPIO_FN(IRQ14),
 
 	/* Port15 */
 	GPIO_FN(LCDD15),
 	GPIO_FN(FSICOSLD),
 	GPIO_FN(DU0_DG7),
-	GPIO_FN(IRQ15),
 
 	/* Port16 */
 	GPIO_FN(LCDD16),
@@ -2254,7 +2238,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(HSI_RX_WAKE),
 	GPIO_FN(MSIOF3_SYNC),
 	GPIO_FN(GenIO4),
-	GPIO_FN(IRQ40),
 
 	/* Port67 */
 	GPIO_FN(HSI_RX_READY),
@@ -2304,8 +2287,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(TXP2),
 	GPIO_FN(COEX_0),
 	GPIO_FN(COEX_1),
-	GPIO_FN(IRQ19),
-	GPIO_FN(IRQ18),
 
 	/* Port96 - Port101 */
 	GPIO_FN(KEYIN0),
@@ -2317,11 +2298,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port102 */
 	GPIO_FN(KEYIN6),
-	GPIO_FN(IRQ41),
 
 	/* Port103 */
 	GPIO_FN(KEYIN7),
-	GPIO_FN(IRQ42),
 
 	/* Port104 - Port108 */
 	GPIO_FN(KEYOUT0),
@@ -2332,40 +2311,33 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port109 */
 	GPIO_FN(KEYOUT5),
-	GPIO_FN(IRQ43),
 
 	/* Port110 */
 	GPIO_FN(KEYOUT6),
-	GPIO_FN(IRQ44),
 
 	/* Port111 */
 	GPIO_FN(KEYOUT7),
 	GPIO_FN(RFANAEN),
-	GPIO_FN(IRQ45),
 
 	/* Port112 */
 	GPIO_FN(KEYIN8),
 	GPIO_FN(KEYOUT8),
 	GPIO_FN(SF_IRQ_04),
-	GPIO_FN(IRQ46),
 
 	/* Port113 */
 	GPIO_FN(KEYIN9),
 	GPIO_FN(KEYOUT9),
 	GPIO_FN(SF_IRQ_05),
-	GPIO_FN(IRQ47),
 
 	/* Port114 */
 	GPIO_FN(KEYIN10),
 	GPIO_FN(KEYOUT10),
 	GPIO_FN(SF_IRQ_06),
-	GPIO_FN(IRQ48),
 
 	/* Port115 */
 	GPIO_FN(KEYIN11),
 	GPIO_FN(KEYOUT11),
 	GPIO_FN(SF_IRQ_07),
-	GPIO_FN(IRQ49),
 
 	/* Port116 */
 	GPIO_FN(CSCIF0_TX),
@@ -2444,10 +2416,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(STP_ISD_1),
 
 	/* Port160 - Port178 */
-	GPIO_FN(IRQ20),
-	GPIO_FN(IRQ21),
-	GPIO_FN(IRQ22),
-	GPIO_FN(IRQ23),
 	GPIO_FN(MMCD0_0),
 	GPIO_FN(MMCD0_1),
 	GPIO_FN(MMCD0_2),
@@ -2459,10 +2427,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MMCCMD0),
 	GPIO_FN(MMCCLK0),
 	GPIO_FN(MMCRST),
-	GPIO_FN(IRQ24),
-	GPIO_FN(IRQ25),
-	GPIO_FN(IRQ26),
-	GPIO_FN(IRQ27),
 
 	/* Port192 - Port200 FN1 */
 	GPIO_FN(A10),
@@ -2487,15 +2451,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(MMCCMD1),
 
 	/* Port192 - Port200 IRQ */
-	GPIO_FN(IRQ31),
-	GPIO_FN(IRQ32),
-	GPIO_FN(IRQ33),
-	GPIO_FN(IRQ34),
-	GPIO_FN(IRQ35),
-	GPIO_FN(IRQ36),
-	GPIO_FN(IRQ37),
-	GPIO_FN(IRQ38),
-	GPIO_FN(IRQ39),
 
 	/* Port201 */
 	GPIO_FN(A1),
@@ -2752,7 +2707,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port290 */
 	GPIO_FN(SDHID1_1),
 	GPIO_FN(STMDATA1_2),
-	GPIO_FN(IRQ51),
 
 	/* Port291 - Port294 FN1 */
 	GPIO_FN(SDHID1_2),
@@ -2774,7 +2728,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* Port296 */
 	GPIO_FN(SDHID2_1),
 	GPIO_FN(MSIOF6_SS2),
-	GPIO_FN(IRQ52),
 
 	/* Port297 - Port300 FN1 */
 	GPIO_FN(SDHID2_2),
@@ -2798,7 +2751,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 
 	/* Port301 */
 	GPIO_FN(SDHICD0),
-	GPIO_FN(IRQ50),
 
 	/* Port302 - Port306 FN1 */
 	GPIO_FN(SDHID0_0),
@@ -2822,16 +2774,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(STMCLK_1),
 
 	/* Port320 - Port329 */
-	GPIO_FN(IRQ16),
-	GPIO_FN(IRQ17),
-	GPIO_FN(IRQ28),
-	GPIO_FN(IRQ29),
-	GPIO_FN(IRQ30),
-	GPIO_FN(IRQ53),
-	GPIO_FN(IRQ54),
-	GPIO_FN(IRQ55),
-	GPIO_FN(IRQ56),
-	GPIO_FN(IRQ57),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.7.10.4

[PATCH 24/28] ARM: shmobile: r8a73a4: Remove SCIF function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove SCIF function GPIOs that have been deprecated by the pinctrl API.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |   45 -------------------------
 1 file changed, 45 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 2d4af4a..703387a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -200,55 +200,45 @@ enum {
 
 	/* Port19 */
 	GPIO_FN_LCDD19,
-	GPIO_FN_SCIFB3_RTS_19,
 	GPIO_FN_DU0_DB3,
 
 	/* Port20 */
 	GPIO_FN_LCDD20,
-	GPIO_FN_SCIFB3_CTS_20,
 	GPIO_FN_DU0_DB4,
 
 	/* Port21 */
 	GPIO_FN_LCDD21,
-	GPIO_FN_SCIFB3_TXD_21,
 	GPIO_FN_DU0_DB5,
 
 	/* Port22 */
 	GPIO_FN_LCDD22,
-	GPIO_FN_SCIFB3_RXD_22,
 	GPIO_FN_DU0_DB6,
 
 	/* Port23 */
 	GPIO_FN_LCDD23,
-	GPIO_FN_SCIFB3_SCK_23,
 	GPIO_FN_DU0_DB7,
 
 	/* Port24 */
 	GPIO_FN_LCDHSYN,
 	GPIO_FN_LCDCS,
-	GPIO_FN_SCIFB1_RTS_24,
 	GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N,
 
 	/* Port25 */
 	GPIO_FN_LCDVSYN,
-	GPIO_FN_SCIFB1_CTS_25,
 	GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N,
 
 	/* Port26 */
 	GPIO_FN_LCDDCK,
 	GPIO_FN_LCDWR,
-	GPIO_FN_SCIFB1_TXD_26,
 	GPIO_FN_DU0_DOTCLKIN,
 
 	/* Port27 */
 	GPIO_FN_LCDDISP,
 	GPIO_FN_LCDRS,
-	GPIO_FN_SCIFB1_RXD_27,
 	GPIO_FN_DU0_DOTCLKOUT,
 
 	/* Port28 */
 	GPIO_FN_LCDRD_N,
-	GPIO_FN_SCIFB1_SCK_28,
 	GPIO_FN_DU0_DOTCLKOUTB,
 
 	/* Port29 */
@@ -262,48 +252,36 @@ enum {
 	GPIO_FN_DU0_ODDF_N_CLAMP,
 
 	/* Port32 */
-	GPIO_FN_SCIFA0_RTS,
 	GPIO_FN_SIM0_DET,
 	GPIO_FN_CSCIF0_RTS,
 
 	/* Port33 */
-	GPIO_FN_SCIFA0_CTS,
 	GPIO_FN_SIM1_DET,
 	GPIO_FN_CSCIF0_CTS,
 
 	/* Port34 */
-	GPIO_FN_SCIFA0_SCK,
 	GPIO_FN_SIM0_PWRON,
 	GPIO_FN_CSCIF0_SCK,
 
 	/* Port35 */
-	GPIO_FN_SCIFA1_RTS,
 	GPIO_FN_CSCIF1_RTS,
 
 	/* Port36 */
-	GPIO_FN_SCIFA1_CTS,
 	GPIO_FN_CSCIF1_CTS,
 
 	/* Port37 */
-	GPIO_FN_SCIFA1_SCK,
 	GPIO_FN_CSCIF1_SCK,
 
 	/* Port38 */
-	GPIO_FN_SCIFB0_RTS,
 	GPIO_FN_TPU0TO1,
-	GPIO_FN_SCIFB3_RTS_38,
 	GPIO_FN_CHSCIF0_HRTS,
 
 	/* Port39 */
-	GPIO_FN_SCIFB0_CTS,
 	GPIO_FN_TPU0TO2,
-	GPIO_FN_SCIFB3_CTS_39,
 	GPIO_FN_CHSCIF0_HCTS,
 
 	/* Port40 */
-	GPIO_FN_SCIFB0_SCK,
 	GPIO_FN_TPU0TO3,
-	GPIO_FN_SCIFB3_SCK_40,
 	GPIO_FN_CHSCIF0_HSCK,
 
 	/* Port64 */
@@ -314,52 +292,44 @@ enum {
 
 	/* Port66 */
 	GPIO_FN_HSI_RX_WAKE,
-	GPIO_FN_SCIFB2_CTS_66,
 	GPIO_FN_MSIOF3_SYNC,
 	GPIO_FN_GenIO4,
 	GPIO_FN_IRQ40,
 
 	/* Port67 */
 	GPIO_FN_HSI_RX_READY,
-	GPIO_FN_SCIFB1_TXD_67,
 	GPIO_FN_GIO_OUT3_67,
 	GPIO_FN_CHSCIF1_HTX,
 
 	/* Port68 */
 	GPIO_FN_HSI_RX_FLAG,
-	GPIO_FN_SCIFB2_TXD_68,
 	GPIO_FN_MSIOF3_TXD,
 	GPIO_FN_GIO_OUT4_68,
 
 	/* Port69 */
 	GPIO_FN_HSI_RX_DATA,
-	GPIO_FN_SCIFB2_RXD_69,
 	GPIO_FN_MSIOF3_RXD,
 	GPIO_FN_GIO_OUT5_69,
 
 	/* Port70 */
 	GPIO_FN_HSI_TX_FLAG,
-	GPIO_FN_SCIFB1_RTS_70,
 	GPIO_FN_GIO_OUT1_70,
 	GPIO_FN_HSIC_TSTCLK0,
 	GPIO_FN_CHSCIF1_HRTS,
 
 	/* Port71 */
 	GPIO_FN_HSI_TX_DATA,
-	GPIO_FN_SCIFB1_CTS_71,
 	GPIO_FN_GIO_OUT2_71,
 	GPIO_FN_HSIC_TSTCLK1,
 	GPIO_FN_CHSCIF1_HCTS,
 
 	/* Port72 */
 	GPIO_FN_HSI_TX_WAKE,
-	GPIO_FN_SCIFB1_RXD_72,
 	GPIO_FN_GenIO8,
 	GPIO_FN_CHSCIF1_HRX,
 
 	/* Port73 */
 	GPIO_FN_HSI_TX_READY,
-	GPIO_FN_SCIFB2_RTS_73,
 	GPIO_FN_MSIOF3_SCK,
 	GPIO_FN_GIO_OUT0_73,
 
@@ -438,36 +408,28 @@ enum {
 	GPIO_FN_IRQ49,
 
 	/* Port116 */
-	GPIO_FN_SCIFA0_TXD,
 	GPIO_FN_CSCIF0_TX,
 
 	/* Port117 */
-	GPIO_FN_SCIFA0_RXD,
 	GPIO_FN_CSCIF0_RX,
 
 	/* Port118 */
-	GPIO_FN_SCIFA1_TXD,
 	GPIO_FN_CSCIF1_TX,
 
 	/* Port119 */
-	GPIO_FN_SCIFA1_RXD,
 	GPIO_FN_CSCIF1_RX,
 
 	/* Port120 */
 	GPIO_FN_SF_PORT_1_120,
-	GPIO_FN_SCIFB3_RXD_120,
 	GPIO_FN_DU0_CDE,
 
 	/* Port121 */
 	GPIO_FN_SF_PORT_0_121,
-	GPIO_FN_SCIFB3_TXD_121,
 
 	/* Port122 */
-	GPIO_FN_SCIFB0_TXD,
 	GPIO_FN_CHSCIF0_HTX,
 
 	/* Port123 */
-	GPIO_FN_SCIFB0_RXD,
 	GPIO_FN_CHSCIF0_HRX,
 
 	/* Port124 */
@@ -761,11 +723,9 @@ enum {
 	GPIO_FN_MSIOF0_TXD,
 
 	/* Port261 */
-	GPIO_FN_SCIFB1_SCK_261,
 	GPIO_FN_CHSCIF1_HSCK,
 
 	/* Port262 */
-	GPIO_FN_SCIFB2_SCK_262,
 
 	/* Port263 - Port266 FN1 */
 	GPIO_FN_MSIOF1_SS2,
@@ -849,7 +809,6 @@ enum {
 	/* Port295 */
 	GPIO_FN_SDHID2_0,
 	GPIO_FN_MSIOF4_TXD,
-	GPIO_FN_SCIFB2_TXD_295,
 	GPIO_FN_MSIOF6_TXD,
 
 	/* Port296 */
@@ -870,10 +829,6 @@ enum {
 	GPIO_FN_MSIOF4_SS1,
 
 	/* Port297 - Port300 FN3 */
-	GPIO_FN_SCIFB2_RXD_297,
-	GPIO_FN_SCIFB2_CTS_298,
-	GPIO_FN_SCIFB2_SCK_299,
-	GPIO_FN_SCIFB2_RTS_300,
 
 	/* Port297 - Port300 FN4 */
 	GPIO_FN_MSIOF6_RXD,
-- 
1.7.10.4

[PATCH 24/28] ARM: shmobile: r8a73a4: Remove SCIF function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove SCIF function GPIOs that have been deprecated by the pinctrl API.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |   45 -------------------------
 1 file changed, 45 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 2d4af4a..703387a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -200,55 +200,45 @@ enum {
 
 	/* Port19 */
 	GPIO_FN_LCDD19,
-	GPIO_FN_SCIFB3_RTS_19,
 	GPIO_FN_DU0_DB3,
 
 	/* Port20 */
 	GPIO_FN_LCDD20,
-	GPIO_FN_SCIFB3_CTS_20,
 	GPIO_FN_DU0_DB4,
 
 	/* Port21 */
 	GPIO_FN_LCDD21,
-	GPIO_FN_SCIFB3_TXD_21,
 	GPIO_FN_DU0_DB5,
 
 	/* Port22 */
 	GPIO_FN_LCDD22,
-	GPIO_FN_SCIFB3_RXD_22,
 	GPIO_FN_DU0_DB6,
 
 	/* Port23 */
 	GPIO_FN_LCDD23,
-	GPIO_FN_SCIFB3_SCK_23,
 	GPIO_FN_DU0_DB7,
 
 	/* Port24 */
 	GPIO_FN_LCDHSYN,
 	GPIO_FN_LCDCS,
-	GPIO_FN_SCIFB1_RTS_24,
 	GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N,
 
 	/* Port25 */
 	GPIO_FN_LCDVSYN,
-	GPIO_FN_SCIFB1_CTS_25,
 	GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N,
 
 	/* Port26 */
 	GPIO_FN_LCDDCK,
 	GPIO_FN_LCDWR,
-	GPIO_FN_SCIFB1_TXD_26,
 	GPIO_FN_DU0_DOTCLKIN,
 
 	/* Port27 */
 	GPIO_FN_LCDDISP,
 	GPIO_FN_LCDRS,
-	GPIO_FN_SCIFB1_RXD_27,
 	GPIO_FN_DU0_DOTCLKOUT,
 
 	/* Port28 */
 	GPIO_FN_LCDRD_N,
-	GPIO_FN_SCIFB1_SCK_28,
 	GPIO_FN_DU0_DOTCLKOUTB,
 
 	/* Port29 */
@@ -262,48 +252,36 @@ enum {
 	GPIO_FN_DU0_ODDF_N_CLAMP,
 
 	/* Port32 */
-	GPIO_FN_SCIFA0_RTS,
 	GPIO_FN_SIM0_DET,
 	GPIO_FN_CSCIF0_RTS,
 
 	/* Port33 */
-	GPIO_FN_SCIFA0_CTS,
 	GPIO_FN_SIM1_DET,
 	GPIO_FN_CSCIF0_CTS,
 
 	/* Port34 */
-	GPIO_FN_SCIFA0_SCK,
 	GPIO_FN_SIM0_PWRON,
 	GPIO_FN_CSCIF0_SCK,
 
 	/* Port35 */
-	GPIO_FN_SCIFA1_RTS,
 	GPIO_FN_CSCIF1_RTS,
 
 	/* Port36 */
-	GPIO_FN_SCIFA1_CTS,
 	GPIO_FN_CSCIF1_CTS,
 
 	/* Port37 */
-	GPIO_FN_SCIFA1_SCK,
 	GPIO_FN_CSCIF1_SCK,
 
 	/* Port38 */
-	GPIO_FN_SCIFB0_RTS,
 	GPIO_FN_TPU0TO1,
-	GPIO_FN_SCIFB3_RTS_38,
 	GPIO_FN_CHSCIF0_HRTS,
 
 	/* Port39 */
-	GPIO_FN_SCIFB0_CTS,
 	GPIO_FN_TPU0TO2,
-	GPIO_FN_SCIFB3_CTS_39,
 	GPIO_FN_CHSCIF0_HCTS,
 
 	/* Port40 */
-	GPIO_FN_SCIFB0_SCK,
 	GPIO_FN_TPU0TO3,
-	GPIO_FN_SCIFB3_SCK_40,
 	GPIO_FN_CHSCIF0_HSCK,
 
 	/* Port64 */
@@ -314,52 +292,44 @@ enum {
 
 	/* Port66 */
 	GPIO_FN_HSI_RX_WAKE,
-	GPIO_FN_SCIFB2_CTS_66,
 	GPIO_FN_MSIOF3_SYNC,
 	GPIO_FN_GenIO4,
 	GPIO_FN_IRQ40,
 
 	/* Port67 */
 	GPIO_FN_HSI_RX_READY,
-	GPIO_FN_SCIFB1_TXD_67,
 	GPIO_FN_GIO_OUT3_67,
 	GPIO_FN_CHSCIF1_HTX,
 
 	/* Port68 */
 	GPIO_FN_HSI_RX_FLAG,
-	GPIO_FN_SCIFB2_TXD_68,
 	GPIO_FN_MSIOF3_TXD,
 	GPIO_FN_GIO_OUT4_68,
 
 	/* Port69 */
 	GPIO_FN_HSI_RX_DATA,
-	GPIO_FN_SCIFB2_RXD_69,
 	GPIO_FN_MSIOF3_RXD,
 	GPIO_FN_GIO_OUT5_69,
 
 	/* Port70 */
 	GPIO_FN_HSI_TX_FLAG,
-	GPIO_FN_SCIFB1_RTS_70,
 	GPIO_FN_GIO_OUT1_70,
 	GPIO_FN_HSIC_TSTCLK0,
 	GPIO_FN_CHSCIF1_HRTS,
 
 	/* Port71 */
 	GPIO_FN_HSI_TX_DATA,
-	GPIO_FN_SCIFB1_CTS_71,
 	GPIO_FN_GIO_OUT2_71,
 	GPIO_FN_HSIC_TSTCLK1,
 	GPIO_FN_CHSCIF1_HCTS,
 
 	/* Port72 */
 	GPIO_FN_HSI_TX_WAKE,
-	GPIO_FN_SCIFB1_RXD_72,
 	GPIO_FN_GenIO8,
 	GPIO_FN_CHSCIF1_HRX,
 
 	/* Port73 */
 	GPIO_FN_HSI_TX_READY,
-	GPIO_FN_SCIFB2_RTS_73,
 	GPIO_FN_MSIOF3_SCK,
 	GPIO_FN_GIO_OUT0_73,
 
@@ -438,36 +408,28 @@ enum {
 	GPIO_FN_IRQ49,
 
 	/* Port116 */
-	GPIO_FN_SCIFA0_TXD,
 	GPIO_FN_CSCIF0_TX,
 
 	/* Port117 */
-	GPIO_FN_SCIFA0_RXD,
 	GPIO_FN_CSCIF0_RX,
 
 	/* Port118 */
-	GPIO_FN_SCIFA1_TXD,
 	GPIO_FN_CSCIF1_TX,
 
 	/* Port119 */
-	GPIO_FN_SCIFA1_RXD,
 	GPIO_FN_CSCIF1_RX,
 
 	/* Port120 */
 	GPIO_FN_SF_PORT_1_120,
-	GPIO_FN_SCIFB3_RXD_120,
 	GPIO_FN_DU0_CDE,
 
 	/* Port121 */
 	GPIO_FN_SF_PORT_0_121,
-	GPIO_FN_SCIFB3_TXD_121,
 
 	/* Port122 */
-	GPIO_FN_SCIFB0_TXD,
 	GPIO_FN_CHSCIF0_HTX,
 
 	/* Port123 */
-	GPIO_FN_SCIFB0_RXD,
 	GPIO_FN_CHSCIF0_HRX,
 
 	/* Port124 */
@@ -761,11 +723,9 @@ enum {
 	GPIO_FN_MSIOF0_TXD,
 
 	/* Port261 */
-	GPIO_FN_SCIFB1_SCK_261,
 	GPIO_FN_CHSCIF1_HSCK,
 
 	/* Port262 */
-	GPIO_FN_SCIFB2_SCK_262,
 
 	/* Port263 - Port266 FN1 */
 	GPIO_FN_MSIOF1_SS2,
@@ -849,7 +809,6 @@ enum {
 	/* Port295 */
 	GPIO_FN_SDHID2_0,
 	GPIO_FN_MSIOF4_TXD,
-	GPIO_FN_SCIFB2_TXD_295,
 	GPIO_FN_MSIOF6_TXD,
 
 	/* Port296 */
@@ -870,10 +829,6 @@ enum {
 	GPIO_FN_MSIOF4_SS1,
 
 	/* Port297 - Port300 FN3 */
-	GPIO_FN_SCIFB2_RXD_297,
-	GPIO_FN_SCIFB2_CTS_298,
-	GPIO_FN_SCIFB2_SCK_299,
-	GPIO_FN_SCIFB2_RTS_300,
 
 	/* Port297 - Port300 FN4 */
 	GPIO_FN_MSIOF6_RXD,
-- 
1.7.10.4

[PATCH 25/28] ARM: shmobile: r8a73a4: Remove IRQC function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove IRQ pin function GPIOs that have been deprecated by the pinctrl
API.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |   58 -------------------------
 1 file changed, 58 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 703387a..9162e86 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -89,99 +89,83 @@ enum {
 	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
-	GPIO_FN_IRQ0,
 
 	/* Port1 */
 	GPIO_FN_LCDD1,
 	GPIO_FN_PDM2_DATA_1,
 	GPIO_FN_DU0_DR19,
-	GPIO_FN_IRQ1,
 
 	/* Port2 */
 	GPIO_FN_LCDD2,
 	GPIO_FN_PDM3_CLK_2,
 	GPIO_FN_DU0_DR2,
-	GPIO_FN_IRQ2,
 
 	/* Port3 */
 	GPIO_FN_LCDD3,
 	GPIO_FN_PDM3_DATA_3,
 	GPIO_FN_DU0_DR3,
-	GPIO_FN_IRQ3,
 
 	/* Port4 */
 	GPIO_FN_LCDD4,
 	GPIO_FN_PDM4_CLK_4,
 	GPIO_FN_DU0_DR4,
-	GPIO_FN_IRQ4,
 
 	/* Port5 */
 	GPIO_FN_LCDD5,
 	GPIO_FN_PDM4_DATA_5,
 	GPIO_FN_DU0_DR5,
-	GPIO_FN_IRQ5,
 
 	/* Port6 */
 	GPIO_FN_LCDD6,
 	GPIO_FN_PDM0_OUTCLK_6,
 	GPIO_FN_DU0_DR6,
-	GPIO_FN_IRQ6,
 
 	/* Port7 */
 	GPIO_FN_LCDD7,
 	GPIO_FN_PDM0_OUTDATA_7,
 	GPIO_FN_DU0_DR7,
-	GPIO_FN_IRQ7,
 
 	/* Port8 */
 	GPIO_FN_LCDD8,
 	GPIO_FN_PDM1_OUTCLK_8,
 	GPIO_FN_DU0_DG0,
-	GPIO_FN_IRQ8,
 
 	/* Port9 */
 	GPIO_FN_LCDD9,
 	GPIO_FN_PDM1_OUTDATA_9,
 	GPIO_FN_DU0_DG1,
-	GPIO_FN_IRQ9,
 
 	/* Port10 */
 	GPIO_FN_LCDD10,
 	GPIO_FN_FSICCK,
 	GPIO_FN_DU0_DG2,
-	GPIO_FN_IRQ10,
 
 	/* Port11 */
 	GPIO_FN_LCDD11,
 	GPIO_FN_FSICISLD,
 	GPIO_FN_DU0_DG3,
-	GPIO_FN_IRQ11,
 
 	/* Port12 */
 	GPIO_FN_LCDD12,
 	GPIO_FN_FSICOMC,
 	GPIO_FN_DU0_DG4,
-	GPIO_FN_IRQ12,
 
 	/* Port13 */
 	GPIO_FN_LCDD13,
 	GPIO_FN_FSICOLR,
 	GPIO_FN_FSICILR,
 	GPIO_FN_DU0_DG5,
-	GPIO_FN_IRQ13,
 
 	/* Port14 */
 	GPIO_FN_LCDD14,
 	GPIO_FN_FSICOBT,
 	GPIO_FN_FSICIBT,
 	GPIO_FN_DU0_DG6,
-	GPIO_FN_IRQ14,
 
 	/* Port15 */
 	GPIO_FN_LCDD15,
 	GPIO_FN_FSICOSLD,
 	GPIO_FN_DU0_DG7,
-	GPIO_FN_IRQ15,
 
 	/* Port16 */
 	GPIO_FN_LCDD16,
@@ -294,7 +278,6 @@ enum {
 	GPIO_FN_HSI_RX_WAKE,
 	GPIO_FN_MSIOF3_SYNC,
 	GPIO_FN_GenIO4,
-	GPIO_FN_IRQ40,
 
 	/* Port67 */
 	GPIO_FN_HSI_RX_READY,
@@ -344,8 +327,6 @@ enum {
 	GPIO_FN_TXP2,
 	GPIO_FN_COEX_0,
 	GPIO_FN_COEX_1,
-	GPIO_FN_IRQ19,
-	GPIO_FN_IRQ18,
 
 	/* Port96 - Port101 */
 	GPIO_FN_KEYIN0,
@@ -357,11 +338,9 @@ enum {
 
 	/* Port102 */
 	GPIO_FN_KEYIN6,
-	GPIO_FN_IRQ41,
 
 	/* Port103 */
 	GPIO_FN_KEYIN7,
-	GPIO_FN_IRQ42,
 
 	/* Port104 - Port108 */
 	GPIO_FN_KEYOUT0,
@@ -372,40 +351,33 @@ enum {
 
 	/* Port109 */
 	GPIO_FN_KEYOUT5,
-	GPIO_FN_IRQ43,
 
 	/* Port110 */
 	GPIO_FN_KEYOUT6,
-	GPIO_FN_IRQ44,
 
 	/* Port111 */
 	GPIO_FN_KEYOUT7,
 	GPIO_FN_RFANAEN,
-	GPIO_FN_IRQ45,
 
 	/* Port112 */
 	GPIO_FN_KEYIN8,
 	GPIO_FN_KEYOUT8,
 	GPIO_FN_SF_IRQ_04,
-	GPIO_FN_IRQ46,
 
 	/* Port113 */
 	GPIO_FN_KEYIN9,
 	GPIO_FN_KEYOUT9,
 	GPIO_FN_SF_IRQ_05,
-	GPIO_FN_IRQ47,
 
 	/* Port114 */
 	GPIO_FN_KEYIN10,
 	GPIO_FN_KEYOUT10,
 	GPIO_FN_SF_IRQ_06,
-	GPIO_FN_IRQ48,
 
 	/* Port115 */
 	GPIO_FN_KEYIN11,
 	GPIO_FN_KEYOUT11,
 	GPIO_FN_SF_IRQ_07,
-	GPIO_FN_IRQ49,
 
 	/* Port116 */
 	GPIO_FN_CSCIF0_TX,
@@ -484,10 +456,6 @@ enum {
 	GPIO_FN_STP_ISD_1,
 
 	/* Port160 - Port178 */
-	GPIO_FN_IRQ20,
-	GPIO_FN_IRQ21,
-	GPIO_FN_IRQ22,
-	GPIO_FN_IRQ23,
 	GPIO_FN_MMCD0_0,
 	GPIO_FN_MMCD0_1,
 	GPIO_FN_MMCD0_2,
@@ -499,10 +467,6 @@ enum {
 	GPIO_FN_MMCCMD0,
 	GPIO_FN_MMCCLK0,
 	GPIO_FN_MMCRST,
-	GPIO_FN_IRQ24,
-	GPIO_FN_IRQ25,
-	GPIO_FN_IRQ26,
-	GPIO_FN_IRQ27,
 
 	/* Port192 - Port200 FN1 */
 	GPIO_FN_A10,
@@ -527,15 +491,6 @@ enum {
 	GPIO_FN_MMCCMD1,
 
 	/* Port192 - Port200 IRQ */
-	GPIO_FN_IRQ31,
-	GPIO_FN_IRQ32,
-	GPIO_FN_IRQ33,
-	GPIO_FN_IRQ34,
-	GPIO_FN_IRQ35,
-	GPIO_FN_IRQ36,
-	GPIO_FN_IRQ37,
-	GPIO_FN_IRQ38,
-	GPIO_FN_IRQ39,
 
 	/* Port201 */
 	GPIO_FN_A1,
@@ -792,7 +747,6 @@ enum {
 	/* Port290 */
 	GPIO_FN_SDHID1_1,
 	GPIO_FN_STMDATA1_2,
-	GPIO_FN_IRQ51,
 
 	/* Port291 - Port294 FN1 */
 	GPIO_FN_SDHID1_2,
@@ -814,7 +768,6 @@ enum {
 	/* Port296 */
 	GPIO_FN_SDHID2_1,
 	GPIO_FN_MSIOF6_SS2,
-	GPIO_FN_IRQ52,
 
 	/* Port297 - Port300 FN1 */
 	GPIO_FN_SDHID2_2,
@@ -838,7 +791,6 @@ enum {
 
 	/* Port301 */
 	GPIO_FN_SDHICD0,
-	GPIO_FN_IRQ50,
 
 	/* Port302 - Port306 FN1 */
 	GPIO_FN_SDHID0_0,
@@ -862,16 +814,6 @@ enum {
 	GPIO_FN_STMCLK_1,
 
 	/* Port320 - Port329 */
-	GPIO_FN_IRQ16,
-	GPIO_FN_IRQ17,
-	GPIO_FN_IRQ28,
-	GPIO_FN_IRQ29,
-	GPIO_FN_IRQ30,
-	GPIO_FN_IRQ53,
-	GPIO_FN_IRQ54,
-	GPIO_FN_IRQ55,
-	GPIO_FN_IRQ56,
-	GPIO_FN_IRQ57,
 };
 
 void r8a73a4_add_standard_devices(void);
-- 
1.7.10.4

[PATCH 25/28] ARM: shmobile: r8a73a4: Remove IRQC function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove IRQ pin function GPIOs that have been deprecated by the pinctrl
API.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |   58 -------------------------
 1 file changed, 58 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 703387a..9162e86 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -89,99 +89,83 @@ enum {
 	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
-	GPIO_FN_IRQ0,
 
 	/* Port1 */
 	GPIO_FN_LCDD1,
 	GPIO_FN_PDM2_DATA_1,
 	GPIO_FN_DU0_DR19,
-	GPIO_FN_IRQ1,
 
 	/* Port2 */
 	GPIO_FN_LCDD2,
 	GPIO_FN_PDM3_CLK_2,
 	GPIO_FN_DU0_DR2,
-	GPIO_FN_IRQ2,
 
 	/* Port3 */
 	GPIO_FN_LCDD3,
 	GPIO_FN_PDM3_DATA_3,
 	GPIO_FN_DU0_DR3,
-	GPIO_FN_IRQ3,
 
 	/* Port4 */
 	GPIO_FN_LCDD4,
 	GPIO_FN_PDM4_CLK_4,
 	GPIO_FN_DU0_DR4,
-	GPIO_FN_IRQ4,
 
 	/* Port5 */
 	GPIO_FN_LCDD5,
 	GPIO_FN_PDM4_DATA_5,
 	GPIO_FN_DU0_DR5,
-	GPIO_FN_IRQ5,
 
 	/* Port6 */
 	GPIO_FN_LCDD6,
 	GPIO_FN_PDM0_OUTCLK_6,
 	GPIO_FN_DU0_DR6,
-	GPIO_FN_IRQ6,
 
 	/* Port7 */
 	GPIO_FN_LCDD7,
 	GPIO_FN_PDM0_OUTDATA_7,
 	GPIO_FN_DU0_DR7,
-	GPIO_FN_IRQ7,
 
 	/* Port8 */
 	GPIO_FN_LCDD8,
 	GPIO_FN_PDM1_OUTCLK_8,
 	GPIO_FN_DU0_DG0,
-	GPIO_FN_IRQ8,
 
 	/* Port9 */
 	GPIO_FN_LCDD9,
 	GPIO_FN_PDM1_OUTDATA_9,
 	GPIO_FN_DU0_DG1,
-	GPIO_FN_IRQ9,
 
 	/* Port10 */
 	GPIO_FN_LCDD10,
 	GPIO_FN_FSICCK,
 	GPIO_FN_DU0_DG2,
-	GPIO_FN_IRQ10,
 
 	/* Port11 */
 	GPIO_FN_LCDD11,
 	GPIO_FN_FSICISLD,
 	GPIO_FN_DU0_DG3,
-	GPIO_FN_IRQ11,
 
 	/* Port12 */
 	GPIO_FN_LCDD12,
 	GPIO_FN_FSICOMC,
 	GPIO_FN_DU0_DG4,
-	GPIO_FN_IRQ12,
 
 	/* Port13 */
 	GPIO_FN_LCDD13,
 	GPIO_FN_FSICOLR,
 	GPIO_FN_FSICILR,
 	GPIO_FN_DU0_DG5,
-	GPIO_FN_IRQ13,
 
 	/* Port14 */
 	GPIO_FN_LCDD14,
 	GPIO_FN_FSICOBT,
 	GPIO_FN_FSICIBT,
 	GPIO_FN_DU0_DG6,
-	GPIO_FN_IRQ14,
 
 	/* Port15 */
 	GPIO_FN_LCDD15,
 	GPIO_FN_FSICOSLD,
 	GPIO_FN_DU0_DG7,
-	GPIO_FN_IRQ15,
 
 	/* Port16 */
 	GPIO_FN_LCDD16,
@@ -294,7 +278,6 @@ enum {
 	GPIO_FN_HSI_RX_WAKE,
 	GPIO_FN_MSIOF3_SYNC,
 	GPIO_FN_GenIO4,
-	GPIO_FN_IRQ40,
 
 	/* Port67 */
 	GPIO_FN_HSI_RX_READY,
@@ -344,8 +327,6 @@ enum {
 	GPIO_FN_TXP2,
 	GPIO_FN_COEX_0,
 	GPIO_FN_COEX_1,
-	GPIO_FN_IRQ19,
-	GPIO_FN_IRQ18,
 
 	/* Port96 - Port101 */
 	GPIO_FN_KEYIN0,
@@ -357,11 +338,9 @@ enum {
 
 	/* Port102 */
 	GPIO_FN_KEYIN6,
-	GPIO_FN_IRQ41,
 
 	/* Port103 */
 	GPIO_FN_KEYIN7,
-	GPIO_FN_IRQ42,
 
 	/* Port104 - Port108 */
 	GPIO_FN_KEYOUT0,
@@ -372,40 +351,33 @@ enum {
 
 	/* Port109 */
 	GPIO_FN_KEYOUT5,
-	GPIO_FN_IRQ43,
 
 	/* Port110 */
 	GPIO_FN_KEYOUT6,
-	GPIO_FN_IRQ44,
 
 	/* Port111 */
 	GPIO_FN_KEYOUT7,
 	GPIO_FN_RFANAEN,
-	GPIO_FN_IRQ45,
 
 	/* Port112 */
 	GPIO_FN_KEYIN8,
 	GPIO_FN_KEYOUT8,
 	GPIO_FN_SF_IRQ_04,
-	GPIO_FN_IRQ46,
 
 	/* Port113 */
 	GPIO_FN_KEYIN9,
 	GPIO_FN_KEYOUT9,
 	GPIO_FN_SF_IRQ_05,
-	GPIO_FN_IRQ47,
 
 	/* Port114 */
 	GPIO_FN_KEYIN10,
 	GPIO_FN_KEYOUT10,
 	GPIO_FN_SF_IRQ_06,
-	GPIO_FN_IRQ48,
 
 	/* Port115 */
 	GPIO_FN_KEYIN11,
 	GPIO_FN_KEYOUT11,
 	GPIO_FN_SF_IRQ_07,
-	GPIO_FN_IRQ49,
 
 	/* Port116 */
 	GPIO_FN_CSCIF0_TX,
@@ -484,10 +456,6 @@ enum {
 	GPIO_FN_STP_ISD_1,
 
 	/* Port160 - Port178 */
-	GPIO_FN_IRQ20,
-	GPIO_FN_IRQ21,
-	GPIO_FN_IRQ22,
-	GPIO_FN_IRQ23,
 	GPIO_FN_MMCD0_0,
 	GPIO_FN_MMCD0_1,
 	GPIO_FN_MMCD0_2,
@@ -499,10 +467,6 @@ enum {
 	GPIO_FN_MMCCMD0,
 	GPIO_FN_MMCCLK0,
 	GPIO_FN_MMCRST,
-	GPIO_FN_IRQ24,
-	GPIO_FN_IRQ25,
-	GPIO_FN_IRQ26,
-	GPIO_FN_IRQ27,
 
 	/* Port192 - Port200 FN1 */
 	GPIO_FN_A10,
@@ -527,15 +491,6 @@ enum {
 	GPIO_FN_MMCCMD1,
 
 	/* Port192 - Port200 IRQ */
-	GPIO_FN_IRQ31,
-	GPIO_FN_IRQ32,
-	GPIO_FN_IRQ33,
-	GPIO_FN_IRQ34,
-	GPIO_FN_IRQ35,
-	GPIO_FN_IRQ36,
-	GPIO_FN_IRQ37,
-	GPIO_FN_IRQ38,
-	GPIO_FN_IRQ39,
 
 	/* Port201 */
 	GPIO_FN_A1,
@@ -792,7 +747,6 @@ enum {
 	/* Port290 */
 	GPIO_FN_SDHID1_1,
 	GPIO_FN_STMDATA1_2,
-	GPIO_FN_IRQ51,
 
 	/* Port291 - Port294 FN1 */
 	GPIO_FN_SDHID1_2,
@@ -814,7 +768,6 @@ enum {
 	/* Port296 */
 	GPIO_FN_SDHID2_1,
 	GPIO_FN_MSIOF6_SS2,
-	GPIO_FN_IRQ52,
 
 	/* Port297 - Port300 FN1 */
 	GPIO_FN_SDHID2_2,
@@ -838,7 +791,6 @@ enum {
 
 	/* Port301 */
 	GPIO_FN_SDHICD0,
-	GPIO_FN_IRQ50,
 
 	/* Port302 - Port306 FN1 */
 	GPIO_FN_SDHID0_0,
@@ -862,16 +814,6 @@ enum {
 	GPIO_FN_STMCLK_1,
 
 	/* Port320 - Port329 */
-	GPIO_FN_IRQ16,
-	GPIO_FN_IRQ17,
-	GPIO_FN_IRQ28,
-	GPIO_FN_IRQ29,
-	GPIO_FN_IRQ30,
-	GPIO_FN_IRQ53,
-	GPIO_FN_IRQ54,
-	GPIO_FN_IRQ55,
-	GPIO_FN_IRQ56,
-	GPIO_FN_IRQ57,
 };
 
 void r8a73a4_add_standard_devices(void);
-- 
1.7.10.4

[PATCH 26/28] sh-pfc: r8a73a4: Remove function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

All r8a73a4 platforms use the pinctrl API to control pin functions.
Function GPIOs are no longer needed.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  737 ----------------------------------
 1 file changed, 737 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 66fc747..464c5f9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2042,740 +2042,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb3),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* Port0 */
-	GPIO_FN(LCDD0),
-	GPIO_FN(PDM2_CLK_0),
-	GPIO_FN(DU0_DR0),
-
-	/* Port1 */
-	GPIO_FN(LCDD1),
-	GPIO_FN(PDM2_DATA_1),
-	GPIO_FN(DU0_DR19),
-
-	/* Port2 */
-	GPIO_FN(LCDD2),
-	GPIO_FN(PDM3_CLK_2),
-	GPIO_FN(DU0_DR2),
-
-	/* Port3 */
-	GPIO_FN(LCDD3),
-	GPIO_FN(PDM3_DATA_3),
-	GPIO_FN(DU0_DR3),
-
-	/* Port4 */
-	GPIO_FN(LCDD4),
-	GPIO_FN(PDM4_CLK_4),
-	GPIO_FN(DU0_DR4),
-
-	/* Port5 */
-	GPIO_FN(LCDD5),
-	GPIO_FN(PDM4_DATA_5),
-	GPIO_FN(DU0_DR5),
-
-	/* Port6 */
-	GPIO_FN(LCDD6),
-	GPIO_FN(PDM0_OUTCLK_6),
-	GPIO_FN(DU0_DR6),
-
-	/* Port7 */
-	GPIO_FN(LCDD7),
-	GPIO_FN(PDM0_OUTDATA_7),
-	GPIO_FN(DU0_DR7),
-
-	/* Port8 */
-	GPIO_FN(LCDD8),
-	GPIO_FN(PDM1_OUTCLK_8),
-	GPIO_FN(DU0_DG0),
-
-	/* Port9 */
-	GPIO_FN(LCDD9),
-	GPIO_FN(PDM1_OUTDATA_9),
-	GPIO_FN(DU0_DG1),
-
-	/* Port10 */
-	GPIO_FN(LCDD10),
-	GPIO_FN(FSICCK),
-	GPIO_FN(DU0_DG2),
-
-	/* Port11 */
-	GPIO_FN(LCDD11),
-	GPIO_FN(FSICISLD),
-	GPIO_FN(DU0_DG3),
-
-	/* Port12 */
-	GPIO_FN(LCDD12),
-	GPIO_FN(FSICOMC),
-	GPIO_FN(DU0_DG4),
-
-	/* Port13 */
-	GPIO_FN(LCDD13),
-	GPIO_FN(FSICOLR),
-	GPIO_FN(FSICILR),
-	GPIO_FN(DU0_DG5),
-
-	/* Port14 */
-	GPIO_FN(LCDD14),
-	GPIO_FN(FSICOBT),
-	GPIO_FN(FSICIBT),
-	GPIO_FN(DU0_DG6),
-
-	/* Port15 */
-	GPIO_FN(LCDD15),
-	GPIO_FN(FSICOSLD),
-	GPIO_FN(DU0_DG7),
-
-	/* Port16 */
-	GPIO_FN(LCDD16),
-	GPIO_FN(TPU1TO1),
-	GPIO_FN(DU0_DB0),
-
-	/* Port17 */
-	GPIO_FN(LCDD17),
-	GPIO_FN(SF_IRQ_00),
-	GPIO_FN(DU0_DB1),
-
-	/* Port18 */
-	GPIO_FN(LCDD18),
-	GPIO_FN(SF_IRQ_01),
-	GPIO_FN(DU0_DB2),
-
-	/* Port19 */
-	GPIO_FN(LCDD19),
-	GPIO_FN(DU0_DB3),
-
-	/* Port20 */
-	GPIO_FN(LCDD20),
-	GPIO_FN(DU0_DB4),
-
-	/* Port21 */
-	GPIO_FN(LCDD21),
-	GPIO_FN(DU0_DB5),
-
-	/* Port22 */
-	GPIO_FN(LCDD22),
-	GPIO_FN(DU0_DB6),
-
-	/* Port23 */
-	GPIO_FN(LCDD23),
-	GPIO_FN(DU0_DB7),
-
-	/* Port24 */
-	GPIO_FN(LCDHSYN),
-	GPIO_FN(LCDCS),
-	GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
-
-	/* Port25 */
-	GPIO_FN(LCDVSYN),
-	GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
-
-	/* Port26 */
-	GPIO_FN(LCDDCK),
-	GPIO_FN(LCDWR),
-	GPIO_FN(DU0_DOTCLKIN),
-
-	/* Port27 */
-	GPIO_FN(LCDDISP),
-	GPIO_FN(LCDRS),
-	GPIO_FN(DU0_DOTCLKOUT),
-
-	/* Port28 */
-	GPIO_FN(LCDRD_N),
-	GPIO_FN(DU0_DOTCLKOUTB),
-
-	/* Port29 */
-	GPIO_FN(LCDLCLK),
-	GPIO_FN(SF_IRQ_02),
-	GPIO_FN(DU0_DISP_CSYNC_N_DE),
-
-	/* Port30 */
-	GPIO_FN(LCDDON),
-	GPIO_FN(SF_IRQ_03),
-	GPIO_FN(DU0_ODDF_N_CLAMP),
-
-	/* Port32 */
-	GPIO_FN(SIM0_DET),
-	GPIO_FN(CSCIF0_RTS),
-
-	/* Port33 */
-	GPIO_FN(SIM1_DET),
-	GPIO_FN(CSCIF0_CTS),
-
-	/* Port34 */
-	GPIO_FN(SIM0_PWRON),
-	GPIO_FN(CSCIF0_SCK),
-
-	/* Port35 */
-	GPIO_FN(CSCIF1_RTS),
-
-	/* Port36 */
-	GPIO_FN(CSCIF1_CTS),
-
-	/* Port37 */
-	GPIO_FN(CSCIF1_SCK),
-
-	/* Port38 */
-	GPIO_FN(TPU0TO1),
-	GPIO_FN(CHSCIF0_HRTS),
-
-	/* Port39 */
-	GPIO_FN(TPU0TO2),
-	GPIO_FN(CHSCIF0_HCTS),
-
-	/* Port40 */
-	GPIO_FN(TPU0TO3),
-	GPIO_FN(CHSCIF0_HSCK),
-
-	/* Port64 */
-	GPIO_FN(PDM0_DATA),
-
-	/* Port65 */
-	GPIO_FN(PDM1_DATA),
-
-	/* Port66 */
-	GPIO_FN(HSI_RX_WAKE),
-	GPIO_FN(MSIOF3_SYNC),
-	GPIO_FN(GenIO4),
-
-	/* Port67 */
-	GPIO_FN(HSI_RX_READY),
-	GPIO_FN(GIO_OUT3_67),
-	GPIO_FN(CHSCIF1_HTX),
-
-	/* Port68 */
-	GPIO_FN(HSI_RX_FLAG),
-	GPIO_FN(MSIOF3_TXD),
-	GPIO_FN(GIO_OUT4_68),
-
-	/* Port69 */
-	GPIO_FN(HSI_RX_DATA),
-	GPIO_FN(MSIOF3_RXD),
-	GPIO_FN(GIO_OUT5_69),
-
-	/* Port70 */
-	GPIO_FN(HSI_TX_FLAG),
-	GPIO_FN(GIO_OUT1_70),
-	GPIO_FN(HSIC_TSTCLK0),
-	GPIO_FN(CHSCIF1_HRTS),
-
-	/* Port71 */
-	GPIO_FN(HSI_TX_DATA),
-	GPIO_FN(GIO_OUT2_71),
-	GPIO_FN(HSIC_TSTCLK1),
-	GPIO_FN(CHSCIF1_HCTS),
-
-	/* Port72 */
-	GPIO_FN(HSI_TX_WAKE),
-	GPIO_FN(GenIO8),
-	GPIO_FN(CHSCIF1_HRX),
-
-	/* Port73 */
-	GPIO_FN(HSI_TX_READY),
-	GPIO_FN(MSIOF3_SCK),
-	GPIO_FN(GIO_OUT0_73),
-
-	/* Port74 - Port85 */
-	GPIO_FN(IRDA_OUT),
-	GPIO_FN(IRDA_IN),
-	GPIO_FN(IRDA_FIRSEL),
-	GPIO_FN(TPU0TO0),
-	GPIO_FN(DIGRFEN),
-	GPIO_FN(GPS_TIMESTAMP),
-	GPIO_FN(TXP),
-	GPIO_FN(TXP2),
-	GPIO_FN(COEX_0),
-	GPIO_FN(COEX_1),
-
-	/* Port96 - Port101 */
-	GPIO_FN(KEYIN0),
-	GPIO_FN(KEYIN1),
-	GPIO_FN(KEYIN2),
-	GPIO_FN(KEYIN3),
-	GPIO_FN(KEYIN4),
-	GPIO_FN(KEYIN5),
-
-	/* Port102 */
-	GPIO_FN(KEYIN6),
-
-	/* Port103 */
-	GPIO_FN(KEYIN7),
-
-	/* Port104 - Port108 */
-	GPIO_FN(KEYOUT0),
-	GPIO_FN(KEYOUT1),
-	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT3),
-	GPIO_FN(KEYOUT4),
-
-	/* Port109 */
-	GPIO_FN(KEYOUT5),
-
-	/* Port110 */
-	GPIO_FN(KEYOUT6),
-
-	/* Port111 */
-	GPIO_FN(KEYOUT7),
-	GPIO_FN(RFANAEN),
-
-	/* Port112 */
-	GPIO_FN(KEYIN8),
-	GPIO_FN(KEYOUT8),
-	GPIO_FN(SF_IRQ_04),
-
-	/* Port113 */
-	GPIO_FN(KEYIN9),
-	GPIO_FN(KEYOUT9),
-	GPIO_FN(SF_IRQ_05),
-
-	/* Port114 */
-	GPIO_FN(KEYIN10),
-	GPIO_FN(KEYOUT10),
-	GPIO_FN(SF_IRQ_06),
-
-	/* Port115 */
-	GPIO_FN(KEYIN11),
-	GPIO_FN(KEYOUT11),
-	GPIO_FN(SF_IRQ_07),
-
-	/* Port116 */
-	GPIO_FN(CSCIF0_TX),
-
-	/* Port117 */
-	GPIO_FN(CSCIF0_RX),
-
-	/* Port118 */
-	GPIO_FN(CSCIF1_TX),
-
-	/* Port119 */
-	GPIO_FN(CSCIF1_RX),
-
-	/* Port120 */
-	GPIO_FN(SF_PORT_1_120),
-	GPIO_FN(DU0_CDE),
-
-	/* Port121 */
-	GPIO_FN(SF_PORT_0_121),
-
-	/* Port122 */
-	GPIO_FN(CHSCIF0_HTX),
-
-	/* Port123 */
-	GPIO_FN(CHSCIF0_HRX),
-
-	/* Port124 */
-	GPIO_FN(ISP_STROBE_124),
-
-	/* Port125 */
-	GPIO_FN(STP_ISD_0),
-	GPIO_FN(PDM4_CLK_125),
-	GPIO_FN(MSIOF2_TXD),
-	GPIO_FN(SIM0_VOLTSEL0),
-
-	/* Port126 */
-	GPIO_FN(TS_SDEN),
-	GPIO_FN(MSIOF7_SYNC),
-	GPIO_FN(STP_ISEN_1),
-
-	/* Port128 */
-	GPIO_FN(STP_ISEN_0),
-	GPIO_FN(PDM1_OUTDATA_128),
-	GPIO_FN(MSIOF2_SYNC),
-	GPIO_FN(SIM1_VOLTSEL1),
-
-	/* Port129 */
-	GPIO_FN(TS_SPSYNC),
-	GPIO_FN(MSIOF7_RXD),
-	GPIO_FN(STP_ISSYNC_1),
-
-	/* Port130 */
-	GPIO_FN(STP_ISSYNC_0),
-	GPIO_FN(PDM4_DATA_130),
-	GPIO_FN(MSIOF2_RXD),
-	GPIO_FN(SIM0_VOLTSEL1),
-
-	/* Port131 */
-	GPIO_FN(STP_OPWM_0),
-	GPIO_FN(SIM1_PWRON),
-
-	/* Port132 */
-	GPIO_FN(TS_SCK),
-	GPIO_FN(MSIOF7_SCK),
-	GPIO_FN(STP_ISCLK_1),
-
-	/* Port133 */
-	GPIO_FN(STP_ISCLK_0),
-	GPIO_FN(PDM1_OUTCLK_133),
-	GPIO_FN(MSIOF2_SCK),
-	GPIO_FN(SIM1_VOLTSEL0),
-
-	/* Port134 */
-	GPIO_FN(TS_SDAT),
-	GPIO_FN(MSIOF7_TXD),
-	GPIO_FN(STP_ISD_1),
-
-	/* Port160 - Port178 */
-	GPIO_FN(MMCD0_0),
-	GPIO_FN(MMCD0_1),
-	GPIO_FN(MMCD0_2),
-	GPIO_FN(MMCD0_3),
-	GPIO_FN(MMCD0_4),
-	GPIO_FN(MMCD0_5),
-	GPIO_FN(MMCD0_6),
-	GPIO_FN(MMCD0_7),
-	GPIO_FN(MMCCMD0),
-	GPIO_FN(MMCCLK0),
-	GPIO_FN(MMCRST),
-
-	/* Port192 - Port200 FN1 */
-	GPIO_FN(A10),
-	GPIO_FN(A9),
-	GPIO_FN(A8),
-	GPIO_FN(A7),
-	GPIO_FN(A6),
-	GPIO_FN(A5),
-	GPIO_FN(A4),
-	GPIO_FN(A3),
-	GPIO_FN(A2),
-
-	/* Port192 - Port200 FN2 */
-	GPIO_FN(MMCD1_7),
-	GPIO_FN(MMCD1_6),
-	GPIO_FN(MMCD1_5),
-	GPIO_FN(MMCD1_4),
-	GPIO_FN(MMCD1_3),
-	GPIO_FN(MMCD1_2),
-	GPIO_FN(MMCD1_1),
-	GPIO_FN(MMCD1_0),
-	GPIO_FN(MMCCMD1),
-
-	/* Port192 - Port200 IRQ */
-
-	/* Port201 */
-	GPIO_FN(A1),
-
-	/* Port202 */
-	GPIO_FN(A0),
-	GPIO_FN(BS),
-
-	/* Port203 */
-	GPIO_FN(CKO),
-	GPIO_FN(MMCCLK1),
-
-	/* Port204 */
-	GPIO_FN(CS0_N),
-	GPIO_FN(SIM0_GPO1),
-
-	/* Port205 */
-	GPIO_FN(CS2_N),
-	GPIO_FN(SIM0_GPO2),
-
-	/* Port206 */
-	GPIO_FN(CS4_N),
-	GPIO_FN(VIO_VD),
-	GPIO_FN(SIM1_GPO0),
-
-	/* Port207 - Port212 FN1 */
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-
-	/* Port207 - Port212 FN5 */
-	GPIO_FN(GIO_OUT15),
-	GPIO_FN(GIO_OUT14),
-	GPIO_FN(GIO_OUT13),
-	GPIO_FN(GIO_OUT12),
-	GPIO_FN(WGM_TXP2),
-	GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK),
-
-	/* Port213 - Port222 FN1 */
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-
-	/* Port213 - Port222 FN2 */
-	GPIO_FN(VIO_D9),
-	GPIO_FN(VIO_D8),
-	GPIO_FN(VIO_D7),
-	GPIO_FN(VIO_D6),
-	GPIO_FN(VIO_D5),
-	GPIO_FN(VIO_D4),
-	GPIO_FN(VIO_D3),
-	GPIO_FN(VIO_D2),
-	GPIO_FN(VIO_D1),
-	GPIO_FN(VIO_D0),
-
-	/* Port213 - Port222 FN5 */
-	GPIO_FN(GIO_OUT9),
-	GPIO_FN(GIO_OUT8),
-	GPIO_FN(GIO_OUT7),
-	GPIO_FN(GIO_OUT6),
-	GPIO_FN(GIO_OUT5_217),
-	GPIO_FN(GIO_OUT4_218),
-	GPIO_FN(GIO_OUT3_219),
-	GPIO_FN(GIO_OUT2_220),
-	GPIO_FN(GIO_OUT1_221),
-	GPIO_FN(GIO_OUT0_222),
-
-	/* Port224 */
-	GPIO_FN(RDWR_224),
-	GPIO_FN(VIO_HD),
-	GPIO_FN(SIM1_GPO2),
-
-	/* Port225 */
-	GPIO_FN(RD_N),
-
-	/* Port226 */
-	GPIO_FN(WAIT_N),
-	GPIO_FN(VIO_CLK),
-	GPIO_FN(SIM1_GPO1),
-
-	/* Port227 */
-	GPIO_FN(WE0_N),
-	GPIO_FN(RDWR_227),
-
-	/* Port228 */
-	GPIO_FN(WE1_N),
-	GPIO_FN(SIM0_GPO0),
-
-	/* Port229 */
-	GPIO_FN(PWMO),
-	GPIO_FN(VIO_CKO1_229),
-
-	/* Port230 */
-	GPIO_FN(SLIM_CLK),
-	GPIO_FN(VIO_CKO4_230),
-
-	/* Port231 */
-	GPIO_FN(SLIM_DATA),
-	GPIO_FN(VIO_CKO5_231),
-
-	/* Port232 */
-	GPIO_FN(VIO_CKO2_232),
-	GPIO_FN(SF_PORT_0_232),
-
-	/* Port233 */
-	GPIO_FN(VIO_CKO3_233),
-	GPIO_FN(SF_PORT_1_233),
-
-	/* Port234 */
-	GPIO_FN(FSIACK),
-	GPIO_FN(PDM3_CLK_234),
-	GPIO_FN(ISP_IRIS1_234),
-
-	/* Port235 */
-	GPIO_FN(FSIAISLD),
-	GPIO_FN(PDM3_DATA_235),
-
-	/* Port236 */
-	GPIO_FN(FSIAOMC),
-	GPIO_FN(PDM0_OUTCLK_236),
-	GPIO_FN(ISP_IRIS0_236),
-
-	/* Port237 */
-	GPIO_FN(FSIAOLR),
-	GPIO_FN(FSIAILR),
-
-	/* Port238 */
-	GPIO_FN(FSIAOBT),
-	GPIO_FN(FSIAIBT),
-
-	/* Port239 */
-	GPIO_FN(FSIAOSLD),
-	GPIO_FN(PDM0_OUTDATA_239),
-
-	/* Port240 */
-	GPIO_FN(FSIBISLD),
-
-	/* Port241 */
-	GPIO_FN(FSIBOLR),
-	GPIO_FN(FSIBILR),
-
-	/* Port242 */
-	GPIO_FN(FSIBOMC),
-	GPIO_FN(ISP_SHUTTER1_242),
-
-	/* Port243 */
-	GPIO_FN(FSIBOBT),
-	GPIO_FN(FSIBIBT),
-
-	/* Port244 */
-	GPIO_FN(FSIBOSLD),
-	GPIO_FN(FSIASPDIF),
-
-	/* Port245 */
-	GPIO_FN(FSIBCK),
-	GPIO_FN(ISP_SHUTTER0_245),
-
-	/* Port246 - Port250 FN1 */
-	GPIO_FN(ISP_IRIS1_246),
-	GPIO_FN(ISP_IRIS0_247),
-	GPIO_FN(ISP_SHUTTER1_248),
-	GPIO_FN(ISP_SHUTTER0_249),
-	GPIO_FN(ISP_STROBE_250),
-
-	/* Port256 - Port258 */
-	GPIO_FN(MSIOF0_SYNC),
-	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(MSIOF0_SCK),
-
-	/* Port259 */
-	GPIO_FN(MSIOF0_SS2),
-	GPIO_FN(VIO_CKO3_259),
-
-	/* Port260 */
-	GPIO_FN(MSIOF0_TXD),
-
-	/* Port261 */
-	GPIO_FN(CHSCIF1_HSCK),
-
-	/* Port262 */
-
-	/* Port263 - Port266 FN1 */
-	GPIO_FN(MSIOF1_SS2),
-	GPIO_FN(MSIOF1_TXD),
-	GPIO_FN(MSIOF1_RXD),
-	GPIO_FN(MSIOF1_SS1),
-
-	/* Port263 - Port266 FN4 */
-	GPIO_FN(MSIOF5_SS2),
-	GPIO_FN(MSIOF5_TXD),
-	GPIO_FN(MSIOF5_RXD),
-	GPIO_FN(MSIOF5_SS1),
-
-	/* Port267 */
-	GPIO_FN(MSIOF0_SS1),
-
-	/* Port268 */
-	GPIO_FN(MSIOF1_SCK),
-	GPIO_FN(MSIOF5_SCK),
-
-	/* Port269 */
-	GPIO_FN(MSIOF1_SYNC),
-	GPIO_FN(MSIOF5_SYNC),
-
-	/* Port270 - Port273 FN1 */
-	GPIO_FN(MSIOF2_SS1),
-	GPIO_FN(MSIOF2_SS2),
-	GPIO_FN(MSIOF3_SS2),
-	GPIO_FN(MSIOF3_SS1),
-
-	/* Port270 - Port273 FN3 */
-	GPIO_FN(VIO_CKO5_270),
-	GPIO_FN(VIO_CKO2_271),
-	GPIO_FN(VIO_CKO1_272),
-	GPIO_FN(VIO_CKO4_273),
-
-	/* Port274 */
-	GPIO_FN(MSIOF4_SS2),
-	GPIO_FN(TPU1TO0),
-
-	/* Port275 - Port280 */
-	GPIO_FN(IC_DP),
-	GPIO_FN(SIM0_RST),
-	GPIO_FN(IC_DM),
-	GPIO_FN(SIM0_BSICOMP),
-	GPIO_FN(SIM0_CLK),
-	GPIO_FN(SIM0_IO),
-
-	/* Port281 */
-	GPIO_FN(SIM1_IO),
-	GPIO_FN(PDM2_DATA_281),
-
-	/* Port282 */
-	GPIO_FN(SIM1_CLK),
-	GPIO_FN(PDM2_CLK_282),
-
-	/* Port283 */
-	GPIO_FN(SIM1_RST),
-
-	/* Port289 */
-	GPIO_FN(SDHID1_0),
-	GPIO_FN(STMDATA0_2),
-
-	/* Port290 */
-	GPIO_FN(SDHID1_1),
-	GPIO_FN(STMDATA1_2),
-
-	/* Port291 - Port294 FN1 */
-	GPIO_FN(SDHID1_2),
-	GPIO_FN(SDHID1_3),
-	GPIO_FN(SDHICLK1),
-	GPIO_FN(SDHICMD1),
-
-	/* Port291 - Port294 FN3 */
-	GPIO_FN(STMDATA2_2),
-	GPIO_FN(STMDATA3_2),
-	GPIO_FN(STMCLK_2),
-	GPIO_FN(STMSIDI_2),
-
-	/* Port295 */
-	GPIO_FN(SDHID2_0),
-	GPIO_FN(MSIOF4_TXD),
-	GPIO_FN(MSIOF6_TXD),
-
-	/* Port296 */
-	GPIO_FN(SDHID2_1),
-	GPIO_FN(MSIOF6_SS2),
-
-	/* Port297 - Port300 FN1 */
-	GPIO_FN(SDHID2_2),
-	GPIO_FN(SDHID2_3),
-	GPIO_FN(SDHICLK2),
-	GPIO_FN(SDHICMD2),
-
-	/* Port297 - Port300 FN2 */
-	GPIO_FN(MSIOF4_RXD),
-	GPIO_FN(MSIOF4_SYNC),
-	GPIO_FN(MSIOF4_SCK),
-	GPIO_FN(MSIOF4_SS1),
-
-	/* Port297 - Port300 FN3 */
-
-	/* Port297 - Port300 FN4 */
-	GPIO_FN(MSIOF6_RXD),
-	GPIO_FN(MSIOF6_SYNC),
-	GPIO_FN(MSIOF6_SCK),
-	GPIO_FN(MSIOF6_SS1),
-
-	/* Port301 */
-	GPIO_FN(SDHICD0),
-
-	/* Port302 - Port306 FN1 */
-	GPIO_FN(SDHID0_0),
-	GPIO_FN(SDHID0_1),
-	GPIO_FN(SDHID0_2),
-	GPIO_FN(SDHID0_3),
-	GPIO_FN(SDHICMD0),
-
-	/* Port302 - Port306 FN3 */
-	GPIO_FN(STMDATA0_1),
-	GPIO_FN(STMDATA1_1),
-	GPIO_FN(STMDATA2_1),
-	GPIO_FN(STMDATA3_1),
-	GPIO_FN(STMSIDI_1),
-
-	/* Port307 */
-	GPIO_FN(SDHIWP0),
-
-	/* Port308 */
-	GPIO_FN(SDHICLK0),
-	GPIO_FN(STMCLK_1),
-
-	/* Port320 - Port329 */
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 
 	PORTCR(0, 0xe6050000),
@@ -3456,9 +2722,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs	= pinmux_config_regs,
 	.data_regs	= pinmux_data_regs,
 
-- 
1.7.10.4

[PATCH 26/28] sh-pfc: r8a73a4: Remove function GPIOs

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

All r8a73a4 platforms use the pinctrl API to control pin functions.
Function GPIOs are no longer needed.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  737 ----------------------------------
 1 file changed, 737 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 66fc747..464c5f9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2042,740 +2042,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb3),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* Port0 */
-	GPIO_FN(LCDD0),
-	GPIO_FN(PDM2_CLK_0),
-	GPIO_FN(DU0_DR0),
-
-	/* Port1 */
-	GPIO_FN(LCDD1),
-	GPIO_FN(PDM2_DATA_1),
-	GPIO_FN(DU0_DR19),
-
-	/* Port2 */
-	GPIO_FN(LCDD2),
-	GPIO_FN(PDM3_CLK_2),
-	GPIO_FN(DU0_DR2),
-
-	/* Port3 */
-	GPIO_FN(LCDD3),
-	GPIO_FN(PDM3_DATA_3),
-	GPIO_FN(DU0_DR3),
-
-	/* Port4 */
-	GPIO_FN(LCDD4),
-	GPIO_FN(PDM4_CLK_4),
-	GPIO_FN(DU0_DR4),
-
-	/* Port5 */
-	GPIO_FN(LCDD5),
-	GPIO_FN(PDM4_DATA_5),
-	GPIO_FN(DU0_DR5),
-
-	/* Port6 */
-	GPIO_FN(LCDD6),
-	GPIO_FN(PDM0_OUTCLK_6),
-	GPIO_FN(DU0_DR6),
-
-	/* Port7 */
-	GPIO_FN(LCDD7),
-	GPIO_FN(PDM0_OUTDATA_7),
-	GPIO_FN(DU0_DR7),
-
-	/* Port8 */
-	GPIO_FN(LCDD8),
-	GPIO_FN(PDM1_OUTCLK_8),
-	GPIO_FN(DU0_DG0),
-
-	/* Port9 */
-	GPIO_FN(LCDD9),
-	GPIO_FN(PDM1_OUTDATA_9),
-	GPIO_FN(DU0_DG1),
-
-	/* Port10 */
-	GPIO_FN(LCDD10),
-	GPIO_FN(FSICCK),
-	GPIO_FN(DU0_DG2),
-
-	/* Port11 */
-	GPIO_FN(LCDD11),
-	GPIO_FN(FSICISLD),
-	GPIO_FN(DU0_DG3),
-
-	/* Port12 */
-	GPIO_FN(LCDD12),
-	GPIO_FN(FSICOMC),
-	GPIO_FN(DU0_DG4),
-
-	/* Port13 */
-	GPIO_FN(LCDD13),
-	GPIO_FN(FSICOLR),
-	GPIO_FN(FSICILR),
-	GPIO_FN(DU0_DG5),
-
-	/* Port14 */
-	GPIO_FN(LCDD14),
-	GPIO_FN(FSICOBT),
-	GPIO_FN(FSICIBT),
-	GPIO_FN(DU0_DG6),
-
-	/* Port15 */
-	GPIO_FN(LCDD15),
-	GPIO_FN(FSICOSLD),
-	GPIO_FN(DU0_DG7),
-
-	/* Port16 */
-	GPIO_FN(LCDD16),
-	GPIO_FN(TPU1TO1),
-	GPIO_FN(DU0_DB0),
-
-	/* Port17 */
-	GPIO_FN(LCDD17),
-	GPIO_FN(SF_IRQ_00),
-	GPIO_FN(DU0_DB1),
-
-	/* Port18 */
-	GPIO_FN(LCDD18),
-	GPIO_FN(SF_IRQ_01),
-	GPIO_FN(DU0_DB2),
-
-	/* Port19 */
-	GPIO_FN(LCDD19),
-	GPIO_FN(DU0_DB3),
-
-	/* Port20 */
-	GPIO_FN(LCDD20),
-	GPIO_FN(DU0_DB4),
-
-	/* Port21 */
-	GPIO_FN(LCDD21),
-	GPIO_FN(DU0_DB5),
-
-	/* Port22 */
-	GPIO_FN(LCDD22),
-	GPIO_FN(DU0_DB6),
-
-	/* Port23 */
-	GPIO_FN(LCDD23),
-	GPIO_FN(DU0_DB7),
-
-	/* Port24 */
-	GPIO_FN(LCDHSYN),
-	GPIO_FN(LCDCS),
-	GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
-
-	/* Port25 */
-	GPIO_FN(LCDVSYN),
-	GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
-
-	/* Port26 */
-	GPIO_FN(LCDDCK),
-	GPIO_FN(LCDWR),
-	GPIO_FN(DU0_DOTCLKIN),
-
-	/* Port27 */
-	GPIO_FN(LCDDISP),
-	GPIO_FN(LCDRS),
-	GPIO_FN(DU0_DOTCLKOUT),
-
-	/* Port28 */
-	GPIO_FN(LCDRD_N),
-	GPIO_FN(DU0_DOTCLKOUTB),
-
-	/* Port29 */
-	GPIO_FN(LCDLCLK),
-	GPIO_FN(SF_IRQ_02),
-	GPIO_FN(DU0_DISP_CSYNC_N_DE),
-
-	/* Port30 */
-	GPIO_FN(LCDDON),
-	GPIO_FN(SF_IRQ_03),
-	GPIO_FN(DU0_ODDF_N_CLAMP),
-
-	/* Port32 */
-	GPIO_FN(SIM0_DET),
-	GPIO_FN(CSCIF0_RTS),
-
-	/* Port33 */
-	GPIO_FN(SIM1_DET),
-	GPIO_FN(CSCIF0_CTS),
-
-	/* Port34 */
-	GPIO_FN(SIM0_PWRON),
-	GPIO_FN(CSCIF0_SCK),
-
-	/* Port35 */
-	GPIO_FN(CSCIF1_RTS),
-
-	/* Port36 */
-	GPIO_FN(CSCIF1_CTS),
-
-	/* Port37 */
-	GPIO_FN(CSCIF1_SCK),
-
-	/* Port38 */
-	GPIO_FN(TPU0TO1),
-	GPIO_FN(CHSCIF0_HRTS),
-
-	/* Port39 */
-	GPIO_FN(TPU0TO2),
-	GPIO_FN(CHSCIF0_HCTS),
-
-	/* Port40 */
-	GPIO_FN(TPU0TO3),
-	GPIO_FN(CHSCIF0_HSCK),
-
-	/* Port64 */
-	GPIO_FN(PDM0_DATA),
-
-	/* Port65 */
-	GPIO_FN(PDM1_DATA),
-
-	/* Port66 */
-	GPIO_FN(HSI_RX_WAKE),
-	GPIO_FN(MSIOF3_SYNC),
-	GPIO_FN(GenIO4),
-
-	/* Port67 */
-	GPIO_FN(HSI_RX_READY),
-	GPIO_FN(GIO_OUT3_67),
-	GPIO_FN(CHSCIF1_HTX),
-
-	/* Port68 */
-	GPIO_FN(HSI_RX_FLAG),
-	GPIO_FN(MSIOF3_TXD),
-	GPIO_FN(GIO_OUT4_68),
-
-	/* Port69 */
-	GPIO_FN(HSI_RX_DATA),
-	GPIO_FN(MSIOF3_RXD),
-	GPIO_FN(GIO_OUT5_69),
-
-	/* Port70 */
-	GPIO_FN(HSI_TX_FLAG),
-	GPIO_FN(GIO_OUT1_70),
-	GPIO_FN(HSIC_TSTCLK0),
-	GPIO_FN(CHSCIF1_HRTS),
-
-	/* Port71 */
-	GPIO_FN(HSI_TX_DATA),
-	GPIO_FN(GIO_OUT2_71),
-	GPIO_FN(HSIC_TSTCLK1),
-	GPIO_FN(CHSCIF1_HCTS),
-
-	/* Port72 */
-	GPIO_FN(HSI_TX_WAKE),
-	GPIO_FN(GenIO8),
-	GPIO_FN(CHSCIF1_HRX),
-
-	/* Port73 */
-	GPIO_FN(HSI_TX_READY),
-	GPIO_FN(MSIOF3_SCK),
-	GPIO_FN(GIO_OUT0_73),
-
-	/* Port74 - Port85 */
-	GPIO_FN(IRDA_OUT),
-	GPIO_FN(IRDA_IN),
-	GPIO_FN(IRDA_FIRSEL),
-	GPIO_FN(TPU0TO0),
-	GPIO_FN(DIGRFEN),
-	GPIO_FN(GPS_TIMESTAMP),
-	GPIO_FN(TXP),
-	GPIO_FN(TXP2),
-	GPIO_FN(COEX_0),
-	GPIO_FN(COEX_1),
-
-	/* Port96 - Port101 */
-	GPIO_FN(KEYIN0),
-	GPIO_FN(KEYIN1),
-	GPIO_FN(KEYIN2),
-	GPIO_FN(KEYIN3),
-	GPIO_FN(KEYIN4),
-	GPIO_FN(KEYIN5),
-
-	/* Port102 */
-	GPIO_FN(KEYIN6),
-
-	/* Port103 */
-	GPIO_FN(KEYIN7),
-
-	/* Port104 - Port108 */
-	GPIO_FN(KEYOUT0),
-	GPIO_FN(KEYOUT1),
-	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT3),
-	GPIO_FN(KEYOUT4),
-
-	/* Port109 */
-	GPIO_FN(KEYOUT5),
-
-	/* Port110 */
-	GPIO_FN(KEYOUT6),
-
-	/* Port111 */
-	GPIO_FN(KEYOUT7),
-	GPIO_FN(RFANAEN),
-
-	/* Port112 */
-	GPIO_FN(KEYIN8),
-	GPIO_FN(KEYOUT8),
-	GPIO_FN(SF_IRQ_04),
-
-	/* Port113 */
-	GPIO_FN(KEYIN9),
-	GPIO_FN(KEYOUT9),
-	GPIO_FN(SF_IRQ_05),
-
-	/* Port114 */
-	GPIO_FN(KEYIN10),
-	GPIO_FN(KEYOUT10),
-	GPIO_FN(SF_IRQ_06),
-
-	/* Port115 */
-	GPIO_FN(KEYIN11),
-	GPIO_FN(KEYOUT11),
-	GPIO_FN(SF_IRQ_07),
-
-	/* Port116 */
-	GPIO_FN(CSCIF0_TX),
-
-	/* Port117 */
-	GPIO_FN(CSCIF0_RX),
-
-	/* Port118 */
-	GPIO_FN(CSCIF1_TX),
-
-	/* Port119 */
-	GPIO_FN(CSCIF1_RX),
-
-	/* Port120 */
-	GPIO_FN(SF_PORT_1_120),
-	GPIO_FN(DU0_CDE),
-
-	/* Port121 */
-	GPIO_FN(SF_PORT_0_121),
-
-	/* Port122 */
-	GPIO_FN(CHSCIF0_HTX),
-
-	/* Port123 */
-	GPIO_FN(CHSCIF0_HRX),
-
-	/* Port124 */
-	GPIO_FN(ISP_STROBE_124),
-
-	/* Port125 */
-	GPIO_FN(STP_ISD_0),
-	GPIO_FN(PDM4_CLK_125),
-	GPIO_FN(MSIOF2_TXD),
-	GPIO_FN(SIM0_VOLTSEL0),
-
-	/* Port126 */
-	GPIO_FN(TS_SDEN),
-	GPIO_FN(MSIOF7_SYNC),
-	GPIO_FN(STP_ISEN_1),
-
-	/* Port128 */
-	GPIO_FN(STP_ISEN_0),
-	GPIO_FN(PDM1_OUTDATA_128),
-	GPIO_FN(MSIOF2_SYNC),
-	GPIO_FN(SIM1_VOLTSEL1),
-
-	/* Port129 */
-	GPIO_FN(TS_SPSYNC),
-	GPIO_FN(MSIOF7_RXD),
-	GPIO_FN(STP_ISSYNC_1),
-
-	/* Port130 */
-	GPIO_FN(STP_ISSYNC_0),
-	GPIO_FN(PDM4_DATA_130),
-	GPIO_FN(MSIOF2_RXD),
-	GPIO_FN(SIM0_VOLTSEL1),
-
-	/* Port131 */
-	GPIO_FN(STP_OPWM_0),
-	GPIO_FN(SIM1_PWRON),
-
-	/* Port132 */
-	GPIO_FN(TS_SCK),
-	GPIO_FN(MSIOF7_SCK),
-	GPIO_FN(STP_ISCLK_1),
-
-	/* Port133 */
-	GPIO_FN(STP_ISCLK_0),
-	GPIO_FN(PDM1_OUTCLK_133),
-	GPIO_FN(MSIOF2_SCK),
-	GPIO_FN(SIM1_VOLTSEL0),
-
-	/* Port134 */
-	GPIO_FN(TS_SDAT),
-	GPIO_FN(MSIOF7_TXD),
-	GPIO_FN(STP_ISD_1),
-
-	/* Port160 - Port178 */
-	GPIO_FN(MMCD0_0),
-	GPIO_FN(MMCD0_1),
-	GPIO_FN(MMCD0_2),
-	GPIO_FN(MMCD0_3),
-	GPIO_FN(MMCD0_4),
-	GPIO_FN(MMCD0_5),
-	GPIO_FN(MMCD0_6),
-	GPIO_FN(MMCD0_7),
-	GPIO_FN(MMCCMD0),
-	GPIO_FN(MMCCLK0),
-	GPIO_FN(MMCRST),
-
-	/* Port192 - Port200 FN1 */
-	GPIO_FN(A10),
-	GPIO_FN(A9),
-	GPIO_FN(A8),
-	GPIO_FN(A7),
-	GPIO_FN(A6),
-	GPIO_FN(A5),
-	GPIO_FN(A4),
-	GPIO_FN(A3),
-	GPIO_FN(A2),
-
-	/* Port192 - Port200 FN2 */
-	GPIO_FN(MMCD1_7),
-	GPIO_FN(MMCD1_6),
-	GPIO_FN(MMCD1_5),
-	GPIO_FN(MMCD1_4),
-	GPIO_FN(MMCD1_3),
-	GPIO_FN(MMCD1_2),
-	GPIO_FN(MMCD1_1),
-	GPIO_FN(MMCD1_0),
-	GPIO_FN(MMCCMD1),
-
-	/* Port192 - Port200 IRQ */
-
-	/* Port201 */
-	GPIO_FN(A1),
-
-	/* Port202 */
-	GPIO_FN(A0),
-	GPIO_FN(BS),
-
-	/* Port203 */
-	GPIO_FN(CKO),
-	GPIO_FN(MMCCLK1),
-
-	/* Port204 */
-	GPIO_FN(CS0_N),
-	GPIO_FN(SIM0_GPO1),
-
-	/* Port205 */
-	GPIO_FN(CS2_N),
-	GPIO_FN(SIM0_GPO2),
-
-	/* Port206 */
-	GPIO_FN(CS4_N),
-	GPIO_FN(VIO_VD),
-	GPIO_FN(SIM1_GPO0),
-
-	/* Port207 - Port212 FN1 */
-	GPIO_FN(D15),
-	GPIO_FN(D14),
-	GPIO_FN(D13),
-	GPIO_FN(D12),
-	GPIO_FN(D11),
-	GPIO_FN(D10),
-
-	/* Port207 - Port212 FN5 */
-	GPIO_FN(GIO_OUT15),
-	GPIO_FN(GIO_OUT14),
-	GPIO_FN(GIO_OUT13),
-	GPIO_FN(GIO_OUT12),
-	GPIO_FN(WGM_TXP2),
-	GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK),
-
-	/* Port213 - Port222 FN1 */
-	GPIO_FN(D9),
-	GPIO_FN(D8),
-	GPIO_FN(D7),
-	GPIO_FN(D6),
-	GPIO_FN(D5),
-	GPIO_FN(D4),
-	GPIO_FN(D3),
-	GPIO_FN(D2),
-	GPIO_FN(D1),
-	GPIO_FN(D0),
-
-	/* Port213 - Port222 FN2 */
-	GPIO_FN(VIO_D9),
-	GPIO_FN(VIO_D8),
-	GPIO_FN(VIO_D7),
-	GPIO_FN(VIO_D6),
-	GPIO_FN(VIO_D5),
-	GPIO_FN(VIO_D4),
-	GPIO_FN(VIO_D3),
-	GPIO_FN(VIO_D2),
-	GPIO_FN(VIO_D1),
-	GPIO_FN(VIO_D0),
-
-	/* Port213 - Port222 FN5 */
-	GPIO_FN(GIO_OUT9),
-	GPIO_FN(GIO_OUT8),
-	GPIO_FN(GIO_OUT7),
-	GPIO_FN(GIO_OUT6),
-	GPIO_FN(GIO_OUT5_217),
-	GPIO_FN(GIO_OUT4_218),
-	GPIO_FN(GIO_OUT3_219),
-	GPIO_FN(GIO_OUT2_220),
-	GPIO_FN(GIO_OUT1_221),
-	GPIO_FN(GIO_OUT0_222),
-
-	/* Port224 */
-	GPIO_FN(RDWR_224),
-	GPIO_FN(VIO_HD),
-	GPIO_FN(SIM1_GPO2),
-
-	/* Port225 */
-	GPIO_FN(RD_N),
-
-	/* Port226 */
-	GPIO_FN(WAIT_N),
-	GPIO_FN(VIO_CLK),
-	GPIO_FN(SIM1_GPO1),
-
-	/* Port227 */
-	GPIO_FN(WE0_N),
-	GPIO_FN(RDWR_227),
-
-	/* Port228 */
-	GPIO_FN(WE1_N),
-	GPIO_FN(SIM0_GPO0),
-
-	/* Port229 */
-	GPIO_FN(PWMO),
-	GPIO_FN(VIO_CKO1_229),
-
-	/* Port230 */
-	GPIO_FN(SLIM_CLK),
-	GPIO_FN(VIO_CKO4_230),
-
-	/* Port231 */
-	GPIO_FN(SLIM_DATA),
-	GPIO_FN(VIO_CKO5_231),
-
-	/* Port232 */
-	GPIO_FN(VIO_CKO2_232),
-	GPIO_FN(SF_PORT_0_232),
-
-	/* Port233 */
-	GPIO_FN(VIO_CKO3_233),
-	GPIO_FN(SF_PORT_1_233),
-
-	/* Port234 */
-	GPIO_FN(FSIACK),
-	GPIO_FN(PDM3_CLK_234),
-	GPIO_FN(ISP_IRIS1_234),
-
-	/* Port235 */
-	GPIO_FN(FSIAISLD),
-	GPIO_FN(PDM3_DATA_235),
-
-	/* Port236 */
-	GPIO_FN(FSIAOMC),
-	GPIO_FN(PDM0_OUTCLK_236),
-	GPIO_FN(ISP_IRIS0_236),
-
-	/* Port237 */
-	GPIO_FN(FSIAOLR),
-	GPIO_FN(FSIAILR),
-
-	/* Port238 */
-	GPIO_FN(FSIAOBT),
-	GPIO_FN(FSIAIBT),
-
-	/* Port239 */
-	GPIO_FN(FSIAOSLD),
-	GPIO_FN(PDM0_OUTDATA_239),
-
-	/* Port240 */
-	GPIO_FN(FSIBISLD),
-
-	/* Port241 */
-	GPIO_FN(FSIBOLR),
-	GPIO_FN(FSIBILR),
-
-	/* Port242 */
-	GPIO_FN(FSIBOMC),
-	GPIO_FN(ISP_SHUTTER1_242),
-
-	/* Port243 */
-	GPIO_FN(FSIBOBT),
-	GPIO_FN(FSIBIBT),
-
-	/* Port244 */
-	GPIO_FN(FSIBOSLD),
-	GPIO_FN(FSIASPDIF),
-
-	/* Port245 */
-	GPIO_FN(FSIBCK),
-	GPIO_FN(ISP_SHUTTER0_245),
-
-	/* Port246 - Port250 FN1 */
-	GPIO_FN(ISP_IRIS1_246),
-	GPIO_FN(ISP_IRIS0_247),
-	GPIO_FN(ISP_SHUTTER1_248),
-	GPIO_FN(ISP_SHUTTER0_249),
-	GPIO_FN(ISP_STROBE_250),
-
-	/* Port256 - Port258 */
-	GPIO_FN(MSIOF0_SYNC),
-	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(MSIOF0_SCK),
-
-	/* Port259 */
-	GPIO_FN(MSIOF0_SS2),
-	GPIO_FN(VIO_CKO3_259),
-
-	/* Port260 */
-	GPIO_FN(MSIOF0_TXD),
-
-	/* Port261 */
-	GPIO_FN(CHSCIF1_HSCK),
-
-	/* Port262 */
-
-	/* Port263 - Port266 FN1 */
-	GPIO_FN(MSIOF1_SS2),
-	GPIO_FN(MSIOF1_TXD),
-	GPIO_FN(MSIOF1_RXD),
-	GPIO_FN(MSIOF1_SS1),
-
-	/* Port263 - Port266 FN4 */
-	GPIO_FN(MSIOF5_SS2),
-	GPIO_FN(MSIOF5_TXD),
-	GPIO_FN(MSIOF5_RXD),
-	GPIO_FN(MSIOF5_SS1),
-
-	/* Port267 */
-	GPIO_FN(MSIOF0_SS1),
-
-	/* Port268 */
-	GPIO_FN(MSIOF1_SCK),
-	GPIO_FN(MSIOF5_SCK),
-
-	/* Port269 */
-	GPIO_FN(MSIOF1_SYNC),
-	GPIO_FN(MSIOF5_SYNC),
-
-	/* Port270 - Port273 FN1 */
-	GPIO_FN(MSIOF2_SS1),
-	GPIO_FN(MSIOF2_SS2),
-	GPIO_FN(MSIOF3_SS2),
-	GPIO_FN(MSIOF3_SS1),
-
-	/* Port270 - Port273 FN3 */
-	GPIO_FN(VIO_CKO5_270),
-	GPIO_FN(VIO_CKO2_271),
-	GPIO_FN(VIO_CKO1_272),
-	GPIO_FN(VIO_CKO4_273),
-
-	/* Port274 */
-	GPIO_FN(MSIOF4_SS2),
-	GPIO_FN(TPU1TO0),
-
-	/* Port275 - Port280 */
-	GPIO_FN(IC_DP),
-	GPIO_FN(SIM0_RST),
-	GPIO_FN(IC_DM),
-	GPIO_FN(SIM0_BSICOMP),
-	GPIO_FN(SIM0_CLK),
-	GPIO_FN(SIM0_IO),
-
-	/* Port281 */
-	GPIO_FN(SIM1_IO),
-	GPIO_FN(PDM2_DATA_281),
-
-	/* Port282 */
-	GPIO_FN(SIM1_CLK),
-	GPIO_FN(PDM2_CLK_282),
-
-	/* Port283 */
-	GPIO_FN(SIM1_RST),
-
-	/* Port289 */
-	GPIO_FN(SDHID1_0),
-	GPIO_FN(STMDATA0_2),
-
-	/* Port290 */
-	GPIO_FN(SDHID1_1),
-	GPIO_FN(STMDATA1_2),
-
-	/* Port291 - Port294 FN1 */
-	GPIO_FN(SDHID1_2),
-	GPIO_FN(SDHID1_3),
-	GPIO_FN(SDHICLK1),
-	GPIO_FN(SDHICMD1),
-
-	/* Port291 - Port294 FN3 */
-	GPIO_FN(STMDATA2_2),
-	GPIO_FN(STMDATA3_2),
-	GPIO_FN(STMCLK_2),
-	GPIO_FN(STMSIDI_2),
-
-	/* Port295 */
-	GPIO_FN(SDHID2_0),
-	GPIO_FN(MSIOF4_TXD),
-	GPIO_FN(MSIOF6_TXD),
-
-	/* Port296 */
-	GPIO_FN(SDHID2_1),
-	GPIO_FN(MSIOF6_SS2),
-
-	/* Port297 - Port300 FN1 */
-	GPIO_FN(SDHID2_2),
-	GPIO_FN(SDHID2_3),
-	GPIO_FN(SDHICLK2),
-	GPIO_FN(SDHICMD2),
-
-	/* Port297 - Port300 FN2 */
-	GPIO_FN(MSIOF4_RXD),
-	GPIO_FN(MSIOF4_SYNC),
-	GPIO_FN(MSIOF4_SCK),
-	GPIO_FN(MSIOF4_SS1),
-
-	/* Port297 - Port300 FN3 */
-
-	/* Port297 - Port300 FN4 */
-	GPIO_FN(MSIOF6_RXD),
-	GPIO_FN(MSIOF6_SYNC),
-	GPIO_FN(MSIOF6_SCK),
-	GPIO_FN(MSIOF6_SS1),
-
-	/* Port301 */
-	GPIO_FN(SDHICD0),
-
-	/* Port302 - Port306 FN1 */
-	GPIO_FN(SDHID0_0),
-	GPIO_FN(SDHID0_1),
-	GPIO_FN(SDHID0_2),
-	GPIO_FN(SDHID0_3),
-	GPIO_FN(SDHICMD0),
-
-	/* Port302 - Port306 FN3 */
-	GPIO_FN(STMDATA0_1),
-	GPIO_FN(STMDATA1_1),
-	GPIO_FN(STMDATA2_1),
-	GPIO_FN(STMDATA3_1),
-	GPIO_FN(STMSIDI_1),
-
-	/* Port307 */
-	GPIO_FN(SDHIWP0),
-
-	/* Port308 */
-	GPIO_FN(SDHICLK0),
-	GPIO_FN(STMCLK_1),
-
-	/* Port320 - Port329 */
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 
 	PORTCR(0, 0xe6050000),
@@ -3456,9 +2722,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs	= pinmux_config_regs,
 	.data_regs	= pinmux_data_regs,
 
-- 
1.7.10.4

[PATCH 27/28] ARM: shmobile: r8a73a4: Remove all GPIO enums

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |  815 -------------------------
 1 file changed, 815 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 9162e86..f043103 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -1,821 +1,6 @@
 #ifndef __ASM_R8A73A4_H__
 #define __ASM_R8A73A4_H__
 
-/*
- * Pin Function Controller:
- *	GPIO_FN_xx - GPIO used to select pin function
- *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-
-	/* PORT */
-	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-	GPIO_PORT30, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-	GPIO_PORT40, GPIO_PORT64,
-	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-	GPIO_PORT85, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-	GPIO_PORT125, GPIO_PORT126, GPIO_PORT128, GPIO_PORT129,
-
-	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-
-	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178,
-
-	GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-	GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-	GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-
-	GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT224,
-	GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-
-	GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-	GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-
-	GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-	GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-
-	GPIO_PORT250, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-
-	GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-	GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
-
-	GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
-	GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
-
-	GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, GPIO_PORT283,
-	GPIO_PORT288, GPIO_PORT289,
-
-	GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
-	GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
-
-	GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
-	GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308,
-
-	GPIO_PORT320, GPIO_PORT321, GPIO_PORT322, GPIO_PORT323, GPIO_PORT324,
-	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
-
-	/* Port0 */
-	GPIO_FN_LCDD0 = 330,
-	GPIO_FN_PDM2_CLK_0,
-	GPIO_FN_DU0_DR0,
-
-	/* Port1 */
-	GPIO_FN_LCDD1,
-	GPIO_FN_PDM2_DATA_1,
-	GPIO_FN_DU0_DR19,
-
-	/* Port2 */
-	GPIO_FN_LCDD2,
-	GPIO_FN_PDM3_CLK_2,
-	GPIO_FN_DU0_DR2,
-
-	/* Port3 */
-	GPIO_FN_LCDD3,
-	GPIO_FN_PDM3_DATA_3,
-	GPIO_FN_DU0_DR3,
-
-	/* Port4 */
-	GPIO_FN_LCDD4,
-	GPIO_FN_PDM4_CLK_4,
-	GPIO_FN_DU0_DR4,
-
-	/* Port5 */
-	GPIO_FN_LCDD5,
-	GPIO_FN_PDM4_DATA_5,
-	GPIO_FN_DU0_DR5,
-
-	/* Port6 */
-	GPIO_FN_LCDD6,
-	GPIO_FN_PDM0_OUTCLK_6,
-	GPIO_FN_DU0_DR6,
-
-	/* Port7 */
-	GPIO_FN_LCDD7,
-	GPIO_FN_PDM0_OUTDATA_7,
-	GPIO_FN_DU0_DR7,
-
-	/* Port8 */
-	GPIO_FN_LCDD8,
-	GPIO_FN_PDM1_OUTCLK_8,
-	GPIO_FN_DU0_DG0,
-
-	/* Port9 */
-	GPIO_FN_LCDD9,
-	GPIO_FN_PDM1_OUTDATA_9,
-	GPIO_FN_DU0_DG1,
-
-	/* Port10 */
-	GPIO_FN_LCDD10,
-	GPIO_FN_FSICCK,
-	GPIO_FN_DU0_DG2,
-
-	/* Port11 */
-	GPIO_FN_LCDD11,
-	GPIO_FN_FSICISLD,
-	GPIO_FN_DU0_DG3,
-
-	/* Port12 */
-	GPIO_FN_LCDD12,
-	GPIO_FN_FSICOMC,
-	GPIO_FN_DU0_DG4,
-
-	/* Port13 */
-	GPIO_FN_LCDD13,
-	GPIO_FN_FSICOLR,
-	GPIO_FN_FSICILR,
-	GPIO_FN_DU0_DG5,
-
-	/* Port14 */
-	GPIO_FN_LCDD14,
-	GPIO_FN_FSICOBT,
-	GPIO_FN_FSICIBT,
-	GPIO_FN_DU0_DG6,
-
-	/* Port15 */
-	GPIO_FN_LCDD15,
-	GPIO_FN_FSICOSLD,
-	GPIO_FN_DU0_DG7,
-
-	/* Port16 */
-	GPIO_FN_LCDD16,
-	GPIO_FN_TPU1TO1,
-	GPIO_FN_DU0_DB0,
-
-	/* Port17 */
-	GPIO_FN_LCDD17,
-	GPIO_FN_SF_IRQ_00,
-	GPIO_FN_DU0_DB1,
-
-	/* Port18 */
-	GPIO_FN_LCDD18,
-	GPIO_FN_SF_IRQ_01,
-	GPIO_FN_DU0_DB2,
-
-	/* Port19 */
-	GPIO_FN_LCDD19,
-	GPIO_FN_DU0_DB3,
-
-	/* Port20 */
-	GPIO_FN_LCDD20,
-	GPIO_FN_DU0_DB4,
-
-	/* Port21 */
-	GPIO_FN_LCDD21,
-	GPIO_FN_DU0_DB5,
-
-	/* Port22 */
-	GPIO_FN_LCDD22,
-	GPIO_FN_DU0_DB6,
-
-	/* Port23 */
-	GPIO_FN_LCDD23,
-	GPIO_FN_DU0_DB7,
-
-	/* Port24 */
-	GPIO_FN_LCDHSYN,
-	GPIO_FN_LCDCS,
-	GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N,
-
-	/* Port25 */
-	GPIO_FN_LCDVSYN,
-	GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N,
-
-	/* Port26 */
-	GPIO_FN_LCDDCK,
-	GPIO_FN_LCDWR,
-	GPIO_FN_DU0_DOTCLKIN,
-
-	/* Port27 */
-	GPIO_FN_LCDDISP,
-	GPIO_FN_LCDRS,
-	GPIO_FN_DU0_DOTCLKOUT,
-
-	/* Port28 */
-	GPIO_FN_LCDRD_N,
-	GPIO_FN_DU0_DOTCLKOUTB,
-
-	/* Port29 */
-	GPIO_FN_LCDLCLK,
-	GPIO_FN_SF_IRQ_02,
-	GPIO_FN_DU0_DISP_CSYNC_N_DE,
-
-	/* Port30 */
-	GPIO_FN_LCDDON,
-	GPIO_FN_SF_IRQ_03,
-	GPIO_FN_DU0_ODDF_N_CLAMP,
-
-	/* Port32 */
-	GPIO_FN_SIM0_DET,
-	GPIO_FN_CSCIF0_RTS,
-
-	/* Port33 */
-	GPIO_FN_SIM1_DET,
-	GPIO_FN_CSCIF0_CTS,
-
-	/* Port34 */
-	GPIO_FN_SIM0_PWRON,
-	GPIO_FN_CSCIF0_SCK,
-
-	/* Port35 */
-	GPIO_FN_CSCIF1_RTS,
-
-	/* Port36 */
-	GPIO_FN_CSCIF1_CTS,
-
-	/* Port37 */
-	GPIO_FN_CSCIF1_SCK,
-
-	/* Port38 */
-	GPIO_FN_TPU0TO1,
-	GPIO_FN_CHSCIF0_HRTS,
-
-	/* Port39 */
-	GPIO_FN_TPU0TO2,
-	GPIO_FN_CHSCIF0_HCTS,
-
-	/* Port40 */
-	GPIO_FN_TPU0TO3,
-	GPIO_FN_CHSCIF0_HSCK,
-
-	/* Port64 */
-	GPIO_FN_PDM0_DATA,
-
-	/* Port65 */
-	GPIO_FN_PDM1_DATA,
-
-	/* Port66 */
-	GPIO_FN_HSI_RX_WAKE,
-	GPIO_FN_MSIOF3_SYNC,
-	GPIO_FN_GenIO4,
-
-	/* Port67 */
-	GPIO_FN_HSI_RX_READY,
-	GPIO_FN_GIO_OUT3_67,
-	GPIO_FN_CHSCIF1_HTX,
-
-	/* Port68 */
-	GPIO_FN_HSI_RX_FLAG,
-	GPIO_FN_MSIOF3_TXD,
-	GPIO_FN_GIO_OUT4_68,
-
-	/* Port69 */
-	GPIO_FN_HSI_RX_DATA,
-	GPIO_FN_MSIOF3_RXD,
-	GPIO_FN_GIO_OUT5_69,
-
-	/* Port70 */
-	GPIO_FN_HSI_TX_FLAG,
-	GPIO_FN_GIO_OUT1_70,
-	GPIO_FN_HSIC_TSTCLK0,
-	GPIO_FN_CHSCIF1_HRTS,
-
-	/* Port71 */
-	GPIO_FN_HSI_TX_DATA,
-	GPIO_FN_GIO_OUT2_71,
-	GPIO_FN_HSIC_TSTCLK1,
-	GPIO_FN_CHSCIF1_HCTS,
-
-	/* Port72 */
-	GPIO_FN_HSI_TX_WAKE,
-	GPIO_FN_GenIO8,
-	GPIO_FN_CHSCIF1_HRX,
-
-	/* Port73 */
-	GPIO_FN_HSI_TX_READY,
-	GPIO_FN_MSIOF3_SCK,
-	GPIO_FN_GIO_OUT0_73,
-
-	/* Port74 - Port85 */
-	GPIO_FN_IRDA_OUT,
-	GPIO_FN_IRDA_IN,
-	GPIO_FN_IRDA_FIRSEL,
-	GPIO_FN_TPU0TO0,
-	GPIO_FN_DIGRFEN,
-	GPIO_FN_GPS_TIMESTAMP,
-	GPIO_FN_TXP,
-	GPIO_FN_TXP2,
-	GPIO_FN_COEX_0,
-	GPIO_FN_COEX_1,
-
-	/* Port96 - Port101 */
-	GPIO_FN_KEYIN0,
-	GPIO_FN_KEYIN1,
-	GPIO_FN_KEYIN2,
-	GPIO_FN_KEYIN3,
-	GPIO_FN_KEYIN4,
-	GPIO_FN_KEYIN5,
-
-	/* Port102 */
-	GPIO_FN_KEYIN6,
-
-	/* Port103 */
-	GPIO_FN_KEYIN7,
-
-	/* Port104 - Port108 */
-	GPIO_FN_KEYOUT0,
-	GPIO_FN_KEYOUT1,
-	GPIO_FN_KEYOUT2,
-	GPIO_FN_KEYOUT3,
-	GPIO_FN_KEYOUT4,
-
-	/* Port109 */
-	GPIO_FN_KEYOUT5,
-
-	/* Port110 */
-	GPIO_FN_KEYOUT6,
-
-	/* Port111 */
-	GPIO_FN_KEYOUT7,
-	GPIO_FN_RFANAEN,
-
-	/* Port112 */
-	GPIO_FN_KEYIN8,
-	GPIO_FN_KEYOUT8,
-	GPIO_FN_SF_IRQ_04,
-
-	/* Port113 */
-	GPIO_FN_KEYIN9,
-	GPIO_FN_KEYOUT9,
-	GPIO_FN_SF_IRQ_05,
-
-	/* Port114 */
-	GPIO_FN_KEYIN10,
-	GPIO_FN_KEYOUT10,
-	GPIO_FN_SF_IRQ_06,
-
-	/* Port115 */
-	GPIO_FN_KEYIN11,
-	GPIO_FN_KEYOUT11,
-	GPIO_FN_SF_IRQ_07,
-
-	/* Port116 */
-	GPIO_FN_CSCIF0_TX,
-
-	/* Port117 */
-	GPIO_FN_CSCIF0_RX,
-
-	/* Port118 */
-	GPIO_FN_CSCIF1_TX,
-
-	/* Port119 */
-	GPIO_FN_CSCIF1_RX,
-
-	/* Port120 */
-	GPIO_FN_SF_PORT_1_120,
-	GPIO_FN_DU0_CDE,
-
-	/* Port121 */
-	GPIO_FN_SF_PORT_0_121,
-
-	/* Port122 */
-	GPIO_FN_CHSCIF0_HTX,
-
-	/* Port123 */
-	GPIO_FN_CHSCIF0_HRX,
-
-	/* Port124 */
-	GPIO_FN_ISP_STROBE_124,
-
-	/* Port125 */
-	GPIO_FN_STP_ISD_0,
-	GPIO_FN_PDM4_CLK_125,
-	GPIO_FN_MSIOF2_TXD,
-	GPIO_FN_SIM0_VOLTSEL0,
-
-	/* Port126 */
-	GPIO_FN_TS_SDEN,
-	GPIO_FN_MSIOF7_SYNC,
-	GPIO_FN_STP_ISEN_1,
-
-	/* Port128 */
-	GPIO_FN_STP_ISEN_0,
-	GPIO_FN_PDM1_OUTDATA_128,
-	GPIO_FN_MSIOF2_SYNC,
-	GPIO_FN_SIM1_VOLTSEL1,
-
-	/* Port129 */
-	GPIO_FN_TS_SPSYNC,
-	GPIO_FN_MSIOF7_RXD,
-	GPIO_FN_STP_ISSYNC_1,
-
-	/* Port130 */
-	GPIO_FN_STP_ISSYNC_0,
-	GPIO_FN_PDM4_DATA_130,
-	GPIO_FN_MSIOF2_RXD,
-	GPIO_FN_SIM0_VOLTSEL1,
-
-	/* Port131 */
-	GPIO_FN_STP_OPWM_0,
-	GPIO_FN_SIM1_PWRON,
-
-	/* Port132 */
-	GPIO_FN_TS_SCK,
-	GPIO_FN_MSIOF7_SCK,
-	GPIO_FN_STP_ISCLK_1,
-
-	/* Port133 */
-	GPIO_FN_STP_ISCLK_0,
-	GPIO_FN_PDM1_OUTCLK_133,
-	GPIO_FN_MSIOF2_SCK,
-	GPIO_FN_SIM1_VOLTSEL0,
-
-	/* Port134 */
-	GPIO_FN_TS_SDAT,
-	GPIO_FN_MSIOF7_TXD,
-	GPIO_FN_STP_ISD_1,
-
-	/* Port160 - Port178 */
-	GPIO_FN_MMCD0_0,
-	GPIO_FN_MMCD0_1,
-	GPIO_FN_MMCD0_2,
-	GPIO_FN_MMCD0_3,
-	GPIO_FN_MMCD0_4,
-	GPIO_FN_MMCD0_5,
-	GPIO_FN_MMCD0_6,
-	GPIO_FN_MMCD0_7,
-	GPIO_FN_MMCCMD0,
-	GPIO_FN_MMCCLK0,
-	GPIO_FN_MMCRST,
-
-	/* Port192 - Port200 FN1 */
-	GPIO_FN_A10,
-	GPIO_FN_A9,
-	GPIO_FN_A8,
-	GPIO_FN_A7,
-	GPIO_FN_A6,
-	GPIO_FN_A5,
-	GPIO_FN_A4,
-	GPIO_FN_A3,
-	GPIO_FN_A2,
-
-	/* Port192 - Port200 FN2 */
-	GPIO_FN_MMCD1_7,
-	GPIO_FN_MMCD1_6,
-	GPIO_FN_MMCD1_5,
-	GPIO_FN_MMCD1_4,
-	GPIO_FN_MMCD1_3,
-	GPIO_FN_MMCD1_2,
-	GPIO_FN_MMCD1_1,
-	GPIO_FN_MMCD1_0,
-	GPIO_FN_MMCCMD1,
-
-	/* Port192 - Port200 IRQ */
-
-	/* Port201 */
-	GPIO_FN_A1,
-
-	/* Port202 */
-	GPIO_FN_A0,
-	GPIO_FN_BS,
-
-	/* Port203 */
-	GPIO_FN_CKO,
-	GPIO_FN_MMCCLK1,
-
-	/* Port204 */
-	GPIO_FN_CS0_N,
-	GPIO_FN_SIM0_GPO1,
-
-	/* Port205 */
-	GPIO_FN_CS2_N,
-	GPIO_FN_SIM0_GPO2,
-
-	/* Port206 */
-	GPIO_FN_CS4_N,
-	GPIO_FN_VIO_VD,
-	GPIO_FN_SIM1_GPO0,
-
-	/* Port207 - Port212 FN1 */
-	GPIO_FN_D15,
-	GPIO_FN_D14,
-	GPIO_FN_D13,
-	GPIO_FN_D12,
-	GPIO_FN_D11,
-	GPIO_FN_D10,
-
-	/* Port207 - Port212 FN5 */
-	GPIO_FN_GIO_OUT15,
-	GPIO_FN_GIO_OUT14,
-	GPIO_FN_GIO_OUT13,
-	GPIO_FN_GIO_OUT12,
-	GPIO_FN_WGM_TXP2,
-	GPIO_FN_WGM_GPS_TIMEM_ASK_RFCLK,
-
-	/* Port213 - Port222 FN1 */
-	GPIO_FN_D9,
-	GPIO_FN_D8,
-	GPIO_FN_D7,
-	GPIO_FN_D6,
-	GPIO_FN_D5,
-	GPIO_FN_D4,
-	GPIO_FN_D3,
-	GPIO_FN_D2,
-	GPIO_FN_D1,
-	GPIO_FN_D0,
-
-	/* Port213 - Port222 FN2 */
-	GPIO_FN_VIO_D9,
-	GPIO_FN_VIO_D8,
-	GPIO_FN_VIO_D7,
-	GPIO_FN_VIO_D6,
-	GPIO_FN_VIO_D5,
-	GPIO_FN_VIO_D4,
-	GPIO_FN_VIO_D3,
-	GPIO_FN_VIO_D2,
-	GPIO_FN_VIO_D1,
-	GPIO_FN_VIO_D0,
-
-	/* Port213 - Port222 FN5 */
-	GPIO_FN_GIO_OUT9,
-	GPIO_FN_GIO_OUT8,
-	GPIO_FN_GIO_OUT7,
-	GPIO_FN_GIO_OUT6,
-	GPIO_FN_GIO_OUT5_217,
-	GPIO_FN_GIO_OUT4_218,
-	GPIO_FN_GIO_OUT3_219,
-	GPIO_FN_GIO_OUT2_220,
-	GPIO_FN_GIO_OUT1_221,
-	GPIO_FN_GIO_OUT0_222,
-
-	/* Port224 */
-	GPIO_FN_RDWR_224,
-	GPIO_FN_VIO_HD,
-	GPIO_FN_SIM1_GPO2,
-
-	/* Port225 */
-	GPIO_FN_RD_N,
-
-	/* Port226 */
-	GPIO_FN_WAIT_N,
-	GPIO_FN_VIO_CLK,
-	GPIO_FN_SIM1_GPO1,
-
-	/* Port227 */
-	GPIO_FN_WE0_N,
-	GPIO_FN_RDWR_227,
-
-	/* Port228 */
-	GPIO_FN_WE1_N,
-	GPIO_FN_SIM0_GPO0,
-
-	/* Port229 */
-	GPIO_FN_PWMO,
-	GPIO_FN_VIO_CKO1_229,
-
-	/* Port230 */
-	GPIO_FN_SLIM_CLK,
-	GPIO_FN_VIO_CKO4_230,
-
-	/* Port231 */
-	GPIO_FN_SLIM_DATA,
-	GPIO_FN_VIO_CKO5_231,
-
-	/* Port232 */
-	GPIO_FN_VIO_CKO2_232,
-	GPIO_FN_SF_PORT_0_232,
-
-	/* Port233 */
-	GPIO_FN_VIO_CKO3_233,
-	GPIO_FN_SF_PORT_1_233,
-
-	/* Port234 */
-	GPIO_FN_FSIACK,
-	GPIO_FN_PDM3_CLK_234,
-	GPIO_FN_ISP_IRIS1_234,
-
-	/* Port235 */
-	GPIO_FN_FSIAISLD,
-	GPIO_FN_PDM3_DATA_235,
-
-	/* Port236 */
-	GPIO_FN_FSIAOMC,
-	GPIO_FN_PDM0_OUTCLK_236,
-	GPIO_FN_ISP_IRIS0_236,
-
-	/* Port237 */
-	GPIO_FN_FSIAOLR,
-	GPIO_FN_FSIAILR,
-
-	/* Port238 */
-	GPIO_FN_FSIAOBT,
-	GPIO_FN_FSIAIBT,
-
-	/* Port239 */
-	GPIO_FN_FSIAOSLD,
-	GPIO_FN_PDM0_OUTDATA_239,
-
-	/* Port240 */
-	GPIO_FN_FSIBISLD,
-
-	/* Port241 */
-	GPIO_FN_FSIBOLR,
-	GPIO_FN_FSIBILR,
-
-	/* Port242 */
-	GPIO_FN_FSIBOMC,
-	GPIO_FN_ISP_SHUTTER1_242,
-
-	/* Port243 */
-	GPIO_FN_FSIBOBT,
-	GPIO_FN_FSIBIBT,
-
-	/* Port244 */
-	GPIO_FN_FSIBOSLD,
-	GPIO_FN_FSIASPDIF,
-
-	/* Port245 */
-	GPIO_FN_FSIBCK,
-	GPIO_FN_ISP_SHUTTER0_245,
-
-	/* Port246 - Port250 FN1 */
-	GPIO_FN_ISP_IRIS1_246,
-	GPIO_FN_ISP_IRIS0_247,
-	GPIO_FN_ISP_SHUTTER1_248,
-	GPIO_FN_ISP_SHUTTER0_249,
-	GPIO_FN_ISP_STROBE_250,
-
-	/* Port256 - Port258 */
-	GPIO_FN_MSIOF0_SYNC,
-	GPIO_FN_MSIOF0_RXD,
-	GPIO_FN_MSIOF0_SCK,
-
-	/* Port259 */
-	GPIO_FN_MSIOF0_SS2,
-	GPIO_FN_VIO_CKO3_259,
-
-	/* Port260 */
-	GPIO_FN_MSIOF0_TXD,
-
-	/* Port261 */
-	GPIO_FN_CHSCIF1_HSCK,
-
-	/* Port262 */
-
-	/* Port263 - Port266 FN1 */
-	GPIO_FN_MSIOF1_SS2,
-	GPIO_FN_MSIOF1_TXD,
-	GPIO_FN_MSIOF1_RXD,
-	GPIO_FN_MSIOF1_SS1,
-
-	/* Port263 - Port266 FN4 */
-	GPIO_FN_MSIOF5_SS2,
-	GPIO_FN_MSIOF5_TXD,
-	GPIO_FN_MSIOF5_RXD,
-	GPIO_FN_MSIOF5_SS1,
-
-	/* Port267 */
-	GPIO_FN_MSIOF0_SS1,
-
-	/* Port268 */
-	GPIO_FN_MSIOF1_SCK,
-	GPIO_FN_MSIOF5_SCK,
-
-	/* Port269 */
-	GPIO_FN_MSIOF1_SYNC,
-	GPIO_FN_MSIOF5_SYNC,
-
-	/* Port270 - Port273 FN1 */
-	GPIO_FN_MSIOF2_SS1,
-	GPIO_FN_MSIOF2_SS2,
-	GPIO_FN_MSIOF3_SS2,
-	GPIO_FN_MSIOF3_SS1,
-
-	/* Port270 - Port273 FN3 */
-	GPIO_FN_VIO_CKO5_270,
-	GPIO_FN_VIO_CKO2_271,
-	GPIO_FN_VIO_CKO1_272,
-	GPIO_FN_VIO_CKO4_273,
-
-	/* Port274 */
-	GPIO_FN_MSIOF4_SS2,
-	GPIO_FN_TPU1TO0,
-
-	/* Port275 - Port280 */
-	GPIO_FN_IC_DP,
-	GPIO_FN_SIM0_RST,
-	GPIO_FN_IC_DM,
-	GPIO_FN_SIM0_BSICOMP,
-	GPIO_FN_SIM0_CLK,
-	GPIO_FN_SIM0_IO,
-
-	/* Port281 */
-	GPIO_FN_SIM1_IO,
-	GPIO_FN_PDM2_DATA_281,
-
-	/* Port282 */
-	GPIO_FN_SIM1_CLK,
-	GPIO_FN_PDM2_CLK_282,
-
-	/* Port283 */
-	GPIO_FN_SIM1_RST,
-
-	/* Port289 */
-	GPIO_FN_SDHID1_0,
-	GPIO_FN_STMDATA0_2,
-
-	/* Port290 */
-	GPIO_FN_SDHID1_1,
-	GPIO_FN_STMDATA1_2,
-
-	/* Port291 - Port294 FN1 */
-	GPIO_FN_SDHID1_2,
-	GPIO_FN_SDHID1_3,
-	GPIO_FN_SDHICLK1,
-	GPIO_FN_SDHICMD1,
-
-	/* Port291 - Port294 FN3 */
-	GPIO_FN_STMDATA2_2,
-	GPIO_FN_STMDATA3_2,
-	GPIO_FN_STMCLK_2,
-	GPIO_FN_STMSIDI_2,
-
-	/* Port295 */
-	GPIO_FN_SDHID2_0,
-	GPIO_FN_MSIOF4_TXD,
-	GPIO_FN_MSIOF6_TXD,
-
-	/* Port296 */
-	GPIO_FN_SDHID2_1,
-	GPIO_FN_MSIOF6_SS2,
-
-	/* Port297 - Port300 FN1 */
-	GPIO_FN_SDHID2_2,
-	GPIO_FN_SDHID2_3,
-	GPIO_FN_SDHICLK2,
-	GPIO_FN_SDHICMD2,
-
-	/* Port297 - Port300 FN2 */
-	GPIO_FN_MSIOF4_RXD,
-	GPIO_FN_MSIOF4_SYNC,
-	GPIO_FN_MSIOF4_SCK,
-	GPIO_FN_MSIOF4_SS1,
-
-	/* Port297 - Port300 FN3 */
-
-	/* Port297 - Port300 FN4 */
-	GPIO_FN_MSIOF6_RXD,
-	GPIO_FN_MSIOF6_SYNC,
-	GPIO_FN_MSIOF6_SCK,
-	GPIO_FN_MSIOF6_SS1,
-
-	/* Port301 */
-	GPIO_FN_SDHICD0,
-
-	/* Port302 - Port306 FN1 */
-	GPIO_FN_SDHID0_0,
-	GPIO_FN_SDHID0_1,
-	GPIO_FN_SDHID0_2,
-	GPIO_FN_SDHID0_3,
-	GPIO_FN_SDHICMD0,
-
-	/* Port302 - Port306 FN3 */
-	GPIO_FN_STMDATA0_1,
-	GPIO_FN_STMDATA1_1,
-	GPIO_FN_STMDATA2_1,
-	GPIO_FN_STMDATA3_1,
-	GPIO_FN_STMSIDI_1,
-
-	/* Port307 */
-	GPIO_FN_SDHIWP0,
-
-	/* Port308 */
-	GPIO_FN_SDHICLK0,
-	GPIO_FN_STMCLK_1,
-
-	/* Port320 - Port329 */
-};
-
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
-- 
1.7.10.4

[PATCH 27/28] ARM: shmobile: r8a73a4: Remove all GPIO enums

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |  815 -------------------------
 1 file changed, 815 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 9162e86..f043103 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -1,821 +1,6 @@
 #ifndef __ASM_R8A73A4_H__
 #define __ASM_R8A73A4_H__
 
-/*
- * Pin Function Controller:
- *	GPIO_FN_xx - GPIO used to select pin function
- *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-
-	/* PORT */
-	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-	GPIO_PORT30, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-	GPIO_PORT40, GPIO_PORT64,
-	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-	GPIO_PORT85, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-	GPIO_PORT125, GPIO_PORT126, GPIO_PORT128, GPIO_PORT129,
-
-	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-
-	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178,
-
-	GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-	GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-	GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-
-	GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT224,
-	GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-
-	GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-	GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-
-	GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-	GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-
-	GPIO_PORT250, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-
-	GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-	GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
-
-	GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
-	GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
-
-	GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, GPIO_PORT283,
-	GPIO_PORT288, GPIO_PORT289,
-
-	GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
-	GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
-
-	GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
-	GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308,
-
-	GPIO_PORT320, GPIO_PORT321, GPIO_PORT322, GPIO_PORT323, GPIO_PORT324,
-	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
-
-	/* Port0 */
-	GPIO_FN_LCDD0 = 330,
-	GPIO_FN_PDM2_CLK_0,
-	GPIO_FN_DU0_DR0,
-
-	/* Port1 */
-	GPIO_FN_LCDD1,
-	GPIO_FN_PDM2_DATA_1,
-	GPIO_FN_DU0_DR19,
-
-	/* Port2 */
-	GPIO_FN_LCDD2,
-	GPIO_FN_PDM3_CLK_2,
-	GPIO_FN_DU0_DR2,
-
-	/* Port3 */
-	GPIO_FN_LCDD3,
-	GPIO_FN_PDM3_DATA_3,
-	GPIO_FN_DU0_DR3,
-
-	/* Port4 */
-	GPIO_FN_LCDD4,
-	GPIO_FN_PDM4_CLK_4,
-	GPIO_FN_DU0_DR4,
-
-	/* Port5 */
-	GPIO_FN_LCDD5,
-	GPIO_FN_PDM4_DATA_5,
-	GPIO_FN_DU0_DR5,
-
-	/* Port6 */
-	GPIO_FN_LCDD6,
-	GPIO_FN_PDM0_OUTCLK_6,
-	GPIO_FN_DU0_DR6,
-
-	/* Port7 */
-	GPIO_FN_LCDD7,
-	GPIO_FN_PDM0_OUTDATA_7,
-	GPIO_FN_DU0_DR7,
-
-	/* Port8 */
-	GPIO_FN_LCDD8,
-	GPIO_FN_PDM1_OUTCLK_8,
-	GPIO_FN_DU0_DG0,
-
-	/* Port9 */
-	GPIO_FN_LCDD9,
-	GPIO_FN_PDM1_OUTDATA_9,
-	GPIO_FN_DU0_DG1,
-
-	/* Port10 */
-	GPIO_FN_LCDD10,
-	GPIO_FN_FSICCK,
-	GPIO_FN_DU0_DG2,
-
-	/* Port11 */
-	GPIO_FN_LCDD11,
-	GPIO_FN_FSICISLD,
-	GPIO_FN_DU0_DG3,
-
-	/* Port12 */
-	GPIO_FN_LCDD12,
-	GPIO_FN_FSICOMC,
-	GPIO_FN_DU0_DG4,
-
-	/* Port13 */
-	GPIO_FN_LCDD13,
-	GPIO_FN_FSICOLR,
-	GPIO_FN_FSICILR,
-	GPIO_FN_DU0_DG5,
-
-	/* Port14 */
-	GPIO_FN_LCDD14,
-	GPIO_FN_FSICOBT,
-	GPIO_FN_FSICIBT,
-	GPIO_FN_DU0_DG6,
-
-	/* Port15 */
-	GPIO_FN_LCDD15,
-	GPIO_FN_FSICOSLD,
-	GPIO_FN_DU0_DG7,
-
-	/* Port16 */
-	GPIO_FN_LCDD16,
-	GPIO_FN_TPU1TO1,
-	GPIO_FN_DU0_DB0,
-
-	/* Port17 */
-	GPIO_FN_LCDD17,
-	GPIO_FN_SF_IRQ_00,
-	GPIO_FN_DU0_DB1,
-
-	/* Port18 */
-	GPIO_FN_LCDD18,
-	GPIO_FN_SF_IRQ_01,
-	GPIO_FN_DU0_DB2,
-
-	/* Port19 */
-	GPIO_FN_LCDD19,
-	GPIO_FN_DU0_DB3,
-
-	/* Port20 */
-	GPIO_FN_LCDD20,
-	GPIO_FN_DU0_DB4,
-
-	/* Port21 */
-	GPIO_FN_LCDD21,
-	GPIO_FN_DU0_DB5,
-
-	/* Port22 */
-	GPIO_FN_LCDD22,
-	GPIO_FN_DU0_DB6,
-
-	/* Port23 */
-	GPIO_FN_LCDD23,
-	GPIO_FN_DU0_DB7,
-
-	/* Port24 */
-	GPIO_FN_LCDHSYN,
-	GPIO_FN_LCDCS,
-	GPIO_FN_DU0_EXHSYNC_N_CSYNC_N_HSYNC_N,
-
-	/* Port25 */
-	GPIO_FN_LCDVSYN,
-	GPIO_FN_DU0_EXVSYNC_N_VSYNC_N_CSYNC_N,
-
-	/* Port26 */
-	GPIO_FN_LCDDCK,
-	GPIO_FN_LCDWR,
-	GPIO_FN_DU0_DOTCLKIN,
-
-	/* Port27 */
-	GPIO_FN_LCDDISP,
-	GPIO_FN_LCDRS,
-	GPIO_FN_DU0_DOTCLKOUT,
-
-	/* Port28 */
-	GPIO_FN_LCDRD_N,
-	GPIO_FN_DU0_DOTCLKOUTB,
-
-	/* Port29 */
-	GPIO_FN_LCDLCLK,
-	GPIO_FN_SF_IRQ_02,
-	GPIO_FN_DU0_DISP_CSYNC_N_DE,
-
-	/* Port30 */
-	GPIO_FN_LCDDON,
-	GPIO_FN_SF_IRQ_03,
-	GPIO_FN_DU0_ODDF_N_CLAMP,
-
-	/* Port32 */
-	GPIO_FN_SIM0_DET,
-	GPIO_FN_CSCIF0_RTS,
-
-	/* Port33 */
-	GPIO_FN_SIM1_DET,
-	GPIO_FN_CSCIF0_CTS,
-
-	/* Port34 */
-	GPIO_FN_SIM0_PWRON,
-	GPIO_FN_CSCIF0_SCK,
-
-	/* Port35 */
-	GPIO_FN_CSCIF1_RTS,
-
-	/* Port36 */
-	GPIO_FN_CSCIF1_CTS,
-
-	/* Port37 */
-	GPIO_FN_CSCIF1_SCK,
-
-	/* Port38 */
-	GPIO_FN_TPU0TO1,
-	GPIO_FN_CHSCIF0_HRTS,
-
-	/* Port39 */
-	GPIO_FN_TPU0TO2,
-	GPIO_FN_CHSCIF0_HCTS,
-
-	/* Port40 */
-	GPIO_FN_TPU0TO3,
-	GPIO_FN_CHSCIF0_HSCK,
-
-	/* Port64 */
-	GPIO_FN_PDM0_DATA,
-
-	/* Port65 */
-	GPIO_FN_PDM1_DATA,
-
-	/* Port66 */
-	GPIO_FN_HSI_RX_WAKE,
-	GPIO_FN_MSIOF3_SYNC,
-	GPIO_FN_GenIO4,
-
-	/* Port67 */
-	GPIO_FN_HSI_RX_READY,
-	GPIO_FN_GIO_OUT3_67,
-	GPIO_FN_CHSCIF1_HTX,
-
-	/* Port68 */
-	GPIO_FN_HSI_RX_FLAG,
-	GPIO_FN_MSIOF3_TXD,
-	GPIO_FN_GIO_OUT4_68,
-
-	/* Port69 */
-	GPIO_FN_HSI_RX_DATA,
-	GPIO_FN_MSIOF3_RXD,
-	GPIO_FN_GIO_OUT5_69,
-
-	/* Port70 */
-	GPIO_FN_HSI_TX_FLAG,
-	GPIO_FN_GIO_OUT1_70,
-	GPIO_FN_HSIC_TSTCLK0,
-	GPIO_FN_CHSCIF1_HRTS,
-
-	/* Port71 */
-	GPIO_FN_HSI_TX_DATA,
-	GPIO_FN_GIO_OUT2_71,
-	GPIO_FN_HSIC_TSTCLK1,
-	GPIO_FN_CHSCIF1_HCTS,
-
-	/* Port72 */
-	GPIO_FN_HSI_TX_WAKE,
-	GPIO_FN_GenIO8,
-	GPIO_FN_CHSCIF1_HRX,
-
-	/* Port73 */
-	GPIO_FN_HSI_TX_READY,
-	GPIO_FN_MSIOF3_SCK,
-	GPIO_FN_GIO_OUT0_73,
-
-	/* Port74 - Port85 */
-	GPIO_FN_IRDA_OUT,
-	GPIO_FN_IRDA_IN,
-	GPIO_FN_IRDA_FIRSEL,
-	GPIO_FN_TPU0TO0,
-	GPIO_FN_DIGRFEN,
-	GPIO_FN_GPS_TIMESTAMP,
-	GPIO_FN_TXP,
-	GPIO_FN_TXP2,
-	GPIO_FN_COEX_0,
-	GPIO_FN_COEX_1,
-
-	/* Port96 - Port101 */
-	GPIO_FN_KEYIN0,
-	GPIO_FN_KEYIN1,
-	GPIO_FN_KEYIN2,
-	GPIO_FN_KEYIN3,
-	GPIO_FN_KEYIN4,
-	GPIO_FN_KEYIN5,
-
-	/* Port102 */
-	GPIO_FN_KEYIN6,
-
-	/* Port103 */
-	GPIO_FN_KEYIN7,
-
-	/* Port104 - Port108 */
-	GPIO_FN_KEYOUT0,
-	GPIO_FN_KEYOUT1,
-	GPIO_FN_KEYOUT2,
-	GPIO_FN_KEYOUT3,
-	GPIO_FN_KEYOUT4,
-
-	/* Port109 */
-	GPIO_FN_KEYOUT5,
-
-	/* Port110 */
-	GPIO_FN_KEYOUT6,
-
-	/* Port111 */
-	GPIO_FN_KEYOUT7,
-	GPIO_FN_RFANAEN,
-
-	/* Port112 */
-	GPIO_FN_KEYIN8,
-	GPIO_FN_KEYOUT8,
-	GPIO_FN_SF_IRQ_04,
-
-	/* Port113 */
-	GPIO_FN_KEYIN9,
-	GPIO_FN_KEYOUT9,
-	GPIO_FN_SF_IRQ_05,
-
-	/* Port114 */
-	GPIO_FN_KEYIN10,
-	GPIO_FN_KEYOUT10,
-	GPIO_FN_SF_IRQ_06,
-
-	/* Port115 */
-	GPIO_FN_KEYIN11,
-	GPIO_FN_KEYOUT11,
-	GPIO_FN_SF_IRQ_07,
-
-	/* Port116 */
-	GPIO_FN_CSCIF0_TX,
-
-	/* Port117 */
-	GPIO_FN_CSCIF0_RX,
-
-	/* Port118 */
-	GPIO_FN_CSCIF1_TX,
-
-	/* Port119 */
-	GPIO_FN_CSCIF1_RX,
-
-	/* Port120 */
-	GPIO_FN_SF_PORT_1_120,
-	GPIO_FN_DU0_CDE,
-
-	/* Port121 */
-	GPIO_FN_SF_PORT_0_121,
-
-	/* Port122 */
-	GPIO_FN_CHSCIF0_HTX,
-
-	/* Port123 */
-	GPIO_FN_CHSCIF0_HRX,
-
-	/* Port124 */
-	GPIO_FN_ISP_STROBE_124,
-
-	/* Port125 */
-	GPIO_FN_STP_ISD_0,
-	GPIO_FN_PDM4_CLK_125,
-	GPIO_FN_MSIOF2_TXD,
-	GPIO_FN_SIM0_VOLTSEL0,
-
-	/* Port126 */
-	GPIO_FN_TS_SDEN,
-	GPIO_FN_MSIOF7_SYNC,
-	GPIO_FN_STP_ISEN_1,
-
-	/* Port128 */
-	GPIO_FN_STP_ISEN_0,
-	GPIO_FN_PDM1_OUTDATA_128,
-	GPIO_FN_MSIOF2_SYNC,
-	GPIO_FN_SIM1_VOLTSEL1,
-
-	/* Port129 */
-	GPIO_FN_TS_SPSYNC,
-	GPIO_FN_MSIOF7_RXD,
-	GPIO_FN_STP_ISSYNC_1,
-
-	/* Port130 */
-	GPIO_FN_STP_ISSYNC_0,
-	GPIO_FN_PDM4_DATA_130,
-	GPIO_FN_MSIOF2_RXD,
-	GPIO_FN_SIM0_VOLTSEL1,
-
-	/* Port131 */
-	GPIO_FN_STP_OPWM_0,
-	GPIO_FN_SIM1_PWRON,
-
-	/* Port132 */
-	GPIO_FN_TS_SCK,
-	GPIO_FN_MSIOF7_SCK,
-	GPIO_FN_STP_ISCLK_1,
-
-	/* Port133 */
-	GPIO_FN_STP_ISCLK_0,
-	GPIO_FN_PDM1_OUTCLK_133,
-	GPIO_FN_MSIOF2_SCK,
-	GPIO_FN_SIM1_VOLTSEL0,
-
-	/* Port134 */
-	GPIO_FN_TS_SDAT,
-	GPIO_FN_MSIOF7_TXD,
-	GPIO_FN_STP_ISD_1,
-
-	/* Port160 - Port178 */
-	GPIO_FN_MMCD0_0,
-	GPIO_FN_MMCD0_1,
-	GPIO_FN_MMCD0_2,
-	GPIO_FN_MMCD0_3,
-	GPIO_FN_MMCD0_4,
-	GPIO_FN_MMCD0_5,
-	GPIO_FN_MMCD0_6,
-	GPIO_FN_MMCD0_7,
-	GPIO_FN_MMCCMD0,
-	GPIO_FN_MMCCLK0,
-	GPIO_FN_MMCRST,
-
-	/* Port192 - Port200 FN1 */
-	GPIO_FN_A10,
-	GPIO_FN_A9,
-	GPIO_FN_A8,
-	GPIO_FN_A7,
-	GPIO_FN_A6,
-	GPIO_FN_A5,
-	GPIO_FN_A4,
-	GPIO_FN_A3,
-	GPIO_FN_A2,
-
-	/* Port192 - Port200 FN2 */
-	GPIO_FN_MMCD1_7,
-	GPIO_FN_MMCD1_6,
-	GPIO_FN_MMCD1_5,
-	GPIO_FN_MMCD1_4,
-	GPIO_FN_MMCD1_3,
-	GPIO_FN_MMCD1_2,
-	GPIO_FN_MMCD1_1,
-	GPIO_FN_MMCD1_0,
-	GPIO_FN_MMCCMD1,
-
-	/* Port192 - Port200 IRQ */
-
-	/* Port201 */
-	GPIO_FN_A1,
-
-	/* Port202 */
-	GPIO_FN_A0,
-	GPIO_FN_BS,
-
-	/* Port203 */
-	GPIO_FN_CKO,
-	GPIO_FN_MMCCLK1,
-
-	/* Port204 */
-	GPIO_FN_CS0_N,
-	GPIO_FN_SIM0_GPO1,
-
-	/* Port205 */
-	GPIO_FN_CS2_N,
-	GPIO_FN_SIM0_GPO2,
-
-	/* Port206 */
-	GPIO_FN_CS4_N,
-	GPIO_FN_VIO_VD,
-	GPIO_FN_SIM1_GPO0,
-
-	/* Port207 - Port212 FN1 */
-	GPIO_FN_D15,
-	GPIO_FN_D14,
-	GPIO_FN_D13,
-	GPIO_FN_D12,
-	GPIO_FN_D11,
-	GPIO_FN_D10,
-
-	/* Port207 - Port212 FN5 */
-	GPIO_FN_GIO_OUT15,
-	GPIO_FN_GIO_OUT14,
-	GPIO_FN_GIO_OUT13,
-	GPIO_FN_GIO_OUT12,
-	GPIO_FN_WGM_TXP2,
-	GPIO_FN_WGM_GPS_TIMEM_ASK_RFCLK,
-
-	/* Port213 - Port222 FN1 */
-	GPIO_FN_D9,
-	GPIO_FN_D8,
-	GPIO_FN_D7,
-	GPIO_FN_D6,
-	GPIO_FN_D5,
-	GPIO_FN_D4,
-	GPIO_FN_D3,
-	GPIO_FN_D2,
-	GPIO_FN_D1,
-	GPIO_FN_D0,
-
-	/* Port213 - Port222 FN2 */
-	GPIO_FN_VIO_D9,
-	GPIO_FN_VIO_D8,
-	GPIO_FN_VIO_D7,
-	GPIO_FN_VIO_D6,
-	GPIO_FN_VIO_D5,
-	GPIO_FN_VIO_D4,
-	GPIO_FN_VIO_D3,
-	GPIO_FN_VIO_D2,
-	GPIO_FN_VIO_D1,
-	GPIO_FN_VIO_D0,
-
-	/* Port213 - Port222 FN5 */
-	GPIO_FN_GIO_OUT9,
-	GPIO_FN_GIO_OUT8,
-	GPIO_FN_GIO_OUT7,
-	GPIO_FN_GIO_OUT6,
-	GPIO_FN_GIO_OUT5_217,
-	GPIO_FN_GIO_OUT4_218,
-	GPIO_FN_GIO_OUT3_219,
-	GPIO_FN_GIO_OUT2_220,
-	GPIO_FN_GIO_OUT1_221,
-	GPIO_FN_GIO_OUT0_222,
-
-	/* Port224 */
-	GPIO_FN_RDWR_224,
-	GPIO_FN_VIO_HD,
-	GPIO_FN_SIM1_GPO2,
-
-	/* Port225 */
-	GPIO_FN_RD_N,
-
-	/* Port226 */
-	GPIO_FN_WAIT_N,
-	GPIO_FN_VIO_CLK,
-	GPIO_FN_SIM1_GPO1,
-
-	/* Port227 */
-	GPIO_FN_WE0_N,
-	GPIO_FN_RDWR_227,
-
-	/* Port228 */
-	GPIO_FN_WE1_N,
-	GPIO_FN_SIM0_GPO0,
-
-	/* Port229 */
-	GPIO_FN_PWMO,
-	GPIO_FN_VIO_CKO1_229,
-
-	/* Port230 */
-	GPIO_FN_SLIM_CLK,
-	GPIO_FN_VIO_CKO4_230,
-
-	/* Port231 */
-	GPIO_FN_SLIM_DATA,
-	GPIO_FN_VIO_CKO5_231,
-
-	/* Port232 */
-	GPIO_FN_VIO_CKO2_232,
-	GPIO_FN_SF_PORT_0_232,
-
-	/* Port233 */
-	GPIO_FN_VIO_CKO3_233,
-	GPIO_FN_SF_PORT_1_233,
-
-	/* Port234 */
-	GPIO_FN_FSIACK,
-	GPIO_FN_PDM3_CLK_234,
-	GPIO_FN_ISP_IRIS1_234,
-
-	/* Port235 */
-	GPIO_FN_FSIAISLD,
-	GPIO_FN_PDM3_DATA_235,
-
-	/* Port236 */
-	GPIO_FN_FSIAOMC,
-	GPIO_FN_PDM0_OUTCLK_236,
-	GPIO_FN_ISP_IRIS0_236,
-
-	/* Port237 */
-	GPIO_FN_FSIAOLR,
-	GPIO_FN_FSIAILR,
-
-	/* Port238 */
-	GPIO_FN_FSIAOBT,
-	GPIO_FN_FSIAIBT,
-
-	/* Port239 */
-	GPIO_FN_FSIAOSLD,
-	GPIO_FN_PDM0_OUTDATA_239,
-
-	/* Port240 */
-	GPIO_FN_FSIBISLD,
-
-	/* Port241 */
-	GPIO_FN_FSIBOLR,
-	GPIO_FN_FSIBILR,
-
-	/* Port242 */
-	GPIO_FN_FSIBOMC,
-	GPIO_FN_ISP_SHUTTER1_242,
-
-	/* Port243 */
-	GPIO_FN_FSIBOBT,
-	GPIO_FN_FSIBIBT,
-
-	/* Port244 */
-	GPIO_FN_FSIBOSLD,
-	GPIO_FN_FSIASPDIF,
-
-	/* Port245 */
-	GPIO_FN_FSIBCK,
-	GPIO_FN_ISP_SHUTTER0_245,
-
-	/* Port246 - Port250 FN1 */
-	GPIO_FN_ISP_IRIS1_246,
-	GPIO_FN_ISP_IRIS0_247,
-	GPIO_FN_ISP_SHUTTER1_248,
-	GPIO_FN_ISP_SHUTTER0_249,
-	GPIO_FN_ISP_STROBE_250,
-
-	/* Port256 - Port258 */
-	GPIO_FN_MSIOF0_SYNC,
-	GPIO_FN_MSIOF0_RXD,
-	GPIO_FN_MSIOF0_SCK,
-
-	/* Port259 */
-	GPIO_FN_MSIOF0_SS2,
-	GPIO_FN_VIO_CKO3_259,
-
-	/* Port260 */
-	GPIO_FN_MSIOF0_TXD,
-
-	/* Port261 */
-	GPIO_FN_CHSCIF1_HSCK,
-
-	/* Port262 */
-
-	/* Port263 - Port266 FN1 */
-	GPIO_FN_MSIOF1_SS2,
-	GPIO_FN_MSIOF1_TXD,
-	GPIO_FN_MSIOF1_RXD,
-	GPIO_FN_MSIOF1_SS1,
-
-	/* Port263 - Port266 FN4 */
-	GPIO_FN_MSIOF5_SS2,
-	GPIO_FN_MSIOF5_TXD,
-	GPIO_FN_MSIOF5_RXD,
-	GPIO_FN_MSIOF5_SS1,
-
-	/* Port267 */
-	GPIO_FN_MSIOF0_SS1,
-
-	/* Port268 */
-	GPIO_FN_MSIOF1_SCK,
-	GPIO_FN_MSIOF5_SCK,
-
-	/* Port269 */
-	GPIO_FN_MSIOF1_SYNC,
-	GPIO_FN_MSIOF5_SYNC,
-
-	/* Port270 - Port273 FN1 */
-	GPIO_FN_MSIOF2_SS1,
-	GPIO_FN_MSIOF2_SS2,
-	GPIO_FN_MSIOF3_SS2,
-	GPIO_FN_MSIOF3_SS1,
-
-	/* Port270 - Port273 FN3 */
-	GPIO_FN_VIO_CKO5_270,
-	GPIO_FN_VIO_CKO2_271,
-	GPIO_FN_VIO_CKO1_272,
-	GPIO_FN_VIO_CKO4_273,
-
-	/* Port274 */
-	GPIO_FN_MSIOF4_SS2,
-	GPIO_FN_TPU1TO0,
-
-	/* Port275 - Port280 */
-	GPIO_FN_IC_DP,
-	GPIO_FN_SIM0_RST,
-	GPIO_FN_IC_DM,
-	GPIO_FN_SIM0_BSICOMP,
-	GPIO_FN_SIM0_CLK,
-	GPIO_FN_SIM0_IO,
-
-	/* Port281 */
-	GPIO_FN_SIM1_IO,
-	GPIO_FN_PDM2_DATA_281,
-
-	/* Port282 */
-	GPIO_FN_SIM1_CLK,
-	GPIO_FN_PDM2_CLK_282,
-
-	/* Port283 */
-	GPIO_FN_SIM1_RST,
-
-	/* Port289 */
-	GPIO_FN_SDHID1_0,
-	GPIO_FN_STMDATA0_2,
-
-	/* Port290 */
-	GPIO_FN_SDHID1_1,
-	GPIO_FN_STMDATA1_2,
-
-	/* Port291 - Port294 FN1 */
-	GPIO_FN_SDHID1_2,
-	GPIO_FN_SDHID1_3,
-	GPIO_FN_SDHICLK1,
-	GPIO_FN_SDHICMD1,
-
-	/* Port291 - Port294 FN3 */
-	GPIO_FN_STMDATA2_2,
-	GPIO_FN_STMDATA3_2,
-	GPIO_FN_STMCLK_2,
-	GPIO_FN_STMSIDI_2,
-
-	/* Port295 */
-	GPIO_FN_SDHID2_0,
-	GPIO_FN_MSIOF4_TXD,
-	GPIO_FN_MSIOF6_TXD,
-
-	/* Port296 */
-	GPIO_FN_SDHID2_1,
-	GPIO_FN_MSIOF6_SS2,
-
-	/* Port297 - Port300 FN1 */
-	GPIO_FN_SDHID2_2,
-	GPIO_FN_SDHID2_3,
-	GPIO_FN_SDHICLK2,
-	GPIO_FN_SDHICMD2,
-
-	/* Port297 - Port300 FN2 */
-	GPIO_FN_MSIOF4_RXD,
-	GPIO_FN_MSIOF4_SYNC,
-	GPIO_FN_MSIOF4_SCK,
-	GPIO_FN_MSIOF4_SS1,
-
-	/* Port297 - Port300 FN3 */
-
-	/* Port297 - Port300 FN4 */
-	GPIO_FN_MSIOF6_RXD,
-	GPIO_FN_MSIOF6_SYNC,
-	GPIO_FN_MSIOF6_SCK,
-	GPIO_FN_MSIOF6_SS1,
-
-	/* Port301 */
-	GPIO_FN_SDHICD0,
-
-	/* Port302 - Port306 FN1 */
-	GPIO_FN_SDHID0_0,
-	GPIO_FN_SDHID0_1,
-	GPIO_FN_SDHID0_2,
-	GPIO_FN_SDHID0_3,
-	GPIO_FN_SDHICMD0,
-
-	/* Port302 - Port306 FN3 */
-	GPIO_FN_STMDATA0_1,
-	GPIO_FN_STMDATA1_1,
-	GPIO_FN_STMDATA2_1,
-	GPIO_FN_STMDATA3_1,
-	GPIO_FN_STMSIDI_1,
-
-	/* Port307 */
-	GPIO_FN_SDHIWP0,
-
-	/* Port308 */
-	GPIO_FN_SDHICLK0,
-	GPIO_FN_STMCLK_1,
-
-	/* Port320 - Port329 */
-};
-
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
-- 
1.7.10.4

[PATCH 28/28] sh-pfc: r8a73a4: Remove unused GPIO bias data

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove unused pull-up/down data from the r8a73a4 PFC code.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  176 +++-------------------------------
 1 file changed, 15 insertions(+), 161 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 464c5f9..bbff559 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -115,16 +115,6 @@ enum {
 	PORT_ALL(IN),
 	PINMUX_INPUT_END,
 
-	/* PORT0_IN_PU -> PORT329_IN_PU */
-	PINMUX_INPUT_PULLUP_BEGIN,
-	PORT_ALL(IN_PU),
-	PINMUX_INPUT_PULLUP_END,
-
-	/* PORT0_IN_PD -> PORT329_IN_PD */
-	PINMUX_INPUT_PULLDOWN_BEGIN,
-	PORT_ALL(IN_PD),
-	PINMUX_INPUT_PULLDOWN_END,
-
 	/* PORT0_OUT -> PORT329_OUT */
 	PINMUX_OUTPUT_BEGIN,
 	PORT_ALL(OUT),
@@ -438,156 +428,12 @@ enum {
 	PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)
+#define PINMUX_DATA_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
 	/* specify valid pin states for each pin in GPIO mode */
-
-	PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
-	PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
-	PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
-	PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
-	PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
-
-	PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
-	PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
-	PORT_DATA_IO_PU_PD(14),	PORT_DATA_IO_PU_PD(15),
-	PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
-	PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
-
-	PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
-	PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
-	PORT_DATA_IO_PU_PD(24),	PORT_DATA_IO_PU_PD(25),
-	PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
-	PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
-
-	PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
-	PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
-	PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
-	PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
-	PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
-
-	PORT_DATA_IO_PU_PD(64),	PORT_DATA_IO_PU_PD(65),
-	PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
-	PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
-
-	PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
-	PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
-	PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
-	PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
-	PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
-
-	PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
-	PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
-	PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
-
-	PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
-	PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
-
-	PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
-	PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
-	PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
-	PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
-	PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
-
-	PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
-	PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
-	PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
-	PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
-	PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
-
-	PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
-	PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
-	PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
-	PORT_DATA_IO_PU_PD(126),
-	PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
-
-	PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
-	PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
-	PORT_DATA_IO_PU_PD(134),
-
-	PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
-	PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
-	PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
-	PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
-	PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
-
-	PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
-	PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
-	PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
-	PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
-	PORT_DATA_IO_PU_PD(178),
-
-	PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
-	PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
-	PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
-	PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
-
-	PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
-	PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
-	PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
-	PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
-	PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
-
-	PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
-	PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
-	PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
-	PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
-	PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
-
-	PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
-	PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
-	PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
-	PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
-	PORT_DATA_IO_PU_PD(229),
-
-	PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
-	PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
-	PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
-	PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
-	PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
-
-	PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
-	PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
-	PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
-	PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
-	PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
-
-	PORT_DATA_IO_PU_PD(250),
-	PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
-	PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
-
-	PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
-	PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
-	PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
-	PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
-	PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
-
-	PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
-	PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
-	PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
-	PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
-	PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
-
-	PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
-	PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
-	PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
-
-	PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
-	PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
-	PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
-	PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
-	PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
-
-	PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
-	PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
-	PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
-	PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
-	PORT_DATA_IO_PU_PD(308),
-
-	PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
-	PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
-	PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
-	PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
-	PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
+	PINMUX_DATA_ALL(),
 
 	/* Port0 */
 	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
@@ -2042,8 +1888,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb3),
 };
 
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#undef PORTCR
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),	\
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
 
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0, 0xe6050000),
 	PORTCR(1, 0xe6050001),
 	PORTCR(2, 0xe6050002),
@@ -2706,8 +2562,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.ops		= &r8a73a4_pinmux_ops,
 
 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
 	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-- 
1.7.10.4

[PATCH 28/28] sh-pfc: r8a73a4: Remove unused GPIO bias data

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Remove unused pull-up/down data from the r8a73a4 PFC code.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c |  176 +++-------------------------------
 1 file changed, 15 insertions(+), 161 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 464c5f9..bbff559 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -115,16 +115,6 @@ enum {
 	PORT_ALL(IN),
 	PINMUX_INPUT_END,
 
-	/* PORT0_IN_PU -> PORT329_IN_PU */
-	PINMUX_INPUT_PULLUP_BEGIN,
-	PORT_ALL(IN_PU),
-	PINMUX_INPUT_PULLUP_END,
-
-	/* PORT0_IN_PD -> PORT329_IN_PD */
-	PINMUX_INPUT_PULLDOWN_BEGIN,
-	PORT_ALL(IN_PD),
-	PINMUX_INPUT_PULLDOWN_END,
-
 	/* PORT0_OUT -> PORT329_OUT */
 	PINMUX_OUTPUT_BEGIN,
 	PORT_ALL(OUT),
@@ -438,156 +428,12 @@ enum {
 	PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)
+#define PINMUX_DATA_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
 	/* specify valid pin states for each pin in GPIO mode */
-
-	PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
-	PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
-	PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
-	PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
-	PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
-
-	PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
-	PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
-	PORT_DATA_IO_PU_PD(14),	PORT_DATA_IO_PU_PD(15),
-	PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
-	PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
-
-	PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
-	PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
-	PORT_DATA_IO_PU_PD(24),	PORT_DATA_IO_PU_PD(25),
-	PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
-	PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
-
-	PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
-	PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
-	PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
-	PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
-	PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
-
-	PORT_DATA_IO_PU_PD(64),	PORT_DATA_IO_PU_PD(65),
-	PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
-	PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
-
-	PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
-	PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
-	PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
-	PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
-	PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
-
-	PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
-	PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
-	PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
-
-	PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
-	PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
-
-	PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
-	PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
-	PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
-	PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
-	PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
-
-	PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
-	PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
-	PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
-	PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
-	PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
-
-	PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
-	PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
-	PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
-	PORT_DATA_IO_PU_PD(126),
-	PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
-
-	PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
-	PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
-	PORT_DATA_IO_PU_PD(134),
-
-	PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
-	PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
-	PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
-	PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
-	PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
-
-	PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
-	PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
-	PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
-	PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
-	PORT_DATA_IO_PU_PD(178),
-
-	PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
-	PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
-	PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
-	PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
-
-	PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
-	PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
-	PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
-	PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
-	PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
-
-	PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
-	PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
-	PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
-	PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
-	PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
-
-	PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
-	PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
-	PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
-	PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
-	PORT_DATA_IO_PU_PD(229),
-
-	PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
-	PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
-	PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
-	PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
-	PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
-
-	PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
-	PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
-	PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
-	PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
-	PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
-
-	PORT_DATA_IO_PU_PD(250),
-	PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
-	PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
-
-	PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
-	PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
-	PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
-	PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
-	PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
-
-	PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
-	PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
-	PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
-	PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
-	PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
-
-	PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
-	PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
-	PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
-
-	PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
-	PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
-	PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
-	PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
-	PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
-
-	PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
-	PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
-	PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
-	PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
-	PORT_DATA_IO_PU_PD(308),
-
-	PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
-	PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
-	PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
-	PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
-	PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
+	PINMUX_DATA_ALL(),
 
 	/* Port0 */
 	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
@@ -2042,8 +1888,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb3),
 };
 
-static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#undef PORTCR
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),	\
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
 
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0, 0xe6050000),
 	PORTCR(1, 0xe6050001),
 	PORTCR(2, 0xe6050002),
@@ -2706,8 +2562,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 	.ops		= &r8a73a4_pinmux_ops,
 
 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
 	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-- 
1.7.10.4

Re: [GIT PULL v2] Renesas ARM and SH based SoC pinmux updates for v3.10

[Olof Johansson]

On Wed, Apr 03, 2013 at 11:04:38AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
> 
> The following changes since commit 809609a5d8427b0025304dbb69a84a692d11c4f9:
> 
>   Merge branch 'soc' into pinmux-base (2013-04-02 11:08:34 +0900)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux2-for-v3.10
> 
> for you to fetch changes up to 202ac6a21a79500ef5aab4cd8665be2597e9345c:
> 
>   sh-pfc: r8a73a4: Remove unused GPIO bias data (2013-04-03 10:30:43 +0900)


Pulled into next/soc2.


-Olof

[GIT PULL v2] Renesas ARM and SH based SoC pinmux updates for v3.10

[Olof Johansson]

On Wed, Apr 03, 2013 at 11:04:38AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
> 
> The following changes since commit 809609a5d8427b0025304dbb69a84a692d11c4f9:
> 
>   Merge branch 'soc' into pinmux-base (2013-04-02 11:08:34 +0900)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux2-for-v3.10
> 
> for you to fetch changes up to 202ac6a21a79500ef5aab4cd8665be2597e9345c:
> 
>   sh-pfc: r8a73a4: Remove unused GPIO bias data (2013-04-03 10:30:43 +0900)


Pulled into next/soc2.


-Olof

[PATCH 17/28] sh-pfc: r8a73a4: Support sparse GPIO numbers

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          |   16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f0b1b4a..2d4af4a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -86,7 +86,7 @@ enum {
 	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
 
 	/* Port0 */
-	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
 	GPIO_FN_IRQ0,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 47d75d5..5dd68fb9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1424,6 +1424,20 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+static const struct pinmux_range pinmux_ranges[] = {
+	{.begin = 0, .end = 30,},
+	{.begin = 32, .end = 40,},
+	{.begin = 64, .end = 85,},
+	{.begin = 96, .end = 126,},
+	{.begin = 128, .end = 134,},
+	{.begin = 160, .end = 178,},
+	{.begin = 192, .end = 222,},
+	{.begin = 224, .end = 250,},
+	{.begin = 256, .end = 283,},
+	{.begin = 288, .end = 308,},
+	{.begin = 320, .end = 329,},
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -2815,6 +2829,8 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.ranges = pinmux_ranges,
+	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4

[PATCH 17/28] sh-pfc: r8a73a4: Support sparse GPIO numbers

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a73a4.h |    2 +-
 drivers/pinctrl/sh-pfc/pfc-r8a73a4.c          |   16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f0b1b4a..2d4af4a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -86,7 +86,7 @@ enum {
 	GPIO_PORT325, GPIO_PORT326, GPIO_PORT327, GPIO_PORT328, GPIO_PORT329,
 
 	/* Port0 */
-	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD0 = 330,
 	GPIO_FN_PDM2_CLK_0,
 	GPIO_FN_DU0_DR0,
 	GPIO_FN_IRQ0,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 47d75d5..5dd68fb9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1424,6 +1424,20 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+static const struct pinmux_range pinmux_ranges[] = {
+	{.begin = 0, .end = 30,},
+	{.begin = 32, .end = 40,},
+	{.begin = 64, .end = 85,},
+	{.begin = 96, .end = 126,},
+	{.begin = 128, .end = 134,},
+	{.begin = 160, .end = 178,},
+	{.begin = 192, .end = 222,},
+	{.begin = 224, .end = 250,},
+	{.begin = 256, .end = 283,},
+	{.begin = 288, .end = 308,},
+	{.begin = 320, .end = 329,},
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -2815,6 +2829,8 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.ranges = pinmux_ranges,
+	.nr_ranges = ARRAY_SIZE(pinmux_ranges),
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-- 
1.7.10.4