* [PATCH 01/18] MIPS: ralink: add PCI IRQ handling
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 02/18] MIPS: ralink: fix RT305x clock setup John Crispin
` (16 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
From: Gabor Juhos <juhosg@openwrt.org>
The Ralink IRQ code was not handling the PCI IRQ yet. Add this functionaility
to make PCI work on rt3883.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/irq.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index 6d054c5..d9807d0 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -31,6 +31,7 @@
#define INTC_INT_GLOBAL BIT(31)
#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
+#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
@@ -104,6 +105,9 @@ asmlinkage void plat_irq_dispatch(void)
else if (pending & STATUSF_IP6)
do_IRQ(RALINK_CPU_IRQ_WIFI);
+ else if (pending & STATUSF_IP4)
+ do_IRQ(RALINK_CPU_IRQ_PCI);
+
else if (pending & STATUSF_IP2)
do_IRQ(RALINK_CPU_IRQ_INTC);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 02/18] MIPS: ralink: fix RT305x clock setup
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
2013-04-10 11:47 ` [PATCH 01/18] MIPS: ralink: add PCI IRQ handling John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 13:47 ` Jonas Gorski
2013-04-10 13:49 ` Sergei Shtylyov
2013-04-10 11:47 ` [PATCH 03/18] MIPS: ralink: add missing comment in irq driver John Crispin
` (15 subsequent siblings)
17 siblings, 2 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a few missing clocks and remove the unused sys clock.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/rt305x.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 0a4bbdc..856ebff 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
{
unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+ int wmac_20mhz = 0;
if (soc_is_rt305x() || soc_is_rt3350()) {
t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
@@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
BUG();
}
+ if (soc_is_rt3352() || soc_is_rt5350()) {
+ u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
+ if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
+ wmac_20mhz = 1;
+ }
+
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("10000b00.spi", sys_rate);
ralink_clk_add("10000100.timer", wdt_rate);
+ ralink_clk_add("10000120.watchdog", wdt_rate);
ralink_clk_add("10000500.uart", uart_rate);
ralink_clk_add("10000c00.uartlite", uart_rate);
+ ralink_clk_add("10100000.ethernet", sys_rate);
+
+ if (wmac_20mhz)
+ ralink_clk_add("wmac@10180000", 20000000);
+ else
+ ralink_clk_add("wmac@10180000", 40000000);
}
void __init ralink_of_remap(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 02/18] MIPS: ralink: fix RT305x clock setup
2013-04-10 11:47 ` [PATCH 02/18] MIPS: ralink: fix RT305x clock setup John Crispin
@ 2013-04-10 13:47 ` Jonas Gorski
2013-04-10 13:49 ` Sergei Shtylyov
1 sibling, 0 replies; 26+ messages in thread
From: Jonas Gorski @ 2013-04-10 13:47 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
On 10 April 2013 13:47, John Crispin <blogic@openwrt.org> wrote:
> Add a few missing clocks and remove the unused sys clock.
You are not removing anything here, only adding ;-)
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/rt305x.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> index 0a4bbdc..856ebff 100644
> --- a/arch/mips/ralink/rt305x.c
> +++ b/arch/mips/ralink/rt305x.c
> @@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
> {
> unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
> u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
> + int wmac_20mhz = 0;
>
> if (soc_is_rt305x() || soc_is_rt3350()) {
> t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
> @@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
> BUG();
> }
>
> + if (soc_is_rt3352() || soc_is_rt5350()) {
> + u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
Empty line missing.
> + if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
> + wmac_20mhz = 1;
Why not just call it wmac_rate, default to 40000000, and set it to
20000000 here?
> + }
> +
> ralink_clk_add("cpu", cpu_rate);
> ralink_clk_add("10000b00.spi", sys_rate);
> ralink_clk_add("10000100.timer", wdt_rate);
> + ralink_clk_add("10000120.watchdog", wdt_rate);
> ralink_clk_add("10000500.uart", uart_rate);
> ralink_clk_add("10000c00.uartlite", uart_rate);
> + ralink_clk_add("10100000.ethernet", sys_rate);
> +
> + if (wmac_20mhz)
> + ralink_clk_add("wmac@10180000", 20000000);
> + else
> + ralink_clk_add("wmac@10180000", 40000000);
> }
Then you wouldn't need the conditional here.
Jonas
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/18] MIPS: ralink: fix RT305x clock setup
2013-04-10 11:47 ` [PATCH 02/18] MIPS: ralink: fix RT305x clock setup John Crispin
2013-04-10 13:47 ` Jonas Gorski
@ 2013-04-10 13:49 ` Sergei Shtylyov
1 sibling, 0 replies; 26+ messages in thread
From: Sergei Shtylyov @ 2013-04-10 13:49 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
Hello.
On 10-04-2013 15:47, John Crispin wrote:
> Add a few missing clocks and remove the unused sys clock.
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/rt305x.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> index 0a4bbdc..856ebff 100644
> --- a/arch/mips/ralink/rt305x.c
> +++ b/arch/mips/ralink/rt305x.c
[...]
> @@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
> BUG();
> }
>
> + if (soc_is_rt3352() || soc_is_rt5350()) {
> + u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
Empty line wouldn't hurt here...
> + if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
Using ! would make this shorter.
WBR, Sergei
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/18] MIPS: ralink: add missing comment in irq driver
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
2013-04-10 11:47 ` [PATCH 01/18] MIPS: ralink: add PCI IRQ handling John Crispin
2013-04-10 11:47 ` [PATCH 02/18] MIPS: ralink: fix RT305x clock setup John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 04/18] MIPS: ralink: add RT5350 sdram register defines John Crispin
` (14 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Trivial patch that adds a comment that makes the code more readable.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index d9807d0..320b1f1 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -166,6 +166,7 @@ static int __init intc_of_init(struct device_node *node,
irq_set_chained_handler(irq, ralink_intc_irq_handler);
irq_set_handler_data(irq, domain);
+ /* tell the kernel which irq is used for performance monitoring */
cp0_perfcount_irq = irq_create_mapping(domain, 9);
return 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 04/18] MIPS: ralink: add RT5350 sdram register defines
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (2 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 03/18] MIPS: ralink: add missing comment in irq driver John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 05/18] MIPS: ralink: add RT3352 usb " John Crispin
` (13 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a few missing defines that are needed to make memory detection work on the
RT5350.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/rt305x.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 7d344f2..4e62cef 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -97,6 +97,14 @@ static inline int soc_is_rt5350(void)
#define RT5350_SYSCFG0_CPUCLK_320 0x2
#define RT5350_SYSCFG0_CPUCLK_300 0x3
+#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
+#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
+#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
+#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
+#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
+#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
+#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
+
/* multi function gpio pins */
#define RT305X_GPIO_I2C_SD 1
#define RT305X_GPIO_I2C_SCLK 2
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 05/18] MIPS: ralink: add RT3352 usb register defines
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (3 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 04/18] MIPS: ralink: add RT5350 sdram register defines John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 06/18] MIPS: ralink: add pinmux driver John Crispin
` (12 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a few missing defines that are needed to make USB work on the RT3352
and RT5350.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/rt305x.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 4e62cef..0e50692 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -144,4 +144,15 @@ static inline int soc_is_rt5350(void)
#define RT305X_GPIO_MODE_SDRAM BIT(8)
#define RT305X_GPIO_MODE_RGMII BIT(9)
+#define RT3352_SYSC_REG_SYSCFG1 0x014
+#define RT3352_SYSC_REG_CLKCFG1 0x030
+#define RT3352_SYSC_REG_RSTCTRL 0x034
+#define RT3352_SYSC_REG_USB_PS 0x05c
+
+#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
+#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT3352_RSTCTRL_UHST BIT(22)
+#define RT3352_RSTCTRL_UDEV BIT(25)
+#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
+
#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 06/18] MIPS: ralink: add pinmux driver
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (4 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 05/18] MIPS: ralink: add RT3352 usb " John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 13:51 ` Jonas Gorski
2013-04-10 11:47 ` [PATCH 07/18] MIPS: ralink: extend RT3050 dtsi file John Crispin
` (11 subsequent siblings)
17 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
for this functionality with simple on/off bits. Building a full featured pinctrl
driver would be overkill.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Makefile | 2 +-
arch/mips/ralink/common.h | 8 +++-
arch/mips/ralink/of.c | 2 +
arch/mips/ralink/pinmux.c | 95 +++++++++++++++++++++++++++++++++++++++++++++
arch/mips/ralink/rt305x.c | 6 +--
5 files changed, 107 insertions(+), 6 deletions(-)
create mode 100644 arch/mips/ralink/pinmux.c
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 939757f..39ef249 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,7 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 3009903..193c76c 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -22,9 +22,13 @@ struct ralink_pinmux {
struct ralink_pinmux_grp *mode;
struct ralink_pinmux_grp *uart;
int uart_shift;
+ u32 uart_mask;
void (*wdt_reset)(void);
+ struct ralink_pinmux_grp *pci;
+ int pci_shift;
+ u32 pci_mask;
};
-extern struct ralink_pinmux gpio_pinmux;
+extern struct ralink_pinmux rt_pinmux;
struct ralink_soc_info {
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
@@ -41,4 +45,6 @@ extern void prom_soc_init(struct ralink_soc_info *soc_info);
__iomem void *plat_of_remap_node(const char *node);
+void ralink_pinmux(void);
+
#endif /* _RALINK_COMMON_H__ */
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 4165e70..ecf1482 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -101,6 +101,8 @@ static int __init plat_of_setup(void)
if (of_platform_populate(NULL, of_ids, NULL, NULL))
panic("failed to populate DT\n");
+ ralink_pinmux();
+
return 0;
}
diff --git a/arch/mips/ralink/pinmux.c b/arch/mips/ralink/pinmux.c
new file mode 100644
index 0000000..c10df50
--- /dev/null
+++ b/arch/mips/ralink/pinmux.c
@@ -0,0 +1,95 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "common.h"
+
+#define SYSC_REG_GPIO_MODE 0x60
+
+static u32 ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps)
+{
+ for (; grps->name; grps++)
+ if (!strcmp(grps->name, name))
+ return grps->mask;
+
+ return 0;
+}
+
+void ralink_pinmux(void)
+{
+ const __be32 *wdt;
+ struct device_node *np;
+ struct property *prop;
+ const char *uart, *pci, *pin;
+ u32 mode = 0;
+
+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
+ if (!np)
+ return;
+
+ of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
+ int m = ralink_mux_mask(pin, rt_pinmux.mode);
+ if (m) {
+ mode |= m;
+ pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
+ } else {
+ pr_err("pinmux: failed to load \"%s\"\n", pin);
+ }
+ }
+
+ of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
+ int m = ralink_mux_mask(pin, rt_pinmux.mode);
+ if (m) {
+ mode &= ~m;
+ pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
+ } else {
+ pr_err("pinmux: failed to load group \"%s\"\n", pin);
+ }
+ }
+
+ uart = NULL;
+ if (rt_pinmux.uart)
+ of_property_read_string(np, "ralink,uartmux", &uart);
+
+ if (uart) {
+ int m = ralink_mux_mask(uart, rt_pinmux.uart);
+
+ if (m) {
+ mode &= ~(rt_pinmux.uart_mask << rt_pinmux.uart_shift);
+ mode |= m << rt_pinmux.uart_shift;
+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
+ } else {
+ pr_debug("pinmux: unknown uartmux \"%s\"\n", uart);
+ }
+ }
+
+ wdt = of_get_property(np, "ralink,wdtmux", NULL);
+ if (wdt && *wdt && rt_pinmux.wdt_reset)
+ rt_pinmux.wdt_reset();
+
+ pci = NULL;
+ if (rt_pinmux.pci)
+ of_property_read_string(np, "ralink,pcimux", &pci);
+
+ if (pci) {
+ int m = ralink_mux_mask(pci, rt_pinmux.pci);
+ mode &= ~(rt_pinmux.pci_mask << rt_pinmux.pci_shift);
+ if (m) {
+ mode |= (m << rt_pinmux.pci_shift);
+ pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
+ } else {
+ pr_debug("pinmux: registered pcimux \"gpio\"\n");
+ }
+ }
+
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
+}
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 856ebff..d9ea53d 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -97,9 +97,6 @@ struct ralink_pinmux_grp uart_mux[] = {
.mask = RT305X_GPIO_MODE_GPIO_I2S,
.gpio_first = RT305X_GPIO_7,
.gpio_last = RT305X_GPIO_14,
- }, {
- .name = "gpio",
- .mask = RT305X_GPIO_MODE_GPIO,
}, {0}
};
@@ -114,10 +111,11 @@ void rt305x_wdt_reset(void)
rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
}
-struct ralink_pinmux gpio_pinmux = {
+struct ralink_pinmux rt_pinmux = {
.mode = mode_mux,
.uart = uart_mux,
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
+ .uart_mask = RT305X_GPIO_MODE_GPIO,
.wdt_reset = rt305x_wdt_reset,
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 06/18] MIPS: ralink: add pinmux driver
2013-04-10 11:47 ` [PATCH 06/18] MIPS: ralink: add pinmux driver John Crispin
@ 2013-04-10 13:51 ` Jonas Gorski
0 siblings, 0 replies; 26+ messages in thread
From: Jonas Gorski @ 2013-04-10 13:51 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
On 10 April 2013 13:47, John Crispin <blogic@openwrt.org> wrote:
> Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
> for this functionality with simple on/off bits. Building a full featured pinctrl
> driver would be overkill.
Bindings documentation, pretty please?
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/Makefile | 2 +-
> arch/mips/ralink/common.h | 8 +++-
> arch/mips/ralink/of.c | 2 +
> arch/mips/ralink/pinmux.c | 95 +++++++++++++++++++++++++++++++++++++++++++++
> arch/mips/ralink/rt305x.c | 6 +--
> 5 files changed, 107 insertions(+), 6 deletions(-)
> create mode 100644 arch/mips/ralink/pinmux.c
>
> diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
> index 939757f..39ef249 100644
> --- a/arch/mips/ralink/Makefile
> +++ b/arch/mips/ralink/Makefile
> @@ -6,7 +6,7 @@
> # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
> # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
>
> -obj-y := prom.o of.o reset.o clk.o irq.o
> +obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
>
> obj-$(CONFIG_SOC_RT305X) += rt305x.o
>
> diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
> index 3009903..193c76c 100644
> --- a/arch/mips/ralink/common.h
> +++ b/arch/mips/ralink/common.h
> @@ -22,9 +22,13 @@ struct ralink_pinmux {
> struct ralink_pinmux_grp *mode;
> struct ralink_pinmux_grp *uart;
> int uart_shift;
> + u32 uart_mask;
> void (*wdt_reset)(void);
> + struct ralink_pinmux_grp *pci;
> + int pci_shift;
> + u32 pci_mask;
> };
> -extern struct ralink_pinmux gpio_pinmux;
> +extern struct ralink_pinmux rt_pinmux;
>
> struct ralink_soc_info {
> unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
> @@ -41,4 +45,6 @@ extern void prom_soc_init(struct ralink_soc_info *soc_info);
>
> __iomem void *plat_of_remap_node(const char *node);
>
> +void ralink_pinmux(void);
> +
> #endif /* _RALINK_COMMON_H__ */
> diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
> index 4165e70..ecf1482 100644
> --- a/arch/mips/ralink/of.c
> +++ b/arch/mips/ralink/of.c
> @@ -101,6 +101,8 @@ static int __init plat_of_setup(void)
> if (of_platform_populate(NULL, of_ids, NULL, NULL))
> panic("failed to populate DT\n");
>
> + ralink_pinmux();
> +
> return 0;
> }
>
> diff --git a/arch/mips/ralink/pinmux.c b/arch/mips/ralink/pinmux.c
> new file mode 100644
> index 0000000..c10df50
> --- /dev/null
> +++ b/arch/mips/ralink/pinmux.c
> @@ -0,0 +1,95 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + *
> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +
> +#include <asm/mach-ralink/ralink_regs.h>
> +
> +#include "common.h"
> +
> +#define SYSC_REG_GPIO_MODE 0x60
> +
> +static u32 ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps)
> +{
> + for (; grps->name; grps++)
> + if (!strcmp(grps->name, name))
> + return grps->mask;
> +
> + return 0;
> +}
> +
> +void ralink_pinmux(void)
Since you are only calling it from init code, couldn't it be also __init?
> +{
> + const __be32 *wdt;
> + struct device_node *np;
> + struct property *prop;
> + const char *uart, *pci, *pin;
> + u32 mode = 0;
> +
> + np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
> + if (!np)
> + return;
> +
> + of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
> + int m = ralink_mux_mask(pin, rt_pinmux.mode);
Missing empty line.
> + if (m) {
> + mode |= m;
> + pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
> + } else {
> + pr_err("pinmux: failed to load \"%s\"\n", pin);
> + }
> + }
> +
> + of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
> + int m = ralink_mux_mask(pin, rt_pinmux.mode);
Missing empty line.
> + if (m) {
> + mode &= ~m;
> + pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
> + } else {
> + pr_err("pinmux: failed to load group \"%s\"\n", pin);
> + }
> + }
> +
> + uart = NULL;
> + if (rt_pinmux.uart)
> + of_property_read_string(np, "ralink,uartmux", &uart);
> +
> + if (uart) {
> + int m = ralink_mux_mask(uart, rt_pinmux.uart);
> +
> + if (m) {
> + mode &= ~(rt_pinmux.uart_mask << rt_pinmux.uart_shift);
> + mode |= m << rt_pinmux.uart_shift;
> + pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
> + } else {
> + pr_debug("pinmux: unknown uartmux \"%s\"\n", uart);
> + }
> + }
> +
> + wdt = of_get_property(np, "ralink,wdtmux", NULL);
> + if (wdt && *wdt && rt_pinmux.wdt_reset)
> + rt_pinmux.wdt_reset();
> +
> + pci = NULL;
> + if (rt_pinmux.pci)
> + of_property_read_string(np, "ralink,pcimux", &pci);
> +
> + if (pci) {
> + int m = ralink_mux_mask(pci, rt_pinmux.pci);
Missing empty line.
> + mode &= ~(rt_pinmux.pci_mask << rt_pinmux.pci_shift);
> + if (m) {
> + mode |= (m << rt_pinmux.pci_shift);
> + pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
> + } else {
> + pr_debug("pinmux: registered pcimux \"gpio\"\n");
> + }
> + }
> +
> + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
> +}
Jonas
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 07/18] MIPS: ralink: extend RT3050 dtsi file
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (5 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 06/18] MIPS: ralink: add pinmux driver John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 08/18] MIPS: ralink: add RT5350 " John Crispin
` (10 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add some additional properties to the dtsi file for ethernet and wifi.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/dts/rt3050.dtsi | 96 ++++++++++++++++++++++++++++------
arch/mips/ralink/dts/rt3052_eval.dts | 2 +-
2 files changed, 82 insertions(+), 16 deletions(-)
diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
index 069d066..5aede8d 100644
--- a/arch/mips/ralink/dts/rt3050.dtsi
+++ b/arch/mips/ralink/dts/rt3050.dtsi
@@ -1,7 +1,7 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
cpus {
cpu@0 {
@@ -23,7 +23,7 @@
palmbus@10000000 {
compatible = "palmbus";
reg = <0x10000000 0x200000>;
- ranges = <0x0 0x10000000 0x1FFFFF>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
@@ -34,8 +34,18 @@
};
timer@100 {
+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@120 {
compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
- reg = <0x100 0x100>;
+ reg = <0x120 0x10>;
};
intc: intc@200 {
@@ -61,10 +71,12 @@
gpio-controller;
#gpio-cells = <2>;
- ralink,ngpio = <24>;
- ralink,regs = [ 00 04 08 0c
- 20 24 28 2c
- 30 34 ];
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+
+ status = "disabled";
};
gpio1: gpio@638 {
@@ -74,10 +86,12 @@
gpio-controller;
#gpio-cells = <2>;
- ralink,ngpio = <16>;
- ralink,regs = [ 00 04 08 0c
- 10 14 18 1c
- 20 24 ];
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
};
gpio2: gpio@660 {
@@ -87,10 +101,21 @@
gpio-controller;
#gpio-cells = <2>;
- ralink,ngpio = <12>;
- ralink,regs = [ 00 04 08 0c
- 10 14 18 1c
- 20 24 ];
+ ralink,num-gpios = <12>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ spi@b00 {
+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
};
uartlite@c00 {
@@ -102,5 +127,46 @@
reg-shift = <2>;
};
+
+ };
+
+ ethernet@10100000 {
+ compatible = "ralink,rt3050-eth";
+ reg = <0x10100000 10000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;
+
+ status = "disabled";
+ };
+
+ esw@10110000 {
+ compatible = "ralink,rt3050-esw";
+ reg = <0x10110000 8000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+
+ status = "disabled";
+ };
+
+ wmac@10180000 {
+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
+ reg = <0x10180000 40000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ status = "disabled";
+ };
+
+ otg@101c0000 {
+ compatible = "ralink,rt3050-otg";
+ reg = <0x101c0000 40000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+
+ status = "disabled";
};
};
diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
index 148a590..dc56e58 100644
--- a/arch/mips/ralink/dts/rt3052_eval.dts
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
@@ -14,7 +14,7 @@
palmbus@10000000 {
sysc@0 {
- ralink,pinmmux = "uartlite", "spi";
+ ralink,pinmux = "uartlite", "spi";
ralink,uartmux = "gpio";
ralink,wdtmux = <0>;
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 08/18] MIPS: ralink: add RT5350 dtsi file
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (6 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 07/18] MIPS: ralink: extend RT3050 dtsi file John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 13:53 ` Jonas Gorski
2013-04-10 11:47 ` [PATCH 09/18] MIPS: ralink: make early_printk work on RT2880 John Crispin
` (9 subsequent siblings)
17 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a dtsi file for RT5350 Soc. This SoC is almost the same as RT3050 but has
OHCI/EHCI in favour of the Synopsis DWC2 core.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/dts/rt5350.dtsi | 181 ++++++++++++++++++++++++++++++++++++++
1 file changed, 181 insertions(+)
create mode 100644 arch/mips/ralink/dts/rt5350.dtsi
diff --git a/arch/mips/ralink/dts/rt5350.dtsi b/arch/mips/ralink/dts/rt5350.dtsi
new file mode 100644
index 0000000..9ca95a3
--- /dev/null
+++ b/arch/mips/ralink/dts/rt5350.dtsi
@@ -0,0 +1,181 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt5350-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600 init=/init";
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ timer@100 {
+ compatible = "ralink,rt5350-timer", "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@120 {
+ compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
+ reg = <0x120 0x10>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300 {
+ compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ gpio0: gpio@600 {
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
+ reg = <0x600 0x34>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+
+ status = "disabled";
+ };
+
+ gpio1: gpio@638 {
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
+ reg = <0x638 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ gpio2: gpio@660 {
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
+ reg = <0x660 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <12>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ spi@b00 {
+ compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ uartlite@c00 {
+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ reg-shift = <2>;
+ };
+ };
+
+ ethernet@10100000 {
+ compatible = "ralink,rt5350-eth", "ralink,rt3050-eth";
+ reg = <0x10100000 10000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;
+
+ status = "disabled";
+ };
+
+ esw@10110000 {
+ compatible = "ralink,rt5350-esw", "ralink,rt3050-esw";
+ reg = <0x10110000 8000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+
+ status = "disabled";
+ };
+
+ wmac@10180000 {
+ compatible = "ralink,rt5350-wmac", "ralink,rt2880-wmac";
+ reg = <0x10180000 40000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ status = "disabled";
+ };
+
+ ehci@101c0000 {
+ compatible = "ralink,rt5350-ehci", "ehci-platform";
+ reg = <0x101c0000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+
+ status = "disabled";
+ };
+
+ ohci@101c1000 {
+ compatible = "ralink,rt5350-ohci", "ohci-platform";
+ reg = <0x101c1000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+
+ status = "disabled";
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 08/18] MIPS: ralink: add RT5350 dtsi file
2013-04-10 11:47 ` [PATCH 08/18] MIPS: ralink: add RT5350 " John Crispin
@ 2013-04-10 13:53 ` Jonas Gorski
2013-04-10 13:54 ` John Crispin
0 siblings, 1 reply; 26+ messages in thread
From: Jonas Gorski @ 2013-04-10 13:53 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
On 10 April 2013 13:47, John Crispin <blogic@openwrt.org> wrote:
> Add a dtsi file for RT5350 Soc. This SoC is almost the same as RT3050 but has
> OHCI/EHCI in favour of the Synopsis DWC2 core.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/dts/rt5350.dtsi | 181 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 181 insertions(+)
> create mode 100644 arch/mips/ralink/dts/rt5350.dtsi
>
> diff --git a/arch/mips/ralink/dts/rt5350.dtsi b/arch/mips/ralink/dts/rt5350.dtsi
> new file mode 100644
> index 0000000..9ca95a3
> --- /dev/null
> +++ b/arch/mips/ralink/dts/rt5350.dtsi
> @@ -0,0 +1,181 @@
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ralink,rt5350-soc";
> +
> + cpus {
> + cpu@0 {
> + compatible = "mips,mips24KEc";
> + };
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,57600 init=/init";
Shouldn't this belong in the individual .dts files instead of the
.dtsi? Likewise for all the other .dtsi files added by this patchset.
Jonas
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 08/18] MIPS: ralink: add RT5350 dtsi file
2013-04-10 13:53 ` Jonas Gorski
@ 2013-04-10 13:54 ` John Crispin
0 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 13:54 UTC (permalink / raw)
To: linux-mips
On 10/04/13 15:53, Jonas Gorski wrote:
>> + chosen {
>> > + bootargs = "console=ttyS0,57600 init=/init";
> Shouldn't this belong in the individual .dts files instead of the
> .dtsi? Likewise for all the other .dtsi files added by this patchset.
>
>
> Jonas
>
>
the init=/init bit is bogus. all other boards with the exception of
maybe 2 or 3 use 57600 for console.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 09/18] MIPS: ralink: make early_printk work on RT2880
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (7 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 08/18] MIPS: ralink: add RT5350 " John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 10/18] MIPS: ralink: adds support for RT2880 SoC family John Crispin
` (8 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
RT2880 has a different location for the early serial port.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/early_printk.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
index c4ae47e..b46d041 100644
--- a/arch/mips/ralink/early_printk.c
+++ b/arch/mips/ralink/early_printk.c
@@ -11,7 +11,11 @@
#include <asm/addrspace.h>
+#ifdef CONFIG_SOC_RT288X
+#define EARLY_UART_BASE 0x300c00
+#else
#define EARLY_UART_BASE 0x10000c00
+#endif
#define UART_REG_RX 0x00
#define UART_REG_TX 0x04
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 10/18] MIPS: ralink: adds support for RT2880 SoC family
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (8 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 09/18] MIPS: ralink: make early_printk work on RT2880 John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 11/18] MIPS: ralink: add rt2880 dts files John Crispin
` (7 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add support code for rt2880 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/Kconfig | 2 +-
arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
arch/mips/ralink/Kconfig | 3 +
arch/mips/ralink/Makefile | 1 +
arch/mips/ralink/Platform | 5 +
arch/mips/ralink/rt288x.c | 143 ++++++++++++++++++++++++++++
6 files changed, 202 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
create mode 100644 arch/mips/ralink/rt288x.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 51244bf..e4da4f8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1152,7 +1152,7 @@ config BOOT_ELF32
config MIPS_L1_CACHE_SHIFT
int
- default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
+ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
default "6" if MIPS_CPU_SCACHE
default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
default "5"
diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
new file mode 100644
index 0000000..ad8b42d
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -0,0 +1,49 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _RT288X_REGS_H_
+#define _RT288X_REGS_H_
+
+#define RT2880_SYSC_BASE 0x00300000
+
+#define SYSC_REG_CHIP_NAME0 0x00
+#define SYSC_REG_CHIP_NAME1 0x04
+#define SYSC_REG_CHIP_ID 0x0c
+#define SYSC_REG_SYSTEM_CONFIG 0x10
+#define SYSC_REG_CLKCFG 0x30
+
+#define RT2880_CHIP_NAME0 0x38325452
+#define RT2880_CHIP_NAME1 0x20203038
+
+#define CHIP_ID_ID_MASK 0xff
+#define CHIP_ID_ID_SHIFT 8
+#define CHIP_ID_REV_MASK 0xff
+
+#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
+#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
+#define SYSTEM_CONFIG_CPUCLK_250 0x0
+#define SYSTEM_CONFIG_CPUCLK_266 0x1
+#define SYSTEM_CONFIG_CPUCLK_280 0x2
+#define SYSTEM_CONFIG_CPUCLK_300 0x3
+
+#define RT2880_GPIO_MODE_I2C BIT(0)
+#define RT2880_GPIO_MODE_UART0 BIT(1)
+#define RT2880_GPIO_MODE_SPI BIT(2)
+#define RT2880_GPIO_MODE_UART1 BIT(3)
+#define RT2880_GPIO_MODE_JTAG BIT(4)
+#define RT2880_GPIO_MODE_MDIO BIT(5)
+#define RT2880_GPIO_MODE_SDRAM BIT(6)
+#define RT2880_GPIO_MODE_PCI BIT(7)
+
+#define CLKCFG_SRAM_CS_N_WDT BIT(9)
+
+#endif
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index a0b0197..6723b94 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -6,6 +6,9 @@ choice
help
Select Ralink MIPS SoC type.
+ config SOC_RT288X
+ bool "RT288x"
+
config SOC_RT305X
bool "RT305x"
select USB_ARCH_HAS_HCD
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 39ef249..ce83bfc 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -8,6 +8,7 @@
obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
+obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index 6babd65..3f49e51 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -5,6 +5,11 @@ core-$(CONFIG_RALINK) += arch/mips/ralink/
cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
#
+# Ralink RT288x
+#
+load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
+
+#
# Ralink RT305x
#
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
new file mode 100644
index 0000000..8f3a0fa
--- /dev/null
+++ b/arch/mips/ralink/rt288x.c
@@ -0,0 +1,143 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mipsregs.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/rt288x.h>
+
+#include "common.h"
+
+struct ralink_pinmux_grp mode_mux[] = {
+ {
+ .name = "i2c",
+ .mask = RT2880_GPIO_MODE_I2C,
+ .gpio_first = 1,
+ .gpio_last = 2,
+ }, {
+ .name = "spi",
+ .mask = RT2880_GPIO_MODE_SPI,
+ .gpio_first = 3,
+ .gpio_last = 6,
+ }, {
+ .name = "uartlite",
+ .mask = RT2880_GPIO_MODE_UART0,
+ .gpio_first = 7,
+ .gpio_last = 14,
+ }, {
+ .name = "jtag",
+ .mask = RT2880_GPIO_MODE_JTAG,
+ .gpio_first = 17,
+ .gpio_last = 21,
+ }, {
+ .name = "mdio",
+ .mask = RT2880_GPIO_MODE_MDIO,
+ .gpio_first = 22,
+ .gpio_last = 23,
+ }, {
+ .name = "sdram",
+ .mask = RT2880_GPIO_MODE_SDRAM,
+ .gpio_first = 24,
+ .gpio_last = 39,
+ }, {
+ .name = "pci",
+ .mask = RT2880_GPIO_MODE_PCI,
+ .gpio_first = 40,
+ .gpio_last = 71,
+ }, {0}
+};
+
+void rt288x_wdt_reset(void)
+{
+ u32 t;
+
+ /* enable WDT reset output on pin SRAM_CS_N */
+ t = rt_sysc_r32(SYSC_REG_CLKCFG);
+ t |= CLKCFG_SRAM_CS_N_WDT;
+ rt_sysc_w32(t, SYSC_REG_CLKCFG);
+}
+
+struct ralink_pinmux rt_pinmux = {
+ .mode = mode_mux,
+ .wdt_reset = rt288x_wdt_reset,
+};
+
+void ralink_usb_platform(void)
+{
+}
+
+void __init ralink_clk_init(void)
+{
+ unsigned long cpu_rate;
+ u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+ t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
+
+ switch (t) {
+ case SYSTEM_CONFIG_CPUCLK_250:
+ cpu_rate = 250000000;
+ break;
+ case SYSTEM_CONFIG_CPUCLK_266:
+ cpu_rate = 266666667;
+ break;
+ case SYSTEM_CONFIG_CPUCLK_280:
+ cpu_rate = 280000000;
+ break;
+ case SYSTEM_CONFIG_CPUCLK_300:
+ cpu_rate = 300000000;
+ break;
+ }
+
+ ralink_clk_add("cpu", cpu_rate);
+ ralink_clk_add("300100.timer", cpu_rate / 2);
+ ralink_clk_add("300120.watchdog", cpu_rate / 2);
+ ralink_clk_add("300500.uart", cpu_rate / 2);
+ ralink_clk_add("300c00.uartlite", cpu_rate / 2);
+ ralink_clk_add("400000.ethernet", cpu_rate / 2);
+}
+
+void __init ralink_of_remap(void)
+{
+ rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
+ rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
+
+ if (!rt_sysc_membase || !rt_memc_membase)
+ panic("Failed to remap core resources");
+}
+
+void prom_soc_init(struct ralink_soc_info *soc_info)
+{
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
+ const char *name;
+ u32 n0;
+ u32 n1;
+ u32 id;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+ id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
+
+ if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
+ soc_info->compatible = "ralink,r2880-soc";
+ name = "RT2880";
+ } else {
+ panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
+ }
+
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %s id:%u rev:%u",
+ name,
+ (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
+ (id & CHIP_ID_REV_MASK));
+}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 11/18] MIPS: ralink: add rt2880 dts files
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (9 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 10/18] MIPS: ralink: adds support for RT2880 SoC family John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 12/18] MIPS: ralink: adds support for RT3883 SoC family John Crispin
` (6 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a dtsi file for RT2880 SoC and a sample dts file. This SoC is first one that
was released in this SoC family.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Kconfig | 4 ++
arch/mips/ralink/dts/Makefile | 1 +
arch/mips/ralink/dts/rt2880.dtsi | 116 ++++++++++++++++++++++++++++++++++
arch/mips/ralink/dts/rt2880_eval.dts | 52 +++++++++++++++
4 files changed, 173 insertions(+)
create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 6723b94..0d312fc 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -26,6 +26,10 @@ choice
config DTB_RT_NONE
bool "None"
+ config DTB_RT2880_EVAL
+ bool "RT2880 eval kit"
+ depends on SOC_RT288X
+
config DTB_RT305X_EVAL
bool "RT305x eval kit"
depends on SOC_RT305X
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
index 1a69fb3..f635a01 100644
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
diff --git a/arch/mips/ralink/dts/rt2880.dtsi b/arch/mips/ralink/dts/rt2880.dtsi
new file mode 100644
index 0000000..b57b2bd
--- /dev/null
+++ b/arch/mips/ralink/dts/rt2880.dtsi
@@ -0,0 +1,116 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt2880-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips4KEc";
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600 init=/init";
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@300000 {
+ compatible = "ralink,rt2880-sysc";
+ reg = <0x300000 0x100>;
+ };
+
+ timer@300100 {
+ compatible = "ralink,rt2880-timer";
+ reg = <0x300100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@300120 {
+ compatible = "ralink,rt2880-wdt";
+ reg = <0x300120 0x10>;
+ };
+
+ intc: intc@300200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x300200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300300 {
+ compatible = "ralink,rt2880-memc";
+ reg = <0x300300 0x100>;
+ };
+
+ gpio0: gpio@300600 {
+ compatible = "ralink,rt2880-gpio";
+ reg = <0x300600 0x34>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+ };
+
+ gpio1: gpio@300638 {
+ compatible = "ralink,rt2880-gpio";
+ reg = <0x300638 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ gpio2: gpio@300660 {
+ compatible = "ralink,rt2880-gpio";
+ reg = <0x300660 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <32>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ uartlite@300c00 {
+ compatible = "ralink,rt2880-uart", "ns16550a";
+ reg = <0x300c00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ reg-shift = <2>;
+ };
+ };
+};
diff --git a/arch/mips/ralink/dts/rt2880_eval.dts b/arch/mips/ralink/dts/rt2880_eval.dts
new file mode 100644
index 0000000..c2710c1
--- /dev/null
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+
+/include/ "rt2880.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
+ model = "Ralink RT2880 evaluation board";
+
+ memory@8000000 {
+ reg = <0x0 0x2000000>;
+ };
+
+ palmbus@10000000 {
+ sysc@300000 {
+ ralink,pinmux = "uartlite", "spi";
+ ralink,uartmux = "gpio";
+ ralink,wdtmux = <0>;
+ };
+ };
+
+ cfi@1f000000 {
+ compatible = "cfi-flash";
+ reg = <0x1f000000 0x800000>;
+
+ bank-width = <2>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+ partition@30000 {
+ label = "uboot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "calibration";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ partition@50000 {
+ label = "linux";
+ reg = <0x50000 0x7b0000>;
+ };
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 12/18] MIPS: ralink: adds support for RT3883 SoC family
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (10 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 11/18] MIPS: ralink: add rt2880 dts files John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 13/18] MIPS: ralink: add rt3883 dts files John Crispin
` (5 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add support code for rt3883 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
arch/mips/ralink/Kconfig | 5 +
arch/mips/ralink/Makefile | 1 +
arch/mips/ralink/Platform | 5 +
arch/mips/ralink/rt3883.c | 244 +++++++++++++++++++++++++++
5 files changed, 502 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
create mode 100644 arch/mips/ralink/rt3883.c
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
new file mode 100644
index 0000000..b91c6c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -0,0 +1,247 @@
+/*
+ * Ralink RT3662/RT3883 SoC register definitions
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _RT3883_REGS_H_
+#define _RT3883_REGS_H_
+
+#include <linux/bitops.h>
+
+#define RT3883_SDRAM_BASE 0x00000000
+#define RT3883_SYSC_BASE 0x10000000
+#define RT3883_TIMER_BASE 0x10000100
+#define RT3883_INTC_BASE 0x10000200
+#define RT3883_MEMC_BASE 0x10000300
+#define RT3883_UART0_BASE 0x10000500
+#define RT3883_PIO_BASE 0x10000600
+#define RT3883_FSCC_BASE 0x10000700
+#define RT3883_NANDC_BASE 0x10000810
+#define RT3883_I2C_BASE 0x10000900
+#define RT3883_I2S_BASE 0x10000a00
+#define RT3883_SPI_BASE 0x10000b00
+#define RT3883_UART1_BASE 0x10000c00
+#define RT3883_PCM_BASE 0x10002000
+#define RT3883_GDMA_BASE 0x10002800
+#define RT3883_CODEC1_BASE 0x10003000
+#define RT3883_CODEC2_BASE 0x10003800
+#define RT3883_FE_BASE 0x10100000
+#define RT3883_ROM_BASE 0x10118000
+#define RT3883_USBDEV_BASE 0x10112000
+#define RT3883_PCI_BASE 0x10140000
+#define RT3883_WLAN_BASE 0x10180000
+#define RT3883_USBHOST_BASE 0x101c0000
+#define RT3883_BOOT_BASE 0x1c000000
+#define RT3883_SRAM_BASE 0x1e000000
+#define RT3883_PCIMEM_BASE 0x20000000
+
+#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
+#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
+
+#define RT3883_SYSC_SIZE 0x100
+#define RT3883_TIMER_SIZE 0x100
+#define RT3883_INTC_SIZE 0x100
+#define RT3883_MEMC_SIZE 0x100
+#define RT3883_UART0_SIZE 0x100
+#define RT3883_UART1_SIZE 0x100
+#define RT3883_PIO_SIZE 0x100
+#define RT3883_FSCC_SIZE 0x100
+#define RT3883_NANDC_SIZE 0x0f0
+#define RT3883_I2C_SIZE 0x100
+#define RT3883_I2S_SIZE 0x100
+#define RT3883_SPI_SIZE 0x100
+#define RT3883_PCM_SIZE 0x800
+#define RT3883_GDMA_SIZE 0x800
+#define RT3883_CODEC1_SIZE 0x800
+#define RT3883_CODEC2_SIZE 0x800
+#define RT3883_FE_SIZE 0x10000
+#define RT3883_ROM_SIZE 0x4000
+#define RT3883_USBDEV_SIZE 0x4000
+#define RT3883_PCI_SIZE 0x40000
+#define RT3883_WLAN_SIZE 0x40000
+#define RT3883_USBHOST_SIZE 0x40000
+#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
+#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
+
+/* SYSC registers */
+#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
+#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
+#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
+#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
+#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
+#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
+#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
+#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
+#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
+#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
+#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
+#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
+#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
+#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
+#define RT3883_SYSC_REG_PMU 0x88
+#define RT3883_SYSC_REG_PMU1 0x8c
+
+#define RT3883_CHIP_NAME0 0x38335452
+#define RT3883_CHIP_NAME1 0x20203338
+
+#define RT3883_REVID_VER_ID_MASK 0x0f
+#define RT3883_REVID_VER_ID_SHIFT 8
+#define RT3883_REVID_ECO_ID_MASK 0x0f
+
+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
+#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
+#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
+#define RT3883_SYSCFG0_CPUCLK_250 0x0
+#define RT3883_SYSCFG0_CPUCLK_384 0x1
+#define RT3883_SYSCFG0_CPUCLK_480 0x2
+#define RT3883_SYSCFG0_CPUCLK_500 0x3
+
+#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
+#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
+#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
+#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
+#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
+
+#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
+#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
+#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
+#define RT3883_GPIO_MODE_I2C BIT(0)
+#define RT3883_GPIO_MODE_SPI BIT(1)
+#define RT3883_GPIO_MODE_UART0_SHIFT 2
+#define RT3883_GPIO_MODE_UART0_MASK 0x7
+#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
+#define RT3883_GPIO_MODE_UARTF 0x0
+#define RT3883_GPIO_MODE_PCM_UARTF 0x1
+#define RT3883_GPIO_MODE_PCM_I2S 0x2
+#define RT3883_GPIO_MODE_I2S_UARTF 0x3
+#define RT3883_GPIO_MODE_PCM_GPIO 0x4
+#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
+#define RT3883_GPIO_MODE_GPIO_I2S 0x6
+#define RT3883_GPIO_MODE_GPIO 0x7
+#define RT3883_GPIO_MODE_UART1 BIT(5)
+#define RT3883_GPIO_MODE_JTAG BIT(6)
+#define RT3883_GPIO_MODE_MDIO BIT(7)
+#define RT3883_GPIO_MODE_GE1 BIT(9)
+#define RT3883_GPIO_MODE_GE2 BIT(10)
+#define RT3883_GPIO_MODE_PCI_SHIFT 11
+#define RT3883_GPIO_MODE_PCI_MASK 0x7
+#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
+#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
+#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
+#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
+#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
+#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
+#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
+#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
+#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
+#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
+#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
+
+#define RT3883_GPIO_I2C_SD 1
+#define RT3883_GPIO_I2C_SCLK 2
+#define RT3883_GPIO_SPI_CS0 3
+#define RT3883_GPIO_SPI_CLK 4
+#define RT3883_GPIO_SPI_MOSI 5
+#define RT3883_GPIO_SPI_MISO 6
+#define RT3883_GPIO_7 7
+#define RT3883_GPIO_10 10
+#define RT3883_GPIO_14 14
+#define RT3883_GPIO_UART1_TXD 15
+#define RT3883_GPIO_UART1_RXD 16
+#define RT3883_GPIO_JTAG_TDO 17
+#define RT3883_GPIO_JTAG_TDI 18
+#define RT3883_GPIO_JTAG_TMS 19
+#define RT3883_GPIO_JTAG_TCLK 20
+#define RT3883_GPIO_JTAG_TRST_N 21
+#define RT3883_GPIO_MDIO_MDC 22
+#define RT3883_GPIO_MDIO_MDIO 23
+#define RT3883_GPIO_LNA_PE_A0 32
+#define RT3883_GPIO_LNA_PE_A1 33
+#define RT3883_GPIO_LNA_PE_A2 34
+#define RT3883_GPIO_LNA_PE_G0 35
+#define RT3883_GPIO_LNA_PE_G1 36
+#define RT3883_GPIO_LNA_PE_G2 37
+#define RT3883_GPIO_PCI_AD0 40
+#define RT3883_GPIO_PCI_AD31 71
+#define RT3883_GPIO_GE2_TXD0 72
+#define RT3883_GPIO_GE2_TXD1 73
+#define RT3883_GPIO_GE2_TXD2 74
+#define RT3883_GPIO_GE2_TXD3 75
+#define RT3883_GPIO_GE2_TXEN 76
+#define RT3883_GPIO_GE2_TXCLK 77
+#define RT3883_GPIO_GE2_RXD0 78
+#define RT3883_GPIO_GE2_RXD1 79
+#define RT3883_GPIO_GE2_RXD2 80
+#define RT3883_GPIO_GE2_RXD3 81
+#define RT3883_GPIO_GE2_RXDV 82
+#define RT3883_GPIO_GE2_RXCLK 83
+#define RT3883_GPIO_GE1_TXD0 84
+#define RT3883_GPIO_GE1_TXD1 85
+#define RT3883_GPIO_GE1_TXD2 86
+#define RT3883_GPIO_GE1_TXD3 87
+#define RT3883_GPIO_GE1_TXEN 88
+#define RT3883_GPIO_GE1_TXCLK 89
+#define RT3883_GPIO_GE1_RXD0 90
+#define RT3883_GPIO_GE1_RXD1 91
+#define RT3883_GPIO_GE1_RXD2 92
+#define RT3883_GPIO_GE1_RXD3 93
+#define RT3883_GPIO_GE1_RXDV 94
+#define RT3883_GPIO_GE1_RXCLK 95
+
+#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
+#define RT3883_RSTCTRL_FLASH BIT(26)
+#define RT3883_RSTCTRL_UDEV BIT(25)
+#define RT3883_RSTCTRL_PCI BIT(24)
+#define RT3883_RSTCTRL_PCIE BIT(23)
+#define RT3883_RSTCTRL_UHST BIT(22)
+#define RT3883_RSTCTRL_FE BIT(21)
+#define RT3883_RSTCTRL_WLAN BIT(20)
+#define RT3883_RSTCTRL_UART1 BIT(29)
+#define RT3883_RSTCTRL_SPI BIT(18)
+#define RT3883_RSTCTRL_I2S BIT(17)
+#define RT3883_RSTCTRL_I2C BIT(16)
+#define RT3883_RSTCTRL_NAND BIT(15)
+#define RT3883_RSTCTRL_DMA BIT(14)
+#define RT3883_RSTCTRL_PIO BIT(13)
+#define RT3883_RSTCTRL_UART BIT(12)
+#define RT3883_RSTCTRL_PCM BIT(11)
+#define RT3883_RSTCTRL_MC BIT(10)
+#define RT3883_RSTCTRL_INTC BIT(9)
+#define RT3883_RSTCTRL_TIMER BIT(8)
+#define RT3883_RSTCTRL_SYS BIT(0)
+
+#define RT3883_INTC_INT_SYSCTL BIT(0)
+#define RT3883_INTC_INT_TIMER0 BIT(1)
+#define RT3883_INTC_INT_TIMER1 BIT(2)
+#define RT3883_INTC_INT_IA BIT(3)
+#define RT3883_INTC_INT_PCM BIT(4)
+#define RT3883_INTC_INT_UART0 BIT(5)
+#define RT3883_INTC_INT_PIO BIT(6)
+#define RT3883_INTC_INT_DMA BIT(7)
+#define RT3883_INTC_INT_NAND BIT(8)
+#define RT3883_INTC_INT_PERFC BIT(9)
+#define RT3883_INTC_INT_I2S BIT(10)
+#define RT3883_INTC_INT_UART1 BIT(12)
+#define RT3883_INTC_INT_UHST BIT(18)
+#define RT3883_INTC_INT_UDEV BIT(19)
+
+/* FLASH/SRAM/Codec Controller registers */
+#define RT3883_FSCC_REG_FLASH_CFG0 0x00
+#define RT3883_FSCC_REG_FLASH_CFG1 0x04
+#define RT3883_FSCC_REG_CODEC_CFG0 0x40
+#define RT3883_FSCC_REG_CODEC_CFG1 0x44
+
+#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
+#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
+#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
+#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
+#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
+
+#endif /* _RT3883_REGS_H_ */
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 0d312fc..f21cbaa 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -15,6 +15,11 @@ choice
select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI
+ config SOC_RT3883
+ bool "RT3883"
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
+
endchoice
choice
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index ce83bfc..87f6ca9 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
+obj-$(CONFIG_SOC_RT3883) += rt3883.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index 3f49e51..f67c08d 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
# Ralink RT305x
#
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
+
+#
+# Ralink RT3883
+#
+load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
new file mode 100644
index 0000000..701c9fd
--- /dev/null
+++ b/arch/mips/ralink/rt3883.c
@@ -0,0 +1,244 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mipsregs.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/rt3883.h>
+
+#include "common.h"
+
+struct ralink_pinmux_grp mode_mux[] = {
+ {
+ .name = "i2c",
+ .mask = RT3883_GPIO_MODE_I2C,
+ .gpio_first = RT3883_GPIO_I2C_SD,
+ .gpio_last = RT3883_GPIO_I2C_SCLK,
+ }, {
+ .name = "spi",
+ .mask = RT3883_GPIO_MODE_SPI,
+ .gpio_first = RT3883_GPIO_SPI_CS0,
+ .gpio_last = RT3883_GPIO_SPI_MISO,
+ }, {
+ .name = "uartlite",
+ .mask = RT3883_GPIO_MODE_UART1,
+ .gpio_first = RT3883_GPIO_UART1_TXD,
+ .gpio_last = RT3883_GPIO_UART1_RXD,
+ }, {
+ .name = "jtag",
+ .mask = RT3883_GPIO_MODE_JTAG,
+ .gpio_first = RT3883_GPIO_JTAG_TDO,
+ .gpio_last = RT3883_GPIO_JTAG_TCLK,
+ }, {
+ .name = "mdio",
+ .mask = RT3883_GPIO_MODE_MDIO,
+ .gpio_first = RT3883_GPIO_MDIO_MDC,
+ .gpio_last = RT3883_GPIO_MDIO_MDIO,
+ }, {
+ .name = "ge1",
+ .mask = RT3883_GPIO_MODE_GE1,
+ .gpio_first = RT3883_GPIO_GE1_TXD0,
+ .gpio_last = RT3883_GPIO_GE1_RXCLK,
+ }, {
+ .name = "ge2",
+ .mask = RT3883_GPIO_MODE_GE2,
+ .gpio_first = RT3883_GPIO_GE2_TXD0,
+ .gpio_last = RT3883_GPIO_GE2_RXCLK,
+ }, {
+ .name = "pci",
+ .mask = RT3883_GPIO_MODE_PCI,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {
+ .name = "lna a",
+ .mask = RT3883_GPIO_MODE_LNA_A,
+ .gpio_first = RT3883_GPIO_LNA_PE_A0,
+ .gpio_last = RT3883_GPIO_LNA_PE_A2,
+ }, {
+ .name = "lna g",
+ .mask = RT3883_GPIO_MODE_LNA_G,
+ .gpio_first = RT3883_GPIO_LNA_PE_G0,
+ .gpio_last = RT3883_GPIO_LNA_PE_G2,
+ }, {0}
+};
+
+struct ralink_pinmux_grp uart_mux[] = {
+ {
+ .name = "uartf",
+ .mask = RT3883_GPIO_MODE_UARTF,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "pcm uartf",
+ .mask = RT3883_GPIO_MODE_PCM_UARTF,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "pcm i2s",
+ .mask = RT3883_GPIO_MODE_PCM_I2S,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "i2s uartf",
+ .mask = RT3883_GPIO_MODE_I2S_UARTF,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "pcm gpio",
+ .mask = RT3883_GPIO_MODE_PCM_GPIO,
+ .gpio_first = RT3883_GPIO_10,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "gpio uartf",
+ .mask = RT3883_GPIO_MODE_GPIO_UARTF,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "gpio i2s",
+ .mask = RT3883_GPIO_MODE_GPIO_I2S,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {
+ .name = "gpio",
+ .mask = RT3883_GPIO_MODE_GPIO,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
+ }, {0}
+};
+
+struct ralink_pinmux_grp pci_mux[] = {
+ {
+ .name = "pci-dev",
+ .mask = 0,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {
+ .name = "pci-host2",
+ .mask = 1,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {
+ .name = "pci-host1",
+ .mask = 2,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {
+ .name = "pci-fnc",
+ .mask = 3,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {
+ .name = "pci-gpio",
+ .mask = 7,
+ .gpio_first = RT3883_GPIO_PCI_AD0,
+ .gpio_last = RT3883_GPIO_PCI_AD31,
+ }, {0}
+};
+
+static void rt3883_wdt_reset(void)
+{
+ u32 t;
+
+ /* enable WDT reset output on GPIO 2 */
+ t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
+ t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
+ rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
+}
+
+struct ralink_pinmux rt_pinmux = {
+ .mode = mode_mux,
+ .uart = uart_mux,
+ .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
+ .uart_mask = RT3883_GPIO_MODE_GPIO,
+ .wdt_reset = rt3883_wdt_reset,
+ .pci = pci_mux,
+ .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
+ .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
+};
+
+void __init ralink_clk_init(void)
+{
+ unsigned long cpu_rate, sys_rate;
+ u32 syscfg0;
+ u32 clksel;
+ u32 ddr2;
+
+ syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
+ clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
+ RT3883_SYSCFG0_CPUCLK_MASK);
+ ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
+
+ switch (clksel) {
+ case RT3883_SYSCFG0_CPUCLK_250:
+ cpu_rate = 250000000;
+ sys_rate = (ddr2) ? 125000000 : 83000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_384:
+ cpu_rate = 384000000;
+ sys_rate = (ddr2) ? 128000000 : 96000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_480:
+ cpu_rate = 480000000;
+ sys_rate = (ddr2) ? 160000000 : 120000000;
+ break;
+ case RT3883_SYSCFG0_CPUCLK_500:
+ cpu_rate = 500000000;
+ sys_rate = (ddr2) ? 166000000 : 125000000;
+ break;
+ }
+
+ ralink_clk_add("cpu", cpu_rate);
+ ralink_clk_add("10000100.timer", sys_rate);
+ ralink_clk_add("10000120.watchdog", sys_rate);
+ ralink_clk_add("10000500.uart", 40000000);
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", 40000000);
+ ralink_clk_add("10100000.ethernet", sys_rate);
+}
+
+void __init ralink_of_remap(void)
+{
+ rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
+ rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
+
+ if (!rt_sysc_membase || !rt_memc_membase)
+ panic("Failed to remap core resources");
+}
+
+void prom_soc_init(struct ralink_soc_info *soc_info)
+{
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
+ const char *name;
+ u32 n0;
+ u32 n1;
+ u32 id;
+
+ n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
+ n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
+ id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
+
+ if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
+ soc_info->compatible = "ralink,rt3883-soc";
+ name = "RT3883";
+ } else {
+ panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
+ }
+
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %s ver:%u eco:%u",
+ name,
+ (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
+ (id & RT3883_REVID_ECO_ID_MASK));
+}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 13/18] MIPS: ralink: add rt3883 dts files
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (11 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 12/18] MIPS: ralink: adds support for RT3883 SoC family John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 14/18] MIPS: ralink: adds support for MT7620 SoC family John Crispin
` (4 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add a dtsi file for RT3883 SoC. This SoC is almost the same as RT3050 but has
OHCI/EHCI in favour of the Synopsis DWC2 core. There is also a 3x3 802.11n
wifi core.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Kconfig | 4 +
arch/mips/ralink/dts/Makefile | 1 +
arch/mips/ralink/dts/rt3883.dtsi | 186 ++++++++++++++++++++++++++++++++++
arch/mips/ralink/dts/rt3883_eval.dts | 52 ++++++++++
4 files changed, 243 insertions(+)
create mode 100644 arch/mips/ralink/dts/rt3883.dtsi
create mode 100644 arch/mips/ralink/dts/rt3883_eval.dts
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index f21cbaa..2ef69ee 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -39,6 +39,10 @@ choice
bool "RT305x eval kit"
depends on SOC_RT305X
+ config DTB_RT3883_EVAL
+ bool "RT3883 eval kit"
+ depends on SOC_RT3883
+
endchoice
endif
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
index f635a01..040a986 100644
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
+obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
diff --git a/arch/mips/ralink/dts/rt3883.dtsi b/arch/mips/ralink/dts/rt3883.dtsi
new file mode 100644
index 0000000..1e80ad3
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3883.dtsi
@@ -0,0 +1,186 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt3883-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips74Kc";
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600 init=/init";
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ timer@100 {
+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@120 {
+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
+ reg = <0x120 0x10>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300 {
+ compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ gpio0: gpio@600 {
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+ reg = <0x600 0x34>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+
+ status = "disabled";
+ };
+
+ gpio1: gpio@638 {
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+ reg = <0x638 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ gpio2: gpio@660 {
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+ reg = <0x660 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <32>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ gpio3: gpio@688 {
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+ reg = <0x688 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
+ spi@b00 {
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uartlite@c00 {
+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ reg-shift = <2>;
+ };
+ };
+
+ ethernet@10100000 {
+ compatible = "ralink,rt3883-eth";
+ reg = <0x10100000 10000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;
+
+ status = "disabled";
+ };
+
+ wmac@10180000 {
+ compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
+ reg = <0x10180000 40000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ status = "disabled";
+ };
+
+ ehci@101c0000 {
+ compatible = "ralink,rt3883-ehci", "ehci-platform";
+ reg = <0x101c0000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+
+ status = "disabled";
+ };
+
+ ohci@101c1000 {
+ compatible = "ralink,rt3883-ohci", "ohci-platform";
+ reg = <0x101c1000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+
+ status = "disabled";
+ };
+};
diff --git a/arch/mips/ralink/dts/rt3883_eval.dts b/arch/mips/ralink/dts/rt3883_eval.dts
new file mode 100644
index 0000000..ca42e68
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+
+/include/ "rt3883.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
+ model = "Ralink RT3883 evaluation board";
+
+ memory@0 {
+ reg = <0x0 0x4000000>;
+ };
+
+ palmbus@10000000 {
+ sysc@0 {
+ ralink,pinmux = "uartlite", "spi";
+ ralink,uartmux = "gpio";
+ ralink,wdtmux = <0>;
+ };
+ };
+
+ cfi@1f000000 {
+ compatible = "cfi-flash";
+ reg = <0x1f000000 0x800000>;
+
+ bank-width = <2>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+ partition@30000 {
+ label = "uboot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "calibration";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ partition@50000 {
+ label = "linux";
+ reg = <0x50000 0x7b0000>;
+ };
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 14/18] MIPS: ralink: adds support for MT7620 SoC family
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (12 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 13/18] MIPS: ralink: add rt3883 dts files John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 15/18] MIPS: ralink: add MT7620 dts files John Crispin
` (3 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Add support code for mt7620 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/mt7620.h | 66 +++++++++
arch/mips/ralink/Kconfig | 3 +
arch/mips/ralink/Makefile | 1 +
arch/mips/ralink/Platform | 5 +
arch/mips/ralink/mt7620.c | 209 ++++++++++++++++++++++++++++
5 files changed, 284 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
create mode 100644 arch/mips/ralink/mt7620.c
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
new file mode 100644
index 0000000..3d51235
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -0,0 +1,66 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _MT7620_REGS_H_
+#define _MT7620_REGS_H_
+
+#define MT7620_SYSC_BASE 0x10000000
+
+#define SYSC_REG_CHIP_NAME0 0x00
+#define SYSC_REG_CHIP_NAME1 0x04
+#define SYSC_REG_CHIP_REV 0x0c
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CPLL_CONFIG0 0x54
+#define SYSC_REG_CPLL_CONFIG1 0x58
+
+#define MT7620N_CHIP_NAME0 0x33365452
+#define MT7620N_CHIP_NAME1 0x20203235
+
+#define MT7620A_CHIP_NAME0 0x3637544d
+#define MT7620A_CHIP_NAME1 0x20203032
+
+#define CHIP_REV_PKG_MASK 0x1
+#define CHIP_REV_PKG_SHIFT 16
+#define CHIP_REV_VER_MASK 0xf
+#define CHIP_REV_VER_SHIFT 8
+#define CHIP_REV_ECO_MASK 0xf
+
+#define MT7620_CPLL_SW_CONFIG_SHIFT 31
+#define MT7620_CPLL_SW_CONFIG_MASK 0x1
+#define MT7620_CPLL_CPU_CLK_SHIFT 24
+#define MT7620_CPLL_CPU_CLK_MASK 0x1
+
+#define MT7620_GPIO_MODE_I2C BIT(0)
+#define MT7620_GPIO_MODE_UART0_SHIFT 2
+#define MT7620_GPIO_MODE_UART0_MASK 0x7
+#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
+#define MT7620_GPIO_MODE_UARTF 0x0
+#define MT7620_GPIO_MODE_PCM_UARTF 0x1
+#define MT7620_GPIO_MODE_PCM_I2S 0x2
+#define MT7620_GPIO_MODE_I2S_UARTF 0x3
+#define MT7620_GPIO_MODE_PCM_GPIO 0x4
+#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
+#define MT7620_GPIO_MODE_GPIO_I2S 0x6
+#define MT7620_GPIO_MODE_GPIO 0x7
+#define MT7620_GPIO_MODE_UART1 BIT(5)
+#define MT7620_GPIO_MODE_MDIO BIT(8)
+#define MT7620_GPIO_MODE_RGMII1 BIT(9)
+#define MT7620_GPIO_MODE_RGMII2 BIT(10)
+#define MT7620_GPIO_MODE_SPI BIT(11)
+#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
+#define MT7620_GPIO_MODE_WLED BIT(13)
+#define MT7620_GPIO_MODE_JTAG BIT(15)
+#define MT7620_GPIO_MODE_EPHY BIT(15)
+#define MT7620_GPIO_MODE_WDT BIT(22)
+
+#endif
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 2ef69ee..493411f 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -20,6 +20,9 @@ choice
select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI
+ config SOC_MT7620
+ bool "MT7620"
+
endchoice
choice
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 87f6ca9..341b4de 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
obj-$(CONFIG_SOC_RT3883) += rt3883.o
+obj-$(CONFIG_SOC_MT7620) += mt7620.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index f67c08d..b2cbf16 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
# Ralink RT3883
#
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
+
+#
+# Ralink MT7620
+#
+load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
new file mode 100644
index 0000000..e7a0e60
--- /dev/null
+++ b/arch/mips/ralink/mt7620.c
@@ -0,0 +1,209 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mipsregs.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/mt7620.h>
+
+#include "common.h"
+
+
+struct ralink_pinmux_grp mode_mux[] = {
+ {
+ .name = "i2c",
+ .mask = MT7620_GPIO_MODE_I2C,
+ .gpio_first = 1,
+ .gpio_last = 2,
+ }, {
+ .name = "spi",
+ .mask = MT7620_GPIO_MODE_SPI,
+ .gpio_first = 3,
+ .gpio_last = 6,
+ }, {
+ .name = "uartlite",
+ .mask = MT7620_GPIO_MODE_UART1,
+ .gpio_first = 15,
+ .gpio_last = 16,
+ }, {
+ .name = "wdt",
+ .mask = MT7620_GPIO_MODE_WDT,
+ .gpio_first = 17,
+ .gpio_last = 17,
+ }, {
+ .name = "mdio",
+ .mask = MT7620_GPIO_MODE_MDIO,
+ .gpio_first = 22,
+ .gpio_last = 23,
+ }, {
+ .name = "rgmii1",
+ .mask = MT7620_GPIO_MODE_RGMII1,
+ .gpio_first = 24,
+ .gpio_last = 35,
+ }, {
+ .name = "spi refclk",
+ .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
+ .gpio_first = 37,
+ .gpio_last = 39,
+ }, {
+ .name = "jtag",
+ .mask = MT7620_GPIO_MODE_JTAG,
+ .gpio_first = 40,
+ .gpio_last = 44,
+ }, {
+ /* shared lines with jtag */
+ .name = "ephy",
+ .mask = MT7620_GPIO_MODE_EPHY,
+ .gpio_first = 40,
+ .gpio_last = 44,
+ }, {
+ .name = "nand",
+ .mask = MT7620_GPIO_MODE_JTAG,
+ .gpio_first = 45,
+ .gpio_last = 59,
+ }, {
+ .name = "rgmii2",
+ .mask = MT7620_GPIO_MODE_RGMII2,
+ .gpio_first = 60,
+ .gpio_last = 71,
+ }, {
+ .name = "wled",
+ .mask = MT7620_GPIO_MODE_WLED,
+ .gpio_first = 72,
+ .gpio_last = 72,
+ }, {0}
+};
+
+
+struct ralink_pinmux_grp uart_mux[] = {
+ {
+ .name = "uartf",
+ .mask = MT7620_GPIO_MODE_UARTF,
+ .gpio_first = 7,
+ .gpio_last = 14,
+ }, {
+ .name = "pcm uartf",
+ .mask = MT7620_GPIO_MODE_PCM_UARTF,
+ .gpio_first = 7,
+ .gpio_last = 14,
+ }, {
+ .name = "pcm i2s",
+ .mask = MT7620_GPIO_MODE_PCM_I2S,
+ .gpio_first = 7,
+ .gpio_last = 14,
+ }, {
+ .name = "i2s uartf",
+ .mask = MT7620_GPIO_MODE_I2S_UARTF,
+ .gpio_first = 7,
+ .gpio_last = 14,
+ }, {
+ .name = "pcm gpio",
+ .mask = MT7620_GPIO_MODE_PCM_GPIO,
+ .gpio_first = 11,
+ .gpio_last = 14,
+ }, {
+ .name = "gpio uartf",
+ .mask = MT7620_GPIO_MODE_GPIO_UARTF,
+ .gpio_first = 7,
+ .gpio_last = 10,
+ }, {
+ .name = "gpio i2s",
+ .mask = MT7620_GPIO_MODE_GPIO_I2S,
+ .gpio_first = 7,
+ .gpio_last = 10,
+ }, {
+ .name = "gpio",
+ .mask = MT7620_GPIO_MODE_GPIO,
+ }, {0}
+};
+
+void mt7620_wdt_reset(void)
+{
+}
+
+struct ralink_pinmux rt_pinmux = {
+ .mode = mode_mux,
+ .uart = uart_mux,
+ .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
+ .wdt_reset = mt7620_wdt_reset,
+};
+
+void __init ralink_clk_init(void)
+{
+ unsigned long cpu_rate, sys_rate;
+ u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
+ u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
+
+ c0 = (c0 >> MT7620_CPLL_SW_CONFIG_SHIFT) &
+ MT7620_CPLL_SW_CONFIG_MASK;
+ c1 = (c1 >> MT7620_CPLL_CPU_CLK_SHIFT) &
+ MT7620_CPLL_CPU_CLK_MASK;
+ if (c1 == 0x01) {
+ cpu_rate = 480000000;
+ } else {
+ if (c1 == 0x0) {
+ cpu_rate = 600000000;
+ } else {
+ /* TODO calculate custom clock from pll settings */
+ BUG();
+ }
+ }
+ /* FIXME SDR - 4, DDR - 3 */
+ sys_rate = cpu_rate / 4;
+
+ ralink_clk_add("cpu", cpu_rate);
+ ralink_clk_add("10000100.timer", 40000000);
+ ralink_clk_add("10000500.uart", 40000000);
+ ralink_clk_add("10000c00.uartlite", 40000000);
+}
+
+void __init ralink_of_remap(void)
+{
+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620-sysc");
+ rt_memc_membase = plat_of_remap_node("ralink,mt7620-memc");
+
+ if (!rt_sysc_membase || !rt_memc_membase)
+ panic("Failed to remap core resources");
+}
+
+void prom_soc_init(struct ralink_soc_info *soc_info)
+{
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
+ unsigned char *name = NULL;
+ u32 n0;
+ u32 n1;
+ u32 rev;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+
+ if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
+ name = "MT7620N";
+ soc_info->compatible = "ralink,mt7620n-soc";
+ } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
+ name = "MT7620A";
+ soc_info->compatible = "ralink,mt7620a-soc";
+ } else {
+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
+ }
+
+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
+
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %s ver:%u eco:%u",
+ name,
+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
+ (rev & CHIP_REV_ECO_MASK));
+}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 15/18] MIPS: ralink: add MT7620 dts files
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (13 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 14/18] MIPS: ralink: adds support for MT7620 SoC family John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 16/18] MIPS: ralink: add support for periodic timer irq John Crispin
` (2 subsequent siblings)
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
by Mediatek.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Kconfig | 4 +
arch/mips/ralink/dts/Makefile | 1 +
arch/mips/ralink/dts/mt7620.dtsi | 138 ++++++++++++++++++++++++++++++++++
arch/mips/ralink/dts/mt7620_eval.dts | 22 ++++++
4 files changed, 165 insertions(+)
create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 493411f..8254502 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -46,6 +46,10 @@ choice
bool "RT3883 eval kit"
depends on SOC_RT3883
+ config DTB_MT7620_EVAL
+ bool "MT7620 eval kit"
+ depends on SOC_MT7620
+
endchoice
endif
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
index 040a986..036603a 100644
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
+obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
diff --git a/arch/mips/ralink/dts/mt7620.dtsi b/arch/mips/ralink/dts/mt7620.dtsi
new file mode 100644
index 0000000..59f057f
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620.dtsi
@@ -0,0 +1,138 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600 init=/init";
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ timer@100 {
+ compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@120 {
+ compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
+ reg = <0x120 0x10>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300 {
+ compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ gpio0: gpio@600 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x600 0x34>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+ };
+
+ gpio1: gpio@638 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x638 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ gpio2: gpio@660 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x660 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <32>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ gpio3: gpio@688 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x688 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <1>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ spi@b00 {
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uartlite@c00 {
+ compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ reg-shift = <2>;
+ };
+ };
+};
diff --git a/arch/mips/ralink/dts/mt7620_eval.dts b/arch/mips/ralink/dts/mt7620_eval.dts
new file mode 100644
index 0000000..ad20d14
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620_eval.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+
+/include/ "mt7620.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+ model = "Ralink MT7620 evaluation board";
+
+ memory@0 {
+ reg = <0x0 0x4000000>;
+ };
+
+ palmbus@10000000 {
+ sysc@0 {
+ ralink,pinmux = "uartlite", "spi";
+ ralink,uartmux = "gpio";
+ ralink,wdtmux = <0>;
+ };
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 16/18] MIPS: ralink: add support for periodic timer irq
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (14 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 15/18] MIPS: ralink: add MT7620 dts files John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 13:41 ` Lars-Peter Clausen
2013-04-10 11:47 ` [PATCH 17/18] MIPS: ralink: add cpu-feature-overrides.h John Crispin
2013-04-10 11:47 ` [PATCH 18/18] MIPS: ralink: add support for runtime memory detection John Crispin
17 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
Adds a driver for the periodic timer found on Ralink SoC.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Makefile | 2 +-
arch/mips/ralink/timer.c | 192 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/ralink/timer.c
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 341b4de..cae7d88 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,7 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
new file mode 100644
index 0000000..f3bd44d
--- /dev/null
+++ b/arch/mips/ralink/timer.c
@@ -0,0 +1,192 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/of_gpio.h>
+#include <linux/clk.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#define TIMER_REG_TMRSTAT 0x00
+#define TIMER_REG_TMR0LOAD 0x10
+#define TIMER_REG_TMR0CTL 0x18
+
+#define TMRSTAT_TMR0INT BIT(0)
+
+#define TMR0CTL_ENABLE BIT(7)
+#define TMR0CTL_MODE_PERIODIC BIT(4)
+#define TMR0CTL_PRESCALER 1
+#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
+#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
+
+struct rt_timer {
+ struct device *dev;
+ void __iomem *membase;
+ int irq;
+ unsigned long timer_freq;
+ unsigned long timer_div;
+};
+
+static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
+{
+ __raw_writel(val, rt->membase + reg);
+}
+
+static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
+{
+ return __raw_readl(rt->membase + reg);
+}
+
+static irqreturn_t rt_timer_irq(int irq, void *_rt)
+{
+ struct rt_timer *rt = (struct rt_timer *) _rt;
+
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+ rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
+
+ return IRQ_HANDLED;
+}
+
+
+static int rt_timer_request(struct rt_timer *rt)
+{
+ int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
+ dev_name(rt->dev), rt);
+ if (err) {
+ dev_err(rt->dev, "failed to request irq\n");
+ } else {
+ u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+ }
+ return err;
+}
+
+static void rt_timer_free(struct rt_timer *rt)
+{
+ free_irq(rt->irq, rt);
+}
+
+static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
+{
+ if (rt->timer_freq < divisor)
+ rt->timer_div = rt->timer_freq;
+ else
+ rt->timer_div = divisor;
+
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+
+ return 0;
+}
+
+static int rt_timer_enable(struct rt_timer *rt)
+{
+ u32 t;
+
+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+
+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
+ t |= TMR0CTL_ENABLE;
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+
+ return 0;
+}
+
+static void rt_timer_disable(struct rt_timer *rt)
+{
+ u32 t;
+
+ t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
+ t &= ~TMR0CTL_ENABLE;
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+}
+
+static int rt_timer_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct rt_timer *rt;
+ struct clk *clk;
+
+ if (!res) {
+ dev_err(&pdev->dev, "no memory resource found\n");
+ return -EINVAL;
+ }
+
+ rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
+ if (!rt) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ rt->irq = platform_get_irq(pdev, 0);
+ if (!rt->irq) {
+ dev_err(&pdev->dev, "failed to load irq\n");
+ return -ENOENT;
+ }
+
+ rt->membase = devm_ioremap_resource(&pdev->dev, res);
+ if (!rt->membase) {
+ dev_err(&pdev->dev, "failed to ioremap\n");
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed get clock rate\n");
+ return PTR_ERR(clk);
+ }
+
+ rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
+ if (!rt->timer_freq)
+ return -EINVAL;
+
+ rt->dev = &pdev->dev;
+ platform_set_drvdata(pdev, rt);
+
+ rt_timer_request(rt);
+ rt_timer_config(rt, 2);
+ rt_timer_enable(rt);
+
+ dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
+
+ return 0;
+}
+
+static int rt_timer_remove(struct platform_device *pdev)
+{
+ struct rt_timer *rt = platform_get_drvdata(pdev);
+
+ rt_timer_disable(rt);
+ rt_timer_free(rt);
+
+ return 0;
+}
+
+static const struct of_device_id rt_timer_match[] = {
+ { .compatible = "ralink,rt2880-timer" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rt_timer_match);
+
+static struct platform_driver rt_timer_driver = {
+ .probe = rt_timer_probe,
+ .remove = rt_timer_remove,
+ .driver = {
+ .name = "rt-timer",
+ .owner = THIS_MODULE,
+ .of_match_table = rt_timer_match
+ },
+};
+
+module_platform_driver(rt_timer_driver);
+
+MODULE_DESCRIPTION("Ralink RT2880 timer");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
+MODULE_LICENSE("GPL");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 16/18] MIPS: ralink: add support for periodic timer irq
2013-04-10 11:47 ` [PATCH 16/18] MIPS: ralink: add support for periodic timer irq John Crispin
@ 2013-04-10 13:41 ` Lars-Peter Clausen
0 siblings, 0 replies; 26+ messages in thread
From: Lars-Peter Clausen @ 2013-04-10 13:41 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
On 04/10/2013 01:47 PM, John Crispin wrote:
> +
> +static int rt_timer_request(struct rt_timer *rt)
> +{
> + int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
IRQF_DISABLED is deprecated and a no-op these dats since all interrupts run
with IRQs disabled, it shouldn't be used in new code.
> + dev_name(rt->dev), rt);
> + if (err) {
> + dev_err(rt->dev, "failed to request irq\n");
> + } else {
> + u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
> + rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
> + }
> + return err;
> +}
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 17/18] MIPS: ralink: add cpu-feature-overrides.h
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (15 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 16/18] MIPS: ralink: add support for periodic timer irq John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 11:47 ` [PATCH 18/18] MIPS: ralink: add support for runtime memory detection John Crispin
17 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
From: Gabor Juhos <juhosg@openwrt.org>
Add cpu-feature-overrides.h for RT288x, RT305x and RT3883.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../asm/mach-ralink/rt288x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
.../asm/mach-ralink/rt305x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
.../asm/mach-ralink/rt3883/cpu-feature-overrides.h | 55 +++++++++++++++++++
arch/mips/ralink/Platform | 3 ++
4 files changed, 170 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
new file mode 100644
index 0000000..72fc106
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ * Ralink RT288x specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
+#define _RT288X_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 16
+#define cpu_icache_line_size() 16
+
+#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
new file mode 100644
index 0000000..917c286
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ * Ralink RT305x specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
+#define _RT305X_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 1
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+
+#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
new file mode 100644
index 0000000..181fbf4
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
@@ -0,0 +1,55 @@
+/*
+ * Ralink RT3662/RT3883 specific CPU feature overrides
+ *
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
+#define _RT3883_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 1
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+
+#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index b2cbf16..cda4b66 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -8,16 +8,19 @@ cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
# Ralink RT288x
#
load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
+cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
#
# Ralink RT305x
#
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
+cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
#
# Ralink RT3883
#
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
+cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
#
# Ralink MT7620
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 18/18] MIPS: ralink: add support for runtime memory detection
2013-04-10 11:47 [PATCH 00/18] MIPS: ralink: add several new Ralink SoC John Crispin
` (16 preceding siblings ...)
2013-04-10 11:47 ` [PATCH 17/18] MIPS: ralink: add cpu-feature-overrides.h John Crispin
@ 2013-04-10 11:47 ` John Crispin
2013-04-10 13:56 ` Jonas Gorski
17 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2013-04-10 11:47 UTC (permalink / raw)
To: Ralf Baechle; +Cc: Gabor Juhos, linux-mips, John Crispin
This allows us to add a device_node called "memorydetect" to the DT with
information about the memory windoe of the SoC. Based on this the memory is
detected ar runtime.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Makefile | 2 +-
arch/mips/ralink/common.h | 3 ++
arch/mips/ralink/memory.c | 119 +++++++++++++++++++++++++++++++++++++++++++++
arch/mips/ralink/of.c | 3 ++
4 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/ralink/memory.c
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index cae7d88..69101a1 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,7 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o memory.o
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 193c76c..48d3405 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -45,6 +45,9 @@ extern void prom_soc_init(struct ralink_soc_info *soc_info);
__iomem void *plat_of_remap_node(const char *node);
+int __init early_init_dt_detect_memory(unsigned long node, const char *uname,
+ int depth, void *data);
+
void ralink_pinmux(void);
#endif /* _RALINK_COMMON_H__ */
diff --git a/arch/mips/ralink/memory.c b/arch/mips/ralink/memory.c
new file mode 100644
index 0000000..57f3b83
--- /dev/null
+++ b/arch/mips/ralink/memory.c
@@ -0,0 +1,119 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include "common.h"
+
+#define MB (1024 * 1024)
+
+unsigned long ramips_mem_base;
+unsigned long ramips_mem_size_min;
+unsigned long ramips_mem_size_max;
+
+#ifdef CONFIG_SOC_RT305X
+
+#include <asm/mach-ralink/rt305x.h>
+
+static unsigned long rt5350_get_mem_size(void)
+{
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+ unsigned long ret;
+ u32 t;
+
+ t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
+ t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
+ RT5350_SYSCFG0_DRAM_SIZE_MASK;
+
+ switch (t) {
+ case RT5350_SYSCFG0_DRAM_SIZE_2M:
+ ret = 2 * 1024 * 1024;
+ break;
+ case RT5350_SYSCFG0_DRAM_SIZE_8M:
+ ret = 8 * 1024 * 1024;
+ break;
+ case RT5350_SYSCFG0_DRAM_SIZE_16M:
+ ret = 16 * 1024 * 1024;
+ break;
+ case RT5350_SYSCFG0_DRAM_SIZE_32M:
+ ret = 32 * 1024 * 1024;
+ break;
+ case RT5350_SYSCFG0_DRAM_SIZE_64M:
+ ret = 64 * 1024 * 1024;
+ break;
+ default:
+ panic("rt5350: invalid DRAM size: %u", t);
+ break;
+ }
+
+ return ret;
+}
+
+#endif
+
+static void __init detect_mem_size(void)
+{
+ unsigned long size;
+
+#ifdef CONFIG_SOC_RT305X
+ if (soc_is_rt5350()) {
+ size = rt5350_get_mem_size();
+ } else
+#endif
+ {
+ void *base;
+
+ base = (void *) KSEG1ADDR(detect_mem_size);
+ for (size = ramips_mem_size_min;
+ size < ramips_mem_size_max; size <<= 1) {
+ if (!memcmp(base, base + size, 1024))
+ break;
+ }
+ }
+
+ pr_info("memory detected: %uMB\n", (unsigned int) size / MB);
+
+ add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM);
+}
+
+int __init early_init_dt_detect_memory(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ unsigned long l;
+ __be32 *mem;
+
+ /* We are scanning "memorydetect" nodes only */
+ if (depth != 1 || strcmp(uname, "memorydetect") != 0)
+ return 0;
+
+ mem = of_get_flat_dt_prop(node, "ralink,memory", &l);
+ if (mem == NULL)
+ return 0;
+
+ if ((l / sizeof(__be32)) != 3)
+ panic("invalid memorydetect node\n");
+
+ ramips_mem_base = dt_mem_next_cell(dt_root_addr_cells, &mem);
+ ramips_mem_size_min = dt_mem_next_cell(dt_root_size_cells, &mem);
+ ramips_mem_size_max = dt_mem_next_cell(dt_root_size_cells, &mem);
+
+ pr_info("memory window: 0x%llx, min: %uMB, max: %uMB\n",
+ (unsigned long long) ramips_mem_base,
+ (unsigned int) ramips_mem_size_min / MB,
+ (unsigned int) ramips_mem_size_max / MB);
+
+ detect_mem_size();
+
+ return 0;
+}
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index ecf1482..90d66ac 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -85,6 +85,9 @@ void __init plat_mem_setup(void)
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__dtb_start);
+
+ /* try to load the mips machine name */
+ of_scan_flat_dt(early_init_dt_detect_memory, NULL);
}
static int __init plat_of_setup(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 18/18] MIPS: ralink: add support for runtime memory detection
2013-04-10 11:47 ` [PATCH 18/18] MIPS: ralink: add support for runtime memory detection John Crispin
@ 2013-04-10 13:56 ` Jonas Gorski
0 siblings, 0 replies; 26+ messages in thread
From: Jonas Gorski @ 2013-04-10 13:56 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, Gabor Juhos, linux-mips
On 10 April 2013 13:47, John Crispin <blogic@openwrt.org> wrote:
> This allows us to add a device_node called "memorydetect" to the DT with
> information about the memory windoe of the SoC. Based on this the memory is
> detected ar runtime.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/Makefile | 2 +-
> arch/mips/ralink/common.h | 3 ++
> arch/mips/ralink/memory.c | 119 +++++++++++++++++++++++++++++++++++++++++++++
> arch/mips/ralink/of.c | 3 ++
> 4 files changed, 126 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/ralink/memory.c
(snip)
> diff --git a/arch/mips/ralink/memory.c b/arch/mips/ralink/memory.c
> new file mode 100644
> index 0000000..57f3b83
> --- /dev/null
> +++ b/arch/mips/ralink/memory.c
> @@ -0,0 +1,119 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + *
> + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
> + */
> +
> +#include <linux/string.h>
> +#include <linux/of_fdt.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/bootinfo.h>
> +#include <asm/addrspace.h>
> +
> +#include "common.h"
> +
> +#define MB (1024 * 1024)
There's <linux/sizes.h>, which has macros like SZ_1M, SZ_2M, SZ_8M,
SZ_16M ... ;-)
> +
> +unsigned long ramips_mem_base;
> +unsigned long ramips_mem_size_min;
> +unsigned long ramips_mem_size_max;
> +
> +#ifdef CONFIG_SOC_RT305X
> +
> +#include <asm/mach-ralink/rt305x.h>
> +
> +static unsigned long rt5350_get_mem_size(void)
> +{
> + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
> + unsigned long ret;
> + u32 t;
> +
> + t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
> + t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
> + RT5350_SYSCFG0_DRAM_SIZE_MASK;
> +
> + switch (t) {
> + case RT5350_SYSCFG0_DRAM_SIZE_2M:
> + ret = 2 * 1024 * 1024;
> + break;
> + case RT5350_SYSCFG0_DRAM_SIZE_8M:
> + ret = 8 * 1024 * 1024;
> + break;
> + case RT5350_SYSCFG0_DRAM_SIZE_16M:
> + ret = 16 * 1024 * 1024;
> + break;
> + case RT5350_SYSCFG0_DRAM_SIZE_32M:
> + ret = 32 * 1024 * 1024;
> + break;
> + case RT5350_SYSCFG0_DRAM_SIZE_64M:
> + ret = 64 * 1024 * 1024;
> + break;
> + default:
> + panic("rt5350: invalid DRAM size: %u", t);
> + break;
> + }
> +
> + return ret;
> +}
> +
> +#endif
> +
> +static void __init detect_mem_size(void)
> +{
> + unsigned long size;
> +
> +#ifdef CONFIG_SOC_RT305X
> + if (soc_is_rt5350()) {
> + size = rt5350_get_mem_size();
> + } else
> +#endif
> + {
> + void *base;
> +
> + base = (void *) KSEG1ADDR(detect_mem_size);
> + for (size = ramips_mem_size_min;
> + size < ramips_mem_size_max; size <<= 1) {
> + if (!memcmp(base, base + size, 1024))
> + break;
> + }
> + }
> +
> + pr_info("memory detected: %uMB\n", (unsigned int) size / MB);
> +
> + add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM);
> +}
> +
> +int __init early_init_dt_detect_memory(unsigned long node, const char *uname,
> + int depth, void *data)
> +{
> + unsigned long l;
> + __be32 *mem;
> +
> + /* We are scanning "memorydetect" nodes only */
> + if (depth != 1 || strcmp(uname, "memorydetect") != 0)
> + return 0;
> +
> + mem = of_get_flat_dt_prop(node, "ralink,memory", &l);
> + if (mem == NULL)
> + return 0;
> +
> + if ((l / sizeof(__be32)) != 3)
> + panic("invalid memorydetect node\n");
> +
> + ramips_mem_base = dt_mem_next_cell(dt_root_addr_cells, &mem);
> + ramips_mem_size_min = dt_mem_next_cell(dt_root_size_cells, &mem);
> + ramips_mem_size_max = dt_mem_next_cell(dt_root_size_cells, &mem);
> +
> + pr_info("memory window: 0x%llx, min: %uMB, max: %uMB\n",
> + (unsigned long long) ramips_mem_base,
> + (unsigned int) ramips_mem_size_min / MB,
> + (unsigned int) ramips_mem_size_max / MB);
Is there a reason for those casts instead of just using the right
printk %-thingies?
> +
> + detect_mem_size();
> +
> + return 0;
> +}
Jonas
^ permalink raw reply [flat|nested] 26+ messages in thread