* [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
as CPU core and a enhanced flow controller for CPU power control. So
we need to skip some code that was for Contex-A9 and some other support
code that was for other Tegra SoC chips. Then adding the proper power up
and hot plug control for Tegra114.
Verified on Seaboard, Cardhu and Dalmore.
V2:
* Double confirmed the patch set is OK with THUMB2_KERNEL enabled.
Joseph Lo (6):
ARM: tegra: add an assembly marco to check Tegra SoC ID
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
ARM: tegra: make tegra_resume can work for Tegra114
ARM: tegra114: add power up sequence for warm boot CPU
clk: tegra114: implement wait_for_reset and disable_clock for
tegra_cpu_car_ops
ARM: tegra114: add CPU hotplug support
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/flowctrl.h | 1 +
arch/arm/mach-tegra/fuse.h | 22 ++++++++--------
arch/arm/mach-tegra/hotplug.c | 2 ++
arch/arm/mach-tegra/platsmp.c | 25 +++++++++++++++++-
arch/arm/mach-tegra/reset-handler.S | 51 +++++++++++++++++++++----------------
arch/arm/mach-tegra/sleep-tegra30.S | 30 ++++++++++++++++++----
arch/arm/mach-tegra/sleep.S | 8 +++---
arch/arm/mach-tegra/sleep.h | 35 ++++++++++++++++++++-----
drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++-
10 files changed, 150 insertions(+), 48 deletions(-)
--
1.8.2.2
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
as CPU core and a enhanced flow controller for CPU power control. So
we need to skip some code that was for Contex-A9 and some other support
code that was for other Tegra SoC chips. Then adding the proper power up
and hot plug control for Tegra114.
Verified on Seaboard, Cardhu and Dalmore.
V2:
* Double confirmed the patch set is OK with THUMB2_KERNEL enabled.
Joseph Lo (6):
ARM: tegra: add an assembly marco to check Tegra SoC ID
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
ARM: tegra: make tegra_resume can work for Tegra114
ARM: tegra114: add power up sequence for warm boot CPU
clk: tegra114: implement wait_for_reset and disable_clock for
tegra_cpu_car_ops
ARM: tegra114: add CPU hotplug support
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/flowctrl.h | 1 +
arch/arm/mach-tegra/fuse.h | 22 ++++++++--------
arch/arm/mach-tegra/hotplug.c | 2 ++
arch/arm/mach-tegra/platsmp.c | 25 +++++++++++++++++-
arch/arm/mach-tegra/reset-handler.S | 51 +++++++++++++++++++++----------------
arch/arm/mach-tegra/sleep-tegra30.S | 30 ++++++++++++++++++----
arch/arm/mach-tegra/sleep.S | 8 +++---
arch/arm/mach-tegra/sleep.h | 35 ++++++++++++++++++++-----
drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++-
10 files changed, 150 insertions(+), 48 deletions(-)
--
1.8.2.2
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 1/6] ARM: tegra: add an assembly marco to check Tegra SoC ID
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* refine the tegra_get_soc_id marco
---
arch/arm/mach-tegra/fuse.h | 22 ++++++++++++----------
arch/arm/mach-tegra/reset-handler.S | 25 +++++++++----------------
arch/arm/mach-tegra/sleep.h | 9 +++++++++
3 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d..def7968 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
#ifndef __MACH_TEGRA_FUSE_H
#define __MACH_TEGRA_FUSE_H
-enum tegra_revision {
- TEGRA_REVISION_UNKNOWN = 0,
- TEGRA_REVISION_A01,
- TEGRA_REVISION_A02,
- TEGRA_REVISION_A03,
- TEGRA_REVISION_A03p,
- TEGRA_REVISION_A04,
- TEGRA_REVISION_MAX,
-};
-
#define SKU_ID_T20 8
#define SKU_ID_T25SE 20
#define SKU_ID_AP25 23
@@ -40,6 +30,17 @@ enum tegra_revision {
#define TEGRA30 0x30
#define TEGRA114 0x35
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+ TEGRA_REVISION_UNKNOWN = 0,
+ TEGRA_REVISION_A01,
+ TEGRA_REVISION_A02,
+ TEGRA_REVISION_A03,
+ TEGRA_REVISION_A03p,
+ TEGRA_REVISION_A04,
+ TEGRA_REVISION_MAX,
+};
+
extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
#else
static inline void tegra114_init_speedo_data(void) {}
#endif
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a..40af405 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
#include <asm/hardware/cache-l2x0.h>
#include "flowctrl.h"
+#include "fuse.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"
-#define APB_MISC_GP_HIDREV 0x804
#define PMC_SCRATCH41 0x140
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
@@ -49,10 +49,8 @@ ENTRY(tegra_resume)
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
/* Are we on Tegra20? */
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r0, [r6, #APB_MISC_GP_HIDREV]
- and r0, r0, #0xff00
- cmp r0, #(0x20 << 8)
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+ cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
@@ -98,7 +96,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
* Register usage within the reset handler:
*
* Others: scratch
- * R6 = SoC ID << 8
+ * R6 = SoC ID
* R7 = CPU present (to the OS) mask
* R8 = CPU in LP1 state mask
* R9 = CPU in LP2 state mask
@@ -115,12 +113,10 @@ ENTRY(__tegra_cpu_reset_handler)
cpsid aif, 0x13 @ SVC mode, interrupts disabled
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r6, [r6, #APB_MISC_GP_HIDREV]
- and r6, r6, #0xff00
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
- cmp r6, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne after_t20_check
t20_errata:
# Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +132,7 @@ after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
- cmp r6, #(0x30 << 8)
+ cmp r6, #TEGRA30
bne after_t30_check
t30_errata:
# Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +159,7 @@ after_errata:
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
- cmp r6, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne 1f
/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
mov32 r5, TEGRA_PMC_BASE
@@ -210,10 +206,7 @@ __die:
mov32 r7, TEGRA_CLK_RESET_BASE
/* Are we on Tegra20? */
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r0, [r6, #APB_MISC_GP_HIDREV]
- and r0, r0, #0xff00
- cmp r0, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne 1f
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb1..f9f2164 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -85,6 +85,15 @@
dsb
.endm
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV 0x804
+.macro tegra_get_soc_id base, tmp1
+ mov32 \tmp1, \base
+ ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+ and \tmp1, \tmp1, #0xff00
+ mov \tmp1, \tmp1, lsr #8
+.endm
+
/* Macro to resume & re-enable L2 cache */
#ifndef L2X0_CTRL_EN
#define L2X0_CTRL_EN 1
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 1/6] ARM: tegra: add an assembly marco to check Tegra SoC ID
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
There are some Tegra SoC ID checking code around the low level assembly
code. Adding a marco to replace them. For the single image to support all
the Tegra series, we may also need the marco in other common code. So we
make it become a marco for the usage.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* refine the tegra_get_soc_id marco
---
arch/arm/mach-tegra/fuse.h | 22 ++++++++++++----------
arch/arm/mach-tegra/reset-handler.S | 25 +++++++++----------------
arch/arm/mach-tegra/sleep.h | 9 +++++++++
3 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d..def7968 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
#ifndef __MACH_TEGRA_FUSE_H
#define __MACH_TEGRA_FUSE_H
-enum tegra_revision {
- TEGRA_REVISION_UNKNOWN = 0,
- TEGRA_REVISION_A01,
- TEGRA_REVISION_A02,
- TEGRA_REVISION_A03,
- TEGRA_REVISION_A03p,
- TEGRA_REVISION_A04,
- TEGRA_REVISION_MAX,
-};
-
#define SKU_ID_T20 8
#define SKU_ID_T25SE 20
#define SKU_ID_AP25 23
@@ -40,6 +30,17 @@ enum tegra_revision {
#define TEGRA30 0x30
#define TEGRA114 0x35
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+ TEGRA_REVISION_UNKNOWN = 0,
+ TEGRA_REVISION_A01,
+ TEGRA_REVISION_A02,
+ TEGRA_REVISION_A03,
+ TEGRA_REVISION_A03p,
+ TEGRA_REVISION_A04,
+ TEGRA_REVISION_MAX,
+};
+
extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
#else
static inline void tegra114_init_speedo_data(void) {}
#endif
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a..40af405 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
#include <asm/hardware/cache-l2x0.h>
#include "flowctrl.h"
+#include "fuse.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"
-#define APB_MISC_GP_HIDREV 0x804
#define PMC_SCRATCH41 0x140
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
@@ -49,10 +49,8 @@ ENTRY(tegra_resume)
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
/* Are we on Tegra20? */
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r0, [r6, #APB_MISC_GP_HIDREV]
- and r0, r0, #0xff00
- cmp r0, #(0x20 << 8)
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+ cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
@@ -98,7 +96,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
* Register usage within the reset handler:
*
* Others: scratch
- * R6 = SoC ID << 8
+ * R6 = SoC ID
* R7 = CPU present (to the OS) mask
* R8 = CPU in LP1 state mask
* R9 = CPU in LP2 state mask
@@ -115,12 +113,10 @@ ENTRY(__tegra_cpu_reset_handler)
cpsid aif, 0x13 @ SVC mode, interrupts disabled
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r6, [r6, #APB_MISC_GP_HIDREV]
- and r6, r6, #0xff00
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
- cmp r6, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne after_t20_check
t20_errata:
# Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +132,7 @@ after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
- cmp r6, #(0x30 << 8)
+ cmp r6, #TEGRA30
bne after_t30_check
t30_errata:
# Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +159,7 @@ after_errata:
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
- cmp r6, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne 1f
/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
mov32 r5, TEGRA_PMC_BASE
@@ -210,10 +206,7 @@ __die:
mov32 r7, TEGRA_CLK_RESET_BASE
/* Are we on Tegra20? */
- mov32 r6, TEGRA_APB_MISC_BASE
- ldr r0, [r6, #APB_MISC_GP_HIDREV]
- and r0, r0, #0xff00
- cmp r0, #(0x20 << 8)
+ cmp r6, #TEGRA20
bne 1f
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb1..f9f2164 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -85,6 +85,15 @@
dsb
.endm
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV 0x804
+.macro tegra_get_soc_id base, tmp1
+ mov32 \tmp1, \base
+ ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+ and \tmp1, \tmp1, #0xff00
+ mov \tmp1, \tmp1, lsr #8
+.endm
+
/* Macro to resume & re-enable L2 cache */
#ifndef L2X0_CTRL_EN
#define L2X0_CTRL_EN 1
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change; but double confirmed the patch is OK with THUMB2_KERNEL
---
arch/arm/mach-tegra/sleep.S | 8 +++++---
arch/arm/mach-tegra/sleep.h | 24 ++++++++++++++++++------
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d845..9daaef2 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
isb
#ifdef CONFIG_CACHE_L2X0
/* Disable L2 cache */
- mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000
- mov r5, #0
- str r5, [r4, #L2X0_CTRL]
+ check_cpu_part_num 0xc09, r9, r10
+ movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+ movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+ moveq r5, #0
+ streq r5, [r4, #L2X0_CTRL]
#endif
mov pc, r0
ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index f9f2164..2269c0d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
movt \reg, #:upper16:\val
.endm
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+ mrc p15, 0, \tmp1, c0, c0, 0
+ ubfx \tmp1, \tmp1, #4, #12
+ mov32 \tmp2, \part_num
+ cmp \tmp1, \tmp2
+.endm
+
/* Macro to exit SMP coherency. */
.macro exit_smp, tmp1, tmp2
mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
isb
- cpu_id \tmp1
- mov \tmp1, \tmp1, lsl #2
- mov \tmp2, #0xf
- mov \tmp2, \tmp2, lsl \tmp1
- mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
- str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+ check_cpu_part_num 0xc09, \tmp1, \tmp2
+ mrceq p15, 0, \tmp1, c0, c0, 5
+ andeq \tmp1, \tmp1, #0xF
+ moveq \tmp1, \tmp1, lsl #2
+ moveq \tmp2, #0xf
+ moveq \tmp2, \tmp2, lsl \tmp1
+ ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+ streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
dsb
+#endif
.endm
/* Macro to check Tegra revision */
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* no change; but double confirmed the patch is OK with THUMB2_KERNEL
---
arch/arm/mach-tegra/sleep.S | 8 +++++---
arch/arm/mach-tegra/sleep.h | 24 ++++++++++++++++++------
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d845..9daaef2 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
isb
#ifdef CONFIG_CACHE_L2X0
/* Disable L2 cache */
- mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000
- mov r5, #0
- str r5, [r4, #L2X0_CTRL]
+ check_cpu_part_num 0xc09, r9, r10
+ movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+ movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+ moveq r5, #0
+ streq r5, [r4, #L2X0_CTRL]
#endif
mov pc, r0
ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index f9f2164..2269c0d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
movt \reg, #:upper16:\val
.endm
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+ mrc p15, 0, \tmp1, c0, c0, 0
+ ubfx \tmp1, \tmp1, #4, #12
+ mov32 \tmp2, \part_num
+ cmp \tmp1, \tmp2
+.endm
+
/* Macro to exit SMP coherency. */
.macro exit_smp, tmp1, tmp2
mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
isb
- cpu_id \tmp1
- mov \tmp1, \tmp1, lsl #2
- mov \tmp2, #0xf
- mov \tmp2, \tmp2, lsl \tmp1
- mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
- str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+ check_cpu_part_num 0xc09, \tmp1, \tmp2
+ mrceq p15, 0, \tmp1, c0, c0, 5
+ andeq \tmp1, \tmp1, #0xF
+ moveq \tmp1, \tmp1, lsl #2
+ moveq \tmp2, #0xf
+ moveq \tmp2, \tmp2, lsl \tmp1
+ ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+ streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
dsb
+#endif
.endm
/* Macro to check Tegra revision */
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
Tegra114 had a newer flow controller hardware that makes its behavior and
configurations are different with other Tegra series. We fix the common
resume function of tegra_resume to make it can work on Tegra114 by checking
SoC ID. And also checking CPU primary part number to isolate the support
code for Cortex A9 and A15.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* update the commit message
* update the comment message for the CSR flags
---
arch/arm/mach-tegra/reset-handler.S | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 40af405..424e01f 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -47,23 +47,27 @@ ENTRY(tegra_resume)
THUMB( it ne )
bne cpu_resume @ no
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
- mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
- ldr r1, [r2]
+ cpu_to_csr_req r1, r0
+ mov32 r2, TEGRA_FLOW_CTRL_BASE
+ ldr r1, [r2, r1]
/* Clear event & intr flag */
orr r1, r1, \
#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
- movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
+ movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
+ @ & ext flags for CPU power mgnt
bic r1, r1, r0
str r1, [r2]
1:
#endif
+ check_cpu_part_num 0xc09, r8, r9
+ bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */
mov32 r0, TEGRA_ARM_PERIF_BASE
@@ -74,6 +78,7 @@ ENTRY(tegra_resume)
/* L2 cache resume & re-enable */
l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
b cpu_resume
ENDPROC(tegra_resume)
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
Tegra114 had a newer flow controller hardware that makes its behavior and
configurations are different with other Tegra series. We fix the common
resume function of tegra_resume to make it can work on Tegra114 by checking
SoC ID. And also checking CPU primary part number to isolate the support
code for Cortex A9 and A15.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* update the commit message
* update the comment message for the CSR flags
---
arch/arm/mach-tegra/reset-handler.S | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 40af405..424e01f 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -47,23 +47,27 @@ ENTRY(tegra_resume)
THUMB( it ne )
bne cpu_resume @ no
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
- mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
- ldr r1, [r2]
+ cpu_to_csr_req r1, r0
+ mov32 r2, TEGRA_FLOW_CTRL_BASE
+ ldr r1, [r2, r1]
/* Clear event & intr flag */
orr r1, r1, \
#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
- movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
+ movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
+ @ & ext flags for CPU power mgnt
bic r1, r1, r0
str r1, [r2]
1:
#endif
+ check_cpu_part_num 0xc09, r8, r9
+ bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */
mov32 r0, TEGRA_ARM_PERIF_BASE
@@ -74,6 +78,7 @@ ENTRY(tegra_resume)
/* L2 cache resume & re-enable */
l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
b cpu_resume
ENDPROC(tegra_resume)
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 4/6] ARM: tegra114: add power up sequence for warm boot CPU
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
For Tegra114, once the CPUs were powered up by PMC in cold boot flow. The
flow controller will maintain the power state and control power sequence
for each CPU by setting event trigger (e.g. CPU hotplug ,idle and
suspend power down/up).
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* no change
---
arch/arm/mach-tegra/flowctrl.h | 1 +
arch/arm/mach-tegra/platsmp.c | 25 ++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56..7a29bae 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
#define FLOW_CTRL_WAITEVENT (2 << 29)
#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
#define FLOW_CTRL_JTAG_RESUME (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME (1 << 27)
#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
#define FLOW_CTRL_CPU0_CSR 0x8
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226..554aedc 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
+ int ret = 0;
+
cpu = cpu_logical_map(cpu);
- return tegra_pmc_cpu_power_on(cpu);
+
+ if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+ /*
+ * Warm boot flow
+ * The flow controller in charge of the power state and
+ * control for each CPU.
+ */
+ /* set SCLK as event trigger for flow controller */
+ flowctrl_write_cpu_csr(cpu, 1);
+ flowctrl_write_cpu_halt(cpu,
+ FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+ } else {
+ /*
+ * Cold boot flow
+ * The CPU is powered up by toggling PMC directly. It will
+ * also initial power state in flow controller. After that,
+ * the CPU's power state is maintained by flow controller.
+ */
+ ret = tegra_pmc_cpu_power_on(cpu);
+ }
+
+ return ret;
}
static int __cpuinit tegra_boot_secondary(unsigned int cpu,
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 4/6] ARM: tegra114: add power up sequence for warm boot CPU
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
For Tegra114, once the CPUs were powered up by PMC in cold boot flow. The
flow controller will maintain the power state and control power sequence
for each CPU by setting event trigger (e.g. CPU hotplug ,idle and
suspend power down/up).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* no change
---
arch/arm/mach-tegra/flowctrl.h | 1 +
arch/arm/mach-tegra/platsmp.c | 25 ++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56..7a29bae 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
#define FLOW_CTRL_WAITEVENT (2 << 29)
#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
#define FLOW_CTRL_JTAG_RESUME (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME (1 << 27)
#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
#define FLOW_CTRL_CPU0_CSR 0x8
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226..554aedc 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
+ int ret = 0;
+
cpu = cpu_logical_map(cpu);
- return tegra_pmc_cpu_power_on(cpu);
+
+ if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+ /*
+ * Warm boot flow
+ * The flow controller in charge of the power state and
+ * control for each CPU.
+ */
+ /* set SCLK as event trigger for flow controller */
+ flowctrl_write_cpu_csr(cpu, 1);
+ flowctrl_write_cpu_halt(cpu,
+ FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+ } else {
+ /*
+ * Cold boot flow
+ * The CPU is powered up by toggling PMC directly. It will
+ * also initial power state in flow controller. After that,
+ * the CPU's power state is maintained by flow controller.
+ */
+ ret = tegra_pmc_cpu_power_on(cpu);
+ }
+
+ return ret;
}
static int __cpuinit tegra_boot_secondary(unsigned int cpu,
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 5/6] clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Acked-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
V2:
* no change
---
drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..40d939d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
#define CLK_SOURCE_EMC 0x19c
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
}
}
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+ /* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+ .wait_for_reset = tegra114_wait_cpu_in_reset,
+ .disable_clock = tegra114_disable_cpu_clock,
+};
static const struct of_device_id pmc_match[] __initconst = {
{ .compatible = "nvidia,tegra114-pmc" },
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 5/6] clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
---
V2:
* no change
---
drivers/clk/tegra/clk-tegra114.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..40d939d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
#define CLK_SOURCE_EMC 0x19c
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
}
}
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+ /* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+ .wait_for_reset = tegra114_wait_cpu_in_reset,
+ .disable_clock = tegra114_disable_cpu_clock,
+};
static const struct of_device_id pmc_match[] __initconst = {
{ .compatible = "nvidia,tegra114-pmc" },
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 6/6] ARM: tegra114: add CPU hotplug support
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 10:39 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo
The Tegra114 is a quad cores SoC. Each core can be hotplugged including
CPU0. The hotplug sequence can be controlled by setting event trigger in
flow controller. Then the flow controller will take care all the power
sequence that include CPU up and down.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
V2:
* add init value (r3) in tegra30_cpu_shutdown
* update some comment message
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/hotplug.c | 2 ++
arch/arm/mach-tegra/reset-handler.S | 15 ++++++++++++---
arch/arm/mach-tegra/sleep-tegra30.S | 30 +++++++++++++++++++++++++-----
arch/arm/mach-tegra/sleep.h | 2 ++
5 files changed, 42 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0a..98b184e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a..d07f152 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -55,4 +55,6 @@ void __init tegra_hotplug_init(void)
tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+ if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+ tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
}
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 424e01f..d2042ac 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -38,18 +38,24 @@
* CPU boot vector when restarting the a CPU following
* an LP2 transition. Also branched to by LP0 and LP1 resume after
* re-enabling sdram.
+ *
+ * r6: SoC ID
*/
ENTRY(tegra_resume)
bl v7_invalidate_l1
cpu_id r0
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+ cmp r6, #TEGRA114
+ beq no_cpu0_chk
+
cmp r0, #0 @ CPU0?
THUMB( it ne )
bne cpu_resume @ no
+no_cpu0_chk:
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
- tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
@@ -187,11 +193,14 @@ __is_not_lp2:
#ifdef CONFIG_SMP
/*
- * Can only be secondary boot (initial or hotplug) but CPU 0
- * cannot be here.
+ * Can only be secondary boot (initial or hotplug)
+ * CPU0 can't be here for Tegra20/30
*/
+ cmp r6, #TEGRA114
+ beq __no_cpu0_chk
cmp r10, #0
bleq __die @ CPU0 cannot be here
+__no_cpu0_chk:
ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
cmp lr, #0
bleq __die @ no secondary startup handler
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcc..ada8821 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
+#include "fuse.h"
#include "sleep.h"
#include "flowctrl.h"
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
*
* Puts the current CPU in wait-for-event mode on the flow controller
* and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
*
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
*/
ENTRY(tegra30_cpu_shutdown)
cpu_id r3
+ tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+ cmp r10, #TEGRA30
+ bne _no_cpu0_chk @ It's not Tegra30
+
cmp r3, #0
moveq pc, lr @ Must never be called for CPU 0
+_no_cpu0_chk:
ldr r12, =TEGRA_FLOW_CTRL_VIRT
cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
movw r12, \
FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
FLOW_CTRL_CSR_ENABLE
- mov r4, #(1 << 4)
+ cmp r10, #TEGRA30
+ moveq r4, #(1 << 4) @ wfe bitmap
+ movne r4, #(1 << 8) @ wfi bitmap
ARM( orr r12, r12, r4, lsl r3 )
THUMB( lsl r4, r4, r3 )
THUMB( orr r12, r12, r4 )
@@ -79,9 +87,20 @@ delay_1:
cpsid a @ disable imprecise aborts.
ldr r3, [r1] @ read CSR
str r3, [r1] @ clear CSR
+
tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+ beq flow_ctrl_setting_for_lp2
+
+ /* flow controller set up for hotplug */
+ mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
+ b flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+ /* flow controller set up for LP2 */
+ cmp r10, #TEGRA30
moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
- movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
+ movne r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+ cmp r10, #TEGRA30
str r3, [r2]
ldr r0, [r2]
b wfe_war
@@ -89,7 +108,8 @@ delay_1:
__cpu_reset_again:
dsb
.align 5
- wfe @ CPU should be power gated here
+ wfeeq @ CPU should be power gated here
+ wfine
wfe_war:
b __cpu_reset_again
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2269c0d..98b7da6 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
+ IO_PPSB_VIRT)
#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+ IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+ + IO_APB_VIRT)
#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH V2 6/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-20 10:39 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-20 10:39 UTC (permalink / raw)
To: linux-arm-kernel
The Tegra114 is a quad cores SoC. Each core can be hotplugged including
CPU0. The hotplug sequence can be controlled by setting event trigger in
flow controller. Then the flow controller will take care all the power
sequence that include CPU up and down.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* add init value (r3) in tegra30_cpu_shutdown
* update some comment message
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/hotplug.c | 2 ++
arch/arm/mach-tegra/reset-handler.S | 15 ++++++++++++---
arch/arm/mach-tegra/sleep-tegra30.S | 30 +++++++++++++++++++++++++-----
arch/arm/mach-tegra/sleep.h | 2 ++
5 files changed, 42 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0a..98b184e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a..d07f152 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -55,4 +55,6 @@ void __init tegra_hotplug_init(void)
tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+ if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+ tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
}
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 424e01f..d2042ac 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -38,18 +38,24 @@
* CPU boot vector when restarting the a CPU following
* an LP2 transition. Also branched to by LP0 and LP1 resume after
* re-enabling sdram.
+ *
+ * r6: SoC ID
*/
ENTRY(tegra_resume)
bl v7_invalidate_l1
cpu_id r0
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+ cmp r6, #TEGRA114
+ beq no_cpu0_chk
+
cmp r0, #0 @ CPU0?
THUMB( it ne )
bne cpu_resume @ no
+no_cpu0_chk:
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
- tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
@@ -187,11 +193,14 @@ __is_not_lp2:
#ifdef CONFIG_SMP
/*
- * Can only be secondary boot (initial or hotplug) but CPU 0
- * cannot be here.
+ * Can only be secondary boot (initial or hotplug)
+ * CPU0 can't be here for Tegra20/30
*/
+ cmp r6, #TEGRA114
+ beq __no_cpu0_chk
cmp r10, #0
bleq __die @ CPU0 cannot be here
+__no_cpu0_chk:
ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
cmp lr, #0
bleq __die @ no secondary startup handler
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcc..ada8821 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
+#include "fuse.h"
#include "sleep.h"
#include "flowctrl.h"
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
*
* Puts the current CPU in wait-for-event mode on the flow controller
* and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
*
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
*/
ENTRY(tegra30_cpu_shutdown)
cpu_id r3
+ tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+ cmp r10, #TEGRA30
+ bne _no_cpu0_chk @ It's not Tegra30
+
cmp r3, #0
moveq pc, lr @ Must never be called for CPU 0
+_no_cpu0_chk:
ldr r12, =TEGRA_FLOW_CTRL_VIRT
cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
movw r12, \
FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
FLOW_CTRL_CSR_ENABLE
- mov r4, #(1 << 4)
+ cmp r10, #TEGRA30
+ moveq r4, #(1 << 4) @ wfe bitmap
+ movne r4, #(1 << 8) @ wfi bitmap
ARM( orr r12, r12, r4, lsl r3 )
THUMB( lsl r4, r4, r3 )
THUMB( orr r12, r12, r4 )
@@ -79,9 +87,20 @@ delay_1:
cpsid a @ disable imprecise aborts.
ldr r3, [r1] @ read CSR
str r3, [r1] @ clear CSR
+
tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+ beq flow_ctrl_setting_for_lp2
+
+ /* flow controller set up for hotplug */
+ mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
+ b flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+ /* flow controller set up for LP2 */
+ cmp r10, #TEGRA30
moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
- movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
+ movne r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+ cmp r10, #TEGRA30
str r3, [r2]
ldr r0, [r2]
b wfe_war
@@ -89,7 +108,8 @@ delay_1:
__cpu_reset_again:
dsb
.align 5
- wfe @ CPU should be power gated here
+ wfeeq @ CPU should be power gated here
+ wfine
wfe_war:
b __cpu_reset_again
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2269c0d..98b7da6 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
+ IO_PPSB_VIRT)
#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+ IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+ + IO_APB_VIRT)
#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
--
1.8.2.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-20 23:20 ` Stephen Warren
-1 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-20 23:20 UTC (permalink / raw)
To: Joseph Lo
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.
This version still doesn't enable hotplug of CPU0, yet at least patch
6/6 contains some changes that support enabling that. Are you planning
on sending a separate patch to enable this later, or was this an oversight?
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-20 23:20 ` Stephen Warren
0 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-20 23:20 UTC (permalink / raw)
To: linux-arm-kernel
On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.
This version still doesn't enable hotplug of CPU0, yet at least patch
6/6 contains some changes that support enabling that. Are you planning
on sending a separate patch to enable this later, or was this an oversight?
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
2013-05-20 23:20 ` Stephen Warren
@ 2013-05-21 9:58 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-21 9:58 UTC (permalink / raw)
To: Stephen Warren
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tue, 2013-05-21 at 07:20 +0800, Stephen Warren wrote:
> On 05/20/2013 04:39 AM, Joseph Lo wrote:
> > Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> > as CPU core and a enhanced flow controller for CPU power control. So
> > we need to skip some code that was for Contex-A9 and some other support
> > code that was for other Tegra SoC chips. Then adding the proper power up
> > and hot plug control for Tegra114.
>
> This version still doesn't enable hotplug of CPU0, yet at least patch
> 6/6 contains some changes that support enabling that. Are you planning
> on sending a separate patch to enable this later, or was this an oversight?
I will provide another patch to support it.
Joseph
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-21 9:58 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-05-21 9:58 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2013-05-21 at 07:20 +0800, Stephen Warren wrote:
> On 05/20/2013 04:39 AM, Joseph Lo wrote:
> > Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> > as CPU core and a enhanced flow controller for CPU power control. So
> > we need to skip some code that was for Contex-A9 and some other support
> > code that was for other Tegra SoC chips. Then adding the proper power up
> > and hot plug control for Tegra114.
>
> This version still doesn't enable hotplug of CPU0, yet at least patch
> 6/6 contains some changes that support enabling that. Are you planning
> on sending a separate patch to enable this later, or was this an oversight?
I will provide another patch to support it.
Joseph
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-22 21:21 ` Stephen Warren
-1 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-22 21:21 UTC (permalink / raw)
To: Joseph Lo
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.
I have applied the series to Tegra's for-3.11/soc branch.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support
@ 2013-05-22 21:21 ` Stephen Warren
0 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-22 21:21 UTC (permalink / raw)
To: linux-arm-kernel
On 05/20/2013 04:39 AM, Joseph Lo wrote:
> Tegra 114 is different with other Tegra SoC chips. It using ARM Cortex-A15
> as CPU core and a enhanced flow controller for CPU power control. So
> we need to skip some code that was for Contex-A9 and some other support
> code that was for other Tegra SoC chips. Then adding the proper power up
> and hot plug control for Tegra114.
I have applied the series to Tegra's for-3.11/soc branch.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
2013-05-20 10:39 ` Joseph Lo
@ 2013-05-31 22:41 ` Arnd Bergmann
-1 siblings, 0 replies; 28+ messages in thread
From: Arnd Bergmann @ 2013-05-31 22:41 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Joseph Lo, Stephen Warren, linux-tegra-u79uwXL29TY76Z2rM5mHXA
On Monday 20 May 2013, Joseph Lo wrote:
> + cpu_to_csr_req r1, r0
> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> + ldr r1, [r2, r1]
This causes build errors now, since cpu_to_csr_req is not defined anywhere.
Arnd
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
@ 2013-05-31 22:41 ` Arnd Bergmann
0 siblings, 0 replies; 28+ messages in thread
From: Arnd Bergmann @ 2013-05-31 22:41 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 20 May 2013, Joseph Lo wrote:
> + cpu_to_csr_req r1, r0
> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> + ldr r1, [r2, r1]
This causes build errors now, since cpu_to_csr_req is not defined anywhere.
Arnd
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
2013-05-31 22:41 ` Arnd Bergmann
@ 2013-05-31 23:46 ` Stephen Warren
-1 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-31 23:46 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Joseph Lo,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> On Monday 20 May 2013, Joseph Lo wrote:
>> + cpu_to_csr_req r1, r0
>> + mov32 r2, TEGRA_FLOW_CTRL_BASE
>> + ldr r1, [r2, r1]
>
> This causes build errors now, since cpu_to_csr_req is not defined anywhere.
What build error are you seeing? I built next-20130531 earlier today
without any issue.
I do remember making a similar comment during review of this patch that
cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
another patch in the series which had added it, or something like that.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
@ 2013-05-31 23:46 ` Stephen Warren
0 siblings, 0 replies; 28+ messages in thread
From: Stephen Warren @ 2013-05-31 23:46 UTC (permalink / raw)
To: linux-arm-kernel
On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> On Monday 20 May 2013, Joseph Lo wrote:
>> + cpu_to_csr_req r1, r0
>> + mov32 r2, TEGRA_FLOW_CTRL_BASE
>> + ldr r1, [r2, r1]
>
> This causes build errors now, since cpu_to_csr_req is not defined anywhere.
What build error are you seeing? I built next-20130531 earlier today
without any issue.
I do remember making a similar comment during review of this patch that
cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
another patch in the series which had added it, or something like that.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
2013-05-31 23:46 ` Stephen Warren
@ 2013-06-01 9:47 ` Arnd Bergmann
-1 siblings, 0 replies; 28+ messages in thread
From: Arnd Bergmann @ 2013-06-01 9:47 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Stephen Warren, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Joseph Lo
On Saturday 01 June 2013, Stephen Warren wrote:
> On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> > On Monday 20 May 2013, Joseph Lo wrote:
> >> + cpu_to_csr_req r1, r0
> >> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> >> + ldr r1, [r2, r1]
> >
> > This causes build errors now, since cpu_to_csr_req is not defined anywhere.
>
> What build error are you seeing? I built next-20130531 earlier today
> without any issue.
>
> I do remember making a similar comment during review of this patch that
> cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
> another patch in the series which had added it, or something like that.
Sorry, I should have mentioned it was using randconfig, all the defconfig
builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC",
but Tegra2 is normally enabled in defconfig, so it does not get built.
I suspect the #ifdef is wrong as well, and should have been "if tegra3
or tegra4" instead. Joseph, can you clarify the intent of this?
Arnd
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
@ 2013-06-01 9:47 ` Arnd Bergmann
0 siblings, 0 replies; 28+ messages in thread
From: Arnd Bergmann @ 2013-06-01 9:47 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 01 June 2013, Stephen Warren wrote:
> On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> > On Monday 20 May 2013, Joseph Lo wrote:
> >> + cpu_to_csr_req r1, r0
> >> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> >> + ldr r1, [r2, r1]
> >
> > This causes build errors now, since cpu_to_csr_req is not defined anywhere.
>
> What build error are you seeing? I built next-20130531 earlier today
> without any issue.
>
> I do remember making a similar comment during review of this patch that
> cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
> another patch in the series which had added it, or something like that.
Sorry, I should have mentioned it was using randconfig, all the defconfig
builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC",
but Tegra2 is normally enabled in defconfig, so it does not get built.
I suspect the #ifdef is wrong as well, and should have been "if tegra3
or tegra4" instead. Joseph, can you clarify the intent of this?
Arnd
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
2013-06-01 9:47 ` Arnd Bergmann
@ 2013-06-03 2:16 ` Joseph Lo
-1 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-06-03 2:16 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Stephen Warren, linux-tegra-u79uwXL29TY76Z2rM5mHXA
On Sat, 2013-06-01 at 17:47 +0800, Arnd Bergmann wrote:
> On Saturday 01 June 2013, Stephen Warren wrote:
> > On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> > > On Monday 20 May 2013, Joseph Lo wrote:
> > >> + cpu_to_csr_req r1, r0
> > >> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> > >> + ldr r1, [r2, r1]
> > >
> > > This causes build errors now, since cpu_to_csr_req is not defined anywhere.
> >
> > What build error are you seeing? I built next-20130531 earlier today
> > without any issue.
> >
> > I do remember making a similar comment during review of this patch that
> > cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
> > another patch in the series which had added it, or something like that.
>
> Sorry, I should have mentioned it was using randconfig, all the defconfig
> builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC",
> but Tegra2 is normally enabled in defconfig, so it does not get built.
>
> I suspect the #ifdef is wrong as well, and should have been "if tegra3
> or tegra4" instead. Joseph, can you clarify the intent of this?
>
> Arnd
Arnd,
I think the "ifdef" should be removed here because we had a runtime
Tegra SoC detection code here, the "ifdef" here would cause the code
won't be built for the tegra_defconfig that we are using. And a typo
need to fix here, it should be "cpu_to_csr_reg" not "cpu_to_csr_req".
Sorry.
Thanks for report. Will provide a fix.
Joseph
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114
@ 2013-06-03 2:16 ` Joseph Lo
0 siblings, 0 replies; 28+ messages in thread
From: Joseph Lo @ 2013-06-03 2:16 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 2013-06-01 at 17:47 +0800, Arnd Bergmann wrote:
> On Saturday 01 June 2013, Stephen Warren wrote:
> > On 05/31/2013 04:41 PM, Arnd Bergmann wrote:
> > > On Monday 20 May 2013, Joseph Lo wrote:
> > >> + cpu_to_csr_req r1, r0
> > >> + mov32 r2, TEGRA_FLOW_CTRL_BASE
> > >> + ldr r1, [r2, r1]
> > >
> > > This causes build errors now, since cpu_to_csr_req is not defined anywhere.
> >
> > What build error are you seeing? I built next-20130531 earlier today
> > without any issue.
> >
> > I do remember making a similar comment during review of this patch that
> > cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to
> > another patch in the series which had added it, or something like that.
>
> Sorry, I should have mentioned it was using randconfig, all the defconfig
> builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC",
> but Tegra2 is normally enabled in defconfig, so it does not get built.
>
> I suspect the #ifdef is wrong as well, and should have been "if tegra3
> or tegra4" instead. Joseph, can you clarify the intent of this?
>
> Arnd
Arnd,
I think the "ifdef" should be removed here because we had a runtime
Tegra SoC detection code here, the "ifdef" here would cause the code
won't be built for the tegra_defconfig that we are using. And a typo
need to fix here, it should be "cpu_to_csr_reg" not "cpu_to_csr_req".
Sorry.
Thanks for report. Will provide a fix.
Joseph
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2013-06-03 2:16 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-20 10:39 [PATCH V2 0/6] ARM: tegra114: add CPU hotplug support Joseph Lo
2013-05-20 10:39 ` Joseph Lo
[not found] ` <1369046369-12489-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-05-20 10:39 ` [PATCH V2 1/6] ARM: tegra: add an assembly marco to check Tegra SoC ID Joseph Lo
2013-05-20 10:39 ` Joseph Lo
2013-05-20 10:39 ` [PATCH V2 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 Joseph Lo
2013-05-20 10:39 ` Joseph Lo
2013-05-20 10:39 ` [PATCH V2 3/6] ARM: tegra: make tegra_resume can work for Tegra114 Joseph Lo
2013-05-20 10:39 ` Joseph Lo
[not found] ` <1369046369-12489-4-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-05-31 22:41 ` Arnd Bergmann
2013-05-31 22:41 ` Arnd Bergmann
[not found] ` <201306010041.07230.arnd-r2nGTMty4D4@public.gmane.org>
2013-05-31 23:46 ` Stephen Warren
2013-05-31 23:46 ` Stephen Warren
[not found] ` <51A9364B.4090002-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-06-01 9:47 ` Arnd Bergmann
2013-06-01 9:47 ` Arnd Bergmann
[not found] ` <201306011147.30379.arnd-r2nGTMty4D4@public.gmane.org>
2013-06-03 2:16 ` Joseph Lo
2013-06-03 2:16 ` Joseph Lo
2013-05-20 10:39 ` [PATCH V2 4/6] ARM: tegra114: add power up sequence for warm boot CPU Joseph Lo
2013-05-20 10:39 ` Joseph Lo
2013-05-20 10:39 ` [PATCH V2 5/6] clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops Joseph Lo
2013-05-20 10:39 ` Joseph Lo
2013-05-20 10:39 ` [PATCH V2 6/6] ARM: tegra114: add CPU hotplug support Joseph Lo
2013-05-20 10:39 ` Joseph Lo
2013-05-20 23:20 ` [PATCH V2 0/6] " Stephen Warren
2013-05-20 23:20 ` Stephen Warren
[not found] ` <519AAFCB.8060007-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-05-21 9:58 ` Joseph Lo
2013-05-21 9:58 ` Joseph Lo
2013-05-22 21:21 ` Stephen Warren
2013-05-22 21:21 ` Stephen Warren
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