* [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-21 14:07 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:07 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash Based function-mask and submask preoperties patch allocates and registers pins. Patch is fixes the issue reported and discussed here: http://www.spinics.net/lists/arm-kernel/msg235213.html Applies on top of 3.10-rc2 of linus's tree. Tested on da850-evm. Manjunathappa, Prakash (3): pinctrl: pinctrl-single: enhance to configure multiple pins of different modules pinctrl: pinctrl-single: pin names for pinctrl-single.bits ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- arch/arm/boot/dts/da850.dtsi | 2 +- drivers/pinctrl/pinctrl-single.c | 215 ++++++++++++++++---- 3 files changed, 179 insertions(+), 41 deletions(-) -- 1.7.4.1 ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-21 14:07 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:07 UTC (permalink / raw) To: linux-arm-kernel Based function-mask and submask preoperties patch allocates and registers pins. Patch is fixes the issue reported and discussed here: http://www.spinics.net/lists/arm-kernel/msg235213.html Applies on top of 3.10-rc2 of linus's tree. Tested on da850-evm. Manjunathappa, Prakash (3): pinctrl: pinctrl-single: enhance to configure multiple pins of different modules pinctrl: pinctrl-single: pin names for pinctrl-single.bits ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- arch/arm/boot/dts/da850.dtsi | 2 +- drivers/pinctrl/pinctrl-single.c | 215 ++++++++++++++++---- 3 files changed, 179 insertions(+), 41 deletions(-) -- 1.7.4.1 ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-21 14:07 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:07 UTC (permalink / raw) To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-doc-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, peter.ujfalusi-l0cyMroinI0, rob-VoJi6FS/r0vR7s880joybQ, grant.likely-QSEj5FYQhm4dnm+yROfE0A, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Based function-mask and submask preoperties patch allocates and registers pins. Patch is fixes the issue reported and discussed here: http://www.spinics.net/lists/arm-kernel/msg235213.html Applies on top of 3.10-rc2 of linus's tree. Tested on da850-evm. Manjunathappa, Prakash (3): pinctrl: pinctrl-single: enhance to configure multiple pins of different modules pinctrl: pinctrl-single: pin names for pinctrl-single.bits ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- arch/arm/boot/dts/da850.dtsi | 2 +- drivers/pinctrl/pinctrl-single.c | 215 ++++++++++++++++---- 3 files changed, 179 insertions(+), 41 deletions(-) -- 1.7.4.1 ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb68a21d5704839a192a46ebcf387773704), Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- drivers/pinctrl/pinctrl-single.c | 198 ++++++++++++++++---- 2 files changed, 167 insertions(+), 34 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 08f0c3d..5a02e30 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -18,7 +18,8 @@ Optional properties: pin functions is ignored - pinctrl-single,bit-per-mux : boolean to indicate that one register controls - more than one pin + more than one pin, for which "pinctrl-single,function-mask" property specifies + position mask of pin. - pinctrl-single,drive-strength : array of value that are used to configure drive strength in the pinmux register. They're value of drive strength diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b9fa046..9a1ea65 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -163,6 +163,7 @@ struct pcs_name { * @foff: value to turn mux off * @fmax: max number of functions in fmask * @is_pinconf: whether supports pinconf + * @bits_per_pin:number of bits per pin * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -190,6 +191,7 @@ struct pcs_device { unsigned fmax; bool bits_per_mux; bool is_pinconf; + unsigned bits_per_pin; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, vals = &func->vals[i]; val = pcs->read(vals->reg); - if (!vals->mask) - mask = pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; else - mask = pcs->fmask & vals->mask; + mask = pcs->fmask; val &= ~mask; val |= (vals->val & mask); @@ -779,7 +782,13 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) int mux_bytes, nr_pins, i; mux_bytes = pcs->width / BITS_PER_BYTE; - nr_pins = pcs->size / mux_bytes; + + if (pcs->bits_per_mux) { + pcs->bits_per_pin = fls(pcs->fmask); + nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + } else { + nr_pins = pcs->size / mux_bytes; + } dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); pcs->pins.pa = devm_kzalloc(pcs->dev, @@ -800,8 +809,14 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; + int byte_num; - offset = i * mux_bytes; + if (pcs->bits_per_mux) { + byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + } else { + offset = i * mux_bytes; + } res = pcs_add_pin(pcs, offset); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); @@ -919,7 +934,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return -EINVAL; } - index = offset / (pcs->width / BITS_PER_BYTE); + if (pcs->bits_per_mux) + index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; + else + index = offset / (pcs->width / BITS_PER_BYTE); return index; } @@ -1097,29 +1115,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - if (pcs->bits_per_mux) { - params = 3; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - } else { - params = 2; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - } - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * params)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if ((!mux) || (size < sizeof(*mux) * 2)) { + dev_err(pcs->dev, "bad data for mux %s\n", + np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / params; + rows = size / 2; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -1137,10 +1144,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; - if (params == 3) { - val = be32_to_cpup(mux + index++); - vals[found].mask = val; - } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1189,6 +1192,125 @@ free_vals: return res; } + +#define PARAMS_FOR_BITS_PER_MUX 3 + +static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps, + const char **pgnames) +{ + struct pcs_func_vals *vals; + const __be32 *mux; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int npins_in_row; + struct pcs_function *function; + + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", np->name); + return -EINVAL; + } + + if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); + return -EINVAL; + } + + /* Number of elements in array */ + size /= sizeof(*mux); + + rows = size / PARAMS_FOR_BITS_PER_MUX; + npins_in_row = pcs->width / pcs->bits_per_pin; + + vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, + GFP_KERNEL); + if (!vals) + return -ENOMEM; + + pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, + GFP_KERNEL); + if (!pins) + goto free_vals; + + while (index < size) { + unsigned offset, val; + unsigned mask, bit_pos, val_pos, mask_pos, submask; + unsigned pin_num_from_lsb; + int pin; + + offset = be32_to_cpup(mux + index++); + val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); + + /* Parse pins in each row from LSB */ + while (mask) { + bit_pos = ffs(mask); + pin_num_from_lsb = bit_pos / pcs->bits_per_pin; + mask_pos = ((pcs->fmask) << (bit_pos - 1)); + val_pos = val & mask_pos; + submask = mask & mask_pos; + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(pcs->dev, + "Invalid submask 0x%x for %s at 0x%x\n", + submask, np->name, offset); + continue; + } + + vals[found].mask = submask; + vals[found].reg = pcs->base + offset; + vals[found].val = val_pos; + + pin = pcs_get_pin_by_offset(pcs, offset); + if (pin < 0) { + dev_err(pcs->dev, + "could not add functions for %s %ux\n", + np->name, offset); + break; + } + pins[found++] = pin + pin_num_from_lsb; + } + } + + pgnames[0] = np->name; + function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); + if (!function) + goto free_pins; + + res = pcs_add_pingroup(pcs, np, np->name, pins, found); + if (res < 0) + goto free_function; + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + + if (pcs->is_pinconf) { + dev_err(pcs->dev, "pinconf not supported\n"); + goto free_pingroups; + } + + *num_maps = 1; + return 0; + +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; +free_function: + pcs_remove_function(pcs, function); + +free_pins: + devm_kfree(pcs->dev, pins); + +free_vals: + devm_kfree(pcs->dev, vals); + + return res; +} /** * pcs_dt_node_to_map() - allocates and parses pinctrl maps * @pctldev: pinctrl instance @@ -1219,12 +1341,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); - if (ret < 0) { - dev_err(pcs->dev, "no pins entries for %s\n", - np_config->name); - goto free_pgnames; + if (pcs->bits_per_mux) { + ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } + } else { + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } } return 0; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linux-arm-kernel Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb68a21d5704839a192a46ebcf387773704), Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- drivers/pinctrl/pinctrl-single.c | 198 ++++++++++++++++---- 2 files changed, 167 insertions(+), 34 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 08f0c3d..5a02e30 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -18,7 +18,8 @@ Optional properties: pin functions is ignored - pinctrl-single,bit-per-mux : boolean to indicate that one register controls - more than one pin + more than one pin, for which "pinctrl-single,function-mask" property specifies + position mask of pin. - pinctrl-single,drive-strength : array of value that are used to configure drive strength in the pinmux register. They're value of drive strength diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b9fa046..9a1ea65 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -163,6 +163,7 @@ struct pcs_name { * @foff: value to turn mux off * @fmax: max number of functions in fmask * @is_pinconf: whether supports pinconf + * @bits_per_pin:number of bits per pin * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -190,6 +191,7 @@ struct pcs_device { unsigned fmax; bool bits_per_mux; bool is_pinconf; + unsigned bits_per_pin; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, vals = &func->vals[i]; val = pcs->read(vals->reg); - if (!vals->mask) - mask = pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; else - mask = pcs->fmask & vals->mask; + mask = pcs->fmask; val &= ~mask; val |= (vals->val & mask); @@ -779,7 +782,13 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) int mux_bytes, nr_pins, i; mux_bytes = pcs->width / BITS_PER_BYTE; - nr_pins = pcs->size / mux_bytes; + + if (pcs->bits_per_mux) { + pcs->bits_per_pin = fls(pcs->fmask); + nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + } else { + nr_pins = pcs->size / mux_bytes; + } dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); pcs->pins.pa = devm_kzalloc(pcs->dev, @@ -800,8 +809,14 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; + int byte_num; - offset = i * mux_bytes; + if (pcs->bits_per_mux) { + byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + } else { + offset = i * mux_bytes; + } res = pcs_add_pin(pcs, offset); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); @@ -919,7 +934,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return -EINVAL; } - index = offset / (pcs->width / BITS_PER_BYTE); + if (pcs->bits_per_mux) + index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; + else + index = offset / (pcs->width / BITS_PER_BYTE); return index; } @@ -1097,29 +1115,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - if (pcs->bits_per_mux) { - params = 3; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - } else { - params = 2; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - } - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * params)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if ((!mux) || (size < sizeof(*mux) * 2)) { + dev_err(pcs->dev, "bad data for mux %s\n", + np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / params; + rows = size / 2; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -1137,10 +1144,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; - if (params == 3) { - val = be32_to_cpup(mux + index++); - vals[found].mask = val; - } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1189,6 +1192,125 @@ free_vals: return res; } + +#define PARAMS_FOR_BITS_PER_MUX 3 + +static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps, + const char **pgnames) +{ + struct pcs_func_vals *vals; + const __be32 *mux; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int npins_in_row; + struct pcs_function *function; + + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", np->name); + return -EINVAL; + } + + if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); + return -EINVAL; + } + + /* Number of elements in array */ + size /= sizeof(*mux); + + rows = size / PARAMS_FOR_BITS_PER_MUX; + npins_in_row = pcs->width / pcs->bits_per_pin; + + vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, + GFP_KERNEL); + if (!vals) + return -ENOMEM; + + pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, + GFP_KERNEL); + if (!pins) + goto free_vals; + + while (index < size) { + unsigned offset, val; + unsigned mask, bit_pos, val_pos, mask_pos, submask; + unsigned pin_num_from_lsb; + int pin; + + offset = be32_to_cpup(mux + index++); + val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); + + /* Parse pins in each row from LSB */ + while (mask) { + bit_pos = ffs(mask); + pin_num_from_lsb = bit_pos / pcs->bits_per_pin; + mask_pos = ((pcs->fmask) << (bit_pos - 1)); + val_pos = val & mask_pos; + submask = mask & mask_pos; + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(pcs->dev, + "Invalid submask 0x%x for %s at 0x%x\n", + submask, np->name, offset); + continue; + } + + vals[found].mask = submask; + vals[found].reg = pcs->base + offset; + vals[found].val = val_pos; + + pin = pcs_get_pin_by_offset(pcs, offset); + if (pin < 0) { + dev_err(pcs->dev, + "could not add functions for %s %ux\n", + np->name, offset); + break; + } + pins[found++] = pin + pin_num_from_lsb; + } + } + + pgnames[0] = np->name; + function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); + if (!function) + goto free_pins; + + res = pcs_add_pingroup(pcs, np, np->name, pins, found); + if (res < 0) + goto free_function; + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + + if (pcs->is_pinconf) { + dev_err(pcs->dev, "pinconf not supported\n"); + goto free_pingroups; + } + + *num_maps = 1; + return 0; + +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; +free_function: + pcs_remove_function(pcs, function); + +free_pins: + devm_kfree(pcs->dev, pins); + +free_vals: + devm_kfree(pcs->dev, vals); + + return res; +} /** * pcs_dt_node_to_map() - allocates and parses pinctrl maps * @pctldev: pinctrl instance @@ -1219,12 +1341,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); - if (ret < 0) { - dev_err(pcs->dev, "no pins entries for %s\n", - np_config->name); - goto free_pgnames; + if (pcs->bits_per_mux) { + ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } + } else { + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } } return 0; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-doc-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, peter.ujfalusi-l0cyMroinI0, rob-VoJi6FS/r0vR7s880joybQ, grant.likely-QSEj5FYQhm4dnm+yROfE0A, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb68a21d5704839a192a46ebcf387773704), Signed-off-by: Manjunathappa, Prakash <prakash.pm-l0cyMroinI0@public.gmane.org> Reported-by: Lad, Prabhakar <prabhakar.csengg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Tested-by: Lad, Prabhakar <prabhakar.csengg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 3 +- drivers/pinctrl/pinctrl-single.c | 198 ++++++++++++++++---- 2 files changed, 167 insertions(+), 34 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 08f0c3d..5a02e30 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -18,7 +18,8 @@ Optional properties: pin functions is ignored - pinctrl-single,bit-per-mux : boolean to indicate that one register controls - more than one pin + more than one pin, for which "pinctrl-single,function-mask" property specifies + position mask of pin. - pinctrl-single,drive-strength : array of value that are used to configure drive strength in the pinmux register. They're value of drive strength diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b9fa046..9a1ea65 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -163,6 +163,7 @@ struct pcs_name { * @foff: value to turn mux off * @fmax: max number of functions in fmask * @is_pinconf: whether supports pinconf + * @bits_per_pin:number of bits per pin * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -190,6 +191,7 @@ struct pcs_device { unsigned fmax; bool bits_per_mux; bool is_pinconf; + unsigned bits_per_pin; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, vals = &func->vals[i]; val = pcs->read(vals->reg); - if (!vals->mask) - mask = pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; else - mask = pcs->fmask & vals->mask; + mask = pcs->fmask; val &= ~mask; val |= (vals->val & mask); @@ -779,7 +782,13 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) int mux_bytes, nr_pins, i; mux_bytes = pcs->width / BITS_PER_BYTE; - nr_pins = pcs->size / mux_bytes; + + if (pcs->bits_per_mux) { + pcs->bits_per_pin = fls(pcs->fmask); + nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + } else { + nr_pins = pcs->size / mux_bytes; + } dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); pcs->pins.pa = devm_kzalloc(pcs->dev, @@ -800,8 +809,14 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; + int byte_num; - offset = i * mux_bytes; + if (pcs->bits_per_mux) { + byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + } else { + offset = i * mux_bytes; + } res = pcs_add_pin(pcs, offset); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); @@ -919,7 +934,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return -EINVAL; } - index = offset / (pcs->width / BITS_PER_BYTE); + if (pcs->bits_per_mux) + index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; + else + index = offset / (pcs->width / BITS_PER_BYTE); return index; } @@ -1097,29 +1115,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - if (pcs->bits_per_mux) { - params = 3; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - } else { - params = 2; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - } - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * params)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if ((!mux) || (size < sizeof(*mux) * 2)) { + dev_err(pcs->dev, "bad data for mux %s\n", + np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / params; + rows = size / 2; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -1137,10 +1144,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; - if (params == 3) { - val = be32_to_cpup(mux + index++); - vals[found].mask = val; - } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1189,6 +1192,125 @@ free_vals: return res; } + +#define PARAMS_FOR_BITS_PER_MUX 3 + +static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps, + const char **pgnames) +{ + struct pcs_func_vals *vals; + const __be32 *mux; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int npins_in_row; + struct pcs_function *function; + + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", np->name); + return -EINVAL; + } + + if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); + return -EINVAL; + } + + /* Number of elements in array */ + size /= sizeof(*mux); + + rows = size / PARAMS_FOR_BITS_PER_MUX; + npins_in_row = pcs->width / pcs->bits_per_pin; + + vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, + GFP_KERNEL); + if (!vals) + return -ENOMEM; + + pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, + GFP_KERNEL); + if (!pins) + goto free_vals; + + while (index < size) { + unsigned offset, val; + unsigned mask, bit_pos, val_pos, mask_pos, submask; + unsigned pin_num_from_lsb; + int pin; + + offset = be32_to_cpup(mux + index++); + val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); + + /* Parse pins in each row from LSB */ + while (mask) { + bit_pos = ffs(mask); + pin_num_from_lsb = bit_pos / pcs->bits_per_pin; + mask_pos = ((pcs->fmask) << (bit_pos - 1)); + val_pos = val & mask_pos; + submask = mask & mask_pos; + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(pcs->dev, + "Invalid submask 0x%x for %s at 0x%x\n", + submask, np->name, offset); + continue; + } + + vals[found].mask = submask; + vals[found].reg = pcs->base + offset; + vals[found].val = val_pos; + + pin = pcs_get_pin_by_offset(pcs, offset); + if (pin < 0) { + dev_err(pcs->dev, + "could not add functions for %s %ux\n", + np->name, offset); + break; + } + pins[found++] = pin + pin_num_from_lsb; + } + } + + pgnames[0] = np->name; + function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); + if (!function) + goto free_pins; + + res = pcs_add_pingroup(pcs, np, np->name, pins, found); + if (res < 0) + goto free_function; + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + + if (pcs->is_pinconf) { + dev_err(pcs->dev, "pinconf not supported\n"); + goto free_pingroups; + } + + *num_maps = 1; + return 0; + +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; +free_function: + pcs_remove_function(pcs, function); + +free_pins: + devm_kfree(pcs->dev, pins); + +free_vals: + devm_kfree(pcs->dev, vals); + + return res; +} /** * pcs_dt_node_to_map() - allocates and parses pinctrl maps * @pctldev: pinctrl instance @@ -1219,12 +1341,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); - if (ret < 0) { - dev_err(pcs->dev, "no pins entries for %s\n", - np_config->name); - goto free_pgnames; + if (pcs->bits_per_mux) { + ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } + } else { + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } } return 0; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules 2013-05-21 14:08 ` Manjunathappa, Prakash (?) @ 2013-06-05 5:24 ` Haojian Zhuang -1 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:24 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Walleij Linus, davinci-linux-open-source, Linux Russell, linux-doc, devicetree-discuss, Sekhar Nori, linux-kernel, Rob Herring, peter.ujfalusi, grant.likely, linux-arm-kernel On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Excuse me for response late. Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-06-05 5:24 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:24 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Excuse me for response late. Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-06-05 5:24 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:24 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Walleij Linus, davinci-linux-open-source, Linux Russell, linux-doc, devicetree-discuss, Sekhar Nori, linux-kernel, Rob Herring, peter.ujfalusi, grant.likely, linux-arm-kernel On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Excuse me for response late. Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules 2013-05-21 14:08 ` Manjunathappa, Prakash @ 2013-06-05 22:01 ` Tony Lindgren -1 siblings, 0 replies; 41+ messages in thread From: Tony Lindgren @ 2013-06-05 22:01 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: linus.walleij, nsekhar, grant.likely, rob.herring, linux, rob, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source * Manjunathappa, Prakash <prakash.pm@ti.com> [130521 07:13]: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. Thanks for fixing this! Looks good to me, and things keep working for me just fine with these applied: Acked-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-06-05 22:01 ` Tony Lindgren 0 siblings, 0 replies; 41+ messages in thread From: Tony Lindgren @ 2013-06-05 22:01 UTC (permalink / raw) To: linux-arm-kernel * Manjunathappa, Prakash <prakash.pm@ti.com> [130521 07:13]: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. Thanks for fixing this! Looks good to me, and things keep working for me just fine with these applied: Acked-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules 2013-05-21 14:08 ` Manjunathappa, Prakash (?) @ 2013-06-07 9:20 ` Linus Walleij -1 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 9:20 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, ext Tony Lindgren, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Patch applied with Haojian's and Tony's ACK. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-06-07 9:20 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 9:20 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Patch applied with Haojian's and Tony's ACK. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/3] pinctrl: pinctrl-single: enhance to configure multiple pins of different modules @ 2013-06-07 9:20 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 9:20 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, ext Tony Lindgren, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Add support to configure multiple pins in each register, existing > implementation added by [1] does not support full fledge multiple pin > configuration in single register, reports a pin clash when different > modules configure different bits of same register. The issue reported > and discussed here > http://www.spinics.net/lists/arm-kernel/msg235213.html > > With pinctrl-single,bits-per-mux property specified, use function-mask > property to find out number pins to configure. Allocate and register > pin control functions based sub mask. > > Tested on da850/omap-l138 EVM. > does not support variable submask for pins. > does not support pinconf. > > [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" > (9e605cb68a21d5704839a192a46ebcf387773704), > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Patch applied with Haojian's and Tony's ACK. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits 2013-05-21 14:07 ` Manjunathappa, Prakash (?) @ 2013-05-21 14:08 ` Manjunathappa, Prakash -1 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- drivers/pinctrl/pinctrl-single.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 9a1ea65..2899c86 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,7 +30,7 @@ #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" #define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) +#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -744,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = { * @pcs: pcs driver instance * @offset: register offset from base */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) +static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, + unsigned pin_pos) { struct pinctrl_pin_desc *pin; struct pcs_name *pn; @@ -759,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx", - (unsigned long)pcs->res->start + offset); + sprintf(pn->name, "%lx.%d", + (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -780,12 +781,14 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; + int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; if (pcs->bits_per_mux) { pcs->bits_per_pin = fls(pcs->fmask); nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + num_pins_in_register = pcs->width / pcs->bits_per_pin; } else { nr_pins = pcs->size / mux_bytes; } @@ -810,14 +813,16 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) unsigned offset; int res; int byte_num; + int pin_pos = 0; if (pcs->bits_per_mux) { byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = i % num_pins_in_register; } else { offset = i * mux_bytes; } - res = pcs_add_pin(pcs, offset); + res = pcs_add_pin(pcs, offset, pin_pos); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linux-arm-kernel Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- drivers/pinctrl/pinctrl-single.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 9a1ea65..2899c86 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,7 +30,7 @@ #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" #define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) +#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -744,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = { * @pcs: pcs driver instance * @offset: register offset from base */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) +static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, + unsigned pin_pos) { struct pinctrl_pin_desc *pin; struct pcs_name *pn; @@ -759,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx", - (unsigned long)pcs->res->start + offset); + sprintf(pn->name, "%lx.%d", + (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -780,12 +781,14 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; + int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; if (pcs->bits_per_mux) { pcs->bits_per_pin = fls(pcs->fmask); nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + num_pins_in_register = pcs->width / pcs->bits_per_pin; } else { nr_pins = pcs->size / mux_bytes; } @@ -810,14 +813,16 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) unsigned offset; int res; int byte_num; + int pin_pos = 0; if (pcs->bits_per_mux) { byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = i % num_pins_in_register; } else { offset = i * mux_bytes; } - res = pcs_add_pin(pcs, offset); + res = pcs_add_pin(pcs, offset, pin_pos); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- drivers/pinctrl/pinctrl-single.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 9a1ea65..2899c86 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,7 +30,7 @@ #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" #define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) +#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -744,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = { * @pcs: pcs driver instance * @offset: register offset from base */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) +static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, + unsigned pin_pos) { struct pinctrl_pin_desc *pin; struct pcs_name *pn; @@ -759,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx", - (unsigned long)pcs->res->start + offset); + sprintf(pn->name, "%lx.%d", + (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -780,12 +781,14 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; + int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; if (pcs->bits_per_mux) { pcs->bits_per_pin = fls(pcs->fmask); nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + num_pins_in_register = pcs->width / pcs->bits_per_pin; } else { nr_pins = pcs->size / mux_bytes; } @@ -810,14 +813,16 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) unsigned offset; int res; int byte_num; + int pin_pos = 0; if (pcs->bits_per_mux) { byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = i % num_pins_in_register; } else { offset = i * mux_bytes; } - res = pcs_add_pin(pcs, offset); + res = pcs_add_pin(pcs, offset, pin_pos); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits 2013-05-21 14:08 ` Manjunathappa, Prakash (?) @ 2013-06-05 5:25 ` Haojian Zhuang -1 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:25 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Walleij Linus, Sekhar Nori, grant.likely, Rob Herring, Linux Russell, Rob Landley, Tony Lindgren, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > --- Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-05 5:25 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:25 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > --- Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-05 5:25 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-06-05 5:25 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Walleij Linus, Sekhar Nori, grant.likely, Rob Herring, Linux Russell, Rob Landley, Tony Lindgren, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > --- Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits 2013-06-05 5:25 ` Haojian Zhuang (?) @ 2013-06-05 22:02 ` Tony Lindgren -1 siblings, 0 replies; 41+ messages in thread From: Tony Lindgren @ 2013-06-05 22:02 UTC (permalink / raw) To: Haojian Zhuang Cc: Manjunathappa, Prakash, Walleij Linus, Sekhar Nori, grant.likely, Rob Herring, Linux Russell, Rob Landley, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source * Haojian Zhuang <haojian.zhuang@gmail.com> [130604 22:31]: > On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash > <prakash.pm@ti.com> wrote: > > Take care to name pin names as > > register-offset.bit-pos-of-pin-in-register in case configuring multiple > > pins in register. > > > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > > --- > > Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-05 22:02 ` Tony Lindgren 0 siblings, 0 replies; 41+ messages in thread From: Tony Lindgren @ 2013-06-05 22:02 UTC (permalink / raw) To: linux-arm-kernel * Haojian Zhuang <haojian.zhuang@gmail.com> [130604 22:31]: > On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash > <prakash.pm@ti.com> wrote: > > Take care to name pin names as > > register-offset.bit-pos-of-pin-in-register in case configuring multiple > > pins in register. > > > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > > --- > > Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-05 22:02 ` Tony Lindgren 0 siblings, 0 replies; 41+ messages in thread From: Tony Lindgren @ 2013-06-05 22:02 UTC (permalink / raw) To: Haojian Zhuang Cc: Manjunathappa, Prakash, Walleij Linus, Sekhar Nori, grant.likely, Rob Herring, Linux Russell, Rob Landley, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source * Haojian Zhuang <haojian.zhuang@gmail.com> [130604 22:31]: > On Tue, May 21, 2013 at 10:08 PM, Manjunathappa, Prakash > <prakash.pm@ti.com> wrote: > > Take care to name pin names as > > register-offset.bit-pos-of-pin-in-register in case configuring multiple > > pins in register. > > > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > > --- > > Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits 2013-05-21 14:08 ` Manjunathappa, Prakash (?) @ 2013-06-07 11:14 ` Linus Walleij -1 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 11:14 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, ext Tony Lindgren, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Applied with Haojian and Tony's ACKs. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-07 11:14 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 11:14 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Applied with Haojian and Tony's ACKs. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits @ 2013-06-07 11:14 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-06-07 11:14 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, ext Tony Lindgren, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 4:08 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Take care to name pin names as > register-offset.bit-pos-of-pin-in-register in case configuring multiple > pins in register. > > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Applied with Haojian and Tony's ACKs. Thanks! Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins 2013-05-21 14:07 ` Manjunathappa, Prakash (?) @ 2013-05-21 14:08 ` Manjunathappa, Prakash -1 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash function-mask property is a mask for a pin at each pin configure offset in a pincontrol register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- arch/arm/boot/dts/da850.dtsi | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 4d43046..9bec36c 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -37,7 +37,7 @@ #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,function-mask = <0xf>; status = "disabled"; nand_cs3_pins: pinmux_nand_pins { -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linux-arm-kernel function-mask property is a mask for a pin at each pin configure offset in a pincontrol register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- arch/arm/boot/dts/da850.dtsi | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 4d43046..9bec36c 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -37,7 +37,7 @@ #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,function-mask = <0xf>; status = "disabled"; nand_cs3_pins: pinmux_nand_pins { -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-05-21 14:08 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-05-21 14:08 UTC (permalink / raw) To: linus.walleij Cc: nsekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, peter.ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source, Manjunathappa, Prakash function-mask property is a mask for a pin at each pin configure offset in a pincontrol register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- arch/arm/boot/dts/da850.dtsi | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 4d43046..9bec36c 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -37,7 +37,7 @@ #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,function-mask = <0xf>; status = "disabled"; nand_cs3_pins: pinmux_nand_pins { -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 41+ messages in thread
* RE: [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 11:48 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-06-24 11:48 UTC (permalink / raw) To: linus.walleij, Nori, Sekhar Cc: Nori, Sekhar, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, Ujfalusi, Peter, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source Hi Sekhar, On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: > function-mask property is a mask for a pin at each pin configure offset > in a pincontrol register. > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or pincontrol tree. Could you please takecare of this? Thanks, Prakash > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > --- > arch/arm/boot/dts/da850.dtsi | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi > index 4d43046..9bec36c 100644 > --- a/arch/arm/boot/dts/da850.dtsi > +++ b/arch/arm/boot/dts/da850.dtsi > @@ -37,7 +37,7 @@ > #size-cells = <0>; > pinctrl-single,bit-per-mux; > pinctrl-single,register-width = <32>; > - pinctrl-single,function-mask = <0xffffffff>; > + pinctrl-single,function-mask = <0xf>; > status = "disabled"; > > nand_cs3_pins: pinmux_nand_pins { > -- > 1.7.4.1 > > ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 11:48 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-06-24 11:48 UTC (permalink / raw) To: linux-arm-kernel Hi Sekhar, On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: > function-mask property is a mask for a pin at each pin configure offset > in a pincontrol register. > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or pincontrol tree. Could you please takecare of this? Thanks, Prakash > Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> > --- > arch/arm/boot/dts/da850.dtsi | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi > index 4d43046..9bec36c 100644 > --- a/arch/arm/boot/dts/da850.dtsi > +++ b/arch/arm/boot/dts/da850.dtsi > @@ -37,7 +37,7 @@ > #size-cells = <0>; > pinctrl-single,bit-per-mux; > pinctrl-single,register-width = <32>; > - pinctrl-single,function-mask = <0xffffffff>; > + pinctrl-single,function-mask = <0xf>; > status = "disabled"; > > nand_cs3_pins: pinmux_nand_pins { > -- > 1.7.4.1 > > ^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 11:48 ` Manjunathappa, Prakash 0 siblings, 0 replies; 41+ messages in thread From: Manjunathappa, Prakash @ 2013-06-24 11:48 UTC (permalink / raw) To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Nori, Sekhar Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-doc-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, Ujfalusi, Peter, rob-VoJi6FS/r0vR7s880joybQ, grant.likely-QSEj5FYQhm4dnm+yROfE0A, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Sekhar, On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: > function-mask property is a mask for a pin at each pin configure offset > in a pincontrol register. > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or pincontrol tree. Could you please takecare of this? Thanks, Prakash > Signed-off-by: Manjunathappa, Prakash <prakash.pm-l0cyMroinI0@public.gmane.org> > --- > arch/arm/boot/dts/da850.dtsi | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi > index 4d43046..9bec36c 100644 > --- a/arch/arm/boot/dts/da850.dtsi > +++ b/arch/arm/boot/dts/da850.dtsi > @@ -37,7 +37,7 @@ > #size-cells = <0>; > pinctrl-single,bit-per-mux; > pinctrl-single,register-width = <32>; > - pinctrl-single,function-mask = <0xffffffff>; > + pinctrl-single,function-mask = <0xf>; > status = "disabled"; > > nand_cs3_pins: pinmux_nand_pins { > -- > 1.7.4.1 > > ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 14:52 ` Sekhar Nori 0 siblings, 0 replies; 41+ messages in thread From: Sekhar Nori @ 2013-06-24 14:52 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: linus.walleij, grant.likely, rob.herring, linux, rob, tony, prabhakar.csengg, Ujfalusi, Peter, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On 6/24/2013 5:18 PM, Manjunathappa, Prakash wrote: > Hi Sekhar, > > On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: >> function-mask property is a mask for a pin at each pin configure offset >> in a pincontrol register. >> > > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or > pincontrol tree. Could you please takecare of this? I will send this via DaVinci tree. I had actually missed that there is a bit waiting for me here. So thanks for asking. Regards, Sekhar ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 14:52 ` Sekhar Nori 0 siblings, 0 replies; 41+ messages in thread From: Sekhar Nori @ 2013-06-24 14:52 UTC (permalink / raw) To: linux-arm-kernel On 6/24/2013 5:18 PM, Manjunathappa, Prakash wrote: > Hi Sekhar, > > On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: >> function-mask property is a mask for a pin at each pin configure offset >> in a pincontrol register. >> > > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or > pincontrol tree. Could you please takecare of this? I will send this via DaVinci tree. I had actually missed that there is a bit waiting for me here. So thanks for asking. Regards, Sekhar ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins @ 2013-06-24 14:52 ` Sekhar Nori 0 siblings, 0 replies; 41+ messages in thread From: Sekhar Nori @ 2013-06-24 14:52 UTC (permalink / raw) To: Manjunathappa, Prakash Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-doc-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, linux-kernel-u79uwXL29TY76Z2rM5mHXA, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, Ujfalusi, Peter, rob-VoJi6FS/r0vR7s880joybQ, grant.likely-QSEj5FYQhm4dnm+yROfE0A, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 6/24/2013 5:18 PM, Manjunathappa, Prakash wrote: > Hi Sekhar, > > On Tue, May 21, 2013 at 19:38:02, Manjunathappa, Prakash wrote: >> function-mask property is a mask for a pin at each pin configure offset >> in a pincontrol register. >> > > Got 1/3 and 2/3 accepted, I do not know if this gets merged via DaVinci tree or > pincontrol tree. Could you please takecare of this? I will send this via DaVinci tree. I had actually missed that there is a bit waiting for me here. So thanks for asking. Regards, Sekhar ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-24 9:03 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-05-24 9:03 UTC (permalink / raw) To: Manjunathappa, Prakash, Haojian Zhuang, ext Tony Lindgren Cc: Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Based function-mask and submask preoperties patch allocates and registers pins. > Patch is fixes the issue reported and discussed here: > http://www.spinics.net/lists/arm-kernel/msg235213.html I'd like Tony to ACK this, and Haojian to have a look at it before applying. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-24 9:03 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-05-24 9:03 UTC (permalink / raw) To: linux-arm-kernel On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash <prakash.pm@ti.com> wrote: > Based function-mask and submask preoperties patch allocates and registers pins. > Patch is fixes the issue reported and discussed here: > http://www.spinics.net/lists/arm-kernel/msg235213.html I'd like Tony to ACK this, and Haojian to have a look at it before applying. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-24 9:03 ` Linus Walleij 0 siblings, 0 replies; 41+ messages in thread From: Linus Walleij @ 2013-05-24 9:03 UTC (permalink / raw) To: Manjunathappa, Prakash, Haojian Zhuang, ext Tony Lindgren Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, Russell King - ARM Linux, linux-doc-u79uwXL29TY76Z2rM5mHXA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Nori, Sekhar, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Peter Ujfalusi, Grant Likely, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash <prakash.pm-l0cyMroinI0@public.gmane.org> wrote: > Based function-mask and submask preoperties patch allocates and registers pins. > Patch is fixes the issue reported and discussed here: > http://www.spinics.net/lists/arm-kernel/msg235213.html I'd like Tony to ACK this, and Haojian to have a look at it before applying. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-26 16:11 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-05-26 16:11 UTC (permalink / raw) To: Linus Walleij Cc: Manjunathappa, Prakash, ext Tony Lindgren, Nori, Sekhar, Grant Likely, Rob Herring, Russell King - ARM Linux, Rob Landley, Prabhakar Lad, Peter Ujfalusi, devicetree-discuss, linux-doc, linux-arm-kernel, linux-kernel, davinci-linux-open-source On 24 May 2013 17:03, Linus Walleij <linus.walleij@linaro.org> wrote: > On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash > <prakash.pm@ti.com> wrote: > >> Based function-mask and submask preoperties patch allocates and registers pins. >> Patch is fixes the issue reported and discussed here: >> http://www.spinics.net/lists/arm-kernel/msg235213.html > > I'd like Tony to ACK this, and Haojian to have a look at it before applying. > > Yours, > Linus Walleij I'll give feedback in the next week. Regards Haojian ^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-26 16:11 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-05-26 16:11 UTC (permalink / raw) To: linux-arm-kernel On 24 May 2013 17:03, Linus Walleij <linus.walleij@linaro.org> wrote: > On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash > <prakash.pm@ti.com> wrote: > >> Based function-mask and submask preoperties patch allocates and registers pins. >> Patch is fixes the issue reported and discussed here: >> http://www.spinics.net/lists/arm-kernel/msg235213.html > > I'd like Tony to ACK this, and Haojian to have a look at it before applying. > > Yours, > Linus Walleij I'll give feedback in the next week. Regards Haojian ^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules @ 2013-05-26 16:11 ` Haojian Zhuang 0 siblings, 0 replies; 41+ messages in thread From: Haojian Zhuang @ 2013-05-26 16:11 UTC (permalink / raw) To: Linus Walleij Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, Russell King - ARM Linux, linux-doc-u79uwXL29TY76Z2rM5mHXA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Nori, Sekhar, Rob Herring, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Peter Ujfalusi, Manjunathappa, Prakash, Grant Likely, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 24 May 2013 17:03, Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > On Tue, May 21, 2013 at 4:07 PM, Manjunathappa, Prakash > <prakash.pm-l0cyMroinI0@public.gmane.org> wrote: > >> Based function-mask and submask preoperties patch allocates and registers pins. >> Patch is fixes the issue reported and discussed here: >> http://www.spinics.net/lists/arm-kernel/msg235213.html > > I'd like Tony to ACK this, and Haojian to have a look at it before applying. > > Yours, > Linus Walleij I'll give feedback in the next week. Regards Haojian ^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2013-06-24 14:53 UTC | newest] Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-05-21 14:07 [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules Manjunathappa, Prakash 2013-05-21 14:07 ` Manjunathappa, Prakash 2013-05-21 14:07 ` Manjunathappa, Prakash 2013-05-21 14:08 ` [PATCH 1/3] pinctrl: pinctrl-single: enhance " Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-06-05 5:24 ` Haojian Zhuang 2013-06-05 5:24 ` Haojian Zhuang 2013-06-05 5:24 ` Haojian Zhuang 2013-06-05 22:01 ` Tony Lindgren 2013-06-05 22:01 ` Tony Lindgren 2013-06-07 9:20 ` Linus Walleij 2013-06-07 9:20 ` Linus Walleij 2013-06-07 9:20 ` Linus Walleij 2013-05-21 14:08 ` [PATCH 2/3] pinctrl: pinctrl-single: pin names for pinctrl-single.bits Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-06-05 5:25 ` Haojian Zhuang 2013-06-05 5:25 ` Haojian Zhuang 2013-06-05 5:25 ` Haojian Zhuang 2013-06-05 22:02 ` Tony Lindgren 2013-06-05 22:02 ` Tony Lindgren 2013-06-05 22:02 ` Tony Lindgren 2013-06-07 11:14 ` Linus Walleij 2013-06-07 11:14 ` Linus Walleij 2013-06-07 11:14 ` Linus Walleij 2013-05-21 14:08 ` [PATCH 3/3] ARM: davinci: da850: adopt to pinctrl-single driver to configure multiple pins Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-05-21 14:08 ` Manjunathappa, Prakash 2013-06-24 11:48 ` Manjunathappa, Prakash 2013-06-24 11:48 ` Manjunathappa, Prakash 2013-06-24 11:48 ` Manjunathappa, Prakash 2013-06-24 14:52 ` Sekhar Nori 2013-06-24 14:52 ` Sekhar Nori 2013-06-24 14:52 ` Sekhar Nori 2013-05-24 9:03 ` [PATCH 0/3] pinctrl: pinctrl-single: Add full fledge support to configure multiple pins of different modules Linus Walleij 2013-05-24 9:03 ` Linus Walleij 2013-05-24 9:03 ` Linus Walleij 2013-05-26 16:11 ` Haojian Zhuang 2013-05-26 16:11 ` Haojian Zhuang 2013-05-26 16:11 ` Haojian Zhuang
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