* [PATCH 0/6] U300 device tree clocks
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mike Turquette
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The following patch set converts all the U300 clocks to be probed
from the device tree. We first move the syscon memory range to the
device tree, then we group the clocks under it.
This goes on top of the previous device tree and multiplatform
series for the U300.
Linus Walleij (6):
ARM: u300: add syscon node
ARM: u300: remove register definition file
clk: move the U300 fixed and fixed-factor to DT
i2c: stu300: do not request a specific clock name
ARM: u300: move the gated system controller clocks to DT
ARM: u300: convert MMC/SD clock to device tree
Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +-
.../bindings/clock/ste-u300-syscon-clock.txt | 80 +++++
arch/arm/boot/dts/ste-u300.dts | 204 +++++++++++
arch/arm/mach-u300/core.c | 135 +++++++-
arch/arm/mach-u300/regulator.c | 21 +-
arch/arm/mach-u300/timer.c | 2 +-
arch/arm/mach-u300/u300-regs.h | 165 ---------
drivers/clk/clk-u300.c | 375 +++++++++++++--------
drivers/i2c/busses/i2c-stu300.c | 4 +-
9 files changed, 702 insertions(+), 314 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
delete mode 100644 arch/arm/mach-u300/u300-regs.h
--
1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/6] U300 device tree clocks
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
The following patch set converts all the U300 clocks to be probed
from the device tree. We first move the syscon memory range to the
device tree, then we group the clocks under it.
This goes on top of the previous device tree and multiplatform
series for the U300.
Linus Walleij (6):
ARM: u300: add syscon node
ARM: u300: remove register definition file
clk: move the U300 fixed and fixed-factor to DT
i2c: stu300: do not request a specific clock name
ARM: u300: move the gated system controller clocks to DT
ARM: u300: convert MMC/SD clock to device tree
Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +-
.../bindings/clock/ste-u300-syscon-clock.txt | 80 +++++
arch/arm/boot/dts/ste-u300.dts | 204 +++++++++++
arch/arm/mach-u300/core.c | 135 +++++++-
arch/arm/mach-u300/regulator.c | 21 +-
arch/arm/mach-u300/timer.c | 2 +-
arch/arm/mach-u300/u300-regs.h | 165 ---------
drivers/clk/clk-u300.c | 375 +++++++++++++--------
drivers/i2c/busses/i2c-stu300.c | 4 +-
9 files changed, 702 insertions(+), 314 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
delete mode 100644 arch/arm/mach-u300/u300-regs.h
--
1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/6] ARM: u300: add syscon node
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mike Turquette
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
This adds a device tree node for the U300 system controller
and remaps this dynamically instead of using hard-coded
virtual addresses. The board power set-up code is altered
to fetch a reference to the syscon using ampersand <&syscon>
notation. This way of passing a pointer to the syscon will
also be used by the clocks.
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +++++++++++++++++++---
arch/arm/boot/dts/ste-u300.dts | 6 +++++
arch/arm/mach-u300/core.c | 22 +++++++++++++---
arch/arm/mach-u300/regulator.c | 21 ++++++++++++---
4 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index cd9001a..69b5ab0 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -8,15 +8,39 @@ Required root node property:
compatible="stericsson,u300";
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+ board.
+- syscon: a pointer to the syscon node so we can acccess the
+ syscon registers to set the board as self-powered.
Example:
-s365 {
- compatible = "stericsson,s365";
- vana15-supply = <&ab3100_ldo_d_reg>;
+/ {
+ model = "ST-Ericsson U300";
+ compatible = "stericsson,u300";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ s365 {
+ compatible = "stericsson,s365";
+ vana15-supply = <&ab3100_ldo_d_reg>;
+ syscon = <&syscon>;
+ };
+
+ syscon: syscon@c0011000 {
+ compatible = "stericsson,u300-syscon";
+ reg = <0xc0011000 0x1000>;
+ };
};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 35a2d58..0530095 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -27,6 +27,12 @@
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
+ syscon = <&syscon>;
+ };
+
+ syscon: syscon@c0011000 {
+ compatible = "stericsson,u300-syscon";
+ reg = <0xc0011000 0x1000>;
};
timer: timer@c0014000 {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 9caf5ea..bde6540 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -18,6 +18,7 @@
#include <linux/platform_data/pinctrl-coh901.h>
#include <linux/platform_data/dma-coh901318.h>
#include <linux/irqchip.h>
+#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
@@ -52,6 +53,8 @@
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
+static void __iomem *syscon_base;
+
/*
* Static I/O mappings that are needed for booting the U300 platforms. The
* only things we need are the areas where we find the timer, syscon and
@@ -205,7 +208,7 @@ static void __init u300_init_check_chip(void)
const char unknown[] = "UNKNOWN";
/* Read out and print chip ID */
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+ val = readw(syscon_base + U300_SYSCON_CIDR);
/* This is in funky bigendian order... */
val = (val & 0xFFU) << 8 | (val >> 8);
chip = db_chips;
@@ -294,10 +297,21 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
static void __init u300_init_irq_dt(void)
{
+ struct device_node *syscon;
struct clk *clk;
+ syscon = of_find_node_by_path("/syscon@c0011000");
+ if (!syscon) {
+ pr_crit("could not find syscon node\n");
+ return;
+ }
+ syscon_base = of_iomap(syscon, 0);
+ if (!syscon_base) {
+ pr_crit("could not remap syscon\n");
+ return;
+ }
/* initialize clocking early, we want to clock the INTCON */
- u300_clk_init(U300_SYSCON_VBASE);
+ u300_clk_init(syscon_base);
/* Bootstrap EMIF and SEMI clocks */
clk = clk_get_sys("pl172", NULL);
@@ -330,9 +344,9 @@ static void __init u300_init_machine_dt(void)
u300_auxdata_lookup, NULL);
/* Enable SEMI self refresh */
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+ val = readw(syscon_base + U300_SYSCON_SMCR) |
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
- writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+ writew(val, syscon_base + U300_SYSCON_SMCR);
}
static const char * u300_board_compat[] = {
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 1cbe88c..273fceb 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -16,8 +16,8 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */
+#include <linux/of_address.h>
#include <linux/io.h>
-#include "u300-regs.h"
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
@@ -57,10 +57,25 @@ void u300_pm_poweroff(void)
*/
static int __init __u300_init_boardpower(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ static void __iomem *syscon_base;
int err;
u32 val;
pr_info("U300: setting up board power\n");
+
+ syscon_np = of_parse_phandle(np, "syscon", 0);
+ if (!syscon_np) {
+ pr_crit("U300: no syscon node\n");
+ return -ENODEV;
+ }
+ syscon_base = of_iomap(syscon_np, 0);
+ if (!syscon_base) {
+ pr_crit("U300: could not remap syscon\n");
+ return -ENODEV;
+ }
+
main_power_15 = regulator_get(&pdev->dev, "vana15");
if (IS_ERR(main_power_15)) {
@@ -81,9 +96,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
* the rest of the U300 power management is implemented.
*/
pr_info("U300: disable system controller pull-up\n");
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+ val = readw(syscon_base + U300_SYSCON_PMCR);
val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
- writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+ writew(val, syscon_base + U300_SYSCON_PMCR);
/* Register globally exported PM poweroff hook */
pm_power_off = u300_pm_poweroff;
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 1/6] ARM: u300: add syscon node
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This adds a device tree node for the U300 system controller
and remaps this dynamically instead of using hard-coded
virtual addresses. The board power set-up code is altered
to fetch a reference to the syscon using ampersand <&syscon>
notation. This way of passing a pointer to the syscon will
also be used by the clocks.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/arm/ste-u300.txt | 30 +++++++++++++++++++---
arch/arm/boot/dts/ste-u300.dts | 6 +++++
arch/arm/mach-u300/core.c | 22 +++++++++++++---
arch/arm/mach-u300/regulator.c | 21 ++++++++++++---
4 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index cd9001a..69b5ab0 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -8,15 +8,39 @@ Required root node property:
compatible="stericsson,u300";
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+ board.
+- syscon: a pointer to the syscon node so we can acccess the
+ syscon registers to set the board as self-powered.
Example:
-s365 {
- compatible = "stericsson,s365";
- vana15-supply = <&ab3100_ldo_d_reg>;
+/ {
+ model = "ST-Ericsson U300";
+ compatible = "stericsson,u300";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ s365 {
+ compatible = "stericsson,s365";
+ vana15-supply = <&ab3100_ldo_d_reg>;
+ syscon = <&syscon>;
+ };
+
+ syscon: syscon at c0011000 {
+ compatible = "stericsson,u300-syscon";
+ reg = <0xc0011000 0x1000>;
+ };
};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 35a2d58..0530095 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -27,6 +27,12 @@
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
+ syscon = <&syscon>;
+ };
+
+ syscon: syscon at c0011000 {
+ compatible = "stericsson,u300-syscon";
+ reg = <0xc0011000 0x1000>;
};
timer: timer at c0014000 {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 9caf5ea..bde6540 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -18,6 +18,7 @@
#include <linux/platform_data/pinctrl-coh901.h>
#include <linux/platform_data/dma-coh901318.h>
#include <linux/irqchip.h>
+#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
@@ -52,6 +53,8 @@
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
+static void __iomem *syscon_base;
+
/*
* Static I/O mappings that are needed for booting the U300 platforms. The
* only things we need are the areas where we find the timer, syscon and
@@ -205,7 +208,7 @@ static void __init u300_init_check_chip(void)
const char unknown[] = "UNKNOWN";
/* Read out and print chip ID */
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+ val = readw(syscon_base + U300_SYSCON_CIDR);
/* This is in funky bigendian order... */
val = (val & 0xFFU) << 8 | (val >> 8);
chip = db_chips;
@@ -294,10 +297,21 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
static void __init u300_init_irq_dt(void)
{
+ struct device_node *syscon;
struct clk *clk;
+ syscon = of_find_node_by_path("/syscon at c0011000");
+ if (!syscon) {
+ pr_crit("could not find syscon node\n");
+ return;
+ }
+ syscon_base = of_iomap(syscon, 0);
+ if (!syscon_base) {
+ pr_crit("could not remap syscon\n");
+ return;
+ }
/* initialize clocking early, we want to clock the INTCON */
- u300_clk_init(U300_SYSCON_VBASE);
+ u300_clk_init(syscon_base);
/* Bootstrap EMIF and SEMI clocks */
clk = clk_get_sys("pl172", NULL);
@@ -330,9 +344,9 @@ static void __init u300_init_machine_dt(void)
u300_auxdata_lookup, NULL);
/* Enable SEMI self refresh */
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+ val = readw(syscon_base + U300_SYSCON_SMCR) |
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
- writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+ writew(val, syscon_base + U300_SYSCON_SMCR);
}
static const char * u300_board_compat[] = {
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 1cbe88c..273fceb 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -16,8 +16,8 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */
+#include <linux/of_address.h>
#include <linux/io.h>
-#include "u300-regs.h"
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
@@ -57,10 +57,25 @@ void u300_pm_poweroff(void)
*/
static int __init __u300_init_boardpower(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ static void __iomem *syscon_base;
int err;
u32 val;
pr_info("U300: setting up board power\n");
+
+ syscon_np = of_parse_phandle(np, "syscon", 0);
+ if (!syscon_np) {
+ pr_crit("U300: no syscon node\n");
+ return -ENODEV;
+ }
+ syscon_base = of_iomap(syscon_np, 0);
+ if (!syscon_base) {
+ pr_crit("U300: could not remap syscon\n");
+ return -ENODEV;
+ }
+
main_power_15 = regulator_get(&pdev->dev, "vana15");
if (IS_ERR(main_power_15)) {
@@ -81,9 +96,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
* the rest of the U300 power management is implemented.
*/
pr_info("U300: disable system controller pull-up\n");
- val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+ val = readw(syscon_base + U300_SYSCON_PMCR);
val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
- writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+ writew(val, syscon_base + U300_SYSCON_PMCR);
/* Register globally exported PM poweroff hook */
pm_power_off = u300_pm_poweroff;
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/6] ARM: u300: remove register definition file
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, Mike Turquette
Cc: devicetree-discuss, Linus Walleij, Arnd Bergmann
From: Linus Walleij <linus.walleij@linaro.org>
Now that the core file is the only one actually using any
of the base addresses, we can delete that header and move
the base address definitions into the one and only core
file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/core.c | 113 +++++++++++++++++++++++++++-
arch/arm/mach-u300/u300-regs.h | 165 -----------------------------------------
2 files changed, 112 insertions(+), 166 deletions(-)
delete mode 100644 arch/arm/mach-u300/u300-regs.h
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index bde6540..4db0b76 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,7 +26,118 @@
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
-#include "u300-regs.h"
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE 0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE 0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE (1 << 16)
+#define PLAT_NAND_ALE (1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE 0xa0000000
+#define U300_AHB_PER_VIRT_BASE 0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE 0xc0000000
+#define U300_FAST_PER_VIRT_BASE 0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE 0xc0010000
+#define U300_SLOW_PER_VIRT_BASE 0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE 0xffff0000
+#define U300_BOOTROM_VIRT_BASE 0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE 0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE (0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE (0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE (0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE (0xd0000000)
/*
* SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
deleted file mode 100644
index 0320495..0000000
--- a/arch/arm/mach-u300/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE 0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE 0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE (1 << 16)
-#define PLAT_NAND_ALE (1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE 0xa0000000
-#define U300_AHB_PER_VIRT_BASE 0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE 0xc0000000
-#define U300_FAST_PER_VIRT_BASE 0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE 0xc0010000
-#define U300_SLOW_PER_VIRT_BASE 0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE 0xffff0000
-#define U300_BOOTROM_VIRT_BASE 0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE 0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE (0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE (0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE (0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE (0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE (0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE (0xd0000000)
-
-#endif
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/6] ARM: u300: remove register definition file
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
Now that the core file is the only one actually using any
of the base addresses, we can delete that header and move
the base address definitions into the one and only core
file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/core.c | 113 +++++++++++++++++++++++++++-
arch/arm/mach-u300/u300-regs.h | 165 -----------------------------------------
2 files changed, 112 insertions(+), 166 deletions(-)
delete mode 100644 arch/arm/mach-u300/u300-regs.h
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index bde6540..4db0b76 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,7 +26,118 @@
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
-#include "u300-regs.h"
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE 0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE 0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE (1 << 16)
+#define PLAT_NAND_ALE (1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE 0xa0000000
+#define U300_AHB_PER_VIRT_BASE 0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE 0xc0000000
+#define U300_FAST_PER_VIRT_BASE 0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE 0xc0010000
+#define U300_SLOW_PER_VIRT_BASE 0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE 0xffff0000
+#define U300_BOOTROM_VIRT_BASE 0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE 0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE (0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE (0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE (0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE (0xd0000000)
/*
* SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
deleted file mode 100644
index 0320495..0000000
--- a/arch/arm/mach-u300/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE 0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE 0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE (1 << 16)
-#define PLAT_NAND_ALE (1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE 0xa0000000
-#define U300_AHB_PER_VIRT_BASE 0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE 0xc0000000
-#define U300_FAST_PER_VIRT_BASE 0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE 0xc0010000
-#define U300_SLOW_PER_VIRT_BASE 0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE 0xffff0000
-#define U300_BOOTROM_VIRT_BASE 0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE 0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE (0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE (0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE (0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE (0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE (0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE (0xd0000000)
-
-#endif
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mike Turquette
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
This converts the fixed and fixed-factor clocks in the U300
platform to register themselves from the device tree.
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Hi Mike, seeking an ACK on this to take the series through
ARM SoC.
---
arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/clk-u300.c | 33 +++++++++++++------------------
2 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 0530095..c51a8c7 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -33,6 +33,49 @@
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
+ clk32: app_32_clk@32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+ pll13: pll13@13M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+ pll208: pll208@208M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <208000000>;
+ };
+ app208: app_208_clk@208M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app104: app_104_clk@104M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app52: app_52_clk@52M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app26: app_26_clk@26M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&app52>;
+ };
};
timer: timer@c0014000 {
@@ -65,6 +108,7 @@
reg = <0xc0012000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <3>;
+ clocks = <&clk32>;
};
rtc: rtc@c0017000 {
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a41e42e..bebd6c9 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
+#include <linux/of.h>
/* APP side SYSCON registers */
/* CLK Control Register 16bit (R/W) */
@@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
return clk;
}
+static const __initconst struct of_device_id u300_clk_match[] = {
+ {
+ .compatible = "fixed-clock",
+ .data = of_fixed_clk_setup,
+ },
+ {
+ .compatible = "fixed-factor-clock",
+ .data = of_fixed_factor_clk_setup,
+ },
+};
+
void __init u300_clk_init(void __iomem *base)
{
u16 val;
@@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
writew(val, syscon_vbase + U300_SYSCON_PMCR);
- /* These are always available (RTC and PLL13) */
- clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
- CLK_IS_ROOT, 32768);
- /* The watchdog sits directly on the 32 kHz clock */
- clk_register_clkdev(clk, NULL, "coh901327_wdog");
- clk = clk_register_fixed_rate(NULL, "pll13", NULL,
- CLK_IS_ROOT, 13000000);
-
- /* These derive from PLL208 */
- clk = clk_register_fixed_rate(NULL, "pll208", NULL,
- CLK_IS_ROOT, 208000000);
- clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
- 0, 1, 1);
- clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
- 0, 1, 2);
- clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
- 0, 1, 4);
- /* The 52 MHz is divided down to 26 MHz */
- clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
- 0, 1, 2);
+ of_clk_init(u300_clk_match);
/* Directly on the AMBA interconnect */
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This converts the fixed and fixed-factor clocks in the U300
platform to register themselves from the device tree.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Mike, seeking an ACK on this to take the series through
ARM SoC.
---
arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/clk-u300.c | 33 +++++++++++++------------------
2 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 0530095..c51a8c7 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -33,6 +33,49 @@
syscon: syscon at c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
+ clk32: app_32_clk at 32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+ pll13: pll13 at 13M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+ pll208: pll208 at 208M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <208000000>;
+ };
+ app208: app_208_clk at 208M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app104: app_104_clk at 104M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app52: app_52_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&pll208>;
+ };
+ app26: app_26_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&app52>;
+ };
};
timer: timer at c0014000 {
@@ -65,6 +108,7 @@
reg = <0xc0012000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <3>;
+ clocks = <&clk32>;
};
rtc: rtc at c0017000 {
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a41e42e..bebd6c9 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
+#include <linux/of.h>
/* APP side SYSCON registers */
/* CLK Control Register 16bit (R/W) */
@@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
return clk;
}
+static const __initconst struct of_device_id u300_clk_match[] = {
+ {
+ .compatible = "fixed-clock",
+ .data = of_fixed_clk_setup,
+ },
+ {
+ .compatible = "fixed-factor-clock",
+ .data = of_fixed_factor_clk_setup,
+ },
+};
+
void __init u300_clk_init(void __iomem *base)
{
u16 val;
@@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
writew(val, syscon_vbase + U300_SYSCON_PMCR);
- /* These are always available (RTC and PLL13) */
- clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
- CLK_IS_ROOT, 32768);
- /* The watchdog sits directly on the 32 kHz clock */
- clk_register_clkdev(clk, NULL, "coh901327_wdog");
- clk = clk_register_fixed_rate(NULL, "pll13", NULL,
- CLK_IS_ROOT, 13000000);
-
- /* These derive from PLL208 */
- clk = clk_register_fixed_rate(NULL, "pll208", NULL,
- CLK_IS_ROOT, 208000000);
- clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
- 0, 1, 1);
- clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
- 0, 1, 2);
- clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
- 0, 1, 4);
- /* The 52 MHz is divided down to 26 MHz */
- clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
- 0, 1, 2);
+ of_clk_init(u300_clk_match);
/* Directly on the AMBA interconnect */
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/6] i2c: stu300: do not request a specific clock name
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mike Turquette
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Wolfram Sang
From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
We have used the default clock associated with the block
for a long time, only heuristics in the clock system has
made this work anyway. This needs to be done away with as
we start probing this driver and its clocks exclusively
from the device tree.
Cc: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Hi Wolfram: seeking an ACK for this to take it through the
ARM SoC tree with the rest of my device tree clock patches
for U300.
---
drivers/i2c/busses/i2c-stu300.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 1beaa05a..d1a6b20 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -868,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
struct resource *res;
int bus_nr;
int ret = 0;
- char clk_name[] = "I2C0";
dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
if (!dev) {
@@ -877,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
}
bus_nr = pdev->id;
- clk_name[3] += (char)bus_nr;
- dev->clk = devm_clk_get(&pdev->dev, clk_name);
+ dev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
return PTR_ERR(dev->clk);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/6] i2c: stu300: do not request a specific clock name
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
We have used the default clock associated with the block
for a long time, only heuristics in the clock system has
made this work anyway. This needs to be done away with as
we start probing this driver and its clocks exclusively
from the device tree.
Cc: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Wolfram: seeking an ACK for this to take it through the
ARM SoC tree with the rest of my device tree clock patches
for U300.
---
drivers/i2c/busses/i2c-stu300.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 1beaa05a..d1a6b20 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -868,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
struct resource *res;
int bus_nr;
int ret = 0;
- char clk_name[] = "I2C0";
dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
if (!dev) {
@@ -877,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
}
bus_nr = pdev->id;
- clk_name[3] += (char)bus_nr;
- dev->clk = devm_clk_get(&pdev->dev, clk_name);
+ dev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
return PTR_ERR(dev->clk);
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mike Turquette
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
This moves the slow, fast, AHB bridge and "rest" clocks on
the U300 system controller over to registration from the
device tree.
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Hi Mike, I'm seeking an ACK to take this patch through the
ARM SoC tree.
---
.../bindings/clock/ste-u300-syscon-clock.txt | 57 ++++
arch/arm/boot/dts/ste-u300.dts | 149 ++++++++++
arch/arm/mach-u300/timer.c | 2 +-
drivers/clk/clk-u300.c | 320 ++++++++++++++-------
4 files changed, 418 insertions(+), 110 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 0000000..b6a30f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+ 0 = slow clock
+ 1 = fast clock
+ 2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type: ID: Clock:
+-------------------
+0 0 Slow peripheral bridge clock
+0 1 UART0 clock
+0 4 GPIO clock
+0 6 RTC clock
+0 7 Application timer clock
+0 8 Access timer clock
+
+1 0 Fast peripheral bridge clock
+1 1 I2C bus 0 clock
+1 2 I2C bus 1 clock
+1 5 MMC interface peripheral (silicon) clock
+1 6 SPI clock
+
+2 3 CPU clock
+2 4 DMA controller clock
+2 5 External Memory Interface (EMIF) clock
+2 6 NAND flask interface clock
+2 8 XGAM graphics engine clock
+2 9 Shared External Memory Interface (SEMI) clock
+2 10 AHB Subsystem Bridge clock
+2 12 Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <4>;
+ clocks = <&slow_clk>;
+};
+
+gpio: gpio@c0016000 {
+ compatible = "stericsson,gpio-coh901";
+ (...)
+ clocks = <&gpio_clk>;
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index c51a8c7..e83aafc 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
+ /* Slow bridge clocks under PLL13 */
+ slow_clk: slow_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <0>;
+ clocks = <&pll13>;
+ };
+ uart0_clk: uart0_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <1>;
+ clocks = <&slow_clk>;
+ };
+ gpio_clk: gpio_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <4>;
+ clocks = <&slow_clk>;
+ };
+ rtc_clk: rtc_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <6>;
+ clocks = <&slow_clk>;
+ };
+ apptimer_clk: app_tmr_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <7>;
+ clocks = <&slow_clk>;
+ };
+ acc_tmr_clk@13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <8>;
+ clocks = <&slow_clk>;
+ };
pll208: pll208@208M {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -55,6 +98,13 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ cpu_clk@208M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <3>;
+ clocks = <&app208>;
+ };
app104: app_104_clk@104M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ semi_clk@104M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <9>;
+ clocks = <&app104>;
+ };
app52: app_52_clk@52M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ /* AHB subsystem clocks */
+ ahb_clk: ahb_subsys_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <10>;
+ clocks = <&app52>;
+ };
+ intcon_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <12>;
+ clocks = <&ahb_clk>;
+ };
+ emif_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <5>;
+ clocks = <&ahb_clk>;
+ };
+ dmac_clk: dmac_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <4>;
+ clocks = <&app52>;
+ };
+ fsmc_clk: fsmc_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <6>;
+ clocks = <&app52>;
+ };
+ xgam_clk: xgam_clk@52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <8>;
+ clocks = <&app52>;
+ };
app26: app_26_clk@26M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
clock-mult = <1>;
clocks = <&app52>;
};
+ /* Fast bridge clocks */
+ fast_clk: fast_clk@26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <0>;
+ clocks = <&app26>;
+ };
+ i2c0_clk: i2c0_clk@26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <1>;
+ clocks = <&fast_clk>;
+ };
+ i2c1_clk: i2c1_clk@26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <2>;
+ clocks = <&fast_clk>;
+ };
+ mmc_pclk: mmc_p_clk@26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <5>;
+ clocks = <&fast_clk>;
+ };
+ spi_clk: spi_p_clk@26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <6>;
+ clocks = <&fast_clk>;
+ };
};
timer: timer@c0014000 {
@@ -83,6 +219,7 @@
reg = <0xc0014000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <24 25 26 27>;
+ clocks = <&apptimer_clk>;
};
gpio: gpio@c0016000 {
@@ -90,6 +227,7 @@
reg = <0xc0016000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <0 1 2 18 21 22 23>;
+ clocks = <&gpio_clk>;
interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6";
interrupt-controller;
@@ -116,6 +254,7 @@
reg = <0xc0017000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <10>;
+ clocks = <&rtc_clk>;
};
dmac: dma-controller@c00020000 {
@@ -125,6 +264,7 @@
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
+ clocks = <&dmac_clk>;
};
/* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
<0x80010000 0x4000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
nand-skip-bbtscan;
+ clocks = <&fsmc_clk>;
partition@0 {
label = "boot records";
@@ -158,6 +299,7 @@
reg = <0xc0004000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <8>;
+ clocks = <&i2c0_clk>;
#address-cells = <1>;
#size-cells = <0>;
ab3100: ab3100@0x48 {
@@ -235,6 +377,7 @@
reg = <0xc0005000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <9>;
+ clocks = <&i2c1_clk>;
#address-cells = <1>;
#size-cells = <0>;
fwcam0: fwcam@0x10 {
@@ -270,6 +413,8 @@
reg = <0xc0013000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <22>;
+ clocks = <&uart0_clk>, <&uart0_clk>;
+ clock-names = "apb_pclk", "uart0_clk";
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
};
@@ -288,6 +433,8 @@
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
+ clocks = <&mmc_pclk>;
+ clock-names = "apb_pclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
reg = <0xc0006000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <23>;
+ clocks = <&spi_clk>, <&spi_clk>;
+ clock-names = "apb_pclk", "spi_clk";
dmas = <&dmac 27 &dmac 28>;
dma-names = "tx", "rx";
#address-cells = <1>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81d..390ae5f 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
/* Clock the interrupt controller */
- clk = clk_get_sys("apptimer", NULL);
+ clk = of_clk_get(np, 0);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index bebd6c9..5f234d3 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
return clk;
}
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+ u8 type;
+ u8 id;
+ bool hw_ctrld;
+ u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 3,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 4,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 8,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 9,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 10,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 12,
+ .hw_ctrld = false,
+ /* INTCON: cannot be enabled, just taken out of reset */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 2,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 4,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 6,
+ .hw_ctrld = true,
+ /* No clock enable register bit */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 7,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 8,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+ },
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+ void __iomem *res_reg;
+ void __iomem *en_reg;
+ u32 clk_type;
+ u32 clk_id;
+ int i;
+
+ if (of_property_read_u32(np, "clock-type", &clk_type)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+ __func__, clk_name);
+ return;
+ }
+ if (of_property_read_u32(np, "clock-id", &clk_id)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+ __func__, clk_name);
+ return;
+ }
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ switch (clk_type) {
+ case U300_CLK_TYPE_SLOW:
+ res_reg = syscon_vbase + U300_SYSCON_RSR;
+ en_reg = syscon_vbase + U300_SYSCON_CESR;
+ break;
+ case U300_CLK_TYPE_FAST:
+ res_reg = syscon_vbase + U300_SYSCON_RFR;
+ en_reg = syscon_vbase + U300_SYSCON_CEFR;
+ break;
+ case U300_CLK_TYPE_REST:
+ res_reg = syscon_vbase + U300_SYSCON_RRR;
+ en_reg = syscon_vbase + U300_SYSCON_CERR;
+ break;
+ default:
+ pr_err("unknown clock type %x specified\n", clk_type);
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+ const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+ if (u3clk->type == clk_type && u3clk->id == clk_id)
+ clk = syscon_clk_register(NULL,
+ clk_name, parent_name,
+ 0, u3clk->hw_ctrld,
+ res_reg, u3clk->id,
+ en_reg, u3clk->id,
+ u3clk->clk_val);
+ }
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+ /*
+ * Some few system clocks - device tree does not
+ * represent clocks without a corresponding device node.
+ * for now we add these three clocks here.
+ */
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+ clk_register_clkdev(clk, NULL, "pl172");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+ clk_register_clkdev(clk, NULL, "semi");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+ clk_register_clkdev(clk, NULL, "intcon");
+ }
+}
+
/**
* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
* @hw: corresponding clock hardware entry
@@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
.compatible = "fixed-factor-clock",
.data = of_fixed_factor_clk_setup,
},
+ {
+ .compatible = "stericsson,u300-syscon-clk",
+ .data = of_u300_syscon_clk_init,
+ },
};
void __init u300_clk_init(void __iomem *base)
@@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
of_clk_init(u300_clk_match);
- /* Directly on the AMBA interconnect */
- clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 3,
- syscon_vbase + U300_SYSCON_CERR, 3,
- U300_SYSCON_SBCER_CPU_CLK_EN);
- clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 4,
- syscon_vbase + U300_SYSCON_CERR, 4,
- U300_SYSCON_SBCER_DMAC_CLK_EN);
- clk_register_clkdev(clk, NULL, "dma");
- clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 6,
- syscon_vbase + U300_SYSCON_CERR, 6,
- U300_SYSCON_SBCER_NANDIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "fsmc-nand");
- clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 8,
- syscon_vbase + U300_SYSCON_CERR, 8,
- U300_SYSCON_SBCER_XGAM_CLK_EN);
- clk_register_clkdev(clk, NULL, "xgam");
- clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 9,
- syscon_vbase + U300_SYSCON_CERR, 9,
- U300_SYSCON_SBCER_SEMI_CLK_EN);
- clk_register_clkdev(clk, NULL, "semi");
-
- /* AHB bridge clocks */
- clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 10,
- syscon_vbase + U300_SYSCON_CERR, 10,
- U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 12,
- syscon_vbase + U300_SYSCON_CERR, 12,
- /* Cannot be enabled, just taken out of reset */
- 0xFFFFU);
- clk_register_clkdev(clk, NULL, "intcon");
- clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 5,
- syscon_vbase + U300_SYSCON_CERR, 5,
- U300_SYSCON_SBCER_EMIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "pl172");
-
- /* FAST bridge clocks */
- clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
- syscon_vbase + U300_SYSCON_RFR, 0,
- syscon_vbase + U300_SYSCON_CEFR, 0,
- U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 1,
- syscon_vbase + U300_SYSCON_CEFR, 1,
- U300_SYSCON_SBCER_I2C0_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.0");
- clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 2,
- syscon_vbase + U300_SYSCON_CEFR, 2,
- U300_SYSCON_SBCER_I2C1_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.1");
- clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 5,
- syscon_vbase + U300_SYSCON_CEFR, 5,
- U300_SYSCON_SBCER_MMC_CLK_EN);
- clk_register_clkdev(clk, "apb_pclk", "mmci");
- clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 6,
- syscon_vbase + U300_SYSCON_CEFR, 6,
- U300_SYSCON_SBCER_SPI_CLK_EN);
- /* The SPI has no external clock for the outward bus, uses the pclk */
- clk_register_clkdev(clk, NULL, "pl022");
- clk_register_clkdev(clk, "apb_pclk", "pl022");
-
- /* SLOW bridge clocks */
- clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 0,
- syscon_vbase + U300_SYSCON_CESR, 0,
- U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 1,
- syscon_vbase + U300_SYSCON_CESR, 1,
- U300_SYSCON_SBCER_UART_CLK_EN);
- /* Same clock is used for APB and outward bus */
- clk_register_clkdev(clk, NULL, "uart0");
- clk_register_clkdev(clk, "apb_pclk", "uart0");
- clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 4,
- syscon_vbase + U300_SYSCON_CESR, 4,
- U300_SYSCON_SBCER_GPIO_CLK_EN);
- clk_register_clkdev(clk, NULL, "u300-gpio");
- clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 5,
- syscon_vbase + U300_SYSCON_CESR, 6,
- U300_SYSCON_SBCER_KEYPAD_CLK_EN);
- clk_register_clkdev(clk, NULL, "coh901461-keypad");
- clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 6,
- /* No clock enable register bit */
- NULL, 0, 0xFFFFU);
- clk_register_clkdev(clk, NULL, "rtc-coh901331");
- clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 7,
- syscon_vbase + U300_SYSCON_CESR, 7,
- U300_SYSCON_SBCER_APP_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "apptimer");
- clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 8,
- syscon_vbase + U300_SYSCON_CESR, 8,
- U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "timer");
-
/* Then this special MMC/SD clock */
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
clk_register_clkdev(clk, NULL, "mmci");
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This moves the slow, fast, AHB bridge and "rest" clocks on
the U300 system controller over to registration from the
device tree.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Mike, I'm seeking an ACK to take this patch through the
ARM SoC tree.
---
.../bindings/clock/ste-u300-syscon-clock.txt | 57 ++++
arch/arm/boot/dts/ste-u300.dts | 149 ++++++++++
arch/arm/mach-u300/timer.c | 2 +-
drivers/clk/clk-u300.c | 320 ++++++++++++++-------
4 files changed, 418 insertions(+), 110 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 0000000..b6a30f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+ 0 = slow clock
+ 1 = fast clock
+ 2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type: ID: Clock:
+-------------------
+0 0 Slow peripheral bridge clock
+0 1 UART0 clock
+0 4 GPIO clock
+0 6 RTC clock
+0 7 Application timer clock
+0 8 Access timer clock
+
+1 0 Fast peripheral bridge clock
+1 1 I2C bus 0 clock
+1 2 I2C bus 1 clock
+1 5 MMC interface peripheral (silicon) clock
+1 6 SPI clock
+
+2 3 CPU clock
+2 4 DMA controller clock
+2 5 External Memory Interface (EMIF) clock
+2 6 NAND flask interface clock
+2 8 XGAM graphics engine clock
+2 9 Shared External Memory Interface (SEMI) clock
+2 10 AHB Subsystem Bridge clock
+2 12 Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <4>;
+ clocks = <&slow_clk>;
+};
+
+gpio: gpio at c0016000 {
+ compatible = "stericsson,gpio-coh901";
+ (...)
+ clocks = <&gpio_clk>;
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index c51a8c7..e83aafc 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
+ /* Slow bridge clocks under PLL13 */
+ slow_clk: slow_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <0>;
+ clocks = <&pll13>;
+ };
+ uart0_clk: uart0_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <1>;
+ clocks = <&slow_clk>;
+ };
+ gpio_clk: gpio_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <4>;
+ clocks = <&slow_clk>;
+ };
+ rtc_clk: rtc_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <6>;
+ clocks = <&slow_clk>;
+ };
+ apptimer_clk: app_tmr_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <7>;
+ clocks = <&slow_clk>;
+ };
+ acc_tmr_clk at 13M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <0>; /* Slow */
+ clock-id = <8>;
+ clocks = <&slow_clk>;
+ };
pll208: pll208 at 208M {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -55,6 +98,13 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ cpu_clk at 208M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <3>;
+ clocks = <&app208>;
+ };
app104: app_104_clk at 104M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ semi_clk at 104M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <9>;
+ clocks = <&app104>;
+ };
app52: app_52_clk at 52M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
clock-mult = <1>;
clocks = <&pll208>;
};
+ /* AHB subsystem clocks */
+ ahb_clk: ahb_subsys_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <10>;
+ clocks = <&app52>;
+ };
+ intcon_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <12>;
+ clocks = <&ahb_clk>;
+ };
+ emif_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <5>;
+ clocks = <&ahb_clk>;
+ };
+ dmac_clk: dmac_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <4>;
+ clocks = <&app52>;
+ };
+ fsmc_clk: fsmc_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <6>;
+ clocks = <&app52>;
+ };
+ xgam_clk: xgam_clk at 52M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <2>; /* Rest */
+ clock-id = <8>;
+ clocks = <&app52>;
+ };
app26: app_26_clk at 26M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
clock-mult = <1>;
clocks = <&app52>;
};
+ /* Fast bridge clocks */
+ fast_clk: fast_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <0>;
+ clocks = <&app26>;
+ };
+ i2c0_clk: i2c0_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <1>;
+ clocks = <&fast_clk>;
+ };
+ i2c1_clk: i2c1_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <2>;
+ clocks = <&fast_clk>;
+ };
+ mmc_pclk: mmc_p_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <5>;
+ clocks = <&fast_clk>;
+ };
+ spi_clk: spi_p_clk at 26M {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-clk";
+ clock-type = <1>; /* Fast */
+ clock-id = <6>;
+ clocks = <&fast_clk>;
+ };
};
timer: timer at c0014000 {
@@ -83,6 +219,7 @@
reg = <0xc0014000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <24 25 26 27>;
+ clocks = <&apptimer_clk>;
};
gpio: gpio at c0016000 {
@@ -90,6 +227,7 @@
reg = <0xc0016000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <0 1 2 18 21 22 23>;
+ clocks = <&gpio_clk>;
interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6";
interrupt-controller;
@@ -116,6 +254,7 @@
reg = <0xc0017000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <10>;
+ clocks = <&rtc_clk>;
};
dmac: dma-controller at c00020000 {
@@ -125,6 +264,7 @@
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
+ clocks = <&dmac_clk>;
};
/* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
<0x80010000 0x4000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
nand-skip-bbtscan;
+ clocks = <&fsmc_clk>;
partition at 0 {
label = "boot records";
@@ -158,6 +299,7 @@
reg = <0xc0004000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <8>;
+ clocks = <&i2c0_clk>;
#address-cells = <1>;
#size-cells = <0>;
ab3100: ab3100 at 0x48 {
@@ -235,6 +377,7 @@
reg = <0xc0005000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <9>;
+ clocks = <&i2c1_clk>;
#address-cells = <1>;
#size-cells = <0>;
fwcam0: fwcam at 0x10 {
@@ -270,6 +413,8 @@
reg = <0xc0013000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <22>;
+ clocks = <&uart0_clk>, <&uart0_clk>;
+ clock-names = "apb_pclk", "uart0_clk";
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
};
@@ -288,6 +433,8 @@
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
+ clocks = <&mmc_pclk>;
+ clock-names = "apb_pclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
reg = <0xc0006000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <23>;
+ clocks = <&spi_clk>, <&spi_clk>;
+ clock-names = "apb_pclk", "spi_clk";
dmas = <&dmac 27 &dmac 28>;
dma-names = "tx", "rx";
#address-cells = <1>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81d..390ae5f 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
/* Clock the interrupt controller */
- clk = clk_get_sys("apptimer", NULL);
+ clk = of_clk_get(np, 0);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index bebd6c9..5f234d3 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
return clk;
}
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+ u8 type;
+ u8 id;
+ bool hw_ctrld;
+ u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 3,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 4,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 8,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 9,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 10,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 12,
+ .hw_ctrld = false,
+ /* INTCON: cannot be enabled, just taken out of reset */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 2,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 4,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 6,
+ .hw_ctrld = true,
+ /* No clock enable register bit */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 7,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 8,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+ },
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+ void __iomem *res_reg;
+ void __iomem *en_reg;
+ u32 clk_type;
+ u32 clk_id;
+ int i;
+
+ if (of_property_read_u32(np, "clock-type", &clk_type)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+ __func__, clk_name);
+ return;
+ }
+ if (of_property_read_u32(np, "clock-id", &clk_id)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+ __func__, clk_name);
+ return;
+ }
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ switch (clk_type) {
+ case U300_CLK_TYPE_SLOW:
+ res_reg = syscon_vbase + U300_SYSCON_RSR;
+ en_reg = syscon_vbase + U300_SYSCON_CESR;
+ break;
+ case U300_CLK_TYPE_FAST:
+ res_reg = syscon_vbase + U300_SYSCON_RFR;
+ en_reg = syscon_vbase + U300_SYSCON_CEFR;
+ break;
+ case U300_CLK_TYPE_REST:
+ res_reg = syscon_vbase + U300_SYSCON_RRR;
+ en_reg = syscon_vbase + U300_SYSCON_CERR;
+ break;
+ default:
+ pr_err("unknown clock type %x specified\n", clk_type);
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+ const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+ if (u3clk->type == clk_type && u3clk->id == clk_id)
+ clk = syscon_clk_register(NULL,
+ clk_name, parent_name,
+ 0, u3clk->hw_ctrld,
+ res_reg, u3clk->id,
+ en_reg, u3clk->id,
+ u3clk->clk_val);
+ }
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+ /*
+ * Some few system clocks - device tree does not
+ * represent clocks without a corresponding device node.
+ * for now we add these three clocks here.
+ */
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+ clk_register_clkdev(clk, NULL, "pl172");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+ clk_register_clkdev(clk, NULL, "semi");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+ clk_register_clkdev(clk, NULL, "intcon");
+ }
+}
+
/**
* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
* @hw: corresponding clock hardware entry
@@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
.compatible = "fixed-factor-clock",
.data = of_fixed_factor_clk_setup,
},
+ {
+ .compatible = "stericsson,u300-syscon-clk",
+ .data = of_u300_syscon_clk_init,
+ },
};
void __init u300_clk_init(void __iomem *base)
@@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
of_clk_init(u300_clk_match);
- /* Directly on the AMBA interconnect */
- clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 3,
- syscon_vbase + U300_SYSCON_CERR, 3,
- U300_SYSCON_SBCER_CPU_CLK_EN);
- clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 4,
- syscon_vbase + U300_SYSCON_CERR, 4,
- U300_SYSCON_SBCER_DMAC_CLK_EN);
- clk_register_clkdev(clk, NULL, "dma");
- clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 6,
- syscon_vbase + U300_SYSCON_CERR, 6,
- U300_SYSCON_SBCER_NANDIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "fsmc-nand");
- clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 8,
- syscon_vbase + U300_SYSCON_CERR, 8,
- U300_SYSCON_SBCER_XGAM_CLK_EN);
- clk_register_clkdev(clk, NULL, "xgam");
- clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 9,
- syscon_vbase + U300_SYSCON_CERR, 9,
- U300_SYSCON_SBCER_SEMI_CLK_EN);
- clk_register_clkdev(clk, NULL, "semi");
-
- /* AHB bridge clocks */
- clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 10,
- syscon_vbase + U300_SYSCON_CERR, 10,
- U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 12,
- syscon_vbase + U300_SYSCON_CERR, 12,
- /* Cannot be enabled, just taken out of reset */
- 0xFFFFU);
- clk_register_clkdev(clk, NULL, "intcon");
- clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 5,
- syscon_vbase + U300_SYSCON_CERR, 5,
- U300_SYSCON_SBCER_EMIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "pl172");
-
- /* FAST bridge clocks */
- clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
- syscon_vbase + U300_SYSCON_RFR, 0,
- syscon_vbase + U300_SYSCON_CEFR, 0,
- U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 1,
- syscon_vbase + U300_SYSCON_CEFR, 1,
- U300_SYSCON_SBCER_I2C0_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.0");
- clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 2,
- syscon_vbase + U300_SYSCON_CEFR, 2,
- U300_SYSCON_SBCER_I2C1_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.1");
- clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 5,
- syscon_vbase + U300_SYSCON_CEFR, 5,
- U300_SYSCON_SBCER_MMC_CLK_EN);
- clk_register_clkdev(clk, "apb_pclk", "mmci");
- clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 6,
- syscon_vbase + U300_SYSCON_CEFR, 6,
- U300_SYSCON_SBCER_SPI_CLK_EN);
- /* The SPI has no external clock for the outward bus, uses the pclk */
- clk_register_clkdev(clk, NULL, "pl022");
- clk_register_clkdev(clk, "apb_pclk", "pl022");
-
- /* SLOW bridge clocks */
- clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 0,
- syscon_vbase + U300_SYSCON_CESR, 0,
- U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 1,
- syscon_vbase + U300_SYSCON_CESR, 1,
- U300_SYSCON_SBCER_UART_CLK_EN);
- /* Same clock is used for APB and outward bus */
- clk_register_clkdev(clk, NULL, "uart0");
- clk_register_clkdev(clk, "apb_pclk", "uart0");
- clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 4,
- syscon_vbase + U300_SYSCON_CESR, 4,
- U300_SYSCON_SBCER_GPIO_CLK_EN);
- clk_register_clkdev(clk, NULL, "u300-gpio");
- clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 5,
- syscon_vbase + U300_SYSCON_CESR, 6,
- U300_SYSCON_SBCER_KEYPAD_CLK_EN);
- clk_register_clkdev(clk, NULL, "coh901461-keypad");
- clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 6,
- /* No clock enable register bit */
- NULL, 0, 0xFFFFU);
- clk_register_clkdev(clk, NULL, "rtc-coh901331");
- clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 7,
- syscon_vbase + U300_SYSCON_CESR, 7,
- U300_SYSCON_SBCER_APP_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "apptimer");
- clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 8,
- syscon_vbase + U300_SYSCON_CESR, 8,
- U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "timer");
-
/* Then this special MMC/SD clock */
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
clk_register_clkdev(clk, NULL, "mmci");
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 17:31 ` Linus Walleij
-1 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, Mike Turquette
Cc: devicetree-discuss, Linus Walleij, Arnd Bergmann
From: Linus Walleij <linus.walleij@linaro.org>
This converts the last of the U300 clocks to being probed from
the device tree.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Mike, I'm seeking an ACK on this to take it through the
ARM SoC tree.
---
.../bindings/clock/ste-u300-syscon-clock.txt | 23 ++++++++++++++++++++++
arch/arm/boot/dts/ste-u300.dts | 9 +++++++--
drivers/clk/clk-u300.c | 22 ++++++++++++++++-----
3 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
index b6a30f5..7cafcb9 100644
--- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -55,3 +55,26 @@ gpio: gpio@c0016000 {
(...)
clocks = <&gpio_clk>;
};
+
+
+Bindings for the MMC/SD card clock:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+
+Optional properties:
+- clocks: parent clock(s)
+
+mmc_mclk: mmc_mclk {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-mclk";
+ clocks = <&mmc_pclk>;
+};
+
+mmcsd: mmcsd@c0001000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ clocks = <&mmc_pclk>, <&mmc_mclk>;
+ clock-names = "apb_pclk", "mclk";
+ (...)
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index e83aafc..d5dd243 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -205,6 +205,11 @@
clock-id = <5>;
clocks = <&fast_clk>;
};
+ mmc_mclk: mmc_mclk {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-mclk";
+ clocks = <&mmc_pclk>;
+ };
spi_clk: spi_p_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
@@ -433,8 +438,8 @@
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
- clocks = <&mmc_pclk>;
- clock-names = "apb_pclk";
+ clocks = <&mmc_pclk>, <&mmc_mclk>;
+ clock-names = "apb_pclk", "mclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
mmc-cap-mmc-highspeed;
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 5f234d3..8774e05 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
return clk;
}
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+ if (!IS_ERR(clk))
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
static const __initconst struct of_device_id u300_clk_match[] = {
{
.compatible = "fixed-clock",
@@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
.compatible = "stericsson,u300-syscon-clk",
.data = of_u300_syscon_clk_init,
},
+ {
+ .compatible = "stericsson,u300-syscon-mclk",
+ .data = of_u300_syscon_mclk_init,
+ },
};
+
void __init u300_clk_init(void __iomem *base)
{
u16 val;
- struct clk *clk;
syscon_vbase = base;
@@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
writew(val, syscon_vbase + U300_SYSCON_PMCR);
of_clk_init(u300_clk_match);
-
- /* Then this special MMC/SD clock */
- clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
- clk_register_clkdev(clk, NULL, "mmci");
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
@ 2013-05-23 17:31 ` Linus Walleij
0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2013-05-23 17:31 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This converts the last of the U300 clocks to being probed from
the device tree.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Mike, I'm seeking an ACK on this to take it through the
ARM SoC tree.
---
.../bindings/clock/ste-u300-syscon-clock.txt | 23 ++++++++++++++++++++++
arch/arm/boot/dts/ste-u300.dts | 9 +++++++--
drivers/clk/clk-u300.c | 22 ++++++++++++++++-----
3 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
index b6a30f5..7cafcb9 100644
--- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -55,3 +55,26 @@ gpio: gpio at c0016000 {
(...)
clocks = <&gpio_clk>;
};
+
+
+Bindings for the MMC/SD card clock:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+
+Optional properties:
+- clocks: parent clock(s)
+
+mmc_mclk: mmc_mclk {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-mclk";
+ clocks = <&mmc_pclk>;
+};
+
+mmcsd: mmcsd at c0001000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ clocks = <&mmc_pclk>, <&mmc_mclk>;
+ clock-names = "apb_pclk", "mclk";
+ (...)
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index e83aafc..d5dd243 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -205,6 +205,11 @@
clock-id = <5>;
clocks = <&fast_clk>;
};
+ mmc_mclk: mmc_mclk {
+ #clock-cells = <0>;
+ compatible = "stericsson,u300-syscon-mclk";
+ clocks = <&mmc_pclk>;
+ };
spi_clk: spi_p_clk at 26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
@@ -433,8 +438,8 @@
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
- clocks = <&mmc_pclk>;
- clock-names = "apb_pclk";
+ clocks = <&mmc_pclk>, <&mmc_mclk>;
+ clock-names = "apb_pclk", "mclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
mmc-cap-mmc-highspeed;
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 5f234d3..8774e05 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
return clk;
}
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+ if (!IS_ERR(clk))
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
static const __initconst struct of_device_id u300_clk_match[] = {
{
.compatible = "fixed-clock",
@@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
.compatible = "stericsson,u300-syscon-clk",
.data = of_u300_syscon_clk_init,
},
+ {
+ .compatible = "stericsson,u300-syscon-mclk",
+ .data = of_u300_syscon_mclk_init,
+ },
};
+
void __init u300_clk_init(void __iomem *base)
{
u16 val;
- struct clk *clk;
syscon_vbase = base;
@@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
writew(val, syscon_vbase + U300_SYSCON_PMCR);
of_clk_init(u300_clk_match);
-
- /* Then this special MMC/SD clock */
- clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
- clk_register_clkdev(clk, NULL, "mmci");
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 4/6] i2c: stu300: do not request a specific clock name
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-23 23:09 ` Wolfram Sang
-1 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2013-05-23 23:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Mike Turquette, Arnd Bergmann, devicetree-discuss, Linus Walleij,
linux-arm-kernel
On Thu, May 23, 2013 at 07:31:26PM +0200, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> We have used the default clock associated with the block
> for a long time, only heuristics in the clock system has
> made this work anyway. This needs to be done away with as
> we start probing this driver and its clocks exclusively
> from the device tree.
>
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 4/6] i2c: stu300: do not request a specific clock name
@ 2013-05-23 23:09 ` Wolfram Sang
0 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2013-05-23 23:09 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 23, 2013 at 07:31:26PM +0200, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> We have used the default clock associated with the block
> for a long time, only heuristics in the clock system has
> made this work anyway. This needs to be done away with as
> we start probing this driver and its clocks exclusively
> from the device tree.
>
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-30 19:00 ` Mike Turquette
-1 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:00 UTC (permalink / raw)
To: Linus Walleij, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Quoting Linus Walleij (2013-05-23 10:31:25)
> From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> This converts the fixed and fixed-factor clocks in the U300
> platform to register themselves from the device tree.
>
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Hi Mike, seeking an ACK on this to take the series through
> ARM SoC.
I'm happy to see another conversion to of_clk_init.
Acked-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/clk-u300.c | 33 +++++++++++++------------------
> 2 files changed, 57 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index 0530095..c51a8c7 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -33,6 +33,49 @@
> syscon: syscon@c0011000 {
> compatible = "stericsson,u300-syscon";
> reg = <0xc0011000 0x1000>;
> + clk32: app_32_clk@32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + };
> + pll13: pll13@13M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <13000000>;
> + };
> + pll208: pll208@208M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <208000000>;
> + };
> + app208: app_208_clk@208M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app104: app_104_clk@104M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app52: app_52_clk@52M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <4>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app26: app_26_clk@26M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&app52>;
> + };
> };
>
> timer: timer@c0014000 {
> @@ -65,6 +108,7 @@
> reg = <0xc0012000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <3>;
> + clocks = <&clk32>;
> };
>
> rtc: rtc@c0017000 {
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index a41e42e..bebd6c9 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -11,6 +11,7 @@
> #include <linux/io.h>
> #include <linux/clk-provider.h>
> #include <linux/spinlock.h>
> +#include <linux/of.h>
>
> /* APP side SYSCON registers */
> /* CLK Control Register 16bit (R/W) */
> @@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +static const __initconst struct of_device_id u300_clk_match[] = {
> + {
> + .compatible = "fixed-clock",
> + .data = of_fixed_clk_setup,
> + },
> + {
> + .compatible = "fixed-factor-clock",
> + .data = of_fixed_factor_clk_setup,
> + },
> +};
> +
> void __init u300_clk_init(void __iomem *base)
> {
> u16 val;
> @@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
> val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
> writew(val, syscon_vbase + U300_SYSCON_PMCR);
>
> - /* These are always available (RTC and PLL13) */
> - clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
> - CLK_IS_ROOT, 32768);
> - /* The watchdog sits directly on the 32 kHz clock */
> - clk_register_clkdev(clk, NULL, "coh901327_wdog");
> - clk = clk_register_fixed_rate(NULL, "pll13", NULL,
> - CLK_IS_ROOT, 13000000);
> -
> - /* These derive from PLL208 */
> - clk = clk_register_fixed_rate(NULL, "pll208", NULL,
> - CLK_IS_ROOT, 208000000);
> - clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
> - 0, 1, 1);
> - clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
> - 0, 1, 2);
> - clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
> - 0, 1, 4);
> - /* The 52 MHz is divided down to 26 MHz */
> - clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
> - 0, 1, 2);
> + of_clk_init(u300_clk_match);
>
> /* Directly on the AMBA interconnect */
> clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT
@ 2013-05-30 19:00 ` Mike Turquette
0 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:00 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Linus Walleij (2013-05-23 10:31:25)
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This converts the fixed and fixed-factor clocks in the U300
> platform to register themselves from the device tree.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Mike, seeking an ACK on this to take the series through
> ARM SoC.
I'm happy to see another conversion to of_clk_init.
Acked-by: Mike Turquette <mturquette@linaro.org>
> ---
> arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/clk-u300.c | 33 +++++++++++++------------------
> 2 files changed, 57 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index 0530095..c51a8c7 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -33,6 +33,49 @@
> syscon: syscon at c0011000 {
> compatible = "stericsson,u300-syscon";
> reg = <0xc0011000 0x1000>;
> + clk32: app_32_clk at 32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + };
> + pll13: pll13 at 13M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <13000000>;
> + };
> + pll208: pll208 at 208M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <208000000>;
> + };
> + app208: app_208_clk at 208M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app104: app_104_clk at 104M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app52: app_52_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <4>;
> + clock-mult = <1>;
> + clocks = <&pll208>;
> + };
> + app26: app_26_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&app52>;
> + };
> };
>
> timer: timer at c0014000 {
> @@ -65,6 +108,7 @@
> reg = <0xc0012000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <3>;
> + clocks = <&clk32>;
> };
>
> rtc: rtc at c0017000 {
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index a41e42e..bebd6c9 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -11,6 +11,7 @@
> #include <linux/io.h>
> #include <linux/clk-provider.h>
> #include <linux/spinlock.h>
> +#include <linux/of.h>
>
> /* APP side SYSCON registers */
> /* CLK Control Register 16bit (R/W) */
> @@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +static const __initconst struct of_device_id u300_clk_match[] = {
> + {
> + .compatible = "fixed-clock",
> + .data = of_fixed_clk_setup,
> + },
> + {
> + .compatible = "fixed-factor-clock",
> + .data = of_fixed_factor_clk_setup,
> + },
> +};
> +
> void __init u300_clk_init(void __iomem *base)
> {
> u16 val;
> @@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base)
> val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
> writew(val, syscon_vbase + U300_SYSCON_PMCR);
>
> - /* These are always available (RTC and PLL13) */
> - clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
> - CLK_IS_ROOT, 32768);
> - /* The watchdog sits directly on the 32 kHz clock */
> - clk_register_clkdev(clk, NULL, "coh901327_wdog");
> - clk = clk_register_fixed_rate(NULL, "pll13", NULL,
> - CLK_IS_ROOT, 13000000);
> -
> - /* These derive from PLL208 */
> - clk = clk_register_fixed_rate(NULL, "pll208", NULL,
> - CLK_IS_ROOT, 208000000);
> - clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
> - 0, 1, 1);
> - clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
> - 0, 1, 2);
> - clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
> - 0, 1, 4);
> - /* The 52 MHz is divided down to 26 MHz */
> - clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
> - 0, 1, 2);
> + of_clk_init(u300_clk_match);
>
> /* Directly on the AMBA interconnect */
> clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-30 19:06 ` Mike Turquette
-1 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:06 UTC (permalink / raw)
To: Linus Walleij, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Quoting Linus Walleij (2013-05-23 10:31:27)
> From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> This moves the slow, fast, AHB bridge and "rest" clocks on
> the U300 system controller over to registration from the
> device tree.
>
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Hi Mike, I'm seeking an ACK to take this patch through the
> ARM SoC tree.
Acked-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/clock/ste-u300-syscon-clock.txt | 57 ++++
> arch/arm/boot/dts/ste-u300.dts | 149 ++++++++++
> arch/arm/mach-u300/timer.c | 2 +-
> drivers/clk/clk-u300.c | 320 ++++++++++++++-------
> 4 files changed, 418 insertions(+), 110 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> new file mode 100644
> index 0000000..b6a30f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -0,0 +1,57 @@
> +Clock bindings for ST-Ericsson U300 System Controller Clocks
> +
> +Bindings for the gated system controller clocks:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-clk"
> +- #clock-cells: must be <0>
> +- clock-type: specifies the type of clock:
> + 0 = slow clock
> + 1 = fast clock
> + 2 = rest/remaining clock
> +- clock-id: specifies the clock in the type range
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +The available clocks per type are as follows:
> +
> +Type: ID: Clock:
> +-------------------
> +0 0 Slow peripheral bridge clock
> +0 1 UART0 clock
> +0 4 GPIO clock
> +0 6 RTC clock
> +0 7 Application timer clock
> +0 8 Access timer clock
> +
> +1 0 Fast peripheral bridge clock
> +1 1 I2C bus 0 clock
> +1 2 I2C bus 1 clock
> +1 5 MMC interface peripheral (silicon) clock
> +1 6 SPI clock
> +
> +2 3 CPU clock
> +2 4 DMA controller clock
> +2 5 External Memory Interface (EMIF) clock
> +2 6 NAND flask interface clock
> +2 8 XGAM graphics engine clock
> +2 9 Shared External Memory Interface (SEMI) clock
> +2 10 AHB Subsystem Bridge clock
> +2 12 Interrupt controller clock
> +
> +Example:
> +
> +gpio_clk: gpio_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <4>;
> + clocks = <&slow_clk>;
> +};
> +
> +gpio: gpio@c0016000 {
> + compatible = "stericsson,gpio-coh901";
> + (...)
> + clocks = <&gpio_clk>;
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index c51a8c7..e83aafc 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -43,6 +43,49 @@
> compatible = "fixed-clock";
> clock-frequency = <13000000>;
> };
> + /* Slow bridge clocks under PLL13 */
> + slow_clk: slow_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <0>;
> + clocks = <&pll13>;
> + };
> + uart0_clk: uart0_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <1>;
> + clocks = <&slow_clk>;
> + };
> + gpio_clk: gpio_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <4>;
> + clocks = <&slow_clk>;
> + };
> + rtc_clk: rtc_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <6>;
> + clocks = <&slow_clk>;
> + };
> + apptimer_clk: app_tmr_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <7>;
> + clocks = <&slow_clk>;
> + };
> + acc_tmr_clk@13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <8>;
> + clocks = <&slow_clk>;
> + };
> pll208: pll208@208M {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> @@ -55,6 +98,13 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + cpu_clk@208M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <3>;
> + clocks = <&app208>;
> + };
> app104: app_104_clk@104M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -62,6 +112,13 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + semi_clk@104M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <9>;
> + clocks = <&app104>;
> + };
> app52: app_52_clk@52M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -69,6 +126,49 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + /* AHB subsystem clocks */
> + ahb_clk: ahb_subsys_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <10>;
> + clocks = <&app52>;
> + };
> + intcon_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <12>;
> + clocks = <&ahb_clk>;
> + };
> + emif_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <5>;
> + clocks = <&ahb_clk>;
> + };
> + dmac_clk: dmac_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <4>;
> + clocks = <&app52>;
> + };
> + fsmc_clk: fsmc_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <6>;
> + clocks = <&app52>;
> + };
> + xgam_clk: xgam_clk@52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <8>;
> + clocks = <&app52>;
> + };
> app26: app_26_clk@26M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -76,6 +176,42 @@
> clock-mult = <1>;
> clocks = <&app52>;
> };
> + /* Fast bridge clocks */
> + fast_clk: fast_clk@26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <0>;
> + clocks = <&app26>;
> + };
> + i2c0_clk: i2c0_clk@26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <1>;
> + clocks = <&fast_clk>;
> + };
> + i2c1_clk: i2c1_clk@26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <2>;
> + clocks = <&fast_clk>;
> + };
> + mmc_pclk: mmc_p_clk@26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <5>;
> + clocks = <&fast_clk>;
> + };
> + spi_clk: spi_p_clk@26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <6>;
> + clocks = <&fast_clk>;
> + };
> };
>
> timer: timer@c0014000 {
> @@ -83,6 +219,7 @@
> reg = <0xc0014000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <24 25 26 27>;
> + clocks = <&apptimer_clk>;
> };
>
> gpio: gpio@c0016000 {
> @@ -90,6 +227,7 @@
> reg = <0xc0016000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <0 1 2 18 21 22 23>;
> + clocks = <&gpio_clk>;
> interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
> "gpio4", "gpio5", "gpio6";
> interrupt-controller;
> @@ -116,6 +254,7 @@
> reg = <0xc0017000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <10>;
> + clocks = <&rtc_clk>;
> };
>
> dmac: dma-controller@c00020000 {
> @@ -125,6 +264,7 @@
> interrupts = <2>;
> #dma-cells = <1>;
> dma-channels = <40>;
> + clocks = <&dmac_clk>;
> };
>
> /* A NAND flash of 128 MiB */
> @@ -138,6 +278,7 @@
> <0x80010000 0x4000>; /* NAND Base CMD */
> reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
> nand-skip-bbtscan;
> + clocks = <&fsmc_clk>;
>
> partition@0 {
> label = "boot records";
> @@ -158,6 +299,7 @@
> reg = <0xc0004000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <8>;
> + clocks = <&i2c0_clk>;
> #address-cells = <1>;
> #size-cells = <0>;
> ab3100: ab3100@0x48 {
> @@ -235,6 +377,7 @@
> reg = <0xc0005000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <9>;
> + clocks = <&i2c1_clk>;
> #address-cells = <1>;
> #size-cells = <0>;
> fwcam0: fwcam@0x10 {
> @@ -270,6 +413,8 @@
> reg = <0xc0013000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <22>;
> + clocks = <&uart0_clk>, <&uart0_clk>;
> + clock-names = "apb_pclk", "uart0_clk";
> dmas = <&dmac 17 &dmac 18>;
> dma-names = "tx", "rx";
> };
> @@ -288,6 +433,8 @@
> reg = <0xc0001000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <6 7>;
> + clocks = <&mmc_pclk>;
> + clock-names = "apb_pclk";
> max-frequency = <24000000>;
> bus-width = <4>; // SD-card slot
> mmc-cap-mmc-highspeed;
> @@ -304,6 +451,8 @@
> reg = <0xc0006000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <23>;
> + clocks = <&spi_clk>, <&spi_clk>;
> + clock-names = "apb_pclk", "spi_clk";
> dmas = <&dmac 27 &dmac 28>;
> dma-names = "tx", "rx";
> #address-cells = <1>;
> diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
> index 2e1c81d..390ae5f 100644
> --- a/arch/arm/mach-u300/timer.c
> +++ b/arch/arm/mach-u300/timer.c
> @@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
> pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
>
> /* Clock the interrupt controller */
> - clk = clk_get_sys("apptimer", NULL);
> + clk = of_clk_get(np, 0);
> BUG_ON(IS_ERR(clk));
> clk_prepare_enable(clk);
> rate = clk_get_rate(clk);
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index bebd6c9..5f234d3 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +#define U300_CLK_TYPE_SLOW 0
> +#define U300_CLK_TYPE_FAST 1
> +#define U300_CLK_TYPE_REST 2
> +
> +/**
> + * struct u300_clock - defines the bits and pieces for a certain clock
> + * @type: the clock type, slow fast or rest
> + * @id: the bit in the slow/fast/rest register for this clock
> + * @hw_ctrld: whether the clock is hardware controlled
> + * @clk_val: a value to poke in the one-write enable/disable registers
> + */
> +struct u300_clock {
> + u8 type;
> + u8 id;
> + bool hw_ctrld;
> + u16 clk_val;
> +};
> +
> +struct u300_clock const __initconst u300_clk_lookup[] = {
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 3,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 4,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 5,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 6,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 8,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 9,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 10,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 12,
> + .hw_ctrld = false,
> + /* INTCON: cannot be enabled, just taken out of reset */
> + .clk_val = 0xFFFFU,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 0,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 1,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 2,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 5,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 6,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 0,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 1,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 4,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 6,
> + .hw_ctrld = true,
> + /* No clock enable register bit */
> + .clk_val = 0xFFFFU,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 7,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 8,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
> + },
> +};
> +
> +static void __init of_u300_syscon_clk_init(struct device_node *np)
> +{
> + struct clk *clk = ERR_PTR(-EINVAL);
> + const char *clk_name = np->name;
> + const char *parent_name;
> + void __iomem *res_reg;
> + void __iomem *en_reg;
> + u32 clk_type;
> + u32 clk_id;
> + int i;
> +
> + if (of_property_read_u32(np, "clock-type", &clk_type)) {
> + pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
> + __func__, clk_name);
> + return;
> + }
> + if (of_property_read_u32(np, "clock-id", &clk_id)) {
> + pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
> + __func__, clk_name);
> + return;
> + }
> + parent_name = of_clk_get_parent_name(np, 0);
> +
> + switch (clk_type) {
> + case U300_CLK_TYPE_SLOW:
> + res_reg = syscon_vbase + U300_SYSCON_RSR;
> + en_reg = syscon_vbase + U300_SYSCON_CESR;
> + break;
> + case U300_CLK_TYPE_FAST:
> + res_reg = syscon_vbase + U300_SYSCON_RFR;
> + en_reg = syscon_vbase + U300_SYSCON_CEFR;
> + break;
> + case U300_CLK_TYPE_REST:
> + res_reg = syscon_vbase + U300_SYSCON_RRR;
> + en_reg = syscon_vbase + U300_SYSCON_CERR;
> + break;
> + default:
> + pr_err("unknown clock type %x specified\n", clk_type);
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
> + const struct u300_clock *u3clk = &u300_clk_lookup[i];
> +
> + if (u3clk->type == clk_type && u3clk->id == clk_id)
> + clk = syscon_clk_register(NULL,
> + clk_name, parent_name,
> + 0, u3clk->hw_ctrld,
> + res_reg, u3clk->id,
> + en_reg, u3clk->id,
> + u3clk->clk_val);
> + }
> +
> + if (!IS_ERR(clk)) {
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +
> + /*
> + * Some few system clocks - device tree does not
> + * represent clocks without a corresponding device node.
> + * for now we add these three clocks here.
> + */
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
> + clk_register_clkdev(clk, NULL, "pl172");
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
> + clk_register_clkdev(clk, NULL, "semi");
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
> + clk_register_clkdev(clk, NULL, "intcon");
> + }
> +}
> +
> /**
> * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
> * @hw: corresponding clock hardware entry
> @@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
> .compatible = "fixed-factor-clock",
> .data = of_fixed_factor_clk_setup,
> },
> + {
> + .compatible = "stericsson,u300-syscon-clk",
> + .data = of_u300_syscon_clk_init,
> + },
> };
>
> void __init u300_clk_init(void __iomem *base)
> @@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
>
> of_clk_init(u300_clk_match);
>
> - /* Directly on the AMBA interconnect */
> - clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 3,
> - syscon_vbase + U300_SYSCON_CERR, 3,
> - U300_SYSCON_SBCER_CPU_CLK_EN);
> - clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 4,
> - syscon_vbase + U300_SYSCON_CERR, 4,
> - U300_SYSCON_SBCER_DMAC_CLK_EN);
> - clk_register_clkdev(clk, NULL, "dma");
> - clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 6,
> - syscon_vbase + U300_SYSCON_CERR, 6,
> - U300_SYSCON_SBCER_NANDIF_CLK_EN);
> - clk_register_clkdev(clk, NULL, "fsmc-nand");
> - clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 8,
> - syscon_vbase + U300_SYSCON_CERR, 8,
> - U300_SYSCON_SBCER_XGAM_CLK_EN);
> - clk_register_clkdev(clk, NULL, "xgam");
> - clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 9,
> - syscon_vbase + U300_SYSCON_CERR, 9,
> - U300_SYSCON_SBCER_SEMI_CLK_EN);
> - clk_register_clkdev(clk, NULL, "semi");
> -
> - /* AHB bridge clocks */
> - clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 10,
> - syscon_vbase + U300_SYSCON_CERR, 10,
> - U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 12,
> - syscon_vbase + U300_SYSCON_CERR, 12,
> - /* Cannot be enabled, just taken out of reset */
> - 0xFFFFU);
> - clk_register_clkdev(clk, NULL, "intcon");
> - clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 5,
> - syscon_vbase + U300_SYSCON_CERR, 5,
> - U300_SYSCON_SBCER_EMIF_CLK_EN);
> - clk_register_clkdev(clk, NULL, "pl172");
> -
> - /* FAST bridge clocks */
> - clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RFR, 0,
> - syscon_vbase + U300_SYSCON_CEFR, 0,
> - U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 1,
> - syscon_vbase + U300_SYSCON_CEFR, 1,
> - U300_SYSCON_SBCER_I2C0_CLK_EN);
> - clk_register_clkdev(clk, NULL, "stu300.0");
> - clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 2,
> - syscon_vbase + U300_SYSCON_CEFR, 2,
> - U300_SYSCON_SBCER_I2C1_CLK_EN);
> - clk_register_clkdev(clk, NULL, "stu300.1");
> - clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 5,
> - syscon_vbase + U300_SYSCON_CEFR, 5,
> - U300_SYSCON_SBCER_MMC_CLK_EN);
> - clk_register_clkdev(clk, "apb_pclk", "mmci");
> - clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 6,
> - syscon_vbase + U300_SYSCON_CEFR, 6,
> - U300_SYSCON_SBCER_SPI_CLK_EN);
> - /* The SPI has no external clock for the outward bus, uses the pclk */
> - clk_register_clkdev(clk, NULL, "pl022");
> - clk_register_clkdev(clk, "apb_pclk", "pl022");
> -
> - /* SLOW bridge clocks */
> - clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
> - syscon_vbase + U300_SYSCON_RSR, 0,
> - syscon_vbase + U300_SYSCON_CESR, 0,
> - U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 1,
> - syscon_vbase + U300_SYSCON_CESR, 1,
> - U300_SYSCON_SBCER_UART_CLK_EN);
> - /* Same clock is used for APB and outward bus */
> - clk_register_clkdev(clk, NULL, "uart0");
> - clk_register_clkdev(clk, "apb_pclk", "uart0");
> - clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 4,
> - syscon_vbase + U300_SYSCON_CESR, 4,
> - U300_SYSCON_SBCER_GPIO_CLK_EN);
> - clk_register_clkdev(clk, NULL, "u300-gpio");
> - clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 5,
> - syscon_vbase + U300_SYSCON_CESR, 6,
> - U300_SYSCON_SBCER_KEYPAD_CLK_EN);
> - clk_register_clkdev(clk, NULL, "coh901461-keypad");
> - clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RSR, 6,
> - /* No clock enable register bit */
> - NULL, 0, 0xFFFFU);
> - clk_register_clkdev(clk, NULL, "rtc-coh901331");
> - clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 7,
> - syscon_vbase + U300_SYSCON_CESR, 7,
> - U300_SYSCON_SBCER_APP_TMR_CLK_EN);
> - clk_register_clkdev(clk, NULL, "apptimer");
> - clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 8,
> - syscon_vbase + U300_SYSCON_CESR, 8,
> - U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
> - clk_register_clkdev(clk, NULL, "timer");
> -
> /* Then this special MMC/SD clock */
> clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
> clk_register_clkdev(clk, NULL, "mmci");
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT
@ 2013-05-30 19:06 ` Mike Turquette
0 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:06 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Linus Walleij (2013-05-23 10:31:27)
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This moves the slow, fast, AHB bridge and "rest" clocks on
> the U300 system controller over to registration from the
> device tree.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Mike, I'm seeking an ACK to take this patch through the
> ARM SoC tree.
Acked-by: Mike Turquette <mturquette@linaro.org>
> ---
> .../bindings/clock/ste-u300-syscon-clock.txt | 57 ++++
> arch/arm/boot/dts/ste-u300.dts | 149 ++++++++++
> arch/arm/mach-u300/timer.c | 2 +-
> drivers/clk/clk-u300.c | 320 ++++++++++++++-------
> 4 files changed, 418 insertions(+), 110 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> new file mode 100644
> index 0000000..b6a30f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -0,0 +1,57 @@
> +Clock bindings for ST-Ericsson U300 System Controller Clocks
> +
> +Bindings for the gated system controller clocks:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-clk"
> +- #clock-cells: must be <0>
> +- clock-type: specifies the type of clock:
> + 0 = slow clock
> + 1 = fast clock
> + 2 = rest/remaining clock
> +- clock-id: specifies the clock in the type range
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +The available clocks per type are as follows:
> +
> +Type: ID: Clock:
> +-------------------
> +0 0 Slow peripheral bridge clock
> +0 1 UART0 clock
> +0 4 GPIO clock
> +0 6 RTC clock
> +0 7 Application timer clock
> +0 8 Access timer clock
> +
> +1 0 Fast peripheral bridge clock
> +1 1 I2C bus 0 clock
> +1 2 I2C bus 1 clock
> +1 5 MMC interface peripheral (silicon) clock
> +1 6 SPI clock
> +
> +2 3 CPU clock
> +2 4 DMA controller clock
> +2 5 External Memory Interface (EMIF) clock
> +2 6 NAND flask interface clock
> +2 8 XGAM graphics engine clock
> +2 9 Shared External Memory Interface (SEMI) clock
> +2 10 AHB Subsystem Bridge clock
> +2 12 Interrupt controller clock
> +
> +Example:
> +
> +gpio_clk: gpio_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <4>;
> + clocks = <&slow_clk>;
> +};
> +
> +gpio: gpio at c0016000 {
> + compatible = "stericsson,gpio-coh901";
> + (...)
> + clocks = <&gpio_clk>;
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index c51a8c7..e83aafc 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -43,6 +43,49 @@
> compatible = "fixed-clock";
> clock-frequency = <13000000>;
> };
> + /* Slow bridge clocks under PLL13 */
> + slow_clk: slow_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <0>;
> + clocks = <&pll13>;
> + };
> + uart0_clk: uart0_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <1>;
> + clocks = <&slow_clk>;
> + };
> + gpio_clk: gpio_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <4>;
> + clocks = <&slow_clk>;
> + };
> + rtc_clk: rtc_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <6>;
> + clocks = <&slow_clk>;
> + };
> + apptimer_clk: app_tmr_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <7>;
> + clocks = <&slow_clk>;
> + };
> + acc_tmr_clk at 13M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <0>; /* Slow */
> + clock-id = <8>;
> + clocks = <&slow_clk>;
> + };
> pll208: pll208 at 208M {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> @@ -55,6 +98,13 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + cpu_clk at 208M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <3>;
> + clocks = <&app208>;
> + };
> app104: app_104_clk at 104M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -62,6 +112,13 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + semi_clk at 104M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <9>;
> + clocks = <&app104>;
> + };
> app52: app_52_clk at 52M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -69,6 +126,49 @@
> clock-mult = <1>;
> clocks = <&pll208>;
> };
> + /* AHB subsystem clocks */
> + ahb_clk: ahb_subsys_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <10>;
> + clocks = <&app52>;
> + };
> + intcon_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <12>;
> + clocks = <&ahb_clk>;
> + };
> + emif_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <5>;
> + clocks = <&ahb_clk>;
> + };
> + dmac_clk: dmac_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <4>;
> + clocks = <&app52>;
> + };
> + fsmc_clk: fsmc_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <6>;
> + clocks = <&app52>;
> + };
> + xgam_clk: xgam_clk at 52M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <2>; /* Rest */
> + clock-id = <8>;
> + clocks = <&app52>;
> + };
> app26: app_26_clk at 26M {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> @@ -76,6 +176,42 @@
> clock-mult = <1>;
> clocks = <&app52>;
> };
> + /* Fast bridge clocks */
> + fast_clk: fast_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <0>;
> + clocks = <&app26>;
> + };
> + i2c0_clk: i2c0_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <1>;
> + clocks = <&fast_clk>;
> + };
> + i2c1_clk: i2c1_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <2>;
> + clocks = <&fast_clk>;
> + };
> + mmc_pclk: mmc_p_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <5>;
> + clocks = <&fast_clk>;
> + };
> + spi_clk: spi_p_clk at 26M {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-clk";
> + clock-type = <1>; /* Fast */
> + clock-id = <6>;
> + clocks = <&fast_clk>;
> + };
> };
>
> timer: timer at c0014000 {
> @@ -83,6 +219,7 @@
> reg = <0xc0014000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <24 25 26 27>;
> + clocks = <&apptimer_clk>;
> };
>
> gpio: gpio at c0016000 {
> @@ -90,6 +227,7 @@
> reg = <0xc0016000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <0 1 2 18 21 22 23>;
> + clocks = <&gpio_clk>;
> interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
> "gpio4", "gpio5", "gpio6";
> interrupt-controller;
> @@ -116,6 +254,7 @@
> reg = <0xc0017000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <10>;
> + clocks = <&rtc_clk>;
> };
>
> dmac: dma-controller at c00020000 {
> @@ -125,6 +264,7 @@
> interrupts = <2>;
> #dma-cells = <1>;
> dma-channels = <40>;
> + clocks = <&dmac_clk>;
> };
>
> /* A NAND flash of 128 MiB */
> @@ -138,6 +278,7 @@
> <0x80010000 0x4000>; /* NAND Base CMD */
> reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
> nand-skip-bbtscan;
> + clocks = <&fsmc_clk>;
>
> partition at 0 {
> label = "boot records";
> @@ -158,6 +299,7 @@
> reg = <0xc0004000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <8>;
> + clocks = <&i2c0_clk>;
> #address-cells = <1>;
> #size-cells = <0>;
> ab3100: ab3100 at 0x48 {
> @@ -235,6 +377,7 @@
> reg = <0xc0005000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <9>;
> + clocks = <&i2c1_clk>;
> #address-cells = <1>;
> #size-cells = <0>;
> fwcam0: fwcam at 0x10 {
> @@ -270,6 +413,8 @@
> reg = <0xc0013000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <22>;
> + clocks = <&uart0_clk>, <&uart0_clk>;
> + clock-names = "apb_pclk", "uart0_clk";
> dmas = <&dmac 17 &dmac 18>;
> dma-names = "tx", "rx";
> };
> @@ -288,6 +433,8 @@
> reg = <0xc0001000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <6 7>;
> + clocks = <&mmc_pclk>;
> + clock-names = "apb_pclk";
> max-frequency = <24000000>;
> bus-width = <4>; // SD-card slot
> mmc-cap-mmc-highspeed;
> @@ -304,6 +451,8 @@
> reg = <0xc0006000 0x1000>;
> interrupt-parent = <&vica>;
> interrupts = <23>;
> + clocks = <&spi_clk>, <&spi_clk>;
> + clock-names = "apb_pclk", "spi_clk";
> dmas = <&dmac 27 &dmac 28>;
> dma-names = "tx", "rx";
> #address-cells = <1>;
> diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
> index 2e1c81d..390ae5f 100644
> --- a/arch/arm/mach-u300/timer.c
> +++ b/arch/arm/mach-u300/timer.c
> @@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
> pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
>
> /* Clock the interrupt controller */
> - clk = clk_get_sys("apptimer", NULL);
> + clk = of_clk_get(np, 0);
> BUG_ON(IS_ERR(clk));
> clk_prepare_enable(clk);
> rate = clk_get_rate(clk);
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index bebd6c9..5f234d3 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +#define U300_CLK_TYPE_SLOW 0
> +#define U300_CLK_TYPE_FAST 1
> +#define U300_CLK_TYPE_REST 2
> +
> +/**
> + * struct u300_clock - defines the bits and pieces for a certain clock
> + * @type: the clock type, slow fast or rest
> + * @id: the bit in the slow/fast/rest register for this clock
> + * @hw_ctrld: whether the clock is hardware controlled
> + * @clk_val: a value to poke in the one-write enable/disable registers
> + */
> +struct u300_clock {
> + u8 type;
> + u8 id;
> + bool hw_ctrld;
> + u16 clk_val;
> +};
> +
> +struct u300_clock const __initconst u300_clk_lookup[] = {
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 3,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 4,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 5,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 6,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 8,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 9,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 10,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_REST,
> + .id = 12,
> + .hw_ctrld = false,
> + /* INTCON: cannot be enabled, just taken out of reset */
> + .clk_val = 0xFFFFU,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 0,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 1,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 2,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 5,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_FAST,
> + .id = 6,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 0,
> + .hw_ctrld = true,
> + .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 1,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 4,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 6,
> + .hw_ctrld = true,
> + /* No clock enable register bit */
> + .clk_val = 0xFFFFU,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 7,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
> + },
> + {
> + .type = U300_CLK_TYPE_SLOW,
> + .id = 8,
> + .hw_ctrld = false,
> + .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
> + },
> +};
> +
> +static void __init of_u300_syscon_clk_init(struct device_node *np)
> +{
> + struct clk *clk = ERR_PTR(-EINVAL);
> + const char *clk_name = np->name;
> + const char *parent_name;
> + void __iomem *res_reg;
> + void __iomem *en_reg;
> + u32 clk_type;
> + u32 clk_id;
> + int i;
> +
> + if (of_property_read_u32(np, "clock-type", &clk_type)) {
> + pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
> + __func__, clk_name);
> + return;
> + }
> + if (of_property_read_u32(np, "clock-id", &clk_id)) {
> + pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
> + __func__, clk_name);
> + return;
> + }
> + parent_name = of_clk_get_parent_name(np, 0);
> +
> + switch (clk_type) {
> + case U300_CLK_TYPE_SLOW:
> + res_reg = syscon_vbase + U300_SYSCON_RSR;
> + en_reg = syscon_vbase + U300_SYSCON_CESR;
> + break;
> + case U300_CLK_TYPE_FAST:
> + res_reg = syscon_vbase + U300_SYSCON_RFR;
> + en_reg = syscon_vbase + U300_SYSCON_CEFR;
> + break;
> + case U300_CLK_TYPE_REST:
> + res_reg = syscon_vbase + U300_SYSCON_RRR;
> + en_reg = syscon_vbase + U300_SYSCON_CERR;
> + break;
> + default:
> + pr_err("unknown clock type %x specified\n", clk_type);
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
> + const struct u300_clock *u3clk = &u300_clk_lookup[i];
> +
> + if (u3clk->type == clk_type && u3clk->id == clk_id)
> + clk = syscon_clk_register(NULL,
> + clk_name, parent_name,
> + 0, u3clk->hw_ctrld,
> + res_reg, u3clk->id,
> + en_reg, u3clk->id,
> + u3clk->clk_val);
> + }
> +
> + if (!IS_ERR(clk)) {
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +
> + /*
> + * Some few system clocks - device tree does not
> + * represent clocks without a corresponding device node.
> + * for now we add these three clocks here.
> + */
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
> + clk_register_clkdev(clk, NULL, "pl172");
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
> + clk_register_clkdev(clk, NULL, "semi");
> + if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
> + clk_register_clkdev(clk, NULL, "intcon");
> + }
> +}
> +
> /**
> * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
> * @hw: corresponding clock hardware entry
> @@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
> .compatible = "fixed-factor-clock",
> .data = of_fixed_factor_clk_setup,
> },
> + {
> + .compatible = "stericsson,u300-syscon-clk",
> + .data = of_u300_syscon_clk_init,
> + },
> };
>
> void __init u300_clk_init(void __iomem *base)
> @@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
>
> of_clk_init(u300_clk_match);
>
> - /* Directly on the AMBA interconnect */
> - clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 3,
> - syscon_vbase + U300_SYSCON_CERR, 3,
> - U300_SYSCON_SBCER_CPU_CLK_EN);
> - clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 4,
> - syscon_vbase + U300_SYSCON_CERR, 4,
> - U300_SYSCON_SBCER_DMAC_CLK_EN);
> - clk_register_clkdev(clk, NULL, "dma");
> - clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 6,
> - syscon_vbase + U300_SYSCON_CERR, 6,
> - U300_SYSCON_SBCER_NANDIF_CLK_EN);
> - clk_register_clkdev(clk, NULL, "fsmc-nand");
> - clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 8,
> - syscon_vbase + U300_SYSCON_CERR, 8,
> - U300_SYSCON_SBCER_XGAM_CLK_EN);
> - clk_register_clkdev(clk, NULL, "xgam");
> - clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 9,
> - syscon_vbase + U300_SYSCON_CERR, 9,
> - U300_SYSCON_SBCER_SEMI_CLK_EN);
> - clk_register_clkdev(clk, NULL, "semi");
> -
> - /* AHB bridge clocks */
> - clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RRR, 10,
> - syscon_vbase + U300_SYSCON_CERR, 10,
> - U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 12,
> - syscon_vbase + U300_SYSCON_CERR, 12,
> - /* Cannot be enabled, just taken out of reset */
> - 0xFFFFU);
> - clk_register_clkdev(clk, NULL, "intcon");
> - clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RRR, 5,
> - syscon_vbase + U300_SYSCON_CERR, 5,
> - U300_SYSCON_SBCER_EMIF_CLK_EN);
> - clk_register_clkdev(clk, NULL, "pl172");
> -
> - /* FAST bridge clocks */
> - clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RFR, 0,
> - syscon_vbase + U300_SYSCON_CEFR, 0,
> - U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 1,
> - syscon_vbase + U300_SYSCON_CEFR, 1,
> - U300_SYSCON_SBCER_I2C0_CLK_EN);
> - clk_register_clkdev(clk, NULL, "stu300.0");
> - clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 2,
> - syscon_vbase + U300_SYSCON_CEFR, 2,
> - U300_SYSCON_SBCER_I2C1_CLK_EN);
> - clk_register_clkdev(clk, NULL, "stu300.1");
> - clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 5,
> - syscon_vbase + U300_SYSCON_CEFR, 5,
> - U300_SYSCON_SBCER_MMC_CLK_EN);
> - clk_register_clkdev(clk, "apb_pclk", "mmci");
> - clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RFR, 6,
> - syscon_vbase + U300_SYSCON_CEFR, 6,
> - U300_SYSCON_SBCER_SPI_CLK_EN);
> - /* The SPI has no external clock for the outward bus, uses the pclk */
> - clk_register_clkdev(clk, NULL, "pl022");
> - clk_register_clkdev(clk, "apb_pclk", "pl022");
> -
> - /* SLOW bridge clocks */
> - clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
> - syscon_vbase + U300_SYSCON_RSR, 0,
> - syscon_vbase + U300_SYSCON_CESR, 0,
> - U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
> - clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 1,
> - syscon_vbase + U300_SYSCON_CESR, 1,
> - U300_SYSCON_SBCER_UART_CLK_EN);
> - /* Same clock is used for APB and outward bus */
> - clk_register_clkdev(clk, NULL, "uart0");
> - clk_register_clkdev(clk, "apb_pclk", "uart0");
> - clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 4,
> - syscon_vbase + U300_SYSCON_CESR, 4,
> - U300_SYSCON_SBCER_GPIO_CLK_EN);
> - clk_register_clkdev(clk, NULL, "u300-gpio");
> - clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 5,
> - syscon_vbase + U300_SYSCON_CESR, 6,
> - U300_SYSCON_SBCER_KEYPAD_CLK_EN);
> - clk_register_clkdev(clk, NULL, "coh901461-keypad");
> - clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
> - syscon_vbase + U300_SYSCON_RSR, 6,
> - /* No clock enable register bit */
> - NULL, 0, 0xFFFFU);
> - clk_register_clkdev(clk, NULL, "rtc-coh901331");
> - clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 7,
> - syscon_vbase + U300_SYSCON_CESR, 7,
> - U300_SYSCON_SBCER_APP_TMR_CLK_EN);
> - clk_register_clkdev(clk, NULL, "apptimer");
> - clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
> - syscon_vbase + U300_SYSCON_RSR, 8,
> - syscon_vbase + U300_SYSCON_CESR, 8,
> - U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
> - clk_register_clkdev(clk, NULL, "timer");
> -
> /* Then this special MMC/SD clock */
> clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
> clk_register_clkdev(clk, NULL, "mmci");
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
2013-05-23 17:31 ` Linus Walleij
@ 2013-05-30 19:07 ` Mike Turquette
-1 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:07 UTC (permalink / raw)
To: Linus Walleij, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Quoting Linus Walleij (2013-05-23 10:31:28)
> From: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> This converts the last of the U300 clocks to being probed from
> the device tree.
>
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Hi Mike, I'm seeking an ACK on this to take it through the
> ARM SoC tree.
Acked-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/clock/ste-u300-syscon-clock.txt | 23 ++++++++++++++++++++++
> arch/arm/boot/dts/ste-u300.dts | 9 +++++++--
> drivers/clk/clk-u300.c | 22 ++++++++++++++++-----
> 3 files changed, 47 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> index b6a30f5..7cafcb9 100644
> --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -55,3 +55,26 @@ gpio: gpio@c0016000 {
> (...)
> clocks = <&gpio_clk>;
> };
> +
> +
> +Bindings for the MMC/SD card clock:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-mclk"
> +- #clock-cells: must be <0>
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +mmc_mclk: mmc_mclk {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-mclk";
> + clocks = <&mmc_pclk>;
> +};
> +
> +mmcsd: mmcsd@c0001000 {
> + compatible = "arm,pl18x", "arm,primecell";
> + clocks = <&mmc_pclk>, <&mmc_mclk>;
> + clock-names = "apb_pclk", "mclk";
> + (...)
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index e83aafc..d5dd243 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -205,6 +205,11 @@
> clock-id = <5>;
> clocks = <&fast_clk>;
> };
> + mmc_mclk: mmc_mclk {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-mclk";
> + clocks = <&mmc_pclk>;
> + };
> spi_clk: spi_p_clk@26M {
> #clock-cells = <0>;
> compatible = "stericsson,u300-syscon-clk";
> @@ -433,8 +438,8 @@
> reg = <0xc0001000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <6 7>;
> - clocks = <&mmc_pclk>;
> - clock-names = "apb_pclk";
> + clocks = <&mmc_pclk>, <&mmc_mclk>;
> + clock-names = "apb_pclk", "mclk";
> max-frequency = <24000000>;
> bus-width = <4>; // SD-card slot
> mmc-cap-mmc-highspeed;
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index 5f234d3..8774e05 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +static void __init of_u300_syscon_mclk_init(struct device_node *np)
> +{
> + struct clk *clk = ERR_PTR(-EINVAL);
> + const char *clk_name = np->name;
> + const char *parent_name;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + clk = mclk_clk_register(NULL, clk_name, parent_name, false);
> + if (!IS_ERR(clk))
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> static const __initconst struct of_device_id u300_clk_match[] = {
> {
> .compatible = "fixed-clock",
> @@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
> .compatible = "stericsson,u300-syscon-clk",
> .data = of_u300_syscon_clk_init,
> },
> + {
> + .compatible = "stericsson,u300-syscon-mclk",
> + .data = of_u300_syscon_mclk_init,
> + },
> };
>
> +
> void __init u300_clk_init(void __iomem *base)
> {
> u16 val;
> - struct clk *clk;
>
> syscon_vbase = base;
>
> @@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
> writew(val, syscon_vbase + U300_SYSCON_PMCR);
>
> of_clk_init(u300_clk_match);
> -
> - /* Then this special MMC/SD clock */
> - clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
> - clk_register_clkdev(clk, NULL, "mmci");
> }
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree
@ 2013-05-30 19:07 ` Mike Turquette
0 siblings, 0 replies; 22+ messages in thread
From: Mike Turquette @ 2013-05-30 19:07 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Linus Walleij (2013-05-23 10:31:28)
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This converts the last of the U300 clocks to being probed from
> the device tree.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Mike, I'm seeking an ACK on this to take it through the
> ARM SoC tree.
Acked-by: Mike Turquette <mturquette@linaro.org>
> ---
> .../bindings/clock/ste-u300-syscon-clock.txt | 23 ++++++++++++++++++++++
> arch/arm/boot/dts/ste-u300.dts | 9 +++++++--
> drivers/clk/clk-u300.c | 22 ++++++++++++++++-----
> 3 files changed, 47 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> index b6a30f5..7cafcb9 100644
> --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
> @@ -55,3 +55,26 @@ gpio: gpio at c0016000 {
> (...)
> clocks = <&gpio_clk>;
> };
> +
> +
> +Bindings for the MMC/SD card clock:
> +
> +Required properties:
> +- compatible: must be "stericsson,u300-syscon-mclk"
> +- #clock-cells: must be <0>
> +
> +Optional properties:
> +- clocks: parent clock(s)
> +
> +mmc_mclk: mmc_mclk {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-mclk";
> + clocks = <&mmc_pclk>;
> +};
> +
> +mmcsd: mmcsd at c0001000 {
> + compatible = "arm,pl18x", "arm,primecell";
> + clocks = <&mmc_pclk>, <&mmc_mclk>;
> + clock-names = "apb_pclk", "mclk";
> + (...)
> +};
> diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
> index e83aafc..d5dd243 100644
> --- a/arch/arm/boot/dts/ste-u300.dts
> +++ b/arch/arm/boot/dts/ste-u300.dts
> @@ -205,6 +205,11 @@
> clock-id = <5>;
> clocks = <&fast_clk>;
> };
> + mmc_mclk: mmc_mclk {
> + #clock-cells = <0>;
> + compatible = "stericsson,u300-syscon-mclk";
> + clocks = <&mmc_pclk>;
> + };
> spi_clk: spi_p_clk at 26M {
> #clock-cells = <0>;
> compatible = "stericsson,u300-syscon-clk";
> @@ -433,8 +438,8 @@
> reg = <0xc0001000 0x1000>;
> interrupt-parent = <&vicb>;
> interrupts = <6 7>;
> - clocks = <&mmc_pclk>;
> - clock-names = "apb_pclk";
> + clocks = <&mmc_pclk>, <&mmc_mclk>;
> + clock-names = "apb_pclk", "mclk";
> max-frequency = <24000000>;
> bus-width = <4>; // SD-card slot
> mmc-cap-mmc-highspeed;
> diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
> index 5f234d3..8774e05 100644
> --- a/drivers/clk/clk-u300.c
> +++ b/drivers/clk/clk-u300.c
> @@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name,
> return clk;
> }
>
> +static void __init of_u300_syscon_mclk_init(struct device_node *np)
> +{
> + struct clk *clk = ERR_PTR(-EINVAL);
> + const char *clk_name = np->name;
> + const char *parent_name;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + clk = mclk_clk_register(NULL, clk_name, parent_name, false);
> + if (!IS_ERR(clk))
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> static const __initconst struct of_device_id u300_clk_match[] = {
> {
> .compatible = "fixed-clock",
> @@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = {
> .compatible = "stericsson,u300-syscon-clk",
> .data = of_u300_syscon_clk_init,
> },
> + {
> + .compatible = "stericsson,u300-syscon-mclk",
> + .data = of_u300_syscon_mclk_init,
> + },
> };
>
> +
> void __init u300_clk_init(void __iomem *base)
> {
> u16 val;
> - struct clk *clk;
>
> syscon_vbase = base;
>
> @@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base)
> writew(val, syscon_vbase + U300_SYSCON_PMCR);
>
> of_clk_init(u300_clk_match);
> -
> - /* Then this special MMC/SD clock */
> - clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
> - clk_register_clkdev(clk, NULL, "mmci");
> }
> --
> 1.7.11.3
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2013-05-30 19:07 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-23 17:31 [PATCH 0/6] U300 device tree clocks Linus Walleij
2013-05-23 17:31 ` Linus Walleij
2013-05-23 17:31 ` [PATCH 2/6] ARM: u300: remove register definition file Linus Walleij
2013-05-23 17:31 ` Linus Walleij
[not found] ` <1369330288-14856-1-git-send-email-linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
2013-05-23 17:31 ` [PATCH 1/6] ARM: u300: add syscon node Linus Walleij
2013-05-23 17:31 ` Linus Walleij
2013-05-23 17:31 ` [PATCH 3/6] clk: move the U300 fixed and fixed-factor to DT Linus Walleij
2013-05-23 17:31 ` Linus Walleij
[not found] ` <1369330288-14856-4-git-send-email-linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
2013-05-30 19:00 ` Mike Turquette
2013-05-30 19:00 ` Mike Turquette
2013-05-23 17:31 ` [PATCH 4/6] i2c: stu300: do not request a specific clock name Linus Walleij
2013-05-23 17:31 ` Linus Walleij
2013-05-23 23:09 ` Wolfram Sang
2013-05-23 23:09 ` Wolfram Sang
2013-05-23 17:31 ` [PATCH 5/6] ARM: u300: move the gated system controller clocks to DT Linus Walleij
2013-05-23 17:31 ` Linus Walleij
[not found] ` <1369330288-14856-6-git-send-email-linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
2013-05-30 19:06 ` Mike Turquette
2013-05-30 19:06 ` Mike Turquette
2013-05-23 17:31 ` [PATCH 6/6] ARM: u300: convert MMC/SD clock to device tree Linus Walleij
2013-05-23 17:31 ` Linus Walleij
[not found] ` <1369330288-14856-7-git-send-email-linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
2013-05-30 19:07 ` Mike Turquette
2013-05-30 19:07 ` Mike Turquette
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