* [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro
@ 2013-05-28 8:20 liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 02/12] target-i386/helper: remove EBX macro liguang
` (10 more replies)
0 siblings, 11 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:20 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 -
target-i386/int_helper.c | 62 ++++++++++++++++++++++----------------------
target-i386/mem_helper.c | 8 +++---
target-i386/misc_helper.c | 10 +++---
target-i386/seg_helper.c | 8 +++---
target-i386/smm_helper.c | 8 +++---
target-i386/svm_helper.c | 24 ++++++++--------
7 files changed, 60 insertions(+), 62 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 058c57f..4585c0a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef EAX
-#define EAX (env->regs[R_EAX])
#undef ECX
#define ECX (env->regs[R_ECX])
#undef EDX
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index 74c7c36..16d1ed5 100644
--- a/target-i386/int_helper.c
+++ b/target-i386/int_helper.c
@@ -45,7 +45,7 @@ void helper_divb_AL(CPUX86State *env, target_ulong t0)
{
unsigned int num, den, q, r;
- num = (EAX & 0xffff);
+ num = (env->regs[R_EAX] & 0xffff);
den = (t0 & 0xff);
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -56,14 +56,14 @@ void helper_divb_AL(CPUX86State *env, target_ulong t0)
}
q &= 0xff;
r = (num % den) & 0xff;
- EAX = (EAX & ~0xffff) | (r << 8) | q;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}
void helper_idivb_AL(CPUX86State *env, target_ulong t0)
{
int num, den, q, r;
- num = (int16_t)EAX;
+ num = (int16_t)env->regs[R_EAX];
den = (int8_t)t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -74,14 +74,14 @@ void helper_idivb_AL(CPUX86State *env, target_ulong t0)
}
q &= 0xff;
r = (num % den) & 0xff;
- EAX = (EAX & ~0xffff) | (r << 8) | q;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}
void helper_divw_AX(CPUX86State *env, target_ulong t0)
{
unsigned int num, den, q, r;
- num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
+ num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16);
den = (t0 & 0xffff);
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -92,7 +92,7 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0)
}
q &= 0xffff;
r = (num % den) & 0xffff;
- EAX = (EAX & ~0xffff) | q;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
EDX = (EDX & ~0xffff) | r;
}
@@ -100,7 +100,7 @@ void helper_idivw_AX(CPUX86State *env, target_ulong t0)
{
int num, den, q, r;
- num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
+ num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16);
den = (int16_t)t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -111,7 +111,7 @@ void helper_idivw_AX(CPUX86State *env, target_ulong t0)
}
q &= 0xffff;
r = (num % den) & 0xffff;
- EAX = (EAX & ~0xffff) | q;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
EDX = (EDX & ~0xffff) | r;
}
@@ -120,7 +120,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
unsigned int den, r;
uint64_t num, q;
- num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
+ num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
den = t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -130,7 +130,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
if (q > 0xffffffff) {
raise_exception(env, EXCP00_DIVZ);
}
- EAX = (uint32_t)q;
+ env->regs[R_EAX] = (uint32_t)q;
EDX = (uint32_t)r;
}
@@ -139,7 +139,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
int den, r;
int64_t num, q;
- num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
+ num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
den = t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -149,7 +149,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
if (q != (int32_t)q) {
raise_exception(env, EXCP00_DIVZ);
}
- EAX = (uint32_t)q;
+ env->regs[R_EAX] = (uint32_t)q;
EDX = (uint32_t)r;
}
@@ -160,10 +160,10 @@ void helper_aam(CPUX86State *env, int base)
{
int al, ah;
- al = EAX & 0xff;
+ al = env->regs[R_EAX] & 0xff;
ah = al / base;
al = al % base;
- EAX = (EAX & ~0xffff) | al | (ah << 8);
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
CC_DST = al;
}
@@ -171,10 +171,10 @@ void helper_aad(CPUX86State *env, int base)
{
int al, ah;
- al = EAX & 0xff;
- ah = (EAX >> 8) & 0xff;
+ al = env->regs[R_EAX] & 0xff;
+ ah = (env->regs[R_EAX] >> 8) & 0xff;
al = ((ah * base) + al) & 0xff;
- EAX = (EAX & ~0xffff) | al;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al;
CC_DST = al;
}
@@ -186,8 +186,8 @@ void helper_aaa(CPUX86State *env)
eflags = cpu_cc_compute_all(env, CC_OP);
af = eflags & CC_A;
- al = EAX & 0xff;
- ah = (EAX >> 8) & 0xff;
+ al = env->regs[R_EAX] & 0xff;
+ ah = (env->regs[R_EAX] >> 8) & 0xff;
icarry = (al > 0xf9);
if (((al & 0x0f) > 9) || af) {
@@ -198,7 +198,7 @@ void helper_aaa(CPUX86State *env)
eflags &= ~(CC_C | CC_A);
al &= 0x0f;
}
- EAX = (EAX & ~0xffff) | al | (ah << 8);
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
CC_SRC = eflags;
}
@@ -210,8 +210,8 @@ void helper_aas(CPUX86State *env)
eflags = cpu_cc_compute_all(env, CC_OP);
af = eflags & CC_A;
- al = EAX & 0xff;
- ah = (EAX >> 8) & 0xff;
+ al = env->regs[R_EAX] & 0xff;
+ ah = (env->regs[R_EAX] >> 8) & 0xff;
icarry = (al < 6);
if (((al & 0x0f) > 9) || af) {
@@ -222,7 +222,7 @@ void helper_aas(CPUX86State *env)
eflags &= ~(CC_C | CC_A);
al &= 0x0f;
}
- EAX = (EAX & ~0xffff) | al | (ah << 8);
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
CC_SRC = eflags;
}
@@ -234,7 +234,7 @@ void helper_daa(CPUX86State *env)
eflags = cpu_cc_compute_all(env, CC_OP);
cf = eflags & CC_C;
af = eflags & CC_A;
- old_al = al = EAX & 0xff;
+ old_al = al = env->regs[R_EAX] & 0xff;
eflags = 0;
if (((al & 0x0f) > 9) || af) {
@@ -245,7 +245,7 @@ void helper_daa(CPUX86State *env)
al = (al + 0x60) & 0xff;
eflags |= CC_C;
}
- EAX = (EAX & ~0xff) | al;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
/* well, speed is not an issue here, so we compute the flags by hand */
eflags |= (al == 0) << 6; /* zf */
eflags |= parity_table[al]; /* pf */
@@ -261,7 +261,7 @@ void helper_das(CPUX86State *env)
eflags = cpu_cc_compute_all(env, CC_OP);
cf = eflags & CC_C;
af = eflags & CC_A;
- al = EAX & 0xff;
+ al = env->regs[R_EAX] & 0xff;
eflags = 0;
al1 = al;
@@ -276,7 +276,7 @@ void helper_das(CPUX86State *env)
al = (al - 0x60) & 0xff;
eflags |= CC_C;
}
- EAX = (EAX & ~0xff) | al;
+ env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
/* well, speed is not an issue here, so we compute the flags by hand */
eflags |= (al == 0) << 6; /* zf */
eflags |= parity_table[al]; /* pf */
@@ -381,12 +381,12 @@ void helper_divq_EAX(CPUX86State *env, target_ulong t0)
if (t0 == 0) {
raise_exception(env, EXCP00_DIVZ);
}
- r0 = EAX;
+ r0 = env->regs[R_EAX];
r1 = EDX;
if (div64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ);
}
- EAX = r0;
+ env->regs[R_EAX] = r0;
EDX = r1;
}
@@ -397,12 +397,12 @@ void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
if (t0 == 0) {
raise_exception(env, EXCP00_DIVZ);
}
- r0 = EAX;
+ r0 = env->regs[R_EAX];
r1 = EDX;
if (idiv64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ);
}
- EAX = r0;
+ env->regs[R_EAX] = r0;
EDX = r1;
}
#endif
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 6cf9ba0..f0f5aec 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -45,14 +45,14 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d = cpu_ldq_data(env, a0);
- if (d == (((uint64_t)EDX << 32) | (uint32_t)EAX)) {
+ if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) {
cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)EBX);
eflags |= CC_Z;
} else {
/* always do the store */
cpu_stq_data(env, a0, d);
EDX = (uint32_t)(d >> 32);
- EAX = (uint32_t)d;
+ env->regs[R_EAX] = (uint32_t)d;
eflags &= ~CC_Z;
}
CC_SRC = eflags;
@@ -70,7 +70,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d0 = cpu_ldq_data(env, a0);
d1 = cpu_ldq_data(env, a0 + 8);
- if (d0 == EAX && d1 == EDX) {
+ if (d0 == env->regs[R_EAX] && d1 == EDX) {
cpu_stq_data(env, a0, EBX);
cpu_stq_data(env, a0 + 8, ECX);
eflags |= CC_Z;
@@ -79,7 +79,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
cpu_stq_data(env, a0, d0);
cpu_stq_data(env, a0 + 8, d1);
EDX = d1;
- EAX = d0;
+ env->regs[R_EAX] = d0;
eflags &= ~CC_Z;
}
CC_SRC = eflags;
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index ec834fc..a6a787f 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -122,8 +122,8 @@ void helper_cpuid(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
- cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
- EAX = eax;
+ cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
+ env->regs[R_EAX] = eax;
EBX = ebx;
ECX = ecx;
EDX = edx;
@@ -234,7 +234,7 @@ void helper_rdtsc(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
val = cpu_get_tsc(env) + env->tsc_offset;
- EAX = (uint32_t)(val);
+ env->regs[R_EAX] = (uint32_t)(val);
EDX = (uint32_t)(val >> 32);
}
@@ -271,7 +271,7 @@ void helper_wrmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
- val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
+ val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
switch ((uint32_t)ECX) {
case MSR_IA32_SYSENTER_CS:
@@ -548,7 +548,7 @@ void helper_rdmsr(CPUX86State *env)
val = 0;
break;
}
- EAX = (uint32_t)(val);
+ env->regs[R_EAX] = (uint32_t)(val);
EDX = (uint32_t)(val >> 32);
}
#endif
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 906e4f3..719b7bb 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -324,7 +324,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
/* 32 bit */
cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), EAX);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), EBX);
@@ -340,7 +340,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
/* 16 bit */
cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), EAX);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), EBX);
@@ -396,7 +396,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
}
cpu_load_eflags(env, new_eflags, eflags_mask);
/* XXX: what to do in 16 bit case? */
- EAX = new_regs[0];
+ env->regs[R_EAX] = new_regs[0];
ECX = new_regs[1];
EDX = new_regs[2];
EBX = new_regs[3];
@@ -1175,7 +1175,7 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
if (intno == 0x0e) {
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
} else {
- qemu_log(" EAX=" TARGET_FMT_lx, EAX);
+ qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
}
qemu_log("\n");
log_cpu_state(env, CPU_DUMP_CCOP);
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index eea2fe9..1ea6107 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -82,7 +82,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ed0, env->efer);
- stq_phys(sm_state + 0x7ff8, EAX);
+ stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(sm_state + 0x7ff0, ECX);
stq_phys(sm_state + 0x7fe8, EDX);
stq_phys(sm_state + 0x7fe0, EBX);
@@ -116,7 +116,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fdc, EBX);
stl_phys(sm_state + 0x7fd8, EDX);
stl_phys(sm_state + 0x7fd4, ECX);
- stl_phys(sm_state + 0x7fd0, EAX);
+ stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
stl_phys(sm_state + 0x7fcc, env->dr[6]);
stl_phys(sm_state + 0x7fc8, env->dr[7]);
@@ -213,7 +213,7 @@ void helper_rsm(CPUX86State *env)
env->tr.limit = ldl_phys(sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
- EAX = ldq_phys(sm_state + 0x7ff8);
+ env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
ECX = ldq_phys(sm_state + 0x7ff0);
EDX = ldq_phys(sm_state + 0x7fe8);
EBX = ldq_phys(sm_state + 0x7fe0);
@@ -251,7 +251,7 @@ void helper_rsm(CPUX86State *env)
EBX = ldl_phys(sm_state + 0x7fdc);
EDX = ldl_phys(sm_state + 0x7fd8);
ECX = ldl_phys(sm_state + 0x7fd4);
- EAX = ldl_phys(sm_state + 0x7fd0);
+ env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
env->dr[6] = ldl_phys(sm_state + 0x7fcc);
env->dr[7] = ldl_phys(sm_state + 0x7fc8);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index c46a213..1243207 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -129,9 +129,9 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0);
if (aflag == 2) {
- addr = EAX;
+ addr = env->regs[R_EAX];
} else {
- addr = (uint32_t)EAX;
+ addr = (uint32_t)env->regs[R_EAX];
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmrun! " TARGET_FMT_lx "\n", addr);
@@ -172,7 +172,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
EIP + next_eip_addend);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), EAX);
+ stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
/* load the interception bitmaps so we do not need to access the
vmcb in svm mode */
@@ -251,7 +251,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
env->eip = EIP;
ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
- EAX = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
+ env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb,
@@ -341,9 +341,9 @@ void helper_vmload(CPUX86State *env, int aflag)
cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);
if (aflag == 2) {
- addr = EAX;
+ addr = env->regs[R_EAX];
} else {
- addr = (uint32_t)EAX;
+ addr = (uint32_t)env->regs[R_EAX];
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
@@ -379,9 +379,9 @@ void helper_vmsave(CPUX86State *env, int aflag)
cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);
if (aflag == 2) {
- addr = EAX;
+ addr = env->regs[R_EAX];
} else {
- addr = (uint32_t)EAX;
+ addr = (uint32_t)env->regs[R_EAX];
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
@@ -439,9 +439,9 @@ void helper_invlpga(CPUX86State *env, int aflag)
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
if (aflag == 2) {
- addr = EAX;
+ addr = env->regs[R_EAX];
} else {
- addr = (uint32_t)EAX;
+ addr = (uint32_t)env->regs[R_EAX];
}
/* XXX: could use the ASID to see if it is needed to do the
@@ -607,7 +607,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
env->eip);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), EAX);
+ stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
@@ -659,7 +659,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
- EAX = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
+ env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 02/12] target-i386/helper: remove EBX macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 03/12] target-i386/helper: remove ECX macro liguang
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/mem_helper.c | 4 ++--
target-i386/misc_helper.c | 2 +-
target-i386/seg_helper.c | 6 +++---
target-i386/smm_helper.c | 8 ++++----
5 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 4585c0a..28ff02d 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1105,8 +1105,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
#define ECX (env->regs[R_ECX])
#undef EDX
#define EDX (env->regs[R_EDX])
-#undef EBX
-#define EBX (env->regs[R_EBX])
#undef ESP
#define ESP (env->regs[R_ESP])
#undef EBP
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index f0f5aec..6370fb5 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -46,7 +46,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d = cpu_ldq_data(env, a0);
if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) {
- cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)EBX);
+ cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)env->regs[R_EBX]);
eflags |= CC_Z;
} else {
/* always do the store */
@@ -71,7 +71,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
d0 = cpu_ldq_data(env, a0);
d1 = cpu_ldq_data(env, a0 + 8);
if (d0 == env->regs[R_EAX] && d1 == EDX) {
- cpu_stq_data(env, a0, EBX);
+ cpu_stq_data(env, a0, env->regs[R_EBX]);
cpu_stq_data(env, a0 + 8, ECX);
eflags |= CC_Z;
} else {
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index a6a787f..d7be4f4 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -124,7 +124,7 @@ void helper_cpuid(CPUX86State *env)
cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
env->regs[R_EAX] = eax;
- EBX = ebx;
+ env->regs[R_EBX] = ebx;
ECX = ecx;
EDX = edx;
}
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 719b7bb..b3c087f 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -327,7 +327,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), EBX);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
@@ -343,7 +343,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), EBX);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
@@ -399,7 +399,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_EAX] = new_regs[0];
ECX = new_regs[1];
EDX = new_regs[2];
- EBX = new_regs[3];
+ env->regs[R_EBX] = new_regs[3];
ESP = new_regs[4];
EBP = new_regs[5];
ESI = new_regs[6];
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 1ea6107..28c78a5 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -85,7 +85,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(sm_state + 0x7ff0, ECX);
stq_phys(sm_state + 0x7fe8, EDX);
- stq_phys(sm_state + 0x7fe0, EBX);
+ stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, ESP);
stq_phys(sm_state + 0x7fd0, EBP);
stq_phys(sm_state + 0x7fc8, ESI);
@@ -113,7 +113,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fe8, ESI);
stl_phys(sm_state + 0x7fe4, EBP);
stl_phys(sm_state + 0x7fe0, ESP);
- stl_phys(sm_state + 0x7fdc, EBX);
+ stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, EDX);
stl_phys(sm_state + 0x7fd4, ECX);
stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
@@ -216,7 +216,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
ECX = ldq_phys(sm_state + 0x7ff0);
EDX = ldq_phys(sm_state + 0x7fe8);
- EBX = ldq_phys(sm_state + 0x7fe0);
+ env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
ESP = ldq_phys(sm_state + 0x7fd8);
EBP = ldq_phys(sm_state + 0x7fd0);
ESI = ldq_phys(sm_state + 0x7fc8);
@@ -248,7 +248,7 @@ void helper_rsm(CPUX86State *env)
ESI = ldl_phys(sm_state + 0x7fe8);
EBP = ldl_phys(sm_state + 0x7fe4);
ESP = ldl_phys(sm_state + 0x7fe0);
- EBX = ldl_phys(sm_state + 0x7fdc);
+ env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
EDX = ldl_phys(sm_state + 0x7fd8);
ECX = ldl_phys(sm_state + 0x7fd4);
env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 03/12] target-i386/helper: remove ECX macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 02/12] target-i386/helper: remove EBX macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 04/12] target-i386/helper: remove EDX macro liguang
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/mem_helper.c | 4 ++--
target-i386/misc_helper.c | 44 ++++++++++++++++++++++----------------------
target-i386/seg_helper.c | 18 +++++++++---------
target-i386/smm_helper.c | 8 ++++----
target-i386/svm_helper.c | 10 +++++-----
6 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 28ff02d..b3c6fcb 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef ECX
-#define ECX (env->regs[R_ECX])
#undef EDX
#define EDX (env->regs[R_EDX])
#undef ESP
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 6370fb5..41ac847 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -46,7 +46,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d = cpu_ldq_data(env, a0);
if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) {
- cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)env->regs[R_EBX]);
+ cpu_stq_data(env, a0, ((uint64_t)env->regs[R_ECX] << 32) | (uint32_t)env->regs[R_EBX]);
eflags |= CC_Z;
} else {
/* always do the store */
@@ -72,7 +72,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
d1 = cpu_ldq_data(env, a0 + 8);
if (d0 == env->regs[R_EAX] && d1 == EDX) {
cpu_stq_data(env, a0, env->regs[R_EBX]);
- cpu_stq_data(env, a0 + 8, ECX);
+ cpu_stq_data(env, a0 + 8, env->regs[R_ECX]);
eflags |= CC_Z;
} else {
/* always do the store */
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index d7be4f4..b0afffe 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -122,10 +122,10 @@ void helper_cpuid(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
- cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
+ cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
env->regs[R_EAX] = eax;
env->regs[R_EBX] = ebx;
- ECX = ecx;
+ env->regs[R_ECX] = ecx;
EDX = edx;
}
@@ -241,7 +241,7 @@ void helper_rdtsc(CPUX86State *env)
void helper_rdtscp(CPUX86State *env)
{
helper_rdtsc(env);
- ECX = (uint32_t)(env->tsc_aux);
+ env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
}
void helper_rdpmc(CPUX86State *env)
@@ -273,7 +273,7 @@ void helper_wrmsr(CPUX86State *env)
val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
- switch ((uint32_t)ECX) {
+ switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS:
env->sysenter_cs = val & 0xffff;
break;
@@ -350,7 +350,7 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val;
+ env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -360,14 +360,14 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val;
+ env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
break;
case MSR_MTRRfix64K_00000:
- env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -377,7 +377,7 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
break;
case MSR_MTRRdefType:
env->mtrr_deftype = val;
@@ -398,9 +398,9 @@ void helper_wrmsr(CPUX86State *env)
env->msr_ia32_misc_enable = val;
break;
default:
- if ((uint32_t)ECX >= MSR_MC0_CTL
- && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
- uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
+ if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
+ uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
if ((offset & 0x3) != 0
|| (val == 0 || val == ~(uint64_t)0)) {
env->mce_banks[offset] = val;
@@ -418,7 +418,7 @@ void helper_rdmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
- switch ((uint32_t)ECX) {
+ switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS:
val = env->sysenter_cs;
break;
@@ -480,7 +480,7 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base;
+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -490,14 +490,14 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask;
+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
break;
case MSR_MTRRfix64K_00000:
val = env->mtrr_fixed[0];
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1];
+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -507,7 +507,7 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3];
+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
break;
case MSR_MTRRdefType:
val = env->mtrr_deftype;
@@ -538,9 +538,9 @@ void helper_rdmsr(CPUX86State *env)
val = env->msr_ia32_misc_enable;
break;
default:
- if ((uint32_t)ECX >= MSR_MC0_CTL
- && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
- uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
+ if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
+ uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
val = env->mce_banks[offset];
break;
}
@@ -576,7 +576,7 @@ void helper_hlt(CPUX86State *env, int next_eip_addend)
void helper_monitor(CPUX86State *env, target_ulong ptr)
{
- if ((uint32_t)ECX != 0) {
+ if ((uint32_t)env->regs[R_ECX] != 0) {
raise_exception(env, EXCP0D_GPF);
}
/* XXX: store address? */
@@ -588,7 +588,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
CPUState *cs;
X86CPU *cpu;
- if ((uint32_t)ECX != 0) {
+ if ((uint32_t)env->regs[R_ECX] != 0) {
raise_exception(env, EXCP0D_GPF);
}
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index b3c087f..60d723a 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -325,7 +325,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
@@ -341,7 +341,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
@@ -397,7 +397,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_load_eflags(env, new_eflags, eflags_mask);
/* XXX: what to do in 16 bit case? */
env->regs[R_EAX] = new_regs[0];
- ECX = new_regs[1];
+ env->regs[R_ECX] = new_regs[1];
EDX = new_regs[2];
env->regs[R_EBX] = new_regs[3];
ESP = new_regs[4];
@@ -949,7 +949,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
if (env->hflags & HF_LMA_MASK) {
int code64;
- ECX = env->eip + next_eip_addend;
+ env->regs[R_ECX] = env->eip + next_eip_addend;
env->regs[11] = cpu_compute_eflags(env);
code64 = env->hflags & HF_CS64_MASK;
@@ -974,7 +974,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
env->eip = env->cstar;
}
} else {
- ECX = (uint32_t)(env->eip + next_eip_addend);
+ env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
cpu_x86_set_cpl(env, 0);
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
@@ -1015,14 +1015,14 @@ void helper_sysret(CPUX86State *env, int dflag)
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
DESC_L_MASK);
- env->eip = ECX;
+ env->eip = env->regs[R_ECX];
} else {
cpu_x86_load_seg_cache(env, R_CS, selector | 3,
0, 0xffffffff,
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
- env->eip = (uint32_t)ECX;
+ env->eip = (uint32_t)env->regs[R_ECX];
}
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
0, 0xffffffff,
@@ -1039,7 +1039,7 @@ void helper_sysret(CPUX86State *env, int dflag)
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
- env->eip = (uint32_t)ECX;
+ env->eip = (uint32_t)env->regs[R_ECX];
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
0, 0xffffffff,
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -2288,7 +2288,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_W_MASK | DESC_A_MASK);
}
- ESP = ECX;
+ ESP = env->regs[R_ECX];
EIP = EDX;
}
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 28c78a5..952c728 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -83,7 +83,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ed0, env->efer);
stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
- stq_phys(sm_state + 0x7ff0, ECX);
+ stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(sm_state + 0x7fe8, EDX);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, ESP);
@@ -115,7 +115,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fe0, ESP);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, EDX);
- stl_phys(sm_state + 0x7fd4, ECX);
+ stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
stl_phys(sm_state + 0x7fcc, env->dr[6]);
stl_phys(sm_state + 0x7fc8, env->dr[7]);
@@ -214,7 +214,7 @@ void helper_rsm(CPUX86State *env)
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
- ECX = ldq_phys(sm_state + 0x7ff0);
+ env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
EDX = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
ESP = ldq_phys(sm_state + 0x7fd8);
@@ -250,7 +250,7 @@ void helper_rsm(CPUX86State *env)
ESP = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
EDX = ldl_phys(sm_state + 0x7fd8);
- ECX = ldl_phys(sm_state + 0x7fd4);
+ env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
env->dr[6] = ldl_phys(sm_state + 0x7fcc);
env->dr[7] = ldl_phys(sm_state + 0x7fc8);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 1243207..b59a2ca 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -489,18 +489,18 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
control.msrpm_base_pa));
uint32_t t0, t1;
- switch ((uint32_t)ECX) {
+ switch ((uint32_t)env->regs[R_ECX]) {
case 0 ... 0x1fff:
- t0 = (ECX * 2) % 8;
- t1 = (ECX * 2) / 8;
+ t0 = (env->regs[R_ECX] * 2) % 8;
+ t1 = (env->regs[R_ECX] * 2) / 8;
break;
case 0xc0000000 ... 0xc0001fff:
- t0 = (8192 + ECX - 0xc0000000) * 2;
+ t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2;
t1 = (t0 / 8);
t0 %= 8;
break;
case 0xc0010000 ... 0xc0011fff:
- t0 = (16384 + ECX - 0xc0010000) * 2;
+ t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2;
t1 = (t0 / 8);
t0 %= 8;
break;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 04/12] target-i386/helper: remove EDX macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 02/12] target-i386/helper: remove EBX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 03/12] target-i386/helper: remove ECX macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 05/12] target-i386/helper: remove EBP macro liguang
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/int_helper.c | 24 ++++++++++++------------
target-i386/mem_helper.c | 8 ++++----
target-i386/misc_helper.c | 8 ++++----
target-i386/seg_helper.c | 8 ++++----
target-i386/smm_helper.c | 8 ++++----
6 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index b3c6fcb..ebc5abd 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef EDX
-#define EDX (env->regs[R_EDX])
#undef ESP
#define ESP (env->regs[R_ESP])
#undef EBP
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index 16d1ed5..0555318 100644
--- a/target-i386/int_helper.c
+++ b/target-i386/int_helper.c
@@ -81,7 +81,7 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0)
{
unsigned int num, den, q, r;
- num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16);
+ num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
den = (t0 & 0xffff);
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -93,14 +93,14 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0)
q &= 0xffff;
r = (num % den) & 0xffff;
env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
- EDX = (EDX & ~0xffff) | r;
+ env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}
void helper_idivw_AX(CPUX86State *env, target_ulong t0)
{
int num, den, q, r;
- num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16);
+ num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
den = (int16_t)t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -112,7 +112,7 @@ void helper_idivw_AX(CPUX86State *env, target_ulong t0)
q &= 0xffff;
r = (num % den) & 0xffff;
env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
- EDX = (EDX & ~0xffff) | r;
+ env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}
void helper_divl_EAX(CPUX86State *env, target_ulong t0)
@@ -120,7 +120,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
unsigned int den, r;
uint64_t num, q;
- num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
+ num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -131,7 +131,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ);
}
env->regs[R_EAX] = (uint32_t)q;
- EDX = (uint32_t)r;
+ env->regs[R_EDX] = (uint32_t)r;
}
void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
@@ -139,7 +139,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
int den, r;
int64_t num, q;
- num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
+ num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0;
if (den == 0) {
raise_exception(env, EXCP00_DIVZ);
@@ -150,7 +150,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ);
}
env->regs[R_EAX] = (uint32_t)q;
- EDX = (uint32_t)r;
+ env->regs[R_EDX] = (uint32_t)r;
}
/* bcd */
@@ -382,12 +382,12 @@ void helper_divq_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ);
}
r0 = env->regs[R_EAX];
- r1 = EDX;
+ r1 = env->regs[R_EDX];
if (div64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ);
}
env->regs[R_EAX] = r0;
- EDX = r1;
+ env->regs[R_EDX] = r1;
}
void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
@@ -398,12 +398,12 @@ void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ);
}
r0 = env->regs[R_EAX];
- r1 = EDX;
+ r1 = env->regs[R_EDX];
if (idiv64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ);
}
env->regs[R_EAX] = r0;
- EDX = r1;
+ env->regs[R_EDX] = r1;
}
#endif
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 41ac847..319a219 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -45,13 +45,13 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d = cpu_ldq_data(env, a0);
- if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) {
+ if (d == (((uint64_t)env->regs[R_EDX] << 32) | (uint32_t)env->regs[R_EAX])) {
cpu_stq_data(env, a0, ((uint64_t)env->regs[R_ECX] << 32) | (uint32_t)env->regs[R_EBX]);
eflags |= CC_Z;
} else {
/* always do the store */
cpu_stq_data(env, a0, d);
- EDX = (uint32_t)(d >> 32);
+ env->regs[R_EDX] = (uint32_t)(d >> 32);
env->regs[R_EAX] = (uint32_t)d;
eflags &= ~CC_Z;
}
@@ -70,7 +70,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP);
d0 = cpu_ldq_data(env, a0);
d1 = cpu_ldq_data(env, a0 + 8);
- if (d0 == env->regs[R_EAX] && d1 == EDX) {
+ if (d0 == env->regs[R_EAX] && d1 == env->regs[R_EDX]) {
cpu_stq_data(env, a0, env->regs[R_EBX]);
cpu_stq_data(env, a0 + 8, env->regs[R_ECX]);
eflags |= CC_Z;
@@ -78,7 +78,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
/* always do the store */
cpu_stq_data(env, a0, d0);
cpu_stq_data(env, a0 + 8, d1);
- EDX = d1;
+ env->regs[R_EDX] = d1;
env->regs[R_EAX] = d0;
eflags &= ~CC_Z;
}
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index b0afffe..380e54e 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -126,7 +126,7 @@ void helper_cpuid(CPUX86State *env)
env->regs[R_EAX] = eax;
env->regs[R_EBX] = ebx;
env->regs[R_ECX] = ecx;
- EDX = edx;
+ env->regs[R_EDX] = edx;
}
#if defined(CONFIG_USER_ONLY)
@@ -235,7 +235,7 @@ void helper_rdtsc(CPUX86State *env)
val = cpu_get_tsc(env) + env->tsc_offset;
env->regs[R_EAX] = (uint32_t)(val);
- EDX = (uint32_t)(val >> 32);
+ env->regs[R_EDX] = (uint32_t)(val >> 32);
}
void helper_rdtscp(CPUX86State *env)
@@ -271,7 +271,7 @@ void helper_wrmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
- val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32);
+ val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS:
@@ -549,7 +549,7 @@ void helper_rdmsr(CPUX86State *env)
break;
}
env->regs[R_EAX] = (uint32_t)(val);
- EDX = (uint32_t)(val >> 32);
+ env->regs[R_EDX] = (uint32_t)(val >> 32);
}
#endif
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 60d723a..fc67f52 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -326,7 +326,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
@@ -342,7 +342,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
@@ -398,7 +398,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
/* XXX: what to do in 16 bit case? */
env->regs[R_EAX] = new_regs[0];
env->regs[R_ECX] = new_regs[1];
- EDX = new_regs[2];
+ env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3];
ESP = new_regs[4];
EBP = new_regs[5];
@@ -2289,7 +2289,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_W_MASK | DESC_A_MASK);
}
ESP = env->regs[R_ECX];
- EIP = EDX;
+ EIP = env->regs[R_EDX];
}
target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 952c728..5bc6802 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -84,7 +84,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
- stq_phys(sm_state + 0x7fe8, EDX);
+ stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, ESP);
stq_phys(sm_state + 0x7fd0, EBP);
@@ -114,7 +114,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fe4, EBP);
stl_phys(sm_state + 0x7fe0, ESP);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
- stl_phys(sm_state + 0x7fd8, EDX);
+ stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
stl_phys(sm_state + 0x7fcc, env->dr[6]);
@@ -215,7 +215,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
- EDX = ldq_phys(sm_state + 0x7fe8);
+ env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
ESP = ldq_phys(sm_state + 0x7fd8);
EBP = ldq_phys(sm_state + 0x7fd0);
@@ -249,7 +249,7 @@ void helper_rsm(CPUX86State *env)
EBP = ldl_phys(sm_state + 0x7fe4);
ESP = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
- EDX = ldl_phys(sm_state + 0x7fd8);
+ env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
env->dr[6] = ldl_phys(sm_state + 0x7fcc);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 05/12] target-i386/helper: remove EBP macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (2 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 04/12] target-i386/helper: remove EDX macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 06/12] target-i386/helper: remove ESP macro liguang
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/seg_helper.c | 10 +++++-----
target-i386/smm_helper.c | 8 ++++----
3 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ebc5abd..fc0cf65 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1103,8 +1103,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
#undef ESP
#define ESP (env->regs[R_ESP])
-#undef EBP
-#define EBP (env->regs[R_EBP])
#undef ESI
#define ESI (env->regs[R_ESI])
#undef EDI
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index fc67f52..56db00f 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -329,7 +329,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
for (i = 0; i < 6; i++) {
@@ -345,7 +345,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
for (i = 0; i < 4; i++) {
@@ -401,7 +401,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3];
ESP = new_regs[4];
- EBP = new_regs[5];
+ env->regs[R_EBP] = new_regs[5];
ESI = new_regs[6];
EDI = new_regs[7];
if (new_eflags & VM_MASK) {
@@ -1272,7 +1272,7 @@ void helper_enter_level(CPUX86State *env, int level, int data32,
esp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
- ebp = EBP;
+ ebp = env->regs[R_EBP];
esp = ESP;
if (data32) {
/* 32 bit */
@@ -1305,7 +1305,7 @@ void helper_enter64_level(CPUX86State *env, int level, int data64,
{
target_ulong esp, ebp;
- ebp = EBP;
+ ebp = env->regs[R_EBP];
esp = ESP;
if (data64) {
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 5bc6802..4bd73eb 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -87,7 +87,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, ESP);
- stq_phys(sm_state + 0x7fd0, EBP);
+ stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(sm_state + 0x7fc8, ESI);
stq_phys(sm_state + 0x7fc0, EDI);
for (i = 8; i < 16; i++) {
@@ -111,7 +111,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7ff0, env->eip);
stl_phys(sm_state + 0x7fec, EDI);
stl_phys(sm_state + 0x7fe8, ESI);
- stl_phys(sm_state + 0x7fe4, EBP);
+ stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
stl_phys(sm_state + 0x7fe0, ESP);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
@@ -218,7 +218,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
ESP = ldq_phys(sm_state + 0x7fd8);
- EBP = ldq_phys(sm_state + 0x7fd0);
+ env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
ESI = ldq_phys(sm_state + 0x7fc8);
EDI = ldq_phys(sm_state + 0x7fc0);
for (i = 8; i < 16; i++) {
@@ -246,7 +246,7 @@ void helper_rsm(CPUX86State *env)
env->eip = ldl_phys(sm_state + 0x7ff0);
EDI = ldl_phys(sm_state + 0x7fec);
ESI = ldl_phys(sm_state + 0x7fe8);
- EBP = ldl_phys(sm_state + 0x7fe4);
+ env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
ESP = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 06/12] target-i386/helper: remove ESP macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (3 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 05/12] target-i386/helper: remove EBP macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 07/12] target-i386/helper: remove ESI macro liguang
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 -
target-i386/seg_helper.c | 90 +++++++++++++++++++++++----------------------
target-i386/smm_helper.c | 8 ++--
target-i386/svm_helper.c | 8 ++--
4 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index fc0cf65..6b058bb 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef ESP
-#define ESP (env->regs[R_ESP])
#undef ESI
#define ESI (env->regs[R_ESI])
#undef EDI
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 56db00f..0c4b3d8 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -328,7 +328,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
@@ -344,7 +344,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
@@ -400,7 +400,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_ECX] = new_regs[1];
env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3];
- ESP = new_regs[4];
+ env->regs[R_ESP] = new_regs[4];
env->regs[R_EBP] = new_regs[5];
ESI = new_regs[6];
EDI = new_regs[7];
@@ -502,20 +502,22 @@ static int exception_has_error_code(int intno)
}
#ifdef TARGET_X86_64
-#define SET_ESP(val, sp_mask) \
- do { \
- if ((sp_mask) == 0xffff) { \
- ESP = (ESP & ~0xffff) | ((val) & 0xffff); \
- } else if ((sp_mask) == 0xffffffffLL) { \
- ESP = (uint32_t)(val); \
- } else { \
- ESP = (val); \
- } \
+#define SET_ESP(val, sp_mask) \
+ do { \
+ if ((sp_mask) == 0xffff) { \
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
+ ((val) & 0xffff); \
+ } else if ((sp_mask) == 0xffffffffLL) { \
+ env->regs[R_ESP] = (uint32_t)(val); \
+ } else { \
+ env->regs[R_ESP] = (val); \
+ } \
} while (0)
#else
-#define SET_ESP(val, sp_mask) \
- do { \
- ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \
+#define SET_ESP(val, sp_mask) \
+ do { \
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
+ ((val) & (sp_mask)); \
} while (0)
#endif
@@ -598,7 +600,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
} else {
mask = 0xffff;
}
- esp = (ESP - (2 << shift)) & mask;
+ esp = (env->regs[R_ESP] - (2 << shift)) & mask;
ssp = env->segs[R_SS].base + esp;
if (shift) {
cpu_stl_kernel(env, ssp, error_code);
@@ -680,7 +682,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
new_stack = 0;
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
- esp = ESP;
+ esp = env->regs[R_ESP];
dpl = cpl;
} else {
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
@@ -709,7 +711,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
}
PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
- PUSHL(ssp, esp, sp_mask, ESP);
+ PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
}
PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
@@ -726,7 +728,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
}
PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
- PUSHW(ssp, esp, sp_mask, ESP);
+ PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
}
PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
@@ -888,7 +890,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
if (ist != 0) {
esp = get_rsp_from_tss(env, ist + 3);
} else {
- esp = ESP;
+ esp = env->regs[R_ESP];
}
esp &= ~0xfLL; /* align stack */
dpl = cpl;
@@ -899,7 +901,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
}
PUSHQ(esp, env->segs[R_SS].selector);
- PUSHQ(esp, ESP);
+ PUSHQ(esp, env->regs[R_ESP]);
PUSHQ(esp, cpu_compute_eflags(env));
PUSHQ(esp, env->segs[R_CS].selector);
PUSHQ(esp, old_eip);
@@ -911,7 +913,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
ss = 0 | dpl;
cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
}
- ESP = esp;
+ env->regs[R_ESP] = esp;
selector = (selector & ~3) | dpl;
cpu_x86_load_seg_cache(env, R_CS, selector,
@@ -1069,7 +1071,7 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
ptr = dt->base + intno * 4;
offset = cpu_lduw_kernel(env, ptr);
selector = cpu_lduw_kernel(env, ptr + 2);
- esp = ESP;
+ esp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
if (is_int) {
old_eip = next_eip;
@@ -1083,7 +1085,7 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
PUSHW(ssp, esp, 0xffff, old_eip);
/* update processor state */
- ESP = (ESP & ~0xffff) | (esp & 0xffff);
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
env->eip = offset;
env->segs[R_CS].selector = selector;
env->segs[R_CS].base = (selector << 4);
@@ -1171,7 +1173,7 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
env->hflags & HF_CPL_MASK,
env->segs[R_CS].selector, EIP,
(int)env->segs[R_CS].base + EIP,
- env->segs[R_SS].selector, ESP);
+ env->segs[R_SS].selector, env->regs[R_ESP]);
if (intno == 0x0e) {
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
} else {
@@ -1273,7 +1275,7 @@ void helper_enter_level(CPUX86State *env, int level, int data32,
esp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
ebp = env->regs[R_EBP];
- esp = ESP;
+ esp = env->regs[R_ESP];
if (data32) {
/* 32 bit */
esp -= 4;
@@ -1306,7 +1308,7 @@ void helper_enter64_level(CPUX86State *env, int level, int data64,
target_ulong esp, ebp;
ebp = env->regs[R_EBP];
- esp = ESP;
+ esp = env->regs[R_ESP];
if (data64) {
/* 64 bit */
@@ -1653,7 +1655,7 @@ void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
target_ulong ssp;
new_eip = new_eip1;
- esp = ESP;
+ esp = env->regs[R_ESP];
esp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
if (shift) {
@@ -1721,11 +1723,11 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
target_ulong rsp;
/* 64 bit case */
- rsp = ESP;
+ rsp = env->regs[R_ESP];
PUSHQ(rsp, env->segs[R_CS].selector);
PUSHQ(rsp, next_eip);
/* from this point, not restartable */
- ESP = rsp;
+ env->regs[R_ESP] = rsp;
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
get_seg_base(e1, e2),
get_seg_limit(e1, e2), e2);
@@ -1733,7 +1735,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
} else
#endif
{
- sp = ESP;
+ sp = env->regs[R_ESP];
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
if (shift) {
@@ -1809,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */
get_ss_esp_from_tss(env, &ss, &sp, dpl);
- LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
+ LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
"\n",
- ss, sp, param_count, ESP);
+ ss, sp, param_count, env->regs[R_ESP]);
if ((ss & 0xfffc) == 0) {
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
}
@@ -1843,17 +1845,17 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
ssp = get_seg_base(ss_e1, ss_e2);
if (shift) {
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
- PUSHL(ssp, sp, sp_mask, ESP);
+ PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
+ val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
old_sp_mask));
PUSHL(ssp, sp, sp_mask, val);
}
} else {
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
- PUSHW(ssp, sp, sp_mask, ESP);
+ PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
+ val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
old_sp_mask));
PUSHW(ssp, sp, sp_mask, val);
}
@@ -1861,7 +1863,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
new_stack = 1;
} else {
/* to same privilege */
- sp = ESP;
+ sp = env->regs[R_ESP];
sp_mask = get_sp_mask(env->segs[R_SS].flags);
ssp = env->segs[R_SS].base;
/* push_size = (4 << shift); */
@@ -1905,7 +1907,7 @@ void helper_iret_real(CPUX86State *env, int shift)
int eflags_mask;
sp_mask = 0xffff; /* XXXX: use SS segment size? */
- sp = ESP;
+ sp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
if (shift == 1) {
/* 32 bits */
@@ -1919,7 +1921,7 @@ void helper_iret_real(CPUX86State *env, int shift)
POPW(ssp, sp, sp_mask, new_cs);
POPW(ssp, sp, sp_mask, new_eflags);
}
- ESP = (ESP & ~sp_mask) | (sp & sp_mask);
+ env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
env->segs[R_CS].selector = new_cs;
env->segs[R_CS].base = (new_cs << 4);
env->eip = new_eip;
@@ -1978,7 +1980,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
{
sp_mask = get_sp_mask(env->segs[R_SS].flags);
}
- sp = ESP;
+ sp = env->regs[R_ESP];
ssp = env->segs[R_SS].base;
new_eflags = 0; /* avoid warning */
#ifdef TARGET_X86_64
@@ -2179,7 +2181,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
load_seg_vm(env, R_GS, new_gs & 0xffff);
env->eip = new_eip & 0xffff;
- ESP = new_esp;
+ env->regs[R_ESP] = new_esp;
}
void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
@@ -2248,7 +2250,7 @@ void helper_sysenter(CPUX86State *env)
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_W_MASK | DESC_A_MASK);
- ESP = env->sysenter_esp;
+ env->regs[R_ESP] = env->sysenter_esp;
EIP = env->sysenter_eip;
}
@@ -2288,7 +2290,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
DESC_W_MASK | DESC_A_MASK);
}
- ESP = env->regs[R_ECX];
+ env->regs[R_ESP] = env->regs[R_ECX];
EIP = env->regs[R_EDX];
}
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 4bd73eb..50c5d99 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -86,7 +86,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
- stq_phys(sm_state + 0x7fd8, ESP);
+ stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(sm_state + 0x7fc8, ESI);
stq_phys(sm_state + 0x7fc0, EDI);
@@ -112,7 +112,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fec, EDI);
stl_phys(sm_state + 0x7fe8, ESI);
stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
- stl_phys(sm_state + 0x7fe0, ESP);
+ stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
@@ -217,7 +217,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
- ESP = ldq_phys(sm_state + 0x7fd8);
+ env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
ESI = ldq_phys(sm_state + 0x7fc8);
EDI = ldq_phys(sm_state + 0x7fc0);
@@ -247,7 +247,7 @@ void helper_rsm(CPUX86State *env)
EDI = ldl_phys(sm_state + 0x7fec);
ESI = ldl_phys(sm_state + 0x7fe8);
env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
- ESP = ldl_phys(sm_state + 0x7fe0);
+ env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index b59a2ca..5706026 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -171,7 +171,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
EIP + next_eip_addend);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
+ stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
/* load the interception bitmaps so we do not need to access the
@@ -250,7 +250,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
env->eip = EIP;
- ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
+ env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
@@ -606,7 +606,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
cpu_compute_eflags(env));
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
env->eip);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
+ stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
@@ -658,7 +658,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
R_DS);
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
- ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
+ env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 07/12] target-i386/helper: remove ESI macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (4 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 06/12] target-i386/helper: remove ESP macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 08/12] target-i386/helper: remove EDI macro liguang
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/seg_helper.c | 6 +++---
target-i386/smm_helper.c | 8 ++++----
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 6b058bb..e287290 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef ESI
-#define ESI (env->regs[R_ESI])
#undef EDI
#define EDI (env->regs[R_EDI])
#undef EIP
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 0c4b3d8..0e02eda 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -330,7 +330,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
for (i = 0; i < 6; i++) {
cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
@@ -346,7 +346,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
for (i = 0; i < 4; i++) {
cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
@@ -402,7 +402,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_EBX] = new_regs[3];
env->regs[R_ESP] = new_regs[4];
env->regs[R_EBP] = new_regs[5];
- ESI = new_regs[6];
+ env->regs[R_ESI] = new_regs[6];
EDI = new_regs[7];
if (new_eflags & VM_MASK) {
for (i = 0; i < 6; i++) {
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 50c5d99..d051f03 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -88,7 +88,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
- stq_phys(sm_state + 0x7fc8, ESI);
+ stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
stq_phys(sm_state + 0x7fc0, EDI);
for (i = 8; i < 16; i++) {
stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
@@ -110,7 +110,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
stl_phys(sm_state + 0x7ff0, env->eip);
stl_phys(sm_state + 0x7fec, EDI);
- stl_phys(sm_state + 0x7fe8, ESI);
+ stl_phys(sm_state + 0x7fe8, env->regs[R_ESI]);
stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
@@ -219,7 +219,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
- ESI = ldq_phys(sm_state + 0x7fc8);
+ env->regs[R_ESI] = ldq_phys(sm_state + 0x7fc8);
EDI = ldq_phys(sm_state + 0x7fc0);
for (i = 8; i < 16; i++) {
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
@@ -245,7 +245,7 @@ void helper_rsm(CPUX86State *env)
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
env->eip = ldl_phys(sm_state + 0x7ff0);
EDI = ldl_phys(sm_state + 0x7fec);
- ESI = ldl_phys(sm_state + 0x7fe8);
+ env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 08/12] target-i386/helper: remove EDI macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (5 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 07/12] target-i386/helper: remove ESI macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 09/12] target-i386/helper: remove EIP macro liguang
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/seg_helper.c | 6 +++---
target-i386/smm_helper.c | 8 ++++----
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index e287290..585776a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef EDI
-#define EDI (env->regs[R_EDI])
#undef EIP
#define EIP (env->eip)
#define DF (env->df)
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 0e02eda..8b2766d 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -331,7 +331,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]);
- cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
+ cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]);
for (i = 0; i < 6; i++) {
cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
env->segs[i].selector);
@@ -347,7 +347,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]);
- cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
+ cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]);
for (i = 0; i < 4; i++) {
cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
env->segs[i].selector);
@@ -403,7 +403,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
env->regs[R_ESP] = new_regs[4];
env->regs[R_EBP] = new_regs[5];
env->regs[R_ESI] = new_regs[6];
- EDI = new_regs[7];
+ env->regs[R_EDI] = new_regs[7];
if (new_eflags & VM_MASK) {
for (i = 0; i < 6; i++) {
load_seg_vm(env, i, new_segs[i]);
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index d051f03..2489573 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -89,7 +89,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
- stq_phys(sm_state + 0x7fc0, EDI);
+ stq_phys(sm_state + 0x7fc0, env->regs[R_EDI]);
for (i = 8; i < 16; i++) {
stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
@@ -109,7 +109,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7ff8, env->cr[3]);
stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
stl_phys(sm_state + 0x7ff0, env->eip);
- stl_phys(sm_state + 0x7fec, EDI);
+ stl_phys(sm_state + 0x7fec, env->regs[R_EDI]);
stl_phys(sm_state + 0x7fe8, env->regs[R_ESI]);
stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
@@ -220,7 +220,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
env->regs[R_ESI] = ldq_phys(sm_state + 0x7fc8);
- EDI = ldq_phys(sm_state + 0x7fc0);
+ env->regs[R_EDI] = ldq_phys(sm_state + 0x7fc0);
for (i = 8; i < 16; i++) {
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
}
@@ -244,7 +244,7 @@ void helper_rsm(CPUX86State *env)
cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
env->eip = ldl_phys(sm_state + 0x7ff0);
- EDI = ldl_phys(sm_state + 0x7fec);
+ env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec);
env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 09/12] target-i386/helper: remove EIP macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (6 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 08/12] target-i386/helper: remove EDI macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 10/12] target-i386/helper: remove DF macro liguang
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/cpu.h | 2 --
target-i386/excp_helper.c | 2 +-
target-i386/misc_helper.c | 4 ++--
target-i386/seg_helper.c | 24 ++++++++++++------------
target-i386/svm_helper.c | 16 ++++++++--------
5 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 585776a..b909f73 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#undef EIP
-#define EIP (env->eip)
#define DF (env->df)
#define CC_DST (env->cc_dst)
diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
index 179ea82..5319aef 100644
--- a/target-i386/excp_helper.c
+++ b/target-i386/excp_helper.c
@@ -87,7 +87,7 @@ static int check_exception(CPUX86State *env, int intno, int *error_code)
/*
* Signal an interruption. It is executed in the main CPU loop.
* is_int is TRUE if coming from the int instruction. next_eip is the
- * EIP value AFTER the interrupt instruction. It is only relevant if
+ * env->eip value AFTER the interrupt instruction. It is only relevant if
* is_int is TRUE.
*/
static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 380e54e..4ee618d 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -569,7 +569,7 @@ void helper_hlt(CPUX86State *env, int next_eip_addend)
X86CPU *cpu = x86_env_get_cpu(env);
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
- EIP += next_eip_addend;
+ env->eip += next_eip_addend;
do_hlt(cpu);
}
@@ -592,7 +592,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
raise_exception(env, EXCP0D_GPF);
}
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
- EIP += next_eip_addend;
+ env->eip += next_eip_addend;
cpu = x86_env_get_cpu(env);
cs = CPU(cpu);
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 8b2766d..939d7dc 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -457,7 +457,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
tss_load_seg(env, R_GS, new_segs[R_GS]);
}
- /* check that EIP is in the CS segment limits */
+ /* check that env->eip is in the CS segment limits */
if (new_eip > env->segs[R_CS].limit) {
/* XXX: different exception if CALL? */
raise_exception_err(env, EXCP0D_GPF, 0);
@@ -1122,7 +1122,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
exiting the emulation with the suitable exception and error
code */
if (is_int) {
- EIP = next_eip;
+ env->eip = next_eip;
}
}
@@ -1157,7 +1157,7 @@ static void handle_even_inj(CPUX86State *env, int intno, int is_int,
/*
* Begin execution of an interruption. is_int is TRUE if coming from
- * the int instruction. next_eip is the EIP value AFTER the interrupt
+ * the int instruction. next_eip is the env->eip value AFTER the interrupt
* instruction. It is only relevant if is_int is TRUE.
*/
static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
@@ -1171,8 +1171,8 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
" pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
count, intno, error_code, is_int,
env->hflags & HF_CPL_MASK,
- env->segs[R_CS].selector, EIP,
- (int)env->segs[R_CS].base + EIP,
+ env->segs[R_CS].selector, env->eip,
+ (int)env->segs[R_CS].base + env->eip,
env->segs[R_SS].selector, env->regs[R_ESP]);
if (intno == 0x0e) {
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
@@ -1584,7 +1584,7 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
}
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
get_seg_base(e1, e2), limit, e2);
- EIP = new_eip;
+ env->eip = new_eip;
} else {
/* jump to call or task gate */
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
@@ -1637,7 +1637,7 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
}
cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
get_seg_base(e1, e2), limit, e2);
- EIP = new_eip;
+ env->eip = new_eip;
break;
default:
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
@@ -1731,7 +1731,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
get_seg_base(e1, e2),
get_seg_limit(e1, e2), e2);
- EIP = new_eip;
+ env->eip = new_eip;
} else
#endif
{
@@ -1754,7 +1754,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
SET_ESP(sp, sp_mask);
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
get_seg_base(e1, e2), limit, e2);
- EIP = new_eip;
+ env->eip = new_eip;
}
} else {
/* check gate type */
@@ -1895,7 +1895,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
e2);
cpu_x86_set_cpl(env, dpl);
SET_ESP(sp, sp_mask);
- EIP = offset;
+ env->eip = offset;
}
}
@@ -2251,7 +2251,7 @@ void helper_sysenter(CPUX86State *env)
DESC_S_MASK |
DESC_W_MASK | DESC_A_MASK);
env->regs[R_ESP] = env->sysenter_esp;
- EIP = env->sysenter_eip;
+ env->eip = env->sysenter_eip;
}
void helper_sysexit(CPUX86State *env, int dflag)
@@ -2291,7 +2291,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_W_MASK | DESC_A_MASK);
}
env->regs[R_ESP] = env->regs[R_ECX];
- EIP = env->regs[R_EDX];
+ env->eip = env->regs[R_EDX];
}
target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 5706026..649be02 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -170,7 +170,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
&env->segs[R_DS]);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
- EIP + next_eip_addend);
+ env->eip + next_eip_addend);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
@@ -248,8 +248,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
R_DS);
- EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
- env->eip = EIP;
+ env->eip = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
+ env->eip = env->eip;
env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
@@ -302,7 +302,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->exception_index = EXCP02_NMI;
env->error_code = event_inj_err;
env->exception_is_int = 0;
- env->exception_next_eip = EIP;
+ env->exception_next_eip = env->eip;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
cpu_loop_exit(env);
break;
@@ -318,7 +318,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->exception_index = vector;
env->error_code = event_inj_err;
env->exception_is_int = 1;
- env->exception_next_eip = EIP;
+ env->exception_next_eip = env->eip;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
cpu_loop_exit(env);
break;
@@ -539,7 +539,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
if (lduw_phys(addr + port / 8) & (mask << (port & 7))) {
- /* next EIP */
+ /* next env->eip */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
env->eip + next_eip_addend);
helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16));
@@ -558,7 +558,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
exit_code, exit_info_1,
ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
control.exit_info_2)),
- EIP);
+ env->eip);
if (env->hflags & HF_INHIBIT_IRQ_MASK) {
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state),
@@ -657,7 +657,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
R_DS);
- EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
+ env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 10/12] target-i386/helper: remove DF macro
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (7 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 09/12] target-i386/helper: remove EIP macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 11/12] target-i386/helper: remove redundant env->eip assignment liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 12/12] target-i386: fix over 80 chars warnings liguang
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
cpu-exec.c | 4 ++--
target-i386/cc_helper.c | 2 +-
target-i386/cpu.h | 6 ++----
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 31c089d..ec46380 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -230,7 +230,7 @@ int cpu_exec(CPUArchState *env)
#if defined(TARGET_I386)
/* put eflags in CPU temporary format */
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- DF = 1 - (2 * ((env->eflags >> 10) & 1));
+ env->df = 1 - (2 * ((env->eflags >> 10) & 1));
CC_OP = CC_OP_EFLAGS;
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_SPARC)
@@ -681,7 +681,7 @@ int cpu_exec(CPUArchState *env)
#if defined(TARGET_I386)
/* restore flags in standard format */
env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
- | (DF & DF_MASK);
+ | (env->df & DF_MASK);
#elif defined(TARGET_ARM)
/* XXX: Save/restore host fpu exception state?. */
#elif defined(TARGET_UNICORE32)
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index 9daa1a0..ee04092 100644
--- a/target-i386/cc_helper.c
+++ b/target-i386/cc_helper.c
@@ -331,7 +331,7 @@ target_ulong helper_read_eflags(CPUX86State *env)
uint32_t eflags;
eflags = cpu_cc_compute_all(env, CC_OP);
- eflags |= (DF & DF_MASK);
+ eflags |= (env->df & DF_MASK);
eflags |= env->eflags & ~(VM_MASK | RF_MASK);
return eflags;
}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index b909f73..62e3547 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
}
-#define DF (env->df)
-
#define CC_DST (env->cc_dst)
#define CC_SRC (env->cc_src)
#define CC_SRC2 (env->cc_src2)
@@ -1196,7 +1194,7 @@ uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
{
- return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
+ return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
}
/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
@@ -1204,7 +1202,7 @@ static inline void cpu_load_eflags(CPUX86State *env, int eflags,
int update_mask)
{
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- DF = 1 - (2 * ((eflags >> 10) & 1));
+ env->df = 1 - (2 * ((eflags >> 10) & 1));
env->eflags = (env->eflags & ~update_mask) |
(eflags & update_mask) | 0x2;
}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 11/12] target-i386/helper: remove redundant env->eip assignment
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (8 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 10/12] target-i386/helper: remove DF macro liguang
@ 2013-05-28 8:21 ` liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 12/12] target-i386: fix over 80 chars warnings liguang
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/svm_helper.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 649be02..e18fa35 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -249,7 +249,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
R_DS);
env->eip = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
- env->eip = env->eip;
+
env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-devel] [PATCH v4 12/12] target-i386: fix over 80 chars warnings
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
` (9 preceding siblings ...)
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 11/12] target-i386/helper: remove redundant env->eip assignment liguang
@ 2013-05-28 8:21 ` liguang
10 siblings, 0 replies; 12+ messages in thread
From: liguang @ 2013-05-28 8:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Anthony Liguori, Eduardo Habkost, Blue Swirl,
Igor Mammedov, Paolo Bonzini, Andreas Färber, liguang,
Richard Henderson
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
target-i386/misc_helper.c | 39 ++++++++++++++++++++++++++-------------
target-i386/seg_helper.c | 16 +++++++++-------
target-i386/svm_helper.c | 6 ++++--
3 files changed, 39 insertions(+), 22 deletions(-)
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 4ee618d..e345f9a 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -122,7 +122,8 @@ void helper_cpuid(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
- cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
+ cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
+ &eax, &ebx, &ecx, &edx);
env->regs[R_EAX] = eax;
env->regs[R_EBX] = ebx;
env->regs[R_ECX] = ecx;
@@ -271,7 +272,8 @@ void helper_wrmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
- val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
+ val = ((uint32_t)env->regs[R_EAX]) |
+ ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS:
@@ -350,7 +352,8 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
+ env->mtrr_var[((uint32_t)env->regs[R_ECX] -
+ MSR_MTRRphysBase(0)) / 2].base = val;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -360,14 +363,17 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
+ env->mtrr_var[((uint32_t)env->regs[R_ECX] -
+ MSR_MTRRphysMask(0)) / 2].mask = val;
break;
case MSR_MTRRfix64K_00000:
- env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
+ MSR_MTRRfix64K_00000] = val;
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
+ MSR_MTRRfix16K_80000 + 1] = val;
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -377,7 +383,8 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
+ MSR_MTRRfix4K_C0000 + 3] = val;
break;
case MSR_MTRRdefType:
env->mtrr_deftype = val;
@@ -399,7 +406,8 @@ void helper_wrmsr(CPUX86State *env)
break;
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
- && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
+ (4 * env->mcg_cap & 0xff)) {
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
if ((offset & 0x3) != 0
|| (val == 0 || val == ~(uint64_t)0)) {
@@ -480,7 +488,8 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
+ MSR_MTRRphysBase(0)) / 2].base;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -490,14 +499,16 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
+ MSR_MTRRphysMask(0)) / 2].mask;
break;
case MSR_MTRRfix64K_00000:
val = env->mtrr_fixed[0];
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
+ MSR_MTRRfix16K_80000 + 1];
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -507,7 +518,8 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
+ MSR_MTRRfix4K_C0000 + 3];
break;
case MSR_MTRRdefType:
val = env->mtrr_deftype;
@@ -539,7 +551,8 @@ void helper_rdmsr(CPUX86State *env)
break;
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
- && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
+ (4 * env->mcg_cap & 0xff)) {
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
val = env->mce_banks[offset];
break;
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 939d7dc..9c799e1 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1811,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */
get_ss_esp_from_tss(env, &ss, &sp, dpl);
- LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
- "\n",
- ss, sp, param_count, env->regs[R_ESP]);
+ LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
+ TARGET_FMT_lx "\n", ss, sp, param_count,
+ env->regs[R_ESP]);
if ((ss & 0xfffc) == 0) {
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
}
@@ -1847,16 +1847,18 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
- old_sp_mask));
+ val = cpu_ldl_kernel(env, old_ssp +
+ ((env->regs[R_ESP] + i * 4) &
+ old_sp_mask));
PUSHL(ssp, sp, sp_mask, val);
}
} else {
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
- old_sp_mask));
+ val = cpu_lduw_kernel(env, old_ssp +
+ ((env->regs[R_ESP] + i * 2) &
+ old_sp_mask));
PUSHW(ssp, sp, sp_mask, val);
}
}
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index e18fa35..4a7de42 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -658,8 +658,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
R_DS);
env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
- env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
- env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
+ env->regs[R_ESP] = ldq_phys(env->vm_hsave +
+ offsetof(struct vmcb, save.rsp));
+ env->regs[R_EAX] = ldq_phys(env->vm_hsave +
+ offsetof(struct vmcb, save.rax));
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
--
1.7.2.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2013-05-28 8:23 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-28 8:20 [Qemu-devel] [PATCH v4 01/12] target-i386/helper: remove EAX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 02/12] target-i386/helper: remove EBX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 03/12] target-i386/helper: remove ECX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 04/12] target-i386/helper: remove EDX macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 05/12] target-i386/helper: remove EBP macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 06/12] target-i386/helper: remove ESP macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 07/12] target-i386/helper: remove ESI macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 08/12] target-i386/helper: remove EDI macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 09/12] target-i386/helper: remove EIP macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 10/12] target-i386/helper: remove DF macro liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 11/12] target-i386/helper: remove redundant env->eip assignment liguang
2013-05-28 8:21 ` [Qemu-devel] [PATCH v4 12/12] target-i386: fix over 80 chars warnings liguang
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