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From: Lokesh Vutla <lokeshvutla@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 04/12] ARM: OMAP5: DRA7xx: support class 0 optimized voltages
Date: Wed, 29 May 2013 16:32:39 +0530	[thread overview]
Message-ID: <1369825367-4537-5-git-send-email-lokeshvutla@ti.com> (raw)
In-Reply-To: <1369825367-4537-1-git-send-email-lokeshvutla@ti.com>

From: Nishanth Menon <nm@ti.com>

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c |   58 +++++++++++++++++++-----
 arch/arm/cpu/armv7/omap5/hw_data.c             |   10 ++++
 arch/arm/include/asm/arch-omap5/clocks.h       |   30 ++++++++++++
 arch/arm/include/asm/omap_common.h             |   11 +++++
 4 files changed, 97 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 1861df4..928327a 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
 		gpio_direction_output(pmic->gpio, 1);
 }
 
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+	u32 val;
+	if (!v->value)
+		return 0;
+	if (!v->efuse.reg)
+		return v->value;
+
+	switch (v->efuse.reg_bits) {
+	case 16:
+		val = readw(v->efuse.reg);
+		break;
+	case 32:
+		val = readl(v->efuse.reg);
+		break;
+	default:
+		printf("Error: efuse 0x%08x bits=%d unknown\n",
+		       v->efuse.reg, v->efuse.reg_bits);
+		return v->value;
+	}
+
+	if (!val) {
+		printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+		       v->efuse.reg, v->efuse.reg_bits, v->value);
+		return v->value;
+	}
+
+	debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+	      __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+	return val;
+}
+
 /*
  * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
  * We set the maximum voltages allowed here because Smart-Reflex is not
@@ -529,23 +561,25 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  */
 void scale_vcores(struct vcores_data const *vcores)
 {
-	do_scale_vcore(vcores->core.addr, vcores->core.value,
-					  vcores->core.pmic);
+	u32 val;
+
+	val = optimize_vcore_voltage(&vcores->core);
+	do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
 
-	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
-					  vcores->mpu.pmic);
+	val = optimize_vcore_voltage(&vcores->mpu);
+	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 
-	do_scale_vcore(vcores->mm.addr, vcores->mm.value,
-					  vcores->mm.pmic);
+	val = optimize_vcore_voltage(&vcores->mm);
+	do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
 
-	do_scale_vcore(vcores->gpu.addr, vcores->gpu.value,
-		       vcores->gpu.pmic);
+	val = optimize_vcore_voltage(&vcores->gpu);
+	do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
 
-	do_scale_vcore(vcores->eve.addr, vcores->eve.value,
-		       vcores->eve.pmic);
+	val = optimize_vcore_voltage(&vcores->eve);
+	do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
 
-	do_scale_vcore(vcores->iva.addr, vcores->iva.value,
-		       vcores->iva.pmic);
+	val = optimize_vcore_voltage(&vcores->iva);
+	do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
 
 	 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
 		/* Configure LDO SRAM "magic" bits */
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index e9d34c1..53aea93 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = {
 
 struct vcores_data dra752_volts = {
 	.mpu.value	= VDD_MPU_DRA752,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12_MPU,
 	.mpu.pmic	= &tps659038,
 
 	.eve.value	= VDD_EVE_DRA752,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45_EVE,
 	.eve.pmic	= &tps659038,
 
 	.gpu.value	= VDD_GPU_DRA752,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6_GPU,
 	.gpu.pmic	= &tps659038,
 
 	.core.value	= VDD_CORE_DRA752,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS659038_REG_ADDR_SMPS7_CORE,
 	.core.pmic	= &tps659038,
 
 	.iva.value	= VDD_IVA_DRA752,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8_IVA,
 	.iva.pmic	= &tps659038,
 };
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index b43737e..cfcf51d 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -219,6 +219,36 @@
 #define VDD_CORE_DRA752		1030
 #define VDD_IVA_DRA752		1060
 
+/* Efuse register offsets for DRA7xx platform */
+#define DRA752_EFUSE_BASE	0x4A002000
+#define DRA752_EFUSE_REGBITS	16
+/* STD_FUSE_OPP_VMIN_IVA_2 */
+#define STD_FUSE_OPP_VMIN_IVA_NOM	(DRA752_EFUSE_BASE + 0x05CC)
+/* STD_FUSE_OPP_VMIN_IVA_3 */
+#define STD_FUSE_OPP_VMIN_IVA_OD	(DRA752_EFUSE_BASE + 0x05D0)
+/* STD_FUSE_OPP_VMIN_IVA_4 */
+#define STD_FUSE_OPP_VMIN_IVA_HIGH	(DRA752_EFUSE_BASE + 0x05D4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_NOM	(DRA752_EFUSE_BASE + 0x05E0)
+/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_OD	(DRA752_EFUSE_BASE + 0x05E4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH	(DRA752_EFUSE_BASE + 0x05E8)
+/* STD_FUSE_OPP_VMIN_CORE_2 */
+#define STD_FUSE_OPP_VMIN_CORE_NOM	(DRA752_EFUSE_BASE + 0x05F4)
+/* STD_FUSE_OPP_VMIN_GPU_2 */
+#define STD_FUSE_OPP_VMIN_GPU_NOM	(DRA752_EFUSE_BASE + 0x1B08)
+/* STD_FUSE_OPP_VMIN_GPU_3 */
+#define STD_FUSE_OPP_VMIN_GPU_OD	(DRA752_EFUSE_BASE + 0x1B0C)
+/* STD_FUSE_OPP_VMIN_GPU_4 */
+#define STD_FUSE_OPP_VMIN_GPU_HIGH	(DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_MPU_2 */
+#define STD_FUSE_OPP_VMIN_MPU_NOM	(DRA752_EFUSE_BASE + 0x1B20)
+/* STD_FUSE_OPP_VMIN_MPU_3 */
+#define STD_FUSE_OPP_VMIN_MPU_OD	(DRA752_EFUSE_BASE + 0x1B24)
+/* STD_FUSE_OPP_VMIN_MPU_4 */
+#define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 6b28f2e..1435674 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -500,9 +500,20 @@ struct pmic_data {
 	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
 };
 
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg:	register address for efuse
+ * @reg_bits:	Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+	u32 reg;
+	u8 reg_bits;
+};
+
 struct volts {
 	u32 value;
 	u32 addr;
+	struct volts_efuse_data efuse;
 	struct pmic_data *pmic;
 };
 
-- 
1.7.9.5

  parent reply	other threads:[~2013-05-29 11:02 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-29 11:02 [U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 01/12] ARM: DRA7xx: Add control id code for DRA7xx Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 02/12] ARM: DRA7xx: power Add support for tps659038 PMIC Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 03/12] ARM: DRA7xx: clocks: Fixing i2c_init for PMIC Lokesh Vutla
2013-05-29 11:02 ` Lokesh Vutla [this message]
2013-05-29 11:02 ` [U-Boot] [PATCH 05/12] ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 06/12] ARM: DRA7xx: Change the Debug UART to UART1 Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 07/12] ARM: DRA7xx: Correct the SYS_CLK to 20MHZ Lokesh Vutla
2013-05-29 13:04   ` Tom Rini
2013-05-29 11:02 ` [U-Boot] [PATCH 08/12] ARM: DRA7xx: Correct SRAM END address Lokesh Vutla
2013-05-29 13:06   ` Tom Rini
2013-05-29 13:33     ` Sricharan R
2013-05-29 13:53       ` Tom Rini
2013-05-29 11:02 ` [U-Boot] [PATCH 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1 Lokesh Vutla
2013-05-29 13:08   ` Tom Rini
2013-05-29 11:02 ` [U-Boot] [PATCH 10/12] ARM: DRA7xx: Update pinmux data Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 11/12] ARM: DRA7xx: clocks: Update PLL values Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 12/12] ARM: DRA7xx: EMIF: Change settings required for EVM board Lokesh Vutla
2013-05-29 13:12 ` [U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's Tom Rini
2013-05-30  4:11   ` Lokesh Vutla

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