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From: Lokesh Vutla <lokeshvutla@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 08/12] ARM: DRA7xx: Correct SRAM END address
Date: Wed, 29 May 2013 16:32:43 +0530	[thread overview]
Message-ID: <1369825367-4537-9-git-send-email-lokeshvutla@ti.com> (raw)
In-Reply-To: <1369825367-4537-1-git-send-email-lokeshvutla@ti.com>

From: Sricharan R <r.sricharan@ti.com>

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
---
 arch/arm/include/asm/arch-omap5/omap.h |    7 -------
 include/configs/dra7xx_evm.h           |    3 +++
 include/configs/omap5_uevm.h           |    3 +++
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index df8222a..15d429f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -159,13 +159,6 @@ struct s32ktimer {
 #define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
-#define NON_SECURE_SRAM_START	0x40300000
-#define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index b0b0bda..fc35f2f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,7 @@
 /* Clock Defines */
 #define V_OSCK			20000000	/* Clock output from T2 */
 
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4f2d425..96c5955 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -61,5 +61,8 @@
 /* Clock Defines */
 #define V_OSCK			19200000	/* Clock output from T2 */
 
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
+
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 #endif /* __CONFIG_OMAP5_EVM_H */
-- 
1.7.9.5

  parent reply	other threads:[~2013-05-29 11:02 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-29 11:02 [U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 01/12] ARM: DRA7xx: Add control id code for DRA7xx Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 02/12] ARM: DRA7xx: power Add support for tps659038 PMIC Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 03/12] ARM: DRA7xx: clocks: Fixing i2c_init for PMIC Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 04/12] ARM: OMAP5: DRA7xx: support class 0 optimized voltages Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 05/12] ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 06/12] ARM: DRA7xx: Change the Debug UART to UART1 Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 07/12] ARM: DRA7xx: Correct the SYS_CLK to 20MHZ Lokesh Vutla
2013-05-29 13:04   ` Tom Rini
2013-05-29 11:02 ` Lokesh Vutla [this message]
2013-05-29 13:06   ` [U-Boot] [PATCH 08/12] ARM: DRA7xx: Correct SRAM END address Tom Rini
2013-05-29 13:33     ` Sricharan R
2013-05-29 13:53       ` Tom Rini
2013-05-29 11:02 ` [U-Boot] [PATCH 09/12] mmc: omap_hsmmc: add mmc1 pbias, ldo1 Lokesh Vutla
2013-05-29 13:08   ` Tom Rini
2013-05-29 11:02 ` [U-Boot] [PATCH 10/12] ARM: DRA7xx: Update pinmux data Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 11/12] ARM: DRA7xx: clocks: Update PLL values Lokesh Vutla
2013-05-29 11:02 ` [U-Boot] [PATCH 12/12] ARM: DRA7xx: EMIF: Change settings required for EVM board Lokesh Vutla
2013-05-29 13:12 ` [U-Boot] [PATCH 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's Tom Rini
2013-05-30  4:11   ` Lokesh Vutla

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