* [PATCH v6 01/21] memory: mvebu-devbus: Remove address decoding window workaround
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
Now that mbus device tree binding has been introduced, remove the address
decoding window management from this driver.
A suitable 'ranges' entry should be added to the devbus-compatible node in
the device tree, as described by the mbus binding documentation.
Acked-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/memory/mvebu-devbus.c | 64 ++-----------------------------------------
1 file changed, 2 insertions(+), 62 deletions(-)
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 978e8e3..94c9248 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -208,16 +208,11 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = pdev->dev.of_node;
- struct device_node *parent;
struct devbus *devbus;
struct resource *res;
struct clk *clk;
unsigned long rate;
- const __be32 *ranges;
- int err, cs;
- int addr_cells, p_addr_cells, size_cells;
- int ranges_len, tuple_len;
- u32 base, size;
+ int err;
devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
if (!devbus)
@@ -248,68 +243,13 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
return err;
/*
- * Allocate an address window for this device.
- * If the device probing fails, then we won't be able to
- * remove the allocated address decoding window.
- *
- * FIXME: This is only a temporary hack! We need to do this here
- * because we still don't have device tree bindings for mbus.
- * Once that support is added, we will declare these address windows
- * statically in the device tree, and remove the window configuration
- * from here.
- */
-
- /*
- * Get the CS to choose the window string.
- * This is a bit hacky, but it will be removed once the
- * address windows are declared in the device tree.
- */
- cs = (((unsigned long)devbus->base) % 0x400) / 8;
-
- /*
- * Parse 'ranges' property to obtain a (base,size) window tuple.
- * This will be removed once the address windows
- * are declared in the device tree.
- */
- parent = of_get_parent(node);
- if (!parent)
- return -EINVAL;
-
- p_addr_cells = of_n_addr_cells(parent);
- of_node_put(parent);
-
- addr_cells = of_n_addr_cells(node);
- size_cells = of_n_size_cells(node);
- tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
-
- ranges = of_get_property(node, "ranges", &ranges_len);
- if (ranges == NULL || ranges_len != tuple_len)
- return -EINVAL;
-
- base = of_translate_address(node, ranges + addr_cells);
- if (base == OF_BAD_ADDR)
- return -EINVAL;
- size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
-
- /*
- * Create an mbus address windows.
- * FIXME: Remove this, together with the above code, once the
- * address windows are declared in the device tree.
- */
- err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
- if (err < 0)
- return err;
-
- /*
* We need to create a child device explicitly from here to
* guarantee that the child will be probed after the timing
* parameters for the bus are written.
*/
err = of_platform_populate(node, NULL, NULL, dev);
- if (err < 0) {
- mvebu_mbus_del_window(base, size);
+ if (err < 0)
return err;
- }
return 0;
}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 01/21] memory: mvebu-devbus: Remove address decoding window workaround
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
Now that mbus device tree binding has been introduced, remove the address
decoding window management from this driver.
A suitable 'ranges' entry should be added to the devbus-compatible node in
the device tree, as described by the mbus binding documentation.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
drivers/memory/mvebu-devbus.c | 64 ++-----------------------------------------
1 file changed, 2 insertions(+), 62 deletions(-)
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 978e8e3..94c9248 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -208,16 +208,11 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = pdev->dev.of_node;
- struct device_node *parent;
struct devbus *devbus;
struct resource *res;
struct clk *clk;
unsigned long rate;
- const __be32 *ranges;
- int err, cs;
- int addr_cells, p_addr_cells, size_cells;
- int ranges_len, tuple_len;
- u32 base, size;
+ int err;
devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
if (!devbus)
@@ -248,68 +243,13 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
return err;
/*
- * Allocate an address window for this device.
- * If the device probing fails, then we won't be able to
- * remove the allocated address decoding window.
- *
- * FIXME: This is only a temporary hack! We need to do this here
- * because we still don't have device tree bindings for mbus.
- * Once that support is added, we will declare these address windows
- * statically in the device tree, and remove the window configuration
- * from here.
- */
-
- /*
- * Get the CS to choose the window string.
- * This is a bit hacky, but it will be removed once the
- * address windows are declared in the device tree.
- */
- cs = (((unsigned long)devbus->base) % 0x400) / 8;
-
- /*
- * Parse 'ranges' property to obtain a (base,size) window tuple.
- * This will be removed once the address windows
- * are declared in the device tree.
- */
- parent = of_get_parent(node);
- if (!parent)
- return -EINVAL;
-
- p_addr_cells = of_n_addr_cells(parent);
- of_node_put(parent);
-
- addr_cells = of_n_addr_cells(node);
- size_cells = of_n_size_cells(node);
- tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
-
- ranges = of_get_property(node, "ranges", &ranges_len);
- if (ranges == NULL || ranges_len != tuple_len)
- return -EINVAL;
-
- base = of_translate_address(node, ranges + addr_cells);
- if (base == OF_BAD_ADDR)
- return -EINVAL;
- size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
-
- /*
- * Create an mbus address windows.
- * FIXME: Remove this, together with the above code, once the
- * address windows are declared in the device tree.
- */
- err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
- if (err < 0)
- return err;
-
- /*
* We need to create a child device explicitly from here to
* guarantee that the child will be probed after the timing
* parameters for the bus are written.
*/
err = of_platform_populate(node, NULL, NULL, dev);
- if (err < 0) {
- mvebu_mbus_del_window(base, size);
+ if (err < 0)
return err;
- }
return 0;
}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 02/21] bus: mvebu-mbus: Add new API for window creation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
We add an API to create MBus address decoding windows from the target
ID and attribute. This function will be used later and deprecate the
current name based scheme.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 33 +++++++++++++++++++++++++--------
include/linux/mbus.h | 6 ++++++
2 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 33c6947..827468a 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -748,6 +748,22 @@ static const struct of_device_id of_mvebu_mbus_ids[] = {
/*
* Public API of the driver
*/
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap)
+{
+ struct mvebu_mbus_state *s = &mbus_state;
+
+ if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+ pr_err("cannot add window '%x:%x', conflicts with another window\n",
+ target, attribute);
+ return -EINVAL;
+ }
+
+ return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
+}
+
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
size_t size, phys_addr_t remap,
unsigned int flags)
@@ -776,14 +792,8 @@ int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
else if (flags == MVEBU_MBUS_PCI_WA)
attr |= 0x28;
- if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
- pr_err("cannot add window '%s', conflicts with another window\n",
- devname);
- return -EINVAL;
- }
-
- return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
-
+ return mvebu_mbus_add_window_remap_by_id(target, attr, base,
+ size, remap);
}
int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
@@ -792,6 +802,13 @@ int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
MVEBU_MBUS_NO_REMAP, 0);
}
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size)
+{
+ return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+ size, MVEBU_MBUS_NO_REMAP);
+}
+
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
{
int win;
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index dba482e..9245b66 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -62,8 +62,14 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
size_t size, phys_addr_t remap,
unsigned int flags);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap);
int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
size_t size);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
size_t mbus_size, phys_addr_t sdram_phys_base,
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 02/21] bus: mvebu-mbus: Add new API for window creation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
We add an API to create MBus address decoding windows from the target
ID and attribute. This function will be used later and deprecate the
current name based scheme.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 33 +++++++++++++++++++++++++--------
include/linux/mbus.h | 6 ++++++
2 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 33c6947..827468a 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -748,6 +748,22 @@ static const struct of_device_id of_mvebu_mbus_ids[] = {
/*
* Public API of the driver
*/
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap)
+{
+ struct mvebu_mbus_state *s = &mbus_state;
+
+ if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+ pr_err("cannot add window '%x:%x', conflicts with another window\n",
+ target, attribute);
+ return -EINVAL;
+ }
+
+ return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
+}
+
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
size_t size, phys_addr_t remap,
unsigned int flags)
@@ -776,14 +792,8 @@ int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
else if (flags == MVEBU_MBUS_PCI_WA)
attr |= 0x28;
- if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
- pr_err("cannot add window '%s', conflicts with another window\n",
- devname);
- return -EINVAL;
- }
-
- return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
-
+ return mvebu_mbus_add_window_remap_by_id(target, attr, base,
+ size, remap);
}
int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
@@ -792,6 +802,13 @@ int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
MVEBU_MBUS_NO_REMAP, 0);
}
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size)
+{
+ return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+ size, MVEBU_MBUS_NO_REMAP);
+}
+
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
{
int win;
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index dba482e..9245b66 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -62,8 +62,14 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
size_t size, phys_addr_t remap,
unsigned int flags);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap);
int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
size_t size);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
size_t mbus_size, phys_addr_t sdram_phys_base,
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 03/21] ARM: kirkwood: Move to ID based MBus window creation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-kirkwood/common.c | 18 ++++++++++++++----
arch/arm/mach-kirkwood/pcie.c | 40 ++++++++++++++++++++++++----------------
2 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index e9238b5..165e751 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -37,6 +37,12 @@
#include <linux/platform_data/dma-mv_xor.h>
#include "common.h"
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_NAND_TARGET 0x01
+#define KIRKWOOD_MBUS_NAND_ATTR 0x2f
+#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
+#define KIRKWOOD_MBUS_SRAM_ATTR 0x01
+
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@@ -672,10 +678,14 @@ char * __init kirkwood_id(void)
void __init kirkwood_setup_wins(void)
{
- mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
- KIRKWOOD_NAND_MEM_SIZE);
- mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
- KIRKWOOD_SRAM_SIZE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
+ KIRKWOOD_MBUS_NAND_ATTR,
+ KIRKWOOD_NAND_MEM_PHYS_BASE,
+ KIRKWOOD_NAND_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
+ KIRKWOOD_MBUS_SRAM_ATTR,
+ KIRKWOOD_SRAM_PHYS_BASE,
+ KIRKWOOD_SRAM_SIZE);
}
void __init kirkwood_l2_init(void)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ddcb09f..12d86f3 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -20,6 +20,16 @@
#include <mach/bridge-regs.h>
#include "common.h"
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
+#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
+#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
+#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
+
static void kirkwood_enable_pcie_clk(const char *port)
{
struct clk *clk;
@@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
void __init kirkwood_pcie_init(unsigned int portmask)
{
- mvebu_mbus_add_window_remap_flags("pcie0.0",
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE0_IO_ATTR,
KIRKWOOD_PCIE_IO_PHYS_BASE,
KIRKWOOD_PCIE_IO_SIZE,
- KIRKWOOD_PCIE_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- KIRKWOOD_PCIE_MEM_PHYS_BASE,
- KIRKWOOD_PCIE_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
+ KIRKWOOD_PCIE_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
+ KIRKWOOD_PCIE_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE_MEM_SIZE);
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE1_IO_ATTR,
KIRKWOOD_PCIE1_IO_PHYS_BASE,
KIRKWOOD_PCIE1_IO_SIZE,
- KIRKWOOD_PCIE1_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
- KIRKWOOD_PCIE1_MEM_PHYS_BASE,
- KIRKWOOD_PCIE1_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ KIRKWOOD_PCIE1_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
+ KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE1_MEM_SIZE);
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 03/21] ARM: kirkwood: Move to ID based MBus window creation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-kirkwood/common.c | 18 ++++++++++++++----
arch/arm/mach-kirkwood/pcie.c | 40 ++++++++++++++++++++++++----------------
2 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index e9238b5..165e751 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -37,6 +37,12 @@
#include <linux/platform_data/dma-mv_xor.h>
#include "common.h"
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_NAND_TARGET 0x01
+#define KIRKWOOD_MBUS_NAND_ATTR 0x2f
+#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
+#define KIRKWOOD_MBUS_SRAM_ATTR 0x01
+
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@@ -672,10 +678,14 @@ char * __init kirkwood_id(void)
void __init kirkwood_setup_wins(void)
{
- mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
- KIRKWOOD_NAND_MEM_SIZE);
- mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
- KIRKWOOD_SRAM_SIZE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
+ KIRKWOOD_MBUS_NAND_ATTR,
+ KIRKWOOD_NAND_MEM_PHYS_BASE,
+ KIRKWOOD_NAND_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
+ KIRKWOOD_MBUS_SRAM_ATTR,
+ KIRKWOOD_SRAM_PHYS_BASE,
+ KIRKWOOD_SRAM_SIZE);
}
void __init kirkwood_l2_init(void)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ddcb09f..12d86f3 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -20,6 +20,16 @@
#include <mach/bridge-regs.h>
#include "common.h"
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
+#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
+#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
+#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
+
static void kirkwood_enable_pcie_clk(const char *port)
{
struct clk *clk;
@@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
void __init kirkwood_pcie_init(unsigned int portmask)
{
- mvebu_mbus_add_window_remap_flags("pcie0.0",
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE0_IO_ATTR,
KIRKWOOD_PCIE_IO_PHYS_BASE,
KIRKWOOD_PCIE_IO_SIZE,
- KIRKWOOD_PCIE_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- KIRKWOOD_PCIE_MEM_PHYS_BASE,
- KIRKWOOD_PCIE_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
+ KIRKWOOD_PCIE_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
+ KIRKWOOD_PCIE_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE_MEM_SIZE);
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE1_IO_ATTR,
KIRKWOOD_PCIE1_IO_PHYS_BASE,
KIRKWOOD_PCIE1_IO_SIZE,
- KIRKWOOD_PCIE1_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
- KIRKWOOD_PCIE1_MEM_PHYS_BASE,
- KIRKWOOD_PCIE1_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ KIRKWOOD_PCIE1_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
+ KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE1_MEM_SIZE);
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 04/21] ARM: mv78xx0: Move to ID based window creation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-mv78xx0/pcie.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index dc26a65..397afde 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -18,6 +18,11 @@
#include <mach/mv78xx0.h>
#include "common.h"
+#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
+#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
+
struct pcie_port {
u8 maj;
u8 min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
start = MV78XX0_PCIE_MEM_PHYS_BASE;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
- char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
if (request_resource(&iomem_resource, &pp->res))
panic("can't allocate PCIe MEM sub-space");
- snprintf(winname, sizeof(winname), "pcie%d.%d",
- pp->maj, pp->min);
-
- mvebu_mbus_add_window_remap_flags(winname,
- pp->res.start,
- resource_size(&pp->res),
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags(winname,
- i * SZ_64K, SZ_64K,
- 0, MVEBU_MBUS_PCI_IO);
+ mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
+ MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
+ pp->res.start, resource_size(&pp->res));
+ mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
+ MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
+ i * SZ_64K, SZ_64K, 0);
}
}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 04/21] ARM: mv78xx0: Move to ID based window creation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mv78xx0/pcie.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index dc26a65..397afde 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -18,6 +18,11 @@
#include <mach/mv78xx0.h>
#include "common.h"
+#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
+#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
+
struct pcie_port {
u8 maj;
u8 min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
start = MV78XX0_PCIE_MEM_PHYS_BASE;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
- char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
if (request_resource(&iomem_resource, &pp->res))
panic("can't allocate PCIe MEM sub-space");
- snprintf(winname, sizeof(winname), "pcie%d.%d",
- pp->maj, pp->min);
-
- mvebu_mbus_add_window_remap_flags(winname,
- pp->res.start,
- resource_size(&pp->res),
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags(winname,
- i * SZ_64K, SZ_64K,
- 0, MVEBU_MBUS_PCI_IO);
+ mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
+ MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
+ pp->res.start, resource_size(&pp->res));
+ mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
+ MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
+ i * SZ_64K, SZ_64K, 0);
}
}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 05/21] ARM: orion5x: Move to ID based window creation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-orion5x/common.c | 36 ++++++++++++++------------
arch/arm/mach-orion5x/common.h | 17 ++++++++++++
arch/arm/mach-orion5x/d2net-setup.c | 6 +++--
arch/arm/mach-orion5x/db88f5281-setup.c | 24 +++++++++++------
arch/arm/mach-orion5x/dns323-setup.c | 6 +++--
arch/arm/mach-orion5x/edmini_v2-setup.c | 6 +++--
arch/arm/mach-orion5x/kurobox_pro-setup.c | 12 ++++++---
arch/arm/mach-orion5x/ls-chl-setup.c | 6 +++--
arch/arm/mach-orion5x/ls_hgl-setup.c | 6 +++--
arch/arm/mach-orion5x/lsmini-setup.c | 6 +++--
arch/arm/mach-orion5x/mss2-setup.c | 6 +++--
arch/arm/mach-orion5x/mv2120-setup.c | 6 +++--
arch/arm/mach-orion5x/net2big-setup.c | 6 +++--
arch/arm/mach-orion5x/pci.c | 9 +++----
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 6 +++--
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 6 +++--
arch/arm/mach-orion5x/rd88f5182-setup.c | 13 ++++++----
arch/arm/mach-orion5x/terastation_pro2-setup.c | 6 +++--
arch/arm/mach-orion5x/ts209-setup.c | 6 +++--
arch/arm/mach-orion5x/ts409-setup.c | 6 +++--
arch/arm/mach-orion5x/wnr854t-setup.c | 6 +++--
arch/arm/mach-orion5x/wrt350n-v2-setup.c | 6 +++--
22 files changed, 137 insertions(+), 70 deletions(-)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b41599f..91a5852 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
****************************************************************************/
static void __init orion5x_crypto_init(void)
{
- mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
- ORION5X_SRAM_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
+ ORION_MBUS_SRAM_ATTR,
+ ORION5X_SRAM_PHYS_BASE,
+ ORION5X_SRAM_SIZE);
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
SZ_8K, IRQ_ORION5X_CESA);
}
@@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
* The PCIe windows will no longer be statically allocated
* here once Orion5x is migrated to the pci-mvebu driver.
*/
- mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+ mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
+ ORION_MBUS_PCIE_IO_ATTR,
+ ORION5X_PCIE_IO_PHYS_BASE,
ORION5X_PCIE_IO_SIZE,
- ORION5X_PCIE_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
- ORION5X_PCIE_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+ ORION5X_PCIE_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
+ ORION_MBUS_PCIE_MEM_ATTR,
+ ORION5X_PCIE_MEM_PHYS_BASE,
+ ORION5X_PCIE_MEM_SIZE);
+ mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
+ ORION_MBUS_PCI_IO_ATTR,
+ ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
- ORION5X_PCI_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
- ORION5X_PCI_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ ORION5X_PCI_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
+ ORION_MBUS_PCI_MEM_ATTR,
+ ORION5X_PCI_MEM_PHYS_BASE,
+ ORION5X_PCI_MEM_SIZE);
}
int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a909afb..f565f99 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -7,6 +7,23 @@ struct dsa_platform_data;
struct mv643xx_eth_platform_data;
struct mv_sata_platform_data;
+#define ORION_MBUS_PCIE_MEM_TARGET 0x04
+#define ORION_MBUS_PCIE_MEM_ATTR 0x59
+#define ORION_MBUS_PCIE_IO_TARGET 0x04
+#define ORION_MBUS_PCIE_IO_ATTR 0x51
+#define ORION_MBUS_PCIE_WA_TARGET 0x04
+#define ORION_MBUS_PCIE_WA_ATTR 0x79
+#define ORION_MBUS_PCI_MEM_TARGET 0x03
+#define ORION_MBUS_PCI_MEM_ATTR 0x59
+#define ORION_MBUS_PCI_IO_TARGET 0x03
+#define ORION_MBUS_PCI_IO_ATTR 0x51
+#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
+#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
+#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
+#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
+#define ORION_MBUS_SRAM_TARGET 0x00
+#define ORION_MBUS_SRAM_ATTR 0x00
+
/*
* Basic Orion init functions used early by machine-setup.
*/
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 16c88bb..8f68b74 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,10 @@ static void __init d2net_init(void)
d2net_sata_power_init();
orion5x_sata_init(&d2net_sata_data);
- mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
- D2NET_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ D2NET_NOR_BOOT_BASE,
+ D2NET_NOR_BOOT_SIZE);
platform_device_register(&d2net_nor_flash);
platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4e1263d..4b2aefd 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
orion5x_uart0_init();
orion5x_uart1_init();
- mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
- DB88F5281_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ DB88F5281_NOR_BOOT_BASE,
+ DB88F5281_NOR_BOOT_SIZE);
platform_device_register(&db88f5281_boot_flash);
- mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
- DB88F5281_7SEG_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+ ORION_MBUS_DEVBUS_ATTR(0),
+ DB88F5281_7SEG_BASE,
+ DB88F5281_7SEG_SIZE);
- mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
- DB88F5281_NOR_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+ ORION_MBUS_DEVBUS_ATTR(1),
+ DB88F5281_NOR_BASE,
+ DB88F5281_NOR_SIZE);
platform_device_register(&db88f5281_nor_flash);
- mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
- DB88F5281_NAND_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
+ ORION_MBUS_DEVBUS_ATTR(2),
+ DB88F5281_NAND_BASE,
+ DB88F5281_NAND_SIZE);
platform_device_register(&db88f5281_nand_flash);
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 9e6baf5..7097473 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,8 +611,10 @@ static void __init dns323_init(void)
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
- mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
- DNS323_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ DNS323_NOR_BOOT_BASE,
+ DNS323_NOR_BOOT_SIZE);
platform_device_register(&dns323_nor_flash);
/* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 1476155..0fc33c5 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,10 @@ void __init edmini_v2_init(void)
orion5x_ehci0_init();
orion5x_eth_init(&edmini_v2_eth_data);
- mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
- EDMINI_V2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ EDMINI_V2_NOR_BOOT_BASE,
+ EDMINI_V2_NOR_BOOT_SIZE);
platform_device_register(&edmini_v2_nor_flash);
pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index aae10e4..fe6a48a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
orion5x_uart1_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
- KUROBOX_PRO_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ KUROBOX_PRO_NOR_BOOT_BASE,
+ KUROBOX_PRO_NOR_BOOT_SIZE);
platform_device_register(&kurobox_pro_nor_flash);
if (machine_is_kurobox_pro()) {
- mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
- KUROBOX_PRO_NAND_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+ ORION_MBUS_DEVBUS_ATTR(0),
+ KUROBOX_PRO_NAND_BASE,
+ KUROBOX_PRO_NAND_SIZE);
platform_device_register(&kurobox_pro_nand_flash);
}
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6234977..028ea03 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,10 @@ static void __init lschl_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
- LSCHL_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LSCHL_NOR_BOOT_BASE,
+ LSCHL_NOR_BOOT_SIZE);
platform_device_register(&lschl_nor_flash);
platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fe04c4b..32b7129 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
- LS_HGL_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LS_HGL_NOR_BOOT_BASE,
+ LS_HGL_NOR_BOOT_SIZE);
platform_device_register(&ls_hgl_nor_flash);
platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ca4dbe9..a6493e7 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,10 @@ static void __init lsmini_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
- LSMINI_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LSMINI_NOR_BOOT_BASE,
+ LSMINI_NOR_BOOT_SIZE);
platform_device_register(&lsmini_nor_flash);
platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 827acba..e105130 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,8 +241,10 @@ static void __init mss2_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
- MSS2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ MSS2_NOR_BOOT_BASE,
+ MSS2_NOR_BOOT_SIZE);
platform_device_register(&mss2_nor_flash);
platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 92600ae..e032f01 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,8 +204,10 @@ static void __init mv2120_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
- MV2120_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ MV2120_NOR_BOOT_BASE,
+ MV2120_NOR_BOOT_SIZE);
platform_device_register(&mv2120_nor_flash);
platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index dd0641a..ba73dc7 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,10 @@ static void __init net2big_init(void)
net2big_sata_power_init();
orion5x_sata_init(&net2big_sata_data);
- mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
- NET2BIG_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ NET2BIG_NOR_BOOT_BASE,
+ NET2BIG_NOR_BOOT_SIZE);
platform_device_register(&net2big_nor_flash);
platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 5033680..7fab670 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
"read transaction workaround\n");
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- ORION5X_PCIE_WA_PHYS_BASE,
- ORION5X_PCIE_WA_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_WA);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
+ ORION_MBUS_PCIE_WA_ATTR,
+ ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
pcie_ops.read = pcie_rd_conf_wa;
}
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 1c4498b..213b3e1 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
- RD88F5181L_FXO_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5181L_FXO_NOR_BOOT_BASE,
+ RD88F5181L_FXO_NOR_BOOT_SIZE);
platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
}
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index adabe34..594800e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
orion5x_i2c_init();
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
- RD88F5181L_GE_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5181L_GE_NOR_BOOT_BASE,
+ RD88F5181L_GE_NOR_BOOT_SIZE);
platform_device_register(&rd88f5181l_ge_nor_boot_flash);
i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 66e77ec..b1cf684 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
- RD88F5182_NOR_BOOT_SIZE);
-
- mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
- RD88F5182_NOR_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5182_NOR_BOOT_BASE,
+ RD88F5182_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+ ORION_MBUS_DEVBUS_ATTR(1),
+ RD88F5182_NOR_BASE,
+ RD88F5182_NOR_SIZE);
platform_device_register(&rd88f5182_nor_flash);
platform_device_register(&rd88f5182_gpio_leds);
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a0bfa53..7e90648 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,10 @@ static void __init tsp2_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
- TSP2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ TSP2_NOR_BOOT_BASE,
+ TSP2_NOR_BOOT_SIZE);
platform_device_register(&tsp2_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 80174f0..e90c061 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
- QNAP_TS209_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ QNAP_TS209_NOR_BOOT_BASE,
+ QNAP_TS209_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts209_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9259279..5c079d3 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
- QNAP_TS409_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ QNAP_TS409_NOR_BOOT_BASE,
+ QNAP_TS409_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts409_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 6b84863..80a56ee 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
- WNR854T_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ WNR854T_NOR_BOOT_BASE,
+ WNR854T_NOR_BOOT_SIZE);
platform_device_register(&wnr854t_nor_flash);
}
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fae684b..670e30d 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
- WRT350N_V2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ WRT350N_V2_NOR_BOOT_BASE,
+ WRT350N_V2_NOR_BOOT_SIZE);
platform_device_register(&wrt350n_v2_nor_flash);
platform_device_register(&wrt350n_v2_leds);
platform_device_register(&wrt350n_v2_button_device);
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 05/21] ARM: orion5x: Move to ID based window creation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-orion5x/common.c | 36 ++++++++++++++------------
arch/arm/mach-orion5x/common.h | 17 ++++++++++++
arch/arm/mach-orion5x/d2net-setup.c | 6 +++--
arch/arm/mach-orion5x/db88f5281-setup.c | 24 +++++++++++------
arch/arm/mach-orion5x/dns323-setup.c | 6 +++--
arch/arm/mach-orion5x/edmini_v2-setup.c | 6 +++--
arch/arm/mach-orion5x/kurobox_pro-setup.c | 12 ++++++---
arch/arm/mach-orion5x/ls-chl-setup.c | 6 +++--
arch/arm/mach-orion5x/ls_hgl-setup.c | 6 +++--
arch/arm/mach-orion5x/lsmini-setup.c | 6 +++--
arch/arm/mach-orion5x/mss2-setup.c | 6 +++--
arch/arm/mach-orion5x/mv2120-setup.c | 6 +++--
arch/arm/mach-orion5x/net2big-setup.c | 6 +++--
arch/arm/mach-orion5x/pci.c | 9 +++----
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 6 +++--
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 6 +++--
arch/arm/mach-orion5x/rd88f5182-setup.c | 13 ++++++----
arch/arm/mach-orion5x/terastation_pro2-setup.c | 6 +++--
arch/arm/mach-orion5x/ts209-setup.c | 6 +++--
arch/arm/mach-orion5x/ts409-setup.c | 6 +++--
arch/arm/mach-orion5x/wnr854t-setup.c | 6 +++--
arch/arm/mach-orion5x/wrt350n-v2-setup.c | 6 +++--
22 files changed, 137 insertions(+), 70 deletions(-)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b41599f..91a5852 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
****************************************************************************/
static void __init orion5x_crypto_init(void)
{
- mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
- ORION5X_SRAM_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
+ ORION_MBUS_SRAM_ATTR,
+ ORION5X_SRAM_PHYS_BASE,
+ ORION5X_SRAM_SIZE);
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
SZ_8K, IRQ_ORION5X_CESA);
}
@@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
* The PCIe windows will no longer be statically allocated
* here once Orion5x is migrated to the pci-mvebu driver.
*/
- mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+ mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
+ ORION_MBUS_PCIE_IO_ATTR,
+ ORION5X_PCIE_IO_PHYS_BASE,
ORION5X_PCIE_IO_SIZE,
- ORION5X_PCIE_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
- ORION5X_PCIE_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+ ORION5X_PCIE_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
+ ORION_MBUS_PCIE_MEM_ATTR,
+ ORION5X_PCIE_MEM_PHYS_BASE,
+ ORION5X_PCIE_MEM_SIZE);
+ mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
+ ORION_MBUS_PCI_IO_ATTR,
+ ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
- ORION5X_PCI_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
- ORION5X_PCI_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ ORION5X_PCI_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
+ ORION_MBUS_PCI_MEM_ATTR,
+ ORION5X_PCI_MEM_PHYS_BASE,
+ ORION5X_PCI_MEM_SIZE);
}
int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a909afb..f565f99 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -7,6 +7,23 @@ struct dsa_platform_data;
struct mv643xx_eth_platform_data;
struct mv_sata_platform_data;
+#define ORION_MBUS_PCIE_MEM_TARGET 0x04
+#define ORION_MBUS_PCIE_MEM_ATTR 0x59
+#define ORION_MBUS_PCIE_IO_TARGET 0x04
+#define ORION_MBUS_PCIE_IO_ATTR 0x51
+#define ORION_MBUS_PCIE_WA_TARGET 0x04
+#define ORION_MBUS_PCIE_WA_ATTR 0x79
+#define ORION_MBUS_PCI_MEM_TARGET 0x03
+#define ORION_MBUS_PCI_MEM_ATTR 0x59
+#define ORION_MBUS_PCI_IO_TARGET 0x03
+#define ORION_MBUS_PCI_IO_ATTR 0x51
+#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
+#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
+#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
+#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
+#define ORION_MBUS_SRAM_TARGET 0x00
+#define ORION_MBUS_SRAM_ATTR 0x00
+
/*
* Basic Orion init functions used early by machine-setup.
*/
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 16c88bb..8f68b74 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,10 @@ static void __init d2net_init(void)
d2net_sata_power_init();
orion5x_sata_init(&d2net_sata_data);
- mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
- D2NET_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ D2NET_NOR_BOOT_BASE,
+ D2NET_NOR_BOOT_SIZE);
platform_device_register(&d2net_nor_flash);
platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4e1263d..4b2aefd 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
orion5x_uart0_init();
orion5x_uart1_init();
- mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
- DB88F5281_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ DB88F5281_NOR_BOOT_BASE,
+ DB88F5281_NOR_BOOT_SIZE);
platform_device_register(&db88f5281_boot_flash);
- mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
- DB88F5281_7SEG_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+ ORION_MBUS_DEVBUS_ATTR(0),
+ DB88F5281_7SEG_BASE,
+ DB88F5281_7SEG_SIZE);
- mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
- DB88F5281_NOR_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+ ORION_MBUS_DEVBUS_ATTR(1),
+ DB88F5281_NOR_BASE,
+ DB88F5281_NOR_SIZE);
platform_device_register(&db88f5281_nor_flash);
- mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
- DB88F5281_NAND_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
+ ORION_MBUS_DEVBUS_ATTR(2),
+ DB88F5281_NAND_BASE,
+ DB88F5281_NAND_SIZE);
platform_device_register(&db88f5281_nand_flash);
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 9e6baf5..7097473 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,8 +611,10 @@ static void __init dns323_init(void)
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
- mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
- DNS323_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ DNS323_NOR_BOOT_BASE,
+ DNS323_NOR_BOOT_SIZE);
platform_device_register(&dns323_nor_flash);
/* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 1476155..0fc33c5 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,10 @@ void __init edmini_v2_init(void)
orion5x_ehci0_init();
orion5x_eth_init(&edmini_v2_eth_data);
- mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
- EDMINI_V2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ EDMINI_V2_NOR_BOOT_BASE,
+ EDMINI_V2_NOR_BOOT_SIZE);
platform_device_register(&edmini_v2_nor_flash);
pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index aae10e4..fe6a48a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
orion5x_uart1_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
- KUROBOX_PRO_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ KUROBOX_PRO_NOR_BOOT_BASE,
+ KUROBOX_PRO_NOR_BOOT_SIZE);
platform_device_register(&kurobox_pro_nor_flash);
if (machine_is_kurobox_pro()) {
- mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
- KUROBOX_PRO_NAND_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+ ORION_MBUS_DEVBUS_ATTR(0),
+ KUROBOX_PRO_NAND_BASE,
+ KUROBOX_PRO_NAND_SIZE);
platform_device_register(&kurobox_pro_nand_flash);
}
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6234977..028ea03 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,10 @@ static void __init lschl_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
- LSCHL_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LSCHL_NOR_BOOT_BASE,
+ LSCHL_NOR_BOOT_SIZE);
platform_device_register(&lschl_nor_flash);
platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fe04c4b..32b7129 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
- LS_HGL_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LS_HGL_NOR_BOOT_BASE,
+ LS_HGL_NOR_BOOT_SIZE);
platform_device_register(&ls_hgl_nor_flash);
platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ca4dbe9..a6493e7 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,10 @@ static void __init lsmini_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
- LSMINI_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ LSMINI_NOR_BOOT_BASE,
+ LSMINI_NOR_BOOT_SIZE);
platform_device_register(&lsmini_nor_flash);
platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 827acba..e105130 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,8 +241,10 @@ static void __init mss2_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
- MSS2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ MSS2_NOR_BOOT_BASE,
+ MSS2_NOR_BOOT_SIZE);
platform_device_register(&mss2_nor_flash);
platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 92600ae..e032f01 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,8 +204,10 @@ static void __init mv2120_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
- MV2120_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ MV2120_NOR_BOOT_BASE,
+ MV2120_NOR_BOOT_SIZE);
platform_device_register(&mv2120_nor_flash);
platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index dd0641a..ba73dc7 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,10 @@ static void __init net2big_init(void)
net2big_sata_power_init();
orion5x_sata_init(&net2big_sata_data);
- mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
- NET2BIG_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ NET2BIG_NOR_BOOT_BASE,
+ NET2BIG_NOR_BOOT_SIZE);
platform_device_register(&net2big_nor_flash);
platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 5033680..7fab670 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
"read transaction workaround\n");
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- ORION5X_PCIE_WA_PHYS_BASE,
- ORION5X_PCIE_WA_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_WA);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
+ ORION_MBUS_PCIE_WA_ATTR,
+ ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
pcie_ops.read = pcie_rd_conf_wa;
}
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 1c4498b..213b3e1 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
- RD88F5181L_FXO_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5181L_FXO_NOR_BOOT_BASE,
+ RD88F5181L_FXO_NOR_BOOT_SIZE);
platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
}
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index adabe34..594800e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
orion5x_i2c_init();
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
- RD88F5181L_GE_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5181L_GE_NOR_BOOT_BASE,
+ RD88F5181L_GE_NOR_BOOT_SIZE);
platform_device_register(&rd88f5181l_ge_nor_boot_flash);
i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 66e77ec..b1cf684 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
orion5x_uart0_init();
orion5x_xor_init();
- mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
- RD88F5182_NOR_BOOT_SIZE);
-
- mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
- RD88F5182_NOR_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ RD88F5182_NOR_BOOT_BASE,
+ RD88F5182_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+ ORION_MBUS_DEVBUS_ATTR(1),
+ RD88F5182_NOR_BASE,
+ RD88F5182_NOR_SIZE);
platform_device_register(&rd88f5182_nor_flash);
platform_device_register(&rd88f5182_gpio_leds);
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a0bfa53..7e90648 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,10 @@ static void __init tsp2_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
- TSP2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ TSP2_NOR_BOOT_BASE,
+ TSP2_NOR_BOOT_SIZE);
platform_device_register(&tsp2_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 80174f0..e90c061 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
- QNAP_TS209_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ QNAP_TS209_NOR_BOOT_BASE,
+ QNAP_TS209_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts209_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9259279..5c079d3 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
/*
* Configure peripherals.
*/
- mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
- QNAP_TS409_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ QNAP_TS409_NOR_BOOT_BASE,
+ QNAP_TS409_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts409_nor_flash);
orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 6b84863..80a56ee 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
- WNR854T_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ WNR854T_NOR_BOOT_BASE,
+ WNR854T_NOR_BOOT_SIZE);
platform_device_register(&wnr854t_nor_flash);
}
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fae684b..670e30d 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
orion5x_uart0_init();
- mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
- WRT350N_V2_NOR_BOOT_SIZE);
+ mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+ ORION_MBUS_DEVBUS_BOOT_ATTR,
+ WRT350N_V2_NOR_BOOT_BASE,
+ WRT350N_V2_NOR_BOOT_SIZE);
platform_device_register(&wrt350n_v2_nor_flash);
platform_device_register(&wrt350n_v2_leds);
platform_device_register(&wrt350n_v2_button_device);
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 06/21] ARM: dove: Move to ID based window creation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-dove/common.c | 68 ++++++++++++++++++++++++++++++---------------
1 file changed, 45 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 00247c7..bc22056 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
#include <plat/time.h>
#include "common.h"
+/* These can go away once Dove uses the mvebu-mbus DT binding */
+#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
+#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
+#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
+#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
+#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
+#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
+#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
+#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
+#define DOVE_MBUS_CESA_TARGET 0x3
+#define DOVE_MBUS_CESA_ATTR 0x1
+#define DOVE_MBUS_BOOTROM_TARGET 0x1
+#define DOVE_MBUS_BOOTROM_ATTR 0xfd
+#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
+#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
+
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
{
/*
* The PCIe windows will no longer be statically allocated
- * here once Dove is migrated to the pci-mvebu driver.
+ * here once Dove is migrated to the pci-mvebu driver. The
+ * non-PCIe windows will no longer be created here once Dove
+ * fully moves to DT.
*/
- mvebu_mbus_add_window_remap_flags("pcie0.0",
+ mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
+ DOVE_MBUS_PCIE0_IO_ATTR,
DOVE_PCIE0_IO_PHYS_BASE,
DOVE_PCIE0_IO_SIZE,
- DOVE_PCIE0_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
+ DOVE_PCIE0_IO_BUS_BASE);
+ mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
+ DOVE_MBUS_PCIE1_IO_ATTR,
DOVE_PCIE1_IO_PHYS_BASE,
DOVE_PCIE1_IO_SIZE,
- DOVE_PCIE1_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- DOVE_PCIE0_MEM_PHYS_BASE,
- DOVE_PCIE0_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
- DOVE_PCIE1_MEM_PHYS_BASE,
- DOVE_PCIE1_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
- DOVE_CESA_SIZE);
- mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
- DOVE_BOOTROM_SIZE);
- mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
- DOVE_SCRATCHPAD_SIZE);
+ DOVE_PCIE1_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
+ DOVE_MBUS_PCIE0_MEM_ATTR,
+ DOVE_PCIE0_MEM_PHYS_BASE,
+ DOVE_PCIE0_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
+ DOVE_MBUS_PCIE1_MEM_ATTR,
+ DOVE_PCIE1_MEM_PHYS_BASE,
+ DOVE_PCIE1_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
+ DOVE_MBUS_CESA_ATTR,
+ DOVE_CESA_PHYS_BASE,
+ DOVE_CESA_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
+ DOVE_MBUS_BOOTROM_ATTR,
+ DOVE_BOOTROM_PHYS_BASE,
+ DOVE_BOOTROM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
+ DOVE_MBUS_SCRATCHPAD_ATTR,
+ DOVE_SCRATCHPAD_PHYS_BASE,
+ DOVE_SCRATCHPAD_SIZE);
}
void __init dove_init(void)
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 06/21] ARM: dove: Move to ID based window creation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-dove/common.c | 68 ++++++++++++++++++++++++++++++---------------
1 file changed, 45 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 00247c7..bc22056 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
#include <plat/time.h>
#include "common.h"
+/* These can go away once Dove uses the mvebu-mbus DT binding */
+#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
+#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
+#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
+#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
+#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
+#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
+#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
+#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
+#define DOVE_MBUS_CESA_TARGET 0x3
+#define DOVE_MBUS_CESA_ATTR 0x1
+#define DOVE_MBUS_BOOTROM_TARGET 0x1
+#define DOVE_MBUS_BOOTROM_ATTR 0xfd
+#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
+#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
+
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
{
/*
* The PCIe windows will no longer be statically allocated
- * here once Dove is migrated to the pci-mvebu driver.
+ * here once Dove is migrated to the pci-mvebu driver. The
+ * non-PCIe windows will no longer be created here once Dove
+ * fully moves to DT.
*/
- mvebu_mbus_add_window_remap_flags("pcie0.0",
+ mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
+ DOVE_MBUS_PCIE0_IO_ATTR,
DOVE_PCIE0_IO_PHYS_BASE,
DOVE_PCIE0_IO_SIZE,
- DOVE_PCIE0_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
+ DOVE_PCIE0_IO_BUS_BASE);
+ mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
+ DOVE_MBUS_PCIE1_IO_ATTR,
DOVE_PCIE1_IO_PHYS_BASE,
DOVE_PCIE1_IO_SIZE,
- DOVE_PCIE1_IO_BUS_BASE,
- MVEBU_MBUS_PCI_IO);
- mvebu_mbus_add_window_remap_flags("pcie0.0",
- DOVE_PCIE0_MEM_PHYS_BASE,
- DOVE_PCIE0_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window_remap_flags("pcie1.0",
- DOVE_PCIE1_MEM_PHYS_BASE,
- DOVE_PCIE1_MEM_SIZE,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
- mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
- DOVE_CESA_SIZE);
- mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
- DOVE_BOOTROM_SIZE);
- mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
- DOVE_SCRATCHPAD_SIZE);
+ DOVE_PCIE1_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
+ DOVE_MBUS_PCIE0_MEM_ATTR,
+ DOVE_PCIE0_MEM_PHYS_BASE,
+ DOVE_PCIE0_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
+ DOVE_MBUS_PCIE1_MEM_ATTR,
+ DOVE_PCIE1_MEM_PHYS_BASE,
+ DOVE_PCIE1_MEM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
+ DOVE_MBUS_CESA_ATTR,
+ DOVE_CESA_PHYS_BASE,
+ DOVE_CESA_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
+ DOVE_MBUS_BOOTROM_ATTR,
+ DOVE_BOOTROM_PHYS_BASE,
+ DOVE_BOOTROM_SIZE);
+ mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
+ DOVE_MBUS_SCRATCHPAD_ATTR,
+ DOVE_SCRATCHPAD_PHYS_BASE,
+ DOVE_SCRATCHPAD_SIZE);
}
void __init dove_init(void)
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 07/21] bus: mvebu-mbus: Factor out initialization details
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
We introduce a common initialization function mvebu_mbus_common_init()
that will be used by both legacy and device-tree initialization code.
This patch is an intermediate step, which will allow to introduce the
DT binding for this driver in a less intrusive way.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 47 ++++++++++++++++++++++++++++++-----------------
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 827468a..1b17954 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -847,26 +847,14 @@ static __init int mvebu_mbus_debugfs_init(void)
}
fs_initcall(mvebu_mbus_debugfs_init);
-int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
- size_t mbuswins_size,
- phys_addr_t sdramwins_phys_base,
- size_t sdramwins_size)
+static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
+ phys_addr_t mbuswins_phys_base,
+ size_t mbuswins_size,
+ phys_addr_t sdramwins_phys_base,
+ size_t sdramwins_size)
{
- struct mvebu_mbus_state *mbus = &mbus_state;
- const struct of_device_id *of_id;
int win;
- for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
- if (!strcmp(of_id->compatible, soc))
- break;
-
- if (!of_id->compatible) {
- pr_err("could not find a matching SoC family\n");
- return -ENODEV;
- }
-
- mbus->soc = of_id->data;
-
mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
if (!mbus->mbuswins_base)
return -ENOMEM;
@@ -887,3 +875,28 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
return 0;
}
+
+int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
+ size_t mbuswins_size,
+ phys_addr_t sdramwins_phys_base,
+ size_t sdramwins_size)
+{
+ const struct of_device_id *of_id;
+
+ for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
+ if (!strcmp(of_id->compatible, soc))
+ break;
+
+ if (!of_id->compatible) {
+ pr_err("could not find a matching SoC family\n");
+ return -ENODEV;
+ }
+
+ mbus_state.soc = of_id->data;
+
+ return mvebu_mbus_common_init(&mbus_state,
+ mbuswins_phys_base,
+ mbuswins_size,
+ sdramwins_phys_base,
+ sdramwins_size);
+}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 07/21] bus: mvebu-mbus: Factor out initialization details
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
We introduce a common initialization function mvebu_mbus_common_init()
that will be used by both legacy and device-tree initialization code.
This patch is an intermediate step, which will allow to introduce the
DT binding for this driver in a less intrusive way.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 47 ++++++++++++++++++++++++++++++-----------------
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 827468a..1b17954 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -847,26 +847,14 @@ static __init int mvebu_mbus_debugfs_init(void)
}
fs_initcall(mvebu_mbus_debugfs_init);
-int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
- size_t mbuswins_size,
- phys_addr_t sdramwins_phys_base,
- size_t sdramwins_size)
+static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
+ phys_addr_t mbuswins_phys_base,
+ size_t mbuswins_size,
+ phys_addr_t sdramwins_phys_base,
+ size_t sdramwins_size)
{
- struct mvebu_mbus_state *mbus = &mbus_state;
- const struct of_device_id *of_id;
int win;
- for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
- if (!strcmp(of_id->compatible, soc))
- break;
-
- if (!of_id->compatible) {
- pr_err("could not find a matching SoC family\n");
- return -ENODEV;
- }
-
- mbus->soc = of_id->data;
-
mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
if (!mbus->mbuswins_base)
return -ENOMEM;
@@ -887,3 +875,28 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
return 0;
}
+
+int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
+ size_t mbuswins_size,
+ phys_addr_t sdramwins_phys_base,
+ size_t sdramwins_size)
+{
+ const struct of_device_id *of_id;
+
+ for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
+ if (!strcmp(of_id->compatible, soc))
+ break;
+
+ if (!of_id->compatible) {
+ pr_err("could not find a matching SoC family\n");
+ return -ENODEV;
+ }
+
+ mbus_state.soc = of_id->data;
+
+ return mvebu_mbus_common_init(&mbus_state,
+ mbuswins_phys_base,
+ mbuswins_size,
+ sdramwins_phys_base,
+ sdramwins_size);
+}
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 08/21] bus: mvebu-mbus: Introduce device tree binding
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
This patch adds the most fundamental device-tree initialization.
We only introduce what's required to be able to probe the mvebu-mbus
driver from the DT. Follow-up patches will extend the device tree binding,
allowing to describe static address decoding windows.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/mbus.h | 1 +
2 files changed, 50 insertions(+)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 1b17954..44a07c4 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -900,3 +900,52 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
sdramwins_phys_base,
sdramwins_size);
}
+
+#ifdef CONFIG_OF
+int __init mvebu_mbus_dt_init(void)
+{
+ struct resource mbuswins_res, sdramwins_res;
+ struct device_node *np, *controller;
+ const struct of_device_id *of_id;
+ const __be32 *prop;
+ int ret;
+
+ np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
+ if (!np) {
+ pr_err("could not find a matching SoC family\n");
+ return -ENODEV;
+ }
+
+ of_id = of_match_node(of_mvebu_mbus_ids, np);
+ mbus_state.soc = of_id->data;
+
+ prop = of_get_property(np, "controller", NULL);
+ if (!prop) {
+ pr_err("required 'controller' property missing\n");
+ return -EINVAL;
+ }
+
+ controller = of_find_node_by_phandle(be32_to_cpup(prop));
+ if (!controller) {
+ pr_err("could not find an 'mbus-controller' node\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(controller, 0, &mbuswins_res)) {
+ pr_err("cannot get MBUS register address\n");
+ return -EINVAL;
+ }
+
+ if (of_address_to_resource(controller, 1, &sdramwins_res)) {
+ pr_err("cannot get SDRAM register address\n");
+ return -EINVAL;
+ }
+
+ ret = mvebu_mbus_common_init(&mbus_state,
+ mbuswins_res.start,
+ resource_size(&mbuswins_res),
+ sdramwins_res.start,
+ resource_size(&sdramwins_res));
+ return ret;
+}
+#endif
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index 9245b66..eadefd6 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -74,5 +74,6 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size);
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
size_t mbus_size, phys_addr_t sdram_phys_base,
size_t sdram_size);
+int mvebu_mbus_dt_init(void);
#endif /* __LINUX_MBUS_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 08/21] bus: mvebu-mbus: Introduce device tree binding
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the most fundamental device-tree initialization.
We only introduce what's required to be able to probe the mvebu-mbus
driver from the DT. Follow-up patches will extend the device tree binding,
allowing to describe static address decoding windows.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/mbus.h | 1 +
2 files changed, 50 insertions(+)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 1b17954..44a07c4 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -900,3 +900,52 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
sdramwins_phys_base,
sdramwins_size);
}
+
+#ifdef CONFIG_OF
+int __init mvebu_mbus_dt_init(void)
+{
+ struct resource mbuswins_res, sdramwins_res;
+ struct device_node *np, *controller;
+ const struct of_device_id *of_id;
+ const __be32 *prop;
+ int ret;
+
+ np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
+ if (!np) {
+ pr_err("could not find a matching SoC family\n");
+ return -ENODEV;
+ }
+
+ of_id = of_match_node(of_mvebu_mbus_ids, np);
+ mbus_state.soc = of_id->data;
+
+ prop = of_get_property(np, "controller", NULL);
+ if (!prop) {
+ pr_err("required 'controller' property missing\n");
+ return -EINVAL;
+ }
+
+ controller = of_find_node_by_phandle(be32_to_cpup(prop));
+ if (!controller) {
+ pr_err("could not find an 'mbus-controller' node\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(controller, 0, &mbuswins_res)) {
+ pr_err("cannot get MBUS register address\n");
+ return -EINVAL;
+ }
+
+ if (of_address_to_resource(controller, 1, &sdramwins_res)) {
+ pr_err("cannot get SDRAM register address\n");
+ return -EINVAL;
+ }
+
+ ret = mvebu_mbus_common_init(&mbus_state,
+ mbuswins_res.start,
+ resource_size(&mbuswins_res),
+ sdramwins_res.start,
+ resource_size(&sdramwins_res));
+ return ret;
+}
+#endif
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index 9245b66..eadefd6 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -74,5 +74,6 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size);
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
size_t mbus_size, phys_addr_t sdram_phys_base,
size_t sdram_size);
+int mvebu_mbus_dt_init(void);
#endif /* __LINUX_MBUS_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 09/21] bus: mvebu-mbus: Add static window allocation to the binding
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
This patch adds static window allocation to the device tree binding.
Each first-child of the mbus-compatible node, with a suitable 'ranges'
property, declaring an address translation, will trigger an address
decoding window allocation.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
.../devicetree/bindings/bus/mvebu-mbus.txt | 253 +++++++++++++++++++++
drivers/bus/mvebu-mbus.c | 121 +++++++++-
2 files changed, 373 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/bus/mvebu-mbus.txt
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
new file mode 100644
index 0000000..cce863f
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
@@ -0,0 +1,253 @@
+
+* Marvell MBus
+
+Required properties:
+
+- compatible: Should be set to one of the following:
+ marvell,armada370-mbus
+ marvell,armadaxp-mbus
+
+- address-cells: Must be '2'. The first cell for the MBus ID encoding,
+ the second cell for the address offset within the window.
+
+- size-cells: Must be '1'.
+
+- ranges: Must be set up to provide a proper translation for each child.
+ See the examples below.
+
+- controller: Contains a single phandle referring to the MBus controller
+ node. This allows to specify the node that contains the
+ registers that control the MBus, which is typically contained
+ within the internal register window (see below).
+
+* Marvell MBus controller
+
+Required properties:
+
+- compatible: Should be set to "marvell,mbus-controller".
+
+- reg: Device's register space.
+ Two entries are expected (see the examples below):
+ the first one controls the devices decoding window and
+ the second one controls the SDRAM decoding window.
+
+Example:
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ internal-regs {
+ compatible = "simple-bus";
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* more children ...*/
+ };
+ };
+
+** MBus address decoding window specification
+
+The MBus children address space is comprised of two cells: the first one for
+the window ID and the second one for the offset within the window.
+In order to allow to describe valid and non-valid window entries, the
+following encoding is used:
+
+ 0xSIAA0000 0x00oooooo
+
+Where:
+
+ S = 0x0 for a MBus valid window
+ S = 0xf for a non-valid window (see below)
+
+If S = 0x0, then:
+
+ I = 4-bit window target ID
+ AA = windpw attribute
+
+If S = 0xf, then:
+
+ I = don't care
+ AA = 1 for internal register
+
+Following the above encoding, for each ranges entry for a MBus valid window
+(S = 0x0), an address decoding window is allocated. On the other side,
+entries for translation that do not correspond to valid windows (S = 0xf)
+are skipped.
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ ranges = <0xf0010000 0 0 0xd0000000 0x100000
+ 0x01e00000 0 0 0xfff00000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <0x01e00000 0 0x100000>;
+ };
+
+ /* other children */
+ ...
+
+ internal-regs {
+ compatible = "simple-bus";
+ ranges = <0 0xf0010000 0 0x100000>;
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* more children ...*/
+ };
+ };
+
+In the shown example, the translation entry in the 'ranges' property is what
+makes the MBus driver create a static decoding window for the corresponding
+given child device. Note that the binding does not require child nodes to be
+present. Of course, child nodes are needed to probe the devices.
+
+Since each window is identified by its target ID and attribute ID there's
+a special macro that can be use to simplify the translation entries:
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+Using this macro, the above example would be:
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+ };
+
+ /* other children */
+ ...
+
+ internal-regs {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* other children */
+ ...
+ };
+ };
+
+
+** About the window base address
+
+Remember the MBus controller allows a great deal of flexibility for choosing
+the decoding window base address. When planning the device tree layout it's
+possible to choose any address as the base address, provided of course there's
+a region large enough available, and with the required alignment.
+
+Yet in other words: there's nothing preventing us from setting a base address
+of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
+unused.
+
+** Window allocation policy
+
+The mbus-node ranges property defines a set of mbus windows that are expected
+to be set by the operating system and that are guaranteed to be free of overlaps
+with one another or with the system memory ranges.
+
+Each entry in the property refers to exactly one window. If the operating system
+choses to use a different set of mbus windows, it must ensure that any address
+translations performed from downstream devices are adapted accordingly.
+
+The operating system may insert additional mbus windows that do not conflict
+with the ones listed in the ranges, e.g. for mapping PCIe devices.
+As a special case, the internal register window must be set up by the boot
+loader at the address listed in the ranges property, since access to that region
+is needed to set up the other windows.
+
+** Example
+
+See the example below, where a more complete device tree is shown:
+
+ soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+ controller = <&mbusc>;
+
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
+ devbus-bootcs {
+ status = "okay";
+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
+
+ /* NOR */
+ nor {
+ compatible = "cfi-flash";
+ reg = <0 0x8000000>;
+ bank-width = <2>;
+ };
+ };
+
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "okay";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
+
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller@20000 {
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ interrupt-controller@20000 {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+ };
+ };
+ };
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 44a07c4..8aa3b45 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -902,6 +902,121 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
}
#ifdef CONFIG_OF
+/*
+ * The window IDs in the ranges DT property have the following format:
+ * - bits 28 to 31: MBus custom field
+ * - bits 24 to 27: window target ID
+ * - bits 16 to 23: window attribute ID
+ * - bits 0 to 15: unused
+ */
+#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
+#define TARGET(id) (((id) & 0x0F000000) >> 24)
+#define ATTR(id) (((id) & 0x00FF0000) >> 16)
+
+static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+ u32 base, u32 size,
+ u8 target, u8 attr)
+{
+ const struct mvebu_mbus_mapping *map = mbus->soc->map;
+ const char *name;
+ int i;
+
+ /* Search for a suitable window in the existing mappings */
+ for (i = 0; map[i].name; i++)
+ if (map[i].target == target &&
+ map[i].attr == (attr & map[i].attrmask))
+ break;
+
+ name = map[i].name;
+ if (!name) {
+ pr_err("window 0x%x:0x%x is unknown, skipping\n",
+ target, attr);
+ return -EINVAL;
+ }
+
+ if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+ pr_err("cannot add window '%s', conflicts with another window\n",
+ name);
+ return -EBUSY;
+ }
+
+ if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
+ target, attr)) {
+ pr_err("cannot add window '%s', too many windows\n",
+ name);
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+static int __init
+mbus_parse_ranges(struct device_node *node,
+ int *addr_cells, int *c_addr_cells, int *c_size_cells,
+ int *cell_count, const __be32 **ranges_start,
+ const __be32 **ranges_end)
+{
+ const __be32 *prop;
+ int ranges_len, tuple_len;
+
+ *addr_cells = of_n_addr_cells(node);
+
+ prop = of_get_property(node, "#address-cells", NULL);
+ *c_addr_cells = be32_to_cpup(prop);
+
+ prop = of_get_property(node, "#size-cells", NULL);
+ *c_size_cells = be32_to_cpup(prop);
+
+ *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
+ tuple_len = (*cell_count) * sizeof(__be32);
+
+ *ranges_start = of_get_property(node, "ranges", &ranges_len);
+ *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
+
+ if (*ranges_start == NULL || ranges_len % tuple_len) {
+ pr_warn("malformed ranges entry '%s'\n", node->name);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
+ struct device_node *np)
+{
+ int addr_cells, c_addr_cells, c_size_cells;
+ int i, ret, cell_count;
+ const __be32 *r, *ranges_start, *ranges_end;
+
+ ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
+ &c_size_cells, &cell_count,
+ &ranges_start, &ranges_end);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
+ u32 windowid, base, size;
+ u8 target, attr;
+
+ /*
+ * An entry with a non-zero custom field do not
+ * correspond to a static window, so skip it.
+ */
+ windowid = of_read_number(r, 1);
+ if (CUSTOM(windowid))
+ continue;
+
+ target = TARGET(windowid);
+ attr = ATTR(windowid);
+
+ base = of_read_number(r + c_addr_cells, addr_cells);
+ size = of_read_number(r + c_addr_cells + addr_cells,
+ c_size_cells);
+ ret = mbus_dt_setup_win(mbus, base, size, target, attr);
+ if (ret < 0)
+ return ret;
+ }
+ return 0;
+}
+
int __init mvebu_mbus_dt_init(void)
{
struct resource mbuswins_res, sdramwins_res;
@@ -946,6 +1061,10 @@ int __init mvebu_mbus_dt_init(void)
resource_size(&mbuswins_res),
sdramwins_res.start,
resource_size(&sdramwins_res));
- return ret;
+ if (ret)
+ return ret;
+
+ /* Setup statically declared windows in the DT */
+ return mbus_dt_setup(&mbus_state, np);
}
#endif
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 09/21] bus: mvebu-mbus: Add static window allocation to the binding
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds static window allocation to the device tree binding.
Each first-child of the mbus-compatible node, with a suitable 'ranges'
property, declaring an address translation, will trigger an address
decoding window allocation.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
.../devicetree/bindings/bus/mvebu-mbus.txt | 253 +++++++++++++++++++++
drivers/bus/mvebu-mbus.c | 121 +++++++++-
2 files changed, 373 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/bus/mvebu-mbus.txt
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
new file mode 100644
index 0000000..cce863f
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
@@ -0,0 +1,253 @@
+
+* Marvell MBus
+
+Required properties:
+
+- compatible: Should be set to one of the following:
+ marvell,armada370-mbus
+ marvell,armadaxp-mbus
+
+- address-cells: Must be '2'. The first cell for the MBus ID encoding,
+ the second cell for the address offset within the window.
+
+- size-cells: Must be '1'.
+
+- ranges: Must be set up to provide a proper translation for each child.
+ See the examples below.
+
+- controller: Contains a single phandle referring to the MBus controller
+ node. This allows to specify the node that contains the
+ registers that control the MBus, which is typically contained
+ within the internal register window (see below).
+
+* Marvell MBus controller
+
+Required properties:
+
+- compatible: Should be set to "marvell,mbus-controller".
+
+- reg: Device's register space.
+ Two entries are expected (see the examples below):
+ the first one controls the devices decoding window and
+ the second one controls the SDRAM decoding window.
+
+Example:
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ internal-regs {
+ compatible = "simple-bus";
+
+ mbusc: mbus-controller at 20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* more children ...*/
+ };
+ };
+
+** MBus address decoding window specification
+
+The MBus children address space is comprised of two cells: the first one for
+the window ID and the second one for the offset within the window.
+In order to allow to describe valid and non-valid window entries, the
+following encoding is used:
+
+ 0xSIAA0000 0x00oooooo
+
+Where:
+
+ S = 0x0 for a MBus valid window
+ S = 0xf for a non-valid window (see below)
+
+If S = 0x0, then:
+
+ I = 4-bit window target ID
+ AA = windpw attribute
+
+If S = 0xf, then:
+
+ I = don't care
+ AA = 1 for internal register
+
+Following the above encoding, for each ranges entry for a MBus valid window
+(S = 0x0), an address decoding window is allocated. On the other side,
+entries for translation that do not correspond to valid windows (S = 0xf)
+are skipped.
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ ranges = <0xf0010000 0 0 0xd0000000 0x100000
+ 0x01e00000 0 0 0xfff00000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <0x01e00000 0 0x100000>;
+ };
+
+ /* other children */
+ ...
+
+ internal-regs {
+ compatible = "simple-bus";
+ ranges = <0 0xf0010000 0 0x100000>;
+
+ mbusc: mbus-controller at 20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* more children ...*/
+ };
+ };
+
+In the shown example, the translation entry in the 'ranges' property is what
+makes the MBus driver create a static decoding window for the corresponding
+given child device. Note that the binding does not require child nodes to be
+present. Of course, child nodes are needed to probe the devices.
+
+Since each window is identified by its target ID and attribute ID there's
+a special macro that can be use to simplify the translation entries:
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+Using this macro, the above example would be:
+
+ soc {
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ controller = <&mbusc>;
+
+ ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+ };
+
+ /* other children */
+ ...
+
+ internal-regs {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller at 20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ /* other children */
+ ...
+ };
+ };
+
+
+** About the window base address
+
+Remember the MBus controller allows a great deal of flexibility for choosing
+the decoding window base address. When planning the device tree layout it's
+possible to choose any address as the base address, provided of course there's
+a region large enough available, and with the required alignment.
+
+Yet in other words: there's nothing preventing us from setting a base address
+of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
+unused.
+
+** Window allocation policy
+
+The mbus-node ranges property defines a set of mbus windows that are expected
+to be set by the operating system and that are guaranteed to be free of overlaps
+with one another or with the system memory ranges.
+
+Each entry in the property refers to exactly one window. If the operating system
+choses to use a different set of mbus windows, it must ensure that any address
+translations performed from downstream devices are adapted accordingly.
+
+The operating system may insert additional mbus windows that do not conflict
+with the ones listed in the ranges, e.g. for mapping PCIe devices.
+As a special case, the internal register window must be set up by the boot
+loader at the address listed in the ranges property, since access to that region
+is needed to set up the other windows.
+
+** Example
+
+See the example below, where a more complete device tree is shown:
+
+ soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+ controller = <&mbusc>;
+
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
+ devbus-bootcs {
+ status = "okay";
+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
+
+ /* NOR */
+ nor {
+ compatible = "cfi-flash";
+ reg = <0 0x8000000>;
+ bank-width = <2>;
+ };
+ };
+
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "okay";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
+
+
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller at 20000 {
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
+
+ interrupt-controller at 20000 {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+ };
+ };
+ };
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 44a07c4..8aa3b45 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -902,6 +902,121 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
}
#ifdef CONFIG_OF
+/*
+ * The window IDs in the ranges DT property have the following format:
+ * - bits 28 to 31: MBus custom field
+ * - bits 24 to 27: window target ID
+ * - bits 16 to 23: window attribute ID
+ * - bits 0 to 15: unused
+ */
+#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
+#define TARGET(id) (((id) & 0x0F000000) >> 24)
+#define ATTR(id) (((id) & 0x00FF0000) >> 16)
+
+static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+ u32 base, u32 size,
+ u8 target, u8 attr)
+{
+ const struct mvebu_mbus_mapping *map = mbus->soc->map;
+ const char *name;
+ int i;
+
+ /* Search for a suitable window in the existing mappings */
+ for (i = 0; map[i].name; i++)
+ if (map[i].target == target &&
+ map[i].attr == (attr & map[i].attrmask))
+ break;
+
+ name = map[i].name;
+ if (!name) {
+ pr_err("window 0x%x:0x%x is unknown, skipping\n",
+ target, attr);
+ return -EINVAL;
+ }
+
+ if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+ pr_err("cannot add window '%s', conflicts with another window\n",
+ name);
+ return -EBUSY;
+ }
+
+ if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
+ target, attr)) {
+ pr_err("cannot add window '%s', too many windows\n",
+ name);
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+static int __init
+mbus_parse_ranges(struct device_node *node,
+ int *addr_cells, int *c_addr_cells, int *c_size_cells,
+ int *cell_count, const __be32 **ranges_start,
+ const __be32 **ranges_end)
+{
+ const __be32 *prop;
+ int ranges_len, tuple_len;
+
+ *addr_cells = of_n_addr_cells(node);
+
+ prop = of_get_property(node, "#address-cells", NULL);
+ *c_addr_cells = be32_to_cpup(prop);
+
+ prop = of_get_property(node, "#size-cells", NULL);
+ *c_size_cells = be32_to_cpup(prop);
+
+ *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
+ tuple_len = (*cell_count) * sizeof(__be32);
+
+ *ranges_start = of_get_property(node, "ranges", &ranges_len);
+ *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
+
+ if (*ranges_start == NULL || ranges_len % tuple_len) {
+ pr_warn("malformed ranges entry '%s'\n", node->name);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
+ struct device_node *np)
+{
+ int addr_cells, c_addr_cells, c_size_cells;
+ int i, ret, cell_count;
+ const __be32 *r, *ranges_start, *ranges_end;
+
+ ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
+ &c_size_cells, &cell_count,
+ &ranges_start, &ranges_end);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
+ u32 windowid, base, size;
+ u8 target, attr;
+
+ /*
+ * An entry with a non-zero custom field do not
+ * correspond to a static window, so skip it.
+ */
+ windowid = of_read_number(r, 1);
+ if (CUSTOM(windowid))
+ continue;
+
+ target = TARGET(windowid);
+ attr = ATTR(windowid);
+
+ base = of_read_number(r + c_addr_cells, addr_cells);
+ size = of_read_number(r + c_addr_cells + addr_cells,
+ c_size_cells);
+ ret = mbus_dt_setup_win(mbus, base, size, target, attr);
+ if (ret < 0)
+ return ret;
+ }
+ return 0;
+}
+
int __init mvebu_mbus_dt_init(void)
{
struct resource mbuswins_res, sdramwins_res;
@@ -946,6 +1061,10 @@ int __init mvebu_mbus_dt_init(void)
resource_size(&mbuswins_res),
sdramwins_res.start,
resource_size(&sdramwins_res));
- return ret;
+ if (ret)
+ return ret;
+
+ /* Setup statically declared windows in the DT */
+ return mbus_dt_setup(&mbus_state, np);
}
#endif
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 10/21] pci: mvebu: Adapt to the new device tree layout
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
The new device tree layout encodes the window's target ID and attribute
in the PCIe controller node's ranges property. This allows to parse
such entries to obtain such information and use the recently introduced
MBus API to create the windows, instead of using the current name based
scheme.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/pci/host/pci-mvebu.c | 152 ++++++++++++++++++++++++++++++++++---------
1 file changed, 120 insertions(+), 32 deletions(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 13a633b..a146f44 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -123,6 +123,10 @@ struct mvebu_pcie_port {
u32 port;
u32 lane;
int devfn;
+ unsigned int mem_target;
+ unsigned int mem_attr;
+ unsigned int io_target;
+ unsigned int io_attr;
struct clk *clk;
struct mvebu_sw_pci_bridge bridge;
struct device_node *dn;
@@ -307,10 +311,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
(port->bridge.iolimitupper << 16)) -
iobase);
- mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
- port->iowin_size,
- iobase,
- MVEBU_MBUS_PCI_IO);
+ mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
+ port->iowin_base, port->iowin_size,
+ iobase);
pci_ioremap_io(iobase, port->iowin_base);
}
@@ -342,10 +345,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
port->memwin_base;
- mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
- port->memwin_size,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
+ port->memwin_base, port->memwin_size);
}
/*
@@ -755,12 +756,104 @@ mvebu_pcie_map_registers(struct platform_device *pdev,
return devm_request_and_ioremap(&pdev->dev, ®s);
}
+#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
+#define DT_TYPE_IO 0x1
+#define DT_TYPE_MEM32 0x2
+#define DT_FLAGS_TO_DEVFN(flags) (((flags) >> 8) & 0xFF)
+#define DT_CPUADDR_TO_ADDR(cpuaddr) ((cpuaddr) & 0xFFFFFFFF)
+#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
+#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
+
+static int mvebu_get_resources(struct device_node *np, struct resource *mem,
+ struct resource *io, struct resource *realio)
+{
+ const int na = 3, ns = 2;
+ const __be32 *range;
+ int rlen, nranges, rangesz, pna, i;
+
+ range = of_get_property(np, "ranges", &rlen);
+ if (!range)
+ return -EINVAL;
+
+ pna = of_n_addr_cells(np);
+ rangesz = pna + na + ns;
+ nranges = rlen / sizeof(__be32) / rangesz;
+
+ for (i = 0; i < nranges; i++) {
+ u32 flags = of_read_number(range, 1);
+ u64 pciaddr = of_read_number(range + 1, ns);
+ u64 cpuaddr = of_read_number(range + na, pna);
+ u64 size = of_read_number(range + na + pna, ns);
+
+ /* I/O */
+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO &&
+ DT_FLAGS_TO_DEVFN(flags) != 0) {
+ io->start = cpuaddr & 0xFFFFFFFF;
+ io->end = io->start + size;
+ io->flags = IORESOURCE_IO;
+ realio->start = max_t(resource_size_t,
+ PCIBIOS_MIN_IO,
+ pciaddr);
+ realio->end = min_t(resource_size_t,
+ IO_SPACE_LIMIT,
+ pciaddr + size);
+ realio->flags = io->flags;
+ }
+ /* MEM */
+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32 &&
+ DT_FLAGS_TO_DEVFN(flags) != 0) {
+ mem->start = cpuaddr & 0xFFFFFFFF;
+ mem->end = mem->start + size;
+ mem->flags = IORESOURCE_MEM;
+ }
+
+ range += rangesz;
+ }
+
+ return 0;
+}
+
+static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
+ unsigned long type, int *tgt, int *attr)
+{
+ const int na = 3, ns = 2;
+ const __be32 *range;
+ int rlen, nranges, rangesz, pna, i;
+
+ range = of_get_property(np, "ranges", &rlen);
+ if (!range)
+ return -EINVAL;
+
+ pna = of_n_addr_cells(np);
+ rangesz = pna + na + ns;
+ nranges = rlen / sizeof(__be32) / rangesz;
+
+ for (i = 0; i < nranges; i++) {
+ u32 flags = of_read_number(range, 1);
+ u64 cpuaddr = of_read_number(range + na, pna);
+ unsigned long rtype;
+
+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
+ rtype = IORESOURCE_IO;
+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
+ rtype = IORESOURCE_MEM;
+
+ if (DT_FLAGS_TO_DEVFN(flags) == devfn && type == rtype) {
+ *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
+ *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
+ return 0;
+ }
+
+ range += rangesz;
+ }
+
+ return -ENOENT;
+}
+
static int __init mvebu_pcie_probe(struct platform_device *pdev)
{
struct mvebu_pcie *pcie;
struct device_node *np = pdev->dev.of_node;
- struct of_pci_range range;
- struct of_pci_range_parser parser;
struct device_node *child;
int i, ret;
@@ -771,28 +864,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
pcie->pdev = pdev;
- if (of_pci_range_parser_init(&parser, np))
- return -EINVAL;
-
- /* Get the I/O and memory ranges from DT */
- for_each_of_pci_range(&parser, &range) {
- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
- if (restype == IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &pcie->io);
- of_pci_range_to_resource(&range, np, &pcie->realio);
- pcie->io.name = "I/O";
- pcie->realio.start = max_t(resource_size_t,
- PCIBIOS_MIN_IO,
- range.pci_addr);
- pcie->realio.end = min_t(resource_size_t,
- IO_SPACE_LIMIT,
- range.pci_addr + range.size);
- }
- if (restype == IORESOURCE_MEM) {
- of_pci_range_to_resource(&range, np, &pcie->mem);
- pcie->mem.name = "MEM";
- }
- }
+ mvebu_get_resources(np, &pcie->mem, &pcie->io, &pcie->realio);
/* Get the bus range */
ret = of_pci_parse_bus_range(np, &pcie->busn);
@@ -841,6 +913,22 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
if (port->devfn < 0)
continue;
+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
+ &port->mem_target, &port->mem_attr);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
+ port->port, port->lane);
+ continue;
+ }
+
+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
+ &port->io_target, &port->io_attr);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
+ port->port, port->lane);
+ continue;
+ }
+
port->base = mvebu_pcie_map_registers(pdev, child, port);
if (!port->base) {
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 10/21] pci: mvebu: Adapt to the new device tree layout
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The new device tree layout encodes the window's target ID and attribute
in the PCIe controller node's ranges property. This allows to parse
such entries to obtain such information and use the recently introduced
MBus API to create the windows, instead of using the current name based
scheme.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-mvebu.c | 152 ++++++++++++++++++++++++++++++++++---------
1 file changed, 120 insertions(+), 32 deletions(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 13a633b..a146f44 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -123,6 +123,10 @@ struct mvebu_pcie_port {
u32 port;
u32 lane;
int devfn;
+ unsigned int mem_target;
+ unsigned int mem_attr;
+ unsigned int io_target;
+ unsigned int io_attr;
struct clk *clk;
struct mvebu_sw_pci_bridge bridge;
struct device_node *dn;
@@ -307,10 +311,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
(port->bridge.iolimitupper << 16)) -
iobase);
- mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
- port->iowin_size,
- iobase,
- MVEBU_MBUS_PCI_IO);
+ mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
+ port->iowin_base, port->iowin_size,
+ iobase);
pci_ioremap_io(iobase, port->iowin_base);
}
@@ -342,10 +345,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
port->memwin_base;
- mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
- port->memwin_size,
- MVEBU_MBUS_NO_REMAP,
- MVEBU_MBUS_PCI_MEM);
+ mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
+ port->memwin_base, port->memwin_size);
}
/*
@@ -755,12 +756,104 @@ mvebu_pcie_map_registers(struct platform_device *pdev,
return devm_request_and_ioremap(&pdev->dev, ®s);
}
+#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
+#define DT_TYPE_IO 0x1
+#define DT_TYPE_MEM32 0x2
+#define DT_FLAGS_TO_DEVFN(flags) (((flags) >> 8) & 0xFF)
+#define DT_CPUADDR_TO_ADDR(cpuaddr) ((cpuaddr) & 0xFFFFFFFF)
+#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
+#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
+
+static int mvebu_get_resources(struct device_node *np, struct resource *mem,
+ struct resource *io, struct resource *realio)
+{
+ const int na = 3, ns = 2;
+ const __be32 *range;
+ int rlen, nranges, rangesz, pna, i;
+
+ range = of_get_property(np, "ranges", &rlen);
+ if (!range)
+ return -EINVAL;
+
+ pna = of_n_addr_cells(np);
+ rangesz = pna + na + ns;
+ nranges = rlen / sizeof(__be32) / rangesz;
+
+ for (i = 0; i < nranges; i++) {
+ u32 flags = of_read_number(range, 1);
+ u64 pciaddr = of_read_number(range + 1, ns);
+ u64 cpuaddr = of_read_number(range + na, pna);
+ u64 size = of_read_number(range + na + pna, ns);
+
+ /* I/O */
+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO &&
+ DT_FLAGS_TO_DEVFN(flags) != 0) {
+ io->start = cpuaddr & 0xFFFFFFFF;
+ io->end = io->start + size;
+ io->flags = IORESOURCE_IO;
+ realio->start = max_t(resource_size_t,
+ PCIBIOS_MIN_IO,
+ pciaddr);
+ realio->end = min_t(resource_size_t,
+ IO_SPACE_LIMIT,
+ pciaddr + size);
+ realio->flags = io->flags;
+ }
+ /* MEM */
+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32 &&
+ DT_FLAGS_TO_DEVFN(flags) != 0) {
+ mem->start = cpuaddr & 0xFFFFFFFF;
+ mem->end = mem->start + size;
+ mem->flags = IORESOURCE_MEM;
+ }
+
+ range += rangesz;
+ }
+
+ return 0;
+}
+
+static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
+ unsigned long type, int *tgt, int *attr)
+{
+ const int na = 3, ns = 2;
+ const __be32 *range;
+ int rlen, nranges, rangesz, pna, i;
+
+ range = of_get_property(np, "ranges", &rlen);
+ if (!range)
+ return -EINVAL;
+
+ pna = of_n_addr_cells(np);
+ rangesz = pna + na + ns;
+ nranges = rlen / sizeof(__be32) / rangesz;
+
+ for (i = 0; i < nranges; i++) {
+ u32 flags = of_read_number(range, 1);
+ u64 cpuaddr = of_read_number(range + na, pna);
+ unsigned long rtype;
+
+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
+ rtype = IORESOURCE_IO;
+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
+ rtype = IORESOURCE_MEM;
+
+ if (DT_FLAGS_TO_DEVFN(flags) == devfn && type == rtype) {
+ *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
+ *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
+ return 0;
+ }
+
+ range += rangesz;
+ }
+
+ return -ENOENT;
+}
+
static int __init mvebu_pcie_probe(struct platform_device *pdev)
{
struct mvebu_pcie *pcie;
struct device_node *np = pdev->dev.of_node;
- struct of_pci_range range;
- struct of_pci_range_parser parser;
struct device_node *child;
int i, ret;
@@ -771,28 +864,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
pcie->pdev = pdev;
- if (of_pci_range_parser_init(&parser, np))
- return -EINVAL;
-
- /* Get the I/O and memory ranges from DT */
- for_each_of_pci_range(&parser, &range) {
- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
- if (restype == IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &pcie->io);
- of_pci_range_to_resource(&range, np, &pcie->realio);
- pcie->io.name = "I/O";
- pcie->realio.start = max_t(resource_size_t,
- PCIBIOS_MIN_IO,
- range.pci_addr);
- pcie->realio.end = min_t(resource_size_t,
- IO_SPACE_LIMIT,
- range.pci_addr + range.size);
- }
- if (restype == IORESOURCE_MEM) {
- of_pci_range_to_resource(&range, np, &pcie->mem);
- pcie->mem.name = "MEM";
- }
- }
+ mvebu_get_resources(np, &pcie->mem, &pcie->io, &pcie->realio);
/* Get the bus range */
ret = of_pci_parse_bus_range(np, &pcie->busn);
@@ -841,6 +913,22 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
if (port->devfn < 0)
continue;
+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
+ &port->mem_target, &port->mem_attr);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
+ port->port, port->lane);
+ continue;
+ }
+
+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
+ &port->io_target, &port->io_attr);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
+ port->port, port->lane);
+ continue;
+ }
+
port->base = mvebu_pcie_map_registers(pdev, child, port);
if (!port->base) {
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 11/21] bus: mvebu-mbus: Remove the no longer used name-based API
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Now that every user of the deprecated name-based API has been
converted to using the ID-based API, let's remove the former one.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 38 --------------------------------------
include/linux/mbus.h | 5 -----
2 files changed, 43 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 8aa3b45..db68436 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -764,44 +764,6 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
}
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags)
-{
- struct mvebu_mbus_state *s = &mbus_state;
- u8 target, attr;
- int i;
-
- if (!s->soc->map)
- return -ENODEV;
-
- for (i = 0; s->soc->map[i].name; i++)
- if (!strcmp(s->soc->map[i].name, devname))
- break;
-
- if (!s->soc->map[i].name) {
- pr_err("unknown device '%s'\n", devname);
- return -ENODEV;
- }
-
- target = s->soc->map[i].target;
- attr = s->soc->map[i].attr;
-
- if (flags == MVEBU_MBUS_PCI_MEM)
- attr |= 0x8;
- else if (flags == MVEBU_MBUS_PCI_WA)
- attr |= 0x28;
-
- return mvebu_mbus_add_window_remap_by_id(target, attr, base,
- size, remap);
-}
-
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
-{
- return mvebu_mbus_add_window_remap_flags(devname, base, size,
- MVEBU_MBUS_NO_REMAP, 0);
-}
-
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size)
{
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index eadefd6..fa84dcb 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -59,15 +59,10 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
}
#endif
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags);
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
unsigned int attribute,
phys_addr_t base, size_t size,
phys_addr_t remap);
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
- size_t size);
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 11/21] bus: mvebu-mbus: Remove the no longer used name-based API
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Now that every user of the deprecated name-based API has been
converted to using the ID-based API, let's remove the former one.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 38 --------------------------------------
include/linux/mbus.h | 5 -----
2 files changed, 43 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 8aa3b45..db68436 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -764,44 +764,6 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
}
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags)
-{
- struct mvebu_mbus_state *s = &mbus_state;
- u8 target, attr;
- int i;
-
- if (!s->soc->map)
- return -ENODEV;
-
- for (i = 0; s->soc->map[i].name; i++)
- if (!strcmp(s->soc->map[i].name, devname))
- break;
-
- if (!s->soc->map[i].name) {
- pr_err("unknown device '%s'\n", devname);
- return -ENODEV;
- }
-
- target = s->soc->map[i].target;
- attr = s->soc->map[i].attr;
-
- if (flags == MVEBU_MBUS_PCI_MEM)
- attr |= 0x8;
- else if (flags == MVEBU_MBUS_PCI_WA)
- attr |= 0x28;
-
- return mvebu_mbus_add_window_remap_by_id(target, attr, base,
- size, remap);
-}
-
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
-{
- return mvebu_mbus_add_window_remap_flags(devname, base, size,
- MVEBU_MBUS_NO_REMAP, 0);
-}
-
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size)
{
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index eadefd6..fa84dcb 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -59,15 +59,10 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
}
#endif
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags);
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
unsigned int attribute,
phys_addr_t base, size_t size,
phys_addr_t remap);
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
- size_t size);
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 12/21] bus: mvebu-mbus: Remove name -> target, attribute mapping tables
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
This tables were used together with the name-based MBus window
creation API. Since that's has been removed, we can also remove
the tables.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 150 +++--------------------------------------------
1 file changed, 7 insertions(+), 143 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index db68436..8240bd7 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -97,33 +97,6 @@
#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
-struct mvebu_mbus_mapping {
- const char *name;
- u8 target;
- u8 attr;
- u8 attrmask;
-};
-
-/*
- * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
- * allow to get the real attribute value, discarding the special bits
- * used to select a PCI MEM region or a PCI WA region. This allows the
- * debugfs code to reverse-match the name of a device from its
- * target/attr values.
- *
- * For all devices except PCI, all bits of 'attr' must be
- * considered. For most SoCs, only bit 3 should be ignored (it allows
- * to select between PCI MEM and PCI I/O). On Orion5x however, there
- * is the special bit 5 to select a PCI WA region.
- */
-#define MAPDEF_NOMASK 0xff
-#define MAPDEF_PCIMASK 0xf7
-#define MAPDEF_ORIONPCIMASK 0xd7
-
-/* Macro used to define one mvebu_mbus_mapping entry */
-#define MAPDEF(__n, __t, __a, __m) \
- { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
-
struct mvebu_mbus_state;
struct mvebu_mbus_soc_data {
@@ -133,7 +106,6 @@ struct mvebu_mbus_soc_data {
void (*setup_cpu_target)(struct mvebu_mbus_state *s);
int (*show_cpu_target)(struct mvebu_mbus_state *s,
struct seq_file *seq, void *v);
- const struct mvebu_mbus_mapping *map;
};
struct mvebu_mbus_state {
@@ -428,8 +400,7 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
u64 wbase, wremap;
u32 wsize;
u8 wtarget, wattr;
- int enabled, i;
- const char *name;
+ int enabled;
mvebu_mbus_read_window(mbus, win,
&enabled, &wbase, &wsize,
@@ -440,18 +411,9 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
continue;
}
-
- for (i = 0; mbus->soc->map[i].name; i++)
- if (mbus->soc->map[i].target == wtarget &&
- mbus->soc->map[i].attr ==
- (wattr & mbus->soc->map[i].attrmask))
- break;
-
- name = mbus->soc->map[i].name ?: "unknown";
-
- seq_printf(seq, "[%02d] %016llx - %016llx : %s",
+ seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x\n",
win, (unsigned long long)wbase,
- (unsigned long long)(wbase + wsize), name);
+ (unsigned long long)(wbase + wsize), wtarget, wattr);
if (win < mbus->soc->num_remappable_wins) {
seq_printf(seq, " (remap %016llx)\n",
@@ -576,45 +538,12 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
mvebu_mbus_dram_info.num_cs = cs;
}
-static const struct mvebu_mbus_mapping armada_370_map[] = {
- MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- {},
-};
-
static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
.num_wins = 20,
.num_remappable_wins = 8,
.win_cfg_offset = armada_370_xp_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = armada_370_map,
-};
-
-static const struct mvebu_mbus_mapping armada_xp_map[] = {
- MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
- {},
};
static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
@@ -623,15 +552,6 @@ static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
.win_cfg_offset = armada_370_xp_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = armada_xp_map,
-};
-
-static const struct mvebu_mbus_mapping kirkwood_map[] = {
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
- MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
- {},
};
static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
@@ -640,16 +560,6 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = kirkwood_map,
-};
-
-static const struct mvebu_mbus_mapping dove_map[] = {
- MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
- MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
- MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
- {},
};
static const struct mvebu_mbus_soc_data dove_mbus_data = {
@@ -658,18 +568,6 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_dove,
- .map = dove_map,
-};
-
-static const struct mvebu_mbus_mapping orion5x_map[] = {
- MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
- MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
- MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
- MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
- {},
};
/*
@@ -682,7 +580,6 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = orion5x_map,
};
static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
@@ -691,21 +588,6 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = orion5x_map,
-};
-
-static const struct mvebu_mbus_mapping mv78xx0_map[] = {
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
- {},
};
static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
@@ -714,7 +596,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
.win_cfg_offset = mv78xx0_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = mv78xx0_map,
};
/*
@@ -879,33 +760,16 @@ static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
u32 base, u32 size,
u8 target, u8 attr)
{
- const struct mvebu_mbus_mapping *map = mbus->soc->map;
- const char *name;
- int i;
-
- /* Search for a suitable window in the existing mappings */
- for (i = 0; map[i].name; i++)
- if (map[i].target == target &&
- map[i].attr == (attr & map[i].attrmask))
- break;
-
- name = map[i].name;
- if (!name) {
- pr_err("window 0x%x:0x%x is unknown, skipping\n",
- target, attr);
- return -EINVAL;
- }
-
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
- pr_err("cannot add window '%s', conflicts with another window\n",
- name);
+ pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
+ target, attr);
return -EBUSY;
}
if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
target, attr)) {
- pr_err("cannot add window '%s', too many windows\n",
- name);
+ pr_err("cannot add window '%04x:%04x', too many windows\n",
+ target, attr);
return -ENOMEM;
}
return 0;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 12/21] bus: mvebu-mbus: Remove name -> target, attribute mapping tables
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This tables were used together with the name-based MBus window
creation API. Since that's has been removed, we can also remove
the tables.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 150 +++--------------------------------------------
1 file changed, 7 insertions(+), 143 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index db68436..8240bd7 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -97,33 +97,6 @@
#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
-struct mvebu_mbus_mapping {
- const char *name;
- u8 target;
- u8 attr;
- u8 attrmask;
-};
-
-/*
- * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
- * allow to get the real attribute value, discarding the special bits
- * used to select a PCI MEM region or a PCI WA region. This allows the
- * debugfs code to reverse-match the name of a device from its
- * target/attr values.
- *
- * For all devices except PCI, all bits of 'attr' must be
- * considered. For most SoCs, only bit 3 should be ignored (it allows
- * to select between PCI MEM and PCI I/O). On Orion5x however, there
- * is the special bit 5 to select a PCI WA region.
- */
-#define MAPDEF_NOMASK 0xff
-#define MAPDEF_PCIMASK 0xf7
-#define MAPDEF_ORIONPCIMASK 0xd7
-
-/* Macro used to define one mvebu_mbus_mapping entry */
-#define MAPDEF(__n, __t, __a, __m) \
- { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
-
struct mvebu_mbus_state;
struct mvebu_mbus_soc_data {
@@ -133,7 +106,6 @@ struct mvebu_mbus_soc_data {
void (*setup_cpu_target)(struct mvebu_mbus_state *s);
int (*show_cpu_target)(struct mvebu_mbus_state *s,
struct seq_file *seq, void *v);
- const struct mvebu_mbus_mapping *map;
};
struct mvebu_mbus_state {
@@ -428,8 +400,7 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
u64 wbase, wremap;
u32 wsize;
u8 wtarget, wattr;
- int enabled, i;
- const char *name;
+ int enabled;
mvebu_mbus_read_window(mbus, win,
&enabled, &wbase, &wsize,
@@ -440,18 +411,9 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
continue;
}
-
- for (i = 0; mbus->soc->map[i].name; i++)
- if (mbus->soc->map[i].target == wtarget &&
- mbus->soc->map[i].attr ==
- (wattr & mbus->soc->map[i].attrmask))
- break;
-
- name = mbus->soc->map[i].name ?: "unknown";
-
- seq_printf(seq, "[%02d] %016llx - %016llx : %s",
+ seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x\n",
win, (unsigned long long)wbase,
- (unsigned long long)(wbase + wsize), name);
+ (unsigned long long)(wbase + wsize), wtarget, wattr);
if (win < mbus->soc->num_remappable_wins) {
seq_printf(seq, " (remap %016llx)\n",
@@ -576,45 +538,12 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
mvebu_mbus_dram_info.num_cs = cs;
}
-static const struct mvebu_mbus_mapping armada_370_map[] = {
- MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- {},
-};
-
static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
.num_wins = 20,
.num_remappable_wins = 8,
.win_cfg_offset = armada_370_xp_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = armada_370_map,
-};
-
-static const struct mvebu_mbus_mapping armada_xp_map[] = {
- MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
- {},
};
static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
@@ -623,15 +552,6 @@ static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
.win_cfg_offset = armada_370_xp_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = armada_xp_map,
-};
-
-static const struct mvebu_mbus_mapping kirkwood_map[] = {
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
- MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
- {},
};
static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
@@ -640,16 +560,6 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = kirkwood_map,
-};
-
-static const struct mvebu_mbus_mapping dove_map[] = {
- MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
- MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
- MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
- {},
};
static const struct mvebu_mbus_soc_data dove_mbus_data = {
@@ -658,18 +568,6 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_dove,
- .map = dove_map,
-};
-
-static const struct mvebu_mbus_mapping orion5x_map[] = {
- MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
- MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
- MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
- MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
- MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
- MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
- MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
- {},
};
/*
@@ -682,7 +580,6 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = orion5x_map,
};
static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
@@ -691,21 +588,6 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
.win_cfg_offset = orion_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = orion5x_map,
-};
-
-static const struct mvebu_mbus_mapping mv78xx0_map[] = {
- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
- {},
};
static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
@@ -714,7 +596,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
.win_cfg_offset = mv78xx0_mbus_win_offset,
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
.show_cpu_target = mvebu_sdram_debug_show_orion,
- .map = mv78xx0_map,
};
/*
@@ -879,33 +760,16 @@ static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
u32 base, u32 size,
u8 target, u8 attr)
{
- const struct mvebu_mbus_mapping *map = mbus->soc->map;
- const char *name;
- int i;
-
- /* Search for a suitable window in the existing mappings */
- for (i = 0; map[i].name; i++)
- if (map[i].target == target &&
- map[i].attr == (attr & map[i].attrmask))
- break;
-
- name = map[i].name;
- if (!name) {
- pr_err("window 0x%x:0x%x is unknown, skipping\n",
- target, attr);
- return -EINVAL;
- }
-
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
- pr_err("cannot add window '%s', conflicts with another window\n",
- name);
+ pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
+ target, attr);
return -EBUSY;
}
if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
target, attr)) {
- pr_err("cannot add window '%s', too many windows\n",
- name);
+ pr_err("cannot add window '%04x:%04x', too many windows\n",
+ target, attr);
return -ENOMEM;
}
return 0;
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 13/21] bus: mvebu-mbus: Update main description
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
After replacing the MBus name-based by the new ID-based API
let's fix the general description of the driver at the beginning
of the file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 8240bd7..58d3c8f 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -35,13 +35,9 @@
*
* - Provides an API for platform code or device drivers to
* dynamically add or remove address decoding windows for the CPU ->
- * device accesses. This API is mvebu_mbus_add_window(),
- * mvebu_mbus_add_window_remap_flags() and
- * mvebu_mbus_del_window(). Since the (target, attribute) values
- * differ from one SoC family to another, the API uses a 'const char
- * *' string to identify devices, and this driver is responsible for
- * knowing the mapping between the name of a device and its
- * corresponding (target, attribute) in the current SoC family.
+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
+ * mvebu_mbus_add_window_remap_by_id() and
+ * mvebu_mbus_del_window().
*
* - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
* see the list of CPU -> SDRAM windows and their configuration
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 13/21] bus: mvebu-mbus: Update main description
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
After replacing the MBus name-based by the new ID-based API
let's fix the general description of the driver at the beginning
of the file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 8240bd7..58d3c8f 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -35,13 +35,9 @@
*
* - Provides an API for platform code or device drivers to
* dynamically add or remove address decoding windows for the CPU ->
- * device accesses. This API is mvebu_mbus_add_window(),
- * mvebu_mbus_add_window_remap_flags() and
- * mvebu_mbus_del_window(). Since the (target, attribute) values
- * differ from one SoC family to another, the API uses a 'const char
- * *' string to identify devices, and this driver is responsible for
- * knowing the mapping between the name of a device and its
- * corresponding (target, attribute) in the current SoC family.
+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
+ * mvebu_mbus_add_window_remap_by_id() and
+ * mvebu_mbus_del_window().
*
* - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
* see the list of CPU -> SDRAM windows and their configuration
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 14/21] bus: mvebu-mbus: Factorize Armada 370/XP data structures
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
From: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
These structures were only different in the mapping tables.
Now that those tables have been removed, it doesn't make any sense
to keep different structures.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/bus/mvebu-mbus.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 58d3c8f..0b7f9f7 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -534,15 +534,7 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
mvebu_mbus_dram_info.num_cs = cs;
}
-static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
- .num_wins = 20,
- .num_remappable_wins = 8,
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-};
-
-static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
+static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
.num_wins = 20,
.num_remappable_wins = 8,
.win_cfg_offset = armada_370_xp_mbus_win_offset,
@@ -602,9 +594,9 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
*/
static const struct of_device_id of_mvebu_mbus_ids[] = {
{ .compatible = "marvell,armada370-mbus",
- .data = &armada_370_mbus_data, },
+ .data = &armada_370_xp_mbus_data, },
{ .compatible = "marvell,armadaxp-mbus",
- .data = &armada_xp_mbus_data, },
+ .data = &armada_370_xp_mbus_data, },
{ .compatible = "marvell,kirkwood-mbus",
.data = &kirkwood_mbus_data, },
{ .compatible = "marvell,dove-mbus",
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 14/21] bus: mvebu-mbus: Factorize Armada 370/XP data structures
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
These structures were only different in the mapping tables.
Now that those tables have been removed, it doesn't make any sense
to keep different structures.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/bus/mvebu-mbus.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 58d3c8f..0b7f9f7 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -534,15 +534,7 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
mvebu_mbus_dram_info.num_cs = cs;
}
-static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
- .num_wins = 20,
- .num_remappable_wins = 8,
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-};
-
-static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
+static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
.num_wins = 20,
.num_remappable_wins = 8,
.win_cfg_offset = armada_370_xp_mbus_win_offset,
@@ -602,9 +594,9 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
*/
static const struct of_device_id of_mvebu_mbus_ids[] = {
{ .compatible = "marvell,armada370-mbus",
- .data = &armada_370_mbus_data, },
+ .data = &armada_370_xp_mbus_data, },
{ .compatible = "marvell,armadaxp-mbus",
- .data = &armada_xp_mbus_data, },
+ .data = &armada_370_xp_mbus_data, },
{ .compatible = "marvell,kirkwood-mbus",
.data = &kirkwood_mbus_data, },
{ .compatible = "marvell,dove-mbus",
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 15/21] ARM: mvebu: Remove the harcoded BootROM window allocation
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
The address decoding window to access the BootROM should not be
allocated programatically, but instead declared in the device tree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-mvebu/platsmp.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index ce81d30..7be1ec2 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/mbus.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
#include "pmsu.h"
#include "coherency.h"
+#define AXP_BOOTROM_BASE 0xfff00000
+#define AXP_BOOTROM_SIZE 0x100000
+
void __init set_secondary_cpus_clock(void)
{
int thiscpu;
@@ -114,10 +118,29 @@ static void __init armada_xp_smp_init_cpus(void)
void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
{
+ struct device_node *node;
+ struct resource res;
+ int err;
+
set_secondary_cpus_clock();
flush_cache_all();
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
- mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
+
+ /*
+ * In order to boot the secondary CPUs we need to ensure
+ * the bootROM is mapped at the correct address.
+ */
+ node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
+ if (!node)
+ panic("Cannot find 'marvell,bootrom' compatible node");
+
+ err = of_address_to_resource(node, 0, &res);
+ if (err < 0)
+ panic("Cannot get 'bootrom' node address");
+
+ if (res.start != AXP_BOOTROM_BASE ||
+ resource_size(&res) != AXP_BOOTROM_SIZE)
+ panic("The address for the BootROM is incorrect");
}
struct smp_operations armada_xp_smp_ops __initdata = {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 15/21] ARM: mvebu: Remove the harcoded BootROM window allocation
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
The address decoding window to access the BootROM should not be
allocated programatically, but instead declared in the device tree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/mach-mvebu/platsmp.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index ce81d30..7be1ec2 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/mbus.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
#include "pmsu.h"
#include "coherency.h"
+#define AXP_BOOTROM_BASE 0xfff00000
+#define AXP_BOOTROM_SIZE 0x100000
+
void __init set_secondary_cpus_clock(void)
{
int thiscpu;
@@ -114,10 +118,29 @@ static void __init armada_xp_smp_init_cpus(void)
void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
{
+ struct device_node *node;
+ struct resource res;
+ int err;
+
set_secondary_cpus_clock();
flush_cache_all();
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
- mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
+
+ /*
+ * In order to boot the secondary CPUs we need to ensure
+ * the bootROM is mapped at the correct address.
+ */
+ node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
+ if (!node)
+ panic("Cannot find 'marvell,bootrom' compatible node");
+
+ err = of_address_to_resource(node, 0, &res);
+ if (err < 0)
+ panic("Cannot get 'bootrom' node address");
+
+ if (res.start != AXP_BOOTROM_BASE ||
+ resource_size(&res) != AXP_BOOTROM_SIZE)
+ panic("The address for the BootROM is incorrect");
}
struct smp_operations armada_xp_smp_ops __initdata = {
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 16/21] ARM: mvebu: Initialize MBus using the DT binding
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
Now that the mbus device tree binding has been introduced, we can
switch over to it.
Also, and since the initialization of the mbus driver is quite
fundamental for the system to work properly, this patch adds a BUG()
in case mbus fails to initialize.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/mach-mvebu/armada-370-xp.c | 34 +---------------------------------
1 file changed, 1 insertion(+), 33 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 97cbb80..829b573 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
debug_ll_io_init();
}
-/*
- * This initialization will be replaced by a DT-based
- * initialization once the mvebu-mbus driver gains DT support.
- */
-
-#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
-#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
-#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
-#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
-
-static void __init armada_370_xp_mbus_init(void)
-{
- char *mbus_soc_name;
- struct device_node *dn;
- const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
- const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-
- if (of_machine_is_compatible("marvell,armada370"))
- mbus_soc_name = "marvell,armada370-mbus";
- else
- mbus_soc_name = "marvell,armadaxp-mbus";
-
- dn = of_find_node_by_name(NULL, "internal-regs");
- BUG_ON(!dn);
-
- mvebu_mbus_init(mbus_soc_name,
- of_translate_address(dn, &mbus_wins_offs),
- ARMADA_370_XP_MBUS_WINS_SIZE,
- of_translate_address(dn, &sdram_wins_offs),
- ARMADA_370_XP_SDRAM_WINS_SIZE);
-}
-
static void __init armada_370_xp_timer_and_clk_init(void)
{
of_clk_init(NULL);
armada_370_xp_timer_init();
coherency_init();
- armada_370_xp_mbus_init();
+ BUG_ON(mvebu_mbus_dt_init());
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 16/21] ARM: mvebu: Initialize MBus using the DT binding
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
Now that the mbus device tree binding has been introduced, we can
switch over to it.
Also, and since the initialization of the mbus driver is quite
fundamental for the system to work properly, this patch adds a BUG()
in case mbus fails to initialize.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.c | 34 +---------------------------------
1 file changed, 1 insertion(+), 33 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 97cbb80..829b573 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
debug_ll_io_init();
}
-/*
- * This initialization will be replaced by a DT-based
- * initialization once the mvebu-mbus driver gains DT support.
- */
-
-#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
-#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
-#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
-#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
-
-static void __init armada_370_xp_mbus_init(void)
-{
- char *mbus_soc_name;
- struct device_node *dn;
- const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
- const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-
- if (of_machine_is_compatible("marvell,armada370"))
- mbus_soc_name = "marvell,armada370-mbus";
- else
- mbus_soc_name = "marvell,armadaxp-mbus";
-
- dn = of_find_node_by_name(NULL, "internal-regs");
- BUG_ON(!dn);
-
- mvebu_mbus_init(mbus_soc_name,
- of_translate_address(dn, &mbus_wins_offs),
- ARMADA_370_XP_MBUS_WINS_SIZE,
- of_translate_address(dn, &sdram_wins_offs),
- ARMADA_370_XP_SDRAM_WINS_SIZE);
-}
-
static void __init armada_370_xp_timer_and_clk_init(void)
{
of_clk_init(NULL);
armada_370_xp_timer_init();
coherency_init();
- armada_370_xp_mbus_init();
+ BUG_ON(mvebu_mbus_dt_init());
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 17/21] ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-db.dts | 2 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-370.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-db.dts | 2 +-
arch/arm/boot/dts/armada-xp-gp.dts | 2 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
arch/arm/boot/dts/armada-xp.dtsi | 2 +-
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee169..55b986c 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Evaluation Board";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b1077..37530af 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Globalscale Mirabox";
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fed..7aa2171 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Reference Design";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6..08ec6e3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
* common to all Armada SoCs.
*/
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68f..a9bd766 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de..54843e5 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335d..985373a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78260 SoC";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d..f8bf25a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78460 SoC";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f51045..d090264 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78260.dtsi"
+#include "armada-xp-mv78260.dtsi"
/ {
model = "PlatHome OpenBlocks AX3-4 board";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb94..8c07bfe 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
* common to all Armada SoCs.
*/
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
/ {
model = "Marvell Armada XP family SoC";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 17/21] ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 2 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-370.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-db.dts | 2 +-
arch/arm/boot/dts/armada-xp-gp.dts | 2 +-
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
arch/arm/boot/dts/armada-xp.dtsi | 2 +-
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee169..55b986c 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Evaluation Board";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b1077..37530af 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Globalscale Mirabox";
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fed..7aa2171 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Reference Design";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6..08ec6e3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
* common to all Armada SoCs.
*/
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68f..a9bd766 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de..54843e5 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335d..985373a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78260 SoC";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d..f8bf25a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78460 SoC";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f51045..d090264 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
*/
/dts-v1/;
-/include/ "armada-xp-mv78260.dtsi"
+#include "armada-xp-mv78260.dtsi"
/ {
model = "PlatHome OpenBlocks AX3-4 board";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb94..8c07bfe 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
* common to all Armada SoCs.
*/
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
/ {
model = "Marvell Armada XP family SoC";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 18/21] ARM: mvebu: Add MBus to Armada 370/XP device tree
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.
A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-db.dts | 2 ++
arch/arm/boot/dts/armada-370-mirabox.dts | 2 ++
arch/arm/boot/dts/armada-370-rd.dts | 2 ++
arch/arm/boot/dts/armada-370-xp.dtsi | 15 ++++++++++-----
arch/arm/boot/dts/armada-370.dtsi | 4 ++--
arch/arm/boot/dts/armada-xp-db.dts | 4 +---
arch/arm/boot/dts/armada-xp-gp.dts | 4 +---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 4 +---
arch/arm/boot/dts/armada-xp.dtsi | 2 ++
9 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 55b986c..5920b4e 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,6 +30,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 37530af..a4202b6 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,6 +25,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 7aa2171..dd0ba01 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,6 +28,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b1176..62639b4 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
@@ -38,18 +40,21 @@
};
soc {
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <1>;
- compatible = "simple-bus";
+ controller = <&mbusc>;
interrupt-parent = <&mpic>;
- ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 08ec6e3..4b54e51 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,8 +29,8 @@
};
soc {
- ranges = <0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+ compatible = "marvell,armada370-mbus", "simple-bus";
+
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index a9bd766..0d4ce54 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,9 +30,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 54843e5..2fa9209 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,9 +39,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index d090264..a3e3a12 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,9 +27,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 8c07bfe..8033824 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -27,6 +27,8 @@
};
soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 18/21] ARM: mvebu: Add MBus to Armada 370/XP device tree
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.
A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 2 ++
arch/arm/boot/dts/armada-370-mirabox.dts | 2 ++
arch/arm/boot/dts/armada-370-rd.dts | 2 ++
arch/arm/boot/dts/armada-370-xp.dtsi | 15 ++++++++++-----
arch/arm/boot/dts/armada-370.dtsi | 4 ++--
arch/arm/boot/dts/armada-xp-db.dts | 4 +---
arch/arm/boot/dts/armada-xp-gp.dts | 4 +---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 4 +---
arch/arm/boot/dts/armada-xp.dtsi | 2 ++
9 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 55b986c..5920b4e 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,6 +30,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial at 12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 37530af..a4202b6 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,6 +25,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial at 12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 7aa2171..dd0ba01 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,6 +28,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial at 12000 {
clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b1176..62639b4 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
@@ -38,18 +40,21 @@
};
soc {
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <1>;
- compatible = "simple-bus";
+ controller = <&mbusc>;
interrupt-parent = <&mpic>;
- ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller at 20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
mpic: interrupt-controller at 20000 {
compatible = "marvell,mpic";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 08ec6e3..4b54e51 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -29,8 +29,8 @@
};
soc {
- ranges = <0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+ compatible = "marvell,armada370-mbus", "simple-bus";
+
internal-regs {
system-controller at 18200 {
compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index a9bd766..0d4ce54 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,9 +30,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 54843e5..2fa9209 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,9 +39,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index d090264..a3e3a12 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,9 +27,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 8c07bfe..8033824 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -27,6 +27,8 @@
};
soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 19/21] ARM: mvebu: Add BootROM to Armada 370/XP device tree
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-db.dts | 3 ++-
arch/arm/boot/dts/armada-370-mirabox.dts | 3 ++-
arch/arm/boot/dts/armada-370-rd.dts | 3 ++-
arch/arm/boot/dts/armada-370.dtsi | 5 +++++
arch/arm/boot/dts/armada-xp-db.dts | 3 ++-
arch/arm/boot/dts/armada-xp-gp.dts | 3 ++-
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 ++-
arch/arm/boot/dts/armada-xp.dtsi | 5 +++++
8 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 5920b4e..90ce29d 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,7 +30,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index a4202b6..19341d2 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,7 +25,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index dd0ba01..0b3acf3 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,7 +28,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 4b54e51..bd21d49 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,6 +31,11 @@
soc {
compatible = "marvell,armada370-mbus", "simple-bus";
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+ };
+
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 0d4ce54..857f272 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,7 +30,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 2fa9209..934dc46 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,7 +39,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index a3e3a12..1700f6f 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,7 +27,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 8033824..7ba99ce 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -29,6 +29,11 @@
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 19/21] ARM: mvebu: Add BootROM to Armada 370/XP device tree
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 3 ++-
arch/arm/boot/dts/armada-370-mirabox.dts | 3 ++-
arch/arm/boot/dts/armada-370-rd.dts | 3 ++-
arch/arm/boot/dts/armada-370.dtsi | 5 +++++
arch/arm/boot/dts/armada-xp-db.dts | 3 ++-
arch/arm/boot/dts/armada-xp-gp.dts | 3 ++-
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 ++-
arch/arm/boot/dts/armada-xp.dtsi | 5 +++++
8 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 5920b4e..90ce29d 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,7 +30,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index a4202b6..19341d2 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,7 +25,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index dd0ba01..0b3acf3 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,7 +28,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 4b54e51..bd21d49 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,6 +31,11 @@
soc {
compatible = "marvell,armada370-mbus", "simple-bus";
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+ };
+
internal-regs {
system-controller at 18200 {
compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 0d4ce54..857f272 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,7 +30,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 2fa9209..934dc46 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,7 +39,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index a3e3a12..1700f6f 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,7 +27,8 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
internal-regs {
serial at 12000 {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 8033824..7ba99ce 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -29,6 +29,11 @@
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 20/21] ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 94 +++++++++++++-----------
arch/arm/boot/dts/armada-xp-db.dts | 59 +++++++--------
arch/arm/boot/dts/armada-xp-gp.dts | 60 +++++++--------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 65 ++++++++--------
4 files changed, 140 insertions(+), 138 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 62639b4..073dd20 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -45,6 +45,56 @@
controller = <&mbusc>;
interrupt-parent = <&mpic>;
+ devbus-bootcs {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs0 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs1 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs2 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs3 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
@@ -200,50 +250,6 @@
status = "disabled";
};
- devbus-bootcs@10400 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10400 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs0@10408 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10408 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs1@10410 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10410 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs2@10418 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10418 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs3@10420 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10420 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 857f272..76ae1a9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -31,7 +31,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial@12000 {
@@ -160,34 +189,6 @@
};
};
- devbus-bootcs@10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x1000000>;
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 16 MiB */
- nor@0 {
- compatible = "cfi-flash";
- reg = <0 0x1000000>;
- bank-width = <2>;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 934dc46..8c0de20 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -40,7 +40,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial@12000 {
@@ -126,35 +155,6 @@
};
};
- devbus-bootcs@10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 16 MiB */
- nor@0 {
- compatible = "cfi-flash";
- reg = <0 0x1000000>;
- bank-width = <2>;
- };
- };
-
pcie-controller {
status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 1700f6f..2b60ee0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -28,7 +28,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 128 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x8000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial@12000 {
@@ -148,40 +177,6 @@
status = "okay";
};
- /* USB interface in the mini-PCIe connector */
- usb@52000 {
- status = "okay";
- };
-
- devbus-bootcs@10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 128 MiB */
- nor@0 {
- compatible = "cfi-flash";
- reg = <0 0x8000000>;
- bank-width = <2>;
- };
- };
-
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 20/21] ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 94 +++++++++++++-----------
arch/arm/boot/dts/armada-xp-db.dts | 59 +++++++--------
arch/arm/boot/dts/armada-xp-gp.dts | 60 +++++++--------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 65 ++++++++--------
4 files changed, 140 insertions(+), 138 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 62639b4..073dd20 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -45,6 +45,56 @@
controller = <&mbusc>;
interrupt-parent = <&mpic>;
+ devbus-bootcs {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs0 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs1 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs2 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ devbus-cs3 {
+ compatible = "marvell,mvebu-devbus";
+ reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+ ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
@@ -200,50 +250,6 @@
status = "disabled";
};
- devbus-bootcs at 10400 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10400 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs0 at 10408 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10408 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs1 at 10410 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10410 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs2 at 10418 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10418 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus-cs3 at 10420 {
- compatible = "marvell,mvebu-devbus";
- reg = <0x10420 0x8>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 857f272..76ae1a9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -31,7 +31,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor at 0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial at 12000 {
@@ -160,34 +189,6 @@
};
};
- devbus-bootcs at 10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x1000000>;
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 16 MiB */
- nor at 0 {
- compatible = "cfi-flash";
- reg = <0 0x1000000>;
- bank-width = <2>;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 934dc46..8c0de20 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -40,7 +40,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor at 0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial at 12000 {
@@ -126,35 +155,6 @@
};
};
- devbus-bootcs at 10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 16 MiB */
- nor at 0 {
- compatible = "cfi-flash";
- reg = <0 0x1000000>;
- bank-width = <2>;
- };
- };
-
pcie-controller {
status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 1700f6f..2b60ee0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -28,7 +28,36 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <8>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 128 MiB */
+ nor at 0 {
+ compatible = "cfi-flash";
+ reg = <0 0x8000000>;
+ bank-width = <2>;
+ };
+ };
internal-regs {
serial at 12000 {
@@ -148,40 +177,6 @@
status = "okay";
};
- /* USB interface in the mini-PCIe connector */
- usb at 52000 {
- status = "okay";
- };
-
- devbus-bootcs at 10400 {
- status = "okay";
- ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
-
- /* Device Bus parameters are required */
-
- /* Read parameters */
- devbus,bus-width = <8>;
- devbus,turn-off-ps = <60000>;
- devbus,badr-skew-ps = <0>;
- devbus,acc-first-ps = <124000>;
- devbus,acc-next-ps = <248000>;
- devbus,rd-setup-ps = <0>;
- devbus,rd-hold-ps = <0>;
-
- /* Write parameters */
- devbus,sync-enable = <0>;
- devbus,wr-high-ps = <60000>;
- devbus,wr-low-ps = <60000>;
- devbus,ale-wr-ps = <60000>;
-
- /* NOR 128 MiB */
- nor at 0 {
- compatible = "cfi-flash";
- reg = <0 0x8000000>;
- bank-width = <2>;
- };
- };
-
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v6 21/21] ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 21:39 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Andrew Lunn, Jason Cooper, Jason Gunthorpe, Maen Suleiman,
Lior Amsalem, Sebastian Hesselbarth
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
arch/arm/boot/dts/armada-370.dtsi | 99 +++---
arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 217 +++++++------
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 256 ++++++++-------
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 395 ++++++++++++-----------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
8 files changed, 584 insertions(+), 542 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 19341d2..2471d9d 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -28,6 +28,22 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+ pcie-controller {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
@@ -123,22 +139,6 @@
reg = <0x25>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index bd21d49..066a79f 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -36,6 +36,57 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
+ pcie-controller {
+ compatible = "marvell,armada-370-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x81001000 0 0 MBUS_ID(0x08, 0xe0) 0xe8000000 0 0x00100000 /* Port 1.0 IO */>;
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 62>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
@@ -174,54 +225,6 @@
0x18304 0x4>;
status = "okay";
};
-
- pcie-controller {
- compatible = "marvell,armada-370-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 9>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 76ae1a9..bcf6d79 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -62,6 +62,39 @@
};
};
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * All 6 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 0, Lane 2 */
+ status = "okay";
+ };
+ pcie@4,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
@@ -155,40 +188,6 @@
spi-max-frequency = <20000000>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /*
- * All 6 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
- pcie@3,0 {
- /* Port 0, Lane 2 */
- status = "okay";
- };
- pcie@4,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 8c0de20..2298e4a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -71,6 +71,27 @@
};
};
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
@@ -154,27 +175,6 @@
spi-max-frequency = <108000000>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa38..335a1c1 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -44,6 +44,119 @@
};
soc {
+ /*
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */>;
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
@@ -77,110 +190,6 @@
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
-
- /*
- * MV78230 has 2 PCIe units Gen2.0: One unit can be
- * configured as x4 or quad x1 lanes. One unit is
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
-#address-cells = <3>;
-#size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie@4,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie@9,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 985373a..4d429ac 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,6 +45,140 @@
};
soc {
+ /*
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.1 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82002800 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */
+ 0x82005000 0 0xe0000000 MBUS_ID(0x08, 0xf8) 0xe0000000 0 0x08000000 /* Port 3.0 MEM */
+ 0x81005000 0 0 MBUS_ID(0x08, 0xf0) 0xe8000000 0 0x00100000 /* Port 3.0 IO */>;
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie@10,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+ reg = <0x5000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 103>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
@@ -97,128 +231,6 @@
clocks = <&gateclk 1>;
status = "disabled";
};
-
- /*
- * MV78260 has 3 PCIe units Gen2.0: Two units can be
- * configured as x4 or quad x1 lanes. One unit is
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie@4,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie@9,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
-
- pcie@10,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 27>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index f8bf25a..3ad3c95 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -61,6 +61,213 @@
};
soc {
+ /*
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. Two units are
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82002800 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x81002800 0 0 MBUS_ID(0x08, 0xe0) 0xe8000000 0 0x00100000 /* Port 1.0 IO */
+ 0x82003000 0 0xe0000000 MBUS_ID(0x08, 0xd8) 0xe0000000 0 0x08000000 /* Port 1.1 MEM */
+ 0x81003000 0 0 MBUS_ID(0x08, 0xd0) 0xe8000000 0 0x00100000 /* Port 1.1 IO */
+ 0x82003800 0 0xe0000000 MBUS_ID(0x08, 0xb8) 0xe0000000 0 0x08000000 /* Port 1.2 MEM */
+ 0x81003800 0 0 MBUS_ID(0x08, 0xb0) 0xe8000000 0 0x00100000 /* Port 1.2 IO */
+ 0x82004000 0 0xe0000000 MBUS_ID(0x08, 0x78) 0xe0000000 0 0x08000000 /* Port 1.3 MEM */
+ 0x81004000 0 0 MBUS_ID(0x08, 0x70) 0xe8000000 0 0x00100000 /* Port 1.3 IO */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */
+ 0x82005000 0 0xe0000000 MBUS_ID(0x08, 0xf8) 0xe0000000 0 0x08000000 /* Port 3.0 MEM */
+ 0x81005000 0 0 MBUS_ID(0x08, 0xf0) 0xe8000000 0 0x00100000 /* Port 3.0 IO */>;
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie@4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie@5,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ reg = <0x2800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 62>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+
+ pcie@6,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
+ reg = <0x3000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 63>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 10>;
+ status = "disabled";
+ };
+
+ pcie@7,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
+ reg = <0x3800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 64>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+ pcie@8,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
+ reg = <0x4000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 65>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 12>;
+ status = "disabled";
+ };
+ pcie@9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie@10,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
+ reg = <0x5000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 103>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
@@ -113,194 +320,6 @@
clocks = <&gateclk 1>;
status = "disabled";
};
-
- /*
- * MV78460 has 4 PCIe units Gen2.0: Two units can be
- * configured as x4 or quad x1 lanes. Two units are
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie@4,0 {
- device_type = "pci";
- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie@5,0 {
- device_type = "pci";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 9>;
- status = "disabled";
- };
-
- pcie@6,0 {
- device_type = "pci";
- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
- reg = <0x3000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 10>;
- status = "disabled";
- };
-
- pcie@7,0 {
- device_type = "pci";
- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
- reg = <0x3800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 11>;
- status = "disabled";
- };
-
- pcie@8,0 {
- device_type = "pci";
- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
- reg = <0x4000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 12>;
- status = "disabled";
- };
- pcie@9,0 {
- device_type = "pci";
- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
-
- pcie@10,0 {
- device_type = "pci";
- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 27>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 2b60ee0..5695afc 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -59,6 +59,15 @@
};
};
+ pcie-controller {
+ status = "okay";
+ /* Internal mini-PCIe connector */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
@@ -176,15 +185,6 @@
usb@51000 {
status = "okay";
};
-
- pcie-controller {
- status = "okay";
- /* Internal mini-PCIe connector */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
};
};
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v6 21/21] ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
@ 2013-07-05 21:39 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-05 21:39 UTC (permalink / raw)
To: linux-arm-kernel
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
arch/arm/boot/dts/armada-370.dtsi | 99 +++---
arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 217 +++++++------
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 256 ++++++++-------
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 395 ++++++++++++-----------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
8 files changed, 584 insertions(+), 542 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 19341d2..2471d9d 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -28,6 +28,22 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+ pcie-controller {
+ status = "okay";
+
+ /* Internal mini-PCIe connector */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected on the PCB to a USB 3.0 XHCI controller */
+ pcie at 2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial at 12000 {
clock-frequency = <200000000>;
@@ -123,22 +139,6 @@
reg = <0x25>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /* Internal mini-PCIe connector */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected on the PCB to a USB 3.0 XHCI controller */
- pcie at 2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index bd21d49..066a79f 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -36,6 +36,57 @@
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
+ pcie-controller {
+ compatible = "marvell,armada-370-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x81001000 0 0 MBUS_ID(0x08, 0xe0) 0xe8000000 0 0x00100000 /* Port 1.0 IO */>;
+
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 62>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
system-controller at 18200 {
compatible = "marvell,armada-370-xp-system-controller";
@@ -174,54 +225,6 @@
0x18304 0x4>;
status = "okay";
};
-
- pcie-controller {
- compatible = "marvell,armada-370-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie at 1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie at 2,0 {
- device_type = "pci";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 9>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 76ae1a9..bcf6d79 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -62,6 +62,39 @@
};
};
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * All 6 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie at 2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+ pcie at 3,0 {
+ /* Port 0, Lane 2 */
+ status = "okay";
+ };
+ pcie at 4,0 {
+ /* Port 0, Lane 3 */
+ status = "okay";
+ };
+ pcie at 9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie at 10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial at 12000 {
clock-frequency = <250000000>;
@@ -155,40 +188,6 @@
spi-max-frequency = <20000000>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /*
- * All 6 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie at 2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
- pcie at 3,0 {
- /* Port 0, Lane 2 */
- status = "okay";
- };
- pcie at 4,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- pcie at 9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie at 10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 8c0de20..2298e4a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -71,6 +71,27 @@
};
};
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie at 9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie at 10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial at 12000 {
clock-frequency = <250000000>;
@@ -154,27 +175,6 @@
spi-max-frequency = <108000000>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie at 9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie at 10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa38..335a1c1 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -44,6 +44,119 @@
};
soc {
+ /*
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */>;
+
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
@@ -77,110 +190,6 @@
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
-
- /*
- * MV78230 has 2 PCIe units Gen2.0: One unit can be
- * configured as x4 or quad x1 lanes. One unit is
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
-#address-cells = <3>;
-#size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie at 1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie at 2,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie at 3,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie at 4,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie at 9,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 985373a..4d429ac 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,6 +45,140 @@
};
soc {
+ /*
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. One unit is
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.1 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82002800 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */
+ 0x82005000 0 0xe0000000 MBUS_ID(0x08, 0xf8) 0xe0000000 0 0x08000000 /* Port 3.0 MEM */
+ 0x81005000 0 0 MBUS_ID(0x08, 0xf0) 0xe8000000 0 0x00100000 /* Port 3.0 IO */>;
+
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie at 10,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+ reg = <0x5000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 103>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
@@ -97,128 +231,6 @@
clocks = <&gateclk 1>;
status = "disabled";
};
-
- /*
- * MV78260 has 3 PCIe units Gen2.0: Two units can be
- * configured as x4 or quad x1 lanes. One unit is
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie at 1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie at 2,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie at 3,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie at 4,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie at 9,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
-
- pcie at 10,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 27>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index f8bf25a..3ad3c95 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -61,6 +61,213 @@
};
soc {
+ /*
+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. Two units are
+ * x4/x1.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */
+ 0x82001000 0 0xe0000000 MBUS_ID(0x04, 0xd8) 0xe0000000 0 0x08000000 /* Port 0.1 MEM */
+ 0x81001000 0 0 MBUS_ID(0x04, 0xd0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82001800 0 0xe0000000 MBUS_ID(0x04, 0xb8) 0xe0000000 0 0x08000000 /* Port 0.2 MEM */
+ 0x81001800 0 0 MBUS_ID(0x04, 0xb0) 0xe8000000 0 0x00100000 /* Port 0.2 IO */
+ 0x82002000 0 0xe0000000 MBUS_ID(0x04, 0x78) 0xe0000000 0 0x08000000 /* Port 0.3 MEM */
+ 0x81002000 0 0 MBUS_ID(0x04, 0x70) 0xe8000000 0 0x00100000 /* Port 0.3 IO */
+ 0x82002800 0 0xe0000000 MBUS_ID(0x08, 0xe8) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
+ 0x81002800 0 0 MBUS_ID(0x08, 0xe0) 0xe8000000 0 0x00100000 /* Port 1.0 IO */
+ 0x82003000 0 0xe0000000 MBUS_ID(0x08, 0xd8) 0xe0000000 0 0x08000000 /* Port 1.1 MEM */
+ 0x81003000 0 0 MBUS_ID(0x08, 0xd0) 0xe8000000 0 0x00100000 /* Port 1.1 IO */
+ 0x82003800 0 0xe0000000 MBUS_ID(0x08, 0xb8) 0xe0000000 0 0x08000000 /* Port 1.2 MEM */
+ 0x81003800 0 0 MBUS_ID(0x08, 0xb0) 0xe8000000 0 0x00100000 /* Port 1.2 IO */
+ 0x82004000 0 0xe0000000 MBUS_ID(0x08, 0x78) 0xe0000000 0 0x08000000 /* Port 1.3 MEM */
+ 0x81004000 0 0 MBUS_ID(0x08, 0x70) 0xe8000000 0 0x00100000 /* Port 1.3 IO */
+ 0x82004800 0 0xe0000000 MBUS_ID(0x04, 0xf8) 0xe0000000 0 0x08000000 /* Port 2.0 MEM */
+ 0x81004800 0 0 MBUS_ID(0x04, 0xf0) 0xe8000000 0 0x00100000 /* Port 2.0 IO */
+ 0x82005000 0 0xe0000000 MBUS_ID(0x08, 0xf8) 0xe0000000 0 0x08000000 /* Port 3.0 MEM */
+ 0x81005000 0 0 MBUS_ID(0x08, 0xf0) 0xe8000000 0 0x00100000 /* Port 3.0 IO */>;
+
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 59>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ pcie at 3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 60>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+
+ pcie at 4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 61>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ pcie at 5,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ reg = <0x2800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 62>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+
+ pcie at 6,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
+ reg = <0x3000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 63>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <1>;
+ clocks = <&gateclk 10>;
+ status = "disabled";
+ };
+
+ pcie at 7,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
+ reg = <0x3800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 64>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <2>;
+ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+ pcie at 8,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
+ reg = <0x4000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 65>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <3>;
+ clocks = <&gateclk 12>;
+ status = "disabled";
+ };
+ pcie at 9,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
+ reg = <0x4800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 99>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+
+ pcie at 10,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
+ reg = <0x5000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 103>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 27>;
+ status = "disabled";
+ };
+ };
+
internal-regs {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
@@ -113,194 +320,6 @@
clocks = <&gateclk 1>;
status = "disabled";
};
-
- /*
- * MV78460 has 4 PCIe units Gen2.0: Two units can be
- * configured as x4 or quad x1 lanes. Two units are
- * x4/x1.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-
- pcie at 1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- pcie at 2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- pcie at 3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
-
- pcie at 4,0 {
- device_type = "pci";
- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- pcie at 5,0 {
- device_type = "pci";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 9>;
- status = "disabled";
- };
-
- pcie at 6,0 {
- device_type = "pci";
- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
- reg = <0x3000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <1>;
- clocks = <&gateclk 10>;
- status = "disabled";
- };
-
- pcie at 7,0 {
- device_type = "pci";
- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
- reg = <0x3800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <2>;
- clocks = <&gateclk 11>;
- status = "disabled";
- };
-
- pcie at 8,0 {
- device_type = "pci";
- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
- reg = <0x4000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <3>;
- clocks = <&gateclk 12>;
- status = "disabled";
- };
- pcie at 9,0 {
- device_type = "pci";
- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 26>;
- status = "disabled";
- };
-
- pcie at 10,0 {
- device_type = "pci";
- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 27>;
- status = "disabled";
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 2b60ee0..5695afc 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -59,6 +59,15 @@
};
};
+ pcie-controller {
+ status = "okay";
+ /* Internal mini-PCIe connector */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial at 12000 {
clock-frequency = <250000000>;
@@ -176,15 +185,6 @@
usb at 51000 {
status = "okay";
};
-
- pcie-controller {
- status = "okay";
- /* Internal mini-PCIe connector */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
};
};
};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 22:08 ` Jason Gunthorpe
-1 siblings, 0 replies; 60+ messages in thread
From: Jason Gunthorpe @ 2013-07-05 22:08 UTC (permalink / raw)
To: Ezequiel Garcia
Cc: Andrew Lunn, Jason Cooper,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
Lior Amsalem, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
> ranges =
> <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
This is a good try, but this coding doesn't work...
Recall the long discussion that came up during the original
development of this binding. The OF spec says this:
In particular, the phys.hi fields of the child address spaces in the
"ranges" property for PCI does not contain
the same information as "reg" property entries within PCI nodes. The
only information that is present in
"ranges" phys.hi entries are the non-relocatable, prefetchable and
the PCI address space bits for which the en-
try applies. I.e., only the n, p and ss bits are present; the
bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
When an address is to be mapped through a PCI bus bridge node, the
phys.hi value of the address to be mapped
and the child field of a "ranges" entry should be masked so that only
the ss bits are compared. I.e., the only
portion of phys.hi that should participate in the range determination
is the address space indicator (the ss bits).
Which forbids (0x82000800 .. ..) from being in a ranges
I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
Arnd? Didn't you have some idea?
FWIW, I like removing the string tables from the driver, you could
keep the fake MBUS-ID and retain that change by adding a
marvell,target-id type property to the bridges...
Jason
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-05 22:08 ` Jason Gunthorpe
0 siblings, 0 replies; 60+ messages in thread
From: Jason Gunthorpe @ 2013-07-05 22:08 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
> ranges =
> <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
This is a good try, but this coding doesn't work...
Recall the long discussion that came up during the original
development of this binding. The OF spec says this:
In particular, the phys.hi fields of the child address spaces in the
"ranges" property for PCI does not contain
the same information as "reg" property entries within PCI nodes. The
only information that is present in
"ranges" phys.hi entries are the non-relocatable, prefetchable and
the PCI address space bits for which the en-
try applies. I.e., only the n, p and ss bits are present; the
bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
When an address is to be mapped through a PCI bus bridge node, the
phys.hi value of the address to be mapped
and the child field of a "ranges" entry should be masked so that only
the ss bits are compared. I.e., the only
portion of phys.hi that should participate in the range determination
is the address space indicator (the ss bits).
Which forbids (0x82000800 .. ..) from being in a ranges
I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
Arnd? Didn't you have some idea?
FWIW, I like removing the string tables from the driver, you could
keep the fake MBUS-ID and retain that change by adding a
marvell,target-id type property to the bridges...
Jason
^ permalink raw reply [flat|nested] 60+ messages in thread
[parent not found: <20130705220820.GA11787-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>]
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 22:08 ` Jason Gunthorpe
@ 2013-07-05 22:37 ` Thomas Petazzoni
-1 siblings, 0 replies; 60+ messages in thread
From: Thomas Petazzoni @ 2013-07-05 22:37 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Lior Amsalem, Andrew Lunn, Jason Cooper,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
Dear Jason Gunthorpe,
Thanks for your quick feedback!
On Fri, 5 Jul 2013 16:08:20 -0600, Jason Gunthorpe wrote:
> On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
>
> > ranges =
> > <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> > 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> > 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> > 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> > 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> > 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> > 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
>
> This is a good try, but this coding doesn't work...
>
> Recall the long discussion that came up during the original
> development of this binding. The OF spec says this:
>
> In particular, the phys.hi fields of the child address spaces in the
> "ranges" property for PCI does not contain
> the same information as "reg" property entries within PCI nodes. The
> only information that is present in
> "ranges" phys.hi entries are the non-relocatable, prefetchable and
> the PCI address space bits for which the en-
> try applies. I.e., only the n, p and ss bits are present; the
> bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
>
> When an address is to be mapped through a PCI bus bridge node, the
> phys.hi value of the address to be mapped
> and the child field of a "ranges" entry should be masked so that only
> the ss bits are compared. I.e., the only
> portion of phys.hi that should participate in the range determination
> is the address space indicator (the ss bits).
>
> Which forbids (0x82000800 .. ..) from being in a ranges
Ah, right, I missed this part of the OF specification. Indeed, having
the ddddd bits non-zero was critical here to allow the PCIe driver to
find which MBUS_ID(x, y) to use for a particular PCIe interface.
> I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
>
> Arnd? Didn't you have some idea?
>
> FWIW, I like removing the string tables from the driver, you could
> keep the fake MBUS-ID and retain that change by adding a
> marvell,target-id type property to the bridges...
The problem we were trying to address here is that apparently the fake
MBUS-ID was not seen by Arnd as a correct solution, if we understood
correctly what Arnd said in
http://www.mail-archive.com/devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org/msg34650.html:
"""
Using 0xffff0002 as a placeholder for the pcie translation is definitely
better than 0xffff0000 as you had before, but let me ask again in case
you missed it the last time (and sorry if I missed the answer):
Why not just put the actual translation here the way it happens for each
of the PCIe ports? With the definition here, the PCIe driver actually
has no way to figure out what settings the windows need to use!
"""
We're not sure how to handle this comment properly in terms of DT
binding. What the PCIe driver needs is:
*) One global range of addresses for PCIe memory regions and one global
range of addresses for PCIe I/O regions. Those were until the v5 of
this patch set expressed using a fake MBUS_ID(0xf0, 0x02). Those
are global to all PCIe interfaces.
*) The target and attribute values for MEM and I/O windows, that are
per-PCIe interface.
As long as we can get those two informations from the DT, I believe
we're open to all your suggestions on how to encode them.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-05 22:37 ` Thomas Petazzoni
0 siblings, 0 replies; 60+ messages in thread
From: Thomas Petazzoni @ 2013-07-05 22:37 UTC (permalink / raw)
To: linux-arm-kernel
Dear Jason Gunthorpe,
Thanks for your quick feedback!
On Fri, 5 Jul 2013 16:08:20 -0600, Jason Gunthorpe wrote:
> On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
>
> > ranges =
> > <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> > 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> > 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> > 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> > 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> > 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> > 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
>
> This is a good try, but this coding doesn't work...
>
> Recall the long discussion that came up during the original
> development of this binding. The OF spec says this:
>
> In particular, the phys.hi fields of the child address spaces in the
> "ranges" property for PCI does not contain
> the same information as "reg" property entries within PCI nodes. The
> only information that is present in
> "ranges" phys.hi entries are the non-relocatable, prefetchable and
> the PCI address space bits for which the en-
> try applies. I.e., only the n, p and ss bits are present; the
> bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
>
> When an address is to be mapped through a PCI bus bridge node, the
> phys.hi value of the address to be mapped
> and the child field of a "ranges" entry should be masked so that only
> the ss bits are compared. I.e., the only
> portion of phys.hi that should participate in the range determination
> is the address space indicator (the ss bits).
>
> Which forbids (0x82000800 .. ..) from being in a ranges
Ah, right, I missed this part of the OF specification. Indeed, having
the ddddd bits non-zero was critical here to allow the PCIe driver to
find which MBUS_ID(x, y) to use for a particular PCIe interface.
> I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
>
> Arnd? Didn't you have some idea?
>
> FWIW, I like removing the string tables from the driver, you could
> keep the fake MBUS-ID and retain that change by adding a
> marvell,target-id type property to the bridges...
The problem we were trying to address here is that apparently the fake
MBUS-ID was not seen by Arnd as a correct solution, if we understood
correctly what Arnd said in
http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg34650.html:
"""
Using 0xffff0002 as a placeholder for the pcie translation is definitely
better than 0xffff0000 as you had before, but let me ask again in case
you missed it the last time (and sorry if I missed the answer):
Why not just put the actual translation here the way it happens for each
of the PCIe ports? With the definition here, the PCIe driver actually
has no way to figure out what settings the windows need to use!
"""
We're not sure how to handle this comment properly in terms of DT
binding. What the PCIe driver needs is:
*) One global range of addresses for PCIe memory regions and one global
range of addresses for PCIe I/O regions. Those were until the v5 of
this patch set expressed using a fake MBUS_ID(0xf0, 0x02). Those
are global to all PCIe interfaces.
*) The target and attribute values for MEM and I/O windows, that are
per-PCIe interface.
As long as we can get those two informations from the DT, I believe
we're open to all your suggestions on how to encode them.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 22:08 ` Jason Gunthorpe
@ 2013-07-05 22:54 ` Arnd Bergmann
-1 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2013-07-05 22:54 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Andrew Lunn, Jason Cooper,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
Lior Amsalem, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
On Saturday 06 July 2013, Jason Gunthorpe wrote:
> This is a good try, but this coding doesn't work...
>
> Recall the long discussion that came up during the original
> development of this binding. The OF spec says this:
>
> In particular, the phys.hi fields of the child address spaces in the
> "ranges" property for PCI does not contain
> the same information as "reg" property entries within PCI nodes. The
> only information that is present in
> "ranges" phys.hi entries are the non-relocatable, prefetchable and
> the PCI address space bits for which the en-
> try applies. I.e., only the n, p and ss bits are present; the
> bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
>
> When an address is to be mapped through a PCI bus bridge node, the
> phys.hi value of the address to be mapped
> and the child field of a "ranges" entry should be masked so that only
> the ss bits are compared. I.e., the only
> portion of phys.hi that should participate in the range determination
> is the address space indicator (the ss bits).
>
> Which forbids (0x82000800 .. ..) from being in a ranges
ah, and I thought Ezequiel was being more clever than what I had suggested
> I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
>
> Arnd? Didn't you have some idea?
The way I described it during the last review, I suggested using
the middle cell of the PCI address here. Since the PCIe port
is 32 bit only, it's otherwise unused. We can do one of two things
here:
a) put the port number in the second cell
0x82000000 1 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
0x82000000 2 0xe0000000 MBUS_ID(0x04, 0xe9) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
b) translate the entire MBUS space here
0x82000000 0 0 0 0 0x1000000 0 /* all MBUS_IDs */
In both cases, the individual ports would have another non-empty
ranges property
a)
0x82000000 1 0xe0000000 0x82000000 0 0xe0000000 0x08000000 /* ranges for port 0.0 */
b)
0x82000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0x82000000 0 0xe0000000 0 0x08000000
I left out the change I suggested in my other reply to not describe
the aperture in this node but translate the entire 4GB space.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-05 22:54 ` Arnd Bergmann
0 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2013-07-05 22:54 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 06 July 2013, Jason Gunthorpe wrote:
> This is a good try, but this coding doesn't work...
>
> Recall the long discussion that came up during the original
> development of this binding. The OF spec says this:
>
> In particular, the phys.hi fields of the child address spaces in the
> "ranges" property for PCI does not contain
> the same information as "reg" property entries within PCI nodes. The
> only information that is present in
> "ranges" phys.hi entries are the non-relocatable, prefetchable and
> the PCI address space bits for which the en-
> try applies. I.e., only the n, p and ss bits are present; the
> bbbbbbbb, ddddd, fff and rrrrrrrr fields are 0.
>
> When an address is to be mapped through a PCI bus bridge node, the
> phys.hi value of the address to be mapped
> and the child field of a "ranges" entry should be masked so that only
> the ss bits are compared. I.e., the only
> portion of phys.hi that should participate in the range determination
> is the address space indicator (the ss bits).
>
> Which forbids (0x82000800 .. ..) from being in a ranges
ah, and I thought Ezequiel was being more clever than what I had suggested
> I don't have an idea how to encode MBUS_ID in the PCI-E ranges :(
>
> Arnd? Didn't you have some idea?
The way I described it during the last review, I suggested using
the middle cell of the PCI address here. Since the PCIe port
is 32 bit only, it's otherwise unused. We can do one of two things
here:
a) put the port number in the second cell
0x82000000 1 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
0x82000000 2 0xe0000000 MBUS_ID(0x04, 0xe9) 0xe0000000 0 0x08000000 /* Port 1.0 MEM */
b) translate the entire MBUS space here
0x82000000 0 0 0 0 0x1000000 0 /* all MBUS_IDs */
In both cases, the individual ports would have another non-empty
ranges property
a)
0x82000000 1 0xe0000000 0x82000000 0 0xe0000000 0x08000000 /* ranges for port 0.0 */
b)
0x82000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0x82000000 0 0xe0000000 0 0x08000000
I left out the change I suggested in my other reply to not describe
the aperture in this node but translate the entire 4GB space.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 21:39 ` Ezequiel Garcia
@ 2013-07-05 23:35 ` Thomas Petazzoni
-1 siblings, 0 replies; 60+ messages in thread
From: Thomas Petazzoni @ 2013-07-05 23:35 UTC (permalink / raw)
To: Jason Gunthorpe, Arnd Bergmann
Cc: Lior Amsalem, Andrew Lunn, Jason Cooper,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
Jason, Arnd,
On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote:
> See the previous version of this patchset for further context:
>
> http://www.mail-archive.com/devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org/msg35753.html
>
> This new proposal is an attempt to address some issues raised about the PCIe
> 'fake' windows mapping present in the previous version.
>
> Instead of defining a 'fake' MBUS_ID(0xf0, 0x02) region for the whole
> PCIe memory and IO space, we use real target ID and attribute for the windows.
>
> See the example below, where a somewhat complete device tree extract is shown:
>
> soc {
> compatible = "marvell,armadaxp-mbus", "simple-bus";
> controller = <&mbusc>;
>
> ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
> MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
>
> bootrom {
> compatible = "marvell,bootrom";
> reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> };
>
> devbus-bootcs {
> status = "okay";
> ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
>
> /* NOR */
> nor {
> compatible = "cfi-flash";
> reg = <0 0x8000000>;
> bank-width = <2>;
> };
> };
>
> pcie-controller {
> compatible = "marvell,armada-xp-pcie";
> status = "okay";
> device_type = "pci";
>
> #address-cells = <3>;
> #size-cells = <2>;
>
> ranges =
> <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
>
>
> pcie@1,0 {
> /* Port 0, Lane 0 */
> status = "okay";
> };
> };
>
> internal-regs {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
>
> mbusc: mbus-controller@20000 {
> reg = <0x20000 0x100>, <0x20180 0x20>;
> };
>
> interrupt-controller@20000 {
> reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> };
> };
> };
After a discussion with Arnd on IRC, here is the new DT layout we came
up with:
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
controller = <&mbusc>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus-bootcs {
status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
nor {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "okay";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 1 0 1 0
0x81000000 0 0 0x81000000 1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 2 0 1 0
0x81000000 0 0 0x81000000 2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller@20000 {
reg = <0x20000 0x100>, <0x20180 0x20>;
};
interrupt-controller@20000 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
};
};
I.e, the changes are :
(1) The main soc {} node gains two new additional DT properties:
pcie-mem-aperture and pcie-io-aperture. The mvebu-mbus reads those
informations, and provides an API
mvebu_mbus_alloc_pcie_{mem,io}_aperture(phys_addr_t *base, size_t
*size) that allows the PCIe driver to get the mem and I/O
apertures for PCIe. In the future, the mvebu-mbus driver may
decide to allocate those apertures dynamically rather than have
values hardcoded in the DT: this is the private business of
mvebu-mbus. For now, the mvebu-mbus driver will use those static
values from the DT, as we don't want to do a full dynamic window
base address allocation for now. This makes sense, as mvebu-mbus
is the "gake keeper" of what gets mapped in terms of mbus windows.
(2) The ranges property of the main pcie-controller {} node is changed
to use 0x82000000 and 0x81000000 for all PCIe interfaces, as requested
by the OF spec. The second 32 bits word of the child address is used
to encode the port number (in our example 1 for the first MEM and I/O
ranges, and 2 for the next MEM and I/O ranges).
(3) A non-empty range property is added in the child pcie@x,y nodes to
translate back into regular PCIe addresses the child addresses
described in the ranges property in pcie-controller. I.e, it
simply translate (0x82000000 0 0) into (0x8200000 <port> 0).
Arnd, Jason, if you could confirm that you both agree with this DT
binding soon, Ezequiel and I would quickly adapt the code accordingly,
and hopefully converge towards a final patch set.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-05 23:35 ` Thomas Petazzoni
0 siblings, 0 replies; 60+ messages in thread
From: Thomas Petazzoni @ 2013-07-05 23:35 UTC (permalink / raw)
To: linux-arm-kernel
Jason, Arnd,
On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote:
> See the previous version of this patchset for further context:
>
> http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg35753.html
>
> This new proposal is an attempt to address some issues raised about the PCIe
> 'fake' windows mapping present in the previous version.
>
> Instead of defining a 'fake' MBUS_ID(0xf0, 0x02) region for the whole
> PCIe memory and IO space, we use real target ID and attribute for the windows.
>
> See the example below, where a somewhat complete device tree extract is shown:
>
> soc {
> compatible = "marvell,armadaxp-mbus", "simple-bus";
> controller = <&mbusc>;
>
> ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
> MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
>
> bootrom {
> compatible = "marvell,bootrom";
> reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> };
>
> devbus-bootcs {
> status = "okay";
> ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
>
> /* NOR */
> nor {
> compatible = "cfi-flash";
> reg = <0 0x8000000>;
> bank-width = <2>;
> };
> };
>
> pcie-controller {
> compatible = "marvell,armada-xp-pcie";
> status = "okay";
> device_type = "pci";
>
> #address-cells = <3>;
> #size-cells = <2>;
>
> ranges =
> <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
> 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
> 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
> 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
> 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
> 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
>
>
> pcie at 1,0 {
> /* Port 0, Lane 0 */
> status = "okay";
> };
> };
>
> internal-regs {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
>
> mbusc: mbus-controller at 20000 {
> reg = <0x20000 0x100>, <0x20180 0x20>;
> };
>
> interrupt-controller at 20000 {
> reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> };
> };
> };
After a discussion with Arnd on IRC, here is the new DT layout we came
up with:
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
controller = <&mbusc>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus-bootcs {
status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
nor {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "okay";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie at 1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 1 0 1 0
0x81000000 0 0 0x81000000 1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie at 2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 2 0 1 0
0x81000000 0 0 0x81000000 2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller at 20000 {
reg = <0x20000 0x100>, <0x20180 0x20>;
};
interrupt-controller at 20000 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
};
};
I.e, the changes are :
(1) The main soc {} node gains two new additional DT properties:
pcie-mem-aperture and pcie-io-aperture. The mvebu-mbus reads those
informations, and provides an API
mvebu_mbus_alloc_pcie_{mem,io}_aperture(phys_addr_t *base, size_t
*size) that allows the PCIe driver to get the mem and I/O
apertures for PCIe. In the future, the mvebu-mbus driver may
decide to allocate those apertures dynamically rather than have
values hardcoded in the DT: this is the private business of
mvebu-mbus. For now, the mvebu-mbus driver will use those static
values from the DT, as we don't want to do a full dynamic window
base address allocation for now. This makes sense, as mvebu-mbus
is the "gake keeper" of what gets mapped in terms of mbus windows.
(2) The ranges property of the main pcie-controller {} node is changed
to use 0x82000000 and 0x81000000 for all PCIe interfaces, as requested
by the OF spec. The second 32 bits word of the child address is used
to encode the port number (in our example 1 for the first MEM and I/O
ranges, and 2 for the next MEM and I/O ranges).
(3) A non-empty range property is added in the child pcie at x,y nodes to
translate back into regular PCIe addresses the child addresses
described in the ranges property in pcie-controller. I.e, it
simply translate (0x82000000 0 0) into (0x8200000 <port> 0).
Arnd, Jason, if you could confirm that you both agree with this DT
binding soon, Ezequiel and I would quickly adapt the code accordingly,
and hopefully converge towards a final patch set.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 23:35 ` Thomas Petazzoni
@ 2013-07-05 23:38 ` Arnd Bergmann
-1 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2013-07-05 23:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Thomas Petazzoni, Lior Amsalem, Jason Cooper, Andrew Lunn,
devicetree-discuss, Grant Likely, Jason Gunthorpe, Maen Suleiman,
Ezequiel Garcia, Gregory Clement, Sebastian Hesselbarth
On Saturday 06 July 2013, Thomas Petazzoni wrote:
> Arnd, Jason, if you could confirm that you both agree with this DT
> binding soon, Ezequiel and I would quickly adapt the code accordingly,
> and hopefully converge towards a final patch set.
Looks all good from what I can tell.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-05 23:38 ` Arnd Bergmann
0 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2013-07-05 23:38 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 06 July 2013, Thomas Petazzoni wrote:
> Arnd, Jason, if you could confirm that you both agree with this DT
> binding soon, Ezequiel and I would quickly adapt the code accordingly,
> and hopefully converge towards a final patch set.
Looks all good from what I can tell.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread
[parent not found: <201307060138.36191.arnd-r2nGTMty4D4@public.gmane.org>]
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-05 23:38 ` Arnd Bergmann
@ 2013-07-08 16:42 ` Jason Gunthorpe
-1 siblings, 0 replies; 60+ messages in thread
From: Jason Gunthorpe @ 2013-07-08 16:42 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Lior Amsalem, Jason Cooper, Andrew Lunn,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
On Sat, Jul 06, 2013 at 01:38:35AM +0200, Arnd Bergmann wrote:
> On Saturday 06 July 2013, Thomas Petazzoni wrote:
> > Arnd, Jason, if you could confirm that you both agree with this DT
> > binding soon, Ezequiel and I would quickly adapt the code accordingly,
> > and hopefully converge towards a final patch set.
>
> Looks all good from what I can tell.
It also looks fine to me.
Regards,
Jsaon
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-08 16:42 ` Jason Gunthorpe
0 siblings, 0 replies; 60+ messages in thread
From: Jason Gunthorpe @ 2013-07-08 16:42 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Jul 06, 2013 at 01:38:35AM +0200, Arnd Bergmann wrote:
> On Saturday 06 July 2013, Thomas Petazzoni wrote:
> > Arnd, Jason, if you could confirm that you both agree with this DT
> > binding soon, Ezequiel and I would quickly adapt the code accordingly,
> > and hopefully converge towards a final patch set.
>
> Looks all good from what I can tell.
It also looks fine to me.
Regards,
Jsaon
^ permalink raw reply [flat|nested] 60+ messages in thread
[parent not found: <20130708164225.GA26618-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>]
* Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back
2013-07-08 16:42 ` Jason Gunthorpe
@ 2013-07-08 19:52 ` Ezequiel Garcia
-1 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-08 19:52 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Lior Amsalem, Jason Cooper, Andrew Lunn,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Maen Suleiman,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
On Mon, Jul 08, 2013 at 10:42:25AM -0600, Jason Gunthorpe wrote:
> On Sat, Jul 06, 2013 at 01:38:35AM +0200, Arnd Bergmann wrote:
> > On Saturday 06 July 2013, Thomas Petazzoni wrote:
> > > Arnd, Jason, if you could confirm that you both agree with this DT
> > > binding soon, Ezequiel and I would quickly adapt the code accordingly,
> > > and hopefully converge towards a final patch set.
> >
> > Looks all good from what I can tell.
>
> It also looks fine to me.
>
Ok, great. I'll see if I can rework it and submit something today.
So, as far as I can tell, that would be v7 and would be ready for
inclusion.
Thanks a lot!
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v6 00/21] MBus DT binding: PCIe strikes back
@ 2013-07-08 19:52 ` Ezequiel Garcia
0 siblings, 0 replies; 60+ messages in thread
From: Ezequiel Garcia @ 2013-07-08 19:52 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 08, 2013 at 10:42:25AM -0600, Jason Gunthorpe wrote:
> On Sat, Jul 06, 2013 at 01:38:35AM +0200, Arnd Bergmann wrote:
> > On Saturday 06 July 2013, Thomas Petazzoni wrote:
> > > Arnd, Jason, if you could confirm that you both agree with this DT
> > > binding soon, Ezequiel and I would quickly adapt the code accordingly,
> > > and hopefully converge towards a final patch set.
> >
> > Looks all good from what I can tell.
>
> It also looks fine to me.
>
Ok, great. I'll see if I can rework it and submit something today.
So, as far as I can tell, that would be v7 and would be ready for
inclusion.
Thanks a lot!
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 60+ messages in thread