* [PATCH 0/3] arm: zynq: SLCR clean up
@ 2013-07-17 17:10 ` Soren Brinkmann
0 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: linux-arm-kernel
These are just a few patches cleaning up the driver - well at least I
find it cleaner this way.
3/3 though adds correct read-modify-write for some register accesses.
The current implementation doesn't seem to do any harm, but this looks
better, IMHO.
S?ren
Soren Brinkmann (3):
arm: zynq: slcr: Remove redundant header #includes
arm: zynq: slcr: Clean up #defines
arm: zynq: slcr: Use read-modify-write for register writes
arch/arm/mach-zynq/slcr.c | 45 +++++++++++++++++----------------------------
1 file changed, 17 insertions(+), 28 deletions(-)
--
1.8.3.3
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/3] arm: zynq: slcr: Remove redundant header #includes
2013-07-17 17:10 ` Soren Brinkmann
@ 2013-07-17 17:10 ` Soren Brinkmann
-1 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: Michal Simek, Russell King
Cc: linux-kernel, linux-arm-kernel, Soren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 50d008d..232c275 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -14,18 +14,8 @@
* 02139, USA.
*/
-#include <linux/export.h>
#include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/uaccess.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/string.h>
#include <linux/clk/zynq.h>
#include "common.h"
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 1/3] arm: zynq: slcr: Remove redundant header #includes
@ 2013-07-17 17:10 ` Soren Brinkmann
0 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 50d008d..232c275 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -14,18 +14,8 @@
* 02139, USA.
*/
-#include <linux/export.h>
#include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/uaccess.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/string.h>
#include <linux/clk/zynq.h>
#include "common.h"
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] arm: zynq: slcr: Clean up #defines
2013-07-17 17:10 ` Soren Brinkmann
@ 2013-07-17 17:10 ` Soren Brinkmann
-1 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: Michal Simek, Russell King
Cc: linux-kernel, linux-arm-kernel, Soren Brinkmann
Use a common naming scheme for register offset #defines:
Some of those used a '_OFFSET' suffix to distinguish them from others.
This scheme is used for all register offsets now.
Separate the register offset #defines from others and sort them in
increasing order.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 232c275..44a4ab6 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -19,17 +19,16 @@
#include <linux/clk/zynq.h>
#include "common.h"
-#define SLCR_UNLOCK_MAGIC 0xDF0D
-#define SLCR_UNLOCK 0x8 /* SCLR unlock register */
-
+/* register offsets */
+#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
+#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
+#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
+#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_A9_CPU_CLKSTOP 0x10
#define SLCR_A9_CPU_RST 0x1
-#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */
-#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
-
void __iomem *zynq_slcr_base;
/**
@@ -44,15 +43,15 @@ void zynq_slcr_system_reset(void)
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+ writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
- reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
- writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
+ reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+ writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
}
@@ -64,9 +63,9 @@ void zynq_slcr_cpu_start(int cpu)
{
/* enable CPUn */
writel(SLCR_A9_CPU_CLKSTOP << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
/* enable CLK for CPUn */
- writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -77,7 +76,7 @@ void zynq_slcr_cpu_stop(int cpu)
{
/* stop CLK and reset CPUn */
writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -103,7 +102,7 @@ int __init zynq_slcr_init(void)
}
/* unlock the SLCR so that registers can be changed */
- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+ writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/3] arm: zynq: slcr: Clean up #defines
@ 2013-07-17 17:10 ` Soren Brinkmann
0 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: linux-arm-kernel
Use a common naming scheme for register offset #defines:
Some of those used a '_OFFSET' suffix to distinguish them from others.
This scheme is used for all register offsets now.
Separate the register offset #defines from others and sort them in
increasing order.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 232c275..44a4ab6 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -19,17 +19,16 @@
#include <linux/clk/zynq.h>
#include "common.h"
-#define SLCR_UNLOCK_MAGIC 0xDF0D
-#define SLCR_UNLOCK 0x8 /* SCLR unlock register */
-
+/* register offsets */
+#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
+#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
+#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
+#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_A9_CPU_CLKSTOP 0x10
#define SLCR_A9_CPU_RST 0x1
-#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */
-#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
-
void __iomem *zynq_slcr_base;
/**
@@ -44,15 +43,15 @@ void zynq_slcr_system_reset(void)
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+ writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
- reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
- writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
+ reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+ writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
}
@@ -64,9 +63,9 @@ void zynq_slcr_cpu_start(int cpu)
{
/* enable CPUn */
writel(SLCR_A9_CPU_CLKSTOP << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
/* enable CLK for CPUn */
- writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -77,7 +76,7 @@ void zynq_slcr_cpu_stop(int cpu)
{
/* stop CLK and reset CPUn */
writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
+ zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -103,7 +102,7 @@ int __init zynq_slcr_init(void)
}
/* unlock the SLCR so that registers can be changed */
- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
+ writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
2013-07-17 17:10 ` Soren Brinkmann
@ 2013-07-17 17:10 ` Soren Brinkmann
-1 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: Michal Simek, Russell King
Cc: linux-kernel, linux-arm-kernel, Soren Brinkmann
zynq_slcr_cpu_start/stop() ignored the current register state when
writing to a register. Fixing this by implementing proper
read-modify-write.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 44a4ab6..1836d5a 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
*/
void zynq_slcr_cpu_start(int cpu)
{
- /* enable CPUn */
- writel(SLCR_A9_CPU_CLKSTOP << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
- /* enable CLK for CPUn */
- writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_RST << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
*/
void zynq_slcr_cpu_stop(int cpu)
{
- /* stop CLK and reset CPUn */
- writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
@ 2013-07-17 17:10 ` Soren Brinkmann
0 siblings, 0 replies; 14+ messages in thread
From: Soren Brinkmann @ 2013-07-17 17:10 UTC (permalink / raw)
To: linux-arm-kernel
zynq_slcr_cpu_start/stop() ignored the current register state when
writing to a register. Fixing this by implementing proper
read-modify-write.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 44a4ab6..1836d5a 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
*/
void zynq_slcr_cpu_start(int cpu)
{
- /* enable CPUn */
- writel(SLCR_A9_CPU_CLKSTOP << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
- /* enable CLK for CPUn */
- writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_RST << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
*/
void zynq_slcr_cpu_stop(int cpu)
{
- /* stop CLK and reset CPUn */
- writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
--
1.8.3.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
2013-07-17 17:10 ` Soren Brinkmann
@ 2013-07-18 7:21 ` Steffen Trumtrar
-1 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2013-07-18 7:21 UTC (permalink / raw)
To: Soren Brinkmann
Cc: Michal Simek, Russell King, linux-kernel, linux-arm-kernel
On Wed, Jul 17, 2013 at 10:10:15AM -0700, Sören Brinkmann wrote:
> zynq_slcr_cpu_start/stop() ignored the current register state when
> writing to a register. Fixing this by implementing proper
> read-modify-write.
>
> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> ---
> arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
> index 44a4ab6..1836d5a 100644
> --- a/arch/arm/mach-zynq/slcr.c
> +++ b/arch/arm/mach-zynq/slcr.c
> @@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
> */
> void zynq_slcr_cpu_start(int cpu)
> {
> - /* enable CPUn */
> - writel(SLCR_A9_CPU_CLKSTOP << cpu,
> - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> - /* enable CLK for CPUn */
> - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg &= ~(SLCR_A9_CPU_RST << cpu);
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> }
>
> /**
> @@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
> */
> void zynq_slcr_cpu_stop(int cpu)
> {
> - /* stop CLK and reset CPUn */
> - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
> - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> }
>
Hi!
Why do you also remove the comments? In my opinion they can stay.
Regards,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
@ 2013-07-18 7:21 ` Steffen Trumtrar
0 siblings, 0 replies; 14+ messages in thread
From: Steffen Trumtrar @ 2013-07-18 7:21 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 17, 2013 at 10:10:15AM -0700, S?ren Brinkmann wrote:
> zynq_slcr_cpu_start/stop() ignored the current register state when
> writing to a register. Fixing this by implementing proper
> read-modify-write.
>
> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> ---
> arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
> index 44a4ab6..1836d5a 100644
> --- a/arch/arm/mach-zynq/slcr.c
> +++ b/arch/arm/mach-zynq/slcr.c
> @@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
> */
> void zynq_slcr_cpu_start(int cpu)
> {
> - /* enable CPUn */
> - writel(SLCR_A9_CPU_CLKSTOP << cpu,
> - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> - /* enable CLK for CPUn */
> - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg &= ~(SLCR_A9_CPU_RST << cpu);
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> }
>
> /**
> @@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
> */
> void zynq_slcr_cpu_stop(int cpu)
> {
> - /* stop CLK and reset CPUn */
> - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
> - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
> + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> }
>
Hi!
Why do you also remove the comments? In my opinion they can stay.
Regards,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
2013-07-18 7:21 ` Steffen Trumtrar
@ 2013-07-18 15:45 ` Sören Brinkmann
-1 siblings, 0 replies; 14+ messages in thread
From: Sören Brinkmann @ 2013-07-18 15:45 UTC (permalink / raw)
To: Steffen Trumtrar
Cc: Michal Simek, Russell King, linux-kernel, linux-arm-kernel
On Thu, Jul 18, 2013 at 09:21:06AM +0200, Steffen Trumtrar wrote:
> On Wed, Jul 17, 2013 at 10:10:15AM -0700, Sören Brinkmann wrote:
> > zynq_slcr_cpu_start/stop() ignored the current register state when
> > writing to a register. Fixing this by implementing proper
> > read-modify-write.
> >
> > Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> > ---
> > arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
> > index 44a4ab6..1836d5a 100644
> > --- a/arch/arm/mach-zynq/slcr.c
> > +++ b/arch/arm/mach-zynq/slcr.c
> > @@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
> > */
> > void zynq_slcr_cpu_start(int cpu)
> > {
> > - /* enable CPUn */
> > - writel(SLCR_A9_CPU_CLKSTOP << cpu,
> > - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > - /* enable CLK for CPUn */
> > - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg &= ~(SLCR_A9_CPU_RST << cpu);
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > }
> >
> > /**
> > @@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
> > */
> > void zynq_slcr_cpu_stop(int cpu)
> > {
> > - /* stop CLK and reset CPUn */
> > - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
> > - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > }
> >
>
> Hi!
>
> Why do you also remove the comments? In my opinion they can stay.
I found the #defines descriptive enough
Sören
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 3/3] arm: zynq: slcr: Use read-modify-write for register writes
@ 2013-07-18 15:45 ` Sören Brinkmann
0 siblings, 0 replies; 14+ messages in thread
From: Sören Brinkmann @ 2013-07-18 15:45 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 18, 2013 at 09:21:06AM +0200, Steffen Trumtrar wrote:
> On Wed, Jul 17, 2013 at 10:10:15AM -0700, S?ren Brinkmann wrote:
> > zynq_slcr_cpu_start/stop() ignored the current register state when
> > writing to a register. Fixing this by implementing proper
> > read-modify-write.
> >
> > Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> > ---
> > arch/arm/mach-zynq/slcr.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
> > index 44a4ab6..1836d5a 100644
> > --- a/arch/arm/mach-zynq/slcr.c
> > +++ b/arch/arm/mach-zynq/slcr.c
> > @@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
> > */
> > void zynq_slcr_cpu_start(int cpu)
> > {
> > - /* enable CPUn */
> > - writel(SLCR_A9_CPU_CLKSTOP << cpu,
> > - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > - /* enable CLK for CPUn */
> > - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg &= ~(SLCR_A9_CPU_RST << cpu);
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > }
> >
> > /**
> > @@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
> > */
> > void zynq_slcr_cpu_stop(int cpu)
> > {
> > - /* stop CLK and reset CPUn */
> > - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
> > - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
> > + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
> > }
> >
>
> Hi!
>
> Why do you also remove the comments? In my opinion they can stay.
I found the #defines descriptive enough
S?ren
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/3] arm: zynq: SLCR clean up
2013-07-17 17:10 ` Soren Brinkmann
@ 2013-07-26 12:15 ` Michal Simek
-1 siblings, 0 replies; 14+ messages in thread
From: Michal Simek @ 2013-07-26 12:15 UTC (permalink / raw)
To: Soren Brinkmann
Cc: Michal Simek, Russell King, linux-kernel, linux-arm-kernel
On 07/17/2013 07:10 PM, Soren Brinkmann wrote:
> These are just a few patches cleaning up the driver - well at least I
> find it cleaner this way.
> 3/3 though adds correct read-modify-write for some register accesses.
> The current implementation doesn't seem to do any harm, but this looks
> better, IMHO.
>
> Sören
>
> Soren Brinkmann (3):
> arm: zynq: slcr: Remove redundant header #includes
> arm: zynq: slcr: Clean up #defines
> arm: zynq: slcr: Use read-modify-write for register writes
>
> arch/arm/mach-zynq/slcr.c | 45 +++++++++++++++++----------------------------
> 1 file changed, 17 insertions(+), 28 deletions(-)
Applied to zynq/cleanup branch.
Thanks,
Michal
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/3] arm: zynq: SLCR clean up
@ 2013-07-26 12:15 ` Michal Simek
0 siblings, 0 replies; 14+ messages in thread
From: Michal Simek @ 2013-07-26 12:15 UTC (permalink / raw)
To: linux-arm-kernel
On 07/17/2013 07:10 PM, Soren Brinkmann wrote:
> These are just a few patches cleaning up the driver - well at least I
> find it cleaner this way.
> 3/3 though adds correct read-modify-write for some register accesses.
> The current implementation doesn't seem to do any harm, but this looks
> better, IMHO.
>
> S?ren
>
> Soren Brinkmann (3):
> arm: zynq: slcr: Remove redundant header #includes
> arm: zynq: slcr: Clean up #defines
> arm: zynq: slcr: Use read-modify-write for register writes
>
> arch/arm/mach-zynq/slcr.c | 45 +++++++++++++++++----------------------------
> 1 file changed, 17 insertions(+), 28 deletions(-)
Applied to zynq/cleanup branch.
Thanks,
Michal
^ permalink raw reply [flat|nested] 14+ messages in thread