* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-17 13:34 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:34 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This patch series is a proposal to move at91 clock implementation
to common clk framework.
Most of the clock provided by the PMC (Power Management Controller) are
implemented :
- main clock (main oscillator)
- pll clocks
- master clock
- programmable clocks
- utmi clock
- peripheral clocks
- system clocks
This implementation is compatible with device tree: the goal is
to define the whole clock tree in the device tree (all currently
available dt SoCs and boards are patched to support dt clocks).
Please feel free to comment the dt bindinds.
I removed the register_clocks function in SoC supporting dt boards only:
- at91sam9x5 SoCs
- at91sam9n12 SoC
- sama5d3 SoCs
This patch series is based on linux-next and has been tested on sama5d31ek
board using device tree. It compiles for other SoCs and both with and without
dt support, but it has not been tested.
BTW could other people test it on other boards (I only have a kizbox and
a sama5d31ek dev kit).
Best Regards,
Boris
Changes since v1:
- fix bugs in pll, programmable and system clock implementations
(wrong bit position).
- add usb clock configuration support (ohci and udc drivers +
clk_lookup for non dt boards)
- rework of the system clock interfaces (no need to define a parent clock,
system clock is a gate with no rate info)
- change system, peripheral and programmable clk dt bindings (1 master node
and multiple child nodes each defining a system/peripheral or prog clock)
- fix bugs in sama5 dt definition
Boris BREZILLON (42):
ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
ARM: at91: add PMC main clock
ARM: at91: add PMC pll clocks
ARM: at91: add PMC master clock
ARM: at91: add PMC system clocks
ARM: at91: add PMC peripheral clocks
ARM: at91: add PMC programmable clocks
ARM: at91: add PMC utmi clock
ARM: at91: add PMC usb clock
ARM: at91: add PMC smd clock
ARM: at91: add PMC clk device tree binding doc.
ARM: at91: move to common clk framework
ARM: at91: move at91rm9200 SoC to new at91 clk implem
ARM: at91: move at91sam9260 SoC to new at91 clk implem
ARM: at91: move at91sam9261 SoC to new at91 clk implem
ARM: at91: move at91sam9263 SoC to new at91 clk implem
ARM: at91: move at91sam9g45 SoC to new at91 clk implem
ARM: at91: move at91sam9n12 SoC to new at91 clk implem
ARM: at91: move at91sam9rl SoC to new at91 clk implem
ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
ARM: at91: move at91sam9 SoCs to new at91 clk implem
ARM: at91: move sama5d3 SoCs to new at91 clk implem
ARM: at91: move at91rm9200 boards to new at91 clk implem
ARM: at91: move at91sam9 boards to new at91 clk implem
ARM: at91: move pit timer to common clk framework
USB: ohci-at91: add usb_clk for transition to common clk framework
usb: gadget: at91_udc: add usb_clk for transition to common clk
framework
ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
ARM: at91/dt: move rm9200 boards to new at91 clk implem
ARM: at91/dt: move sam9263 boards to new at91 clk implem
ARM: at91/dt: move sam9g45 boards to new at91 clk implem
ARM: at91/dt: move sam9n12 boards to new at91 clk implem
ARM: at91/dt: move sam9x5 boards to new at91 clk implem
ARM: at91/dt: move sama5d3 boards to new at91 clk implem
.../devicetree/bindings/clock/at91-clock.txt | 262 ++++++
arch/arm/boot/dts/animeo_ip.dts | 17 +-
arch/arm/boot/dts/at91-ariag25.dts | 17 +-
arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++
arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
arch/arm/boot/dts/at91sam9260.dtsi | 236 +++++
arch/arm/boot/dts/at91sam9263.dtsi | 237 +++++
arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
arch/arm/boot/dts/at91sam9g45.dtsi | 257 +++++
arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 251 +++++
arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++--
arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +
arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 ++
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 ++
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++
arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
arch/arm/boot/dts/kizbox.dts | 5 +
arch/arm/boot/dts/mpa1600.dts | 16 +-
arch/arm/boot/dts/pm9g45.dts | 16 +-
arch/arm/boot/dts/sama5d3.dtsi | 510 ++++++----
arch/arm/boot/dts/sama5d31ek.dts | 4 +
arch/arm/boot/dts/sama5d33ek.dts | 2 +
arch/arm/boot/dts/sama5d34ek.dts | 4 +
arch/arm/boot/dts/sama5d35ek.dts | 6 +
arch/arm/boot/dts/sama5d3_can.dtsi | 71 ++
arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++
arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++
arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 ++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +
arch/arm/boot/dts/sama5d3_uart.dtsi | 46 +
arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
arch/arm/boot/dts/tny_a9263.dts | 17 +-
arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
arch/arm/boot/dts/usb_a9263.dts | 17 +-
arch/arm/mach-at91/Kconfig | 26 +
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/at91rm9200.c | 568 +++++++-----
arch/arm/mach-at91/at91sam9260.c | 689 +++++++++-----
arch/arm/mach-at91/at91sam9261.c | 572 ++++++++----
arch/arm/mach-at91/at91sam9263.c | 595 +++++++-----
arch/arm/mach-at91/at91sam926x_time.c | 21 +-
arch/arm/mach-at91/at91sam9g45.c | 704 ++++++++------
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
arch/arm/mach-at91/at91sam9n12.c | 196 +---
arch/arm/mach-at91/at91sam9rl.c | 502 ++++++----
arch/arm/mach-at91/at91sam9x5.c | 293 +-----
arch/arm/mach-at91/board-1arm.c | 12 +-
arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
arch/arm/mach-at91/board-cam60.c | 13 +-
arch/arm/mach-at91/board-carmeva.c | 13 +-
arch/arm/mach-at91/board-cpu9krea.c | 12 +-
arch/arm/mach-at91/board-cpuat91.c | 12 +-
arch/arm/mach-at91/board-csb337.c | 11 +-
arch/arm/mach-at91/board-csb637.c | 11 +-
arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
arch/arm/mach-at91/board-dt-sam9.c | 9 +-
arch/arm/mach-at91/board-dt-sama5.c | 9 +-
arch/arm/mach-at91/board-eb9200.c | 11 +-
arch/arm/mach-at91/board-ecbat91.c | 12 +-
arch/arm/mach-at91/board-eco920.c | 13 +-
arch/arm/mach-at91/board-flexibity.c | 12 +-
arch/arm/mach-at91/board-foxg20.c | 12 +-
arch/arm/mach-at91/board-gsia18s.c | 8 +-
arch/arm/mach-at91/board-kafa.c | 12 +-
arch/arm/mach-at91/board-kb9202.c | 12 +-
arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
arch/arm/mach-at91/board-picotux200.c | 11 +-
arch/arm/mach-at91/board-qil-a9260.c | 11 +-
arch/arm/mach-at91/board-rm9200ek.c | 11 +-
arch/arm/mach-at91/board-rsi-ews.c | 12 +-
arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
arch/arm/mach-at91/board-sam9260ek.c | 11 +-
arch/arm/mach-at91/board-sam9261ek.c | 15 +-
arch/arm/mach-at91/board-sam9263ek.c | 11 +-
arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
arch/arm/mach-at91/board-sam9rlek.c | 11 +-
arch/arm/mach-at91/board-snapper9260.c | 12 +-
arch/arm/mach-at91/board-stamp9g20.c | 15 +-
arch/arm/mach-at91/board-yl-9200.c | 12 +-
arch/arm/mach-at91/clock.c | 977 --------------------
arch/arm/mach-at91/clock.h | 49 -
arch/arm/mach-at91/generic.h | 10 +-
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/pmc.c | 58 ++
arch/arm/mach-at91/sama5d3.c | 344 +------
arch/arm/mach-at91/setup.c | 38 +-
arch/arm/mach-at91/stamp9g20.h | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/at91/Makefile | 11 +
drivers/clk/at91/clk-main.c | 106 +++
drivers/clk/at91/clk-master.c | 317 +++++++
drivers/clk/at91/clk-peripheral.c | 371 ++++++++
drivers/clk/at91/clk-pll.c | 438 +++++++++
drivers/clk/at91/clk-plldiv.c | 125 +++
drivers/clk/at91/clk-programmable.c | 368 ++++++++
drivers/clk/at91/clk-smd.c | 157 ++++
drivers/clk/at91/clk-system.c | 184 ++++
drivers/clk/at91/clk-usb.c | 303 ++++++
drivers/clk/at91/clk-utmi.c | 114 +++
drivers/usb/gadget/at91_udc.c | 31 +-
drivers/usb/gadget/at91_udc.h | 2 +-
drivers/usb/gadget/atmel_usba_udc.c | 2 +-
drivers/usb/host/ohci-at91.c | 16 +-
.../mach/at91_pmc.h => include/linux/clk/at91.h | 116 ++-
119 files changed, 8193 insertions(+), 3835 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
delete mode 100644 arch/arm/mach-at91/clock.c
delete mode 100644 arch/arm/mach-at91/clock.h
create mode 100644 arch/arm/mach-at91/pmc.c
create mode 100644 drivers/clk/at91/Makefile
create mode 100644 drivers/clk/at91/clk-main.c
create mode 100644 drivers/clk/at91/clk-master.c
create mode 100644 drivers/clk/at91/clk-peripheral.c
create mode 100644 drivers/clk/at91/clk-pll.c
create mode 100644 drivers/clk/at91/clk-plldiv.c
create mode 100644 drivers/clk/at91/clk-programmable.c
create mode 100644 drivers/clk/at91/clk-smd.c
create mode 100644 drivers/clk/at91/clk-system.c
create mode 100644 drivers/clk/at91/clk-usb.c
create mode 100644 drivers/clk/at91/clk-utmi.c
rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (78%)
--
1.7.9.5
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:37 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:37 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King, Felipe Balbi, Greg Kroah-Hartman, Josh Wu
Cc: linux-arm-kernel, linux-kernel, linux-usb, Boris BREZILLON
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91rm9200.c | 2 +-
arch/arm/mach-at91/at91sam9260.c | 2 +-
arch/arm/mach-at91/at91sam9261.c | 2 +-
arch/arm/mach-at91/at91sam9263.c | 2 +-
arch/arm/mach-at91/at91sam9g45.c | 2 +-
arch/arm/mach-at91/at91sam9n12.c | 2 +-
arch/arm/mach-at91/at91sam9rl.c | 2 +-
arch/arm/mach-at91/at91sam9x5.c | 2 +-
arch/arm/mach-at91/clock.c | 2 +-
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/sama5d3.c | 2 +-
arch/arm/mach-at91/setup.c | 2 +-
drivers/usb/gadget/atmel_usba_udc.c | 2 +-
.../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
15 files changed, 15 insertions(+), 15 deletions(-)
rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 4aad93d..8de5b02 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,13 +12,13 @@
#include <linux/module.h>
#include <linux/reboot.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91rm9200.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_st.h>
#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5de6074..db9d89a 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -20,7 +21,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 0e07932..a4123bd 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91sam9261.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 6ce7d18..e0a1a68 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -18,7 +19,6 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9263.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 474ee04..29ba2ca 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c7d670d..c270503 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d4ec0d9..2694bd1 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 2abee66..9fdea07 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b2630a..cc263d0 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include <asm/proc-fns.h>
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 15afb5d..de425e0 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..76387e0 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
*/
#include <linux/linkage.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_ramc.h>
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 4012797..32e0522 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,12 +9,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d3.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "soc.h"
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index b17fbcf..de3c519 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
#include <linux/pm.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
+#include <linux/clk/at91.h>
#include <asm/system_misc.h>
#include <asm/mach/map.h>
@@ -18,7 +19,6 @@
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
#include "at91_shdwc.h"
#include "soc.h"
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f018017..a678537 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
#if defined(CONFIG_ARCH_AT91SAM9RL)
-#include <mach/at91_pmc.h>
+#include <linux/clk/at91.h>
static void toggle_bias(int is_on)
{
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
similarity index 99%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to include/linux/clk/at91.h
index c604cc6..0ce9586 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/include/linux/clk/at91.h
@@ -1,5 +1,5 @@
/*
- * arch/arm/mach-at91/include/mach/at91_pmc.h
+ * include/linux/clk/at91.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
@ 2013-07-17 13:37 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:37 UTC (permalink / raw)
To: linux-arm-kernel
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91rm9200.c | 2 +-
arch/arm/mach-at91/at91sam9260.c | 2 +-
arch/arm/mach-at91/at91sam9261.c | 2 +-
arch/arm/mach-at91/at91sam9263.c | 2 +-
arch/arm/mach-at91/at91sam9g45.c | 2 +-
arch/arm/mach-at91/at91sam9n12.c | 2 +-
arch/arm/mach-at91/at91sam9rl.c | 2 +-
arch/arm/mach-at91/at91sam9x5.c | 2 +-
arch/arm/mach-at91/clock.c | 2 +-
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/sama5d3.c | 2 +-
arch/arm/mach-at91/setup.c | 2 +-
drivers/usb/gadget/atmel_usba_udc.c | 2 +-
.../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
15 files changed, 15 insertions(+), 15 deletions(-)
rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 4aad93d..8de5b02 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,13 +12,13 @@
#include <linux/module.h>
#include <linux/reboot.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91rm9200.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_st.h>
#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5de6074..db9d89a 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -20,7 +21,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 0e07932..a4123bd 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91sam9261.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 6ce7d18..e0a1a68 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -18,7 +19,6 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9263.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 474ee04..29ba2ca 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c7d670d..c270503 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d4ec0d9..2694bd1 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 2abee66..9fdea07 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b2630a..cc263d0 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include <asm/proc-fns.h>
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 15afb5d..de425e0 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..76387e0 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
*/
#include <linux/linkage.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_ramc.h>
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 4012797..32e0522 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,12 +9,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d3.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "soc.h"
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index b17fbcf..de3c519 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
#include <linux/pm.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
+#include <linux/clk/at91.h>
#include <asm/system_misc.h>
#include <asm/mach/map.h>
@@ -18,7 +19,6 @@
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
#include "at91_shdwc.h"
#include "soc.h"
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f018017..a678537 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
#if defined(CONFIG_ARCH_AT91SAM9RL)
-#include <mach/at91_pmc.h>
+#include <linux/clk/at91.h>
static void toggle_bias(int is_on)
{
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
similarity index 99%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to include/linux/clk/at91.h
index c604cc6..0ce9586 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/include/linux/clk/at91.h
@@ -1,5 +1,5 @@
/*
- * arch/arm/mach-at91/include/mach/at91_pmc.h
+ * include/linux/clk/at91.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* Re: [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
2013-07-17 13:37 ` Boris BREZILLON
@ 2013-07-23 18:03 ` Jean-Christophe PLAGNIOL-VILLARD
-1 siblings, 0 replies; 129+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-07-23 18:03 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches, Mike Turquette, Andrew Victor,
Russell King, Felipe Balbi, Greg Kroah-Hartman, Josh Wu,
linux-arm-kernel, linux-kernel, linux-usb
On 15:37 Wed 17 Jul , Boris BREZILLON wrote:
> This patch moves at91_pmc.h header from machine specific directory
> (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
> (include/linux/clk/at91.h).
please the at91_pmc.h in the name
so we known the IP that we use and if we change it we will not have to rename
it in the futur
otherwise
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Best Regards,
J.
> We need this to avoid reference to machine specific headers in clk
> drivers.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> arch/arm/mach-at91/at91rm9200.c | 2 +-
> arch/arm/mach-at91/at91sam9260.c | 2 +-
> arch/arm/mach-at91/at91sam9261.c | 2 +-
> arch/arm/mach-at91/at91sam9263.c | 2 +-
> arch/arm/mach-at91/at91sam9g45.c | 2 +-
> arch/arm/mach-at91/at91sam9n12.c | 2 +-
> arch/arm/mach-at91/at91sam9rl.c | 2 +-
> arch/arm/mach-at91/at91sam9x5.c | 2 +-
> arch/arm/mach-at91/clock.c | 2 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/sama5d3.c | 2 +-
> arch/arm/mach-at91/setup.c | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
> 15 files changed, 15 insertions(+), 15 deletions(-)
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
>
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index 4aad93d..8de5b02 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -12,13 +12,13 @@
>
> #include <linux/module.h>
> #include <linux/reboot.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91rm9200.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_st.h>
> #include <mach/cpu.h>
>
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 5de6074..db9d89a 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -20,7 +21,6 @@
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> #include <mach/at91sam9260.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index 0e07932..a4123bd 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -19,7 +20,6 @@
> #include <asm/system_misc.h>
> #include <mach/cpu.h>
> #include <mach/at91sam9261.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 6ce7d18..e0a1a68 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -18,7 +19,6 @@
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91sam9263.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 474ee04..29ba2ca 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -12,13 +12,13 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91sam9g45.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index c7d670d..c270503 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -8,12 +8,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/at91sam9n12.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "board.h"
> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
> index d4ec0d9..2694bd1 100644
> --- a/arch/arm/mach-at91/at91sam9rl.c
> +++ b/arch/arm/mach-at91/at91sam9rl.c
> @@ -10,6 +10,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -19,7 +20,6 @@
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> #include <mach/at91sam9rl.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 2abee66..9fdea07 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -8,12 +8,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/at91sam9x5.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "board.h"
> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
> index 6b2630a..cc263d0 100644
> --- a/arch/arm/mach-at91/clock.c
> +++ b/arch/arm/mach-at91/clock.c
> @@ -24,9 +24,9 @@
> #include <linux/clk.h>
> #include <linux/io.h>
> #include <linux/of_address.h>
> +#include <linux/clk/at91.h>
>
> #include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include <asm/proc-fns.h>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 15afb5d..de425e0 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -19,13 +19,13 @@
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/io.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <linux/atomic.h>
> #include <asm/mach/time.h>
> #include <asm/mach/irq.h>
>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 098c28d..76387e0 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -13,8 +13,8 @@
> */
>
> #include <linux/linkage.h>
> +#include <linux/clk/at91.h>
> #include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_ramc.h>
>
>
> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
> index 4012797..32e0522 100644
> --- a/arch/arm/mach-at91/sama5d3.c
> +++ b/arch/arm/mach-at91/sama5d3.c
> @@ -9,12 +9,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/sama5d3.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "soc.h"
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index b17fbcf..de3c519 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -11,6 +11,7 @@
> #include <linux/pm.h>
> #include <linux/of_address.h>
> #include <linux/pinctrl/machine.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/system_misc.h>
> #include <asm/mach/map.h>
> @@ -18,7 +19,6 @@
> #include <mach/hardware.h>
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_shdwc.h"
> #include "soc.h"
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
> index f018017..a678537 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
>
> #if defined(CONFIG_ARCH_AT91SAM9RL)
>
> -#include <mach/at91_pmc.h>
> +#include <linux/clk/at91.h>
>
> static void toggle_bias(int is_on)
> {
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
> similarity index 99%
> rename from arch/arm/mach-at91/include/mach/at91_pmc.h
> rename to include/linux/clk/at91.h
> index c604cc6..0ce9586 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/include/linux/clk/at91.h
> @@ -1,5 +1,5 @@
> /*
> - * arch/arm/mach-at91/include/mach/at91_pmc.h
> + * include/linux/clk/at91.h
> *
> * Copyright (C) 2005 Ivan Kokshaysky
> * Copyright (C) SAN People
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
@ 2013-07-23 18:03 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 129+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-07-23 18:03 UTC (permalink / raw)
To: linux-arm-kernel
On 15:37 Wed 17 Jul , Boris BREZILLON wrote:
> This patch moves at91_pmc.h header from machine specific directory
> (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
> (include/linux/clk/at91.h).
please the at91_pmc.h in the name
so we known the IP that we use and if we change it we will not have to rename
it in the futur
otherwise
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Best Regards,
J.
> We need this to avoid reference to machine specific headers in clk
> drivers.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> arch/arm/mach-at91/at91rm9200.c | 2 +-
> arch/arm/mach-at91/at91sam9260.c | 2 +-
> arch/arm/mach-at91/at91sam9261.c | 2 +-
> arch/arm/mach-at91/at91sam9263.c | 2 +-
> arch/arm/mach-at91/at91sam9g45.c | 2 +-
> arch/arm/mach-at91/at91sam9n12.c | 2 +-
> arch/arm/mach-at91/at91sam9rl.c | 2 +-
> arch/arm/mach-at91/at91sam9x5.c | 2 +-
> arch/arm/mach-at91/clock.c | 2 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/sama5d3.c | 2 +-
> arch/arm/mach-at91/setup.c | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
> 15 files changed, 15 insertions(+), 15 deletions(-)
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
>
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index 4aad93d..8de5b02 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -12,13 +12,13 @@
>
> #include <linux/module.h>
> #include <linux/reboot.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91rm9200.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_st.h>
> #include <mach/cpu.h>
>
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 5de6074..db9d89a 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -20,7 +21,6 @@
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> #include <mach/at91sam9260.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index 0e07932..a4123bd 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -19,7 +20,6 @@
> #include <asm/system_misc.h>
> #include <mach/cpu.h>
> #include <mach/at91sam9261.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 6ce7d18..e0a1a68 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -11,6 +11,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -18,7 +19,6 @@
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91sam9263.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 474ee04..29ba2ca 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -12,13 +12,13 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
> #include <mach/at91sam9g45.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index c7d670d..c270503 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -8,12 +8,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/at91sam9n12.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "board.h"
> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
> index d4ec0d9..2694bd1 100644
> --- a/arch/arm/mach-at91/at91sam9rl.c
> +++ b/arch/arm/mach-at91/at91sam9rl.c
> @@ -10,6 +10,7 @@
> */
>
> #include <linux/module.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/proc-fns.h>
> #include <asm/irq.h>
> @@ -19,7 +20,6 @@
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> #include <mach/at91sam9rl.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_aic.h"
> #include "at91_rstc.h"
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 2abee66..9fdea07 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -8,12 +8,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/at91sam9x5.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "board.h"
> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
> index 6b2630a..cc263d0 100644
> --- a/arch/arm/mach-at91/clock.c
> +++ b/arch/arm/mach-at91/clock.c
> @@ -24,9 +24,9 @@
> #include <linux/clk.h>
> #include <linux/io.h>
> #include <linux/of_address.h>
> +#include <linux/clk/at91.h>
>
> #include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include <asm/proc-fns.h>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 15afb5d..de425e0 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -19,13 +19,13 @@
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/io.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <linux/atomic.h>
> #include <asm/mach/time.h>
> #include <asm/mach/irq.h>
>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 098c28d..76387e0 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -13,8 +13,8 @@
> */
>
> #include <linux/linkage.h>
> +#include <linux/clk/at91.h>
> #include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> #include <mach/at91_ramc.h>
>
>
> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
> index 4012797..32e0522 100644
> --- a/arch/arm/mach-at91/sama5d3.c
> +++ b/arch/arm/mach-at91/sama5d3.c
> @@ -9,12 +9,12 @@
>
> #include <linux/module.h>
> #include <linux/dma-mapping.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/irq.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <mach/sama5d3.h>
> -#include <mach/at91_pmc.h>
> #include <mach/cpu.h>
>
> #include "soc.h"
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index b17fbcf..de3c519 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -11,6 +11,7 @@
> #include <linux/pm.h>
> #include <linux/of_address.h>
> #include <linux/pinctrl/machine.h>
> +#include <linux/clk/at91.h>
>
> #include <asm/system_misc.h>
> #include <asm/mach/map.h>
> @@ -18,7 +19,6 @@
> #include <mach/hardware.h>
> #include <mach/cpu.h>
> #include <mach/at91_dbgu.h>
> -#include <mach/at91_pmc.h>
>
> #include "at91_shdwc.h"
> #include "soc.h"
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
> index f018017..a678537 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
>
> #if defined(CONFIG_ARCH_AT91SAM9RL)
>
> -#include <mach/at91_pmc.h>
> +#include <linux/clk/at91.h>
>
> static void toggle_bias(int is_on)
> {
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
> similarity index 99%
> rename from arch/arm/mach-at91/include/mach/at91_pmc.h
> rename to include/linux/clk/at91.h
> index c604cc6..0ce9586 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/include/linux/clk/at91.h
> @@ -1,5 +1,5 @@
> /*
> - * arch/arm/mach-at91/include/mach/at91_pmc.h
> + * include/linux/clk/at91.h
> *
> * Copyright (C) 2005 Ivan Kokshaysky
> * Copyright (C) SAN People
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
2013-07-23 18:03 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-07-23 22:24 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-23 22:24 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD
Cc: Nicolas Ferre, Ludovic Desroches, Mike Turquette, Andrew Victor,
Russell King, Felipe Balbi, Greg Kroah-Hartman, Josh Wu,
linux-arm-kernel, linux-kernel, linux-usb
Le 23/07/2013 20:03, Jean-Christophe PLAGNIOL-VILLARD a écrit :
> On 15:37 Wed 17 Jul , Boris BREZILLON wrote:
>> This patch moves at91_pmc.h header from machine specific directory
>> (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
>> (include/linux/clk/at91.h).
> please the at91_pmc.h in the name
>
> so we known the IP that we use and if we change it we will not have to rename
> it in the futur
OK. I will change the name to at91_pmc.h in the next version.
>
> otherwise
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>
> Best Regards,
> J.
>> We need this to avoid reference to machine specific headers in clk
>> drivers.
>>
>> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
>> ---
>> arch/arm/mach-at91/at91rm9200.c | 2 +-
>> arch/arm/mach-at91/at91sam9260.c | 2 +-
>> arch/arm/mach-at91/at91sam9261.c | 2 +-
>> arch/arm/mach-at91/at91sam9263.c | 2 +-
>> arch/arm/mach-at91/at91sam9g45.c | 2 +-
>> arch/arm/mach-at91/at91sam9n12.c | 2 +-
>> arch/arm/mach-at91/at91sam9rl.c | 2 +-
>> arch/arm/mach-at91/at91sam9x5.c | 2 +-
>> arch/arm/mach-at91/clock.c | 2 +-
>> arch/arm/mach-at91/pm.c | 2 +-
>> arch/arm/mach-at91/pm_slowclock.S | 2 +-
>> arch/arm/mach-at91/sama5d3.c | 2 +-
>> arch/arm/mach-at91/setup.c | 2 +-
>> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
>> .../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
>> 15 files changed, 15 insertions(+), 15 deletions(-)
>> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
>>
>> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
>> index 4aad93d..8de5b02 100644
>> --- a/arch/arm/mach-at91/at91rm9200.c
>> +++ b/arch/arm/mach-at91/at91rm9200.c
>> @@ -12,13 +12,13 @@
>>
>> #include <linux/module.h>
>> #include <linux/reboot.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91rm9200.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/at91_st.h>
>> #include <mach/cpu.h>
>>
>> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
>> index 5de6074..db9d89a 100644
>> --- a/arch/arm/mach-at91/at91sam9260.c
>> +++ b/arch/arm/mach-at91/at91sam9260.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -20,7 +21,6 @@
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> #include <mach/at91sam9260.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
>> index 0e07932..a4123bd 100644
>> --- a/arch/arm/mach-at91/at91sam9261.c
>> +++ b/arch/arm/mach-at91/at91sam9261.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -19,7 +20,6 @@
>> #include <asm/system_misc.h>
>> #include <mach/cpu.h>
>> #include <mach/at91sam9261.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
>> index 6ce7d18..e0a1a68 100644
>> --- a/arch/arm/mach-at91/at91sam9263.c
>> +++ b/arch/arm/mach-at91/at91sam9263.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -18,7 +19,6 @@
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91sam9263.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
>> index 474ee04..29ba2ca 100644
>> --- a/arch/arm/mach-at91/at91sam9g45.c
>> +++ b/arch/arm/mach-at91/at91sam9g45.c
>> @@ -12,13 +12,13 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91sam9g45.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "at91_aic.h"
>> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
>> index c7d670d..c270503 100644
>> --- a/arch/arm/mach-at91/at91sam9n12.c
>> +++ b/arch/arm/mach-at91/at91sam9n12.c
>> @@ -8,12 +8,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/at91sam9n12.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "board.h"
>> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
>> index d4ec0d9..2694bd1 100644
>> --- a/arch/arm/mach-at91/at91sam9rl.c
>> +++ b/arch/arm/mach-at91/at91sam9rl.c
>> @@ -10,6 +10,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -19,7 +20,6 @@
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> #include <mach/at91sam9rl.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
>> index 2abee66..9fdea07 100644
>> --- a/arch/arm/mach-at91/at91sam9x5.c
>> +++ b/arch/arm/mach-at91/at91sam9x5.c
>> @@ -8,12 +8,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/at91sam9x5.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "board.h"
>> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
>> index 6b2630a..cc263d0 100644
>> --- a/arch/arm/mach-at91/clock.c
>> +++ b/arch/arm/mach-at91/clock.c
>> @@ -24,9 +24,9 @@
>> #include <linux/clk.h>
>> #include <linux/io.h>
>> #include <linux/of_address.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <mach/hardware.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include <asm/proc-fns.h>
>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>> index 15afb5d..de425e0 100644
>> --- a/arch/arm/mach-at91/pm.c
>> +++ b/arch/arm/mach-at91/pm.c
>> @@ -19,13 +19,13 @@
>> #include <linux/module.h>
>> #include <linux/platform_device.h>
>> #include <linux/io.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <linux/atomic.h>
>> #include <asm/mach/time.h>
>> #include <asm/mach/irq.h>
>>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "at91_aic.h"
>> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
>> index 098c28d..76387e0 100644
>> --- a/arch/arm/mach-at91/pm_slowclock.S
>> +++ b/arch/arm/mach-at91/pm_slowclock.S
>> @@ -13,8 +13,8 @@
>> */
>>
>> #include <linux/linkage.h>
>> +#include <linux/clk/at91.h>
>> #include <mach/hardware.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/at91_ramc.h>
>>
>>
>> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
>> index 4012797..32e0522 100644
>> --- a/arch/arm/mach-at91/sama5d3.c
>> +++ b/arch/arm/mach-at91/sama5d3.c
>> @@ -9,12 +9,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/sama5d3.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "soc.h"
>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>> index b17fbcf..de3c519 100644
>> --- a/arch/arm/mach-at91/setup.c
>> +++ b/arch/arm/mach-at91/setup.c
>> @@ -11,6 +11,7 @@
>> #include <linux/pm.h>
>> #include <linux/of_address.h>
>> #include <linux/pinctrl/machine.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/system_misc.h>
>> #include <asm/mach/map.h>
>> @@ -18,7 +19,6 @@
>> #include <mach/hardware.h>
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_shdwc.h"
>> #include "soc.h"
>> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
>> index f018017..a678537 100644
>> --- a/drivers/usb/gadget/atmel_usba_udc.c
>> +++ b/drivers/usb/gadget/atmel_usba_udc.c
>> @@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
>>
>> #if defined(CONFIG_ARCH_AT91SAM9RL)
>>
>> -#include <mach/at91_pmc.h>
>> +#include <linux/clk/at91.h>
>>
>> static void toggle_bias(int is_on)
>> {
>> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
>> similarity index 99%
>> rename from arch/arm/mach-at91/include/mach/at91_pmc.h
>> rename to include/linux/clk/at91.h
>> index c604cc6..0ce9586 100644
>> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
>> +++ b/include/linux/clk/at91.h
>> @@ -1,5 +1,5 @@
>> /*
>> - * arch/arm/mach-at91/include/mach/at91_pmc.h
>> + * include/linux/clk/at91.h
>> *
>> * Copyright (C) 2005 Ivan Kokshaysky
>> * Copyright (C) SAN People
>> --
>> 1.7.9.5
>>
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 01/42] ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
@ 2013-07-23 22:24 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-23 22:24 UTC (permalink / raw)
To: linux-arm-kernel
Le 23/07/2013 20:03, Jean-Christophe PLAGNIOL-VILLARD a ?crit :
> On 15:37 Wed 17 Jul , Boris BREZILLON wrote:
>> This patch moves at91_pmc.h header from machine specific directory
>> (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
>> (include/linux/clk/at91.h).
> please the at91_pmc.h in the name
>
> so we known the IP that we use and if we change it we will not have to rename
> it in the futur
OK. I will change the name to at91_pmc.h in the next version.
>
> otherwise
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>
> Best Regards,
> J.
>> We need this to avoid reference to machine specific headers in clk
>> drivers.
>>
>> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
>> ---
>> arch/arm/mach-at91/at91rm9200.c | 2 +-
>> arch/arm/mach-at91/at91sam9260.c | 2 +-
>> arch/arm/mach-at91/at91sam9261.c | 2 +-
>> arch/arm/mach-at91/at91sam9263.c | 2 +-
>> arch/arm/mach-at91/at91sam9g45.c | 2 +-
>> arch/arm/mach-at91/at91sam9n12.c | 2 +-
>> arch/arm/mach-at91/at91sam9rl.c | 2 +-
>> arch/arm/mach-at91/at91sam9x5.c | 2 +-
>> arch/arm/mach-at91/clock.c | 2 +-
>> arch/arm/mach-at91/pm.c | 2 +-
>> arch/arm/mach-at91/pm_slowclock.S | 2 +-
>> arch/arm/mach-at91/sama5d3.c | 2 +-
>> arch/arm/mach-at91/setup.c | 2 +-
>> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
>> .../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
>> 15 files changed, 15 insertions(+), 15 deletions(-)
>> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (99%)
>>
>> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
>> index 4aad93d..8de5b02 100644
>> --- a/arch/arm/mach-at91/at91rm9200.c
>> +++ b/arch/arm/mach-at91/at91rm9200.c
>> @@ -12,13 +12,13 @@
>>
>> #include <linux/module.h>
>> #include <linux/reboot.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91rm9200.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/at91_st.h>
>> #include <mach/cpu.h>
>>
>> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
>> index 5de6074..db9d89a 100644
>> --- a/arch/arm/mach-at91/at91sam9260.c
>> +++ b/arch/arm/mach-at91/at91sam9260.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -20,7 +21,6 @@
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> #include <mach/at91sam9260.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
>> index 0e07932..a4123bd 100644
>> --- a/arch/arm/mach-at91/at91sam9261.c
>> +++ b/arch/arm/mach-at91/at91sam9261.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -19,7 +20,6 @@
>> #include <asm/system_misc.h>
>> #include <mach/cpu.h>
>> #include <mach/at91sam9261.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
>> index 6ce7d18..e0a1a68 100644
>> --- a/arch/arm/mach-at91/at91sam9263.c
>> +++ b/arch/arm/mach-at91/at91sam9263.c
>> @@ -11,6 +11,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -18,7 +19,6 @@
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91sam9263.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
>> index 474ee04..29ba2ca 100644
>> --- a/arch/arm/mach-at91/at91sam9g45.c
>> +++ b/arch/arm/mach-at91/at91sam9g45.c
>> @@ -12,13 +12,13 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <asm/system_misc.h>
>> #include <mach/at91sam9g45.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "at91_aic.h"
>> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
>> index c7d670d..c270503 100644
>> --- a/arch/arm/mach-at91/at91sam9n12.c
>> +++ b/arch/arm/mach-at91/at91sam9n12.c
>> @@ -8,12 +8,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/at91sam9n12.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "board.h"
>> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
>> index d4ec0d9..2694bd1 100644
>> --- a/arch/arm/mach-at91/at91sam9rl.c
>> +++ b/arch/arm/mach-at91/at91sam9rl.c
>> @@ -10,6 +10,7 @@
>> */
>>
>> #include <linux/module.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/proc-fns.h>
>> #include <asm/irq.h>
>> @@ -19,7 +20,6 @@
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> #include <mach/at91sam9rl.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_aic.h"
>> #include "at91_rstc.h"
>> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
>> index 2abee66..9fdea07 100644
>> --- a/arch/arm/mach-at91/at91sam9x5.c
>> +++ b/arch/arm/mach-at91/at91sam9x5.c
>> @@ -8,12 +8,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/at91sam9x5.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "board.h"
>> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
>> index 6b2630a..cc263d0 100644
>> --- a/arch/arm/mach-at91/clock.c
>> +++ b/arch/arm/mach-at91/clock.c
>> @@ -24,9 +24,9 @@
>> #include <linux/clk.h>
>> #include <linux/io.h>
>> #include <linux/of_address.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <mach/hardware.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include <asm/proc-fns.h>
>> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
>> index 15afb5d..de425e0 100644
>> --- a/arch/arm/mach-at91/pm.c
>> +++ b/arch/arm/mach-at91/pm.c
>> @@ -19,13 +19,13 @@
>> #include <linux/module.h>
>> #include <linux/platform_device.h>
>> #include <linux/io.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <linux/atomic.h>
>> #include <asm/mach/time.h>
>> #include <asm/mach/irq.h>
>>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "at91_aic.h"
>> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
>> index 098c28d..76387e0 100644
>> --- a/arch/arm/mach-at91/pm_slowclock.S
>> +++ b/arch/arm/mach-at91/pm_slowclock.S
>> @@ -13,8 +13,8 @@
>> */
>>
>> #include <linux/linkage.h>
>> +#include <linux/clk/at91.h>
>> #include <mach/hardware.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/at91_ramc.h>
>>
>>
>> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
>> index 4012797..32e0522 100644
>> --- a/arch/arm/mach-at91/sama5d3.c
>> +++ b/arch/arm/mach-at91/sama5d3.c
>> @@ -9,12 +9,12 @@
>>
>> #include <linux/module.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/irq.h>
>> #include <asm/mach/arch.h>
>> #include <asm/mach/map.h>
>> #include <mach/sama5d3.h>
>> -#include <mach/at91_pmc.h>
>> #include <mach/cpu.h>
>>
>> #include "soc.h"
>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>> index b17fbcf..de3c519 100644
>> --- a/arch/arm/mach-at91/setup.c
>> +++ b/arch/arm/mach-at91/setup.c
>> @@ -11,6 +11,7 @@
>> #include <linux/pm.h>
>> #include <linux/of_address.h>
>> #include <linux/pinctrl/machine.h>
>> +#include <linux/clk/at91.h>
>>
>> #include <asm/system_misc.h>
>> #include <asm/mach/map.h>
>> @@ -18,7 +19,6 @@
>> #include <mach/hardware.h>
>> #include <mach/cpu.h>
>> #include <mach/at91_dbgu.h>
>> -#include <mach/at91_pmc.h>
>>
>> #include "at91_shdwc.h"
>> #include "soc.h"
>> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
>> index f018017..a678537 100644
>> --- a/drivers/usb/gadget/atmel_usba_udc.c
>> +++ b/drivers/usb/gadget/atmel_usba_udc.c
>> @@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
>>
>> #if defined(CONFIG_ARCH_AT91SAM9RL)
>>
>> -#include <mach/at91_pmc.h>
>> +#include <linux/clk/at91.h>
>>
>> static void toggle_bias(int is_on)
>> {
>> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
>> similarity index 99%
>> rename from arch/arm/mach-at91/include/mach/at91_pmc.h
>> rename to include/linux/clk/at91.h
>> index c604cc6..0ce9586 100644
>> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
>> +++ b/include/linux/clk/at91.h
>> @@ -1,5 +1,5 @@
>> /*
>> - * arch/arm/mach-at91/include/mach/at91_pmc.h
>> + * include/linux/clk/at91.h
>> *
>> * Copyright (C) 2005 Ivan Kokshaysky
>> * Copyright (C) SAN People
>> --
>> 1.7.9.5
>>
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 02/42] ARM: at91: add PMC main clock
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:40 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:40 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registraction it is computed using
the slow clock (main clk parent in this case) rate and the MCFR register.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 5 ++
drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 10 ++++
3 files changed, 121 insertions(+)
create mode 100644 drivers/clk/at91/Makefile
create mode 100644 drivers/clk/at91/clk-main.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 0000000..42c084e
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for at91 specific clk
+#
+
+obj-y += clk-main.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 0000000..738fa39
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,106 @@
+/*
+ * drivers/clk/at91/clk-main.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This mainram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
+struct clk_main {
+ struct clk_hw hw;
+ unsigned long rate;
+};
+
+static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_main *clkmain = to_clk_main(hw);
+ if (clkmain->rate)
+ return clkmain->rate;
+ while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
+ ;
+ tmp &= AT91_PMC_MAINF;
+ clkmain->rate = (tmp * parent_rate) / 16;
+ return clkmain->rate;
+}
+
+static const struct clk_ops main_ops = {
+ .recalc_rate = clk_main_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate)
+{
+ struct clk_main *clkmain;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ if (!rate && !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
+ if (!clkmain)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &main_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = parent_name ? 0 : CLK_IS_ROOT;
+
+ clkmain->hw.init = &init;
+ clkmain->rate = rate;
+
+ clk = clk_register(NULL, &clkmain->hw);
+
+ if (IS_ERR(clk))
+ kfree(clkmain);
+
+ return clk;
+}
+
+
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_main_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 rate = 0;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_string(np, "clock-output-names", &name);
+ of_property_read_u32(np, "clock-frequency", &rate);
+
+ clk = at91_clk_register_main(name, parent_name, rate);
+
+ if (!IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
+{
+ of_at91_clk_main_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
+ of_at91rm9200_clk_main_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 0ce9586..8e83942 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -16,6 +16,8 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
+#include <linux/clk-provider.h>
+
#ifndef __ASSEMBLY__
extern void __iomem *at91_pmc_base;
@@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+
+
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 02/42] ARM: at91: add PMC main clock
@ 2013-07-17 13:40 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:40 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registraction it is computed using
the slow clock (main clk parent in this case) rate and the MCFR register.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 5 ++
drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 10 ++++
3 files changed, 121 insertions(+)
create mode 100644 drivers/clk/at91/Makefile
create mode 100644 drivers/clk/at91/clk-main.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 0000000..42c084e
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for at91 specific clk
+#
+
+obj-y += clk-main.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 0000000..738fa39
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,106 @@
+/*
+ * drivers/clk/at91/clk-main.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This mainram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
+struct clk_main {
+ struct clk_hw hw;
+ unsigned long rate;
+};
+
+static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_main *clkmain = to_clk_main(hw);
+ if (clkmain->rate)
+ return clkmain->rate;
+ while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
+ ;
+ tmp &= AT91_PMC_MAINF;
+ clkmain->rate = (tmp * parent_rate) / 16;
+ return clkmain->rate;
+}
+
+static const struct clk_ops main_ops = {
+ .recalc_rate = clk_main_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate)
+{
+ struct clk_main *clkmain;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ if (!rate && !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
+ if (!clkmain)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &main_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = parent_name ? 0 : CLK_IS_ROOT;
+
+ clkmain->hw.init = &init;
+ clkmain->rate = rate;
+
+ clk = clk_register(NULL, &clkmain->hw);
+
+ if (IS_ERR(clk))
+ kfree(clkmain);
+
+ return clk;
+}
+
+
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_main_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 rate = 0;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_string(np, "clock-output-names", &name);
+ of_property_read_u32(np, "clock-frequency", &rate);
+
+ clk = at91_clk_register_main(name, parent_name, rate);
+
+ if (!IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
+{
+ of_at91_clk_main_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
+ of_at91rm9200_clk_main_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 0ce9586..8e83942 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -16,6 +16,8 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
+#include <linux/clk-provider.h>
+
#ifndef __ASSEMBLY__
extern void __iomem *at91_pmc_base;
@@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+
+
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* Re: [PATCH v2 02/42] ARM: at91: add PMC main clock
2013-07-17 13:40 ` Boris BREZILLON
@ 2013-07-17 16:39 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-17 16:39 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette,
linux-arm-kernel, linux-kernel
On 17/07/2013 15:40, Boris BREZILLON wrote:
> This is the at91 main oscillator clock implementation using common
> clk framework.
>
> If rate is not provided during clock registraction it is computed using
> the slow clock (main clk parent in this case) rate and the MCFR register.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/clk/at91/Makefile | 5 ++
> drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/clk/at91.h | 10 ++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
>
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> new file mode 100644
> index 0000000..42c084e
> --- /dev/null
> +++ b/drivers/clk/at91/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for at91 specific clk
> +#
> +
> +obj-y += clk-main.o
> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
> new file mode 100644
> index 0000000..738fa39
> --- /dev/null
> +++ b/drivers/clk/at91/clk-main.c
> @@ -0,0 +1,106 @@
> +/*
> + * drivers/clk/at91/clk-main.c
> + *
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
> + *
> + * This mainram is free software; you can redistribute it and/or modify
^program not mainram
This typo error is still present in pll, main and master clock
implementations.
I will fix it for the next version.
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/at91.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +
> +#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
> +struct clk_main {
> + struct clk_hw hw;
> + unsigned long rate;
> +};
> +
> +static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 tmp;
> + struct clk_main *clkmain = to_clk_main(hw);
> + if (clkmain->rate)
> + return clkmain->rate;
> + while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
> + ;
> + tmp &= AT91_PMC_MAINF;
> + clkmain->rate = (tmp * parent_rate) / 16;
> + return clkmain->rate;
> +}
> +
> +static const struct clk_ops main_ops = {
> + .recalc_rate = clk_main_recalc_rate,
> +};
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate)
> +{
> + struct clk_main *clkmain;
> + struct clk *clk = NULL;
> + struct clk_init_data init;
> +
> + if (!rate && !parent_name)
> + return ERR_PTR(-EINVAL);
> +
> + clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
> + if (!clkmain)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &main_ops;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.flags = parent_name ? 0 : CLK_IS_ROOT;
> +
> + clkmain->hw.init = &init;
> + clkmain->rate = rate;
> +
> + clk = clk_register(NULL, &clkmain->hw);
> +
> + if (IS_ERR(clk))
> + kfree(clkmain);
> +
> + return clk;
> +}
> +
> +
> +
> +#if defined(CONFIG_OF)
> +static void __init
> +of_at91_clk_main_setup(struct device_node *np)
> +{
> + struct clk *clk;
> + const char *parent_name;
> + const char *name = np->name;
> + u32 rate = 0;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + of_property_read_string(np, "clock-output-names", &name);
> + of_property_read_u32(np, "clock-frequency", &rate);
> +
> + clk = at91_clk_register_main(name, parent_name, rate);
> +
> + if (!IS_ERR(clk))
> + return;
> +
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> +static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
> +{
> + of_at91_clk_main_setup(np);
> +}
> +CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
> + of_at91rm9200_clk_main_setup);
> +#endif
> diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
> index 0ce9586..8e83942 100644
> --- a/include/linux/clk/at91.h
> +++ b/include/linux/clk/at91.h
> @@ -16,6 +16,8 @@
> #ifndef AT91_PMC_H
> #define AT91_PMC_H
>
> +#include <linux/clk-provider.h>
> +
> #ifndef __ASSEMBLY__
> extern void __iomem *at91_pmc_base;
>
> @@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
> #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
> #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
>
> +
> +
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate);
> +
> #endif
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 02/42] ARM: at91: add PMC main clock
@ 2013-07-17 16:39 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-17 16:39 UTC (permalink / raw)
To: linux-arm-kernel
On 17/07/2013 15:40, Boris BREZILLON wrote:
> This is the at91 main oscillator clock implementation using common
> clk framework.
>
> If rate is not provided during clock registraction it is computed using
> the slow clock (main clk parent in this case) rate and the MCFR register.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/clk/at91/Makefile | 5 ++
> drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/clk/at91.h | 10 ++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
>
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> new file mode 100644
> index 0000000..42c084e
> --- /dev/null
> +++ b/drivers/clk/at91/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for at91 specific clk
> +#
> +
> +obj-y += clk-main.o
> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
> new file mode 100644
> index 0000000..738fa39
> --- /dev/null
> +++ b/drivers/clk/at91/clk-main.c
> @@ -0,0 +1,106 @@
> +/*
> + * drivers/clk/at91/clk-main.c
> + *
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
> + *
> + * This mainram is free software; you can redistribute it and/or modify
^program not mainram
This typo error is still present in pll, main and master clock
implementations.
I will fix it for the next version.
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/at91.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +
> +#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
> +struct clk_main {
> + struct clk_hw hw;
> + unsigned long rate;
> +};
> +
> +static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 tmp;
> + struct clk_main *clkmain = to_clk_main(hw);
> + if (clkmain->rate)
> + return clkmain->rate;
> + while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
> + ;
> + tmp &= AT91_PMC_MAINF;
> + clkmain->rate = (tmp * parent_rate) / 16;
> + return clkmain->rate;
> +}
> +
> +static const struct clk_ops main_ops = {
> + .recalc_rate = clk_main_recalc_rate,
> +};
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate)
> +{
> + struct clk_main *clkmain;
> + struct clk *clk = NULL;
> + struct clk_init_data init;
> +
> + if (!rate && !parent_name)
> + return ERR_PTR(-EINVAL);
> +
> + clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
> + if (!clkmain)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &main_ops;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.flags = parent_name ? 0 : CLK_IS_ROOT;
> +
> + clkmain->hw.init = &init;
> + clkmain->rate = rate;
> +
> + clk = clk_register(NULL, &clkmain->hw);
> +
> + if (IS_ERR(clk))
> + kfree(clkmain);
> +
> + return clk;
> +}
> +
> +
> +
> +#if defined(CONFIG_OF)
> +static void __init
> +of_at91_clk_main_setup(struct device_node *np)
> +{
> + struct clk *clk;
> + const char *parent_name;
> + const char *name = np->name;
> + u32 rate = 0;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + of_property_read_string(np, "clock-output-names", &name);
> + of_property_read_u32(np, "clock-frequency", &rate);
> +
> + clk = at91_clk_register_main(name, parent_name, rate);
> +
> + if (!IS_ERR(clk))
> + return;
> +
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> +static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
> +{
> + of_at91_clk_main_setup(np);
> +}
> +CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
> + of_at91rm9200_clk_main_setup);
> +#endif
> diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
> index 0ce9586..8e83942 100644
> --- a/include/linux/clk/at91.h
> +++ b/include/linux/clk/at91.h
> @@ -16,6 +16,8 @@
> #ifndef AT91_PMC_H
> #define AT91_PMC_H
>
> +#include <linux/clk-provider.h>
> +
> #ifndef __ASSEMBLY__
> extern void __iomem *at91_pmc_base;
>
> @@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
> #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
> #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
>
> +
> +
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate);
> +
> #endif
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 02/42] ARM: at91: add PMC main clock
2013-07-17 13:40 ` Boris BREZILLON
@ 2013-07-26 16:41 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 16:41 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette,
linux-arm-kernel, linux-kernel
On 17/07/2013 15:40, Boris BREZILLON wrote:
> This is the at91 main oscillator clock implementation using common
> clk framework.
>
> If rate is not provided during clock registraction it is computed using
> the slow clock (main clk parent in this case) rate and the MCFR register.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/clk/at91/Makefile | 5 ++
> drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/clk/at91.h | 10 ++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
>
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> new file mode 100644
> index 0000000..42c084e
> --- /dev/null
> +++ b/drivers/clk/at91/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for at91 specific clk
> +#
> +
> +obj-y += clk-main.o
> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
> new file mode 100644
> index 0000000..738fa39
> --- /dev/null
> +++ b/drivers/clk/at91/clk-main.c
> @@ -0,0 +1,106 @@
> +/*
> + * drivers/clk/at91/clk-main.c
> + *
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
> + *
> + * This mainram is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/at91.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +
> +#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
> +struct clk_main {
> + struct clk_hw hw;
> + unsigned long rate;
> +};
> +
> +static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 tmp;
> + struct clk_main *clkmain = to_clk_main(hw);
> + if (clkmain->rate)
> + return clkmain->rate;
> + while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
> + ;
wrong test here, should be:
while (!((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY))
;
> + tmp &= AT91_PMC_MAINF;
> + clkmain->rate = (tmp * parent_rate) / 16;
> + return clkmain->rate;
> +}
> +
> +static const struct clk_ops main_ops = {
> + .recalc_rate = clk_main_recalc_rate,
> +};
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate)
> +{
> + struct clk_main *clkmain;
> + struct clk *clk = NULL;
> + struct clk_init_data init;
> +
> + if (!rate && !parent_name)
> + return ERR_PTR(-EINVAL);
> +
> + clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
> + if (!clkmain)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &main_ops;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.flags = parent_name ? 0 : CLK_IS_ROOT;
> +
> + clkmain->hw.init = &init;
> + clkmain->rate = rate;
> +
> + clk = clk_register(NULL, &clkmain->hw);
> +
> + if (IS_ERR(clk))
> + kfree(clkmain);
> +
> + return clk;
> +}
> +
> +
> +
> +#if defined(CONFIG_OF)
> +static void __init
> +of_at91_clk_main_setup(struct device_node *np)
> +{
> + struct clk *clk;
> + const char *parent_name;
> + const char *name = np->name;
> + u32 rate = 0;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + of_property_read_string(np, "clock-output-names", &name);
> + of_property_read_u32(np, "clock-frequency", &rate);
> +
> + clk = at91_clk_register_main(name, parent_name, rate);
> +
> + if (!IS_ERR(clk))
> + return;
> +
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> +static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
> +{
> + of_at91_clk_main_setup(np);
> +}
> +CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
> + of_at91rm9200_clk_main_setup);
> +#endif
> diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
> index 0ce9586..8e83942 100644
> --- a/include/linux/clk/at91.h
> +++ b/include/linux/clk/at91.h
> @@ -16,6 +16,8 @@
> #ifndef AT91_PMC_H
> #define AT91_PMC_H
>
> +#include <linux/clk-provider.h>
> +
> #ifndef __ASSEMBLY__
> extern void __iomem *at91_pmc_base;
>
> @@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
> #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
> #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
>
> +
> +
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate);
> +
> #endif
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 02/42] ARM: at91: add PMC main clock
@ 2013-07-26 16:41 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 16:41 UTC (permalink / raw)
To: linux-arm-kernel
On 17/07/2013 15:40, Boris BREZILLON wrote:
> This is the at91 main oscillator clock implementation using common
> clk framework.
>
> If rate is not provided during clock registraction it is computed using
> the slow clock (main clk parent in this case) rate and the MCFR register.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/clk/at91/Makefile | 5 ++
> drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/clk/at91.h | 10 ++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
>
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> new file mode 100644
> index 0000000..42c084e
> --- /dev/null
> +++ b/drivers/clk/at91/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for at91 specific clk
> +#
> +
> +obj-y += clk-main.o
> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
> new file mode 100644
> index 0000000..738fa39
> --- /dev/null
> +++ b/drivers/clk/at91/clk-main.c
> @@ -0,0 +1,106 @@
> +/*
> + * drivers/clk/at91/clk-main.c
> + *
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
> + *
> + * This mainram is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/at91.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
> +
> +#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
> +struct clk_main {
> + struct clk_hw hw;
> + unsigned long rate;
> +};
> +
> +static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 tmp;
> + struct clk_main *clkmain = to_clk_main(hw);
> + if (clkmain->rate)
> + return clkmain->rate;
> + while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
> + ;
wrong test here, should be:
while (!((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY))
;
> + tmp &= AT91_PMC_MAINF;
> + clkmain->rate = (tmp * parent_rate) / 16;
> + return clkmain->rate;
> +}
> +
> +static const struct clk_ops main_ops = {
> + .recalc_rate = clk_main_recalc_rate,
> +};
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate)
> +{
> + struct clk_main *clkmain;
> + struct clk *clk = NULL;
> + struct clk_init_data init;
> +
> + if (!rate && !parent_name)
> + return ERR_PTR(-EINVAL);
> +
> + clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
> + if (!clkmain)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &main_ops;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.flags = parent_name ? 0 : CLK_IS_ROOT;
> +
> + clkmain->hw.init = &init;
> + clkmain->rate = rate;
> +
> + clk = clk_register(NULL, &clkmain->hw);
> +
> + if (IS_ERR(clk))
> + kfree(clkmain);
> +
> + return clk;
> +}
> +
> +
> +
> +#if defined(CONFIG_OF)
> +static void __init
> +of_at91_clk_main_setup(struct device_node *np)
> +{
> + struct clk *clk;
> + const char *parent_name;
> + const char *name = np->name;
> + u32 rate = 0;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> + of_property_read_string(np, "clock-output-names", &name);
> + of_property_read_u32(np, "clock-frequency", &rate);
> +
> + clk = at91_clk_register_main(name, parent_name, rate);
> +
> + if (!IS_ERR(clk))
> + return;
> +
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> +
> +static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
> +{
> + of_at91_clk_main_setup(np);
> +}
> +CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
> + of_at91rm9200_clk_main_setup);
> +#endif
> diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
> index 0ce9586..8e83942 100644
> --- a/include/linux/clk/at91.h
> +++ b/include/linux/clk/at91.h
> @@ -16,6 +16,8 @@
> #ifndef AT91_PMC_H
> #define AT91_PMC_H
>
> +#include <linux/clk-provider.h>
> +
> #ifndef __ASSEMBLY__
> extern void __iomem *at91_pmc_base;
>
> @@ -187,4 +189,12 @@ extern void __iomem *at91_pmc_base;
> #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
> #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
>
> +
> +
> +
> +struct clk * __init
> +at91_clk_register_main(const char *name,
> + const char *parent_name,
> + unsigned long rate);
> +
> #endif
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 03/42] ARM: at91: add PMC pll clocks
2013-07-17 13:34 ` Boris BREZILLON
(?)
@ 2013-07-17 13:42 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:42 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Grant Likely,
Rob Herring
Cc: linux-arm-kernel, linux-kernel, devicetree-discuss, Boris BREZILLON
This is the at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-pll.c | 438 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/at91/clk-plldiv.c | 125 ++++++++++++
include/linux/clk/at91.h | 39 ++++
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-pll.c
create mode 100644 drivers/clk/at91/clk-plldiv.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 42c084e..564076f 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 0000000..e9390e2
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,438 @@
+/*
+ * drivers/clk/at91/clk-pll.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This pllram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
+
+struct clk_pll {
+ struct clk_hw hw;
+ u8 id;
+ u8 div;
+ u8 range;
+ u16 mul;
+ struct clk_pll_layout *layout;
+ struct clk_pll_characteristics *characteristics;
+};
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id))))
+ ;
+ return 0;
+}
+
+static int clk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ at91_pmc_write(offset, tmp);
+}
+
+static int clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & layout->pllr_mask;
+ u8 div = tmp & 0xFF;
+ u16 mul = (tmp >> layout->mul_shift) & layout->mul_mask;
+ if (!div || !mul)
+ return 0;
+
+ return (parent_rate * (mul + 1)) / div;
+}
+
+static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+ unsigned long parent_rate,
+ u32 *div, u32 *mul,
+ u32 *index) {
+ unsigned long maxrate;
+ unsigned long minrate;
+ unsigned long divrate;
+ unsigned long bestdiv = 1;
+ unsigned long bestmul;
+ unsigned long tmpdiv;
+ unsigned long roundup;
+ unsigned long rounddown;
+ unsigned long remainder;
+ unsigned long bestremainder;
+ unsigned long maxmul;
+ unsigned long maxdiv;
+ unsigned long mindiv;
+ int i = 0;
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+
+ /* Minimum divider = 1 */
+ /* Maximum multiplier = max_mul */
+ maxmul = layout->mul_mask + 1;
+ maxrate = (parent_rate * maxmul) / 1;
+
+ /* Maximum divider = max_div */
+ /* Minimum multiplier = 2 */
+ maxdiv = 0xFF;
+ minrate = (parent_rate * 2) / maxdiv;
+
+ if (parent_rate < characteristics->input.min ||
+ parent_rate < characteristics->input.max)
+ return -ERANGE;
+
+ if (parent_rate < minrate || parent_rate > maxrate)
+ return -ERANGE;
+
+ for (i = 0; i < characteristics->num_output; ++i) {
+ if (parent_rate >= characteristics->output[i].min &&
+ parent_rate <= characteristics->output[i].max)
+ break;
+ ++i;
+ }
+
+ if (i >= characteristics->num_output)
+ return -ERANGE;
+
+ bestmul = rate / parent_rate;
+ rounddown = parent_rate % rate;
+ roundup = rate - rounddown;
+ bestremainder = roundup < rounddown ? roundup : rounddown;
+
+ if (!bestremainder) {
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+ return rate;
+ }
+
+ maxdiv = 255 / (bestmul + 1);
+ if (parent_rate / maxdiv < characteristics->input.min)
+ maxdiv = parent_rate / characteristics->input.min;
+ mindiv = parent_rate / characteristics->input.max;
+ if (parent_rate % characteristics->input.max)
+ mindiv++;
+
+ for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
+ divrate = parent_rate / tmpdiv;
+
+ rounddown = rate % divrate;
+ roundup = divrate - rounddown;
+ remainder = roundup < rounddown ? roundup : rounddown;
+
+ if (remainder < bestremainder) {
+ bestremainder = remainder;
+ bestmul = rate / divrate;
+ bestdiv = tmpdiv;
+ }
+
+ if (!remainder)
+ break;
+ }
+
+ rate = (parent_rate / bestdiv) * bestmul;
+
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+
+ return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
+ NULL, NULL, NULL);
+
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ long ret;
+ u32 div;
+ u32 mul;
+ u32 index;
+ u32 tmp;
+ u8 out = 0;
+ ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
+ &div, &mul, &index);
+
+ if (ret < 0)
+ return ret;
+
+ if (characteristics->out)
+ out = characteristics->out[pll->range];
+ if (characteristics->icpll) {
+ tmp = at91_pmc_read(AT91_PMC_PLLICPR) &
+ ~(0xFFFF << (16 * pll->id));
+ tmp |= characteristics->icpll[pll->range] << (16 * pll->id);
+ at91_pmc_write(AT91_PMC_PLLICPR, tmp);
+ }
+ tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ tmp |= layout->pllr_mask & (div | 0x3F << 8 | out << 14 |
+ (mul & layout->mul_mask) <<
+ layout->mul_shift);
+ at91_pmc_write(offset, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_prepared,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_enabled,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics)
+{
+ struct clk_pll *pll;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 3;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &pll_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->id = id;
+ pll->hw.init = &init;
+ pll->layout = layout;
+ pll->characteristics = characteristics;
+
+ clk = clk_register(NULL, &pll->hw);
+
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+
+struct clk_pll_layout at91rm9200_pll_layout = {
+ .pllr_mask = 0x7FFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x7FF,
+};
+
+struct clk_pll_layout at91sam9g45_pll_layout = {
+ .pllr_mask = 0xFFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0xFF,
+};
+
+struct clk_pll_layout at91sam9g20_pllb_layout = {
+ .pllr_mask = 0x3FFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x3F,
+};
+
+struct clk_pll_layout sama5d3_pll_layout = {
+ .pllr_mask = 0x1FFFFFF,
+ .mul_shift = 18,
+ .mul_mask = 0x7F,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_pll_characteristics * __init
+of_at91_clk_pll_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ int num_output;
+ struct clk_range *output = NULL;
+ u8 *out = NULL;
+ u16 *icpll = NULL;
+ struct clk_pll_characteristics *characteristics = NULL;
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "input", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.min = tmp;
+
+ if (of_property_read_u32_index(np, "input", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.max = tmp;
+
+ if (!of_get_property(np, "output", &num_output))
+ goto out_free_characteristics;
+ num_output /= (sizeof(u32) * 2);
+
+ output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "output", i * 2, &tmp))
+ goto out_free_output;
+ output[i].min = tmp;
+ if (of_property_read_u32_index(np, "output", (i * 2) + 1, &tmp))
+ goto out_free_output;
+ output[i].max = tmp;
+ }
+
+ if (of_get_property(np, "out", NULL)) {
+ out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
+ if (!out)
+ goto out_free_output;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "out", i, &tmp))
+ goto out_free_out;
+ out[i] = tmp;
+ }
+ }
+
+ if (of_get_property(np, "icpll", NULL)) {
+ icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
+ if (!icpll)
+ goto out_free_out;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "icpll", i, &tmp))
+ goto out_free_icpll;
+ icpll[i] = tmp;
+ }
+ }
+
+ characteristics->num_output = num_output;
+ characteristics->output = output;
+ characteristics->out = out;
+ characteristics->icpll = icpll;
+ return characteristics;
+
+out_free_icpll:
+ kfree(icpll);
+out_free_out:
+ kfree(out);
+out_free_output:
+ kfree(output);
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_pll_setup(struct device_node *np,
+ struct clk_pll_layout *layout)
+{
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_property_read_u32(np, "id", &id))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_pll_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_pll(name, parent_name, id, layout,
+ characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
+ of_at91rm9200_clk_pll_setup);
+
+static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
+ of_at91sam9g45_clk_pll_setup);
+
+static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
+}
+CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
+ of_at91sam9g20_clk_pllb_setup);
+
+static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
+}
+CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
+ of_sama5d3_clk_pll_setup);
+#endif
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 0000000..430de9b
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,125 @@
+/*
+ * drivers/clk/at91/clk-plldiv.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This plldivram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
+
+struct clk_plldiv {
+ struct clk_hw hw;
+};
+
+static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
+ return parent_rate / 2;
+ return parent_rate;
+}
+
+static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ if (rate > *parent_rate)
+ return *parent_rate;
+ div = *parent_rate / 2;
+ if (rate < div)
+ return div;
+
+ if (rate - div < *parent_rate - rate)
+ return div;
+
+ return *parent_rate;
+}
+
+static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ if (parent_rate != rate && (parent_rate / 2) != rate)
+ return -EINVAL;
+
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
+ if ((parent_rate / 2) == rate)
+ tmp |= AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops plldiv_ops = {
+ .recalc_rate = clk_plldiv_recalc_rate,
+ .round_rate = clk_plldiv_round_rate,
+ .set_rate = clk_plldiv_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name)
+{
+ struct clk_plldiv *plldiv;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
+ if (!plldiv)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &plldiv_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ plldiv->hw.init = &init;
+
+ clk = clk_register(NULL, &plldiv->hw);
+
+ if (IS_ERR(clk))
+ kfree(plldiv);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_plldiv_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_plldiv(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
+{
+ of_at91_clk_plldiv_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
+ of_at91sam9x5_clk_plldiv_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 8e83942..51b7134 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -166,6 +166,8 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
@@ -190,6 +192,26 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+struct clk_range {
+ unsigned long min;
+ unsigned long max;
+};
+
+#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
+
+struct clk_pll_characteristics {
+ struct clk_range input;
+ int num_output;
+ struct clk_range *output;
+ u16 *icpll;
+ u8 *out;
+};
+
+struct clk_pll_layout {
+ u32 pllr_mask;
+ u16 mul_mask;
+ u8 mul_shift;
+};
struct clk * __init
@@ -197,4 +219,21 @@ at91_clk_register_main(const char *name,
const char *parent_name,
unsigned long rate);
+
+extern struct clk_pll_layout at91rm9200_pll_layout;
+
+extern struct clk_pll_layout at91sam9g45_pll_layout;
+
+extern struct clk_pll_layout at91sam9g20_pllb_layout;
+
+extern struct clk_pll_layout sama5d3_pll_layout;
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics);
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 03/42] ARM: at91: add PMC pll clocks
@ 2013-07-17 13:42 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:42 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-pll.c | 438 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/at91/clk-plldiv.c | 125 ++++++++++++
include/linux/clk/at91.h | 39 ++++
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-pll.c
create mode 100644 drivers/clk/at91/clk-plldiv.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 42c084e..564076f 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 0000000..e9390e2
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,438 @@
+/*
+ * drivers/clk/at91/clk-pll.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This pllram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
+
+struct clk_pll {
+ struct clk_hw hw;
+ u8 id;
+ u8 div;
+ u8 range;
+ u16 mul;
+ struct clk_pll_layout *layout;
+ struct clk_pll_characteristics *characteristics;
+};
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id))))
+ ;
+ return 0;
+}
+
+static int clk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ at91_pmc_write(offset, tmp);
+}
+
+static int clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & layout->pllr_mask;
+ u8 div = tmp & 0xFF;
+ u16 mul = (tmp >> layout->mul_shift) & layout->mul_mask;
+ if (!div || !mul)
+ return 0;
+
+ return (parent_rate * (mul + 1)) / div;
+}
+
+static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+ unsigned long parent_rate,
+ u32 *div, u32 *mul,
+ u32 *index) {
+ unsigned long maxrate;
+ unsigned long minrate;
+ unsigned long divrate;
+ unsigned long bestdiv = 1;
+ unsigned long bestmul;
+ unsigned long tmpdiv;
+ unsigned long roundup;
+ unsigned long rounddown;
+ unsigned long remainder;
+ unsigned long bestremainder;
+ unsigned long maxmul;
+ unsigned long maxdiv;
+ unsigned long mindiv;
+ int i = 0;
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+
+ /* Minimum divider = 1 */
+ /* Maximum multiplier = max_mul */
+ maxmul = layout->mul_mask + 1;
+ maxrate = (parent_rate * maxmul) / 1;
+
+ /* Maximum divider = max_div */
+ /* Minimum multiplier = 2 */
+ maxdiv = 0xFF;
+ minrate = (parent_rate * 2) / maxdiv;
+
+ if (parent_rate < characteristics->input.min ||
+ parent_rate < characteristics->input.max)
+ return -ERANGE;
+
+ if (parent_rate < minrate || parent_rate > maxrate)
+ return -ERANGE;
+
+ for (i = 0; i < characteristics->num_output; ++i) {
+ if (parent_rate >= characteristics->output[i].min &&
+ parent_rate <= characteristics->output[i].max)
+ break;
+ ++i;
+ }
+
+ if (i >= characteristics->num_output)
+ return -ERANGE;
+
+ bestmul = rate / parent_rate;
+ rounddown = parent_rate % rate;
+ roundup = rate - rounddown;
+ bestremainder = roundup < rounddown ? roundup : rounddown;
+
+ if (!bestremainder) {
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+ return rate;
+ }
+
+ maxdiv = 255 / (bestmul + 1);
+ if (parent_rate / maxdiv < characteristics->input.min)
+ maxdiv = parent_rate / characteristics->input.min;
+ mindiv = parent_rate / characteristics->input.max;
+ if (parent_rate % characteristics->input.max)
+ mindiv++;
+
+ for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
+ divrate = parent_rate / tmpdiv;
+
+ rounddown = rate % divrate;
+ roundup = divrate - rounddown;
+ remainder = roundup < rounddown ? roundup : rounddown;
+
+ if (remainder < bestremainder) {
+ bestremainder = remainder;
+ bestmul = rate / divrate;
+ bestdiv = tmpdiv;
+ }
+
+ if (!remainder)
+ break;
+ }
+
+ rate = (parent_rate / bestdiv) * bestmul;
+
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+
+ return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
+ NULL, NULL, NULL);
+
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ long ret;
+ u32 div;
+ u32 mul;
+ u32 index;
+ u32 tmp;
+ u8 out = 0;
+ ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
+ &div, &mul, &index);
+
+ if (ret < 0)
+ return ret;
+
+ if (characteristics->out)
+ out = characteristics->out[pll->range];
+ if (characteristics->icpll) {
+ tmp = at91_pmc_read(AT91_PMC_PLLICPR) &
+ ~(0xFFFF << (16 * pll->id));
+ tmp |= characteristics->icpll[pll->range] << (16 * pll->id);
+ at91_pmc_write(AT91_PMC_PLLICPR, tmp);
+ }
+ tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ tmp |= layout->pllr_mask & (div | 0x3F << 8 | out << 14 |
+ (mul & layout->mul_mask) <<
+ layout->mul_shift);
+ at91_pmc_write(offset, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_prepared,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_enabled,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics)
+{
+ struct clk_pll *pll;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 3;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &pll_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->id = id;
+ pll->hw.init = &init;
+ pll->layout = layout;
+ pll->characteristics = characteristics;
+
+ clk = clk_register(NULL, &pll->hw);
+
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+
+struct clk_pll_layout at91rm9200_pll_layout = {
+ .pllr_mask = 0x7FFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x7FF,
+};
+
+struct clk_pll_layout at91sam9g45_pll_layout = {
+ .pllr_mask = 0xFFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0xFF,
+};
+
+struct clk_pll_layout at91sam9g20_pllb_layout = {
+ .pllr_mask = 0x3FFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x3F,
+};
+
+struct clk_pll_layout sama5d3_pll_layout = {
+ .pllr_mask = 0x1FFFFFF,
+ .mul_shift = 18,
+ .mul_mask = 0x7F,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_pll_characteristics * __init
+of_at91_clk_pll_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ int num_output;
+ struct clk_range *output = NULL;
+ u8 *out = NULL;
+ u16 *icpll = NULL;
+ struct clk_pll_characteristics *characteristics = NULL;
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "input", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.min = tmp;
+
+ if (of_property_read_u32_index(np, "input", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.max = tmp;
+
+ if (!of_get_property(np, "output", &num_output))
+ goto out_free_characteristics;
+ num_output /= (sizeof(u32) * 2);
+
+ output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "output", i * 2, &tmp))
+ goto out_free_output;
+ output[i].min = tmp;
+ if (of_property_read_u32_index(np, "output", (i * 2) + 1, &tmp))
+ goto out_free_output;
+ output[i].max = tmp;
+ }
+
+ if (of_get_property(np, "out", NULL)) {
+ out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
+ if (!out)
+ goto out_free_output;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "out", i, &tmp))
+ goto out_free_out;
+ out[i] = tmp;
+ }
+ }
+
+ if (of_get_property(np, "icpll", NULL)) {
+ icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
+ if (!icpll)
+ goto out_free_out;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "icpll", i, &tmp))
+ goto out_free_icpll;
+ icpll[i] = tmp;
+ }
+ }
+
+ characteristics->num_output = num_output;
+ characteristics->output = output;
+ characteristics->out = out;
+ characteristics->icpll = icpll;
+ return characteristics;
+
+out_free_icpll:
+ kfree(icpll);
+out_free_out:
+ kfree(out);
+out_free_output:
+ kfree(output);
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_pll_setup(struct device_node *np,
+ struct clk_pll_layout *layout)
+{
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_property_read_u32(np, "id", &id))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_pll_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_pll(name, parent_name, id, layout,
+ characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
+ of_at91rm9200_clk_pll_setup);
+
+static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
+ of_at91sam9g45_clk_pll_setup);
+
+static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
+}
+CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
+ of_at91sam9g20_clk_pllb_setup);
+
+static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
+}
+CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
+ of_sama5d3_clk_pll_setup);
+#endif
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 0000000..430de9b
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,125 @@
+/*
+ * drivers/clk/at91/clk-plldiv.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This plldivram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
+
+struct clk_plldiv {
+ struct clk_hw hw;
+};
+
+static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
+ return parent_rate / 2;
+ return parent_rate;
+}
+
+static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ if (rate > *parent_rate)
+ return *parent_rate;
+ div = *parent_rate / 2;
+ if (rate < div)
+ return div;
+
+ if (rate - div < *parent_rate - rate)
+ return div;
+
+ return *parent_rate;
+}
+
+static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ if (parent_rate != rate && (parent_rate / 2) != rate)
+ return -EINVAL;
+
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
+ if ((parent_rate / 2) == rate)
+ tmp |= AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops plldiv_ops = {
+ .recalc_rate = clk_plldiv_recalc_rate,
+ .round_rate = clk_plldiv_round_rate,
+ .set_rate = clk_plldiv_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name)
+{
+ struct clk_plldiv *plldiv;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
+ if (!plldiv)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &plldiv_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ plldiv->hw.init = &init;
+
+ clk = clk_register(NULL, &plldiv->hw);
+
+ if (IS_ERR(clk))
+ kfree(plldiv);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_plldiv_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_plldiv(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
+{
+ of_at91_clk_plldiv_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
+ of_at91sam9x5_clk_plldiv_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 8e83942..51b7134 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -166,6 +166,8 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
@@ -190,6 +192,26 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+struct clk_range {
+ unsigned long min;
+ unsigned long max;
+};
+
+#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
+
+struct clk_pll_characteristics {
+ struct clk_range input;
+ int num_output;
+ struct clk_range *output;
+ u16 *icpll;
+ u8 *out;
+};
+
+struct clk_pll_layout {
+ u32 pllr_mask;
+ u16 mul_mask;
+ u8 mul_shift;
+};
struct clk * __init
@@ -197,4 +219,21 @@ at91_clk_register_main(const char *name,
const char *parent_name,
unsigned long rate);
+
+extern struct clk_pll_layout at91rm9200_pll_layout;
+
+extern struct clk_pll_layout at91sam9g45_pll_layout;
+
+extern struct clk_pll_layout at91sam9g20_pllb_layout;
+
+extern struct clk_pll_layout sama5d3_pll_layout;
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics);
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 03/42] ARM: at91: add PMC pll clocks
@ 2013-07-17 13:42 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:42 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Grant Likely,
Rob Herring
Cc: devicetree-discuss, linux-kernel, linux-arm-kernel, Boris BREZILLON
This is the at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-pll.c | 438 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/at91/clk-plldiv.c | 125 ++++++++++++
include/linux/clk/at91.h | 39 ++++
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-pll.c
create mode 100644 drivers/clk/at91/clk-plldiv.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 42c084e..564076f 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 0000000..e9390e2
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,438 @@
+/*
+ * drivers/clk/at91/clk-pll.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This pllram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
+
+struct clk_pll {
+ struct clk_hw hw;
+ u8 id;
+ u8 div;
+ u8 range;
+ u16 mul;
+ struct clk_pll_layout *layout;
+ struct clk_pll_characteristics *characteristics;
+};
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id))))
+ ;
+ return 0;
+}
+
+static int clk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ at91_pmc_write(offset, tmp);
+}
+
+static int clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (1 + pll->id)));
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & layout->pllr_mask;
+ u8 div = tmp & 0xFF;
+ u16 mul = (tmp >> layout->mul_shift) & layout->mul_mask;
+ if (!div || !mul)
+ return 0;
+
+ return (parent_rate * (mul + 1)) / div;
+}
+
+static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+ unsigned long parent_rate,
+ u32 *div, u32 *mul,
+ u32 *index) {
+ unsigned long maxrate;
+ unsigned long minrate;
+ unsigned long divrate;
+ unsigned long bestdiv = 1;
+ unsigned long bestmul;
+ unsigned long tmpdiv;
+ unsigned long roundup;
+ unsigned long rounddown;
+ unsigned long remainder;
+ unsigned long bestremainder;
+ unsigned long maxmul;
+ unsigned long maxdiv;
+ unsigned long mindiv;
+ int i = 0;
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+
+ /* Minimum divider = 1 */
+ /* Maximum multiplier = max_mul */
+ maxmul = layout->mul_mask + 1;
+ maxrate = (parent_rate * maxmul) / 1;
+
+ /* Maximum divider = max_div */
+ /* Minimum multiplier = 2 */
+ maxdiv = 0xFF;
+ minrate = (parent_rate * 2) / maxdiv;
+
+ if (parent_rate < characteristics->input.min ||
+ parent_rate < characteristics->input.max)
+ return -ERANGE;
+
+ if (parent_rate < minrate || parent_rate > maxrate)
+ return -ERANGE;
+
+ for (i = 0; i < characteristics->num_output; ++i) {
+ if (parent_rate >= characteristics->output[i].min &&
+ parent_rate <= characteristics->output[i].max)
+ break;
+ ++i;
+ }
+
+ if (i >= characteristics->num_output)
+ return -ERANGE;
+
+ bestmul = rate / parent_rate;
+ rounddown = parent_rate % rate;
+ roundup = rate - rounddown;
+ bestremainder = roundup < rounddown ? roundup : rounddown;
+
+ if (!bestremainder) {
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+ return rate;
+ }
+
+ maxdiv = 255 / (bestmul + 1);
+ if (parent_rate / maxdiv < characteristics->input.min)
+ maxdiv = parent_rate / characteristics->input.min;
+ mindiv = parent_rate / characteristics->input.max;
+ if (parent_rate % characteristics->input.max)
+ mindiv++;
+
+ for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
+ divrate = parent_rate / tmpdiv;
+
+ rounddown = rate % divrate;
+ roundup = divrate - rounddown;
+ remainder = roundup < rounddown ? roundup : rounddown;
+
+ if (remainder < bestremainder) {
+ bestremainder = remainder;
+ bestmul = rate / divrate;
+ bestdiv = tmpdiv;
+ }
+
+ if (!remainder)
+ break;
+ }
+
+ rate = (parent_rate / bestdiv) * bestmul;
+
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+
+ return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
+ NULL, NULL, NULL);
+
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ long ret;
+ u32 div;
+ u32 mul;
+ u32 index;
+ u32 tmp;
+ u8 out = 0;
+ ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
+ &div, &mul, &index);
+
+ if (ret < 0)
+ return ret;
+
+ if (characteristics->out)
+ out = characteristics->out[pll->range];
+ if (characteristics->icpll) {
+ tmp = at91_pmc_read(AT91_PMC_PLLICPR) &
+ ~(0xFFFF << (16 * pll->id));
+ tmp |= characteristics->icpll[pll->range] << (16 * pll->id);
+ at91_pmc_write(AT91_PMC_PLLICPR, tmp);
+ }
+ tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ tmp |= layout->pllr_mask & (div | 0x3F << 8 | out << 14 |
+ (mul & layout->mul_mask) <<
+ layout->mul_shift);
+ at91_pmc_write(offset, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_prepared,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_enabled,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics)
+{
+ struct clk_pll *pll;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 3;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &pll_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->id = id;
+ pll->hw.init = &init;
+ pll->layout = layout;
+ pll->characteristics = characteristics;
+
+ clk = clk_register(NULL, &pll->hw);
+
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+
+struct clk_pll_layout at91rm9200_pll_layout = {
+ .pllr_mask = 0x7FFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x7FF,
+};
+
+struct clk_pll_layout at91sam9g45_pll_layout = {
+ .pllr_mask = 0xFFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0xFF,
+};
+
+struct clk_pll_layout at91sam9g20_pllb_layout = {
+ .pllr_mask = 0x3FFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x3F,
+};
+
+struct clk_pll_layout sama5d3_pll_layout = {
+ .pllr_mask = 0x1FFFFFF,
+ .mul_shift = 18,
+ .mul_mask = 0x7F,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_pll_characteristics * __init
+of_at91_clk_pll_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ int num_output;
+ struct clk_range *output = NULL;
+ u8 *out = NULL;
+ u16 *icpll = NULL;
+ struct clk_pll_characteristics *characteristics = NULL;
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "input", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.min = tmp;
+
+ if (of_property_read_u32_index(np, "input", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.max = tmp;
+
+ if (!of_get_property(np, "output", &num_output))
+ goto out_free_characteristics;
+ num_output /= (sizeof(u32) * 2);
+
+ output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "output", i * 2, &tmp))
+ goto out_free_output;
+ output[i].min = tmp;
+ if (of_property_read_u32_index(np, "output", (i * 2) + 1, &tmp))
+ goto out_free_output;
+ output[i].max = tmp;
+ }
+
+ if (of_get_property(np, "out", NULL)) {
+ out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
+ if (!out)
+ goto out_free_output;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "out", i, &tmp))
+ goto out_free_out;
+ out[i] = tmp;
+ }
+ }
+
+ if (of_get_property(np, "icpll", NULL)) {
+ icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
+ if (!icpll)
+ goto out_free_out;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "icpll", i, &tmp))
+ goto out_free_icpll;
+ icpll[i] = tmp;
+ }
+ }
+
+ characteristics->num_output = num_output;
+ characteristics->output = output;
+ characteristics->out = out;
+ characteristics->icpll = icpll;
+ return characteristics;
+
+out_free_icpll:
+ kfree(icpll);
+out_free_out:
+ kfree(out);
+out_free_output:
+ kfree(output);
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_pll_setup(struct device_node *np,
+ struct clk_pll_layout *layout)
+{
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_property_read_u32(np, "id", &id))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_pll_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_pll(name, parent_name, id, layout,
+ characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
+ of_at91rm9200_clk_pll_setup);
+
+static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
+ of_at91sam9g45_clk_pll_setup);
+
+static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
+}
+CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
+ of_at91sam9g20_clk_pllb_setup);
+
+static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
+}
+CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
+ of_sama5d3_clk_pll_setup);
+#endif
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 0000000..430de9b
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,125 @@
+/*
+ * drivers/clk/at91/clk-plldiv.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This plldivram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
+
+struct clk_plldiv {
+ struct clk_hw hw;
+};
+
+static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
+ return parent_rate / 2;
+ return parent_rate;
+}
+
+static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ if (rate > *parent_rate)
+ return *parent_rate;
+ div = *parent_rate / 2;
+ if (rate < div)
+ return div;
+
+ if (rate - div < *parent_rate - rate)
+ return div;
+
+ return *parent_rate;
+}
+
+static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ if (parent_rate != rate && (parent_rate / 2) != rate)
+ return -EINVAL;
+
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
+ if ((parent_rate / 2) == rate)
+ tmp |= AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops plldiv_ops = {
+ .recalc_rate = clk_plldiv_recalc_rate,
+ .round_rate = clk_plldiv_round_rate,
+ .set_rate = clk_plldiv_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name)
+{
+ struct clk_plldiv *plldiv;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
+ if (!plldiv)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &plldiv_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ plldiv->hw.init = &init;
+
+ clk = clk_register(NULL, &plldiv->hw);
+
+ if (IS_ERR(clk))
+ kfree(plldiv);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_plldiv_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_plldiv(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
+{
+ of_at91_clk_plldiv_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
+ of_at91sam9x5_clk_plldiv_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 8e83942..51b7134 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -166,6 +166,8 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
@@ -190,6 +192,26 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+struct clk_range {
+ unsigned long min;
+ unsigned long max;
+};
+
+#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
+
+struct clk_pll_characteristics {
+ struct clk_range input;
+ int num_output;
+ struct clk_range *output;
+ u16 *icpll;
+ u8 *out;
+};
+
+struct clk_pll_layout {
+ u32 pllr_mask;
+ u16 mul_mask;
+ u8 mul_shift;
+};
struct clk * __init
@@ -197,4 +219,21 @@ at91_clk_register_main(const char *name,
const char *parent_name,
unsigned long rate);
+
+extern struct clk_pll_layout at91rm9200_pll_layout;
+
+extern struct clk_pll_layout at91sam9g45_pll_layout;
+
+extern struct clk_pll_layout at91sam9g20_pllb_layout;
+
+extern struct clk_pll_layout sama5d3_pll_layout;
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics);
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 04/42] ARM: at91: add PMC master clock
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:44 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:44 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 master clock implementation using common clk framework.
The pll clock layout describe the MCKR register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9x5
Master clocks are given characteristics:
- min/max clock output rate
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-master.c | 317 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 23 +++
3 files changed, 341 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-master.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 564076f..d41f616 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o clk-pll.o clk-plldiv.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 0000000..71ade7d
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,317 @@
+/*
+ * drivers/clk/at91/clk-master.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This masterram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define MASTER_SOURCE_MAX 4
+
+#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
+
+struct clk_master {
+ struct clk_hw hw;
+ struct clk_master_layout *layout;
+ struct clk_master_characteristics *characteristics;
+};
+
+static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u8 pres;
+ u8 div;
+ unsigned long rate = parent_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ u32 tmp = at91_pmc_read(AT91_PMC_MCKR) & layout->mask;
+
+ pres = (tmp >> layout->pres_shift) & 0x7;
+ div = (tmp >> 8) & 0x3;
+
+ if (characteristics->have_div3_pres && pres == 7)
+ rate /= 3;
+ else
+ rate >>= pres;
+
+ rate /= characteristics->divisors[div];
+
+ /* print overclocking or underclocking error */
+ /*
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max) {
+ }
+ */
+ return rate;
+}
+
+static long clk_master_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ long best_rate = -EINVAL;
+ unsigned long best_diff = 0;
+ unsigned long cur_diff;
+ unsigned long pres_rate;
+ unsigned long cur_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max)
+ return -EINVAL;
+
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = *parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = *parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (rate < cur_rate)
+ cur_diff = cur_rate - rate;
+ else
+ cur_diff = rate - cur_rate;
+
+ if (best_rate < 0 || cur_diff < best_diff) {
+ best_rate = cur_rate;
+ best_diff = cur_diff;
+ if (!best_diff)
+ return best_rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+static int clk_master_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > AT91_PMC_CSS)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_CSS;
+ tmp |= index;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+ return 0;
+}
+
+static u8 clk_master_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_CSS;
+}
+
+static int clk_master_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ u32 tmp;
+ unsigned long cur_rate;
+ unsigned long pres_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (cur_rate == rate) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= layout->mask;
+ tmp &= ~AT91_PMC_CSS;
+ tmp |= pres << layout->pres_shift | mdiv << 8;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ AT91_PMC_MCKRDY))
+ ;
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops master_ops = {
+ .recalc_rate = clk_master_recalc_rate,
+ .round_rate = clk_master_round_rate,
+ .get_parent = clk_master_get_parent,
+ .set_parent = clk_master_set_parent,
+ .set_rate = clk_master_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_master(const char *name,
+ int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics)
+{
+ struct clk_master *master;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ master = kzalloc(sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &master_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ master->hw.init = &init;
+ master->layout = layout;
+ master->characteristics = characteristics;
+
+ clk = clk_register(NULL, &master->hw);
+
+ if (IS_ERR(clk))
+ kfree(master);
+
+ return clk;
+}
+
+
+struct clk_master_layout at91rm9200_master_layout = {
+ .mask = 0x31F,
+ .pres_shift = 2,
+};
+
+struct clk_master_layout at91sam9x5_master_layout = {
+ .mask = 0x373,
+ .pres_shift = 4,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_master_characteristics * __init
+of_at91_clk_master_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ struct clk_master_characteristics *characteristics = NULL;
+
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "output", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.min = tmp;
+
+ if (of_property_read_u32_index(np, "output", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.max = tmp;
+
+ for (i = 0; i < 4; i++) {
+ tmp = 0;
+ of_property_read_u32_index(np, "divisors", i, &tmp);
+ characteristics->divisors[i] = tmp;
+ }
+
+ characteristics->have_div3_pres =
+ of_property_read_bool(np, "have-div3-pres");
+
+ return characteristics;
+
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_master_setup(struct device_node *np,
+ struct clk_master_layout *layout)
+{
+ struct clk *clk;
+ int num_parents;
+ int i;
+ const char *parent_names[MASTER_SOURCE_MAX];
+ const char *name = np->name;
+ struct clk_master_characteristics *characteristics;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_master_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_master(name, num_parents, parent_names,
+ layout, characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91rm9200_master_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
+ of_at91rm9200_clk_master_setup);
+
+static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
+ of_at91sam9x5_clk_master_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 51b7134..324134c 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -213,6 +213,17 @@ struct clk_pll_layout {
u8 mul_shift;
};
+struct clk_master_characteristics {
+ struct clk_range output;
+ u32 divisors[4];
+ u8 have_div3_pres;
+};
+
+struct clk_master_layout {
+ u32 mask;
+ u8 pres_shift;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -236,4 +247,16 @@ at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
struct clk * __init
at91_clk_register_plldiv(const char *name, const char *parent_name);
+
+extern struct clk_master_layout at91rm9200_master_layout;
+
+extern struct clk_master_layout at91sam9x5_master_layout;
+
+struct clk * __init
+at91_clk_register_master(const char *name, int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics);
+
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 04/42] ARM: at91: add PMC master clock
@ 2013-07-17 13:44 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:44 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 master clock implementation using common clk framework.
The pll clock layout describe the MCKR register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9x5
Master clocks are given characteristics:
- min/max clock output rate
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-master.c | 317 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 23 +++
3 files changed, 341 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-master.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 564076f..d41f616 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o clk-pll.o clk-plldiv.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 0000000..71ade7d
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,317 @@
+/*
+ * drivers/clk/at91/clk-master.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This masterram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define MASTER_SOURCE_MAX 4
+
+#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
+
+struct clk_master {
+ struct clk_hw hw;
+ struct clk_master_layout *layout;
+ struct clk_master_characteristics *characteristics;
+};
+
+static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u8 pres;
+ u8 div;
+ unsigned long rate = parent_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ u32 tmp = at91_pmc_read(AT91_PMC_MCKR) & layout->mask;
+
+ pres = (tmp >> layout->pres_shift) & 0x7;
+ div = (tmp >> 8) & 0x3;
+
+ if (characteristics->have_div3_pres && pres == 7)
+ rate /= 3;
+ else
+ rate >>= pres;
+
+ rate /= characteristics->divisors[div];
+
+ /* print overclocking or underclocking error */
+ /*
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max) {
+ }
+ */
+ return rate;
+}
+
+static long clk_master_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ long best_rate = -EINVAL;
+ unsigned long best_diff = 0;
+ unsigned long cur_diff;
+ unsigned long pres_rate;
+ unsigned long cur_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max)
+ return -EINVAL;
+
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = *parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = *parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (rate < cur_rate)
+ cur_diff = cur_rate - rate;
+ else
+ cur_diff = rate - cur_rate;
+
+ if (best_rate < 0 || cur_diff < best_diff) {
+ best_rate = cur_rate;
+ best_diff = cur_diff;
+ if (!best_diff)
+ return best_rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+static int clk_master_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > AT91_PMC_CSS)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_CSS;
+ tmp |= index;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+ return 0;
+}
+
+static u8 clk_master_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_CSS;
+}
+
+static int clk_master_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ u32 tmp;
+ unsigned long cur_rate;
+ unsigned long pres_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (cur_rate == rate) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= layout->mask;
+ tmp &= ~AT91_PMC_CSS;
+ tmp |= pres << layout->pres_shift | mdiv << 8;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ AT91_PMC_MCKRDY))
+ ;
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops master_ops = {
+ .recalc_rate = clk_master_recalc_rate,
+ .round_rate = clk_master_round_rate,
+ .get_parent = clk_master_get_parent,
+ .set_parent = clk_master_set_parent,
+ .set_rate = clk_master_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_master(const char *name,
+ int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics)
+{
+ struct clk_master *master;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ master = kzalloc(sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &master_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ master->hw.init = &init;
+ master->layout = layout;
+ master->characteristics = characteristics;
+
+ clk = clk_register(NULL, &master->hw);
+
+ if (IS_ERR(clk))
+ kfree(master);
+
+ return clk;
+}
+
+
+struct clk_master_layout at91rm9200_master_layout = {
+ .mask = 0x31F,
+ .pres_shift = 2,
+};
+
+struct clk_master_layout at91sam9x5_master_layout = {
+ .mask = 0x373,
+ .pres_shift = 4,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_master_characteristics * __init
+of_at91_clk_master_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ struct clk_master_characteristics *characteristics = NULL;
+
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "output", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.min = tmp;
+
+ if (of_property_read_u32_index(np, "output", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.max = tmp;
+
+ for (i = 0; i < 4; i++) {
+ tmp = 0;
+ of_property_read_u32_index(np, "divisors", i, &tmp);
+ characteristics->divisors[i] = tmp;
+ }
+
+ characteristics->have_div3_pres =
+ of_property_read_bool(np, "have-div3-pres");
+
+ return characteristics;
+
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_master_setup(struct device_node *np,
+ struct clk_master_layout *layout)
+{
+ struct clk *clk;
+ int num_parents;
+ int i;
+ const char *parent_names[MASTER_SOURCE_MAX];
+ const char *name = np->name;
+ struct clk_master_characteristics *characteristics;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_master_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_master(name, num_parents, parent_names,
+ layout, characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91rm9200_master_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
+ of_at91rm9200_clk_master_setup);
+
+static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
+ of_at91sam9x5_clk_master_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 51b7134..324134c 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -213,6 +213,17 @@ struct clk_pll_layout {
u8 mul_shift;
};
+struct clk_master_characteristics {
+ struct clk_range output;
+ u32 divisors[4];
+ u8 have_div3_pres;
+};
+
+struct clk_master_layout {
+ u32 mask;
+ u8 pres_shift;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -236,4 +247,16 @@ at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
struct clk * __init
at91_clk_register_plldiv(const char *name, const char *parent_name);
+
+extern struct clk_master_layout at91rm9200_master_layout;
+
+extern struct clk_master_layout at91sam9x5_master_layout;
+
+struct clk * __init
+at91_clk_register_master(const char *name, int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics);
+
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 05/42] ARM: at91: add PMC system clocks
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:45 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:45 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 system clock implementation using common clk framework.
Some peripheral needs to enable a "system" clock in order to work properly.
Each system clock is given an id which is the bit offset used in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-system.c | 184 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 3 +
3 files changed, 188 insertions(+)
create mode 100644 drivers/clk/at91/clk-system.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index d41f616..13e5714 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,3 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
+obj-y += clk-system.o
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 0000000..17e092a
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,184 @@
+/*
+ * drivers/clk/at91/clk-system.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SYSTEM_MAX 32
+
+#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
+struct clk_system {
+ struct clk_hw hw;
+ u8 id;
+};
+
+static int clk_system_enable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCER, 1 << sys->id);
+ return 0;
+}
+
+static void clk_system_disable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCDR, 1 << sys->id);
+}
+
+static int clk_system_is_enabled(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ return !!(at91_pmc_read(AT91_PMC_SCSR) & (1 << sys->id));
+}
+
+static const struct clk_ops system_ops = {
+ .enable = clk_system_enable,
+ .disable = clk_system_disable,
+ .is_enabled = clk_system_is_enabled,
+};
+
+struct clk * __init
+at91_clk_register_system(const char *name, u8 id)
+{
+ struct clk_system *sys;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+
+ sys = kzalloc(sizeof(*sys), GFP_KERNEL);
+ if (!sys)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &system_ops;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+ /*
+ * CLK_IGNORE_UNUSED is used to avoid ddrck switch off.
+ * TODO : we should implement a driver supporting at91 ddr controller
+ * (see drivers/memory) which would request and enable the ddrck clock.
+ * When this is done we will be able to remove CLK_IGNORE_UNUSED flag.
+ */
+ init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
+
+ sys->id = id;
+ sys->hw.init = &init;
+
+ clk = clk_register(NULL, &sys->hw);
+
+ if (IS_ERR(clk))
+ kfree(sys);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_system_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_system_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_system_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= SYSTEM_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_sys_setup(struct device_node *np)
+{
+ int i;
+ int num;
+ u32 id;
+ struct clk *clk;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_system_data *clktab;
+ const char *name;
+ struct device_node *sysclknp;
+
+ num = of_get_child_count(np);
+ if (num > SYSTEM_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, sysclknp) {
+ name = sysclknp->name;
+
+ if (of_property_read_u32(sysclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= SYSTEM_MAX)
+ goto out_free_clks;
+
+ clk = at91_clk_register_system(name, id);
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i] = id;
+
+ i++;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_system_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
+{
+ of_at91_clk_sys_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
+ of_at91rm9200_clk_sys_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 324134c..518a568 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -259,4 +259,7 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk_master_characteristics *characteristics);
+struct clk * __init
+at91_clk_register_system(const char *name, u8 id);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 05/42] ARM: at91: add PMC system clocks
@ 2013-07-17 13:45 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:45 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 system clock implementation using common clk framework.
Some peripheral needs to enable a "system" clock in order to work properly.
Each system clock is given an id which is the bit offset used in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-system.c | 184 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 3 +
3 files changed, 188 insertions(+)
create mode 100644 drivers/clk/at91/clk-system.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index d41f616..13e5714 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,3 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
+obj-y += clk-system.o
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 0000000..17e092a
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,184 @@
+/*
+ * drivers/clk/at91/clk-system.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SYSTEM_MAX 32
+
+#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
+struct clk_system {
+ struct clk_hw hw;
+ u8 id;
+};
+
+static int clk_system_enable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCER, 1 << sys->id);
+ return 0;
+}
+
+static void clk_system_disable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCDR, 1 << sys->id);
+}
+
+static int clk_system_is_enabled(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ return !!(at91_pmc_read(AT91_PMC_SCSR) & (1 << sys->id));
+}
+
+static const struct clk_ops system_ops = {
+ .enable = clk_system_enable,
+ .disable = clk_system_disable,
+ .is_enabled = clk_system_is_enabled,
+};
+
+struct clk * __init
+at91_clk_register_system(const char *name, u8 id)
+{
+ struct clk_system *sys;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+
+ sys = kzalloc(sizeof(*sys), GFP_KERNEL);
+ if (!sys)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &system_ops;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+ /*
+ * CLK_IGNORE_UNUSED is used to avoid ddrck switch off.
+ * TODO : we should implement a driver supporting at91 ddr controller
+ * (see drivers/memory) which would request and enable the ddrck clock.
+ * When this is done we will be able to remove CLK_IGNORE_UNUSED flag.
+ */
+ init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
+
+ sys->id = id;
+ sys->hw.init = &init;
+
+ clk = clk_register(NULL, &sys->hw);
+
+ if (IS_ERR(clk))
+ kfree(sys);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_system_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_system_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_system_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= SYSTEM_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_sys_setup(struct device_node *np)
+{
+ int i;
+ int num;
+ u32 id;
+ struct clk *clk;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_system_data *clktab;
+ const char *name;
+ struct device_node *sysclknp;
+
+ num = of_get_child_count(np);
+ if (num > SYSTEM_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, sysclknp) {
+ name = sysclknp->name;
+
+ if (of_property_read_u32(sysclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= SYSTEM_MAX)
+ goto out_free_clks;
+
+ clk = at91_clk_register_system(name, id);
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i] = id;
+
+ i++;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_system_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
+{
+ of_at91_clk_sys_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
+ of_at91rm9200_clk_sys_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 324134c..518a568 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -259,4 +259,7 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk_master_characteristics *characteristics);
+struct clk * __init
+at91_clk_register_system(const char *name, u8 id);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 06/42] ARM: at91: add PMC peripheral clocks
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:46 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:46 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 peripheral clock implementation using common clk framework.
Almost all peripherals provided by an at91 SoC need a clock to work properly.
This clock is enabled/disabled using PCER/PCDR resgisters.
Each peripheral is given an id (see atmel's datasheets) which is used as bit
position in SCER/SCDR registers.
Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you
can configure the peripheral clock as a division of the master clock.
This will help reducing the peripherals power comsumption.
This patch fixes erronous AT91_PMC_PCR_DIV values.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-peripheral.c | 371 +++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 8 +
3 files changed, 380 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-peripheral.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 13e5714..3e2a670 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,4 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
-obj-y += clk-system.o
+obj-y += clk-system.o clk-peripheral.o
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 0000000..11be85ea
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,371 @@
+/*
+ * drivers/clk/at91/clk-peripheral.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PERIPHERAL_MAX 64
+
+#define PERIPHERAL_AT91RM9200 0
+#define PERIPHERAL_AT91SAM9X5 1
+
+#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
+struct clk_peripheral {
+ struct clk_hw hw;
+ u32 id;
+};
+
+#define to_clk_sam9x5_peripheral(hw) \
+ container_of(hw, struct clk_sam9x5_peripheral, hw)
+struct clk_sam9x5_peripheral {
+ struct clk_hw hw;
+ u32 id;
+ u8 div;
+ u8 have_div_support;
+};
+
+static int clk_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCER;
+ if (periph->id < 2)
+ return 0;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCER1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+ return 0;
+}
+
+static void clk_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCDR;
+ if (periph->id < 2)
+ return;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCDR1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+}
+
+static int clk_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCSR;
+ if (periph->id < 2)
+ return 1;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCSR1;
+ return !!(at91_pmc_read(offset) & (1 << (periph->id & 31)));
+}
+
+static const struct clk_ops peripheral_ops = {
+ .enable = clk_peripheral_enable,
+ .disable = clk_peripheral_disable,
+ .is_enabled = clk_peripheral_is_enabled,
+};
+
+struct clk * __init at91_clk_register_peripheral(const char *name,
+ const char *parent_name,
+ u32 id)
+{
+ struct clk_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = 0;
+
+ periph->id = id;
+ periph->hw.init = &init;
+
+ clk = clk_register(NULL, &periph->hw);
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 0;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD |
+ AT91_PMC_PCR_DIV(periph->div) |
+ AT91_PMC_PCR_EN);
+ return 0;
+}
+
+static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return;
+
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD);
+}
+
+static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 1;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ return !!(at91_pmc_read(AT91_PMC_PCR) & AT91_PMC_PCR_EN);
+}
+
+static unsigned long
+clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ u32 shift;
+ if (periph->id < 2 || !periph->have_div_support)
+ return parent_rate;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ shift = (at91_pmc_read(AT91_PMC_PCR) >> 16) & 0x3;
+ return parent_rate >> shift;
+}
+
+static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int shift;
+ unsigned long best_rate;
+ unsigned long best_diff;
+ unsigned long cur_rate;
+ unsigned long cur_diff;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support)
+ return *parent_rate;
+ if (rate >= *parent_rate)
+ return rate;
+ best_diff = *parent_rate - rate;
+ best_rate = *parent_rate;
+ for (shift = 1; shift < 4; shift++) {
+ cur_rate = *parent_rate >> shift;
+ if (cur_rate < rate)
+ cur_diff = rate - cur_rate;
+ else
+ cur_diff = cur_rate - rate;
+ if (cur_diff < best_diff) {
+ best_diff = cur_diff;
+ best_rate = cur_rate;
+ }
+ if (!best_diff || cur_rate < rate)
+ break;
+ }
+ return best_rate;
+}
+
+static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ int shift;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support) {
+ if (parent_rate == rate)
+ return 0;
+ else
+ return -EINVAL;
+ }
+
+ for (shift = 0; shift < 4; shift++) {
+ if (parent_rate >> shift == rate) {
+ periph->div = shift;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops sam9x5_peripheral_ops = {
+ .enable = clk_sam9x5_peripheral_enable,
+ .disable = clk_sam9x5_peripheral_disable,
+ .is_enabled = clk_sam9x5_peripheral_is_enabled,
+ .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
+ .round_rate = clk_sam9x5_peripheral_round_rate,
+ .set_rate = clk_sam9x5_peripheral_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name,
+ const char *parent_name,
+ u32 id, u32 default_div)
+{
+ struct clk_sam9x5_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &sam9x5_peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = CLK_SET_RATE_GATE;
+
+ periph->id = id;
+ periph->hw.init = &init;
+ periph->div = default_div;
+
+ clk = clk_register(NULL, &periph->hw);
+
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_periph_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_periph_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PERIPHERAL_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_periph_setup(struct device_node *np, u8 type)
+{
+ int num;
+ int i;
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name;
+ u32 divisor;
+ struct clk **clks;
+ u8 *ids;
+ struct clk_periph_data *clktab;
+ struct device_node *periphclknp;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ num = of_get_child_count(np);
+ if (!num || num > PERIPHERAL_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, periphclknp) {
+ name = periphclknp->name;
+
+ if (of_property_read_u32(periphclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= PERIPHERAL_MAX)
+ goto out_free_clks;
+
+ if (type == PERIPHERAL_AT91RM9200) {
+ clk = at91_clk_register_peripheral(name,
+ parent_name, id);
+ } else {
+ if (of_property_read_u32(periphclknp,
+ "default-divisor",
+ &divisor))
+ divisor = 0;
+
+ clk = at91_clk_register_sam9x5_peripheral(name,
+ parent_name,
+ id,
+ divisor);
+ }
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i++] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
+}
+CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
+ of_at91rm9200_clk_periph_setup);
+
+static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
+ of_at91sam9x5_clk_periph_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 518a568..112a060 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -262,4 +262,12 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk * __init
at91_clk_register_system(const char *name, u8 id);
+struct clk * __init
+at91_clk_register_peripheral(const char *name, const char *parent_name,
+ u32 id);
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
+ u32 id, u32 default_div);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 06/42] ARM: at91: add PMC peripheral clocks
@ 2013-07-17 13:46 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:46 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 peripheral clock implementation using common clk framework.
Almost all peripherals provided by an at91 SoC need a clock to work properly.
This clock is enabled/disabled using PCER/PCDR resgisters.
Each peripheral is given an id (see atmel's datasheets) which is used as bit
position in SCER/SCDR registers.
Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you
can configure the peripheral clock as a division of the master clock.
This will help reducing the peripherals power comsumption.
This patch fixes erronous AT91_PMC_PCR_DIV values.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-peripheral.c | 371 +++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 8 +
3 files changed, 380 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-peripheral.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 13e5714..3e2a670 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,4 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
-obj-y += clk-system.o
+obj-y += clk-system.o clk-peripheral.o
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 0000000..11be85ea
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,371 @@
+/*
+ * drivers/clk/at91/clk-peripheral.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PERIPHERAL_MAX 64
+
+#define PERIPHERAL_AT91RM9200 0
+#define PERIPHERAL_AT91SAM9X5 1
+
+#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
+struct clk_peripheral {
+ struct clk_hw hw;
+ u32 id;
+};
+
+#define to_clk_sam9x5_peripheral(hw) \
+ container_of(hw, struct clk_sam9x5_peripheral, hw)
+struct clk_sam9x5_peripheral {
+ struct clk_hw hw;
+ u32 id;
+ u8 div;
+ u8 have_div_support;
+};
+
+static int clk_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCER;
+ if (periph->id < 2)
+ return 0;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCER1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+ return 0;
+}
+
+static void clk_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCDR;
+ if (periph->id < 2)
+ return;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCDR1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+}
+
+static int clk_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCSR;
+ if (periph->id < 2)
+ return 1;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCSR1;
+ return !!(at91_pmc_read(offset) & (1 << (periph->id & 31)));
+}
+
+static const struct clk_ops peripheral_ops = {
+ .enable = clk_peripheral_enable,
+ .disable = clk_peripheral_disable,
+ .is_enabled = clk_peripheral_is_enabled,
+};
+
+struct clk * __init at91_clk_register_peripheral(const char *name,
+ const char *parent_name,
+ u32 id)
+{
+ struct clk_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = 0;
+
+ periph->id = id;
+ periph->hw.init = &init;
+
+ clk = clk_register(NULL, &periph->hw);
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 0;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD |
+ AT91_PMC_PCR_DIV(periph->div) |
+ AT91_PMC_PCR_EN);
+ return 0;
+}
+
+static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return;
+
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD);
+}
+
+static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 1;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ return !!(at91_pmc_read(AT91_PMC_PCR) & AT91_PMC_PCR_EN);
+}
+
+static unsigned long
+clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ u32 shift;
+ if (periph->id < 2 || !periph->have_div_support)
+ return parent_rate;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ shift = (at91_pmc_read(AT91_PMC_PCR) >> 16) & 0x3;
+ return parent_rate >> shift;
+}
+
+static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int shift;
+ unsigned long best_rate;
+ unsigned long best_diff;
+ unsigned long cur_rate;
+ unsigned long cur_diff;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support)
+ return *parent_rate;
+ if (rate >= *parent_rate)
+ return rate;
+ best_diff = *parent_rate - rate;
+ best_rate = *parent_rate;
+ for (shift = 1; shift < 4; shift++) {
+ cur_rate = *parent_rate >> shift;
+ if (cur_rate < rate)
+ cur_diff = rate - cur_rate;
+ else
+ cur_diff = cur_rate - rate;
+ if (cur_diff < best_diff) {
+ best_diff = cur_diff;
+ best_rate = cur_rate;
+ }
+ if (!best_diff || cur_rate < rate)
+ break;
+ }
+ return best_rate;
+}
+
+static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ int shift;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support) {
+ if (parent_rate == rate)
+ return 0;
+ else
+ return -EINVAL;
+ }
+
+ for (shift = 0; shift < 4; shift++) {
+ if (parent_rate >> shift == rate) {
+ periph->div = shift;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops sam9x5_peripheral_ops = {
+ .enable = clk_sam9x5_peripheral_enable,
+ .disable = clk_sam9x5_peripheral_disable,
+ .is_enabled = clk_sam9x5_peripheral_is_enabled,
+ .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
+ .round_rate = clk_sam9x5_peripheral_round_rate,
+ .set_rate = clk_sam9x5_peripheral_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name,
+ const char *parent_name,
+ u32 id, u32 default_div)
+{
+ struct clk_sam9x5_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &sam9x5_peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = CLK_SET_RATE_GATE;
+
+ periph->id = id;
+ periph->hw.init = &init;
+ periph->div = default_div;
+
+ clk = clk_register(NULL, &periph->hw);
+
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_periph_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_periph_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PERIPHERAL_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_periph_setup(struct device_node *np, u8 type)
+{
+ int num;
+ int i;
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name;
+ u32 divisor;
+ struct clk **clks;
+ u8 *ids;
+ struct clk_periph_data *clktab;
+ struct device_node *periphclknp;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ num = of_get_child_count(np);
+ if (!num || num > PERIPHERAL_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, periphclknp) {
+ name = periphclknp->name;
+
+ if (of_property_read_u32(periphclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= PERIPHERAL_MAX)
+ goto out_free_clks;
+
+ if (type == PERIPHERAL_AT91RM9200) {
+ clk = at91_clk_register_peripheral(name,
+ parent_name, id);
+ } else {
+ if (of_property_read_u32(periphclknp,
+ "default-divisor",
+ &divisor))
+ divisor = 0;
+
+ clk = at91_clk_register_sam9x5_peripheral(name,
+ parent_name,
+ id,
+ divisor);
+ }
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i++] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
+}
+CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
+ of_at91rm9200_clk_periph_setup);
+
+static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
+ of_at91sam9x5_clk_periph_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 518a568..112a060 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -262,4 +262,12 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk * __init
at91_clk_register_system(const char *name, u8 id);
+struct clk * __init
+at91_clk_register_peripheral(const char *name, const char *parent_name,
+ u32 id);
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
+ u32 id, u32 default_div);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 07/42] ARM: at91: add PMC programmable clocks
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:47 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:47 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 programmable clocks implementation using common clk
framework.
A programmable clock is a clock which can be exported on a given pin to clock
external devices.
Each programmable clock is given an id (from 0 to 8).
The number of available programmable clocks depends on the SoC you're using.
Programmable clock driver only implements the clock setting (clock rate and
parent setting). It must be chained to a system clock in order to
enable/disable the generated clock.
The PCKX pins used to output the clock signals must be assigned to the
appropriate peripheral (see atmel's datasheets).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-programmable.c | 368 +++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 18 ++
3 files changed, 388 insertions(+)
create mode 100644 drivers/clk/at91/clk-programmable.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 3e2a670..2d7c119 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,3 +4,5 @@
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
+
+obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 0000000..21829fc
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,368 @@
+/*
+ * drivers/clk/at91/clk-programmable.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PROG_SOURCE_MAX 5
+#define PROG_MAX 8
+
+#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
+struct clk_programmable {
+ struct clk_hw hw;
+ u8 id;
+ u8 css;
+ u8 pres;
+ u8 slckmck;
+ struct clk_programmable_layout *layout;
+};
+
+static int clk_programmable_prepare(struct clk_hw *hw)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = prog->css | (prog->pres << layout->pres_shift);
+ if (layout->have_slck_mck && prog->slckmck)
+ tmp |= 1 << 8;
+ at91_pmc_write(AT91_PMC_PCKR(prog->id), tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & (1 << (prog->id + 8))))
+ ;
+ return 0;
+}
+
+static int clk_programmable_is_prepared(struct clk_hw *hw)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) & (1 << (prog->id + 8)));
+}
+
+static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->pres = (tmp >> layout->pres_shift) & 0x7;
+ return parent_rate >> prog->pres;
+}
+
+static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long best_rate = *parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = shift;
+
+ if (rate > *parent_rate)
+ return *parent_rate;
+ else
+ best_diff = *parent_rate - rate;
+
+ if (!best_diff)
+ return best_rate;
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = *parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ return cur_rate;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ return best_rate;
+}
+
+static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ if (index > layout->css_mask) {
+ if (index == 4 && layout->have_slck_mck) {
+ prog->css = 0;
+ prog->slckmck = 1;
+ return 0;
+ } else
+ return -EINVAL;
+ }
+
+ prog->css = index;
+ return 0;
+}
+
+static u8 clk_programmable_get_parent(struct clk_hw *hw)
+{
+ u32 tmp;
+ u8 ret;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->css = tmp & layout->css_mask;
+ ret = prog->css;
+ if (layout->have_slck_mck) {
+ prog->slckmck = !!(tmp & (1 << 8));
+ if (prog->slckmck && !ret)
+ ret = 4;
+ }
+
+ return ret;
+}
+
+static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ unsigned long best_rate = parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = 0;
+
+ if (rate > parent_rate)
+ return parent_rate;
+ else
+ best_diff = parent_rate - rate;
+
+ if (!best_diff) {
+ prog->pres = shift;
+ return 0;
+ }
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ break;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ prog->pres = shift;
+ return 0;
+}
+
+static const struct clk_ops programmable_ops = {
+ .prepare = clk_programmable_prepare,
+ .is_prepared = clk_programmable_is_prepared,
+ .recalc_rate = clk_programmable_recalc_rate,
+ .round_rate = clk_programmable_round_rate,
+ .get_parent = clk_programmable_get_parent,
+ .set_parent = clk_programmable_set_parent,
+ .set_rate = clk_programmable_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout)
+{
+ struct clk_programmable *prog;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 7;
+
+ prog = kzalloc(sizeof(*prog), GFP_KERNEL);
+ if (!prog)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &programmable_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ prog->id = id;
+ prog->layout = layout;
+ prog->hw.init = &init;
+
+ clk = clk_register(NULL, &prog->hw);
+
+ if (IS_ERR(clk))
+ kfree(prog);
+
+ return clk;
+}
+
+struct clk_programmable_layout at91rm9200_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 0,
+};
+
+struct clk_programmable_layout at91sam9g45_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 1,
+};
+
+struct clk_programmable_layout at91sam9x5_programmable_layout = {
+ .pres_shift = 4,
+ .css_mask = 0x7,
+ .have_slck_mck = 0,
+};
+
+#if defined(CONFIG_OF)
+struct clk_prog_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_prog_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PROG_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_prog_setup(struct device_node *np,
+ struct clk_programmable_layout *layout)
+{
+ int num;
+ u32 id;
+ int i;
+ struct clk *clk;
+ int num_parents;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_prog_data *clktab;
+ const char *parent_names[PROG_SOURCE_MAX];
+ const char *name;
+ struct device_node *progclknp;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ num = of_get_child_count(np);
+ if (!num || num > PROG_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, progclknp) {
+ name = progclknp->name;
+
+ if (of_property_read_u32(progclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= PROG_MAX)
+ goto out_free_clks;
+
+ clk = at91_clk_register_programmable(name, parent_names,
+ num_parents, id, layout);
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i++] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+
+static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
+ of_at91rm9200_clk_prog_setup);
+
+static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
+ of_at91sam9g45_clk_prog_setup);
+
+static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
+ of_at91sam9x5_clk_prog_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 112a060..3cafd36 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -224,6 +224,12 @@ struct clk_master_layout {
u8 pres_shift;
};
+struct clk_programmable_layout {
+ u8 pres_shift;
+ u8 css_mask;
+ u8 have_slck_mck;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -270,4 +276,16 @@ struct clk * __init
at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
u32 id, u32 default_div);
+
+extern struct clk_programmable_layout at91rm9200_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9g45_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9x5_programmable_layout;
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 07/42] ARM: at91: add PMC programmable clocks
@ 2013-07-17 13:47 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:47 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 programmable clocks implementation using common clk
framework.
A programmable clock is a clock which can be exported on a given pin to clock
external devices.
Each programmable clock is given an id (from 0 to 8).
The number of available programmable clocks depends on the SoC you're using.
Programmable clock driver only implements the clock setting (clock rate and
parent setting). It must be chained to a system clock in order to
enable/disable the generated clock.
The PCKX pins used to output the clock signals must be assigned to the
appropriate peripheral (see atmel's datasheets).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-programmable.c | 368 +++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 18 ++
3 files changed, 388 insertions(+)
create mode 100644 drivers/clk/at91/clk-programmable.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 3e2a670..2d7c119 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,3 +4,5 @@
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
+
+obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 0000000..21829fc
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,368 @@
+/*
+ * drivers/clk/at91/clk-programmable.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PROG_SOURCE_MAX 5
+#define PROG_MAX 8
+
+#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
+struct clk_programmable {
+ struct clk_hw hw;
+ u8 id;
+ u8 css;
+ u8 pres;
+ u8 slckmck;
+ struct clk_programmable_layout *layout;
+};
+
+static int clk_programmable_prepare(struct clk_hw *hw)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = prog->css | (prog->pres << layout->pres_shift);
+ if (layout->have_slck_mck && prog->slckmck)
+ tmp |= 1 << 8;
+ at91_pmc_write(AT91_PMC_PCKR(prog->id), tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & (1 << (prog->id + 8))))
+ ;
+ return 0;
+}
+
+static int clk_programmable_is_prepared(struct clk_hw *hw)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) & (1 << (prog->id + 8)));
+}
+
+static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->pres = (tmp >> layout->pres_shift) & 0x7;
+ return parent_rate >> prog->pres;
+}
+
+static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long best_rate = *parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = shift;
+
+ if (rate > *parent_rate)
+ return *parent_rate;
+ else
+ best_diff = *parent_rate - rate;
+
+ if (!best_diff)
+ return best_rate;
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = *parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ return cur_rate;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ return best_rate;
+}
+
+static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ if (index > layout->css_mask) {
+ if (index == 4 && layout->have_slck_mck) {
+ prog->css = 0;
+ prog->slckmck = 1;
+ return 0;
+ } else
+ return -EINVAL;
+ }
+
+ prog->css = index;
+ return 0;
+}
+
+static u8 clk_programmable_get_parent(struct clk_hw *hw)
+{
+ u32 tmp;
+ u8 ret;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->css = tmp & layout->css_mask;
+ ret = prog->css;
+ if (layout->have_slck_mck) {
+ prog->slckmck = !!(tmp & (1 << 8));
+ if (prog->slckmck && !ret)
+ ret = 4;
+ }
+
+ return ret;
+}
+
+static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ unsigned long best_rate = parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = 0;
+
+ if (rate > parent_rate)
+ return parent_rate;
+ else
+ best_diff = parent_rate - rate;
+
+ if (!best_diff) {
+ prog->pres = shift;
+ return 0;
+ }
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ break;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ prog->pres = shift;
+ return 0;
+}
+
+static const struct clk_ops programmable_ops = {
+ .prepare = clk_programmable_prepare,
+ .is_prepared = clk_programmable_is_prepared,
+ .recalc_rate = clk_programmable_recalc_rate,
+ .round_rate = clk_programmable_round_rate,
+ .get_parent = clk_programmable_get_parent,
+ .set_parent = clk_programmable_set_parent,
+ .set_rate = clk_programmable_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout)
+{
+ struct clk_programmable *prog;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 7;
+
+ prog = kzalloc(sizeof(*prog), GFP_KERNEL);
+ if (!prog)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &programmable_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ prog->id = id;
+ prog->layout = layout;
+ prog->hw.init = &init;
+
+ clk = clk_register(NULL, &prog->hw);
+
+ if (IS_ERR(clk))
+ kfree(prog);
+
+ return clk;
+}
+
+struct clk_programmable_layout at91rm9200_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 0,
+};
+
+struct clk_programmable_layout at91sam9g45_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 1,
+};
+
+struct clk_programmable_layout at91sam9x5_programmable_layout = {
+ .pres_shift = 4,
+ .css_mask = 0x7,
+ .have_slck_mck = 0,
+};
+
+#if defined(CONFIG_OF)
+struct clk_prog_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_prog_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PROG_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_prog_setup(struct device_node *np,
+ struct clk_programmable_layout *layout)
+{
+ int num;
+ u32 id;
+ int i;
+ struct clk *clk;
+ int num_parents;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_prog_data *clktab;
+ const char *parent_names[PROG_SOURCE_MAX];
+ const char *name;
+ struct device_node *progclknp;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ num = of_get_child_count(np);
+ if (!num || num > PROG_MAX)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ i = 0;
+ for_each_child_of_node(np, progclknp) {
+ name = progclknp->name;
+
+ if (of_property_read_u32(progclknp, "id", &id))
+ goto out_free_clks;
+ if (id >= PROG_MAX)
+ goto out_free_clks;
+
+ clk = at91_clk_register_programmable(name, parent_names,
+ num_parents, id, layout);
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i++] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+
+static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
+ of_at91rm9200_clk_prog_setup);
+
+static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
+ of_at91sam9g45_clk_prog_setup);
+
+static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
+ of_at91sam9x5_clk_prog_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 112a060..3cafd36 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -224,6 +224,12 @@ struct clk_master_layout {
u8 pres_shift;
};
+struct clk_programmable_layout {
+ u8 pres_shift;
+ u8 css_mask;
+ u8 have_slck_mck;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -270,4 +276,16 @@ struct clk * __init
at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
u32 id, u32 default_div);
+
+extern struct clk_programmable_layout at91rm9200_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9g45_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9x5_programmable_layout;
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 08/42] ARM: at91: add PMC utmi clock
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:50 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:50 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 utmi clock implementation using common clk framework.
This clock is a pll with a fixed factor (x40).
It is used as a source for usb clock.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 7 +++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-utmi.c | 114 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 4 ++
4 files changed, 126 insertions(+)
create mode 100644 drivers/clk/at91/clk-utmi.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 699b71e..1a24a1f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,8 @@
if ARCH_AT91
+config HAVE_AT91_UTMI
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -65,6 +68,7 @@ config SOC_SAMA5D3
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -106,12 +110,14 @@ config SOC_AT91SAM9RL
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
config SOC_AT91SAM9G45
bool "AT91SAM9G45 or AT91SAM9M10 families"
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +127,7 @@ config SOC_AT91SAM9X5
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 2d7c119..76d09f0 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 0000000..c0dd596
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,114 @@
+/*
+ * drivers/clk/at91/clk-utmi.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
+
+struct clk_utmi {
+ struct clk_hw hw;
+};
+
+static int clk_utmi_prepare(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
+ AT91_PMC_UPLLCOUNT;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU))
+ ;
+ return 0;
+}
+
+static int clk_utmi_is_prepared(struct clk_hw *hw)
+{
+ return !!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU);
+}
+
+static void clk_utmi_disable(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+}
+
+static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate * 40;
+}
+
+static const struct clk_ops utmi_ops = {
+ .prepare = clk_utmi_prepare,
+ .is_prepared = clk_utmi_is_prepared,
+ .disable = clk_utmi_disable,
+ .recalc_rate = clk_utmi_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name)
+{
+ struct clk_utmi *utmi;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &utmi_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ utmi->hw.init = &init;
+
+ clk = clk_register(NULL, &utmi->hw);
+
+ if (IS_ERR(clk))
+ kfree(utmi);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_utmi_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_utmi(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
+{
+ of_at91_clk_utmi_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
+ of_at91sam9x5_clk_utmi_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 3cafd36..47ef7e8 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -288,4 +288,8 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
u8 num_parents, u8 id,
struct clk_programmable_layout *layout);
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 08/42] ARM: at91: add PMC utmi clock
@ 2013-07-17 13:50 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:50 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 utmi clock implementation using common clk framework.
This clock is a pll with a fixed factor (x40).
It is used as a source for usb clock.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 7 +++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-utmi.c | 114 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 4 ++
4 files changed, 126 insertions(+)
create mode 100644 drivers/clk/at91/clk-utmi.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 699b71e..1a24a1f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,8 @@
if ARCH_AT91
+config HAVE_AT91_UTMI
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -65,6 +68,7 @@ config SOC_SAMA5D3
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -106,12 +110,14 @@ config SOC_AT91SAM9RL
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
config SOC_AT91SAM9G45
bool "AT91SAM9G45 or AT91SAM9M10 families"
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +127,7 @@ config SOC_AT91SAM9X5
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 2d7c119..76d09f0 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 0000000..c0dd596
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,114 @@
+/*
+ * drivers/clk/at91/clk-utmi.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
+
+struct clk_utmi {
+ struct clk_hw hw;
+};
+
+static int clk_utmi_prepare(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
+ AT91_PMC_UPLLCOUNT;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU))
+ ;
+ return 0;
+}
+
+static int clk_utmi_is_prepared(struct clk_hw *hw)
+{
+ return !!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU);
+}
+
+static void clk_utmi_disable(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+}
+
+static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate * 40;
+}
+
+static const struct clk_ops utmi_ops = {
+ .prepare = clk_utmi_prepare,
+ .is_prepared = clk_utmi_is_prepared,
+ .disable = clk_utmi_disable,
+ .recalc_rate = clk_utmi_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name)
+{
+ struct clk_utmi *utmi;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &utmi_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ utmi->hw.init = &init;
+
+ clk = clk_register(NULL, &utmi->hw);
+
+ if (IS_ERR(clk))
+ kfree(utmi);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_utmi_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_utmi(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
+{
+ of_at91_clk_utmi_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
+ of_at91sam9x5_clk_utmi_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 3cafd36..47ef7e8 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -288,4 +288,8 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
u8 num_parents, u8 id,
struct clk_programmable_layout *layout);
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 09/42] ARM: at91: add PMC usb clock
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:52 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:52 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 11 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-usb.c | 303 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 9 ++
4 files changed, 324 insertions(+)
create mode 100644 drivers/clk/at91/clk-usb.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1a24a1f..ac18755 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,9 @@ if ARCH_AT91
config HAVE_AT91_UTMI
bool
+config HAVE_AT91_USB_CLK
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -69,6 +72,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -82,11 +86,13 @@ config SOC_AT91RM9200
select HAVE_AT91_DBGU0
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
select HAVE_AT91_DBGU0
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@@ -96,6 +102,7 @@ config SOC_AT91SAM9261
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -104,6 +111,7 @@ config SOC_AT91SAM9263
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9RL
bool "AT91SAM9RL"
@@ -118,6 +126,7 @@ config SOC_AT91SAM9G45
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -128,6 +137,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
@@ -140,6 +150,7 @@ config SOC_AT91SAM9N12
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 76d09f0..bbfd245 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
+obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 0000000..4af0fe3
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,303 @@
+/*
+ * drivers/clk/at91/clk-usb.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define USB_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_usb(hw) \
+ container_of(hw, struct at91sam9x5_clk_usb, hw)
+struct at91sam9x5_clk_usb {
+ struct clk_hw hw;
+ u8 usbs0_unused; /* sam9n12 uses usbs0 to disable usb clock */
+};
+
+#define to_at91rm9200_clk_usb(hw) \
+ container_of(hw, struct at91rm9200_clk_usb, hw)
+struct at91rm9200_clk_usb {
+ struct clk_hw hw;
+ u32 divisors[4];
+};
+
+static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_PMC_USB);
+ usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> 8;
+ return parent_rate / (usbdiv + 1);
+}
+
+static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ index++;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_USBS;
+ if (index)
+ tmp |= AT91_PMC_USBS;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
+{
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ return 0;
+ return at91_pmc_read(AT91_PMC_USB) & AT91_PMC_USBS;
+}
+
+static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_usb_ops = {
+ .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
+ .round_rate = at91sam9x5_clk_usb_round_rate,
+ .get_parent = at91sam9x5_clk_usb_get_parent,
+ .set_parent = at91sam9x5_clk_usb_set_parent,
+ .set_rate = at91sam9x5_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused)
+{
+ struct at91sam9x5_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_usb_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ usb->usbs0_unused = usbs0_unused;
+ usb->hw.init = &init;
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR);
+ usbdiv = (tmp & AT91_PMC_USBDIV) >> 28;
+ if (usb->divisors[usbdiv])
+ return parent_rate / usb->divisors[usbdiv];
+ return 0;
+}
+
+static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long bestrate = 0;
+ int bestdiff = -1;
+ unsigned long tmprate;
+ int tmpdiff;
+ int i = 0;
+
+ for (i = 0; i < 4; i++) {
+ if (!usb->divisors[i])
+ continue;
+ tmprate = *parent_rate / usb->divisors[i];
+ if (tmprate < rate)
+ tmpdiff = rate - tmprate;
+ else
+ tmpdiff = tmprate - rate;
+
+ if (bestdiff < 0 || bestdiff > tmpdiff) {
+ bestrate = tmprate;
+ bestdiff = tmpdiff;
+ }
+
+ if (!bestdiff)
+ break;
+ }
+
+ return bestrate;
+}
+
+static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ int i;
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate)
+ return -EINVAL;
+ for (i = 0; i < 4; i++) {
+ if (usb->divisors[i] == div) {
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR) &
+ ~AT91_PMC_USBDIV;
+ tmp |= i << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops at91rm9200_usb_ops = {
+ .recalc_rate = at91rm9200_clk_usb_recalc_rate,
+ .round_rate = at91rm9200_clk_usb_round_rate,
+ .set_rate = at91rm9200_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors)
+{
+ struct at91rm9200_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91rm9200_usb_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = 0;
+
+ usb->hw.init = &init;
+ memcpy(usb->divisors, divisors, sizeof(usb->divisors));
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ u8 usbs0_unused;
+ const char *parent_names[USB_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > USB_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ usbs0_unused = of_property_read_bool(np, "usbs0-unused");
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_usb(name, parent_names, num_parents,
+ usbs0_unused);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
+ of_at91sam9x5_clk_usb_setup);
+
+static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 divisors[4] = {0, 0, 0, 0};
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ of_property_read_u32_array(np, "divisors", divisors, 4);
+ if (!divisors[0])
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91rm9200_clk_register_usb(name, parent_name, divisors);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
+ of_at91rm9200_clk_usb_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 47ef7e8..2d083d1 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -292,4 +292,13 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
struct clk * __init
at91_clk_register_utmi(const char *name, const char *parent_name);
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors);
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 09/42] ARM: at91: add PMC usb clock
@ 2013-07-17 13:52 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:52 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 11 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-usb.c | 303 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 9 ++
4 files changed, 324 insertions(+)
create mode 100644 drivers/clk/at91/clk-usb.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1a24a1f..ac18755 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,9 @@ if ARCH_AT91
config HAVE_AT91_UTMI
bool
+config HAVE_AT91_USB_CLK
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -69,6 +72,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -82,11 +86,13 @@ config SOC_AT91RM9200
select HAVE_AT91_DBGU0
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
select HAVE_AT91_DBGU0
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@@ -96,6 +102,7 @@ config SOC_AT91SAM9261
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -104,6 +111,7 @@ config SOC_AT91SAM9263
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9RL
bool "AT91SAM9RL"
@@ -118,6 +126,7 @@ config SOC_AT91SAM9G45
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -128,6 +137,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
@@ -140,6 +150,7 @@ config SOC_AT91SAM9N12
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 76d09f0..bbfd245 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
+obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 0000000..4af0fe3
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,303 @@
+/*
+ * drivers/clk/at91/clk-usb.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define USB_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_usb(hw) \
+ container_of(hw, struct at91sam9x5_clk_usb, hw)
+struct at91sam9x5_clk_usb {
+ struct clk_hw hw;
+ u8 usbs0_unused; /* sam9n12 uses usbs0 to disable usb clock */
+};
+
+#define to_at91rm9200_clk_usb(hw) \
+ container_of(hw, struct at91rm9200_clk_usb, hw)
+struct at91rm9200_clk_usb {
+ struct clk_hw hw;
+ u32 divisors[4];
+};
+
+static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_PMC_USB);
+ usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> 8;
+ return parent_rate / (usbdiv + 1);
+}
+
+static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ index++;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_USBS;
+ if (index)
+ tmp |= AT91_PMC_USBS;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
+{
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ return 0;
+ return at91_pmc_read(AT91_PMC_USB) & AT91_PMC_USBS;
+}
+
+static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_usb_ops = {
+ .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
+ .round_rate = at91sam9x5_clk_usb_round_rate,
+ .get_parent = at91sam9x5_clk_usb_get_parent,
+ .set_parent = at91sam9x5_clk_usb_set_parent,
+ .set_rate = at91sam9x5_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused)
+{
+ struct at91sam9x5_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_usb_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ usb->usbs0_unused = usbs0_unused;
+ usb->hw.init = &init;
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR);
+ usbdiv = (tmp & AT91_PMC_USBDIV) >> 28;
+ if (usb->divisors[usbdiv])
+ return parent_rate / usb->divisors[usbdiv];
+ return 0;
+}
+
+static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long bestrate = 0;
+ int bestdiff = -1;
+ unsigned long tmprate;
+ int tmpdiff;
+ int i = 0;
+
+ for (i = 0; i < 4; i++) {
+ if (!usb->divisors[i])
+ continue;
+ tmprate = *parent_rate / usb->divisors[i];
+ if (tmprate < rate)
+ tmpdiff = rate - tmprate;
+ else
+ tmpdiff = tmprate - rate;
+
+ if (bestdiff < 0 || bestdiff > tmpdiff) {
+ bestrate = tmprate;
+ bestdiff = tmpdiff;
+ }
+
+ if (!bestdiff)
+ break;
+ }
+
+ return bestrate;
+}
+
+static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ int i;
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate)
+ return -EINVAL;
+ for (i = 0; i < 4; i++) {
+ if (usb->divisors[i] == div) {
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR) &
+ ~AT91_PMC_USBDIV;
+ tmp |= i << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops at91rm9200_usb_ops = {
+ .recalc_rate = at91rm9200_clk_usb_recalc_rate,
+ .round_rate = at91rm9200_clk_usb_round_rate,
+ .set_rate = at91rm9200_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors)
+{
+ struct at91rm9200_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91rm9200_usb_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = 0;
+
+ usb->hw.init = &init;
+ memcpy(usb->divisors, divisors, sizeof(usb->divisors));
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ u8 usbs0_unused;
+ const char *parent_names[USB_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > USB_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ usbs0_unused = of_property_read_bool(np, "usbs0-unused");
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_usb(name, parent_names, num_parents,
+ usbs0_unused);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
+ of_at91sam9x5_clk_usb_setup);
+
+static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 divisors[4] = {0, 0, 0, 0};
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ of_property_read_u32_array(np, "divisors", divisors, 4);
+ if (!divisors[0])
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91rm9200_clk_register_usb(name, parent_name, divisors);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
+ of_at91rm9200_clk_usb_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 47ef7e8..2d083d1 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -292,4 +292,13 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
struct clk * __init
at91_clk_register_utmi(const char *name, const char *parent_name);
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors);
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused);
+
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 10/42] ARM: at91: add PMC smd clock
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:53 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:53 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This is the at91 smd (Soft Modem) clock implementation using common clk
framework.
Not used by any driver right now.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 5 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-smd.c | 157 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
create mode 100644 drivers/clk/at91/clk-smd.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index ac18755..c8e02ca 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -27,6 +27,9 @@ config AT91_SAM9G45_RESET
config AT91_SAM9_TIME
bool
+config HAVE_AT91_SMD
+ bool
+
config SOC_AT91SAM9
bool
select AT91_SAM9_TIME
@@ -72,6 +75,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
@@ -137,6 +141,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index bbfd245..7206f4c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -8,3 +8,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
+obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 0000000..61bd8a5
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,157 @@
+/*
+ * drivers/clk/at91/clk-smd.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SMD_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_smd(hw) \
+ container_of(hw, struct at91sam9x5_clk_smd, hw)
+struct at91sam9x5_clk_smd {
+ struct clk_hw hw;
+};
+
+static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 smddiv;
+ tmp = at91_pmc_read(AT91_PMC_SMD);
+ smddiv = (tmp & AT91_PMC_SMD_DIV) >> 8;
+ return parent_rate / (smddiv + 1);
+}
+
+static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMDS;
+ if (index)
+ tmp |= AT91_PMC_SMDS;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_SMD) & AT91_PMC_SMDS;
+}
+
+static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_smd_ops = {
+ .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
+ .round_rate = at91sam9x5_clk_smd_round_rate,
+ .get_parent = at91sam9x5_clk_smd_get_parent,
+ .set_parent = at91sam9x5_clk_smd_set_parent,
+ .set_rate = at91sam9x5_clk_smd_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_smd(const char *name, const char **parent_names,
+ u8 num_parents)
+{
+ struct at91sam9x5_clk_smd *smd;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ smd = kzalloc(sizeof(*smd), GFP_KERNEL);
+ if (!smd)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_smd_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ smd->hw.init = &init;
+
+ clk = clk_register(NULL, &smd->hw);
+
+ if (IS_ERR(clk))
+ kfree(smd);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ const char *parent_names[SMD_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents >= SMD_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_smd(name, parent_names, num_parents);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
+ of_at91sam9x5_clk_smd_setup);
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 10/42] ARM: at91: add PMC smd clock
@ 2013-07-17 13:53 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:53 UTC (permalink / raw)
To: linux-arm-kernel
This is the at91 smd (Soft Modem) clock implementation using common clk
framework.
Not used by any driver right now.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 5 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-smd.c | 157 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
create mode 100644 drivers/clk/at91/clk-smd.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index ac18755..c8e02ca 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -27,6 +27,9 @@ config AT91_SAM9G45_RESET
config AT91_SAM9_TIME
bool
+config HAVE_AT91_SMD
+ bool
+
config SOC_AT91SAM9
bool
select AT91_SAM9_TIME
@@ -72,6 +75,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
@@ -137,6 +141,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index bbfd245..7206f4c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -8,3 +8,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
+obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 0000000..61bd8a5
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,157 @@
+/*
+ * drivers/clk/at91/clk-smd.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SMD_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_smd(hw) \
+ container_of(hw, struct at91sam9x5_clk_smd, hw)
+struct at91sam9x5_clk_smd {
+ struct clk_hw hw;
+};
+
+static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 smddiv;
+ tmp = at91_pmc_read(AT91_PMC_SMD);
+ smddiv = (tmp & AT91_PMC_SMD_DIV) >> 8;
+ return parent_rate / (smddiv + 1);
+}
+
+static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMDS;
+ if (index)
+ tmp |= AT91_PMC_SMDS;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_SMD) & AT91_PMC_SMDS;
+}
+
+static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_smd_ops = {
+ .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
+ .round_rate = at91sam9x5_clk_smd_round_rate,
+ .get_parent = at91sam9x5_clk_smd_get_parent,
+ .set_parent = at91sam9x5_clk_smd_set_parent,
+ .set_rate = at91sam9x5_clk_smd_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_smd(const char *name, const char **parent_names,
+ u8 num_parents)
+{
+ struct at91sam9x5_clk_smd *smd;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ smd = kzalloc(sizeof(*smd), GFP_KERNEL);
+ if (!smd)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_smd_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ smd->hw.init = &init;
+
+ clk = clk_register(NULL, &smd->hw);
+
+ if (IS_ERR(clk))
+ kfree(smd);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ const char *parent_names[SMD_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents >= SMD_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_smd(name, parent_names, num_parents);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
+ of_at91sam9x5_clk_smd_setup);
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 11/42] ARM: at91: add PMC clk device tree binding doc.
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 13:55 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:55 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Grant Likely,
Rob Herring, Rob Landley
Cc: linux-arm-kernel, linux-kernel, devicetree-discuss, linux-doc,
Boris BREZILLON
This is the documentation of the dt bindings used by at91 clks.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
.../devicetree/bindings/clock/at91-clock.txt | 262 ++++++++++++++++++++
1 file changed, 262 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
new file mode 100644
index 0000000..ca98783
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -0,0 +1,262 @@
+Device Tree Clock bindings for arch-at91
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "atmel,at91rm9200-clk-main":
+ at91 main oscillator
+
+ "atmel,at91rm9200-clk-master" or
+ "atmel,at91sam9x5-clk-master":
+ at91 master clock
+
+ "atmel,at91sam9x5-clk-peripheral" or
+ "atmel,at91rm9200-clk-peripheral":
+ at91 peripheral clocks
+
+ "atmel,at91rm9200-clk-pll" or
+ "atmel,at91sam9g45-clk-pll" or
+ "atmel,at91sam9g20-clk-pllb" or
+ "atmel,sama5d3-clk-pll":
+ at91 pll clocks
+
+ "atmel,at91sam9x5-clk-plldiv":
+ at91 plla divisor
+
+ "atmel,at91rm9200-clk-programmable" or
+ "atmel,at91sam9g45-clk-programmable" or
+ "atmel,at91sam9x5-clk-programmable":
+ at91 programmable clocks
+
+ "atmel,at91sam9x5-clk-smd":
+ at91 SMD (Soft Modem) clock
+
+ "atmel,at91rm9200-clk-system":
+ at91 system clocks
+
+ "atmel,at91rm9200-clk-usb" or
+ "atmel,at91sam9x5-clk-usb":
+ at91 usb clock
+
+ "atmel,at91sam9x5-clk-utmi":
+ at91 utmi clock
+
+
+Required properties for main clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks (optional if clock-frequency is provided) : shall be the slow clock
+ phandle. This clock is used to compute the main clock rate if
+ "clock-frequency" is not provided.
+- clock-frequency: the main oscillator frequency.Prefer the use of
+ "clock-frequency" over automatic clock rate computation.
+
+For example:
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&ck32k>;
+ clock-frequency = <18432000>;
+ };
+
+Required properties for master clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock sources (see atmel datasheet) phandles.
+ e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
+- characteristics : device tree node describing master clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * output : minimum and maximum clock frequency (two u32 fields).
+ e.g. output = <0 133000000>; <=> 0 to 133MHz.
+ * divisors : master clock divisors table (four u32 fields).
+ 0 <=> reserved value.
+ e.g. divisors = <1 2 4 6>;
+ * have-div3-pres : some SoC use the reserved value 7 in the PRES field
+ as CLOCK_DIV3 (e.g sam9x5).
+
+For example:
+ mck: mck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ characteristics = {
+ output = <0 133000000>;
+ divisors = <1 2 4 0>;
+ };
+ };
+
+Required properties for peripheral clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the peripheral id. Peripheral ids are defined in
+ atmel's SoC datasheets.
+- clocks : shall be the master clock phandle.
+ e.g. clocks = <&mck>;
+- name@id: device tree node describing a specific system clock.
+ * id: peripheral id.
+ * default-divisor (optional, only available for
+ "atmel,at91sam9x5-clk-peripheral"): sam9x5 and sama5d3 SoC provides
+ configurable peripheral clock divisor. If you define this property
+ (u32), the default divisor will be applied when enabling
+ peripheral clock. If not provided the peripheral clock is not divided.
+
+For example:
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk@1 {
+ id = <1>;
+ default-divisor = <1>;
+ };
+
+ pioB_clk@2 {
+ id = <2>;
+ default-divisor = <2>;
+ };
+ };
+
+
+Required properties for pll clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock phandle.
+- id : pll id
+ * 0 <=> plla
+ * 1 <=> pllb
+- characteristics : device tree node describing pll clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * input : minimum and maximum source clock frequency (two u32 fields).
+ e.g. input = <1 32000000>; <=> 1 to 32MHz.
+ * output : output frequency ranges.
+ * out: out field value for output frequency ranges.
+ * icpll (not available on some SoC): icpll field value for output
+ frequency ranges.
+
+For example:
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+Required properties for plldiv clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the plla clock phandle.
+
+For example:
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+Required properties for programmable clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the programmable clock id.
+ Peripheral ids are in atmel's SoC
+ datasheets.
+- clocks : shall be the programmable clock source phandles.
+ e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+- name@id: device tree node describing a specific prog clock.
+ * id: programmable clock id (register offset from PCKx register).
+
+For example:
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+ };
+
+
+Required properties for smd clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&plladiv>, <&utmi>;
+
+For example:
+ smd: smdck {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+Required properties for system clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the system clock id (bit used in SCER/SCDR register).
+- name@id: device tree node describing a specific system clock.
+ * id: system clock id (bit position in SCER/SCDR/SCSR registers).
+
+For example:
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck@2 {
+ id = <2>;
+ };
+
+ uhpck@6 {
+ id = <6>;
+ };
+
+ udpck@7 {
+ id = <7>;
+ };
+ };
+
+
+Required properties for usb clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&pllb>;
+- divisors (only available for "atmel,at91rm9200-clk-usb"):
+ usb clock divisor table.
+ e.g. divisors = <1 2 4 0>;
+- usbs0-unused (only available for "atmel,at91sam9x5-clk-usb"):
+ Some SoC (sam9n12) use usb source 0 to disable the usb clock.
+
+For example:
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+
+Required properties for utmi clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock source phandle.
+
+For example:
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 11/42] ARM: at91: add PMC clk device tree binding doc.
@ 2013-07-17 13:55 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 13:55 UTC (permalink / raw)
To: linux-arm-kernel
This is the documentation of the dt bindings used by at91 clks.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
.../devicetree/bindings/clock/at91-clock.txt | 262 ++++++++++++++++++++
1 file changed, 262 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
new file mode 100644
index 0000000..ca98783
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -0,0 +1,262 @@
+Device Tree Clock bindings for arch-at91
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "atmel,at91rm9200-clk-main":
+ at91 main oscillator
+
+ "atmel,at91rm9200-clk-master" or
+ "atmel,at91sam9x5-clk-master":
+ at91 master clock
+
+ "atmel,at91sam9x5-clk-peripheral" or
+ "atmel,at91rm9200-clk-peripheral":
+ at91 peripheral clocks
+
+ "atmel,at91rm9200-clk-pll" or
+ "atmel,at91sam9g45-clk-pll" or
+ "atmel,at91sam9g20-clk-pllb" or
+ "atmel,sama5d3-clk-pll":
+ at91 pll clocks
+
+ "atmel,at91sam9x5-clk-plldiv":
+ at91 plla divisor
+
+ "atmel,at91rm9200-clk-programmable" or
+ "atmel,at91sam9g45-clk-programmable" or
+ "atmel,at91sam9x5-clk-programmable":
+ at91 programmable clocks
+
+ "atmel,at91sam9x5-clk-smd":
+ at91 SMD (Soft Modem) clock
+
+ "atmel,at91rm9200-clk-system":
+ at91 system clocks
+
+ "atmel,at91rm9200-clk-usb" or
+ "atmel,at91sam9x5-clk-usb":
+ at91 usb clock
+
+ "atmel,at91sam9x5-clk-utmi":
+ at91 utmi clock
+
+
+Required properties for main clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks (optional if clock-frequency is provided) : shall be the slow clock
+ phandle. This clock is used to compute the main clock rate if
+ "clock-frequency" is not provided.
+- clock-frequency: the main oscillator frequency.Prefer the use of
+ "clock-frequency" over automatic clock rate computation.
+
+For example:
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&ck32k>;
+ clock-frequency = <18432000>;
+ };
+
+Required properties for master clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock sources (see atmel datasheet) phandles.
+ e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
+- characteristics : device tree node describing master clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * output : minimum and maximum clock frequency (two u32 fields).
+ e.g. output = <0 133000000>; <=> 0 to 133MHz.
+ * divisors : master clock divisors table (four u32 fields).
+ 0 <=> reserved value.
+ e.g. divisors = <1 2 4 6>;
+ * have-div3-pres : some SoC use the reserved value 7 in the PRES field
+ as CLOCK_DIV3 (e.g sam9x5).
+
+For example:
+ mck: mck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ characteristics = {
+ output = <0 133000000>;
+ divisors = <1 2 4 0>;
+ };
+ };
+
+Required properties for peripheral clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the peripheral id. Peripheral ids are defined in
+ atmel's SoC datasheets.
+- clocks : shall be the master clock phandle.
+ e.g. clocks = <&mck>;
+- name at id: device tree node describing a specific system clock.
+ * id: peripheral id.
+ * default-divisor (optional, only available for
+ "atmel,at91sam9x5-clk-peripheral"): sam9x5 and sama5d3 SoC provides
+ configurable peripheral clock divisor. If you define this property
+ (u32), the default divisor will be applied when enabling
+ peripheral clock. If not provided the peripheral clock is not divided.
+
+For example:
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk at 1 {
+ id = <1>;
+ default-divisor = <1>;
+ };
+
+ pioB_clk at 2 {
+ id = <2>;
+ default-divisor = <2>;
+ };
+ };
+
+
+Required properties for pll clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock phandle.
+- id : pll id
+ * 0 <=> plla
+ * 1 <=> pllb
+- characteristics : device tree node describing pll clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * input : minimum and maximum source clock frequency (two u32 fields).
+ e.g. input = <1 32000000>; <=> 1 to 32MHz.
+ * output : output frequency ranges.
+ * out: out field value for output frequency ranges.
+ * icpll (not available on some SoC): icpll field value for output
+ frequency ranges.
+
+For example:
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+Required properties for plldiv clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the plla clock phandle.
+
+For example:
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+Required properties for programmable clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the programmable clock id.
+ Peripheral ids are in atmel's SoC
+ datasheets.
+- clocks : shall be the programmable clock source phandles.
+ e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+- name at id: device tree node describing a specific prog clock.
+ * id: programmable clock id (register offset from PCKx register).
+
+For example:
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+ };
+
+
+Required properties for smd clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&plladiv>, <&utmi>;
+
+For example:
+ smd: smdck {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+Required properties for system clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the system clock id (bit used in SCER/SCDR register).
+- name at id: device tree node describing a specific system clock.
+ * id: system clock id (bit position in SCER/SCDR/SCSR registers).
+
+For example:
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck at 2 {
+ id = <2>;
+ };
+
+ uhpck at 6 {
+ id = <6>;
+ };
+
+ udpck at 7 {
+ id = <7>;
+ };
+ };
+
+
+Required properties for usb clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&pllb>;
+- divisors (only available for "atmel,at91rm9200-clk-usb"):
+ usb clock divisor table.
+ e.g. divisors = <1 2 4 0>;
+- usbs0-unused (only available for "atmel,at91sam9x5-clk-usb"):
+ Some SoC (sam9n12) use usb source 0 to disable the usb clock.
+
+For example:
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+
+Required properties for utmi clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock source phandle.
+
+For example:
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 12/42] ARM: at91: move to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:35 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:35 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes the old at91 clk implementation, and keep the
PMC initialization and sam9idle functions in pmc.c.
The at91_initialize function no longer initiliaze at91 clks: the new clk
registration process requires kzalloc which is not available when early_init
is called.
The clk registration is moved to at91_clk_init function which should be called
before timer_init (pit timer request at91 master clock).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/clock.c | 977 ------------------------------------------
arch/arm/mach-at91/clock.h | 49 ---
arch/arm/mach-at91/generic.h | 10 +-
arch/arm/mach-at91/pmc.c | 58 +++
arch/arm/mach-at91/setup.c | 36 +-
drivers/clk/Makefile | 1 +
7 files changed, 86 insertions(+), 1047 deletions(-)
delete mode 100644 arch/arm/mach-at91/clock.c
delete mode 100644 arch/arm/mach-at91/clock.h
create mode 100644 arch/arm/mach-at91/pmc.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 3b0a953..66c1796 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m :=
obj-n :=
obj- :=
-obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
+obj-$(CONFIG_AT91_PMC_UNIT) += pmc.o
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index cc263d0..0000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,977 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.c
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/clk/at91.h>
-
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-
-#include <asm/proc-fns.h>
-
-#include "clock.h"
-#include "generic.h"
-
-void __iomem *at91_pmc_base;
-EXPORT_SYMBOL_GPL(at91_pmc_base);
-
-/*
- * There's a lot more which can be done with clocks, including cpufreq
- * integration, slow clock mode support (for system suspend), letting
- * PLLB be used at other rates (on boards that don't need USB), etc.
- */
-
-#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
-#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
-
-
-/*
- * Chips have some kind of clocks : group them by functionality
- */
-#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-#define cpu_has_1056M_plla() (cpu_is_sama5d3())
-
-#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12())
-
-#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
-
-#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
- || cpu_is_at91sam9263() \
- || cpu_is_at91sam9rl())
-
-#define cpu_has_210M_plla() (cpu_is_at91sam9260())
-
-#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3()))
-
-#define cpu_has_upll() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-/* USB host HS & FS */
-#define cpu_has_uhp() (!cpu_is_at91sam9rl())
-
-/* USB device FS only */
-#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3()))
-
-#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-static LIST_HEAD(clocks);
-static DEFINE_SPINLOCK(clk_lock);
-
-static u32 at91_pllb_usb_init;
-
-/*
- * Four primary clock sources: two crystal oscillators (32K, main), and
- * two PLLs. PLLA usually runs the master clock; and PLLB must run at
- * 48 MHz (unless no USB function clocks are needed). The main clock and
- * both PLLs are turned off to run in "slow clock mode" (system suspend).
- */
-static struct clk clk32k = {
- .name = "clk32k",
- .rate_hz = AT91_SLOW_CLOCK,
- .users = 1, /* always on */
- .id = 0,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk main_clk = {
- .name = "main",
- .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
- .id = 1,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk plla = {
- .name = "plla",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
- .id = 2,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pllb_mode(struct clk *clk, int is_on)
-{
- u32 value;
-
- if (is_on) {
- is_on = AT91_PMC_LOCKB;
- value = at91_pllb_usb_init;
- } else
- value = 0;
-
- // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
- at91_pmc_write(AT91_CKGR_PLLBR, value);
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
-}
-
-static struct clk pllb = {
- .name = "pllb",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
- .mode = pllb_mode,
- .id = 3,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pmc_sys_mode(struct clk *clk, int is_on)
-{
- if (is_on)
- at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
-}
-
-static void pmc_uckr_mode(struct clk *clk, int is_on)
-{
- unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
-
- if (is_on) {
- is_on = AT91_PMC_LOCKU;
- at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
- } else
- at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
-}
-
-/* USB function clocks (PLLB must be 48 MHz) */
-static struct clk udpck = {
- .name = "udpck",
- .parent = &pllb,
- .mode = pmc_sys_mode,
-};
-struct clk utmi_clk = {
- .name = "utmi_clk",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
- .mode = pmc_uckr_mode,
- .type = CLK_TYPE_PLL,
-};
-static struct clk uhpck = {
- .name = "uhpck",
- /*.parent = ... we choose parent at runtime */
- .mode = pmc_sys_mode,
-};
-
-
-/*
- * The master clock is divided from the CPU clock (by 1-4). It's used for
- * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
- * (e.g baud rate generation). It's sourced from one of the primary clocks.
- */
-struct clk mck = {
- .name = "mck",
- .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
-};
-
-static void pmc_periph_mode(struct clk *clk, int is_on)
-{
- u32 regval = 0;
-
- /*
- * With sama5d3 devices, we are managing clock division so we have to
- * use the Peripheral Control Register introduced from at91sam9x5
- * devices.
- */
- if (cpu_is_sama5d3()) {
- regval |= AT91_PMC_PCR_CMD; /* write command */
- regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
- regval |= AT91_PMC_PCR_DIV(clk->div);
- if (is_on)
- regval |= AT91_PMC_PCR_EN; /* enable clock */
- at91_pmc_write(AT91_PMC_PCR, regval);
- } else {
- if (is_on)
- at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
- }
-}
-
-static struct clk __init *at91_css_to_clk(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_CSS_SLOW:
- return &clk32k;
- case AT91_PMC_CSS_MAIN:
- return &main_clk;
- case AT91_PMC_CSS_PLLA:
- return &plla;
- case AT91_PMC_CSS_PLLB:
- if (cpu_has_upll())
- /* CSS_PLLB == CSS_UPLL */
- return &utmi_clk;
- else if (cpu_has_pllb())
- return &pllb;
- break;
- /* alternate PMC: can use master clock */
- case AT91_PMC_CSS_MASTER:
- return &mck;
- }
-
- return NULL;
-}
-
-static int pmc_prescaler_divider(u32 reg)
-{
- if (cpu_has_alt_prescaler()) {
- return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
- } else {
- return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
- }
-}
-
-static void __clk_enable(struct clk *clk)
-{
- if (clk->parent)
- __clk_enable(clk->parent);
- if (clk->users++ == 0 && clk->mode)
- clk->mode(clk, 1);
-}
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_enable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
- BUG_ON(clk->users == 0);
- if (--clk->users == 0 && clk->mode)
- clk->mode(clk, 0);
- if (clk->parent)
- __clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_disable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long flags;
- unsigned long rate;
-
- spin_lock_irqsave(&clk_lock, flags);
- for (;;) {
- rate = clk->rate_hz;
- if (rate || !clk->parent)
- break;
- clk = clk->parent;
- }
- spin_unlock_irqrestore(&clk_lock, flags);
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
-
-/*
- * For now, only the programmable clocks support reparenting (MCK could
- * do this too, with care) or rate changing (the PLLs could do this too,
- * ditto MCK but that's more for cpufreq). Drivers may reparent to get
- * a better rate match; we don't.
- */
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long actual;
- unsigned long prev = ULONG_MAX;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual > rate)
- prev = actual;
-
- if (actual && actual <= rate) {
- if ((prev - rate) < (rate - actual)) {
- actual = prev;
- prescale--;
- }
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long prescale_offset, css_mask;
- unsigned long actual;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- if (clk->users)
- return -EBUSY;
-
- if (cpu_has_alt_prescaler()) {
- prescale_offset = PMC_ALT_PRES_OFFSET;
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- } else {
- prescale_offset = PMC_PRES_OFFSET;
- css_mask = AT91_PMC_CSS;
- }
-
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual && actual <= rate) {
- u32 pckr;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- pckr &= css_mask; /* keep clock selection */
- pckr |= prescale << prescale_offset;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
- clk->rate_hz = actual;
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- unsigned long flags;
-
- if (clk->users)
- return -EBUSY;
- if (!clk_is_primary(parent) || !clk_is_programmable(clk))
- return -EINVAL;
-
- if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
- return -EINVAL;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- clk->rate_hz = parent->rate_hz;
- clk->parent = parent;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* establish PCK0..PCKN parentage and rate */
-static void __init init_programmable_clock(struct clk *clk)
-{
- struct clk *parent;
- u32 pckr;
- unsigned int css_mask;
-
- if (cpu_has_alt_prescaler())
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- else
- css_mask = AT91_PMC_CSS;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- parent = at91_css_to_clk(pckr & css_mask);
- clk->parent = parent;
- clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
-}
-
-#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_DEBUG_FS
-
-static int at91_clk_show(struct seq_file *s, void *unused)
-{
- u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
- struct clk *clk;
-
- scsr = at91_pmc_read(AT91_PMC_SCSR);
- pcsr = at91_pmc_read(AT91_PMC_PCSR);
- if (cpu_is_sama5d3())
- pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
- sr = at91_pmc_read(AT91_PMC_SR);
- seq_printf(s, "SCSR = %8x\n", scsr);
- seq_printf(s, "PCSR = %8x\n", pcsr);
- if (cpu_is_sama5d3())
- seq_printf(s, "PCSR1 = %8x\n", pcsr1);
- seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
- seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
- seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_pllb())
- seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
- if (cpu_has_utmi()) {
- uckr = at91_pmc_read(AT91_CKGR_UCKR);
- seq_printf(s, "UCKR = %8x\n", uckr);
- }
- seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
- if (cpu_has_upll() || cpu_is_at91sam9n12())
- seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
- seq_printf(s, "SR = %8x\n", sr);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(clk, &clocks, node) {
- char *state;
-
- if (clk->mode == pmc_sys_mode) {
- state = (scsr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- state = (pcsr1 & pmc_mask) ? "on" : "off";
- else
- state = (pcsr & pmc_mask) ? "on" : "off";
- } else {
- state = (pcsr & clk->pmc_mask) ? "on" : "off";
- }
- } else if (clk->mode == pmc_uckr_mode) {
- state = (uckr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->pmc_mask) {
- state = (sr & clk->pmc_mask) ? "on" : "off";
- } else if (clk == &clk32k || clk == &main_clk) {
- state = "on";
- } else {
- state = "";
- }
-
- seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
- clk->name, clk->users, state, clk_get_rate(clk),
- clk->parent ? clk->parent->name : "");
- }
- return 0;
-}
-
-static int at91_clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, at91_clk_show, NULL);
-}
-
-static const struct file_operations at91_clk_operations = {
- .open = at91_clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init at91_clk_debugfs_init(void)
-{
- /* /sys/kernel/debug/at91_clk */
- (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
-
- return 0;
-}
-postcore_initcall(at91_clk_debugfs_init);
-
-#endif
-
-/*------------------------------------------------------------------------*/
-
-/* Register a new clock */
-static void __init at91_clk_add(struct clk *clk)
-{
- list_add_tail(&clk->node, &clocks);
-
- clk->cl.con_id = clk->name;
- clk->cl.clk = clk;
- clkdev_add(&clk->cl);
-}
-
-int __init clk_register(struct clk *clk)
-{
- if (clk_is_peripheral(clk)) {
- if (!clk->parent)
- clk->parent = &mck;
- if (cpu_is_sama5d3())
- clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
- 1 << clk->div);
- clk->mode = pmc_periph_mode;
- }
- else if (clk_is_sys(clk)) {
- clk->parent = &mck;
- clk->mode = pmc_sys_mode;
- }
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
- else if (clk_is_programmable(clk)) {
- clk->mode = pmc_sys_mode;
- init_programmable_clock(clk);
- }
-#endif
-
- at91_clk_add(clk);
-
- return 0;
-}
-
-/*------------------------------------------------------------------------*/
-
-static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- if (cpu_is_sama5d3())
- mul = AT91_PMC3_MUL_GET(reg);
- else
- mul = AT91_PMC_MUL_GET(reg);
-
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
-{
- if (pll == &pllb && (reg & AT91_PMC_USB96M))
- return freq / 2;
- else if (pll == &utmi_clk || cpu_is_at91sam9n12())
- return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
- else
- return freq;
-}
-
-static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (cpu_is_at91sam9g20() && input < 2000000)
- continue;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (cpu_is_at91sam9g20() && mul > 63)
- continue;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-
-static struct clk *const standard_pmc_clocks[] __initconst = {
- /* four primary clocks */
- &clk32k,
- &main_clk,
- &plla,
-
- /* MCK */
- &mck
-};
-
-/* PLLB generated USB full speed clock init */
-static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
-{
- unsigned int reg;
-
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- uhpck.parent = &pllb;
-
- reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
- pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
- if (cpu_is_at91rm9200()) {
- reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
- uhpck.pmc_mask = AT91RM9200_PMC_UHP;
- udpck.pmc_mask = AT91RM9200_PMC_UDP;
- at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
- } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
- cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
- cpu_is_at91sam9g10()) {
- reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- udpck.pmc_mask = AT91SAM926x_PMC_UDP;
- } else if (cpu_is_at91sam9n12()) {
- /* Divider for USB clock is in USB clock register for 9n12 */
- reg = AT91_PMC_USBS_PLLB;
-
- /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
- reg |= AT91_PMC_OHCIUSBDIV_2;
- at91_pmc_write(AT91_PMC_USB, reg);
-
- /* Still setup masks */
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- udpck.pmc_mask = AT91SAM926x_PMC_UDP;
- }
- at91_pmc_write(AT91_CKGR_PLLBR, 0);
-
- udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
- uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
-}
-
-/* UPLL generated USB full speed clock init */
-static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
-{
- /*
- * USB clock init: choose 480 MHz from UPLL,
- */
- unsigned int usbr = AT91_PMC_USBS_UPLL;
-
- /* Setup divider by 10 to reach 48 MHz */
- usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
-
- at91_pmc_write(AT91_PMC_USB, usbr);
-
- /* Now set uhpck values */
- uhpck.parent = &utmi_clk;
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
-}
-
-static int __init at91_pmc_init(unsigned long main_clock)
-{
- unsigned tmp, freq, mckr;
- int i;
- int pll_overclock = false;
-
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = at91_pmc_read(AT91_CKGR_MCFR);
- } while (!(tmp & AT91_PMC_MAINRDY));
- main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
- }
- main_clk.rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_1056M_plla()) {
- if (plla.rate_hz > 1056000000)
- pll_overclock = true;
- } else if (cpu_has_800M_plla()) {
- if (plla.rate_hz > 800000000)
- pll_overclock = true;
- } else if (cpu_has_300M_plla()) {
- if (plla.rate_hz > 300000000)
- pll_overclock = true;
- } else if (cpu_has_240M_plla()) {
- if (plla.rate_hz > 240000000)
- pll_overclock = true;
- } else if (cpu_has_210M_plla()) {
- if (plla.rate_hz > 210000000)
- pll_overclock = true;
- } else {
- if (plla.rate_hz > 209000000)
- pll_overclock = true;
- }
- if (pll_overclock)
- pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
- if (cpu_has_plladiv2()) {
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
- }
-
- if (!cpu_has_pllb() && cpu_has_upll()) {
- /* setup UTMI clock as the fourth primary clock
- * (instead of pllb) */
- utmi_clk.type |= CLK_TYPE_PRIMARY;
- utmi_clk.id = 3;
- }
-
-
- /*
- * USB HS clock init
- */
- if (cpu_has_utmi()) {
- /*
- * multiplier is hard-wired to 40
- * (obtain the USB High Speed 480 MHz when input is 12 MHz)
- */
- utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
-
- /* UTMI bias and PLL are managed at the same time */
- if (cpu_has_upll())
- utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
- }
-
- /*
- * USB FS clock init
- */
- if (cpu_has_pllb())
- at91_pllb_usbfs_clock_init(main_clock);
- if (cpu_has_upll())
- /* assumes that we choose UPLL for USB and not PLLA */
- at91_upll_usbfs_clock_init(main_clock);
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
- freq = mck.parent->rate_hz;
- freq /= pmc_prescaler_divider(mckr); /* prescale */
- if (cpu_is_at91rm9200()) {
- mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else if (cpu_is_at91sam9g20()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
- freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- if (mckr & AT91_PMC_PDIV)
- freq /= 2; /* processor clock division */
- } else if (cpu_has_mdiv3()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
- freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else {
- mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- }
-
- if (cpu_has_alt_prescaler()) {
- /* Programmable clocks can use MCK */
- mck.type |= CLK_TYPE_PRIMARY;
- mck.id = 4;
- }
-
- /* Register the PMC's standard clocks */
- for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
- at91_clk_add(standard_pmc_clocks[i]);
-
- if (cpu_has_pllb())
- at91_clk_add(&pllb);
-
- if (cpu_has_uhp())
- at91_clk_add(&uhpck);
-
- if (cpu_has_udpfs())
- at91_clk_add(&udpck);
-
- if (cpu_has_utmi())
- at91_clk_add(&utmi_clk);
-
- /* MCK and CPU clock are "always on" */
- clk_enable(&mck);
-
- printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
- freq / 1000000, (unsigned) mck.rate_hz / 1000000,
- (unsigned) main_clock / 1000000,
- ((unsigned) main_clock % 1000000) / 1000);
-
- return 0;
-}
-
-#if defined(CONFIG_OF)
-static struct of_device_id pmc_ids[] = {
- { .compatible = "atmel,at91rm9200-pmc" },
- { /*sentinel*/ }
-};
-
-static struct of_device_id osc_ids[] = {
- { .compatible = "atmel,osc" },
- { /*sentinel*/ }
-};
-
-int __init at91_dt_clock_init(void)
-{
- struct device_node *np;
- u32 main_clock = 0;
-
- np = of_find_matching_node(NULL, pmc_ids);
- if (!np)
- panic("unable to find compatible pmc node in dtb\n");
-
- at91_pmc_base = of_iomap(np, 0);
- if (!at91_pmc_base)
- panic("unable to map pmc cpu registers\n");
-
- of_node_put(np);
-
- /* retrieve the freqency of fixed clocks from device tree */
- np = of_find_matching_node(NULL, osc_ids);
- if (np) {
- u32 rate;
- if (!of_property_read_u32(np, "clock-frequency", &rate))
- main_clock = rate;
- }
-
- of_node_put(np);
-
- return at91_pmc_init(main_clock);
-}
-#endif
-
-int __init at91_clock_init(unsigned long main_clock)
-{
- at91_pmc_base = ioremap(AT91_PMC, 256);
- if (!at91_pmc_base)
- panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
- return at91_pmc_init(main_clock);
-}
-
-/*
- * Several unused clocks may be active. Turn them off.
- */
-static int __init at91_clock_reset(void)
-{
- unsigned long pcdr = 0;
- unsigned long pcdr1 = 0;
- unsigned long scdr = 0;
- struct clk *clk;
-
- list_for_each_entry(clk, &clocks, node) {
- if (clk->users > 0)
- continue;
-
- if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- pcdr1 |= pmc_mask;
- else
- pcdr |= pmc_mask;
- } else
- pcdr |= clk->pmc_mask;
- }
-
- if (clk->mode == pmc_sys_mode)
- scdr |= clk->pmc_mask;
-
- pr_debug("Clocks: disable unused %s\n", clk->name);
- }
-
- at91_pmc_write(AT91_PMC_SCDR, scdr);
- if (cpu_is_sama5d3())
- at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
-
- return 0;
-}
-late_initcall(at91_clock_reset);
-
-void at91sam9_idle(void)
-{
- at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
- cpu_do_idle();
-}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39b..0000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clkdev.h>
-
-#define CLK_TYPE_PRIMARY 0x1
-#define CLK_TYPE_PLL 0x2
-#define CLK_TYPE_PROGRAMMABLE 0x4
-#define CLK_TYPE_PERIPHERAL 0x8
-#define CLK_TYPE_SYSTEM 0x10
-
-
-struct clk {
- struct list_head node;
- const char *name; /* unique clock name */
- struct clk_lookup cl;
- unsigned long rate_hz;
- unsigned div; /* parent clock divider */
- struct clk *parent;
- unsigned pid; /* peripheral ID */
- u32 pmc_mask;
- void (*mode)(struct clk *, int);
- unsigned id:3; /* PCK0..4, or 32k/main/a/b */
- unsigned type; /* clock type */
- u16 users;
-};
-
-
-extern int __init clk_register(struct clk *clk);
-extern struct clk mck;
-extern struct clk utmi_clk;
-
-#define CLKDEV_CON_ID(_id, _clk) \
- { \
- .con_id = _id, \
- .clk = _clk, \
- }
-
-#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
- { \
- .con_id = _con_id, \
- .dev_id = _dev_id, \
- .clk = _clk, \
- }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index dc6e2f5..684befb 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -19,10 +19,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
/* Processors */
extern void __init at91rm9200_set_type(int type);
-extern void __init at91_initialize(unsigned long main_clock);
+extern void __init at91_initialize(void);
+extern void __init at91_clk_init(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void);
+extern void __init at91_dt_clk_init(void);
/* Interrupts */
extern void __init at91_init_irq_default(void);
@@ -45,10 +47,10 @@ extern void at91x40_timer_init(void);
/* Clocks */
#ifdef CONFIG_AT91_PMC_UNIT
-extern int __init at91_clock_init(unsigned long main_clock);
-extern int __init at91_dt_clock_init(void);
+extern int __init at91_pmc_init(void);
+extern int __init at91_dt_pmc_init(void);
#else
-static int inline at91_clock_init(unsigned long main_clock) { return 0; }
+static int inline at91_pmc_init() { return 0; }
#endif
struct device;
diff --git a/arch/arm/mach-at91/pmc.c b/arch/arm/mach-at91/pmc.c
new file mode 100644
index 0000000..2a8a6cf
--- /dev/null
+++ b/arch/arm/mach-at91/pmc.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/mach-at91/pmc.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/at91.h>
+
+#include <asm/io.h>
+#include <asm/proc-fns.h>
+
+void __iomem *at91_pmc_base;
+EXPORT_SYMBOL_GPL(at91_pmc_base);
+
+void at91sam9_idle(void)
+{
+ at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+ cpu_do_idle();
+}
+
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+ { .compatible = "atmel,at91rm9200-pmc" },
+ { /*sentinel*/ }
+};
+
+int __init at91_dt_pmc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, pmc_ids);
+ if (!np)
+ panic("unable to find compatible pmc node in dtb\n");
+
+ at91_pmc_base = of_iomap(np, 0);
+ if (!at91_pmc_base)
+ panic("unable to map pmc cpu registers\n");
+
+ of_node_put(np);
+
+ return 0;
+}
+#endif
+
+int __init at91_pmc_init(void)
+{
+ at91_pmc_base = ioremap(AT91_PMC, 256);
+ if (!at91_pmc_base)
+ panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index de3c519..9a8d58c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -479,41 +479,45 @@ void __init at91rm9200_dt_initialize(void)
{
at91_dt_ramc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
at91_boot_soc.init();
}
-void __init at91_dt_initialize(void)
+void __init at91_dt_initialize()
{
at91_dt_rstc();
at91_dt_ramc();
at91_dt_shdwc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
if (at91_boot_soc.init)
at91_boot_soc.init();
}
-#endif
-void __init at91_initialize(unsigned long main_clock)
+void __init at91_dt_clk_init(void)
{
- at91_boot_soc.ioremap_registers();
+ of_clk_init(NULL);
+}
+#endif
- /* Init clock subsystem */
- at91_clock_init(main_clock);
+void __init at91_clk_init(unsigned long main_clock)
+{
+ clk_register_fixed_rate(NULL, "clk32k", NULL, CLK_IS_ROOT,
+ AT91_SLOW_CLOCK);
+ at91_clk_register_main("main", "clk32k", main_clock);
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();
+}
+
+void __init at91_initialize(void)
+{
+ at91_boot_soc.ioremap_registers();
+
+ /* Init clock subsystem */
+ at91_pmc_init();
at91_boot_soc.init();
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..8c91671 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_AT91) += at91/
obj-$(CONFIG_X86) += x86/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 12/42] ARM: at91: move to common clk framework
@ 2013-07-17 14:35 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:35 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes the old at91 clk implementation, and keep the
PMC initialization and sam9idle functions in pmc.c.
The at91_initialize function no longer initiliaze at91 clks: the new clk
registration process requires kzalloc which is not available when early_init
is called.
The clk registration is moved to at91_clk_init function which should be called
before timer_init (pit timer request at91 master clock).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/clock.c | 977 ------------------------------------------
arch/arm/mach-at91/clock.h | 49 ---
arch/arm/mach-at91/generic.h | 10 +-
arch/arm/mach-at91/pmc.c | 58 +++
arch/arm/mach-at91/setup.c | 36 +-
drivers/clk/Makefile | 1 +
7 files changed, 86 insertions(+), 1047 deletions(-)
delete mode 100644 arch/arm/mach-at91/clock.c
delete mode 100644 arch/arm/mach-at91/clock.h
create mode 100644 arch/arm/mach-at91/pmc.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 3b0a953..66c1796 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m :=
obj-n :=
obj- :=
-obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
+obj-$(CONFIG_AT91_PMC_UNIT) += pmc.o
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index cc263d0..0000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,977 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.c
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/clk/at91.h>
-
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-
-#include <asm/proc-fns.h>
-
-#include "clock.h"
-#include "generic.h"
-
-void __iomem *at91_pmc_base;
-EXPORT_SYMBOL_GPL(at91_pmc_base);
-
-/*
- * There's a lot more which can be done with clocks, including cpufreq
- * integration, slow clock mode support (for system suspend), letting
- * PLLB be used at other rates (on boards that don't need USB), etc.
- */
-
-#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
-#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
-
-
-/*
- * Chips have some kind of clocks : group them by functionality
- */
-#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-#define cpu_has_1056M_plla() (cpu_is_sama5d3())
-
-#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12())
-
-#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
-
-#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
- || cpu_is_at91sam9263() \
- || cpu_is_at91sam9rl())
-
-#define cpu_has_210M_plla() (cpu_is_at91sam9260())
-
-#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3()))
-
-#define cpu_has_upll() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-/* USB host HS & FS */
-#define cpu_has_uhp() (!cpu_is_at91sam9rl())
-
-/* USB device FS only */
-#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3()))
-
-#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-static LIST_HEAD(clocks);
-static DEFINE_SPINLOCK(clk_lock);
-
-static u32 at91_pllb_usb_init;
-
-/*
- * Four primary clock sources: two crystal oscillators (32K, main), and
- * two PLLs. PLLA usually runs the master clock; and PLLB must run at
- * 48 MHz (unless no USB function clocks are needed). The main clock and
- * both PLLs are turned off to run in "slow clock mode" (system suspend).
- */
-static struct clk clk32k = {
- .name = "clk32k",
- .rate_hz = AT91_SLOW_CLOCK,
- .users = 1, /* always on */
- .id = 0,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk main_clk = {
- .name = "main",
- .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
- .id = 1,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk plla = {
- .name = "plla",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
- .id = 2,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pllb_mode(struct clk *clk, int is_on)
-{
- u32 value;
-
- if (is_on) {
- is_on = AT91_PMC_LOCKB;
- value = at91_pllb_usb_init;
- } else
- value = 0;
-
- // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
- at91_pmc_write(AT91_CKGR_PLLBR, value);
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
-}
-
-static struct clk pllb = {
- .name = "pllb",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
- .mode = pllb_mode,
- .id = 3,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pmc_sys_mode(struct clk *clk, int is_on)
-{
- if (is_on)
- at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
-}
-
-static void pmc_uckr_mode(struct clk *clk, int is_on)
-{
- unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
-
- if (is_on) {
- is_on = AT91_PMC_LOCKU;
- at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
- } else
- at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
-}
-
-/* USB function clocks (PLLB must be 48 MHz) */
-static struct clk udpck = {
- .name = "udpck",
- .parent = &pllb,
- .mode = pmc_sys_mode,
-};
-struct clk utmi_clk = {
- .name = "utmi_clk",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
- .mode = pmc_uckr_mode,
- .type = CLK_TYPE_PLL,
-};
-static struct clk uhpck = {
- .name = "uhpck",
- /*.parent = ... we choose parent at runtime */
- .mode = pmc_sys_mode,
-};
-
-
-/*
- * The master clock is divided from the CPU clock (by 1-4). It's used for
- * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
- * (e.g baud rate generation). It's sourced from one of the primary clocks.
- */
-struct clk mck = {
- .name = "mck",
- .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
-};
-
-static void pmc_periph_mode(struct clk *clk, int is_on)
-{
- u32 regval = 0;
-
- /*
- * With sama5d3 devices, we are managing clock division so we have to
- * use the Peripheral Control Register introduced from at91sam9x5
- * devices.
- */
- if (cpu_is_sama5d3()) {
- regval |= AT91_PMC_PCR_CMD; /* write command */
- regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
- regval |= AT91_PMC_PCR_DIV(clk->div);
- if (is_on)
- regval |= AT91_PMC_PCR_EN; /* enable clock */
- at91_pmc_write(AT91_PMC_PCR, regval);
- } else {
- if (is_on)
- at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
- }
-}
-
-static struct clk __init *at91_css_to_clk(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_CSS_SLOW:
- return &clk32k;
- case AT91_PMC_CSS_MAIN:
- return &main_clk;
- case AT91_PMC_CSS_PLLA:
- return &plla;
- case AT91_PMC_CSS_PLLB:
- if (cpu_has_upll())
- /* CSS_PLLB == CSS_UPLL */
- return &utmi_clk;
- else if (cpu_has_pllb())
- return &pllb;
- break;
- /* alternate PMC: can use master clock */
- case AT91_PMC_CSS_MASTER:
- return &mck;
- }
-
- return NULL;
-}
-
-static int pmc_prescaler_divider(u32 reg)
-{
- if (cpu_has_alt_prescaler()) {
- return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
- } else {
- return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
- }
-}
-
-static void __clk_enable(struct clk *clk)
-{
- if (clk->parent)
- __clk_enable(clk->parent);
- if (clk->users++ == 0 && clk->mode)
- clk->mode(clk, 1);
-}
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_enable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
- BUG_ON(clk->users == 0);
- if (--clk->users == 0 && clk->mode)
- clk->mode(clk, 0);
- if (clk->parent)
- __clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_disable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long flags;
- unsigned long rate;
-
- spin_lock_irqsave(&clk_lock, flags);
- for (;;) {
- rate = clk->rate_hz;
- if (rate || !clk->parent)
- break;
- clk = clk->parent;
- }
- spin_unlock_irqrestore(&clk_lock, flags);
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
-
-/*
- * For now, only the programmable clocks support reparenting (MCK could
- * do this too, with care) or rate changing (the PLLs could do this too,
- * ditto MCK but that's more for cpufreq). Drivers may reparent to get
- * a better rate match; we don't.
- */
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long actual;
- unsigned long prev = ULONG_MAX;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual > rate)
- prev = actual;
-
- if (actual && actual <= rate) {
- if ((prev - rate) < (rate - actual)) {
- actual = prev;
- prescale--;
- }
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long prescale_offset, css_mask;
- unsigned long actual;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- if (clk->users)
- return -EBUSY;
-
- if (cpu_has_alt_prescaler()) {
- prescale_offset = PMC_ALT_PRES_OFFSET;
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- } else {
- prescale_offset = PMC_PRES_OFFSET;
- css_mask = AT91_PMC_CSS;
- }
-
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual && actual <= rate) {
- u32 pckr;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- pckr &= css_mask; /* keep clock selection */
- pckr |= prescale << prescale_offset;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
- clk->rate_hz = actual;
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- unsigned long flags;
-
- if (clk->users)
- return -EBUSY;
- if (!clk_is_primary(parent) || !clk_is_programmable(clk))
- return -EINVAL;
-
- if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
- return -EINVAL;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- clk->rate_hz = parent->rate_hz;
- clk->parent = parent;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* establish PCK0..PCKN parentage and rate */
-static void __init init_programmable_clock(struct clk *clk)
-{
- struct clk *parent;
- u32 pckr;
- unsigned int css_mask;
-
- if (cpu_has_alt_prescaler())
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- else
- css_mask = AT91_PMC_CSS;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- parent = at91_css_to_clk(pckr & css_mask);
- clk->parent = parent;
- clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
-}
-
-#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_DEBUG_FS
-
-static int at91_clk_show(struct seq_file *s, void *unused)
-{
- u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
- struct clk *clk;
-
- scsr = at91_pmc_read(AT91_PMC_SCSR);
- pcsr = at91_pmc_read(AT91_PMC_PCSR);
- if (cpu_is_sama5d3())
- pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
- sr = at91_pmc_read(AT91_PMC_SR);
- seq_printf(s, "SCSR = %8x\n", scsr);
- seq_printf(s, "PCSR = %8x\n", pcsr);
- if (cpu_is_sama5d3())
- seq_printf(s, "PCSR1 = %8x\n", pcsr1);
- seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
- seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
- seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_pllb())
- seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
- if (cpu_has_utmi()) {
- uckr = at91_pmc_read(AT91_CKGR_UCKR);
- seq_printf(s, "UCKR = %8x\n", uckr);
- }
- seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
- if (cpu_has_upll() || cpu_is_at91sam9n12())
- seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
- seq_printf(s, "SR = %8x\n", sr);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(clk, &clocks, node) {
- char *state;
-
- if (clk->mode == pmc_sys_mode) {
- state = (scsr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- state = (pcsr1 & pmc_mask) ? "on" : "off";
- else
- state = (pcsr & pmc_mask) ? "on" : "off";
- } else {
- state = (pcsr & clk->pmc_mask) ? "on" : "off";
- }
- } else if (clk->mode == pmc_uckr_mode) {
- state = (uckr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->pmc_mask) {
- state = (sr & clk->pmc_mask) ? "on" : "off";
- } else if (clk == &clk32k || clk == &main_clk) {
- state = "on";
- } else {
- state = "";
- }
-
- seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
- clk->name, clk->users, state, clk_get_rate(clk),
- clk->parent ? clk->parent->name : "");
- }
- return 0;
-}
-
-static int at91_clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, at91_clk_show, NULL);
-}
-
-static const struct file_operations at91_clk_operations = {
- .open = at91_clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init at91_clk_debugfs_init(void)
-{
- /* /sys/kernel/debug/at91_clk */
- (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
-
- return 0;
-}
-postcore_initcall(at91_clk_debugfs_init);
-
-#endif
-
-/*------------------------------------------------------------------------*/
-
-/* Register a new clock */
-static void __init at91_clk_add(struct clk *clk)
-{
- list_add_tail(&clk->node, &clocks);
-
- clk->cl.con_id = clk->name;
- clk->cl.clk = clk;
- clkdev_add(&clk->cl);
-}
-
-int __init clk_register(struct clk *clk)
-{
- if (clk_is_peripheral(clk)) {
- if (!clk->parent)
- clk->parent = &mck;
- if (cpu_is_sama5d3())
- clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
- 1 << clk->div);
- clk->mode = pmc_periph_mode;
- }
- else if (clk_is_sys(clk)) {
- clk->parent = &mck;
- clk->mode = pmc_sys_mode;
- }
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
- else if (clk_is_programmable(clk)) {
- clk->mode = pmc_sys_mode;
- init_programmable_clock(clk);
- }
-#endif
-
- at91_clk_add(clk);
-
- return 0;
-}
-
-/*------------------------------------------------------------------------*/
-
-static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- if (cpu_is_sama5d3())
- mul = AT91_PMC3_MUL_GET(reg);
- else
- mul = AT91_PMC_MUL_GET(reg);
-
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
-{
- if (pll == &pllb && (reg & AT91_PMC_USB96M))
- return freq / 2;
- else if (pll == &utmi_clk || cpu_is_at91sam9n12())
- return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
- else
- return freq;
-}
-
-static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (cpu_is_at91sam9g20() && input < 2000000)
- continue;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (cpu_is_at91sam9g20() && mul > 63)
- continue;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-
-static struct clk *const standard_pmc_clocks[] __initconst = {
- /* four primary clocks */
- &clk32k,
- &main_clk,
- &plla,
-
- /* MCK */
- &mck
-};
-
-/* PLLB generated USB full speed clock init */
-static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
-{
- unsigned int reg;
-
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- uhpck.parent = &pllb;
-
- reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
- pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
- if (cpu_is_at91rm9200()) {
- reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
- uhpck.pmc_mask = AT91RM9200_PMC_UHP;
- udpck.pmc_mask = AT91RM9200_PMC_UDP;
- at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
- } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
- cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
- cpu_is_at91sam9g10()) {
- reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- udpck.pmc_mask = AT91SAM926x_PMC_UDP;
- } else if (cpu_is_at91sam9n12()) {
- /* Divider for USB clock is in USB clock register for 9n12 */
- reg = AT91_PMC_USBS_PLLB;
-
- /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
- reg |= AT91_PMC_OHCIUSBDIV_2;
- at91_pmc_write(AT91_PMC_USB, reg);
-
- /* Still setup masks */
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- udpck.pmc_mask = AT91SAM926x_PMC_UDP;
- }
- at91_pmc_write(AT91_CKGR_PLLBR, 0);
-
- udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
- uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
-}
-
-/* UPLL generated USB full speed clock init */
-static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
-{
- /*
- * USB clock init: choose 480 MHz from UPLL,
- */
- unsigned int usbr = AT91_PMC_USBS_UPLL;
-
- /* Setup divider by 10 to reach 48 MHz */
- usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
-
- at91_pmc_write(AT91_PMC_USB, usbr);
-
- /* Now set uhpck values */
- uhpck.parent = &utmi_clk;
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
-}
-
-static int __init at91_pmc_init(unsigned long main_clock)
-{
- unsigned tmp, freq, mckr;
- int i;
- int pll_overclock = false;
-
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = at91_pmc_read(AT91_CKGR_MCFR);
- } while (!(tmp & AT91_PMC_MAINRDY));
- main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
- }
- main_clk.rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_1056M_plla()) {
- if (plla.rate_hz > 1056000000)
- pll_overclock = true;
- } else if (cpu_has_800M_plla()) {
- if (plla.rate_hz > 800000000)
- pll_overclock = true;
- } else if (cpu_has_300M_plla()) {
- if (plla.rate_hz > 300000000)
- pll_overclock = true;
- } else if (cpu_has_240M_plla()) {
- if (plla.rate_hz > 240000000)
- pll_overclock = true;
- } else if (cpu_has_210M_plla()) {
- if (plla.rate_hz > 210000000)
- pll_overclock = true;
- } else {
- if (plla.rate_hz > 209000000)
- pll_overclock = true;
- }
- if (pll_overclock)
- pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
- if (cpu_has_plladiv2()) {
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
- }
-
- if (!cpu_has_pllb() && cpu_has_upll()) {
- /* setup UTMI clock as the fourth primary clock
- * (instead of pllb) */
- utmi_clk.type |= CLK_TYPE_PRIMARY;
- utmi_clk.id = 3;
- }
-
-
- /*
- * USB HS clock init
- */
- if (cpu_has_utmi()) {
- /*
- * multiplier is hard-wired to 40
- * (obtain the USB High Speed 480 MHz when input is 12 MHz)
- */
- utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
-
- /* UTMI bias and PLL are managed at the same time */
- if (cpu_has_upll())
- utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
- }
-
- /*
- * USB FS clock init
- */
- if (cpu_has_pllb())
- at91_pllb_usbfs_clock_init(main_clock);
- if (cpu_has_upll())
- /* assumes that we choose UPLL for USB and not PLLA */
- at91_upll_usbfs_clock_init(main_clock);
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
- freq = mck.parent->rate_hz;
- freq /= pmc_prescaler_divider(mckr); /* prescale */
- if (cpu_is_at91rm9200()) {
- mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else if (cpu_is_at91sam9g20()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
- freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- if (mckr & AT91_PMC_PDIV)
- freq /= 2; /* processor clock division */
- } else if (cpu_has_mdiv3()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
- freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else {
- mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- }
-
- if (cpu_has_alt_prescaler()) {
- /* Programmable clocks can use MCK */
- mck.type |= CLK_TYPE_PRIMARY;
- mck.id = 4;
- }
-
- /* Register the PMC's standard clocks */
- for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
- at91_clk_add(standard_pmc_clocks[i]);
-
- if (cpu_has_pllb())
- at91_clk_add(&pllb);
-
- if (cpu_has_uhp())
- at91_clk_add(&uhpck);
-
- if (cpu_has_udpfs())
- at91_clk_add(&udpck);
-
- if (cpu_has_utmi())
- at91_clk_add(&utmi_clk);
-
- /* MCK and CPU clock are "always on" */
- clk_enable(&mck);
-
- printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
- freq / 1000000, (unsigned) mck.rate_hz / 1000000,
- (unsigned) main_clock / 1000000,
- ((unsigned) main_clock % 1000000) / 1000);
-
- return 0;
-}
-
-#if defined(CONFIG_OF)
-static struct of_device_id pmc_ids[] = {
- { .compatible = "atmel,at91rm9200-pmc" },
- { /*sentinel*/ }
-};
-
-static struct of_device_id osc_ids[] = {
- { .compatible = "atmel,osc" },
- { /*sentinel*/ }
-};
-
-int __init at91_dt_clock_init(void)
-{
- struct device_node *np;
- u32 main_clock = 0;
-
- np = of_find_matching_node(NULL, pmc_ids);
- if (!np)
- panic("unable to find compatible pmc node in dtb\n");
-
- at91_pmc_base = of_iomap(np, 0);
- if (!at91_pmc_base)
- panic("unable to map pmc cpu registers\n");
-
- of_node_put(np);
-
- /* retrieve the freqency of fixed clocks from device tree */
- np = of_find_matching_node(NULL, osc_ids);
- if (np) {
- u32 rate;
- if (!of_property_read_u32(np, "clock-frequency", &rate))
- main_clock = rate;
- }
-
- of_node_put(np);
-
- return at91_pmc_init(main_clock);
-}
-#endif
-
-int __init at91_clock_init(unsigned long main_clock)
-{
- at91_pmc_base = ioremap(AT91_PMC, 256);
- if (!at91_pmc_base)
- panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
- return at91_pmc_init(main_clock);
-}
-
-/*
- * Several unused clocks may be active. Turn them off.
- */
-static int __init at91_clock_reset(void)
-{
- unsigned long pcdr = 0;
- unsigned long pcdr1 = 0;
- unsigned long scdr = 0;
- struct clk *clk;
-
- list_for_each_entry(clk, &clocks, node) {
- if (clk->users > 0)
- continue;
-
- if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- pcdr1 |= pmc_mask;
- else
- pcdr |= pmc_mask;
- } else
- pcdr |= clk->pmc_mask;
- }
-
- if (clk->mode == pmc_sys_mode)
- scdr |= clk->pmc_mask;
-
- pr_debug("Clocks: disable unused %s\n", clk->name);
- }
-
- at91_pmc_write(AT91_PMC_SCDR, scdr);
- if (cpu_is_sama5d3())
- at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
-
- return 0;
-}
-late_initcall(at91_clock_reset);
-
-void at91sam9_idle(void)
-{
- at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
- cpu_do_idle();
-}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39b..0000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clkdev.h>
-
-#define CLK_TYPE_PRIMARY 0x1
-#define CLK_TYPE_PLL 0x2
-#define CLK_TYPE_PROGRAMMABLE 0x4
-#define CLK_TYPE_PERIPHERAL 0x8
-#define CLK_TYPE_SYSTEM 0x10
-
-
-struct clk {
- struct list_head node;
- const char *name; /* unique clock name */
- struct clk_lookup cl;
- unsigned long rate_hz;
- unsigned div; /* parent clock divider */
- struct clk *parent;
- unsigned pid; /* peripheral ID */
- u32 pmc_mask;
- void (*mode)(struct clk *, int);
- unsigned id:3; /* PCK0..4, or 32k/main/a/b */
- unsigned type; /* clock type */
- u16 users;
-};
-
-
-extern int __init clk_register(struct clk *clk);
-extern struct clk mck;
-extern struct clk utmi_clk;
-
-#define CLKDEV_CON_ID(_id, _clk) \
- { \
- .con_id = _id, \
- .clk = _clk, \
- }
-
-#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
- { \
- .con_id = _con_id, \
- .dev_id = _dev_id, \
- .clk = _clk, \
- }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index dc6e2f5..684befb 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -19,10 +19,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
/* Processors */
extern void __init at91rm9200_set_type(int type);
-extern void __init at91_initialize(unsigned long main_clock);
+extern void __init at91_initialize(void);
+extern void __init at91_clk_init(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void);
+extern void __init at91_dt_clk_init(void);
/* Interrupts */
extern void __init at91_init_irq_default(void);
@@ -45,10 +47,10 @@ extern void at91x40_timer_init(void);
/* Clocks */
#ifdef CONFIG_AT91_PMC_UNIT
-extern int __init at91_clock_init(unsigned long main_clock);
-extern int __init at91_dt_clock_init(void);
+extern int __init at91_pmc_init(void);
+extern int __init at91_dt_pmc_init(void);
#else
-static int inline at91_clock_init(unsigned long main_clock) { return 0; }
+static int inline at91_pmc_init() { return 0; }
#endif
struct device;
diff --git a/arch/arm/mach-at91/pmc.c b/arch/arm/mach-at91/pmc.c
new file mode 100644
index 0000000..2a8a6cf
--- /dev/null
+++ b/arch/arm/mach-at91/pmc.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/mach-at91/pmc.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/at91.h>
+
+#include <asm/io.h>
+#include <asm/proc-fns.h>
+
+void __iomem *at91_pmc_base;
+EXPORT_SYMBOL_GPL(at91_pmc_base);
+
+void at91sam9_idle(void)
+{
+ at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+ cpu_do_idle();
+}
+
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+ { .compatible = "atmel,at91rm9200-pmc" },
+ { /*sentinel*/ }
+};
+
+int __init at91_dt_pmc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, pmc_ids);
+ if (!np)
+ panic("unable to find compatible pmc node in dtb\n");
+
+ at91_pmc_base = of_iomap(np, 0);
+ if (!at91_pmc_base)
+ panic("unable to map pmc cpu registers\n");
+
+ of_node_put(np);
+
+ return 0;
+}
+#endif
+
+int __init at91_pmc_init(void)
+{
+ at91_pmc_base = ioremap(AT91_PMC, 256);
+ if (!at91_pmc_base)
+ panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index de3c519..9a8d58c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -479,41 +479,45 @@ void __init at91rm9200_dt_initialize(void)
{
at91_dt_ramc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
at91_boot_soc.init();
}
-void __init at91_dt_initialize(void)
+void __init at91_dt_initialize()
{
at91_dt_rstc();
at91_dt_ramc();
at91_dt_shdwc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
if (at91_boot_soc.init)
at91_boot_soc.init();
}
-#endif
-void __init at91_initialize(unsigned long main_clock)
+void __init at91_dt_clk_init(void)
{
- at91_boot_soc.ioremap_registers();
+ of_clk_init(NULL);
+}
+#endif
- /* Init clock subsystem */
- at91_clock_init(main_clock);
+void __init at91_clk_init(unsigned long main_clock)
+{
+ clk_register_fixed_rate(NULL, "clk32k", NULL, CLK_IS_ROOT,
+ AT91_SLOW_CLOCK);
+ at91_clk_register_main("main", "clk32k", main_clock);
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();
+}
+
+void __init at91_initialize(void)
+{
+ at91_boot_soc.ioremap_registers();
+
+ /* Init clock subsystem */
+ at91_pmc_init();
at91_boot_soc.init();
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..8c91671 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_AT91) += at91/
obj-$(CONFIG_X86) += x86/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 13/42] ARM: at91: move at91rm9200 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:41 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:41 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91rm9200 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/at91rm9200.c | 566 +++++++++++++++++++++++----------------
2 files changed, 341 insertions(+), 226 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8e02ca..3253373 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -85,6 +85,7 @@ endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
+ select COMMON_CLK
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 8de5b02..3454c8b 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -13,6 +13,7 @@
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/clk/at91.h>
+#include <linux/clkdev.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@@ -25,7 +26,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,245 +35,359 @@
/*
* The peripheral clocks.
*/
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ether_clk = {
- .name = "ether_clk",
- .pmc_mask = 1 << AT91RM9200_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- &ohci_clk,
- ðer_clk,
- // irq0 .. irq6
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
- /* usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
- /* tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91rm9200.0", NULL, NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup ether_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ether_clk", NULL),
+ CLKDEV_INIT("emac_clk", "fffbc000.ethernet", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(ether_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+ ohci_clk_lookup,
+ ether_clk_lookup,
+};
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ ARRAY_SIZE(udp_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ udp_clk_lookup,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] __initdata = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91rm9200_pll_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 180000000),
};
+static u8 at91rm9200_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91rm9200_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91rm9200_pll_output),
+ .output = at91rm9200_pll_output,
+ .out = at91rm9200_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91rm9200_master_characteristics = {
+ .output = CLK_RANGE(0, 80000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 3, 4},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 0, 0};
static void __init at91rm9200_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91rm9200_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91rm9200_master_characteristics);
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 13/42] ARM: at91: move at91rm9200 SoC to new at91 clk implem
@ 2013-07-17 14:41 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:41 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91rm9200 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/at91rm9200.c | 566 +++++++++++++++++++++++----------------
2 files changed, 341 insertions(+), 226 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8e02ca..3253373 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -85,6 +85,7 @@ endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
+ select COMMON_CLK
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 8de5b02..3454c8b 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -13,6 +13,7 @@
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/clk/at91.h>
+#include <linux/clkdev.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@@ -25,7 +26,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,245 +35,359 @@
/*
* The peripheral clocks.
*/
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ether_clk = {
- .name = "ether_clk",
- .pmc_mask = 1 << AT91RM9200_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- &ohci_clk,
- ðer_clk,
- // irq0 .. irq6
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
- /* usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
- /* tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91rm9200.0", NULL, NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup ether_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ether_clk", NULL),
+ CLKDEV_INIT("emac_clk", "fffbc000.ethernet", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(ether_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+ ohci_clk_lookup,
+ ether_clk_lookup,
+};
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ ARRAY_SIZE(udp_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ udp_clk_lookup,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] __initdata = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91rm9200_pll_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 180000000),
};
+static u8 at91rm9200_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91rm9200_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91rm9200_pll_output),
+ .output = at91rm9200_pll_output,
+ .out = at91rm9200_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91rm9200_master_characteristics = {
+ .output = CLK_RANGE(0, 80000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 3, 4},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 0, 0};
static void __init at91rm9200_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91rm9200_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91rm9200_master_characteristics);
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 14/42] ARM: at91: move at91sam9260 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:42 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:42 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9260 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9260.c | 687 +++++++++++++++++++++++++-------------
1 file changed, 452 insertions(+), 235 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index db9d89a..3becd5a 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -26,7 +26,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -36,255 +35,473 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart4_clk = {
- .name = "usart4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart5_clk = {
- .name = "usart5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &adc_clk,
- &adc_op_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &macb_clk,
- &isi_clk,
- &usart3_clk,
- &usart4_clk,
- &usart5_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup adc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "adc_clk", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup usart4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart4_clk", NULL),
+ CLKDEV_INIT("atmel_usart.5", "usart", NULL),
+};
+
+static struct clk_lookup usart5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart5_clk", NULL),
+ CLKDEV_INIT("atmel_usart.6", "usart", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("t0_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("t1_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("t2_clk", "atmel_tcb.1", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(adc_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(usart4_clk_lookup),
+ ARRAY_SIZE(usart5_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ adc_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc_clk_lookup,
+ NULL,
+ NULL,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ usart3_clk_lookup,
+ usart4_clk_lookup,
+ usart5_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9260_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 240000000),
+};
+static u8 at91sam9260_plla_out[] = {0, 2};
+
+static struct clk_range at91sam9260_pllb_output[] = {
+ CLK_RANGE(70000000, 130000000),
+};
+static u8 at91sam9260_pllb_out[] = {1,};
+
+struct clk_pll_characteristics at91sam9260_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9260_plla_output),
+ .output = at91sam9260_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9xe_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 220000000),
+};
+
+struct clk_pll_characteristics at91sam9xe_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9xe_plla_output),
+ .output = at91sam9xe_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9g20_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g20_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g20_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+static struct clk_range at91sam9g20_pllb_output[] = {
+ CLK_RANGE(30000000, 100000000),
+};
+static u8 at91sam9g20_pllb_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g20_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_plla_output),
+ .output = at91sam9g20_plla_output,
+ .out = at91sam9g20_plla_out,
+ .icpll = at91sam9g20_plla_icpll,
+ },
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_pllb_output),
+ .output = at91sam9g20_pllb_output,
+ .out = at91sam9g20_pllb_out,
+ },
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9260_master_characteristics = {
+ .output = CLK_RANGE(0, 105000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9xe_master_characteristics = {
+ .output = CLK_RANGE(0, 90000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g20_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 6},
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9260_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_pll_layout *pll_layout;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9xe()) {
+ pll_characteristics = at91sam9xe_pll_characteristics;
+ master_characteristics = &at91sam9xe_master_characteristics;
+ } else if (cpu_is_at91sam9g20()) {
+ pll_characteristics = at91sam9g20_pll_characteristics;
+ master_characteristics = &at91sam9g20_master_characteristics;
+ } else {
+ pll_characteristics = at91sam9260_pll_characteristics;
+ master_characteristics = &at91sam9260_master_characteristics;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ pll_layout = &at91rm9200_pll_layout;
+ if (cpu_is_at91sam9g20()) {
+ if (!i)
+ pll_layout = &at91sam9g45_pll_layout;
+ else
+ pll_layout = &at91sam9g20_pllb_layout;
+ }
+ clk = at91_clk_register_pll(name, "main", i, pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 5000000);
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 14/42] ARM: at91: move at91sam9260 SoC to new at91 clk implem
@ 2013-07-17 14:42 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:42 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9260 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9260.c | 687 +++++++++++++++++++++++++-------------
1 file changed, 452 insertions(+), 235 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index db9d89a..3becd5a 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -26,7 +26,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -36,255 +35,473 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart4_clk = {
- .name = "usart4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart5_clk = {
- .name = "usart5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &adc_clk,
- &adc_op_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &macb_clk,
- &isi_clk,
- &usart3_clk,
- &usart4_clk,
- &usart5_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup adc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "adc_clk", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup usart4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart4_clk", NULL),
+ CLKDEV_INIT("atmel_usart.5", "usart", NULL),
+};
+
+static struct clk_lookup usart5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart5_clk", NULL),
+ CLKDEV_INIT("atmel_usart.6", "usart", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("t0_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("t1_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("t2_clk", "atmel_tcb.1", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(adc_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(usart4_clk_lookup),
+ ARRAY_SIZE(usart5_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ adc_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc_clk_lookup,
+ NULL,
+ NULL,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ usart3_clk_lookup,
+ usart4_clk_lookup,
+ usart5_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9260_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 240000000),
+};
+static u8 at91sam9260_plla_out[] = {0, 2};
+
+static struct clk_range at91sam9260_pllb_output[] = {
+ CLK_RANGE(70000000, 130000000),
+};
+static u8 at91sam9260_pllb_out[] = {1,};
+
+struct clk_pll_characteristics at91sam9260_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9260_plla_output),
+ .output = at91sam9260_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9xe_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 220000000),
+};
+
+struct clk_pll_characteristics at91sam9xe_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9xe_plla_output),
+ .output = at91sam9xe_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9g20_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g20_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g20_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+static struct clk_range at91sam9g20_pllb_output[] = {
+ CLK_RANGE(30000000, 100000000),
+};
+static u8 at91sam9g20_pllb_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g20_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_plla_output),
+ .output = at91sam9g20_plla_output,
+ .out = at91sam9g20_plla_out,
+ .icpll = at91sam9g20_plla_icpll,
+ },
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_pllb_output),
+ .output = at91sam9g20_pllb_output,
+ .out = at91sam9g20_pllb_out,
+ },
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9260_master_characteristics = {
+ .output = CLK_RANGE(0, 105000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9xe_master_characteristics = {
+ .output = CLK_RANGE(0, 90000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g20_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 6},
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9260_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_pll_layout *pll_layout;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9xe()) {
+ pll_characteristics = at91sam9xe_pll_characteristics;
+ master_characteristics = &at91sam9xe_master_characteristics;
+ } else if (cpu_is_at91sam9g20()) {
+ pll_characteristics = at91sam9g20_pll_characteristics;
+ master_characteristics = &at91sam9g20_master_characteristics;
+ } else {
+ pll_characteristics = at91sam9260_pll_characteristics;
+ master_characteristics = &at91sam9260_master_characteristics;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ pll_layout = &at91rm9200_pll_layout;
+ if (cpu_is_at91sam9g20()) {
+ if (!i)
+ pll_layout = &at91sam9g45_pll_layout;
+ else
+ pll_layout = &at91sam9g20_pllb_layout;
+ }
+ clk = at91_clk_register_pll(name, "main", i, pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 5000000);
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 15/42] ARM: at91: move at91sam9261 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:44 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:44 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9261 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9261.c | 570 +++++++++++++++++++++++++-------------
1 file changed, 374 insertions(+), 196 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index a4123bd..50695e8 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,216 +34,395 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* HClocks */
-static struct clk hck0 = {
- .name = "hck0",
- .pmc_mask = AT91_PMC_HCK0,
- .type = CLK_TYPE_SYSTEM,
- .id = 0,
-};
-static struct clk hck1 = {
- .name = "hck1",
- .pmc_mask = AT91_PMC_HCK1,
- .type = CLK_TYPE_SYSTEM,
- .id = 1,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &lcdc_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9261.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.2", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ lcdc_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static struct clk_lookup hck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck0", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup hck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck1", NULL),
+ CLKDEV_INIT("at91sam9261-lcdfb.0", "hclk", NULL),
+ CLKDEV_INIT("at91sam9g10-lcdfb.0", "hclk", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(hck0_clk_lookup),
+ ARRAY_SIZE(hck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ hck0_clk_lookup,
+ hck1_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9261_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9261_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9261_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9261_pll_output),
+ .output = at91sam9261_pll_output,
+ .out = at91sam9261_pll_out,
+};
+
+static struct clk_range at91sam9g10_pll_output[] = {
+ CLK_RANGE(80000000, 266000000),
+};
+static u8 at91sam9g10_pll_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g10_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g10_pll_output),
+ .output = at91sam9g10_pll_output,
+ .out = at91sam9g10_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9261_master_characteristics = {
+ .output = CLK_RANGE(0, 94000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g10_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9261_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9g10()) {
+ pll_characteristics = &at91sam9g10_pll_characteristics;
+ master_characteristics = &at91sam9g10_master_characteristics;
+ } else {
+ pll_characteristics = &at91sam9261_pll_characteristics;
+ master_characteristics = &at91sam9261_master_characteristics;
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&hck0);
- clk_register(&hck1);
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 15/42] ARM: at91: move at91sam9261 SoC to new at91 clk implem
@ 2013-07-17 14:44 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:44 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9261 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9261.c | 570 +++++++++++++++++++++++++-------------
1 file changed, 374 insertions(+), 196 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index a4123bd..50695e8 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,216 +34,395 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* HClocks */
-static struct clk hck0 = {
- .name = "hck0",
- .pmc_mask = AT91_PMC_HCK0,
- .type = CLK_TYPE_SYSTEM,
- .id = 0,
-};
-static struct clk hck1 = {
- .name = "hck1",
- .pmc_mask = AT91_PMC_HCK1,
- .type = CLK_TYPE_SYSTEM,
- .id = 1,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &lcdc_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9261.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.2", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ lcdc_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static struct clk_lookup hck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck0", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup hck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck1", NULL),
+ CLKDEV_INIT("at91sam9261-lcdfb.0", "hclk", NULL),
+ CLKDEV_INIT("at91sam9g10-lcdfb.0", "hclk", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(hck0_clk_lookup),
+ ARRAY_SIZE(hck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ hck0_clk_lookup,
+ hck1_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9261_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9261_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9261_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9261_pll_output),
+ .output = at91sam9261_pll_output,
+ .out = at91sam9261_pll_out,
+};
+
+static struct clk_range at91sam9g10_pll_output[] = {
+ CLK_RANGE(80000000, 266000000),
+};
+static u8 at91sam9g10_pll_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g10_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g10_pll_output),
+ .output = at91sam9g10_pll_output,
+ .out = at91sam9g10_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9261_master_characteristics = {
+ .output = CLK_RANGE(0, 94000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g10_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9261_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9g10()) {
+ pll_characteristics = &at91sam9g10_pll_characteristics;
+ master_characteristics = &at91sam9g10_master_characteristics;
+ } else {
+ pll_characteristics = &at91sam9261_pll_characteristics;
+ master_characteristics = &at91sam9261_master_characteristics;
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&hck0);
- clk_register(&hck1);
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 16/42] ARM: at91: move at91sam9263 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:45 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:45 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9263 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9263.c | 593 +++++++++++++++++++++++---------------
1 file changed, 364 insertions(+), 229 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index e0a1a68..339b9ef 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -24,7 +24,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,248 +33,384 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCDE_clk = {
- .name = "pioCDE_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
- .name = "can_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_CAN,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twodge_clk = {
- .name = "2dge_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioCDE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &can_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ac97_clk,
- &tcb_clk,
- &pwm_clk,
- &macb_clk,
- &twodge_clk,
- &udc_clk,
- &isi_clk,
- &lcdc_clk,
- &dma_clk,
- &ohci_clk,
- // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioCDE_clk),
- CLKDEV_CON_ID("pioD", &pioCDE_clk),
- CLKDEV_CON_ID("pioE", &pioCDE_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioCDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioCDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup can_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "can_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup tcb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup twodge_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "2dge_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9263-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioCDE_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(mci1_clk_lookup),
+ ARRAY_SIZE(can_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(tcb_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(twodge_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ 0,
+ ARRAY_SIZE(ohci_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioCDE_clk_lookup,
+ NULL,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci0_clk_lookup,
+ mci1_clk_lookup,
+ can_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ac97_clk_lookup,
+ tcb_clk_lookup,
+ pwm_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ twodge_clk_lookup,
+ udc_clk_lookup,
+ isi_clk_lookup,
+ lcdc_clk_lookup,
+ dma_clk_lookup,
+ NULL,
+ ohci_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9263_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9263_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9263_pll_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9263_pll_output),
+ .output = at91sam9263_pll_output,
+ .out = at91sam9263_pll_out,
+};
+
+struct clk_master_characteristics at91sam9263_master_characteristics = {
+ .output = CLK_RANGE(0, 120000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9263_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91sam9263_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9263_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 16/42] ARM: at91: move at91sam9263 SoC to new at91 clk implem
@ 2013-07-17 14:45 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9263 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9263.c | 593 +++++++++++++++++++++++---------------
1 file changed, 364 insertions(+), 229 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index e0a1a68..339b9ef 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -24,7 +24,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,248 +33,384 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCDE_clk = {
- .name = "pioCDE_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
- .name = "can_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_CAN,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twodge_clk = {
- .name = "2dge_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioCDE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &can_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ac97_clk,
- &tcb_clk,
- &pwm_clk,
- &macb_clk,
- &twodge_clk,
- &udc_clk,
- &isi_clk,
- &lcdc_clk,
- &dma_clk,
- &ohci_clk,
- // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioCDE_clk),
- CLKDEV_CON_ID("pioD", &pioCDE_clk),
- CLKDEV_CON_ID("pioE", &pioCDE_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioCDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioCDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup can_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "can_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup tcb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup twodge_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "2dge_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9263-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioCDE_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(mci1_clk_lookup),
+ ARRAY_SIZE(can_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(tcb_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(twodge_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ 0,
+ ARRAY_SIZE(ohci_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioCDE_clk_lookup,
+ NULL,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci0_clk_lookup,
+ mci1_clk_lookup,
+ can_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ac97_clk_lookup,
+ tcb_clk_lookup,
+ pwm_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ twodge_clk_lookup,
+ udc_clk_lookup,
+ isi_clk_lookup,
+ lcdc_clk_lookup,
+ dma_clk_lookup,
+ NULL,
+ ohci_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9263_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9263_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9263_pll_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9263_pll_output),
+ .output = at91sam9263_pll_output,
+ .out = at91sam9263_pll_out,
+};
+
+struct clk_master_characteristics at91sam9263_master_characteristics = {
+ .output = CLK_RANGE(0, 120000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9263_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91sam9263_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9263_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 17/42] ARM: at91: move at91sam9g45 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:49 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:49 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9g45 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9g45.c | 702 ++++++++++++++++++------------
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
2 files changed, 424 insertions(+), 279 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 29ba2ca..a24915a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -24,7 +24,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,299 +33,446 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioDE_clk = {
- .name = "pioDE_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk trng_clk = {
- .name = "trng_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* Video decoder clock - Only for sam9m10/sam9m11 */
-static struct clk vdec_clk = {
- .name = "vdec_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 13200000,
-};
-
-/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
-static struct clk aestdessha_clk = {
- .name = "aestdessha_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioDE_clk,
- &trng_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc0_clk,
- &twi0_clk,
- &twi1_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tcb0_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &uhphs_clk,
- &lcdc_clk,
- &ac97_clk,
- &macb_clk,
- &isi_clk,
- &udphs_clk,
- &mmc1_clk,
- &adc_op_clk,
- &aestdessha_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- /* One additional fake clock for ohci */
- CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
-
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioDE_clk),
- CLKDEV_CON_ID("pioE", &pioDE_clk),
- /* Fake adc clock */
- CLKDEV_CON_ID("adc_clk", &tsc_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup trng_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "trng_clk", NULL),
+ CLKDEV_INIT("atmel-trng", NULL, NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.1", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tcb0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+ CLKDEV_INIT("adc_clk", NULL, NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup uhphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhphs_clk", NULL),
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("atmel-ehci", "ehci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45-lcdfb.0", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45es-lcdfb.0", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup aestdessha_clk_lookup[] = {
+ CLKDEV_INIT("atmel_sha", NULL, NULL),
+ CLKDEV_INIT("atmel_tdes", NULL, NULL),
+ CLKDEV_INIT("atmel_aes", NULL, NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup vdec_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "vdec_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioDE_clk_lookup),
+ ARRAY_SIZE(trng_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tcb0_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(uhphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ 0,
+ ARRAY_SIZE(mci1_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioDE_clk_lookup,
+ trng_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci0_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tcb0_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ uhphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+ macb_clk_lookup,
+ isi_clk_lookup,
+ udphs_clk_lookup,
+ NULL,
+ mci1_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup ddr_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ddrck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(ddr_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ ddr_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+ "mck",
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+};
+
+static struct clk_range at91sam9g45_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g45_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g45_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+struct clk_pll_characteristics at91sam9g45_plla_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g45_plla_output),
+ .output = at91sam9g45_plla_output,
+ .out = at91sam9g45_plla_out,
+ .icpll = at91sam9g45_plla_icpll,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9g45_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 3},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+};
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
+};
+
+/*
+ * USB clock.
+ */
+static const char *usb_clock_parent_names[] __initdata = {
+ "plladiv",
+ "utmi_clk",
+};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9g45_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91sam9g45_pll_layout,
+ &at91sam9g45_plla_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+ clk = at91_clk_register_plldiv("plladiv", "plla");
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9g45_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
- clk_register(&vdec_clk);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_VDEC);
+ for (k = 0; k < ARRAY_SIZE(vdec_clk_lookup); k++)
+ vdec_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup, ARRAY_SIZE(vdec_clk_lookup));
+ }
+
+ if (cpu_is_at91sam9m11() || cpu_is_at91sam9g46()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_AESTDESSHA);
+ for (k = 0; k < ARRAY_SIZE(aestdessha_clk_lookup); k++)
+ aestdessha_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup,
+ ARRAY_SIZE(aestdessha_clk_lookup));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91sam9g45_programmable_layout);
+ }
+
+ clk = at91sam9x5_clk_register_usb("usbck", usb_clock_parent_names,
+ ARRAY_SIZE(usb_clock_parent_names),
+ 0);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 13200000);
}
/* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index cb36fa8..13c650c 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -37,7 +37,6 @@
#include "board.h"
#include "generic.h"
-#include "clock.h"
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 17/42] ARM: at91: move at91sam9g45 SoC to new at91 clk implem
@ 2013-07-17 14:49 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:49 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9g45 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9g45.c | 702 ++++++++++++++++++------------
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
2 files changed, 424 insertions(+), 279 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 29ba2ca..a24915a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -24,7 +24,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,299 +33,446 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioDE_clk = {
- .name = "pioDE_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk trng_clk = {
- .name = "trng_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* Video decoder clock - Only for sam9m10/sam9m11 */
-static struct clk vdec_clk = {
- .name = "vdec_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 13200000,
-};
-
-/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
-static struct clk aestdessha_clk = {
- .name = "aestdessha_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioDE_clk,
- &trng_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc0_clk,
- &twi0_clk,
- &twi1_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tcb0_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &uhphs_clk,
- &lcdc_clk,
- &ac97_clk,
- &macb_clk,
- &isi_clk,
- &udphs_clk,
- &mmc1_clk,
- &adc_op_clk,
- &aestdessha_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- /* One additional fake clock for ohci */
- CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
-
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioDE_clk),
- CLKDEV_CON_ID("pioE", &pioDE_clk),
- /* Fake adc clock */
- CLKDEV_CON_ID("adc_clk", &tsc_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup trng_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "trng_clk", NULL),
+ CLKDEV_INIT("atmel-trng", NULL, NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.1", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tcb0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+ CLKDEV_INIT("adc_clk", NULL, NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup uhphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhphs_clk", NULL),
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("atmel-ehci", "ehci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45-lcdfb.0", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45es-lcdfb.0", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup aestdessha_clk_lookup[] = {
+ CLKDEV_INIT("atmel_sha", NULL, NULL),
+ CLKDEV_INIT("atmel_tdes", NULL, NULL),
+ CLKDEV_INIT("atmel_aes", NULL, NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup vdec_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "vdec_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioDE_clk_lookup),
+ ARRAY_SIZE(trng_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tcb0_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(uhphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ 0,
+ ARRAY_SIZE(mci1_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioDE_clk_lookup,
+ trng_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci0_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tcb0_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ uhphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+ macb_clk_lookup,
+ isi_clk_lookup,
+ udphs_clk_lookup,
+ NULL,
+ mci1_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup ddr_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ddrck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(ddr_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ ddr_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+ "mck",
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+};
+
+static struct clk_range at91sam9g45_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g45_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g45_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+struct clk_pll_characteristics at91sam9g45_plla_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g45_plla_output),
+ .output = at91sam9g45_plla_output,
+ .out = at91sam9g45_plla_out,
+ .icpll = at91sam9g45_plla_icpll,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9g45_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 3},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+};
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
+};
+
+/*
+ * USB clock.
+ */
+static const char *usb_clock_parent_names[] __initdata = {
+ "plladiv",
+ "utmi_clk",
+};
+
+static struct clk_lookup usb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usb_clk", NULL),
};
static void __init at91sam9g45_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91sam9g45_pll_layout,
+ &at91sam9g45_plla_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+ clk = at91_clk_register_plldiv("plladiv", "plla");
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9g45_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
- clk_register(&vdec_clk);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_VDEC);
+ for (k = 0; k < ARRAY_SIZE(vdec_clk_lookup); k++)
+ vdec_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup, ARRAY_SIZE(vdec_clk_lookup));
+ }
+
+ if (cpu_is_at91sam9m11() || cpu_is_at91sam9g46()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_AESTDESSHA);
+ for (k = 0; k < ARRAY_SIZE(aestdessha_clk_lookup); k++)
+ aestdessha_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup,
+ ARRAY_SIZE(aestdessha_clk_lookup));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91sam9g45_programmable_layout);
+ }
+
+ clk = at91sam9x5_clk_register_usb("usbck", usb_clock_parent_names,
+ ARRAY_SIZE(usb_clock_parent_names),
+ 0);
+ for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
+ usb_clk_lookup[i].clk = clk;
+ clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 13200000);
}
/* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index cb36fa8..13c650c 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -37,7 +37,6 @@
#include "board.h"
#include "generic.h"
-#include "clock.h"
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* Re: [PATCH v2 17/42] ARM: at91: move at91sam9g45 SoC to new at91 clk implem
2013-07-17 14:49 ` Boris BREZILLON
@ 2013-07-23 22:29 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-23 22:29 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King, linux-arm-kernel, linux-kernel
Le 17/07/2013 16:49, Boris BREZILLON a écrit :
> This patch removes all references to the old at91 clks implementation and
> make use of the new at91 clk implem for at91sam9g45 SoC.
>
> All dt specific lookups are removed (handled in clk device tree binding).
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> arch/arm/mach-at91/at91sam9g45.c | 702 ++++++++++++++++++------------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> 2 files changed, 424 insertions(+), 279 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 29ba2ca..a24915a 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -24,7 +24,6 @@
> #include "at91_aic.h"
> #include "soc.h"
> #include "generic.h"
> -#include "clock.h"
> #include "sam9_smc.h"
>
> /* --------------------------------------------------------------------
> @@ -34,299 +33,446 @@
> /*
> * The peripheral clocks.
> */
> -static struct clk pioA_clk = {
> - .name = "pioA_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioB_clk = {
> - .name = "pioB_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioC_clk = {
> - .name = "pioC_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioDE_clk = {
> - .name = "pioDE_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk trng_clk = {
> - .name = "trng_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart0_clk = {
> - .name = "usart0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart1_clk = {
> - .name = "usart1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart2_clk = {
> - .name = "usart2_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US2,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart3_clk = {
> - .name = "usart3_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US3,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk mmc0_clk = {
> - .name = "mci0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk twi0_clk = {
> - .name = "twi0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk twi1_clk = {
> - .name = "twi1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk spi0_clk = {
> - .name = "spi0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk spi1_clk = {
> - .name = "spi1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ssc0_clk = {
> - .name = "ssc0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ssc1_clk = {
> - .name = "ssc1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk tcb0_clk = {
> - .name = "tcb0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pwm_clk = {
> - .name = "pwm_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk tsc_clk = {
> - .name = "tsc_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk dma_clk = {
> - .name = "dma_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk uhphs_clk = {
> - .name = "uhphs_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk lcdc_clk = {
> - .name = "lcdc_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ac97_clk = {
> - .name = "ac97_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk macb_clk = {
> - .name = "pclk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk isi_clk = {
> - .name = "isi_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk udphs_clk = {
> - .name = "udphs_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk mmc1_clk = {
> - .name = "mci1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -/* Video decoder clock - Only for sam9m10/sam9m11 */
> -static struct clk vdec_clk = {
> - .name = "vdec_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -static struct clk adc_op_clk = {
> - .name = "adc_op_clk",
> - .type = CLK_TYPE_PERIPHERAL,
> - .rate_hz = 13200000,
> -};
> -
> -/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
> -static struct clk aestdessha_clk = {
> - .name = "aestdessha_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -static struct clk *periph_clocks[] __initdata = {
> - &pioA_clk,
> - &pioB_clk,
> - &pioC_clk,
> - &pioDE_clk,
> - &trng_clk,
> - &usart0_clk,
> - &usart1_clk,
> - &usart2_clk,
> - &usart3_clk,
> - &mmc0_clk,
> - &twi0_clk,
> - &twi1_clk,
> - &spi0_clk,
> - &spi1_clk,
> - &ssc0_clk,
> - &ssc1_clk,
> - &tcb0_clk,
> - &pwm_clk,
> - &tsc_clk,
> - &dma_clk,
> - &uhphs_clk,
> - &lcdc_clk,
> - &ac97_clk,
> - &macb_clk,
> - &isi_clk,
> - &udphs_clk,
> - &mmc1_clk,
> - &adc_op_clk,
> - &aestdessha_clk,
> - // irq0
> -};
> -
> -static struct clk_lookup periph_clocks_lookups[] = {
> - /* One additional fake clock for macb_hclk */
> - CLKDEV_CON_ID("hclk", &macb_clk),
> - /* One additional fake clock for ohci */
> - CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
> - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
> - CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
> - CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
> - CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
> - CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
> - CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
> - CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
> - /* more usart lookup table for DT entries */
> - CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
> - CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
> - /* more tc lookup table for DT entries */
> - CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
> - CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
> - CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
> - /* fake hclk clock */
> - CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
> -
> - CLKDEV_CON_ID("pioA", &pioA_clk),
> - CLKDEV_CON_ID("pioB", &pioB_clk),
> - CLKDEV_CON_ID("pioC", &pioC_clk),
> - CLKDEV_CON_ID("pioD", &pioDE_clk),
> - CLKDEV_CON_ID("pioE", &pioDE_clk),
> - /* Fake adc clock */
> - CLKDEV_CON_ID("adc_clk", &tsc_clk),
> -};
> -
> -static struct clk_lookup usart_clocks_lookups[] = {
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
> +static struct clk_lookup pioA_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioA_clk", NULL),
> + CLKDEV_INIT(NULL, "pioA", NULL),
> +};
> +
> +static struct clk_lookup pioB_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioB_clk", NULL),
> + CLKDEV_INIT(NULL, "pioB", NULL),
> +};
> +
> +static struct clk_lookup pioC_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioC_clk", NULL),
> + CLKDEV_INIT(NULL, "pioC", NULL),
> +};
> +
> +static struct clk_lookup pioDE_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioDE_clk", NULL),
> + CLKDEV_INIT(NULL, "pioD", NULL),
> + CLKDEV_INIT(NULL, "pioE", NULL),
> +};
> +
> +static struct clk_lookup trng_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "trng_clk", NULL),
> + CLKDEV_INIT("atmel-trng", NULL, NULL),
> +};
> +
> +static struct clk_lookup usart0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart0_clk", NULL),
> + CLKDEV_INIT("atmel_usart.1", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart1_clk", NULL),
> + CLKDEV_INIT("atmel_usart.2", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart2_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart2_clk", NULL),
> + CLKDEV_INIT("atmel_usart.3", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart3_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart3_clk", NULL),
> + CLKDEV_INIT("atmel_usart.4", "usart", NULL),
> +};
> +
> +static struct clk_lookup mci0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mci0_clk", NULL),
> + CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
> +};
> +
> +static struct clk_lookup twi0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "twi0_clk", NULL),
> + CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
> +};
> +
> +static struct clk_lookup twi1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "twi1_clk", NULL),
> + CLKDEV_INIT("i2c-at91sam9g10.1", NULL, NULL),
> +};
> +
> +static struct clk_lookup spi0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "spi0_clk", NULL),
> + CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
> +};
> +
> +static struct clk_lookup spi1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "spi0_clk", NULL),
> + CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
> +};
> +
> +static struct clk_lookup ssc0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ssc0_clk", NULL),
> + CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
> +};
> +
> +static struct clk_lookup ssc1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ssc1_clk", NULL),
> + CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
> +};
> +
> +static struct clk_lookup tcb0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "tcb0_clk", NULL),
> + CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
> + CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
> +};
> +
> +static struct clk_lookup pwm_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pwm_clk", NULL),
> +};
> +
> +static struct clk_lookup tsc_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "tsc_clk", NULL),
> + CLKDEV_INIT("adc_clk", NULL, NULL),
> +};
> +
> +static struct clk_lookup dma_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "dma_clk", NULL),
> +};
> +
> +static struct clk_lookup uhphs_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "uhphs_clk", NULL),
> + CLKDEV_INIT(NULL, "ohci_clk", NULL),
> + CLKDEV_INIT("atmel-ehci", "ehci_clk", NULL),
> + CLKDEV_INIT("at91_ohci", "hclk", NULL),
> +};
> +
> +static struct clk_lookup lcdc_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "lcdc_clk", NULL),
> + CLKDEV_INIT("hclk", "at91sam9g45-lcdfb.0", NULL),
> + CLKDEV_INIT("hclk", "at91sam9g45es-lcdfb.0", NULL),
> +};
> +
> +static struct clk_lookup ac97_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ac97_clk", NULL),
> +};
> +
> +static struct clk_lookup macb_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pclk", NULL),
> + CLKDEV_INIT(NULL, "hclk", NULL),
> +};
> +
> +static struct clk_lookup isi_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "isi_clk", NULL),
> +};
> +
> +static struct clk_lookup udphs_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "udphs_clk", NULL),
> + CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
> +};
> +
> +static struct clk_lookup aestdessha_clk_lookup[] = {
> + CLKDEV_INIT("atmel_sha", NULL, NULL),
> + CLKDEV_INIT("atmel_tdes", NULL, NULL),
> + CLKDEV_INIT("atmel_aes", NULL, NULL),
> +};
> +
> +static struct clk_lookup mci1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mci1_clk", NULL),
> + CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
> +};
> +
> +static struct clk_lookup vdec_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "vdec_clk", NULL),
> +};
> +
> +static size_t periph_clock_lookup_sizes[] __initdata = {
> + 0,
> + 0,
> + ARRAY_SIZE(pioA_clk_lookup),
> + ARRAY_SIZE(pioB_clk_lookup),
> + ARRAY_SIZE(pioC_clk_lookup),
> + ARRAY_SIZE(pioDE_clk_lookup),
> + ARRAY_SIZE(trng_clk_lookup),
> + ARRAY_SIZE(usart0_clk_lookup),
> + ARRAY_SIZE(usart1_clk_lookup),
> + ARRAY_SIZE(usart2_clk_lookup),
> + ARRAY_SIZE(usart3_clk_lookup),
> + ARRAY_SIZE(mci0_clk_lookup),
> + ARRAY_SIZE(twi0_clk_lookup),
> + ARRAY_SIZE(twi1_clk_lookup),
> + ARRAY_SIZE(spi0_clk_lookup),
> + ARRAY_SIZE(spi1_clk_lookup),
> + ARRAY_SIZE(ssc0_clk_lookup),
> + ARRAY_SIZE(ssc1_clk_lookup),
> + ARRAY_SIZE(tcb0_clk_lookup),
> + ARRAY_SIZE(pwm_clk_lookup),
> + ARRAY_SIZE(tsc_clk_lookup),
> + ARRAY_SIZE(dma_clk_lookup),
> + ARRAY_SIZE(uhphs_clk_lookup),
> + ARRAY_SIZE(lcdc_clk_lookup),
> + ARRAY_SIZE(ac97_clk_lookup),
> + ARRAY_SIZE(macb_clk_lookup),
> + ARRAY_SIZE(isi_clk_lookup),
> + ARRAY_SIZE(udphs_clk_lookup),
> + 0,
> + ARRAY_SIZE(mci1_clk_lookup),
> +};
> +
> +static struct clk_lookup *periph_clock_lookups[] __initdata = {
> + NULL,
> + NULL,
> + pioA_clk_lookup,
> + pioB_clk_lookup,
> + pioC_clk_lookup,
> + pioDE_clk_lookup,
> + trng_clk_lookup,
> + usart0_clk_lookup,
> + usart1_clk_lookup,
> + usart2_clk_lookup,
> + usart3_clk_lookup,
> + mci0_clk_lookup,
> + twi0_clk_lookup,
> + twi1_clk_lookup,
> + spi0_clk_lookup,
> + spi1_clk_lookup,
> + ssc0_clk_lookup,
> + ssc1_clk_lookup,
> + tcb0_clk_lookup,
> + pwm_clk_lookup,
> + tsc_clk_lookup,
> + dma_clk_lookup,
> + uhphs_clk_lookup,
> + lcdc_clk_lookup,
> + ac97_clk_lookup,
> + macb_clk_lookup,
> + isi_clk_lookup,
> + udphs_clk_lookup,
> + NULL,
> + mci1_clk_lookup,
> +};
> +
> +
> +/*
> + * The system clocks.
> + */
> +static struct clk_lookup ddr_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ddrck", NULL),
> +};
> +
> +static struct clk_lookup uhp_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "uhpck", NULL),
> +};
> +
> +static struct clk_lookup pck0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pck0", NULL),
> +};
> +
> +static struct clk_lookup pck1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pck1", NULL),
> +};
> +
> +static size_t system_clock_lookup_sizes[] __initdata = {
> + 0,
> + 0,
> + ARRAY_SIZE(ddr_clk_lookup),
> + 0,
> + 0,
> + 0,
> + ARRAY_SIZE(uhp_clk_lookup),
> + 0,
> + ARRAY_SIZE(pck0_clk_lookup),
> + ARRAY_SIZE(pck1_clk_lookup),
> +};
> +
> +static struct clk_lookup *system_clock_lookups[] __initdata = {
> + NULL,
> + NULL,
> + ddr_clk_lookup,
> + NULL,
> + NULL,
> + NULL,
> + uhp_clk_lookup,
> + NULL,
> + pck0_clk_lookup,
> + pck1_clk_lookup,
> };
>
> /*
> * The two programmable clocks.
> * You must configure pin multiplexing to bring these signals out.
> */
> -static struct clk pck0 = {
> - .name = "pck0",
> - .pmc_mask = AT91_PMC_PCK0,
> - .type = CLK_TYPE_PROGRAMMABLE,
> - .id = 0,
> +static const char *prog_clock_parent_names[] __initdata = {
> + "clk32k",
> + "main",
> + "plladiv",
> + "utmi_clk",
> + "mck",
> };
> -static struct clk pck1 = {
> - .name = "pck1",
> - .pmc_mask = AT91_PMC_PCK1,
> - .type = CLK_TYPE_PROGRAMMABLE,
> - .id = 1,
> +
> +static const char *prog_clock_names[] __initdata = {
> + "prog0",
> + "prog1",
> +};
> +
> +/*
> + * The pll clocks.
> + */
> +static struct clk_lookup pll_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "plla", NULL),
> +};
> +
> +static struct clk_range at91sam9g45_plla_output[] = {
> + CLK_RANGE(745000000, 800000000),
> + CLK_RANGE(695000000, 750000000),
> + CLK_RANGE(645000000, 700000000),
> + CLK_RANGE(595000000, 650000000),
> + CLK_RANGE(545000000, 600000000),
> + CLK_RANGE(495000000, 550000000),
> + CLK_RANGE(445000000, 500000000),
> + CLK_RANGE(400000000, 450000000),
> +};
> +static u8 at91sam9g45_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
> +static u16 at91sam9g45_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
> +
> +struct clk_pll_characteristics at91sam9g45_plla_characteristics = {
> + .input = CLK_RANGE(2000000, 32000000),
> + .num_output = ARRAY_SIZE(at91sam9g45_plla_output),
> + .output = at91sam9g45_plla_output,
> + .out = at91sam9g45_plla_out,
> + .icpll = at91sam9g45_plla_icpll,
> +};
> +
> +
> +/*
> + * The master clock.
> + */
> +static struct clk_lookup mck_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mck", NULL),
> + CLKDEV_INIT("atmel_usart.0", "usart", NULL),
> +};
> +
> +struct clk_master_characteristics at91sam9g45_master_characteristics = {
> + .output = CLK_RANGE(0, 133000000),
> + .have_div3_pres = 0,
> + .divisors = {1, 2, 4, 3},
> +};
> +
> +static const char *master_clock_parent_names[] __initdata = {
> + "clk32k",
> + "main",
> + "plladiv",
> + "utmi_clk",
> +};
> +
> +/*
> + * UTMI clock.
> + */
> +static struct clk_lookup utmi_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "utmi_clk", NULL),
> + CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
> +};
> +
> +/*
> + * USB clock.
> + */
> +static const char *usb_clock_parent_names[] __initdata = {
> + "plladiv",
> + "utmi_clk",
> +};
> +
> +static struct clk_lookup usb_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usb_clk", NULL),
> };
>
> static void __init at91sam9g45_register_clocks(void)
> {
> int i;
> + int k;
> + size_t size;
> + struct clk *clk;
> + const char *name;
> + struct clk_lookup *lookup;
> +
> + clk = at91_clk_register_pll("plla", "main", 0,
> + &at91sam9g45_pll_layout,
> + &at91sam9g45_plla_characteristics);
> + for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
> + pll_clk_lookup[i].clk = clk;
> + clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
> + clk = at91_clk_register_plldiv("plladiv", "plla");
>
> - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
> - clk_register(periph_clocks[i]);
> + clk = at91_clk_register_utmi("utmi_clk", "main");
> + for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
> + utmi_clk_lookup[i].clk = clk;
> + clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
>
> - clkdev_add_table(periph_clocks_lookups,
> - ARRAY_SIZE(periph_clocks_lookups));
> - clkdev_add_table(usart_clocks_lookups,
> - ARRAY_SIZE(usart_clocks_lookups));
> + clk = at91_clk_register_master("mck",
> + ARRAY_SIZE(master_clock_parent_names),
> + master_clock_parent_names,
> + &at91rm9200_master_layout,
> + &at91sam9g45_master_characteristics);
> + for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
> + mck_clk_lookup[i].clk = clk;
> + clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
>
> - if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
> - clk_register(&vdec_clk);
> + for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
> + size = periph_clock_lookup_sizes[i];
> + lookup = periph_clock_lookups[i];
> + if (!size || !lookup)
> + continue;
> + name = periph_clock_lookups[i][0].con_id;
> + if (!name)
> + continue;
> + clk = at91_clk_register_peripheral(name, "mck", i);
> +
> + for (k = 0; k < size; k++)
> + lookup[k].clk = clk;
> + clkdev_add_table(lookup, size);
> + }
> +
> + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) {
> + clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
> + "mck",
> + AT91SAM9G45_ID_VDEC);
> + for (k = 0; k < ARRAY_SIZE(vdec_clk_lookup); k++)
> + vdec_clk_lookup[k].clk = clk;
> + clkdev_add_table(vdec_clk_lookup, ARRAY_SIZE(vdec_clk_lookup));
> + }
> +
> + if (cpu_is_at91sam9m11() || cpu_is_at91sam9g46()) {
> + clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
> + "mck",
> + AT91SAM9G45_ID_AESTDESSHA);
There is a bug here. It should be:
clk = at91_clk_register_peripheral(aestdessha_clk_lookup[0].con_id,
"mck", AT91SAM9G45_ID_AESTDESSHA);
> + for (k = 0; k < ARRAY_SIZE(aestdessha_clk_lookup); k++)
> + aestdessha_clk_lookup[k].clk = clk;
> + clkdev_add_table(vdec_clk_lookup,
> + ARRAY_SIZE(aestdessha_clk_lookup));
Same bug here:
clkdev_add_table(aestdessha_clk_lookup, ARRAY_SIZE(aestdessha_clk_lookup));
These bugs will be fixed in next version.
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
> + name = prog_clock_names[i];
> + clk = at91_clk_register_programmable(name,
> + prog_clock_parent_names,
> + ARRAY_SIZE(prog_clock_parent_names),
> + i, &at91sam9g45_programmable_layout);
> + }
> +
> + clk = at91sam9x5_clk_register_usb("usbck", usb_clock_parent_names,
> + ARRAY_SIZE(usb_clock_parent_names),
> + 0);
> + for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
> + usb_clk_lookup[i].clk = clk;
> + clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
> +
> + for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
> + size = system_clock_lookup_sizes[i];
> + lookup = system_clock_lookups[i];
> + if (!size || !lookup)
> + continue;
> + name = system_clock_lookups[i][0].con_id;
> + if (!name)
> + continue;
> + clk = at91_clk_register_system(name, i);
> + for (k = 0; k < size; k++)
> + lookup[k].clk = clk;
> + clkdev_add_table(lookup, size);
> + }
>
> - clk_register(&pck0);
> - clk_register(&pck1);
> + clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 13200000);
> }
>
> /* --------------------------------------------------------------------
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index cb36fa8..13c650c 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -37,7 +37,6 @@
>
> #include "board.h"
> #include "generic.h"
> -#include "clock.h"
>
>
> /* --------------------------------------------------------------------
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 17/42] ARM: at91: move at91sam9g45 SoC to new at91 clk implem
@ 2013-07-23 22:29 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-23 22:29 UTC (permalink / raw)
To: linux-arm-kernel
Le 17/07/2013 16:49, Boris BREZILLON a ?crit :
> This patch removes all references to the old at91 clks implementation and
> make use of the new at91 clk implem for at91sam9g45 SoC.
>
> All dt specific lookups are removed (handled in clk device tree binding).
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> arch/arm/mach-at91/at91sam9g45.c | 702 ++++++++++++++++++------------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> 2 files changed, 424 insertions(+), 279 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 29ba2ca..a24915a 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -24,7 +24,6 @@
> #include "at91_aic.h"
> #include "soc.h"
> #include "generic.h"
> -#include "clock.h"
> #include "sam9_smc.h"
>
> /* --------------------------------------------------------------------
> @@ -34,299 +33,446 @@
> /*
> * The peripheral clocks.
> */
> -static struct clk pioA_clk = {
> - .name = "pioA_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioB_clk = {
> - .name = "pioB_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioC_clk = {
> - .name = "pioC_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pioDE_clk = {
> - .name = "pioDE_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk trng_clk = {
> - .name = "trng_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart0_clk = {
> - .name = "usart0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart1_clk = {
> - .name = "usart1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart2_clk = {
> - .name = "usart2_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US2,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk usart3_clk = {
> - .name = "usart3_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_US3,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk mmc0_clk = {
> - .name = "mci0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk twi0_clk = {
> - .name = "twi0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk twi1_clk = {
> - .name = "twi1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk spi0_clk = {
> - .name = "spi0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk spi1_clk = {
> - .name = "spi1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ssc0_clk = {
> - .name = "ssc0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ssc1_clk = {
> - .name = "ssc1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk tcb0_clk = {
> - .name = "tcb0_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk pwm_clk = {
> - .name = "pwm_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk tsc_clk = {
> - .name = "tsc_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk dma_clk = {
> - .name = "dma_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk uhphs_clk = {
> - .name = "uhphs_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk lcdc_clk = {
> - .name = "lcdc_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk ac97_clk = {
> - .name = "ac97_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk macb_clk = {
> - .name = "pclk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk isi_clk = {
> - .name = "isi_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk udphs_clk = {
> - .name = "udphs_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -static struct clk mmc1_clk = {
> - .name = "mci1_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -/* Video decoder clock - Only for sam9m10/sam9m11 */
> -static struct clk vdec_clk = {
> - .name = "vdec_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -static struct clk adc_op_clk = {
> - .name = "adc_op_clk",
> - .type = CLK_TYPE_PERIPHERAL,
> - .rate_hz = 13200000,
> -};
> -
> -/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
> -static struct clk aestdessha_clk = {
> - .name = "aestdessha_clk",
> - .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
> - .type = CLK_TYPE_PERIPHERAL,
> -};
> -
> -static struct clk *periph_clocks[] __initdata = {
> - &pioA_clk,
> - &pioB_clk,
> - &pioC_clk,
> - &pioDE_clk,
> - &trng_clk,
> - &usart0_clk,
> - &usart1_clk,
> - &usart2_clk,
> - &usart3_clk,
> - &mmc0_clk,
> - &twi0_clk,
> - &twi1_clk,
> - &spi0_clk,
> - &spi1_clk,
> - &ssc0_clk,
> - &ssc1_clk,
> - &tcb0_clk,
> - &pwm_clk,
> - &tsc_clk,
> - &dma_clk,
> - &uhphs_clk,
> - &lcdc_clk,
> - &ac97_clk,
> - &macb_clk,
> - &isi_clk,
> - &udphs_clk,
> - &mmc1_clk,
> - &adc_op_clk,
> - &aestdessha_clk,
> - // irq0
> -};
> -
> -static struct clk_lookup periph_clocks_lookups[] = {
> - /* One additional fake clock for macb_hclk */
> - CLKDEV_CON_ID("hclk", &macb_clk),
> - /* One additional fake clock for ohci */
> - CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
> - CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
> - CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
> - CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
> - CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
> - CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
> - CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
> - CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
> - CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
> - /* more usart lookup table for DT entries */
> - CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
> - CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
> - CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
> - /* more tc lookup table for DT entries */
> - CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
> - CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
> - CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
> - CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
> - CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
> - CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
> - /* fake hclk clock */
> - CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
> - CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
> -
> - CLKDEV_CON_ID("pioA", &pioA_clk),
> - CLKDEV_CON_ID("pioB", &pioB_clk),
> - CLKDEV_CON_ID("pioC", &pioC_clk),
> - CLKDEV_CON_ID("pioD", &pioDE_clk),
> - CLKDEV_CON_ID("pioE", &pioDE_clk),
> - /* Fake adc clock */
> - CLKDEV_CON_ID("adc_clk", &tsc_clk),
> -};
> -
> -static struct clk_lookup usart_clocks_lookups[] = {
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
> - CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
> +static struct clk_lookup pioA_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioA_clk", NULL),
> + CLKDEV_INIT(NULL, "pioA", NULL),
> +};
> +
> +static struct clk_lookup pioB_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioB_clk", NULL),
> + CLKDEV_INIT(NULL, "pioB", NULL),
> +};
> +
> +static struct clk_lookup pioC_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioC_clk", NULL),
> + CLKDEV_INIT(NULL, "pioC", NULL),
> +};
> +
> +static struct clk_lookup pioDE_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioDE_clk", NULL),
> + CLKDEV_INIT(NULL, "pioD", NULL),
> + CLKDEV_INIT(NULL, "pioE", NULL),
> +};
> +
> +static struct clk_lookup trng_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "trng_clk", NULL),
> + CLKDEV_INIT("atmel-trng", NULL, NULL),
> +};
> +
> +static struct clk_lookup usart0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart0_clk", NULL),
> + CLKDEV_INIT("atmel_usart.1", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart1_clk", NULL),
> + CLKDEV_INIT("atmel_usart.2", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart2_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart2_clk", NULL),
> + CLKDEV_INIT("atmel_usart.3", "usart", NULL),
> +};
> +
> +static struct clk_lookup usart3_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usart3_clk", NULL),
> + CLKDEV_INIT("atmel_usart.4", "usart", NULL),
> +};
> +
> +static struct clk_lookup mci0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mci0_clk", NULL),
> + CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
> +};
> +
> +static struct clk_lookup twi0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "twi0_clk", NULL),
> + CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
> +};
> +
> +static struct clk_lookup twi1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "twi1_clk", NULL),
> + CLKDEV_INIT("i2c-at91sam9g10.1", NULL, NULL),
> +};
> +
> +static struct clk_lookup spi0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "spi0_clk", NULL),
> + CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
> +};
> +
> +static struct clk_lookup spi1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "spi0_clk", NULL),
> + CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
> +};
> +
> +static struct clk_lookup ssc0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ssc0_clk", NULL),
> + CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
> +};
> +
> +static struct clk_lookup ssc1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ssc1_clk", NULL),
> + CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
> +};
> +
> +static struct clk_lookup tcb0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "tcb0_clk", NULL),
> + CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
> + CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
> +};
> +
> +static struct clk_lookup pwm_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pwm_clk", NULL),
> +};
> +
> +static struct clk_lookup tsc_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "tsc_clk", NULL),
> + CLKDEV_INIT("adc_clk", NULL, NULL),
> +};
> +
> +static struct clk_lookup dma_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "dma_clk", NULL),
> +};
> +
> +static struct clk_lookup uhphs_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "uhphs_clk", NULL),
> + CLKDEV_INIT(NULL, "ohci_clk", NULL),
> + CLKDEV_INIT("atmel-ehci", "ehci_clk", NULL),
> + CLKDEV_INIT("at91_ohci", "hclk", NULL),
> +};
> +
> +static struct clk_lookup lcdc_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "lcdc_clk", NULL),
> + CLKDEV_INIT("hclk", "at91sam9g45-lcdfb.0", NULL),
> + CLKDEV_INIT("hclk", "at91sam9g45es-lcdfb.0", NULL),
> +};
> +
> +static struct clk_lookup ac97_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ac97_clk", NULL),
> +};
> +
> +static struct clk_lookup macb_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pclk", NULL),
> + CLKDEV_INIT(NULL, "hclk", NULL),
> +};
> +
> +static struct clk_lookup isi_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "isi_clk", NULL),
> +};
> +
> +static struct clk_lookup udphs_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "udphs_clk", NULL),
> + CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
> +};
> +
> +static struct clk_lookup aestdessha_clk_lookup[] = {
> + CLKDEV_INIT("atmel_sha", NULL, NULL),
> + CLKDEV_INIT("atmel_tdes", NULL, NULL),
> + CLKDEV_INIT("atmel_aes", NULL, NULL),
> +};
> +
> +static struct clk_lookup mci1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mci1_clk", NULL),
> + CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
> +};
> +
> +static struct clk_lookup vdec_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "vdec_clk", NULL),
> +};
> +
> +static size_t periph_clock_lookup_sizes[] __initdata = {
> + 0,
> + 0,
> + ARRAY_SIZE(pioA_clk_lookup),
> + ARRAY_SIZE(pioB_clk_lookup),
> + ARRAY_SIZE(pioC_clk_lookup),
> + ARRAY_SIZE(pioDE_clk_lookup),
> + ARRAY_SIZE(trng_clk_lookup),
> + ARRAY_SIZE(usart0_clk_lookup),
> + ARRAY_SIZE(usart1_clk_lookup),
> + ARRAY_SIZE(usart2_clk_lookup),
> + ARRAY_SIZE(usart3_clk_lookup),
> + ARRAY_SIZE(mci0_clk_lookup),
> + ARRAY_SIZE(twi0_clk_lookup),
> + ARRAY_SIZE(twi1_clk_lookup),
> + ARRAY_SIZE(spi0_clk_lookup),
> + ARRAY_SIZE(spi1_clk_lookup),
> + ARRAY_SIZE(ssc0_clk_lookup),
> + ARRAY_SIZE(ssc1_clk_lookup),
> + ARRAY_SIZE(tcb0_clk_lookup),
> + ARRAY_SIZE(pwm_clk_lookup),
> + ARRAY_SIZE(tsc_clk_lookup),
> + ARRAY_SIZE(dma_clk_lookup),
> + ARRAY_SIZE(uhphs_clk_lookup),
> + ARRAY_SIZE(lcdc_clk_lookup),
> + ARRAY_SIZE(ac97_clk_lookup),
> + ARRAY_SIZE(macb_clk_lookup),
> + ARRAY_SIZE(isi_clk_lookup),
> + ARRAY_SIZE(udphs_clk_lookup),
> + 0,
> + ARRAY_SIZE(mci1_clk_lookup),
> +};
> +
> +static struct clk_lookup *periph_clock_lookups[] __initdata = {
> + NULL,
> + NULL,
> + pioA_clk_lookup,
> + pioB_clk_lookup,
> + pioC_clk_lookup,
> + pioDE_clk_lookup,
> + trng_clk_lookup,
> + usart0_clk_lookup,
> + usart1_clk_lookup,
> + usart2_clk_lookup,
> + usart3_clk_lookup,
> + mci0_clk_lookup,
> + twi0_clk_lookup,
> + twi1_clk_lookup,
> + spi0_clk_lookup,
> + spi1_clk_lookup,
> + ssc0_clk_lookup,
> + ssc1_clk_lookup,
> + tcb0_clk_lookup,
> + pwm_clk_lookup,
> + tsc_clk_lookup,
> + dma_clk_lookup,
> + uhphs_clk_lookup,
> + lcdc_clk_lookup,
> + ac97_clk_lookup,
> + macb_clk_lookup,
> + isi_clk_lookup,
> + udphs_clk_lookup,
> + NULL,
> + mci1_clk_lookup,
> +};
> +
> +
> +/*
> + * The system clocks.
> + */
> +static struct clk_lookup ddr_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "ddrck", NULL),
> +};
> +
> +static struct clk_lookup uhp_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "uhpck", NULL),
> +};
> +
> +static struct clk_lookup pck0_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pck0", NULL),
> +};
> +
> +static struct clk_lookup pck1_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pck1", NULL),
> +};
> +
> +static size_t system_clock_lookup_sizes[] __initdata = {
> + 0,
> + 0,
> + ARRAY_SIZE(ddr_clk_lookup),
> + 0,
> + 0,
> + 0,
> + ARRAY_SIZE(uhp_clk_lookup),
> + 0,
> + ARRAY_SIZE(pck0_clk_lookup),
> + ARRAY_SIZE(pck1_clk_lookup),
> +};
> +
> +static struct clk_lookup *system_clock_lookups[] __initdata = {
> + NULL,
> + NULL,
> + ddr_clk_lookup,
> + NULL,
> + NULL,
> + NULL,
> + uhp_clk_lookup,
> + NULL,
> + pck0_clk_lookup,
> + pck1_clk_lookup,
> };
>
> /*
> * The two programmable clocks.
> * You must configure pin multiplexing to bring these signals out.
> */
> -static struct clk pck0 = {
> - .name = "pck0",
> - .pmc_mask = AT91_PMC_PCK0,
> - .type = CLK_TYPE_PROGRAMMABLE,
> - .id = 0,
> +static const char *prog_clock_parent_names[] __initdata = {
> + "clk32k",
> + "main",
> + "plladiv",
> + "utmi_clk",
> + "mck",
> };
> -static struct clk pck1 = {
> - .name = "pck1",
> - .pmc_mask = AT91_PMC_PCK1,
> - .type = CLK_TYPE_PROGRAMMABLE,
> - .id = 1,
> +
> +static const char *prog_clock_names[] __initdata = {
> + "prog0",
> + "prog1",
> +};
> +
> +/*
> + * The pll clocks.
> + */
> +static struct clk_lookup pll_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "plla", NULL),
> +};
> +
> +static struct clk_range at91sam9g45_plla_output[] = {
> + CLK_RANGE(745000000, 800000000),
> + CLK_RANGE(695000000, 750000000),
> + CLK_RANGE(645000000, 700000000),
> + CLK_RANGE(595000000, 650000000),
> + CLK_RANGE(545000000, 600000000),
> + CLK_RANGE(495000000, 550000000),
> + CLK_RANGE(445000000, 500000000),
> + CLK_RANGE(400000000, 450000000),
> +};
> +static u8 at91sam9g45_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
> +static u16 at91sam9g45_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
> +
> +struct clk_pll_characteristics at91sam9g45_plla_characteristics = {
> + .input = CLK_RANGE(2000000, 32000000),
> + .num_output = ARRAY_SIZE(at91sam9g45_plla_output),
> + .output = at91sam9g45_plla_output,
> + .out = at91sam9g45_plla_out,
> + .icpll = at91sam9g45_plla_icpll,
> +};
> +
> +
> +/*
> + * The master clock.
> + */
> +static struct clk_lookup mck_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "mck", NULL),
> + CLKDEV_INIT("atmel_usart.0", "usart", NULL),
> +};
> +
> +struct clk_master_characteristics at91sam9g45_master_characteristics = {
> + .output = CLK_RANGE(0, 133000000),
> + .have_div3_pres = 0,
> + .divisors = {1, 2, 4, 3},
> +};
> +
> +static const char *master_clock_parent_names[] __initdata = {
> + "clk32k",
> + "main",
> + "plladiv",
> + "utmi_clk",
> +};
> +
> +/*
> + * UTMI clock.
> + */
> +static struct clk_lookup utmi_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "utmi_clk", NULL),
> + CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
> +};
> +
> +/*
> + * USB clock.
> + */
> +static const char *usb_clock_parent_names[] __initdata = {
> + "plladiv",
> + "utmi_clk",
> +};
> +
> +static struct clk_lookup usb_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "usb_clk", NULL),
> };
>
> static void __init at91sam9g45_register_clocks(void)
> {
> int i;
> + int k;
> + size_t size;
> + struct clk *clk;
> + const char *name;
> + struct clk_lookup *lookup;
> +
> + clk = at91_clk_register_pll("plla", "main", 0,
> + &at91sam9g45_pll_layout,
> + &at91sam9g45_plla_characteristics);
> + for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
> + pll_clk_lookup[i].clk = clk;
> + clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
> + clk = at91_clk_register_plldiv("plladiv", "plla");
>
> - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
> - clk_register(periph_clocks[i]);
> + clk = at91_clk_register_utmi("utmi_clk", "main");
> + for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
> + utmi_clk_lookup[i].clk = clk;
> + clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
>
> - clkdev_add_table(periph_clocks_lookups,
> - ARRAY_SIZE(periph_clocks_lookups));
> - clkdev_add_table(usart_clocks_lookups,
> - ARRAY_SIZE(usart_clocks_lookups));
> + clk = at91_clk_register_master("mck",
> + ARRAY_SIZE(master_clock_parent_names),
> + master_clock_parent_names,
> + &at91rm9200_master_layout,
> + &at91sam9g45_master_characteristics);
> + for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
> + mck_clk_lookup[i].clk = clk;
> + clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
>
> - if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
> - clk_register(&vdec_clk);
> + for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
> + size = periph_clock_lookup_sizes[i];
> + lookup = periph_clock_lookups[i];
> + if (!size || !lookup)
> + continue;
> + name = periph_clock_lookups[i][0].con_id;
> + if (!name)
> + continue;
> + clk = at91_clk_register_peripheral(name, "mck", i);
> +
> + for (k = 0; k < size; k++)
> + lookup[k].clk = clk;
> + clkdev_add_table(lookup, size);
> + }
> +
> + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) {
> + clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
> + "mck",
> + AT91SAM9G45_ID_VDEC);
> + for (k = 0; k < ARRAY_SIZE(vdec_clk_lookup); k++)
> + vdec_clk_lookup[k].clk = clk;
> + clkdev_add_table(vdec_clk_lookup, ARRAY_SIZE(vdec_clk_lookup));
> + }
> +
> + if (cpu_is_at91sam9m11() || cpu_is_at91sam9g46()) {
> + clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
> + "mck",
> + AT91SAM9G45_ID_AESTDESSHA);
There is a bug here. It should be:
clk = at91_clk_register_peripheral(aestdessha_clk_lookup[0].con_id,
"mck", AT91SAM9G45_ID_AESTDESSHA);
> + for (k = 0; k < ARRAY_SIZE(aestdessha_clk_lookup); k++)
> + aestdessha_clk_lookup[k].clk = clk;
> + clkdev_add_table(vdec_clk_lookup,
> + ARRAY_SIZE(aestdessha_clk_lookup));
Same bug here:
clkdev_add_table(aestdessha_clk_lookup, ARRAY_SIZE(aestdessha_clk_lookup));
These bugs will be fixed in next version.
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
> + name = prog_clock_names[i];
> + clk = at91_clk_register_programmable(name,
> + prog_clock_parent_names,
> + ARRAY_SIZE(prog_clock_parent_names),
> + i, &at91sam9g45_programmable_layout);
> + }
> +
> + clk = at91sam9x5_clk_register_usb("usbck", usb_clock_parent_names,
> + ARRAY_SIZE(usb_clock_parent_names),
> + 0);
> + for (i = 0; i < ARRAY_SIZE(usb_clk_lookup); i++)
> + usb_clk_lookup[i].clk = clk;
> + clkdev_add_table(usb_clk_lookup, ARRAY_SIZE(usb_clk_lookup));
> +
> + for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
> + size = system_clock_lookup_sizes[i];
> + lookup = system_clock_lookups[i];
> + if (!size || !lookup)
> + continue;
> + name = system_clock_lookups[i][0].con_id;
> + if (!name)
> + continue;
> + clk = at91_clk_register_system(name, i);
> + for (k = 0; k < size; k++)
> + lookup[k].clk = clk;
> + clkdev_add_table(lookup, size);
> + }
>
> - clk_register(&pck0);
> - clk_register(&pck1);
> + clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 13200000);
> }
>
> /* --------------------------------------------------------------------
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index cb36fa8..13c650c 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -37,7 +37,6 @@
>
> #include "board.h"
> #include "generic.h"
> -#include "clock.h"
>
>
> /* --------------------------------------------------------------------
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 18/42] ARM: at91: move at91sam9n12 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:49 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:49 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks for at91sam9n12 SoC.
This SoC only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9n12.c | 194 --------------------------------------
1 file changed, 194 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c270503..e4863fc 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -19,202 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhp_clk = {
- .name = "uhp",
- .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udp_clk = {
- .name = "udp_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &twi0_clk,
- &twi1_clk,
- &mmc_clk,
- &spi0_clk,
- &spi1_clk,
- &lcdc_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb_clk,
- &pwm_clk,
- &adc_clk,
- &dma_clk,
- &uhp_clk,
- &udp_clk,
- &ssc_clk,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9n12_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
- clk_register(&pck0);
- clk_register(&pck1);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
@@ -225,5 +32,4 @@ static void __init at91sam9n12_map_io(void)
AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io,
- .register_clocks = at91sam9n12_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 18/42] ARM: at91: move at91sam9n12 SoC to new at91 clk implem
@ 2013-07-17 14:49 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:49 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks for at91sam9n12 SoC.
This SoC only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9n12.c | 194 --------------------------------------
1 file changed, 194 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c270503..e4863fc 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -19,202 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhp_clk = {
- .name = "uhp",
- .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udp_clk = {
- .name = "udp_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &twi0_clk,
- &twi1_clk,
- &mmc_clk,
- &spi0_clk,
- &spi1_clk,
- &lcdc_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb_clk,
- &pwm_clk,
- &adc_clk,
- &dma_clk,
- &uhp_clk,
- &udp_clk,
- &ssc_clk,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9n12_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
- clk_register(&pck0);
- clk_register(&pck1);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
@@ -225,5 +32,4 @@ static void __init at91sam9n12_map_io(void)
AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io,
- .register_clocks = at91sam9n12_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 19/42] ARM: at91: move at91sam9rl SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:52 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:52 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9rl SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9rl.c | 500 ++++++++++++++++++++++++---------------
1 file changed, 311 insertions(+), 189 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 2694bd1..57ef54b 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,207 +34,330 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &twi0_clk,
- &twi1_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &udphs_clk,
- &lcdc_clk,
- &ac97_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.1", NULL, NULL),
+};
+
+static struct clk_lookup spi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9rl-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ udphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
+ * The pll clocks.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static struct clk_range at91sam9rl_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9rl_pll_out[] = {0, 2,};
+
+struct clk_pll_characteristics at91sam9rl_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9rl_pll_output),
+ .output = at91sam9rl_pll_output,
+ .out = at91sam9rl_pll_out,
};
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9rl_master_characteristics = {
+ .output = CLK_RANGE(0, 100000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+static const char *master_prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
+};
+
+
static void __init at91sam9rl_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91rm9200_pll_layout,
+ &at91sam9rl_pll_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ master_prog_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9rl_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ master_prog_clock_parent_names,
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 19/42] ARM: at91: move at91sam9rl SoC to new at91 clk implem
@ 2013-07-17 14:52 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:52 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9rl SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9rl.c | 500 ++++++++++++++++++++++++---------------
1 file changed, 311 insertions(+), 189 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 2694bd1..57ef54b 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,207 +34,330 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &twi0_clk,
- &twi1_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &udphs_clk,
- &lcdc_clk,
- &ac97_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.1", NULL, NULL),
+};
+
+static struct clk_lookup spi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9rl-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ udphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
};
/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
+ * The pll clocks.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+static struct clk_range at91sam9rl_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9rl_pll_out[] = {0, 2,};
+
+struct clk_pll_characteristics at91sam9rl_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9rl_pll_output),
+ .output = at91sam9rl_pll_output,
+ .out = at91sam9rl_pll_out,
};
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9rl_master_characteristics = {
+ .output = CLK_RANGE(0, 100000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+static const char *master_prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+};
+
+static const char *prog_clock_names[] __initdata = {
+ "prog0",
+ "prog1",
+};
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
+};
+
+
static void __init at91sam9rl_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91rm9200_pll_layout,
+ &at91sam9rl_pll_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ master_prog_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9rl_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(prog_clock_names); i++) {
+ name = prog_clock_names[i];
+ clk = at91_clk_register_programmable(name,
+ master_prog_clock_parent_names,
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_system(name, i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 20/42] ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:53 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:53 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks for at91sam9x5 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9x5.c | 291 ---------------------------------------
1 file changed, 291 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 9fdea07..583a3d5 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -19,299 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk smd_clk = {
- .name = "smd_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* USART3 clock - Only for sam9g25/sam9x25 */
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
-static struct clk macb0_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi clock - Only for sam9g25 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac1 clock - Only for sam9x25 */
-static struct clk macb1_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can0 clock - Only for sam9x35 */
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can1 clock - Only for sam9x35 */
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &smd_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &spi0_clk,
- &spi1_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb0_clk,
- &pwm_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &mmc1_clk,
- &ssc_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9x5_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25())
- clk_register(&usart3_clk);
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&macb0_clk);
-
- if (cpu_is_at91sam9g15()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&lcdc_clk);
-
- if (cpu_is_at91sam9g25())
- clk_register(&isi_clk);
-
- if (cpu_is_at91sam9x25())
- clk_register(&macb1_clk);
-
- if (cpu_is_at91sam9x25()
- || cpu_is_at91sam9x35()) {
- clk_register(&can0_clk);
- clk_register(&can1_clk);
- }
-
- clk_register(&pck0);
- clk_register(&pck1);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -326,5 +36,4 @@ static void __init at91sam9x5_map_io(void)
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
- .register_clocks = at91sam9x5_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 20/42] ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
@ 2013-07-17 14:53 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:53 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks for at91sam9x5 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam9x5.c | 291 ---------------------------------------
1 file changed, 291 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 9fdea07..583a3d5 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -19,299 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk smd_clk = {
- .name = "smd_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* USART3 clock - Only for sam9g25/sam9x25 */
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
-static struct clk macb0_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi clock - Only for sam9g25 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac1 clock - Only for sam9x25 */
-static struct clk macb1_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can0 clock - Only for sam9x35 */
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can1 clock - Only for sam9x35 */
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &smd_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &spi0_clk,
- &spi1_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb0_clk,
- &pwm_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &mmc1_clk,
- &ssc_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9x5_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25())
- clk_register(&usart3_clk);
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&macb0_clk);
-
- if (cpu_is_at91sam9g15()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&lcdc_clk);
-
- if (cpu_is_at91sam9g25())
- clk_register(&isi_clk);
-
- if (cpu_is_at91sam9x25())
- clk_register(&macb1_clk);
-
- if (cpu_is_at91sam9x25()
- || cpu_is_at91sam9x35()) {
- clk_register(&can0_clk);
- clk_register(&can1_clk);
- }
-
- clk_register(&pck0);
- clk_register(&pck1);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -326,5 +36,4 @@ static void __init at91sam9x5_map_io(void)
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
- .register_clocks = at91sam9x5_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 21/42] ARM: at91: move at91sam9 SoCs to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:59 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:59 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Make use of common clk framework for all at91sam9 SoCs
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3253373..9901316 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -32,6 +32,7 @@ config HAVE_AT91_SMD
config SOC_AT91SAM9
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 21/42] ARM: at91: move at91sam9 SoCs to new at91 clk implem
@ 2013-07-17 14:59 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:59 UTC (permalink / raw)
To: linux-arm-kernel
Make use of common clk framework for all at91sam9 SoCs
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3253373..9901316 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -32,6 +32,7 @@ config HAVE_AT91_SMD
config SOC_AT91SAM9
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 22/42] ARM: at91: move sama5d3 SoCs to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 14:59 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:59 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
This patch removes all references to the old at91 clks for sama5d3 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/sama5d3.c | 342 ------------------------------------------
2 files changed, 1 insertion(+), 342 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9901316..5a51254 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -41,6 +41,7 @@ config SOC_AT91SAM9
config SOC_SAMA5
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_V7
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 32e0522..5e53be8 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -19,350 +19,9 @@
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pid = SAMA5D3_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pid = SAMA5D3_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pid = SAMA5D3_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pid = SAMA5D3_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioE_clk = {
- .name = "pioE_clk",
- .pid = SAMA5D3_ID_PIOE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pid = SAMA5D3_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pid = SAMA5D3_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pid = SAMA5D3_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pid = SAMA5D3_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pid = SAMA5D3_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pid = SAMA5D3_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pid = SAMA5D3_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pid = SAMA5D3_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pid = SAMA5D3_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pid = SAMA5D3_ID_HSMCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pid = SAMA5D3_ID_HSMCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc2_clk = {
- .name = "mci2_clk",
- .pid = SAMA5D3_ID_HSMCI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pid = SAMA5D3_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pid = SAMA5D3_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pid = SAMA5D3_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk tcb1_clk = {
- .name = "tcb1_clk",
- .pid = SAMA5D3_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pid = SAMA5D3_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pid = SAMA5D3_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pid = SAMA5D3_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pid = SAMA5D3_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pid = SAMA5D3_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* gmac only for sama5d33, sama5d34, sama5d35 */
-static struct clk macb0_clk = {
- .name = "macb0_clk",
- .pid = SAMA5D3_ID_GMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac only for sama5d31, sama5d35 */
-static struct clk macb1_clk = {
- .name = "macb1_clk",
- .pid = SAMA5D3_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd only for sama5d31, sama5d33, sama5d34 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pid = SAMA5D3_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi only for sama5d33, sama5d35 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pid = SAMA5D3_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pid = SAMA5D3_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pid = SAMA5D3_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pid = SAMA5D3_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pid = SAMA5D3_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk sha_clk = {
- .name = "sha_clk",
- .pid = SAMA5D3_ID_SHA,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV8,
-};
-static struct clk aes_clk = {
- .name = "aes_clk",
- .pid = SAMA5D3_ID_AES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tdes_clk = {
- .name = "tdes_clk",
- .pid = SAMA5D3_ID_TDES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &pioE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &uart0_clk,
- &uart1_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &mmc2_clk,
- &spi0_clk,
- &spi1_clk,
- &tcb0_clk,
- &tcb1_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &macb0_clk,
- &macb1_clk,
- &lcdc_clk,
- &isi_clk,
- &can0_clk,
- &can1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &sha_clk,
- &aes_clk,
- &tdes_clk,
-};
-
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
- CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
- CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
- CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
- CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
- CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
-};
-
-static void __init sama5d3_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -373,5 +32,4 @@ static void __init sama5d3_map_io(void)
AT91_SOC_START(sama5d3)
.map_io = sama5d3_map_io,
- .register_clocks = sama5d3_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 22/42] ARM: at91: move sama5d3 SoCs to new at91 clk implem
@ 2013-07-17 14:59 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 14:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes all references to the old at91 clks for sama5d3 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/sama5d3.c | 342 ------------------------------------------
2 files changed, 1 insertion(+), 342 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9901316..5a51254 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -41,6 +41,7 @@ config SOC_AT91SAM9
config SOC_SAMA5
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_V7
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 32e0522..5e53be8 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -19,350 +19,9 @@
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pid = SAMA5D3_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pid = SAMA5D3_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pid = SAMA5D3_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pid = SAMA5D3_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioE_clk = {
- .name = "pioE_clk",
- .pid = SAMA5D3_ID_PIOE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pid = SAMA5D3_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pid = SAMA5D3_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pid = SAMA5D3_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pid = SAMA5D3_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pid = SAMA5D3_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pid = SAMA5D3_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pid = SAMA5D3_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pid = SAMA5D3_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pid = SAMA5D3_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pid = SAMA5D3_ID_HSMCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pid = SAMA5D3_ID_HSMCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc2_clk = {
- .name = "mci2_clk",
- .pid = SAMA5D3_ID_HSMCI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pid = SAMA5D3_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pid = SAMA5D3_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pid = SAMA5D3_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk tcb1_clk = {
- .name = "tcb1_clk",
- .pid = SAMA5D3_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pid = SAMA5D3_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pid = SAMA5D3_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pid = SAMA5D3_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pid = SAMA5D3_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pid = SAMA5D3_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* gmac only for sama5d33, sama5d34, sama5d35 */
-static struct clk macb0_clk = {
- .name = "macb0_clk",
- .pid = SAMA5D3_ID_GMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac only for sama5d31, sama5d35 */
-static struct clk macb1_clk = {
- .name = "macb1_clk",
- .pid = SAMA5D3_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd only for sama5d31, sama5d33, sama5d34 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pid = SAMA5D3_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi only for sama5d33, sama5d35 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pid = SAMA5D3_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pid = SAMA5D3_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pid = SAMA5D3_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pid = SAMA5D3_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pid = SAMA5D3_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk sha_clk = {
- .name = "sha_clk",
- .pid = SAMA5D3_ID_SHA,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV8,
-};
-static struct clk aes_clk = {
- .name = "aes_clk",
- .pid = SAMA5D3_ID_AES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tdes_clk = {
- .name = "tdes_clk",
- .pid = SAMA5D3_ID_TDES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &pioE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &uart0_clk,
- &uart1_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &mmc2_clk,
- &spi0_clk,
- &spi1_clk,
- &tcb0_clk,
- &tcb1_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &macb0_clk,
- &macb1_clk,
- &lcdc_clk,
- &isi_clk,
- &can0_clk,
- &can1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &sha_clk,
- &aes_clk,
- &tdes_clk,
-};
-
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
- CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
- CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
- CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
- CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
- CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
-};
-
-static void __init sama5d3_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -373,5 +32,4 @@ static void __init sama5d3_map_io(void)
AT91_SOC_START(sama5d3)
.map_io = sama5d3_map_io,
- .register_clocks = sama5d3_register_clocks,
AT91_SOC_END
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 23/42] ARM: at91: move at91rm9200 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:00 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:00 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Move at91 clk init from early_init to timer_init for all at91rm9200 non dt
boards.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/board-1arm.c | 12 ++++++++++--
arch/arm/mach-at91/board-carmeva.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpuat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-csb337.c | 11 +++++++----
arch/arm/mach-at91/board-csb637.c | 11 +++++++----
arch/arm/mach-at91/board-dt-rm9200.c | 9 ++++++++-
arch/arm/mach-at91/board-eb9200.c | 11 +++++++----
arch/arm/mach-at91/board-ecbat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-eco920.c | 13 +++++++++++--
arch/arm/mach-at91/board-kafa.c | 12 ++++++++++--
arch/arm/mach-at91/board-kb9202.c | 12 ++++++++++--
arch/arm/mach-at91/board-picotux200.c | 11 +++++++----
arch/arm/mach-at91/board-rm9200ek.c | 11 +++++++----
arch/arm/mach-at91/board-rsi-ews.c | 12 ++++++++----
arch/arm/mach-at91/board-yl-9200.c | 12 ++++++++++--
15 files changed, 130 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..1ccfa2d 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -46,8 +46,16 @@ static void __init onearm_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init onearm_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata onearm_eth_data = {
@@ -90,7 +98,7 @@ static void __init onearm_board_init(void)
MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .init_time = at91rm9200_timer_init,
+ .init_time = onearm_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = onearm_init_early,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..591ff4c 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init carmeva_init_early(void)
+static void __init carmeva_timer_init(void)
{
- /* Initialize processor: 20.000 MHz crystal */
- at91_initialize(20000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(20000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata carmeva_eth_data = {
@@ -157,10 +160,10 @@ static void __init carmeva_board_init(void)
MACHINE_START(CARMEVA, "Carmeva")
/* Maintainer: Conitec Datasystems */
- .init_time = at91rm9200_timer_init,
+ .init_time = carmeva_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = carmeva_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = carmeva_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..42b51d9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -58,8 +58,16 @@ static void __init cpuat91_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init cpuat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata cpuat91_eth_data = {
@@ -178,7 +186,7 @@ static void __init cpuat91_board_init(void)
MACHINE_START(CPUAT91, "Eukrea")
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91rm9200_timer_init,
+ .init_time = cpuat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = cpuat91_init_early,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..b772ec2 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -44,10 +44,13 @@
#include "generic.h"
-static void __init csb337_init_early(void)
+static void __init csb337_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb337_eth_data = {
@@ -251,10 +254,10 @@ static void __init csb337_board_init(void)
MACHINE_START(CSB337, "Cogent CSB337")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb337_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb337_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb337_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..4815dbe 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init csb637_init_early(void)
+static void __init csb637_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb637_eth_data = {
@@ -132,10 +135,10 @@ static void __init csb637_board_init(void)
MACHINE_START(CSB637, "Cogent CSB637")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb637_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb637_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb637_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..4f3882e 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -15,6 +15,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91rm9200_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91rm9200_timer_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ /*sentinel*/ }
@@ -47,7 +54,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
- .init_time = at91rm9200_timer_init,
+ .init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..84cc538 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init eb9200_init_early(void)
+static void __init eb9200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eb9200_eth_data = {
@@ -116,10 +119,10 @@ static void __init eb9200_board_init(void)
}
MACHINE_START(ATEB9200, "Embest ATEB9200")
- .init_time = at91rm9200_timer_init,
+ .init_time = eb9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = eb9200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = eb9200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..fc767bd 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -49,8 +49,16 @@ static void __init ecb_at91init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init ecbat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ecb_at91eth_data = {
@@ -181,7 +189,7 @@ static void __init ecb_at91board_init(void)
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
- .init_time = at91rm9200_timer_init,
+ .init_time = ecbat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ecb_at91init_early,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..b910c41 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -37,7 +37,16 @@ static void __init eco920_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
- at91_initialize(18432000);
+ at91_initialize();
+}
+
+static void __init eco920_timer_init(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eco920_eth_data = {
@@ -149,7 +158,7 @@ static void __init eco920_board_init(void)
MACHINE_START(ECO920, "eco920")
/* Maintainer: Sascha Hauer */
- .init_time = at91rm9200_timer_init,
+ .init_time = eco920_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = eco920_init_early,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..e7378c4 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -46,8 +46,16 @@ static void __init kafa_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kafa_eth_data = {
@@ -103,7 +111,7 @@ static void __init kafa_board_init(void)
MACHINE_START(KAFA, "Sperry-Sun KAFA")
/* Maintainer: Sergei Sharonov */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kafa_init_early,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..58f2069 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -49,8 +49,16 @@ static void __init kb9202_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ at91_clk_init(10000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kb9202_eth_data = {
@@ -149,7 +157,7 @@ static void __init kb9202_board_init(void)
MACHINE_START(KB9200, "KB920x")
/* Maintainer: KwikByte, Inc. */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kb9202_init_early,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..8855fad 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init picotux200_init_early(void)
+static void __init picotux200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata picotux200_eth_data = {
@@ -119,10 +122,10 @@ static void __init picotux200_board_init(void)
MACHINE_START(PICOTUX2XX, "picotux 200")
/* Maintainer: Kleinhenz Elektronik GmbH */
- .init_time = at91rm9200_timer_init,
+ .init_time = picotux200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = picotux200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = picotux200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..5d3abac 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -47,10 +47,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ek_eth_data = {
@@ -186,10 +189,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
/* Maintainer: SAN People/Atmel */
- .init_time = at91rm9200_timer_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..31738f9 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -32,10 +32,14 @@
#include "board.h"
#include "generic.h"
-static void __init rsi_ews_init_early(void)
+
+static void __init rsi_ews_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -222,10 +226,10 @@ static void __init rsi_ews_board_init(void)
MACHINE_START(RSI_EWS, "RSI EWS")
/* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
- .init_time = at91rm9200_timer_init,
+ .init_time = rsi_ews_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = rsi_ews_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = rsi_ews_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..78a0780 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -57,8 +57,16 @@ static void __init yl9200_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init yl9200_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -587,7 +595,7 @@ static void __init yl9200_board_init(void)
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles */
- .init_time = at91rm9200_timer_init,
+ .init_time = yl9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = yl9200_init_early,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 23/42] ARM: at91: move at91rm9200 boards to new at91 clk implem
@ 2013-07-17 15:00 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:00 UTC (permalink / raw)
To: linux-arm-kernel
Move at91 clk init from early_init to timer_init for all at91rm9200 non dt
boards.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/board-1arm.c | 12 ++++++++++--
arch/arm/mach-at91/board-carmeva.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpuat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-csb337.c | 11 +++++++----
arch/arm/mach-at91/board-csb637.c | 11 +++++++----
arch/arm/mach-at91/board-dt-rm9200.c | 9 ++++++++-
arch/arm/mach-at91/board-eb9200.c | 11 +++++++----
arch/arm/mach-at91/board-ecbat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-eco920.c | 13 +++++++++++--
arch/arm/mach-at91/board-kafa.c | 12 ++++++++++--
arch/arm/mach-at91/board-kb9202.c | 12 ++++++++++--
arch/arm/mach-at91/board-picotux200.c | 11 +++++++----
arch/arm/mach-at91/board-rm9200ek.c | 11 +++++++----
arch/arm/mach-at91/board-rsi-ews.c | 12 ++++++++----
arch/arm/mach-at91/board-yl-9200.c | 12 ++++++++++--
15 files changed, 130 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..1ccfa2d 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -46,8 +46,16 @@ static void __init onearm_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init onearm_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata onearm_eth_data = {
@@ -90,7 +98,7 @@ static void __init onearm_board_init(void)
MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .init_time = at91rm9200_timer_init,
+ .init_time = onearm_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = onearm_init_early,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..591ff4c 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init carmeva_init_early(void)
+static void __init carmeva_timer_init(void)
{
- /* Initialize processor: 20.000 MHz crystal */
- at91_initialize(20000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(20000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata carmeva_eth_data = {
@@ -157,10 +160,10 @@ static void __init carmeva_board_init(void)
MACHINE_START(CARMEVA, "Carmeva")
/* Maintainer: Conitec Datasystems */
- .init_time = at91rm9200_timer_init,
+ .init_time = carmeva_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = carmeva_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = carmeva_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..42b51d9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -58,8 +58,16 @@ static void __init cpuat91_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init cpuat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata cpuat91_eth_data = {
@@ -178,7 +186,7 @@ static void __init cpuat91_board_init(void)
MACHINE_START(CPUAT91, "Eukrea")
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91rm9200_timer_init,
+ .init_time = cpuat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = cpuat91_init_early,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..b772ec2 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -44,10 +44,13 @@
#include "generic.h"
-static void __init csb337_init_early(void)
+static void __init csb337_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb337_eth_data = {
@@ -251,10 +254,10 @@ static void __init csb337_board_init(void)
MACHINE_START(CSB337, "Cogent CSB337")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb337_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb337_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb337_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..4815dbe 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init csb637_init_early(void)
+static void __init csb637_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb637_eth_data = {
@@ -132,10 +135,10 @@ static void __init csb637_board_init(void)
MACHINE_START(CSB637, "Cogent CSB637")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb637_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb637_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb637_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..4f3882e 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -15,6 +15,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91rm9200_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91rm9200_timer_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ /*sentinel*/ }
@@ -47,7 +54,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
- .init_time = at91rm9200_timer_init,
+ .init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..84cc538 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init eb9200_init_early(void)
+static void __init eb9200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eb9200_eth_data = {
@@ -116,10 +119,10 @@ static void __init eb9200_board_init(void)
}
MACHINE_START(ATEB9200, "Embest ATEB9200")
- .init_time = at91rm9200_timer_init,
+ .init_time = eb9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = eb9200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = eb9200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..fc767bd 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -49,8 +49,16 @@ static void __init ecb_at91init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init ecbat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ecb_at91eth_data = {
@@ -181,7 +189,7 @@ static void __init ecb_at91board_init(void)
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
- .init_time = at91rm9200_timer_init,
+ .init_time = ecbat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ecb_at91init_early,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..b910c41 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -37,7 +37,16 @@ static void __init eco920_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
- at91_initialize(18432000);
+ at91_initialize();
+}
+
+static void __init eco920_timer_init(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eco920_eth_data = {
@@ -149,7 +158,7 @@ static void __init eco920_board_init(void)
MACHINE_START(ECO920, "eco920")
/* Maintainer: Sascha Hauer */
- .init_time = at91rm9200_timer_init,
+ .init_time = eco920_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = eco920_init_early,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..e7378c4 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -46,8 +46,16 @@ static void __init kafa_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kafa_eth_data = {
@@ -103,7 +111,7 @@ static void __init kafa_board_init(void)
MACHINE_START(KAFA, "Sperry-Sun KAFA")
/* Maintainer: Sergei Sharonov */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kafa_init_early,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..58f2069 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -49,8 +49,16 @@ static void __init kb9202_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ at91_clk_init(10000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kb9202_eth_data = {
@@ -149,7 +157,7 @@ static void __init kb9202_board_init(void)
MACHINE_START(KB9200, "KB920x")
/* Maintainer: KwikByte, Inc. */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kb9202_init_early,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..8855fad 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init picotux200_init_early(void)
+static void __init picotux200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata picotux200_eth_data = {
@@ -119,10 +122,10 @@ static void __init picotux200_board_init(void)
MACHINE_START(PICOTUX2XX, "picotux 200")
/* Maintainer: Kleinhenz Elektronik GmbH */
- .init_time = at91rm9200_timer_init,
+ .init_time = picotux200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = picotux200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = picotux200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..5d3abac 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -47,10 +47,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ek_eth_data = {
@@ -186,10 +189,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
/* Maintainer: SAN People/Atmel */
- .init_time = at91rm9200_timer_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..31738f9 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -32,10 +32,14 @@
#include "board.h"
#include "generic.h"
-static void __init rsi_ews_init_early(void)
+
+static void __init rsi_ews_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -222,10 +226,10 @@ static void __init rsi_ews_board_init(void)
MACHINE_START(RSI_EWS, "RSI EWS")
/* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
- .init_time = at91rm9200_timer_init,
+ .init_time = rsi_ews_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = rsi_ews_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = rsi_ews_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..78a0780 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -57,8 +57,16 @@ static void __init yl9200_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init yl9200_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -587,7 +595,7 @@ static void __init yl9200_board_init(void)
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles */
- .init_time = at91rm9200_timer_init,
+ .init_time = yl9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = yl9200_init_early,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:37 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:37 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Move at91 clk init from early_init to timer_init for all at91sam9 non dt
boards.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/board-afeb-9260v1.c | 11 +++++++----
arch/arm/mach-at91/board-cam60.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpu9krea.c | 12 ++++++++----
arch/arm/mach-at91/board-dt-sam9.c | 9 ++++++++-
arch/arm/mach-at91/board-dt-sama5.c | 9 ++++++++-
arch/arm/mach-at91/board-flexibity.c | 12 ++++++++----
arch/arm/mach-at91/board-foxg20.c | 12 +++++++-----
arch/arm/mach-at91/board-gsia18s.c | 8 ++------
arch/arm/mach-at91/board-pcontrol-g20.c | 9 ++-------
arch/arm/mach-at91/board-qil-a9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9-l9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9260ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9261ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9263ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9g20ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9rlek.c | 11 +++++++----
arch/arm/mach-at91/board-snapper9260.c | 12 ++++++++----
arch/arm/mach-at91/board-stamp9g20.c | 15 +++++++++------
arch/arm/mach-at91/stamp9g20.h | 2 +-
20 files changed, 136 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..c6849e1 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -48,10 +48,13 @@
#include "generic.h"
-static void __init afeb9260_init_early(void)
+static void __init afeb9260_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -210,10 +213,10 @@ static void __init afeb9260_board_init(void)
MACHINE_START(AFEB9260, "Custom afeb9260 board")
/* Maintainer: Sergey Lapin <slapin@ossfans.org> */
- .init_time = at91sam926x_pit_init,
+ .init_time = afeb9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = afeb9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = afeb9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..75c89a0 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -46,10 +46,13 @@
#include "generic.h"
-static void __init cam60_init_early(void)
+static void __init cam60_timer_init(void)
{
- /* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(10000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -187,10 +190,10 @@ static void __init cam60_board_init(void)
MACHINE_START(CAM60, "KwikByte CAM60")
/* Maintainer: KwikByte */
- .init_time = at91sam926x_pit_init,
+ .init_time = cam60_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cam60_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cam60_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..a88d8ec 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -49,10 +49,14 @@
#include "sam9_smc.h"
#include "generic.h"
-static void __init cpu9krea_init_early(void)
+
+static void __init cpu9krea_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -374,10 +378,10 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
#endif
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91sam926x_pit_init,
+ .init_time = cpu9krea_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cpu9krea_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cpu9krea_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..a7ea21f 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91sam_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -49,7 +56,7 @@ static const char *at91_dt_board_compat[] __initdata = {
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sam_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index ad95f6a..7ad3d96 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -27,6 +28,12 @@
#include "generic.h"
+static void __init at91sama5_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
@@ -77,7 +84,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sama5_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic5_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..f64b47a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -38,10 +38,14 @@
#include "board.h"
#include "generic.h"
-static void __init flexibity_init_early(void)
+
+static void __init flexibity_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/* USB Host port */
@@ -159,10 +163,10 @@ static void __init flexibity_board_init(void)
MACHINE_START(FLEXIBITY, "Flexibity Connect")
/* Maintainer: Maxim Osipov */
- .init_time = at91sam926x_pit_init,
+ .init_time = flexibity_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = flexibity_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = flexibity_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..c4caeb3 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -57,11 +57,13 @@
* For more info visit: http://www.acmesystems.it/foxg20
*/
-
-static void __init foxg20_init_early(void)
+static void __init foxg20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -262,10 +264,10 @@ static void __init foxg20_board_init(void)
MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
/* Maintainer: Sergio Tanzilli */
- .init_time = at91sam926x_pit_init,
+ .init_time = foxg20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = foxg20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = foxg20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..4ed7ef4 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -39,10 +39,6 @@
#include "gsia18s.h"
#include "stamp9g20.h"
-static void __init gsia18s_init_early(void)
-{
- stamp9g20_init_early();
-}
/*
* Two USB Host ports
@@ -574,10 +570,10 @@ static void __init gsia18s_board_init(void)
}
MACHINE_START(GSIA18S, "GS_IA18_S")
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = gsia18s_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = gsia18s_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..6602e14 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -38,11 +38,6 @@
#include "stamp9g20.h"
-static void __init pcontrol_g20_init_early(void)
-{
- stamp9g20_init_early();
-}
-
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.ncs_read_setup = 16,
.nrd_setup = 18,
@@ -217,10 +212,10 @@ static void __init pcontrol_g20_board_init(void)
MACHINE_START(PCONTROL_G20, "PControl G20")
/* Maintainer: pgsellmann@portner-elektronik.at */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = pcontrol_g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = pcontrol_g20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..b7a9976 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -49,10 +49,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -257,10 +260,10 @@ static void __init ek_board_init(void)
MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
/* Maintainer: calao-systems */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..f078f94 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -218,10 +221,10 @@ static void __init ek_board_init(void)
MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
/* Maintainer: Olimex */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..2737a5c 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -51,10 +51,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -343,10 +346,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 473546b..212210e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -55,10 +55,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -602,20 +605,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 8b4942c..c427d62 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -54,10 +54,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 16.367 MHz crystal */
- at91_initialize(16367660);
+ at91_clk_init(16367660);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -443,10 +446,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..10abb59 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -64,10 +64,13 @@ static int inline ek_have_2mmc(void)
}
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -409,20 +412,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ef39078..4125b82 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -52,10 +52,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -502,10 +505,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 604eecf..1490d91 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -320,10 +323,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..afe48fd 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -41,9 +41,13 @@
#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
-static void __init snapper9260_init_early(void)
+static void __init snapper9260_timer_init(void)
{
- at91_initialize(18432000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
@@ -177,10 +181,10 @@ static void __init snapper9260_board_init(void)
}
MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
- .init_time = at91sam926x_pit_init,
+ .init_time = snapper9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = snapper9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = snapper9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..e4cee53 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -33,10 +33,13 @@
#include "generic.h"
-void __init stamp9g20_init_early(void)
+void __init stamp9g20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -273,20 +276,20 @@ static void __init stamp9g20evb_board_init(void)
MACHINE_START(PORTUXG20, "taskit PortuxG20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = portuxg20_board_init,
MACHINE_END
MACHINE_START(STAMP9G20, "taskit Stamp9G20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = stamp9g20evb_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
index f62c0ab..26a37b5 100644
--- a/arch/arm/mach-at91/stamp9g20.h
+++ b/arch/arm/mach-at91/stamp9g20.h
@@ -1,7 +1,7 @@
#ifndef __MACH_STAMP9G20_H
#define __MACH_STAMP9G20_H
-void stamp9g20_init_early(void);
+void stamp9g20_timer_init(void);
void stamp9g20_board_init(void);
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
@ 2013-07-17 15:37 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:37 UTC (permalink / raw)
To: linux-arm-kernel
Move at91 clk init from early_init to timer_init for all at91sam9 non dt
boards.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/board-afeb-9260v1.c | 11 +++++++----
arch/arm/mach-at91/board-cam60.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpu9krea.c | 12 ++++++++----
arch/arm/mach-at91/board-dt-sam9.c | 9 ++++++++-
arch/arm/mach-at91/board-dt-sama5.c | 9 ++++++++-
arch/arm/mach-at91/board-flexibity.c | 12 ++++++++----
arch/arm/mach-at91/board-foxg20.c | 12 +++++++-----
arch/arm/mach-at91/board-gsia18s.c | 8 ++------
arch/arm/mach-at91/board-pcontrol-g20.c | 9 ++-------
arch/arm/mach-at91/board-qil-a9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9-l9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9260ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9261ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9263ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9g20ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9rlek.c | 11 +++++++----
arch/arm/mach-at91/board-snapper9260.c | 12 ++++++++----
arch/arm/mach-at91/board-stamp9g20.c | 15 +++++++++------
arch/arm/mach-at91/stamp9g20.h | 2 +-
20 files changed, 136 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..c6849e1 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -48,10 +48,13 @@
#include "generic.h"
-static void __init afeb9260_init_early(void)
+static void __init afeb9260_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -210,10 +213,10 @@ static void __init afeb9260_board_init(void)
MACHINE_START(AFEB9260, "Custom afeb9260 board")
/* Maintainer: Sergey Lapin <slapin@ossfans.org> */
- .init_time = at91sam926x_pit_init,
+ .init_time = afeb9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = afeb9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = afeb9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..75c89a0 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -46,10 +46,13 @@
#include "generic.h"
-static void __init cam60_init_early(void)
+static void __init cam60_timer_init(void)
{
- /* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(10000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -187,10 +190,10 @@ static void __init cam60_board_init(void)
MACHINE_START(CAM60, "KwikByte CAM60")
/* Maintainer: KwikByte */
- .init_time = at91sam926x_pit_init,
+ .init_time = cam60_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cam60_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cam60_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..a88d8ec 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -49,10 +49,14 @@
#include "sam9_smc.h"
#include "generic.h"
-static void __init cpu9krea_init_early(void)
+
+static void __init cpu9krea_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -374,10 +378,10 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
#endif
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91sam926x_pit_init,
+ .init_time = cpu9krea_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cpu9krea_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cpu9krea_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..a7ea21f 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91sam_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -49,7 +56,7 @@ static const char *at91_dt_board_compat[] __initdata = {
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sam_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index ad95f6a..7ad3d96 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -27,6 +28,12 @@
#include "generic.h"
+static void __init at91sama5_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
@@ -77,7 +84,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sama5_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic5_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..f64b47a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -38,10 +38,14 @@
#include "board.h"
#include "generic.h"
-static void __init flexibity_init_early(void)
+
+static void __init flexibity_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/* USB Host port */
@@ -159,10 +163,10 @@ static void __init flexibity_board_init(void)
MACHINE_START(FLEXIBITY, "Flexibity Connect")
/* Maintainer: Maxim Osipov */
- .init_time = at91sam926x_pit_init,
+ .init_time = flexibity_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = flexibity_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = flexibity_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..c4caeb3 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -57,11 +57,13 @@
* For more info visit: http://www.acmesystems.it/foxg20
*/
-
-static void __init foxg20_init_early(void)
+static void __init foxg20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -262,10 +264,10 @@ static void __init foxg20_board_init(void)
MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
/* Maintainer: Sergio Tanzilli */
- .init_time = at91sam926x_pit_init,
+ .init_time = foxg20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = foxg20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = foxg20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..4ed7ef4 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -39,10 +39,6 @@
#include "gsia18s.h"
#include "stamp9g20.h"
-static void __init gsia18s_init_early(void)
-{
- stamp9g20_init_early();
-}
/*
* Two USB Host ports
@@ -574,10 +570,10 @@ static void __init gsia18s_board_init(void)
}
MACHINE_START(GSIA18S, "GS_IA18_S")
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = gsia18s_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = gsia18s_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..6602e14 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -38,11 +38,6 @@
#include "stamp9g20.h"
-static void __init pcontrol_g20_init_early(void)
-{
- stamp9g20_init_early();
-}
-
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.ncs_read_setup = 16,
.nrd_setup = 18,
@@ -217,10 +212,10 @@ static void __init pcontrol_g20_board_init(void)
MACHINE_START(PCONTROL_G20, "PControl G20")
/* Maintainer: pgsellmann at portner-elektronik.at */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = pcontrol_g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = pcontrol_g20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..b7a9976 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -49,10 +49,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -257,10 +260,10 @@ static void __init ek_board_init(void)
MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
/* Maintainer: calao-systems */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..f078f94 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -218,10 +221,10 @@ static void __init ek_board_init(void)
MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
/* Maintainer: Olimex */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..2737a5c 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -51,10 +51,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -343,10 +346,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 473546b..212210e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -55,10 +55,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -602,20 +605,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 8b4942c..c427d62 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -54,10 +54,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 16.367 MHz crystal */
- at91_initialize(16367660);
+ at91_clk_init(16367660);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -443,10 +446,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..10abb59 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -64,10 +64,13 @@ static int inline ek_have_2mmc(void)
}
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -409,20 +412,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ef39078..4125b82 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -52,10 +52,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -502,10 +505,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 604eecf..1490d91 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -320,10 +323,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..afe48fd 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -41,9 +41,13 @@
#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
-static void __init snapper9260_init_early(void)
+static void __init snapper9260_timer_init(void)
{
- at91_initialize(18432000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
@@ -177,10 +181,10 @@ static void __init snapper9260_board_init(void)
}
MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
- .init_time = at91sam926x_pit_init,
+ .init_time = snapper9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = snapper9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = snapper9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..e4cee53 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -33,10 +33,13 @@
#include "generic.h"
-void __init stamp9g20_init_early(void)
+void __init stamp9g20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -273,20 +276,20 @@ static void __init stamp9g20evb_board_init(void)
MACHINE_START(PORTUXG20, "taskit PortuxG20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = portuxg20_board_init,
MACHINE_END
MACHINE_START(STAMP9G20, "taskit Stamp9G20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = stamp9g20evb_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
index f62c0ab..26a37b5 100644
--- a/arch/arm/mach-at91/stamp9g20.h
+++ b/arch/arm/mach-at91/stamp9g20.h
@@ -1,7 +1,7 @@
#ifndef __MACH_STAMP9G20_H
#define __MACH_STAMP9G20_H
-void stamp9g20_init_early(void);
+void stamp9g20_timer_init(void);
void stamp9g20_board_init(void);
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* Re: [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
2013-07-17 15:37 ` Boris BREZILLON
@ 2013-07-17 17:13 ` Russell King - ARM Linux
-1 siblings, 0 replies; 129+ messages in thread
From: Russell King - ARM Linux @ 2013-07-17 17:13 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
linux-arm-kernel, linux-kernel
On Wed, Jul 17, 2013 at 05:37:13PM +0200, Boris BREZILLON wrote:
> Move at91 clk init from early_init to timer_init for all at91sam9 non dt
> boards.
Using black ball point pen, please complete the following sentence using
as many words as you desire. Additional underscores are available on
request.
The reason for this change is ______________________________________.
Thanks. :)
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
@ 2013-07-17 17:13 ` Russell King - ARM Linux
0 siblings, 0 replies; 129+ messages in thread
From: Russell King - ARM Linux @ 2013-07-17 17:13 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 17, 2013 at 05:37:13PM +0200, Boris BREZILLON wrote:
> Move at91 clk init from early_init to timer_init for all at91sam9 non dt
> boards.
Using black ball point pen, please complete the following sentence using
as many words as you desire. Additional underscores are available on
request.
The reason for this change is ______________________________________.
Thanks. :)
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
2013-07-17 17:13 ` Russell King - ARM Linux
@ 2013-07-17 20:32 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-17 20:32 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
linux-arm-kernel, linux-kernel
On 17/07/2013 19:13, Russell King - ARM Linux wrote:
> On Wed, Jul 17, 2013 at 05:37:13PM +0200, Boris BREZILLON wrote:
>> Move at91 clk init from early_init to timer_init for all at91sam9 non dt
>> boards.
> Using black ball point pen, please complete the following sentence using
> as many words as you desire. Additional underscores are available on
> request.
>
> The reason for this change is ______________________________________.
>
> Thanks. :)
Indeed, this commit message is a bit useless as it only describe what is
done not why...
The reason for this is that dynamic allocator is not ready yet when
early_init callback is called,
and new at91 clk implementation calls kzalloc functions.
It is moved in timer_init (before timer init) because at91sam9 init
timer (pit timer) request the
mck clk which is registered by at91 clk init function.
I'll change this commit message in the next version.
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 24/42] ARM: at91: move at91sam9 boards to new at91 clk implem
@ 2013-07-17 20:32 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-17 20:32 UTC (permalink / raw)
To: linux-arm-kernel
On 17/07/2013 19:13, Russell King - ARM Linux wrote:
> On Wed, Jul 17, 2013 at 05:37:13PM +0200, Boris BREZILLON wrote:
>> Move at91 clk init from early_init to timer_init for all at91sam9 non dt
>> boards.
> Using black ball point pen, please complete the following sentence using
> as many words as you desire. Additional underscores are available on
> request.
>
> The reason for this change is ______________________________________.
>
> Thanks. :)
Indeed, this commit message is a bit useless as it only describe what is
done not why...
The reason for this is that dynamic allocator is not ready yet when
early_init callback is called,
and new at91 clk implementation calls kzalloc functions.
It is moved in timer_init (before timer init) because at91sam9 init
timer (pit timer) request the
mck clk which is registered by at91 clk init function.
I'll change this commit message in the next version.
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 25/42] ARM: at91: move pit timer to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:46 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:46 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Andrew Victor,
Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Use device tree to get the source clock of the PIT (Periodic Interval Timer).
If the clock is not found in device tree (or dt is not enabled) we'll try to
get it using clk_lookup definitions.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam926x_time.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 3a4bc2e..fba7bd6 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
static u32 pit_cycle; /* write-once */
static u32 pit_cnt; /* access only w/system irq blocked */
static void __iomem *pit_base_addr __read_mostly;
+static struct clk *mck;
static inline unsigned int pit_read(unsigned int reg_offset)
{
@@ -186,6 +187,7 @@ static int __init of_at91sam926x_pit_init(void)
{
struct device_node *np;
int ret;
+ int err = -EINVAL;
np = of_find_matching_node(NULL, pit_timer_ids);
if (!np)
@@ -195,10 +197,19 @@ static int __init of_at91sam926x_pit_init(void)
if (!pit_base_addr)
goto node_err;
+ mck = of_clk_get(np, 0);
+ if (IS_ERR(mck)) {
+ err = PTR_RET(mck);
+ mck = NULL;
+ pr_crit("AT91: PIT: Unable to get mck clk from DT\n");
+ goto ioremap_err;
+ }
+
/* Get the interrupts property */
ret = irq_of_parse_and_map(np, 0);
if (!ret) {
pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+ clk_put(mck);
goto ioremap_err;
}
at91sam926x_pit_irq.irq = ret;
@@ -212,7 +223,7 @@ ioremap_err:
node_err:
of_node_put(np);
err:
- return -EINVAL;
+ return err;
}
#else
static int __init of_at91sam926x_pit_init(void)
@@ -237,7 +248,13 @@ void __init at91sam926x_pit_init(void)
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
- pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ if (!mck)
+ mck = clk_get(NULL, "mck");
+
+ if (IS_ERR(mck))
+ panic("AT91: PIT: Unable to get mck clk\n");
+ pit_rate = clk_get_rate(mck) / 16;
+ pr_notice("AT91: PIT: mck rate = %lu\n", pit_rate);
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 25/42] ARM: at91: move pit timer to common clk framework
@ 2013-07-17 15:46 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:46 UTC (permalink / raw)
To: linux-arm-kernel
Use device tree to get the source clock of the PIT (Periodic Interval Timer).
If the clock is not found in device tree (or dt is not enabled) we'll try to
get it using clk_lookup definitions.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/mach-at91/at91sam926x_time.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 3a4bc2e..fba7bd6 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
static u32 pit_cycle; /* write-once */
static u32 pit_cnt; /* access only w/system irq blocked */
static void __iomem *pit_base_addr __read_mostly;
+static struct clk *mck;
static inline unsigned int pit_read(unsigned int reg_offset)
{
@@ -186,6 +187,7 @@ static int __init of_at91sam926x_pit_init(void)
{
struct device_node *np;
int ret;
+ int err = -EINVAL;
np = of_find_matching_node(NULL, pit_timer_ids);
if (!np)
@@ -195,10 +197,19 @@ static int __init of_at91sam926x_pit_init(void)
if (!pit_base_addr)
goto node_err;
+ mck = of_clk_get(np, 0);
+ if (IS_ERR(mck)) {
+ err = PTR_RET(mck);
+ mck = NULL;
+ pr_crit("AT91: PIT: Unable to get mck clk from DT\n");
+ goto ioremap_err;
+ }
+
/* Get the interrupts property */
ret = irq_of_parse_and_map(np, 0);
if (!ret) {
pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+ clk_put(mck);
goto ioremap_err;
}
at91sam926x_pit_irq.irq = ret;
@@ -212,7 +223,7 @@ ioremap_err:
node_err:
of_node_put(np);
err:
- return -EINVAL;
+ return err;
}
#else
static int __init of_at91sam926x_pit_init(void)
@@ -237,7 +248,13 @@ void __init at91sam926x_pit_init(void)
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
- pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ if (!mck)
+ mck = clk_get(NULL, "mck");
+
+ if (IS_ERR(mck))
+ panic("AT91: PIT: Unable to get mck clk\n");
+ pit_rate = clk_get_rate(mck) / 16;
+ pr_notice("AT91: PIT: mck rate = %lu\n", pit_rate);
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:47 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:47 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Alan Stern,
Greg Kroah-Hartman
Cc: linux-arm-kernel, linux-kernel, linux-usb, Boris BREZILLON
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed when moving to common clk framework.
This patch add support for usb clock retrieval and configuration.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/usb/host/ohci-at91.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9677f68..ca1cdd6 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -31,8 +31,8 @@
#define at91_for_each_port(index) \
for ((index) = 0; (index) < AT91_MAX_USBH_PORTS; (index)++)
-/* interface and function clocks; sometimes also an AHB clock */
-static struct clk *iclk, *fclk, *hclk;
+/* interface, function and usb clocks; sometimes also an AHB clock */
+static struct clk *iclk, *fclk, *uclk, *hclk;
static int clocked;
extern int usb_disabled(void);
@@ -41,6 +41,8 @@ extern int usb_disabled(void);
static void at91_start_clock(void)
{
+ clk_set_rate(uclk, 48000000);
+ clk_prepare_enable(uclk);
clk_prepare_enable(hclk);
clk_prepare_enable(iclk);
clk_prepare_enable(fclk);
@@ -52,6 +54,7 @@ static void at91_stop_clock(void)
clk_disable_unprepare(fclk);
clk_disable_unprepare(iclk);
clk_disable_unprepare(hclk);
+ clk_disable_unprepare(uclk);
clocked = 0;
}
@@ -162,6 +165,12 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
retval = PTR_ERR(hclk);
goto err5;
}
+ uclk = clk_get(&pdev->dev, "usb_clk");
+ if (IS_ERR(uclk)) {
+ dev_err(&pdev->dev, "failed to get usb_clk\n");
+ retval = PTR_ERR(uclk);
+ goto err6;
+ }
at91_start_hc(pdev);
ohci_hcd_init(hcd_to_ohci(hcd));
@@ -173,6 +182,8 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
/* Error handling */
at91_stop_hc(pdev);
+ clk_put(uclk);
+ err6:
clk_put(hclk);
err5:
clk_put(fclk);
@@ -212,6 +223,7 @@ static void usb_hcd_at91_remove(struct usb_hcd *hcd,
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
+ clk_put(uclk);
clk_put(hclk);
clk_put(fclk);
clk_put(iclk);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
@ 2013-07-17 15:47 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:47 UTC (permalink / raw)
To: linux-arm-kernel
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed when moving to common clk framework.
This patch add support for usb clock retrieval and configuration.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/usb/host/ohci-at91.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9677f68..ca1cdd6 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -31,8 +31,8 @@
#define at91_for_each_port(index) \
for ((index) = 0; (index) < AT91_MAX_USBH_PORTS; (index)++)
-/* interface and function clocks; sometimes also an AHB clock */
-static struct clk *iclk, *fclk, *hclk;
+/* interface, function and usb clocks; sometimes also an AHB clock */
+static struct clk *iclk, *fclk, *uclk, *hclk;
static int clocked;
extern int usb_disabled(void);
@@ -41,6 +41,8 @@ extern int usb_disabled(void);
static void at91_start_clock(void)
{
+ clk_set_rate(uclk, 48000000);
+ clk_prepare_enable(uclk);
clk_prepare_enable(hclk);
clk_prepare_enable(iclk);
clk_prepare_enable(fclk);
@@ -52,6 +54,7 @@ static void at91_stop_clock(void)
clk_disable_unprepare(fclk);
clk_disable_unprepare(iclk);
clk_disable_unprepare(hclk);
+ clk_disable_unprepare(uclk);
clocked = 0;
}
@@ -162,6 +165,12 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
retval = PTR_ERR(hclk);
goto err5;
}
+ uclk = clk_get(&pdev->dev, "usb_clk");
+ if (IS_ERR(uclk)) {
+ dev_err(&pdev->dev, "failed to get usb_clk\n");
+ retval = PTR_ERR(uclk);
+ goto err6;
+ }
at91_start_hc(pdev);
ohci_hcd_init(hcd_to_ohci(hcd));
@@ -173,6 +182,8 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
/* Error handling */
at91_stop_hc(pdev);
+ clk_put(uclk);
+ err6:
clk_put(hclk);
err5:
clk_put(fclk);
@@ -212,6 +223,7 @@ static void usb_hcd_at91_remove(struct usb_hcd *hcd,
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
+ clk_put(uclk);
clk_put(hclk);
clk_put(fclk);
clk_put(iclk);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* Re: [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
2013-07-17 15:47 ` Boris BREZILLON
@ 2013-07-31 7:56 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-31 7:56 UTC (permalink / raw)
To: Boris BREZILLON, Alan Stern
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Alan Stern,
Greg Kroah-Hartman, linux-arm-kernel, linux-kernel, linux-usb
Hello Alan,
I don't know if you remember but a few days back I sent a series which
included this patch ("ARM: at91: prepare transition to common clk
framework").
It was decided to move this patch out of the "prepare" series to avoid
backward
compatility handling.
Things have changed a little bit.
I was asked to split the "ARM: at91: move to common clk framework"
series into
several smaller series (one for each SoC).
This means at91 will have some SoCs supporting using common clk framework
(and thus will define the usb_clk) and other SoCs using the old at91 clk
implementation
(which does not define usb_clk).
I was also requested to drop common clk framework support for non dt
boards, which
means, as long as at91 keep non dt boards the at91 old clk implem will
remain active.
For all these reasons I will have to reintroduce the backward
compatibility hack.
Should I get this patch (and patch 27) out of the this series and back
to the "prepare" series ?
Best Regards,
Boris
On 17/07/2013 17:47, Boris BREZILLON wrote:
> The AT91 PMC (Power Management Controller) provides an USB clock used by
> USB Full Speed host (ohci) and USB Full Speed device (udc).
> The usb drivers (ohci and udc) must configure this clock to 48Mhz.
> This configuration was formely done in mach-at91/clock.c, but this
> implementation will be removed when moving to common clk framework.
>
> This patch add support for usb clock retrieval and configuration.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/usb/host/ohci-at91.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index 9677f68..ca1cdd6 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -31,8 +31,8 @@
> #define at91_for_each_port(index) \
> for ((index) = 0; (index) < AT91_MAX_USBH_PORTS; (index)++)
>
> -/* interface and function clocks; sometimes also an AHB clock */
> -static struct clk *iclk, *fclk, *hclk;
> +/* interface, function and usb clocks; sometimes also an AHB clock */
> +static struct clk *iclk, *fclk, *uclk, *hclk;
> static int clocked;
>
> extern int usb_disabled(void);
> @@ -41,6 +41,8 @@ extern int usb_disabled(void);
>
> static void at91_start_clock(void)
> {
> + clk_set_rate(uclk, 48000000);
> + clk_prepare_enable(uclk);
> clk_prepare_enable(hclk);
> clk_prepare_enable(iclk);
> clk_prepare_enable(fclk);
> @@ -52,6 +54,7 @@ static void at91_stop_clock(void)
> clk_disable_unprepare(fclk);
> clk_disable_unprepare(iclk);
> clk_disable_unprepare(hclk);
> + clk_disable_unprepare(uclk);
> clocked = 0;
> }
>
> @@ -162,6 +165,12 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
> retval = PTR_ERR(hclk);
> goto err5;
> }
> + uclk = clk_get(&pdev->dev, "usb_clk");
> + if (IS_ERR(uclk)) {
> + dev_err(&pdev->dev, "failed to get usb_clk\n");
> + retval = PTR_ERR(uclk);
> + goto err6;
> + }
>
> at91_start_hc(pdev);
> ohci_hcd_init(hcd_to_ohci(hcd));
> @@ -173,6 +182,8 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
> /* Error handling */
> at91_stop_hc(pdev);
>
> + clk_put(uclk);
> + err6:
> clk_put(hclk);
> err5:
> clk_put(fclk);
> @@ -212,6 +223,7 @@ static void usb_hcd_at91_remove(struct usb_hcd *hcd,
> release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
> usb_put_hcd(hcd);
>
> + clk_put(uclk);
> clk_put(hclk);
> clk_put(fclk);
> clk_put(iclk);
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
@ 2013-07-31 7:56 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-31 7:56 UTC (permalink / raw)
To: linux-arm-kernel
Hello Alan,
I don't know if you remember but a few days back I sent a series which
included this patch ("ARM: at91: prepare transition to common clk
framework").
It was decided to move this patch out of the "prepare" series to avoid
backward
compatility handling.
Things have changed a little bit.
I was asked to split the "ARM: at91: move to common clk framework"
series into
several smaller series (one for each SoC).
This means at91 will have some SoCs supporting using common clk framework
(and thus will define the usb_clk) and other SoCs using the old at91 clk
implementation
(which does not define usb_clk).
I was also requested to drop common clk framework support for non dt
boards, which
means, as long as at91 keep non dt boards the at91 old clk implem will
remain active.
For all these reasons I will have to reintroduce the backward
compatibility hack.
Should I get this patch (and patch 27) out of the this series and back
to the "prepare" series ?
Best Regards,
Boris
On 17/07/2013 17:47, Boris BREZILLON wrote:
> The AT91 PMC (Power Management Controller) provides an USB clock used by
> USB Full Speed host (ohci) and USB Full Speed device (udc).
> The usb drivers (ohci and udc) must configure this clock to 48Mhz.
> This configuration was formely done in mach-at91/clock.c, but this
> implementation will be removed when moving to common clk framework.
>
> This patch add support for usb clock retrieval and configuration.
>
> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
> ---
> drivers/usb/host/ohci-at91.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index 9677f68..ca1cdd6 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -31,8 +31,8 @@
> #define at91_for_each_port(index) \
> for ((index) = 0; (index) < AT91_MAX_USBH_PORTS; (index)++)
>
> -/* interface and function clocks; sometimes also an AHB clock */
> -static struct clk *iclk, *fclk, *hclk;
> +/* interface, function and usb clocks; sometimes also an AHB clock */
> +static struct clk *iclk, *fclk, *uclk, *hclk;
> static int clocked;
>
> extern int usb_disabled(void);
> @@ -41,6 +41,8 @@ extern int usb_disabled(void);
>
> static void at91_start_clock(void)
> {
> + clk_set_rate(uclk, 48000000);
> + clk_prepare_enable(uclk);
> clk_prepare_enable(hclk);
> clk_prepare_enable(iclk);
> clk_prepare_enable(fclk);
> @@ -52,6 +54,7 @@ static void at91_stop_clock(void)
> clk_disable_unprepare(fclk);
> clk_disable_unprepare(iclk);
> clk_disable_unprepare(hclk);
> + clk_disable_unprepare(uclk);
> clocked = 0;
> }
>
> @@ -162,6 +165,12 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
> retval = PTR_ERR(hclk);
> goto err5;
> }
> + uclk = clk_get(&pdev->dev, "usb_clk");
> + if (IS_ERR(uclk)) {
> + dev_err(&pdev->dev, "failed to get usb_clk\n");
> + retval = PTR_ERR(uclk);
> + goto err6;
> + }
>
> at91_start_hc(pdev);
> ohci_hcd_init(hcd_to_ohci(hcd));
> @@ -173,6 +182,8 @@ static int usb_hcd_at91_probe(const struct hc_driver *driver,
> /* Error handling */
> at91_stop_hc(pdev);
>
> + clk_put(uclk);
> + err6:
> clk_put(hclk);
> err5:
> clk_put(fclk);
> @@ -212,6 +223,7 @@ static void usb_hcd_at91_remove(struct usb_hcd *hcd,
> release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
> usb_put_hcd(hcd);
>
> + clk_put(uclk);
> clk_put(hclk);
> clk_put(fclk);
> clk_put(iclk);
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
2013-07-31 7:56 ` boris brezillon
@ 2013-07-31 14:32 ` Alan Stern
-1 siblings, 0 replies; 129+ messages in thread
From: Alan Stern @ 2013-07-31 14:32 UTC (permalink / raw)
To: boris brezillon
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette,
Greg Kroah-Hartman, linux-arm-kernel, linux-kernel, linux-usb
On Wed, 31 Jul 2013, boris brezillon wrote:
> Hello Alan,
>
> I don't know if you remember but a few days back I sent a series which
> included this patch ("ARM: at91: prepare transition to common clk
> framework").
>
> It was decided to move this patch out of the "prepare" series to avoid
> backward
> compatility handling.
>
> Things have changed a little bit.
>
> I was asked to split the "ARM: at91: move to common clk framework"
> series into
> several smaller series (one for each SoC).
> This means at91 will have some SoCs supporting using common clk framework
> (and thus will define the usb_clk) and other SoCs using the old at91 clk
> implementation
> (which does not define usb_clk).
>
> I was also requested to drop common clk framework support for non dt
> boards, which
> means, as long as at91 keep non dt boards the at91 old clk implem will
> remain active.
>
> For all these reasons I will have to reintroduce the backward
> compatibility hack.
>
> Should I get this patch (and patch 27) out of the this series and back
> to the "prepare" series ?
I don't care too much how the two patch series are organized, although
some of the other maintainers involved in this project might. So long
as everything remains compatible with all the hardware variations and
bisectable at each stage, I'll be happy.
Alan Stern
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 26/42] USB: ohci-at91: add usb_clk for transition to common clk framework
@ 2013-07-31 14:32 ` Alan Stern
0 siblings, 0 replies; 129+ messages in thread
From: Alan Stern @ 2013-07-31 14:32 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 31 Jul 2013, boris brezillon wrote:
> Hello Alan,
>
> I don't know if you remember but a few days back I sent a series which
> included this patch ("ARM: at91: prepare transition to common clk
> framework").
>
> It was decided to move this patch out of the "prepare" series to avoid
> backward
> compatility handling.
>
> Things have changed a little bit.
>
> I was asked to split the "ARM: at91: move to common clk framework"
> series into
> several smaller series (one for each SoC).
> This means at91 will have some SoCs supporting using common clk framework
> (and thus will define the usb_clk) and other SoCs using the old at91 clk
> implementation
> (which does not define usb_clk).
>
> I was also requested to drop common clk framework support for non dt
> boards, which
> means, as long as at91 keep non dt boards the at91 old clk implem will
> remain active.
>
> For all these reasons I will have to reintroduce the backward
> compatibility hack.
>
> Should I get this patch (and patch 27) out of the this series and back
> to the "prepare" series ?
I don't care too much how the two patch series are organized, although
some of the other maintainers involved in this project might. So long
as everything remains compatible with all the hardware variations and
bisectable at each stage, I'll be happy.
Alan Stern
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 27/42] usb: gadget: at91_udc: add usb_clk for transition to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:49 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:49 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Felipe Balbi,
Greg Kroah-Hartman
Cc: linux-arm-kernel, linux-kernel, linux-usb, Boris BREZILLON
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed when moving to common clk framework.
This patch add support for usb clock retrieval and configuration.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/usb/gadget/at91_udc.c | 31 ++++++++++++++++++++++++++-----
drivers/usb/gadget/at91_udc.h | 2 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index fce8e4e..05aac04 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -870,6 +870,8 @@ static void clk_on(struct at91_udc *udc)
if (udc->clocked)
return;
udc->clocked = 1;
+ clk_set_rate(udc->uclk, 48000000);
+ clk_prepare_enable(udc->uclk);
clk_prepare_enable(udc->iclk);
clk_prepare_enable(udc->fclk);
}
@@ -882,6 +884,7 @@ static void clk_off(struct at91_udc *udc)
udc->gadget.speed = USB_SPEED_UNKNOWN;
clk_disable_unprepare(udc->fclk);
clk_disable_unprepare(udc->iclk);
+ clk_disable_unprepare(udc->uclk);
}
/*
@@ -1773,18 +1776,28 @@ static int at91udc_probe(struct platform_device *pdev)
/* get interface and function clocks */
udc->iclk = clk_get(dev, "udc_clk");
- udc->fclk = clk_get(dev, "udpck");
- if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) {
- DBG("clocks missing\n");
+ if (IS_ERR(udc->iclk)) {
+ DBG("interface clock missing\n");
retval = -ENODEV;
- /* NOTE: we "know" here that refcounts on these are NOPs */
goto fail1;
}
+ udc->fclk = clk_get(dev, "udpck");
+ if (IS_ERR(udc->fclk)) {
+ DBG("function clock missing\n");
+ retval = -ENODEV;
+ goto fail1a;
+ }
+ udc->uclk = clk_get(dev, "usb_clk");
+ if (IS_ERR(udc->uclk)) {
+ DBG("usb clock missing\n");
+ retval = -ENODEV;
+ goto fail1b;
+ }
/* don't do anything until we have both gadget driver and VBUS */
retval = clk_prepare_enable(udc->iclk);
if (retval)
- goto fail1;
+ goto fail1c;
at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff);
/* Clear all pending interrupts - UDP may be used by bootloader. */
@@ -1850,6 +1863,13 @@ fail3:
gpio_free(udc->board.vbus_pin);
fail2:
free_irq(udc->udp_irq, udc);
+
+fail1c:
+ clk_put(udc->uclk);
+fail1b:
+ clk_put(udc->fclk);
+fail1a:
+ clk_put(udc->iclk);
fail1:
iounmap(udc->udp_baseaddr);
fail0a:
@@ -1894,6 +1914,7 @@ static int __exit at91udc_remove(struct platform_device *pdev)
clk_put(udc->iclk);
clk_put(udc->fclk);
+ clk_put(udc->uclk);
return 0;
}
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index e647d1c..0175246 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -126,7 +126,7 @@ struct at91_udc {
unsigned active_suspend:1;
u8 addr;
struct at91_udc_data board;
- struct clk *iclk, *fclk;
+ struct clk *iclk, *fclk, *uclk;
struct platform_device *pdev;
struct proc_dir_entry *pde;
void __iomem *udp_baseaddr;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 27/42] usb: gadget: at91_udc: add usb_clk for transition to common clk framework
@ 2013-07-17 15:49 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:49 UTC (permalink / raw)
To: linux-arm-kernel
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed when moving to common clk framework.
This patch add support for usb clock retrieval and configuration.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
drivers/usb/gadget/at91_udc.c | 31 ++++++++++++++++++++++++++-----
drivers/usb/gadget/at91_udc.h | 2 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index fce8e4e..05aac04 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -870,6 +870,8 @@ static void clk_on(struct at91_udc *udc)
if (udc->clocked)
return;
udc->clocked = 1;
+ clk_set_rate(udc->uclk, 48000000);
+ clk_prepare_enable(udc->uclk);
clk_prepare_enable(udc->iclk);
clk_prepare_enable(udc->fclk);
}
@@ -882,6 +884,7 @@ static void clk_off(struct at91_udc *udc)
udc->gadget.speed = USB_SPEED_UNKNOWN;
clk_disable_unprepare(udc->fclk);
clk_disable_unprepare(udc->iclk);
+ clk_disable_unprepare(udc->uclk);
}
/*
@@ -1773,18 +1776,28 @@ static int at91udc_probe(struct platform_device *pdev)
/* get interface and function clocks */
udc->iclk = clk_get(dev, "udc_clk");
- udc->fclk = clk_get(dev, "udpck");
- if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) {
- DBG("clocks missing\n");
+ if (IS_ERR(udc->iclk)) {
+ DBG("interface clock missing\n");
retval = -ENODEV;
- /* NOTE: we "know" here that refcounts on these are NOPs */
goto fail1;
}
+ udc->fclk = clk_get(dev, "udpck");
+ if (IS_ERR(udc->fclk)) {
+ DBG("function clock missing\n");
+ retval = -ENODEV;
+ goto fail1a;
+ }
+ udc->uclk = clk_get(dev, "usb_clk");
+ if (IS_ERR(udc->uclk)) {
+ DBG("usb clock missing\n");
+ retval = -ENODEV;
+ goto fail1b;
+ }
/* don't do anything until we have both gadget driver and VBUS */
retval = clk_prepare_enable(udc->iclk);
if (retval)
- goto fail1;
+ goto fail1c;
at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff);
/* Clear all pending interrupts - UDP may be used by bootloader. */
@@ -1850,6 +1863,13 @@ fail3:
gpio_free(udc->board.vbus_pin);
fail2:
free_irq(udc->udp_irq, udc);
+
+fail1c:
+ clk_put(udc->uclk);
+fail1b:
+ clk_put(udc->fclk);
+fail1a:
+ clk_put(udc->iclk);
fail1:
iounmap(udc->udp_baseaddr);
fail0a:
@@ -1894,6 +1914,7 @@ static int __exit at91udc_remove(struct platform_device *pdev)
clk_put(udc->iclk);
clk_put(udc->fclk);
+ clk_put(udc->uclk);
return 0;
}
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index e647d1c..0175246 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -126,7 +126,7 @@ struct at91_udc {
unsigned active_suspend:1;
u8 addr;
struct at91_udc_data board;
- struct clk *iclk, *fclk;
+ struct clk *iclk, *fclk, *uclk;
struct platform_device *pdev;
struct proc_dir_entry *pde;
void __iomem *udp_baseaddr;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 28/42] ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:51 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:51 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Joachim Eastwood, Lorenzo Pieralisi
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91rm9200 clocks in at91rm9200 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 92b9e21..5596b1f 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -79,6 +79,204 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 80000000>;
+ divisors = <1 2 3 4>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 0 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+
+ prog2@2 {
+ id = <2>;
+ };
+
+ prog3@3 {
+ id = <3>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck@1 {
+ id = <1>;
+ };
+
+ uhpck@4 {
+ id = <4>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+
+ pck2@10 {
+ id = <10>;
+ };
+
+ pck3@11 {
+ id = <11>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk@2 {
+ id = <2>;
+ };
+
+ pioB_clk@3 {
+ id = <3>;
+ };
+
+ pioC_clk@4 {
+ id = <4>;
+ };
+
+ pioD_clk@5 {
+ id = <5>;
+ };
+
+ usart0_clk@6 {
+ id = <6>;
+ };
+
+ usart1_clk@7 {
+ id = <7>;
+ };
+
+ usart2_clk@8 {
+ id = <8>;
+ };
+
+ usart3_clk@9 {
+ id = <9>;
+ };
+
+ mci_clk@10 {
+ id = <10>;
+ };
+
+ udc_clk@11 {
+ id = <11>;
+ };
+
+ twi_clk@12 {
+ id = <12>;
+ };
+
+ spi_clk@13 {
+ id = <13>;
+ };
+
+ ssc0_clk@14 {
+ id = <14>;
+ };
+
+ ssc1_clk@15 {
+ id = <15>;
+ };
+
+ ssc2_clk@16 {
+ id = <16>;
+ };
+
+ tc0_clk@17 {
+ id = <17>;
+ };
+
+ tc1_clk@18 {
+ id = <18>;
+ };
+
+ tc2_clk@19 {
+ id = <19>;
+ };
+
+ tc3_clk@20 {
+ id = <20>;
+ };
+
+ tc4_clk@21 {
+ id = <21>;
+ };
+
+ tc5_clk@22 {
+ id = <22>;
+ };
+
+ ohci_clk@23 {
+ id = <23>;
+ };
+
+ pclk@24 {
+ id = <24>;
+ };
+ };
};
st: timer@fffffd00 {
@@ -93,6 +291,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffa4000 {
@@ -101,6 +301,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&periph 21>, <&periph 22>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
i2c0: i2c@fffb8000 {
@@ -111,6 +313,7 @@
pinctrl-0 = <&pinctrl_twi>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -120,6 +323,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -129,6 +334,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disable";
};
@@ -138,6 +345,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 15>;
+ clock-names = "pclk";
status = "disable";
};
@@ -147,6 +356,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disable";
};
@@ -157,6 +368,8 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 24>, <&periph 24>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -495,6 +708,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -505,6 +719,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -515,6 +730,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffffa00 {
@@ -525,6 +741,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -534,6 +751,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -545,6 +764,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -556,6 +777,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -567,6 +790,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -578,6 +803,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -585,6 +812,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 11>, <&system 1>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -621,6 +850,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00300000 0x100000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 23>, <&periph 23>, <&system 4>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 28/42] ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
@ 2013-07-17 15:51 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:51 UTC (permalink / raw)
To: linux-arm-kernel
Define at91rm9200 clocks in at91rm9200 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 92b9e21..5596b1f 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -79,6 +79,204 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 80000000>;
+ divisors = <1 2 3 4>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 0 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+
+ prog2 at 2 {
+ id = <2>;
+ };
+
+ prog3 at 3 {
+ id = <3>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck at 1 {
+ id = <1>;
+ };
+
+ uhpck at 4 {
+ id = <4>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+
+ pck2 at 10 {
+ id = <10>;
+ };
+
+ pck3 at 11 {
+ id = <11>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk at 2 {
+ id = <2>;
+ };
+
+ pioB_clk at 3 {
+ id = <3>;
+ };
+
+ pioC_clk at 4 {
+ id = <4>;
+ };
+
+ pioD_clk at 5 {
+ id = <5>;
+ };
+
+ usart0_clk at 6 {
+ id = <6>;
+ };
+
+ usart1_clk at 7 {
+ id = <7>;
+ };
+
+ usart2_clk at 8 {
+ id = <8>;
+ };
+
+ usart3_clk at 9 {
+ id = <9>;
+ };
+
+ mci_clk at 10 {
+ id = <10>;
+ };
+
+ udc_clk at 11 {
+ id = <11>;
+ };
+
+ twi_clk at 12 {
+ id = <12>;
+ };
+
+ spi_clk at 13 {
+ id = <13>;
+ };
+
+ ssc0_clk at 14 {
+ id = <14>;
+ };
+
+ ssc1_clk at 15 {
+ id = <15>;
+ };
+
+ ssc2_clk at 16 {
+ id = <16>;
+ };
+
+ tc0_clk at 17 {
+ id = <17>;
+ };
+
+ tc1_clk at 18 {
+ id = <18>;
+ };
+
+ tc2_clk at 19 {
+ id = <19>;
+ };
+
+ tc3_clk at 20 {
+ id = <20>;
+ };
+
+ tc4_clk at 21 {
+ id = <21>;
+ };
+
+ tc5_clk at 22 {
+ id = <22>;
+ };
+
+ ohci_clk at 23 {
+ id = <23>;
+ };
+
+ pclk at 24 {
+ id = <24>;
+ };
+ };
};
st: timer at fffffd00 {
@@ -93,6 +291,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer at fffa4000 {
@@ -101,6 +301,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&periph 21>, <&periph 22>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
i2c0: i2c at fffb8000 {
@@ -111,6 +313,7 @@
pinctrl-0 = <&pinctrl_twi>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -120,6 +323,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -129,6 +334,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disable";
};
@@ -138,6 +345,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 15>;
+ clock-names = "pclk";
status = "disable";
};
@@ -147,6 +356,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disable";
};
@@ -157,6 +368,8 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 24>, <&periph 24>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -495,6 +708,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff600 {
@@ -505,6 +719,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio at fffff800 {
@@ -515,6 +730,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio at fffffa00 {
@@ -525,6 +741,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -534,6 +751,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -545,6 +764,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -556,6 +777,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -567,6 +790,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -578,6 +803,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -585,6 +812,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 11>, <&system 1>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -621,6 +850,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00300000 0x100000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 23>, <&periph 23>, <&system 4>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 29/42] ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:53 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:53 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Mark Brown, Bo Shen
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9260 clocks in at91sam9260 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9260.dtsi | 236 ++++++++++++++++++++++++++++++++++++
1 file changed, 236 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index c7ccbcb..24b0165 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -48,6 +48,14 @@
reg = <0x20000000 0x04000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -76,6 +84,195 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 5000000>;
+ output = <70000000 130000000>;
+ out = <1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 105000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck@6 {
+ id = <6>;
+ };
+
+ uhpck@7 {
+ id = <7>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk@2 {
+ id = <2>;
+ };
+
+ pioB_clk@3 {
+ id = <3>;
+ };
+
+ pioC_clk@4 {
+ id = <4>;
+ };
+
+ adc_clk@5 {
+ id = <5>;
+ };
+
+ usart0_clk@6 {
+ id = <6>;
+ };
+
+ usart1_clk@7 {
+ id = <7>;
+ };
+
+ usart2_clk@8 {
+ id = <8>;
+ };
+
+ mci_clk@9 {
+ id = <9>;
+ };
+
+ udc_clk@10 {
+ id = <10>;
+ };
+
+ twi_clk@11 {
+ id = <11>;
+ };
+
+ spi0_clk@12 {
+ id = <12>;
+ };
+
+ spi1_clk@13 {
+ id = <13>;
+ };
+
+ ssc_clk@14 {
+ id = <14>;
+ };
+
+ tc0_clk@17 {
+ id = <17>;
+ };
+
+ tc1_clk@18 {
+ id = <18>;
+ };
+
+ tc2_clk@19 {
+ id = <19>;
+ };
+
+ ohci_clk@20 {
+ id = <20>;
+ };
+
+ pclk@21 {
+ id = <21>;
+ };
+
+ isi_clk@22 {
+ id = <22>;
+ };
+
+ usart3@23 {
+ id = <23>;
+ };
+
+ usart4@24 {
+ id = <24>;
+ };
+
+ usart5@25 {
+ id = <25>;
+ };
+
+ tc3_clk@26 {
+ id = <26>;
+ };
+
+ tc4_clk@27 {
+ id = <27>;
+ };
+
+ tc5_clk@28 {
+ id = <28>;
+ };
+ };
};
rstc@fffffd00 {
@@ -92,6 +289,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fffa0000 {
@@ -100,6 +298,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffdc000 {
@@ -108,6 +308,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>, <&periph 27>, <&periph 28>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
pinctrl@fffff400 {
@@ -443,6 +645,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -453,6 +656,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -463,6 +667,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -472,6 +677,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -483,6 +690,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -494,6 +703,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -505,6 +716,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -516,6 +729,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 23>;
+ clock-names = "usart";
status = "disabled";
};
@@ -527,6 +742,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 24>;
+ clock-names = "usart";
status = "disabled";
};
@@ -538,6 +755,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 25>;
+ clock-names = "usart";
status = "disabled";
};
@@ -547,6 +766,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -554,6 +775,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 10>, <&system 6>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -563,6 +786,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -572,6 +796,8 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -581,6 +807,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -592,6 +820,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 12>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -603,6 +833,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -610,6 +842,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 5>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
@@ -673,6 +907,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 20>, <&periph 20>, <&system 7>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 29/42] ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
@ 2013-07-17 15:53 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:53 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9260 clocks in at91sam9260 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9260.dtsi | 236 ++++++++++++++++++++++++++++++++++++
1 file changed, 236 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index c7ccbcb..24b0165 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -48,6 +48,14 @@
reg = <0x20000000 0x04000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -76,6 +84,195 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 5000000>;
+ output = <70000000 130000000>;
+ out = <1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 105000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck at 6 {
+ id = <6>;
+ };
+
+ uhpck at 7 {
+ id = <7>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk at 2 {
+ id = <2>;
+ };
+
+ pioB_clk at 3 {
+ id = <3>;
+ };
+
+ pioC_clk at 4 {
+ id = <4>;
+ };
+
+ adc_clk at 5 {
+ id = <5>;
+ };
+
+ usart0_clk at 6 {
+ id = <6>;
+ };
+
+ usart1_clk at 7 {
+ id = <7>;
+ };
+
+ usart2_clk at 8 {
+ id = <8>;
+ };
+
+ mci_clk at 9 {
+ id = <9>;
+ };
+
+ udc_clk at 10 {
+ id = <10>;
+ };
+
+ twi_clk at 11 {
+ id = <11>;
+ };
+
+ spi0_clk at 12 {
+ id = <12>;
+ };
+
+ spi1_clk at 13 {
+ id = <13>;
+ };
+
+ ssc_clk at 14 {
+ id = <14>;
+ };
+
+ tc0_clk at 17 {
+ id = <17>;
+ };
+
+ tc1_clk at 18 {
+ id = <18>;
+ };
+
+ tc2_clk at 19 {
+ id = <19>;
+ };
+
+ ohci_clk at 20 {
+ id = <20>;
+ };
+
+ pclk at 21 {
+ id = <21>;
+ };
+
+ isi_clk at 22 {
+ id = <22>;
+ };
+
+ usart3 at 23 {
+ id = <23>;
+ };
+
+ usart4 at 24 {
+ id = <24>;
+ };
+
+ usart5 at 25 {
+ id = <25>;
+ };
+
+ tc3_clk at 26 {
+ id = <26>;
+ };
+
+ tc4_clk at 27 {
+ id = <27>;
+ };
+
+ tc5_clk at 28 {
+ id = <28>;
+ };
+ };
};
rstc at fffffd00 {
@@ -92,6 +289,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer at fffa0000 {
@@ -100,6 +298,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer at fffdc000 {
@@ -108,6 +308,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>, <&periph 27>, <&periph 28>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
pinctrl at fffff400 {
@@ -443,6 +645,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff600 {
@@ -453,6 +656,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio at fffff800 {
@@ -463,6 +667,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -472,6 +677,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -483,6 +690,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -494,6 +703,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -505,6 +716,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -516,6 +729,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 23>;
+ clock-names = "usart";
status = "disabled";
};
@@ -527,6 +742,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 24>;
+ clock-names = "usart";
status = "disabled";
};
@@ -538,6 +755,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 25>;
+ clock-names = "usart";
status = "disabled";
};
@@ -547,6 +766,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -554,6 +775,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 10>, <&system 6>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -563,6 +786,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -572,6 +796,8 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -581,6 +807,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -592,6 +820,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 12>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -603,6 +833,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -610,6 +842,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 5>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
@@ -673,6 +907,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 20>, <&periph 20>, <&system 7>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 30/42] ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 15:55 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:55 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Mark Brown, Bo Shen, Wenyou Yang
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9263 clocks in at91sam9263 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9263.dtsi | 237 ++++++++++++++++++++++++++++++++++++
1 file changed, 237 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f..f4b0d3b 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -68,6 +68,208 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 120000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+
+ prog2@2 {
+ id = <2>;
+ };
+
+ prog3@3 {
+ id = <3>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck@6 {
+ id = <6>;
+ };
+
+ uhpck@7 {
+ id = <7>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+
+ pck2@10 {
+ id = <10>;
+ };
+
+ pck3@11 {
+ id = <11>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk@2 {
+ id = <2>;
+ };
+
+ pioB_clk@3 {
+ id = <3>;
+ };
+
+ pioCDE_clk@4 {
+ id = <4>;
+ };
+
+ usart0_clk@7 {
+ id = <7>;
+ };
+
+ usart1_clk@8 {
+ id = <8>;
+ };
+
+ usart2_clk@9 {
+ id = <9>;
+ };
+
+ mci0_clk@10 {
+ id = <10>;
+ };
+
+ mci1_clk@11 {
+ id = <11>;
+ };
+
+ can_clk@12 {
+ id = <12>;
+ };
+
+ twi_clk@13 {
+ id = <13>;
+ };
+
+ spi0_clk@14 {
+ id = <14>;
+ };
+
+ spi1_clk@15 {
+ id = <15>;
+ };
+
+ ssc0_clk@16 {
+ id = <16>;
+ };
+
+ ssc1_clk@17 {
+ id = <17>;
+ };
+
+ ac97_clk@18 {
+ id = <18>;
+ };
+
+ tcb_clk@19 {
+ id = <19>;
+ };
+
+ pwm_clk@20 {
+ id = <20>;
+ };
+
+ pclk@21 {
+ id = <21>;
+ };
+
+ 2dge_clk@23 {
+ id = <23>;
+ };
+
+ udc_clk@24 {
+ id = <24>;
+ };
+
+ isi_clk@25 {
+ id = <25>;
+ };
+
+ lcdc_clk@26 {
+ id = <26>;
+ };
+
+ dma_clk@27 {
+ id = <27>;
+ };
+
+ ohci_clk@29 {
+ id = <29>;
+ };
+ };
};
ramc: ramc@ffffe200 {
@@ -80,12 +282,15 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>;
+ clock-names = "t0_clk";
};
rstc@fffffd00 {
@@ -374,6 +579,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff400 {
@@ -384,6 +590,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff600 {
@@ -394,6 +601,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffff800 {
@@ -404,6 +612,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioE: gpio@fffffa00 {
@@ -414,6 +623,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -423,6 +633,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -434,6 +646,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -445,6 +659,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -456,6 +672,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -465,6 +683,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -474,6 +694,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -483,6 +705,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -490,6 +714,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 24>, <&system 7>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -499,6 +725,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -508,6 +735,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -517,6 +746,8 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -534,6 +765,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -545,6 +778,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
};
@@ -571,6 +806,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 29>, <&periph 29>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 30/42] ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
@ 2013-07-17 15:55 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 15:55 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9263 clocks in at91sam9263 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9263.dtsi | 237 ++++++++++++++++++++++++++++++++++++
1 file changed, 237 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f..f4b0d3b 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -68,6 +68,208 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 120000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+
+ prog2 at 2 {
+ id = <2>;
+ };
+
+ prog3 at 3 {
+ id = <3>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ udpck at 6 {
+ id = <6>;
+ };
+
+ uhpck at 7 {
+ id = <7>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+
+ pck2 at 10 {
+ id = <10>;
+ };
+
+ pck3 at 11 {
+ id = <11>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk at 2 {
+ id = <2>;
+ };
+
+ pioB_clk at 3 {
+ id = <3>;
+ };
+
+ pioCDE_clk at 4 {
+ id = <4>;
+ };
+
+ usart0_clk at 7 {
+ id = <7>;
+ };
+
+ usart1_clk at 8 {
+ id = <8>;
+ };
+
+ usart2_clk at 9 {
+ id = <9>;
+ };
+
+ mci0_clk at 10 {
+ id = <10>;
+ };
+
+ mci1_clk at 11 {
+ id = <11>;
+ };
+
+ can_clk at 12 {
+ id = <12>;
+ };
+
+ twi_clk at 13 {
+ id = <13>;
+ };
+
+ spi0_clk at 14 {
+ id = <14>;
+ };
+
+ spi1_clk at 15 {
+ id = <15>;
+ };
+
+ ssc0_clk at 16 {
+ id = <16>;
+ };
+
+ ssc1_clk at 17 {
+ id = <17>;
+ };
+
+ ac97_clk at 18 {
+ id = <18>;
+ };
+
+ tcb_clk at 19 {
+ id = <19>;
+ };
+
+ pwm_clk at 20 {
+ id = <20>;
+ };
+
+ pclk at 21 {
+ id = <21>;
+ };
+
+ 2dge_clk at 23 {
+ id = <23>;
+ };
+
+ udc_clk at 24 {
+ id = <24>;
+ };
+
+ isi_clk at 25 {
+ id = <25>;
+ };
+
+ lcdc_clk at 26 {
+ id = <26>;
+ };
+
+ dma_clk at 27 {
+ id = <27>;
+ };
+
+ ohci_clk at 29 {
+ id = <29>;
+ };
+ };
};
ramc: ramc at ffffe200 {
@@ -80,12 +282,15 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer at fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>;
+ clock-names = "t0_clk";
};
rstc at fffffd00 {
@@ -374,6 +579,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff400 {
@@ -384,6 +590,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio at fffff600 {
@@ -394,6 +601,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio at fffff800 {
@@ -404,6 +612,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioE: gpio at fffffa00 {
@@ -414,6 +623,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -423,6 +633,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -434,6 +646,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -445,6 +659,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -456,6 +672,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -465,6 +683,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -474,6 +694,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -483,6 +705,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -490,6 +714,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 24>, <&system 7>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -499,6 +725,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -508,6 +735,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -517,6 +746,8 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -534,6 +765,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -545,6 +778,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
};
@@ -571,6 +806,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 29>, <&periph 29>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 31/42] ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 16:00 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:00 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Mark Brown, Bo Shen
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9g45 clocks in at91sam9g45 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g45.dtsi | 257 ++++++++++++++++++++++++++++++++++++
1 file changed, 257 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e5148..dfca115 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -52,6 +52,14 @@
reg = <0x70000000 0x10000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -81,6 +89,211 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck@2 {
+ id = <2>;
+ };
+
+ uhpck@6 {
+ id = <6>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk@2 {
+ id = <2>;
+ };
+
+ pioB_clk@3 {
+ id = <3>;
+ };
+
+ pioC_clk@4 {
+ id = <4>;
+ };
+
+ pioDE_clk@5 {
+ id = <5>;
+ };
+
+ trng_clk@6 {
+ id = <6>;
+ };
+
+ usart0_clk@7 {
+ id = <7>;
+ };
+
+ usart1_clk@8 {
+ id = <8>;
+ };
+
+ usart2_clk@9 {
+ id = <9>;
+ };
+
+ usart3_clk@10 {
+ id = <10>;
+ };
+
+ mci0_clk@11 {
+ id = <11>;
+ };
+
+ twi0_clk@12 {
+ id = <12>;
+ };
+
+ twi1_clk@13 {
+ id = <13>;
+ };
+
+ spi0_clk@14 {
+ id = <14>;
+ };
+
+ spi1_clk@15 {
+ id = <15>;
+ };
+
+ ssc0_clk@16 {
+ id = <16>;
+ };
+
+ ssc1_clk@17 {
+ id = <17>;
+ };
+
+ tcb0_clk@18 {
+ id = <18>;
+ };
+
+ pwm_clk@19 {
+ id = <19>;
+ };
+
+ tsc_clk@20 {
+ id = <20>;
+ };
+
+ dma_clk@21 {
+ id = <21>;
+ };
+
+ uhphs_clk@22 {
+ id = <22>;
+ };
+
+ lcdc_clk@23 {
+ id = <23>;
+ };
+
+ ac97_clk@24 {
+ id = <24>;
+ };
+
+ pclk@25 {
+ id = <25>;
+ };
+
+ isi_clk@26 {
+ id = <26>;
+ };
+
+ udphs_clk@27 {
+ id = <27>;
+ };
+
+ mci1_clk@29 {
+ id = <29>;
+ };
+ };
};
rstc@fffffd00 {
@@ -92,6 +305,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
@@ -104,12 +318,16 @@
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
dma: dma-controller@ffffec00 {
@@ -117,6 +335,8 @@
reg = <0xffffec00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl@fffff200 {
@@ -433,6 +653,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff400 {
@@ -443,6 +664,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff600 {
@@ -453,6 +675,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffff800 {
@@ -463,6 +686,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
pioE: gpio@fffffa00 {
@@ -473,6 +697,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -482,6 +707,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -493,6 +720,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -504,6 +733,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -515,6 +746,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -526,6 +759,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 10>;
+ clock-names = "usart";
status = "disabled";
};
@@ -535,6 +770,8 @@
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 25>, <&periph 25>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -544,6 +781,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -553,6 +791,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -562,6 +801,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -571,6 +812,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -578,6 +821,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>;
@@ -622,6 +867,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -633,6 +880,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -650,6 +899,8 @@
interrupts = <14 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -661,6 +912,8 @@
interrupts = <15 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -749,6 +1002,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -756,6 +1011,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 31/42] ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
@ 2013-07-17 16:00 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9g45 clocks in at91sam9g45 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g45.dtsi | 257 ++++++++++++++++++++++++++++++++++++
1 file changed, 257 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e5148..dfca115 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -52,6 +52,14 @@
reg = <0x70000000 0x10000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -81,6 +89,211 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck at 2 {
+ id = <2>;
+ };
+
+ uhpck at 6 {
+ id = <6>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioA_clk at 2 {
+ id = <2>;
+ };
+
+ pioB_clk at 3 {
+ id = <3>;
+ };
+
+ pioC_clk at 4 {
+ id = <4>;
+ };
+
+ pioDE_clk at 5 {
+ id = <5>;
+ };
+
+ trng_clk at 6 {
+ id = <6>;
+ };
+
+ usart0_clk at 7 {
+ id = <7>;
+ };
+
+ usart1_clk at 8 {
+ id = <8>;
+ };
+
+ usart2_clk at 9 {
+ id = <9>;
+ };
+
+ usart3_clk at 10 {
+ id = <10>;
+ };
+
+ mci0_clk at 11 {
+ id = <11>;
+ };
+
+ twi0_clk at 12 {
+ id = <12>;
+ };
+
+ twi1_clk at 13 {
+ id = <13>;
+ };
+
+ spi0_clk at 14 {
+ id = <14>;
+ };
+
+ spi1_clk at 15 {
+ id = <15>;
+ };
+
+ ssc0_clk at 16 {
+ id = <16>;
+ };
+
+ ssc1_clk at 17 {
+ id = <17>;
+ };
+
+ tcb0_clk at 18 {
+ id = <18>;
+ };
+
+ pwm_clk at 19 {
+ id = <19>;
+ };
+
+ tsc_clk at 20 {
+ id = <20>;
+ };
+
+ dma_clk at 21 {
+ id = <21>;
+ };
+
+ uhphs_clk at 22 {
+ id = <22>;
+ };
+
+ lcdc_clk at 23 {
+ id = <23>;
+ };
+
+ ac97_clk at 24 {
+ id = <24>;
+ };
+
+ pclk at 25 {
+ id = <25>;
+ };
+
+ isi_clk at 26 {
+ id = <26>;
+ };
+
+ udphs_clk at 27 {
+ id = <27>;
+ };
+
+ mci1_clk at 29 {
+ id = <29>;
+ };
+ };
};
rstc at fffffd00 {
@@ -92,6 +305,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
@@ -104,12 +318,16 @@
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
tcb1: timer at fffd4000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
dma: dma-controller at ffffec00 {
@@ -117,6 +335,8 @@
reg = <0xffffec00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl at fffff200 {
@@ -433,6 +653,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff400 {
@@ -443,6 +664,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio at fffff600 {
@@ -453,6 +675,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio at fffff800 {
@@ -463,6 +686,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
pioE: gpio at fffffa00 {
@@ -473,6 +697,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -482,6 +707,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -493,6 +720,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -504,6 +733,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -515,6 +746,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -526,6 +759,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 10>;
+ clock-names = "usart";
status = "disabled";
};
@@ -535,6 +770,8 @@
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 25>, <&periph 25>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -544,6 +781,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -553,6 +791,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -562,6 +801,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -571,6 +812,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -578,6 +821,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>;
@@ -622,6 +867,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -633,6 +880,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -650,6 +899,8 @@
interrupts = <14 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -661,6 +912,8 @@
interrupts = <15 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -749,6 +1002,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -756,6 +1011,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 32/42] ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 16:02 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:02 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Wenyou Yang
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9n12 clocks in at91sam9n12 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 251 ++++++++++++++++++++++++++++++++++++
1 file changed, 251 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bb7f564..a12ad9f 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -76,6 +76,224 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ usbs0-unused;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck@2 {
+ id = <2>;
+ };
+
+ lcdck@3 {
+ id = <3>;
+ };
+
+ uhpck@6 {
+ id = <6>;
+ };
+
+ udpck@7 {
+ id = <7>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioAB_clk@2 {
+ id = <2>;
+ };
+
+ pioCD_clk@3 {
+ id = <3>;
+ };
+
+ fuse_clk@4 {
+ id = <4>;
+ };
+
+ usart0_clk@5 {
+ id = <5>;
+ };
+
+ usart1_clk@6 {
+ id = <6>;
+ };
+
+ usart2_clk@7 {
+ id = <7>;
+ };
+
+ usart3_clk@8 {
+ id = <8>;
+ };
+
+ twi0_ck@9 {
+ id = <9>;
+ };
+
+ twi1_ck@10 {
+ id = <10>;
+ };
+
+ hsmci_clk@12 {
+ id = <12>;
+ };
+
+ spi0_clk@13 {
+ id = <13>;
+ };
+
+ spi1_clk@14 {
+ id = <14>;
+ };
+
+ uart0_clk@15 {
+ id = <15>;
+ };
+
+ uart1_clk@16 {
+ id = <16>;
+ };
+
+ tcb_clk@17 {
+ id = <17>;
+ };
+
+ pwm_clk@18 {
+ id = <18>;
+ };
+
+ adc_clk@19 {
+ id = <19>;
+ };
+
+ dma_clk@20 {
+ id = <20>;
+ };
+
+ uhp_clk@22 {
+ id = <22>;
+ };
+
+ udc_clk@23 {
+ id = <23>;
+ };
+
+ lcdc_clk@25 {
+ id = <25>;
+ };
+
+ sha_clk@27 {
+ id = <27>;
+ };
+
+ ssc_clk@28 {
+ id = <28>;
+ };
+
+ aes_clk@29 {
+ id = <29>;
+ };
+
+ trng_clk@30 {
+ id = <30>;
+ };
+ };
};
rstc@fffffe00 {
@@ -87,6 +305,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
shdwc@fffffe10 {
@@ -102,6 +321,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -109,12 +330,16 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma: dma-controller@ffffec00 {
@@ -122,6 +347,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
pinctrl@fffff400 {
@@ -375,6 +602,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -385,6 +613,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio@fffff800 {
@@ -395,6 +624,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio@fffffa00 {
@@ -405,6 +635,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -414,6 +645,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -423,6 +656,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -432,6 +667,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -441,6 +678,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -450,6 +689,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -459,6 +700,8 @@
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -471,6 +714,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -483,6 +727,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -497,6 +742,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -511,6 +758,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -546,6 +795,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 32/42] ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
@ 2013-07-17 16:02 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:02 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9n12 clocks in at91sam9n12 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 251 ++++++++++++++++++++++++++++++++++++
1 file changed, 251 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bb7f564..a12ad9f 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -76,6 +76,224 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ usbs0-unused;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck at 2 {
+ id = <2>;
+ };
+
+ lcdck at 3 {
+ id = <3>;
+ };
+
+ uhpck at 6 {
+ id = <6>;
+ };
+
+ udpck at 7 {
+ id = <7>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioAB_clk at 2 {
+ id = <2>;
+ };
+
+ pioCD_clk at 3 {
+ id = <3>;
+ };
+
+ fuse_clk at 4 {
+ id = <4>;
+ };
+
+ usart0_clk at 5 {
+ id = <5>;
+ };
+
+ usart1_clk at 6 {
+ id = <6>;
+ };
+
+ usart2_clk at 7 {
+ id = <7>;
+ };
+
+ usart3_clk at 8 {
+ id = <8>;
+ };
+
+ twi0_ck at 9 {
+ id = <9>;
+ };
+
+ twi1_ck at 10 {
+ id = <10>;
+ };
+
+ hsmci_clk at 12 {
+ id = <12>;
+ };
+
+ spi0_clk at 13 {
+ id = <13>;
+ };
+
+ spi1_clk at 14 {
+ id = <14>;
+ };
+
+ uart0_clk at 15 {
+ id = <15>;
+ };
+
+ uart1_clk at 16 {
+ id = <16>;
+ };
+
+ tcb_clk at 17 {
+ id = <17>;
+ };
+
+ pwm_clk at 18 {
+ id = <18>;
+ };
+
+ adc_clk at 19 {
+ id = <19>;
+ };
+
+ dma_clk at 20 {
+ id = <20>;
+ };
+
+ uhp_clk at 22 {
+ id = <22>;
+ };
+
+ udc_clk at 23 {
+ id = <23>;
+ };
+
+ lcdc_clk at 25 {
+ id = <25>;
+ };
+
+ sha_clk at 27 {
+ id = <27>;
+ };
+
+ ssc_clk at 28 {
+ id = <28>;
+ };
+
+ aes_clk at 29 {
+ id = <29>;
+ };
+
+ trng_clk at 30 {
+ id = <30>;
+ };
+ };
};
rstc at fffffe00 {
@@ -87,6 +305,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
shdwc at fffffe10 {
@@ -102,6 +321,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -109,12 +330,16 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer at f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma: dma-controller at ffffec00 {
@@ -122,6 +347,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
pinctrl at fffff400 {
@@ -375,6 +602,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff600 {
@@ -385,6 +613,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio at fffff800 {
@@ -395,6 +624,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio at fffffa00 {
@@ -405,6 +635,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -414,6 +645,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -423,6 +656,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -432,6 +667,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -441,6 +678,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -450,6 +689,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -459,6 +700,8 @@
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -471,6 +714,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -483,6 +727,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -497,6 +742,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -511,6 +758,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -546,6 +795,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 33/42] ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 16:05 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:05 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Linus Walleij, Richard Genoud
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9x5 clocks in at91sam9x5 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
arch/arm/boot/dts/at91sam9x25.dtsi | 25 +--
arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++++++++++++++++++++-------
arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +++
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +++
arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +++
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 +++++++
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 +++++
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++++++
12 files changed, 519 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index cfd7044..e0d8d84 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
/ {
model = "Atmel AT91SAM9G15 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index b4ec6fe..49f5122 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index bebf9f5..cde7626 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -7,6 +7,8 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 49e94ab..3c5fa33 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -7,6 +7,10 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X25 SoC";
@@ -22,27 +26,6 @@
0x80000000 0xfffd0000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
- AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
- AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
- AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
- AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
- AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
- AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
- AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
- AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
- AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
- };
- };
- };
-
- macb1: ethernet@f8030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 1a3d525..ecbdf5d 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 57d45f5..1dd5d11 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -50,6 +50,14 @@
reg = <0x20000000 0x10000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -78,6 +86,210 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ have-div3-pres;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+ };
+
+ smd: smdclk {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck@2 {
+ id = <2>;
+ };
+
+ smdck@4 {
+ id = <4>;
+ };
+
+ udpck@6 {
+ id = <6>;
+ };
+
+ uhpck@7 {
+ id = <7>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioAB_clk@2 {
+ id = <2>;
+ };
+
+ pioCD_clk@3 {
+ id = <3>;
+ };
+
+ smd_clk@4 {
+ id = <4>;
+ };
+
+ usart0_clk@5 {
+ id = <5>;
+ };
+
+ usart1_clk@6 {
+ id = <6>;
+ };
+
+ usart2_clk@7 {
+ id = <7>;
+ };
+
+ twi0_clk@9 {
+ id = <9>;
+ };
+
+ twi1_clk@10 {
+ id = <10>;
+ };
+
+ twi2_clk@11 {
+ id = <11>;
+ };
+
+ mci0_clk@12 {
+ id = <12>;
+ };
+
+ spi0_clk@13 {
+ id = <13>;
+ };
+
+ spi1_clk@14 {
+ id = <14>;
+ };
+
+ uart0_clk@15 {
+ id = <15>;
+ };
+
+ uart1_clk@16 {
+ id = <16>;
+ };
+
+ tcb_clk@17 {
+ id = <17>;
+ };
+
+ pwm_clk@18 {
+ id = <18>;
+ };
+
+ adc_clk@19 {
+ id = <19>;
+ };
+
+ dma0_clk@20 {
+ id = <20>;
+ };
+
+ dma1_clk@21 {
+ id = <21>;
+ };
+
+ uhphs_clk@22 {
+ id = <22>;
+ };
+
+ udphs_clk@23 {
+ id = <23>;
+ };
+
+ mci1_clk@26 {
+ id = <26>;
+ };
+
+ ssc_clk@27 {
+ id = <27>;
+ };
+ };
};
rstc@fffffe00 {
@@ -94,18 +306,23 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma0: dma-controller@ffffec00 {
@@ -113,6 +330,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
dma1: dma-controller@ffffee00 {
@@ -120,6 +339,8 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl@fffff400 {
@@ -206,29 +427,6 @@
};
};
- usart3 {
- pinctrl_usart3: usart3-0 {
- atmel,pins =
- <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
- AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
- };
-
- pinctrl_usart3_rts: usart3_rts-0 {
- atmel,pins =
- <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
- };
-
- pinctrl_usart3_cts: usart3_cts-0 {
- atmel,pins =
- <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
- };
-
- pinctrl_usart3_sck: usart3_sck-0 {
- atmel,pins =
- <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
- };
- };
-
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
@@ -277,34 +475,6 @@
};
};
- macb0 {
- pinctrl_macb0_rmii: macb0_rmii-0 {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
- };
-
- pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
- };
- };
-
mmc0 {
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
atmel,pins =
@@ -503,6 +673,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -514,6 +685,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio@fffff800 {
@@ -524,6 +696,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio@fffffa00 {
@@ -535,6 +708,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -544,6 +718,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -555,6 +731,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -566,6 +744,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 26>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -575,6 +755,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -584,6 +766,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -593,6 +777,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -602,22 +788,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- status = "disabled";
- };
-
- macb0: ethernet@f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_rmii>;
- status = "disabled";
- };
-
- macb1: ethernet@f8030000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf8030000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -632,6 +804,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -646,6 +819,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -660,6 +834,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -685,6 +860,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external;
atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>;
@@ -733,6 +910,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -747,6 +926,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -851,6 +1032,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -858,6 +1041,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
new file mode 100644
index 0000000..e6db2f2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -0,0 +1,26 @@
+/*
+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ can0_clk@29 {
+ id = <29>;
+ };
+
+ can1_clk@30 {
+ id = <30>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
new file mode 100644
index 0000000..593c9e4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -0,0 +1,22 @@
+/*
+ * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * ISI (Image Sensor Interface) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ isi_clk@25 {
+ id = <25>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
new file mode 100644
index 0000000..5e04c50
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCDC (LCD controller) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ system: systemck {
+ lcdck@3 {
+ id = <3>;
+ };
+ };
+
+ periph: periphck {
+ lcdc_clk@25 {
+ id = <25>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
new file mode 100644
index 0000000..5483e1a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -0,0 +1,66 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+
+ pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ macb0_clk@24 {
+ id = <24>;
+ };
+ };
+ };
+
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clocks = <&periph 24>, <&periph 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
new file mode 100644
index 0000000..d20a680
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -0,0 +1,54 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
+ AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
+ AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
+ AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
+ AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
+ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
+ AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
+ AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
+ AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
+ AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ macb1_clk@27 {
+ id = <27>;
+ };
+ };
+ };
+
+ macb1: ethernet@f8030000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf8030000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 27>, <&periph 27>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
new file mode 100644
index 0000000..292b276
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -0,0 +1,58 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
+ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
+ };
+
+ pinctrl_usart3_sck: usart3_sck-0 {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ usart3_clk@8 {
+ id = <8>;
+ };
+ };
+ };
+
+ usart3: serial@f8028000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf8028000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 33/42] ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
@ 2013-07-17 16:05 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:05 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9x5 clocks in at91sam9x5 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
arch/arm/boot/dts/at91sam9x25.dtsi | 25 +--
arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++++++++++++++++++++-------
arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +++
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +++
arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +++
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 +++++++
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 +++++
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++++++
12 files changed, 519 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index cfd7044..e0d8d84 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
/ {
model = "Atmel AT91SAM9G15 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index b4ec6fe..49f5122 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index bebf9f5..cde7626 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -7,6 +7,8 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 49e94ab..3c5fa33 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -7,6 +7,10 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X25 SoC";
@@ -22,27 +26,6 @@
0x80000000 0xfffd0000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
- AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
- AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
- AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
- AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
- AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
- AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
- AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
- AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
- AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
- };
- };
- };
-
- macb1: ethernet at f8030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 1a3d525..ecbdf5d 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 57d45f5..1dd5d11 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -50,6 +50,14 @@
reg = <0x20000000 0x10000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -78,6 +86,210 @@
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ have-div3-pres;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+ };
+
+ smd: smdclk {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck at 2 {
+ id = <2>;
+ };
+
+ smdck at 4 {
+ id = <4>;
+ };
+
+ udpck at 6 {
+ id = <6>;
+ };
+
+ uhpck at 7 {
+ id = <7>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+
+ pioAB_clk at 2 {
+ id = <2>;
+ };
+
+ pioCD_clk at 3 {
+ id = <3>;
+ };
+
+ smd_clk at 4 {
+ id = <4>;
+ };
+
+ usart0_clk at 5 {
+ id = <5>;
+ };
+
+ usart1_clk at 6 {
+ id = <6>;
+ };
+
+ usart2_clk at 7 {
+ id = <7>;
+ };
+
+ twi0_clk at 9 {
+ id = <9>;
+ };
+
+ twi1_clk at 10 {
+ id = <10>;
+ };
+
+ twi2_clk at 11 {
+ id = <11>;
+ };
+
+ mci0_clk at 12 {
+ id = <12>;
+ };
+
+ spi0_clk at 13 {
+ id = <13>;
+ };
+
+ spi1_clk at 14 {
+ id = <14>;
+ };
+
+ uart0_clk at 15 {
+ id = <15>;
+ };
+
+ uart1_clk at 16 {
+ id = <16>;
+ };
+
+ tcb_clk at 17 {
+ id = <17>;
+ };
+
+ pwm_clk at 18 {
+ id = <18>;
+ };
+
+ adc_clk at 19 {
+ id = <19>;
+ };
+
+ dma0_clk at 20 {
+ id = <20>;
+ };
+
+ dma1_clk at 21 {
+ id = <21>;
+ };
+
+ uhphs_clk at 22 {
+ id = <22>;
+ };
+
+ udphs_clk at 23 {
+ id = <23>;
+ };
+
+ mci1_clk at 26 {
+ id = <26>;
+ };
+
+ ssc_clk at 27 {
+ id = <27>;
+ };
+ };
};
rstc at fffffe00 {
@@ -94,18 +306,23 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer at f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer at f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma0: dma-controller at ffffec00 {
@@ -113,6 +330,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
dma1: dma-controller at ffffee00 {
@@ -120,6 +339,8 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl at fffff400 {
@@ -206,29 +427,6 @@
};
};
- usart3 {
- pinctrl_usart3: usart3-0 {
- atmel,pins =
- <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
- AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
- };
-
- pinctrl_usart3_rts: usart3_rts-0 {
- atmel,pins =
- <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
- };
-
- pinctrl_usart3_cts: usart3_cts-0 {
- atmel,pins =
- <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
- };
-
- pinctrl_usart3_sck: usart3_sck-0 {
- atmel,pins =
- <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
- };
- };
-
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
@@ -277,34 +475,6 @@
};
};
- macb0 {
- pinctrl_macb0_rmii: macb0_rmii-0 {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
- };
-
- pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
- };
- };
-
mmc0 {
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
atmel,pins =
@@ -503,6 +673,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio at fffff600 {
@@ -514,6 +685,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio at fffff800 {
@@ -524,6 +696,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio at fffffa00 {
@@ -535,6 +708,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -544,6 +718,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -555,6 +731,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -566,6 +744,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 26>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -575,6 +755,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -584,6 +766,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -593,6 +777,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -602,22 +788,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- status = "disabled";
- };
-
- macb0: ethernet at f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_rmii>;
- status = "disabled";
- };
-
- macb1: ethernet at f8030000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf8030000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -632,6 +804,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -646,6 +819,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -660,6 +834,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -685,6 +860,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external;
atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>;
@@ -733,6 +910,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -747,6 +926,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -851,6 +1032,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -858,6 +1041,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
new file mode 100644
index 0000000..e6db2f2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -0,0 +1,26 @@
+/*
+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ can0_clk at 29 {
+ id = <29>;
+ };
+
+ can1_clk at 30 {
+ id = <30>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
new file mode 100644
index 0000000..593c9e4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -0,0 +1,22 @@
+/*
+ * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * ISI (Image Sensor Interface) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ isi_clk at 25 {
+ id = <25>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
new file mode 100644
index 0000000..5e04c50
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCDC (LCD controller) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc at fffffc00 {
+ system: systemck {
+ lcdck at 3 {
+ id = <3>;
+ };
+ };
+
+ periph: periphck {
+ lcdc_clk at 25 {
+ id = <25>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
new file mode 100644
index 0000000..5483e1a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -0,0 +1,66 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff400 {
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+
+ pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ macb0_clk at 24 {
+ id = <24>;
+ };
+ };
+ };
+
+ macb0: ethernet at f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clocks = <&periph 24>, <&periph 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
new file mode 100644
index 0000000..d20a680
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -0,0 +1,54 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff400 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
+ AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
+ AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
+ AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
+ AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
+ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
+ AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
+ AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
+ AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
+ AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ macb1_clk at 27 {
+ id = <27>;
+ };
+ };
+ };
+
+ macb1: ethernet at f8030000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf8030000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 27>, <&periph 27>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
new file mode 100644
index 0000000..292b276
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -0,0 +1,58 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff400 {
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
+ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
+ };
+
+ pinctrl_usart3_sck: usart3_sck-0 {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ usart3_clk at 8 {
+ id = <8>;
+ };
+ };
+ };
+
+ usart3: serial at f8028000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf8028000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 34/42] ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 16:45 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:45 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Wolfram Sang
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define at91sam9g20 clocks in at91sam9g20 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g20.dtsi | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index b8e7946..60a20ec 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -25,6 +25,43 @@
adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
+
+ pmc: pmc@fffffc00 {
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91sam9g20-clk-pllb";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <30000000 100000000>;
+ out = <0>;
+ };
+
+ mck: masterck {
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 6>;
+ };
+ };
};
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 34/42] ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
@ 2013-07-17 16:45 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:45 UTC (permalink / raw)
To: linux-arm-kernel
Define at91sam9g20 clocks in at91sam9g20 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9g20.dtsi | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index b8e7946..60a20ec 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -25,6 +25,43 @@
adc0: adc at fffe0000 {
atmel,adc-startup-time = <40>;
};
+
+ pmc: pmc at fffffc00 {
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91sam9g20-clk-pllb";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <30000000 100000000>;
+ out = <0>;
+ };
+
+ mck: masterck {
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 6>;
+ };
+ };
};
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 35/42] ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 16:50 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:50 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Lorenzo Pieralisi
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define sama5d3 clocks in sama5d3 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/sama5d3.dtsi | 510 +++++++++++++++++++++--------------
arch/arm/boot/dts/sama5d3_can.dtsi | 71 +++++
arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++++
arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++++++
arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 +++++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++++
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +++
arch/arm/boot/dts/sama5d3_uart.dtsi | 46 ++++
8 files changed, 729 insertions(+), 203 deletions(-)
create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a1d5e25..6980c4d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -31,7 +31,6 @@
gpio3 = &pioD;
gpio4 = &pioE;
tcb0 = &tcb0;
- tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -52,6 +51,14 @@
reg = <0x20000000 0x8000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -75,6 +82,8 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 21>;
+ clock-names = "mci_clk";
};
spi0: spi@f0004000 {
@@ -88,6 +97,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 24>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -97,15 +108,8 @@
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
- };
-
- can0: can@f000c000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf000c000 0x300>;
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&periph 38>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -113,6 +117,8 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf0010000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>;
+ clock-names = "t0_clk";
};
i2c0: i2c@f0014000 {
@@ -126,6 +132,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 18>;
status = "disabled";
};
@@ -140,6 +147,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 19>;
status = "disabled";
};
@@ -149,6 +157,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 12>;
+ clock-names = "usart";
status = "disabled";
};
@@ -158,15 +168,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- status = "disabled";
- };
-
- macb0: ethernet@f0028000 {
- compatible = "cdns,pc302-gem", "cdns,gem";
- reg = <0xf0028000 0x100>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 13>;
+ clock-names = "usart";
status = "disabled";
};
@@ -188,19 +191,8 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- };
-
- mmc2: mmc@f8004000 {
- compatible = "atmel,hsmci";
- reg = <0xf8004000 0x600>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
- dma-names = "rxtx";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&periph 22>;
+ clock-names = "mci_clk";
};
spi1: spi@f8008000 {
@@ -214,6 +206,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 25>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -223,23 +217,11 @@
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 39>;
+ clock-names = "pclk";
status = "disabled";
};
- can1: can@f8010000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf8010000 0x300>;
- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_rx_tx>;
- };
-
- tcb1: timer@f8014000 {
- compatible = "atmel,at91sam9x5-tcb";
- reg = <0xf8014000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
adc0: adc@f8018000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xf8018000 0x100>;
@@ -260,6 +242,8 @@
&pinctrl_adc0_ad10
&pinctrl_adc0_ad11
>;
+ clocks = <&periph 29>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channel-base = <0x50>;
atmel,adc-channels-used = <0xfff>;
atmel,adc-drdy-mask = <0x1000000>;
@@ -315,6 +299,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 20>;
status = "disabled";
};
@@ -324,6 +309,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 14>;
+ clock-names = "usart";
status = "disabled";
};
@@ -333,15 +320,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- status = "disabled";
- };
-
- macb1: ethernet@f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 15>;
+ clock-names = "usart";
status = "disabled";
};
@@ -368,6 +348,8 @@
reg = <0xffffe600 0x200>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 30>;
+ clock-names = "dma_clk";
};
dma1: dma-controller@ffffe800 {
@@ -375,6 +357,8 @@
reg = <0xffffe800 0x200>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 31>;
+ clock-names = "dma_clk";
};
ramc0: ramc@ffffea00 {
@@ -388,6 +372,8 @@
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&periph 2>;
+ clock-names = "usart";
status = "disabled";
};
@@ -469,22 +455,6 @@
};
};
- can0 {
- pinctrl_can0_rx_tx: can0_rx_tx {
- atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
- AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
- };
- };
-
- can1 {
- pinctrl_can1_rx_tx: can1_rx_tx {
- atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
- AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
- };
- };
-
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
@@ -532,107 +502,6 @@
};
};
- lcd {
- pinctrl_lcd: lcd-0 {
- atmel,pins =
- <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
- AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
- AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
- AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
- AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
- AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
- AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
- AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
- AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
- AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
- AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
- AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
- AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
- AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
- AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
- AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
- AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
- AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
- AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
- AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
- AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
- AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
- AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
- AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
- AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
- AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
- AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
- AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
- };
- };
-
- macb0 {
- pinctrl_macb0_data_rgmii: macb0_data_rgmii {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
- };
- pinctrl_macb0_data_gmii: macb0_data_gmii {
- atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
- AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
- AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
- AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
- AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
- AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
- AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
- AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
- };
- pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
- };
- pinctrl_macb0_signal_gmii: macb0_signal_gmii {
- atmel,pins =
- <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
- };
-
- };
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
- AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
- AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
- AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
- AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
- AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
- AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
- AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
- AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
- AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
- };
- };
-
mmc0 {
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
atmel,pins =
@@ -670,21 +539,6 @@
};
};
- mmc2 {
- pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
- atmel,pins =
- <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
- AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
- AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
- };
- pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
- atmel,pins =
- <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
- AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
- AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
- };
- };
-
nand0 {
pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
atmel,pins =
@@ -743,22 +597,6 @@
};
};
- uart0 {
- pinctrl_uart0: uart0-0 {
- atmel,pins =
- <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
- AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
- };
- };
-
- uart1 {
- pinctrl_uart1: uart1-0 {
- atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
- AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
- };
- };
-
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -824,6 +662,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 6>;
};
pioB: gpio@fffff400 {
@@ -834,6 +673,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 7>;
};
pioC: gpio@fffff600 {
@@ -844,6 +684,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 8>;
};
pioD: gpio@fffff800 {
@@ -854,6 +695,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 9>;
};
pioE: gpio@fffffa00 {
@@ -864,12 +706,267 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 10>;
};
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x120>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,sama5d3-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <8000000 50000000>;
+ output = <400000000 1000000000>;
+ out = <0>;
+ icpll = <0>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 166000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0@0 {
+ id = <0>;
+ };
+
+ prog1@1 {
+ id = <1>;
+ };
+
+ prog2@2 {
+ id = <2>;
+ };
+ };
+
+ smd: smdclk {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck@2 {
+ id = <2>;
+ };
+
+ smdck@4 {
+ id = <4>;
+ };
+
+ uhpck@6 {
+ id = <6>;
+ };
+
+ udpck@7 {
+ id = <7>;
+ };
+
+ pck0@8 {
+ id = <8>;
+ };
+
+ pck1@9 {
+ id = <9>;
+ };
+
+ pck2@10 {
+ id = <10>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 6 7 8 9 10 12 13 14 15 18 19 20 21 22 24 25
+ 26 28 29 30 31 32 33 37 38 39 42 43 44 45 48>;
+
+ dbgu_clk@2 {
+ id = <2>;
+ };
+
+ pioA_clk@6 {
+ id = <6>;
+ };
+
+ pioB_clk@7 {
+ id = <7>;
+ };
+
+ pioC_clk@8 {
+ id = <8>;
+ };
+
+ pioD_clk@9 {
+ id = <9>;
+ };
+
+ pioE_clk@10 {
+ id = <10>;
+ };
+
+ usart0_clk@12 {
+ id = <12>;
+ default-divisor = <1>;
+ };
+
+ usart1_clk@13 {
+ id = <13>;
+ default-divisor = <1>;
+ };
+
+ usart2_clk@14 {
+ id = <14>;
+ default-divisor = <1>;
+ };
+
+ usart3_clk@15 {
+ id = <15>;
+ default-divisor = <1>;
+ };
+
+ twi0_clk@18 {
+ id = <18>;
+ default-divisor = <1>;
+ };
+
+ twi1_clk@19 {
+ id = <19>;
+ default-divisor = <1>;
+ };
+
+ twi2_clk@20 {
+ id = <20>;
+ default-divisor = <1>;
+ };
+
+ mci0_clk@21 {
+ id = <21>;
+ };
+
+ mci1_clk@22 {
+ id = <22>;
+ };
+
+ spi0_clk@24 {
+ id = <24>;
+ };
+
+ spi1_clk@25 {
+ id = <25>;
+ };
+
+ tcb0_clk@26 {
+ id = <26>;
+ default-divisor = <1>;
+ };
+
+ pwm_clk@28 {
+ id = <28>;
+ };
+
+ adc_clk@29 {
+ id = <29>;
+ default-divisor = <1>;
+ };
+
+ dma0_clk@30 {
+ id = <30>;
+ };
+
+ dma1_clk@31 {
+ id = <31>;
+ };
+
+ uhphs_clk@32 {
+ id = <32>;
+ };
+
+ udphs_clk@33 {
+ id = <33>;
+ };
+
+ isi_clk@37 {
+ id = <37>;
+ };
+
+ ssc0_clk@38 {
+ id = <38>;
+ default-divisor = <1>;
+ };
+
+ ssc1_clk@39 {
+ id = <39>;
+ default-divisor = <1>;
+ };
+
+ sha_clk@42 {
+ id = <42>;
+ default-divisor = <3>;
+ };
+
+ aes_clk@43 {
+ id = <43>;
+ };
+
+ tdes_clk@44 {
+ id = <44>;
+ };
+
+ trng_clk@45 {
+ id = <45>;
+ };
+
+ fuse_clk@48 {
+ id = <48>;
+ };
+ };
};
rstc@fffffe00 {
@@ -881,6 +978,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&mck>;
};
watchdog@fffffe40 {
@@ -903,6 +1001,8 @@
reg = <0x00500000 0x100000
0xf8030000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 33>, <&utmi>;
+ clock-names = "pclk", "hclk";
status = "disabled";
ep0 {
@@ -1015,6 +1115,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 32>, <&periph 32>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1022,6 +1124,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 32>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
new file mode 100644
index 0000000..a90075f
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -0,0 +1,71 @@
+/*
+ * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+ AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
+ AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
+ };
+ };
+
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ can0_clk@40 {
+ id = <40>;
+ default-divisor = <1>;
+ };
+
+ can1_clk@41 {
+ id = <41>;
+ default-divisor = <1>;
+ };
+ };
+ };
+
+ can0: can@f000c000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf000c000 0x300>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&periph 40>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ can1: can@f8010000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf8010000 0x300>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ clocks = <&periph 41>;
+ clock-names = "can_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
new file mode 100644
index 0000000..68d537d
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -0,0 +1,54 @@
+/*
+ * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ macb1_clk@35 {
+ id = <35>;
+ };
+ };
+ };
+
+ macb1: ethernet@f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 35>, <&periph 35>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
new file mode 100644
index 0000000..c87425e
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -0,0 +1,87 @@
+/*
+ * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Gigabit Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ macb0 {
+ pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
+ };
+ pinctrl_macb0_data_gmii: macb0_data_gmii {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+ AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
+ AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
+ AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
+ };
+ pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
+ };
+ pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+ atmel,pins =
+ <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
+ };
+
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ macb0_clk@34 {
+ id = <34>;
+ };
+ };
+ };
+
+ macb0: ethernet@f0028000 {
+ compatible = "cdns,pc302-gem", "cdns,gem";
+ reg = <0xf0028000 0x100>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 34>, <&periph 34>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
new file mode 100644
index 0000000..924a102
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -0,0 +1,69 @@
+/*
+ * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCD support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ lcd {
+ pinctrl_lcd: lcd-0 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
+ AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
+ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
+ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
+ AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
+ AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
+ AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
+ AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
+ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
+ AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
+ AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
+ AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
+ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
+ AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
+ AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
+ AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
+ AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
+ AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
+ AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
+ AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
+ AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ lcdc_clk@36 {
+ id = <36>;
+ };
+ };
+
+ system: systemck {
+ lcdck@3 {
+ id = <3>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
new file mode 100644
index 0000000..b40926b
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -0,0 +1,57 @@
+/*
+ * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 3 MMC ports
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ mmc2 {
+ pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
+ };
+ pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ mci2_clk@23 {
+ id = <23>;
+ };
+ };
+ };
+
+ mmc2: mmc@f8004000 {
+ compatible = "atmel,hsmci";
+ reg = <0xf8004000 0x600>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph 23>;
+ clock-names = "mci_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
new file mode 100644
index 0000000..1a46ec9
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -0,0 +1,38 @@
+/*
+ * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 2 TC blocks.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ tcb1 = &tcb1;
+ };
+
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ tcb1_clk@27 {
+ id = <27>;
+ default-divisor = <1>;
+ };
+ };
+ };
+
+ tcb1: timer@f8014000 {
+ compatible = "atmel,at91sam9x5-tcb";
+ reg = <0xf8014000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 27>;
+ clock-names = "t0_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
new file mode 100644
index 0000000..e46626a
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -0,0 +1,46 @@
+/*
+ * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * UART support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ uart0 {
+ pinctrl_uart0: uart0-0 {
+ atmel,pins =
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+ AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ periph: periphck {
+ uart0_clk@16 {
+ id = <16>;
+ default-divisor = <1>;
+ };
+
+ uart1_clk@17 {
+ id = <17>;
+ default-divisor = <1>;
+ };
+ };
+ };
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 35/42] ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
@ 2013-07-17 16:50 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 16:50 UTC (permalink / raw)
To: linux-arm-kernel
Define sama5d3 clocks in sama5d3 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/sama5d3.dtsi | 510 +++++++++++++++++++++--------------
arch/arm/boot/dts/sama5d3_can.dtsi | 71 +++++
arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++++
arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++++++
arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 +++++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++++
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +++
arch/arm/boot/dts/sama5d3_uart.dtsi | 46 ++++
8 files changed, 729 insertions(+), 203 deletions(-)
create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a1d5e25..6980c4d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -31,7 +31,6 @@
gpio3 = &pioD;
gpio4 = &pioE;
tcb0 = &tcb0;
- tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -52,6 +51,14 @@
reg = <0x20000000 0x8000000>;
};
+ clocks {
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -75,6 +82,8 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 21>;
+ clock-names = "mci_clk";
};
spi0: spi at f0004000 {
@@ -88,6 +97,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 24>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -97,15 +108,8 @@
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
- };
-
- can0: can at f000c000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf000c000 0x300>;
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&periph 38>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -113,6 +117,8 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf0010000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>;
+ clock-names = "t0_clk";
};
i2c0: i2c at f0014000 {
@@ -126,6 +132,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 18>;
status = "disabled";
};
@@ -140,6 +147,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 19>;
status = "disabled";
};
@@ -149,6 +157,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 12>;
+ clock-names = "usart";
status = "disabled";
};
@@ -158,15 +168,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- status = "disabled";
- };
-
- macb0: ethernet at f0028000 {
- compatible = "cdns,pc302-gem", "cdns,gem";
- reg = <0xf0028000 0x100>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 13>;
+ clock-names = "usart";
status = "disabled";
};
@@ -188,19 +191,8 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- };
-
- mmc2: mmc at f8004000 {
- compatible = "atmel,hsmci";
- reg = <0xf8004000 0x600>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
- dma-names = "rxtx";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&periph 22>;
+ clock-names = "mci_clk";
};
spi1: spi at f8008000 {
@@ -214,6 +206,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 25>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -223,23 +217,11 @@
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 39>;
+ clock-names = "pclk";
status = "disabled";
};
- can1: can at f8010000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf8010000 0x300>;
- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_rx_tx>;
- };
-
- tcb1: timer at f8014000 {
- compatible = "atmel,at91sam9x5-tcb";
- reg = <0xf8014000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
adc0: adc at f8018000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xf8018000 0x100>;
@@ -260,6 +242,8 @@
&pinctrl_adc0_ad10
&pinctrl_adc0_ad11
>;
+ clocks = <&periph 29>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channel-base = <0x50>;
atmel,adc-channels-used = <0xfff>;
atmel,adc-drdy-mask = <0x1000000>;
@@ -315,6 +299,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 20>;
status = "disabled";
};
@@ -324,6 +309,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 14>;
+ clock-names = "usart";
status = "disabled";
};
@@ -333,15 +320,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- status = "disabled";
- };
-
- macb1: ethernet at f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 15>;
+ clock-names = "usart";
status = "disabled";
};
@@ -368,6 +348,8 @@
reg = <0xffffe600 0x200>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 30>;
+ clock-names = "dma_clk";
};
dma1: dma-controller at ffffe800 {
@@ -375,6 +357,8 @@
reg = <0xffffe800 0x200>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 31>;
+ clock-names = "dma_clk";
};
ramc0: ramc at ffffea00 {
@@ -388,6 +372,8 @@
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&periph 2>;
+ clock-names = "usart";
status = "disabled";
};
@@ -469,22 +455,6 @@
};
};
- can0 {
- pinctrl_can0_rx_tx: can0_rx_tx {
- atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
- AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
- };
- };
-
- can1 {
- pinctrl_can1_rx_tx: can1_rx_tx {
- atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
- AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
- };
- };
-
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
@@ -532,107 +502,6 @@
};
};
- lcd {
- pinctrl_lcd: lcd-0 {
- atmel,pins =
- <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
- AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
- AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
- AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
- AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
- AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
- AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
- AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
- AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
- AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
- AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
- AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
- AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
- AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
- AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
- AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
- AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
- AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
- AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
- AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
- AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
- AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
- AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
- AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
- AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
- AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
- AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
- AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
- };
- };
-
- macb0 {
- pinctrl_macb0_data_rgmii: macb0_data_rgmii {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
- };
- pinctrl_macb0_data_gmii: macb0_data_gmii {
- atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
- AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
- AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
- AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
- AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
- AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
- AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
- AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
- };
- pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
- };
- pinctrl_macb0_signal_gmii: macb0_signal_gmii {
- atmel,pins =
- <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
- };
-
- };
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
- AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
- AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
- AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
- AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
- AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
- AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
- AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
- AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
- AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
- };
- };
-
mmc0 {
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
atmel,pins =
@@ -670,21 +539,6 @@
};
};
- mmc2 {
- pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
- atmel,pins =
- <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
- AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
- AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
- };
- pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
- atmel,pins =
- <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
- AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
- AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
- };
- };
-
nand0 {
pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
atmel,pins =
@@ -743,22 +597,6 @@
};
};
- uart0 {
- pinctrl_uart0: uart0-0 {
- atmel,pins =
- <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
- AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
- };
- };
-
- uart1 {
- pinctrl_uart1: uart1-0 {
- atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
- AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
- };
- };
-
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -824,6 +662,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 6>;
};
pioB: gpio at fffff400 {
@@ -834,6 +673,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 7>;
};
pioC: gpio at fffff600 {
@@ -844,6 +684,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 8>;
};
pioD: gpio at fffff800 {
@@ -854,6 +695,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 9>;
};
pioE: gpio at fffffa00 {
@@ -864,12 +706,267 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 10>;
};
};
pmc: pmc at fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x120>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,sama5d3-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <8000000 50000000>;
+ output = <400000000 1000000000>;
+ out = <0>;
+ icpll = <0>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 166000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0 at 0 {
+ id = <0>;
+ };
+
+ prog1 at 1 {
+ id = <1>;
+ };
+
+ prog2 at 2 {
+ id = <2>;
+ };
+ };
+
+ smd: smdclk {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+
+ ddrck at 2 {
+ id = <2>;
+ };
+
+ smdck at 4 {
+ id = <4>;
+ };
+
+ uhpck at 6 {
+ id = <6>;
+ };
+
+ udpck at 7 {
+ id = <7>;
+ };
+
+ pck0 at 8 {
+ id = <8>;
+ };
+
+ pck1 at 9 {
+ id = <9>;
+ };
+
+ pck2 at 10 {
+ id = <10>;
+ };
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 6 7 8 9 10 12 13 14 15 18 19 20 21 22 24 25
+ 26 28 29 30 31 32 33 37 38 39 42 43 44 45 48>;
+
+ dbgu_clk at 2 {
+ id = <2>;
+ };
+
+ pioA_clk at 6 {
+ id = <6>;
+ };
+
+ pioB_clk at 7 {
+ id = <7>;
+ };
+
+ pioC_clk at 8 {
+ id = <8>;
+ };
+
+ pioD_clk at 9 {
+ id = <9>;
+ };
+
+ pioE_clk at 10 {
+ id = <10>;
+ };
+
+ usart0_clk at 12 {
+ id = <12>;
+ default-divisor = <1>;
+ };
+
+ usart1_clk at 13 {
+ id = <13>;
+ default-divisor = <1>;
+ };
+
+ usart2_clk at 14 {
+ id = <14>;
+ default-divisor = <1>;
+ };
+
+ usart3_clk at 15 {
+ id = <15>;
+ default-divisor = <1>;
+ };
+
+ twi0_clk at 18 {
+ id = <18>;
+ default-divisor = <1>;
+ };
+
+ twi1_clk at 19 {
+ id = <19>;
+ default-divisor = <1>;
+ };
+
+ twi2_clk at 20 {
+ id = <20>;
+ default-divisor = <1>;
+ };
+
+ mci0_clk at 21 {
+ id = <21>;
+ };
+
+ mci1_clk at 22 {
+ id = <22>;
+ };
+
+ spi0_clk at 24 {
+ id = <24>;
+ };
+
+ spi1_clk at 25 {
+ id = <25>;
+ };
+
+ tcb0_clk at 26 {
+ id = <26>;
+ default-divisor = <1>;
+ };
+
+ pwm_clk at 28 {
+ id = <28>;
+ };
+
+ adc_clk at 29 {
+ id = <29>;
+ default-divisor = <1>;
+ };
+
+ dma0_clk at 30 {
+ id = <30>;
+ };
+
+ dma1_clk at 31 {
+ id = <31>;
+ };
+
+ uhphs_clk at 32 {
+ id = <32>;
+ };
+
+ udphs_clk at 33 {
+ id = <33>;
+ };
+
+ isi_clk at 37 {
+ id = <37>;
+ };
+
+ ssc0_clk at 38 {
+ id = <38>;
+ default-divisor = <1>;
+ };
+
+ ssc1_clk at 39 {
+ id = <39>;
+ default-divisor = <1>;
+ };
+
+ sha_clk at 42 {
+ id = <42>;
+ default-divisor = <3>;
+ };
+
+ aes_clk at 43 {
+ id = <43>;
+ };
+
+ tdes_clk at 44 {
+ id = <44>;
+ };
+
+ trng_clk at 45 {
+ id = <45>;
+ };
+
+ fuse_clk at 48 {
+ id = <48>;
+ };
+ };
};
rstc at fffffe00 {
@@ -881,6 +978,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&mck>;
};
watchdog at fffffe40 {
@@ -903,6 +1001,8 @@
reg = <0x00500000 0x100000
0xf8030000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 33>, <&utmi>;
+ clock-names = "pclk", "hclk";
status = "disabled";
ep0 {
@@ -1015,6 +1115,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&periph 32>, <&periph 32>, <&system 6>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1022,6 +1124,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 32>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
new file mode 100644
index 0000000..a90075f
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -0,0 +1,71 @@
+/*
+ * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+ AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
+ AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
+ };
+ };
+
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ can0_clk at 40 {
+ id = <40>;
+ default-divisor = <1>;
+ };
+
+ can1_clk at 41 {
+ id = <41>;
+ default-divisor = <1>;
+ };
+ };
+ };
+
+ can0: can at f000c000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf000c000 0x300>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&periph 40>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ can1: can at f8010000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf8010000 0x300>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ clocks = <&periph 41>;
+ clock-names = "can_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
new file mode 100644
index 0000000..68d537d
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -0,0 +1,54 @@
+/*
+ * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ macb1_clk at 35 {
+ id = <35>;
+ };
+ };
+ };
+
+ macb1: ethernet at f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 35>, <&periph 35>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
new file mode 100644
index 0000000..c87425e
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -0,0 +1,87 @@
+/*
+ * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Gigabit Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ macb0 {
+ pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
+ };
+ pinctrl_macb0_data_gmii: macb0_data_gmii {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+ AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
+ AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
+ AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
+ };
+ pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
+ };
+ pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+ atmel,pins =
+ <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
+ };
+
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ macb0_clk at 34 {
+ id = <34>;
+ };
+ };
+ };
+
+ macb0: ethernet at f0028000 {
+ compatible = "cdns,pc302-gem", "cdns,gem";
+ reg = <0xf0028000 0x100>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 34>, <&periph 34>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
new file mode 100644
index 0000000..924a102
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -0,0 +1,69 @@
+/*
+ * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCD support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ lcd {
+ pinctrl_lcd: lcd-0 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
+ AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
+ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
+ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
+ AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
+ AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
+ AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
+ AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
+ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
+ AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
+ AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
+ AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
+ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
+ AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
+ AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
+ AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
+ AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
+ AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
+ AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
+ AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
+ AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ lcdc_clk at 36 {
+ id = <36>;
+ };
+ };
+
+ system: systemck {
+ lcdck at 3 {
+ id = <3>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
new file mode 100644
index 0000000..b40926b
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -0,0 +1,57 @@
+/*
+ * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 3 MMC ports
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ mmc2 {
+ pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
+ };
+ pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ mci2_clk at 23 {
+ id = <23>;
+ };
+ };
+ };
+
+ mmc2: mmc at f8004000 {
+ compatible = "atmel,hsmci";
+ reg = <0xf8004000 0x600>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph 23>;
+ clock-names = "mci_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
new file mode 100644
index 0000000..1a46ec9
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -0,0 +1,38 @@
+/*
+ * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 2 TC blocks.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ tcb1 = &tcb1;
+ };
+
+ ahb {
+ apb {
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ tcb1_clk at 27 {
+ id = <27>;
+ default-divisor = <1>;
+ };
+ };
+ };
+
+ tcb1: timer at f8014000 {
+ compatible = "atmel,at91sam9x5-tcb";
+ reg = <0xf8014000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 27>;
+ clock-names = "t0_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
new file mode 100644
index 0000000..e46626a
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -0,0 +1,46 @@
+/*
+ * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * UART support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ uart0 {
+ pinctrl_uart0: uart0-0 {
+ atmel,pins =
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+ AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+ };
+ };
+ };
+
+ pmc: pmc at fffffc00 {
+ periph: periphck {
+ uart0_clk at 16 {
+ id = <16>;
+ default-divisor = <1>;
+ };
+
+ uart1_clk at 17 {
+ id = <17>;
+ default-divisor = <1>;
+ };
+ };
+ };
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 36/42] ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:06 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:06 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Linus Walleij, Wenyou Yang
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every sam9260/sam9g20 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/animeo_ip.dts | 17 ++++++-----------
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/ge863-pro3.dtsi | 16 ++++++----------
arch/arm/boot/dts/kizbox.dts | 5 +++++
arch/arm/boot/dts/tny_a9260_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/usb_a9260_common.dtsi | 17 ++++++-----------
6 files changed, 35 insertions(+), 54 deletions(-)
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9e..1843f15 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -31,17 +31,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
usart0: serial@fffb0000 {
@@ -82,6 +71,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 1373546..b8c823d 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -17,17 +17,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
pinctrl@fffff400 {
@@ -108,6 +97,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 230099b..b0b6aae 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -10,22 +10,18 @@
#include "at91sam9260.dtsi"
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <6000000>;
- };
- };
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <6000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 02df191..091da2e 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -53,6 +53,11 @@
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index 0e6d3de..1cecb7a 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -15,22 +15,17 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index 2859776..3ed4db8 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -7,17 +7,6 @@
*/
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -33,6 +22,12 @@
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 36/42] ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
@ 2013-07-17 20:06 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:06 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every sam9260/sam9g20 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/animeo_ip.dts | 17 ++++++-----------
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/ge863-pro3.dtsi | 16 ++++++----------
arch/arm/boot/dts/kizbox.dts | 5 +++++
arch/arm/boot/dts/tny_a9260_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/usb_a9260_common.dtsi | 17 ++++++-----------
6 files changed, 35 insertions(+), 54 deletions(-)
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9e..1843f15 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -31,17 +31,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
usart0: serial at fffb0000 {
@@ -82,6 +71,12 @@
watchdog at fffffd40 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 1373546..b8c823d 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -17,17 +17,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
pinctrl at fffff400 {
@@ -108,6 +97,12 @@
watchdog at fffffd40 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 230099b..b0b6aae 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -10,22 +10,18 @@
#include "at91sam9260.dtsi"
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <6000000>;
- };
- };
ahb {
apb {
dbgu: serial at fffff200 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <6000000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 02df191..091da2e 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -53,6 +53,11 @@
status = "okay";
};
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index 0e6d3de..1cecb7a 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -15,22 +15,17 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at fffff200 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index 2859776..3ed4db8 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -7,17 +7,6 @@
*/
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at fffff200 {
@@ -33,6 +22,12 @@
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 37/42] ARM: at91/dt: move rm9200 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:08 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:08 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Joachim Eastwood
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every at91rm9200 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91rm9200ek.dts | 17 ++++++-----------
arch/arm/boot/dts/mpa1600.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..e2960b4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -16,19 +16,14 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
+
dbgu: serial@fffff200 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index ccf9ea2..317ee5a 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -16,17 +16,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -45,6 +34,11 @@
ssc1: ssc@fffd4000 {
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
usb0: ohci@00300000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 37/42] ARM: at91/dt: move rm9200 boards to new at91 clk implem
@ 2013-07-17 20:08 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:08 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every at91rm9200 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91rm9200ek.dts | 17 ++++++-----------
arch/arm/boot/dts/mpa1600.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..e2960b4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -16,19 +16,14 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
+
dbgu: serial at fffff200 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index ccf9ea2..317ee5a 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -16,17 +16,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
dbgu: serial at fffff200 {
@@ -45,6 +34,11 @@
ssc1: ssc at fffd4000 {
status = "okay";
};
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
usb0: ohci at 00300000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 38/42] ARM: at91/dt: move sam9263 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:09 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:09 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Wenyou Yang, Linus Walleij
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every at91sam9263 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9263ek.dts | 17 ++++++-----------
arch/arm/boot/dts/tny_a9263.dts | 17 ++++++-----------
arch/arm/boot/dts/usb_a9263.dts | 17 ++++++-----------
3 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b..b3aa143 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16367660>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -93,6 +82,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <16367660>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 0751a6a..067eefb 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -41,6 +30,12 @@
atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 290e603..ae5b92d 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -61,6 +50,12 @@
atmel,wakeup-counter = <10>;
atmel,wakeup-rtt-timer;
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 38/42] ARM: at91/dt: move sam9263 boards to new at91 clk implem
@ 2013-07-17 20:09 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:09 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every at91sam9263 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9263ek.dts | 17 ++++++-----------
arch/arm/boot/dts/tny_a9263.dts | 17 ++++++-----------
arch/arm/boot/dts/usb_a9263.dts | 17 ++++++-----------
3 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b..b3aa143 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16367660>;
- };
- };
-
ahb {
apb {
dbgu: serial at ffffee00 {
@@ -93,6 +82,12 @@
watchdog at fffffd40 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <16367660>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 0751a6a..067eefb 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at ffffee00 {
@@ -41,6 +30,12 @@
atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 290e603..ae5b92d 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at ffffee00 {
@@ -61,6 +50,12 @@
atmel,wakeup-counter = <10>;
atmel,wakeup-rtt-timer;
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 39/42] ARM: at91/dt: move sam9g45 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:17 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:17 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Wenyou Yang, Linus Walleij
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every at91sam9g45 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 ++++++-----------
arch/arm/boot/dts/pm9g45.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5..f83bda2 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -21,17 +21,6 @@
reg = <0x70000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -121,6 +110,12 @@
atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 33ffabe..3d8af99 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -20,17 +20,6 @@
reg = <0x70000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -73,6 +62,11 @@
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 39/42] ARM: at91/dt: move sam9g45 boards to new at91 clk implem
@ 2013-07-17 20:17 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:17 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every at91sam9g45 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 ++++++-----------
arch/arm/boot/dts/pm9g45.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5..f83bda2 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -21,17 +21,6 @@
reg = <0x70000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at ffffee00 {
@@ -121,6 +110,12 @@
atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 33ffabe..3d8af99 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -20,17 +20,6 @@
reg = <0x70000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at ffffee00 {
@@ -73,6 +62,11 @@
status = "okay";
};
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 40/42] ARM: at91/dt: move sam9n12 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:19 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:19 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Wenyou Yang, Josh Wu
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every at91sam9n12 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9n12ek.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d59b70c..35f484a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -21,17 +21,6 @@
reg = <0x20000000 0x10000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -81,6 +70,12 @@
watchdog@fffffe40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <16000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 40/42] ARM: at91/dt: move sam9n12 boards to new at91 clk implem
@ 2013-07-17 20:19 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:19 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every at91sam9n12 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91sam9n12ek.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d59b70c..35f484a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -21,17 +21,6 @@
reg = <0x20000000 0x10000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16000000>;
- };
- };
-
ahb {
apb {
dbgu: serial at fffff200 {
@@ -81,6 +70,12 @@
watchdog at fffffe40 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <16000000>;
+ };
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 41/42] ARM: at91/dt: move sam9x5 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:21 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:21 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King,
Douglas Gilbert
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every at91sam9x5 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91-ariag25.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index cce45f5..f574682 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -33,17 +33,6 @@
reg = <0x20000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
mmc0: mmc@f0008000 {
@@ -147,6 +136,12 @@
rtc@fffffeb0 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
usb0: ohci@00600000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 41/42] ARM: at91/dt: move sam9x5 boards to new at91 clk implem
@ 2013-07-17 20:21 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:21 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every at91sam9x5 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/at91-ariag25.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index cce45f5..f574682 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -33,17 +33,6 @@
reg = <0x20000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
mmc0: mmc at f0008000 {
@@ -147,6 +136,12 @@
rtc at fffffeb0 {
status = "okay";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
usb0: ohci at 00600000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* [PATCH v2 42/42] ARM: at91/dt: move sama5d3 boards to new at91 clk implem
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-17 20:32 ` Boris BREZILLON
-1 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:32 UTC (permalink / raw)
To: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, Russell King
Cc: linux-arm-kernel, linux-kernel, Boris BREZILLON
Define the main clock frequency in every sama5d3 boards.
Remove the old main clock definition.
Include the appropriate peripheral options according to peripherals
availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/sama5d31ek.dts | 4 ++++
arch/arm/boot/dts/sama5d33ek.dts | 2 ++
arch/arm/boot/dts/sama5d34ek.dts | 4 ++++
arch/arm/boot/dts/sama5d35ek.dts | 6 ++++++
arch/arm/boot/dts/sama5d3xcm.dtsi | 17 ++++++-----------
5 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 027bac7..4628533 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -9,6 +9,10 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
/ {
model = "Atmel SAMA5D31-EK";
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index 99bd0c8..5aa32f5 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -9,6 +9,8 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
/ {
model = "Atmel SAMA5D33-EK";
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index fb8ee11..272a611 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -9,6 +9,10 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
/ {
model = "Atmel SAMA5D34-EK";
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 509a53d..155bb9d 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -8,6 +8,12 @@
*/
/dts-v1/;
#include "sama5d3xmb.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
+#include "sama5d3_tcb1.dtsi"
/ {
model = "Atmel SAMA5D35-EK";
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f80508..f58aa43 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -19,17 +19,6 @@
reg = <0x20000000 0x20000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
spi0: spi@f0004000 {
@@ -39,6 +28,12 @@
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@60000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 42/42] ARM: at91/dt: move sama5d3 boards to new at91 clk implem
@ 2013-07-17 20:32 ` Boris BREZILLON
0 siblings, 0 replies; 129+ messages in thread
From: Boris BREZILLON @ 2013-07-17 20:32 UTC (permalink / raw)
To: linux-arm-kernel
Define the main clock frequency in every sama5d3 boards.
Remove the old main clock definition.
Include the appropriate peripheral options according to peripherals
availability.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/sama5d31ek.dts | 4 ++++
arch/arm/boot/dts/sama5d33ek.dts | 2 ++
arch/arm/boot/dts/sama5d34ek.dts | 4 ++++
arch/arm/boot/dts/sama5d35ek.dts | 6 ++++++
arch/arm/boot/dts/sama5d3xcm.dtsi | 17 ++++++-----------
5 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 027bac7..4628533 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -9,6 +9,10 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
/ {
model = "Atmel SAMA5D31-EK";
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index 99bd0c8..5aa32f5 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -9,6 +9,8 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
/ {
model = "Atmel SAMA5D33-EK";
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index fb8ee11..272a611 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -9,6 +9,10 @@
/dts-v1/;
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
/ {
model = "Atmel SAMA5D34-EK";
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 509a53d..155bb9d 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -8,6 +8,12 @@
*/
/dts-v1/;
#include "sama5d3xmb.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
+#include "sama5d3_tcb1.dtsi"
/ {
model = "Atmel SAMA5D35-EK";
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f80508..f58aa43 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -19,17 +19,6 @@
reg = <0x20000000 0x20000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock at 0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
spi0: spi at f0004000 {
@@ -39,6 +28,12 @@
macb0: ethernet at f0028000 {
phy-mode = "rgmii";
};
+
+ pmc: pmc at fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand at 60000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-18 8:51 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-18 8:51 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette,
linux-arm-kernel, linux-kernel
On 17/07/2013 15:34, Boris BREZILLON wrote:
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
This was tested on kizbox board too.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
> Boris BREZILLON (42):
> ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
> ARM: at91: add PMC main clock
> ARM: at91: add PMC pll clocks
> ARM: at91: add PMC master clock
> ARM: at91: add PMC system clocks
> ARM: at91: add PMC peripheral clocks
> ARM: at91: add PMC programmable clocks
> ARM: at91: add PMC utmi clock
> ARM: at91: add PMC usb clock
> ARM: at91: add PMC smd clock
> ARM: at91: add PMC clk device tree binding doc.
> ARM: at91: move to common clk framework
> ARM: at91: move at91rm9200 SoC to new at91 clk implem
> ARM: at91: move at91sam9260 SoC to new at91 clk implem
> ARM: at91: move at91sam9261 SoC to new at91 clk implem
> ARM: at91: move at91sam9263 SoC to new at91 clk implem
> ARM: at91: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91: move at91sam9rl SoC to new at91 clk implem
> ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91: move at91sam9 SoCs to new at91 clk implem
> ARM: at91: move sama5d3 SoCs to new at91 clk implem
> ARM: at91: move at91rm9200 boards to new at91 clk implem
> ARM: at91: move at91sam9 boards to new at91 clk implem
> ARM: at91: move pit timer to common clk framework
> USB: ohci-at91: add usb_clk for transition to common clk framework
> usb: gadget: at91_udc: add usb_clk for transition to common clk
> framework
> ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
> ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
> ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
> ARM: at91/dt: move rm9200 boards to new at91 clk implem
> ARM: at91/dt: move sam9263 boards to new at91 clk implem
> ARM: at91/dt: move sam9g45 boards to new at91 clk implem
> ARM: at91/dt: move sam9n12 boards to new at91 clk implem
> ARM: at91/dt: move sam9x5 boards to new at91 clk implem
> ARM: at91/dt: move sama5d3 boards to new at91 clk implem
>
> .../devicetree/bindings/clock/at91-clock.txt | 262 ++++++
> arch/arm/boot/dts/animeo_ip.dts | 17 +-
> arch/arm/boot/dts/at91-ariag25.dts | 17 +-
> arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++
> arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9260.dtsi | 236 +++++
> arch/arm/boot/dts/at91sam9263.dtsi | 237 +++++
> arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
> arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
> arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
> arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
> arch/arm/boot/dts/at91sam9g45.dtsi | 257 +++++
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9n12.dtsi | 251 +++++
> arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
> arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
> arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++--
> arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +
> arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +
> arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +
> arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 ++
> arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 ++
> arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++
> arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
> arch/arm/boot/dts/kizbox.dts | 5 +
> arch/arm/boot/dts/mpa1600.dts | 16 +-
> arch/arm/boot/dts/pm9g45.dts | 16 +-
> arch/arm/boot/dts/sama5d3.dtsi | 510 ++++++----
> arch/arm/boot/dts/sama5d31ek.dts | 4 +
> arch/arm/boot/dts/sama5d33ek.dts | 2 +
> arch/arm/boot/dts/sama5d34ek.dts | 4 +
> arch/arm/boot/dts/sama5d35ek.dts | 6 +
> arch/arm/boot/dts/sama5d3_can.dtsi | 71 ++
> arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++
> arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++
> arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 ++
> arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++
> arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +
> arch/arm/boot/dts/sama5d3_uart.dtsi | 46 +
> arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9263.dts | 17 +-
> arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/usb_a9263.dts | 17 +-
> arch/arm/mach-at91/Kconfig | 26 +
> arch/arm/mach-at91/Makefile | 2 +-
> arch/arm/mach-at91/at91rm9200.c | 568 +++++++-----
> arch/arm/mach-at91/at91sam9260.c | 689 +++++++++-----
> arch/arm/mach-at91/at91sam9261.c | 572 ++++++++----
> arch/arm/mach-at91/at91sam9263.c | 595 +++++++-----
> arch/arm/mach-at91/at91sam926x_time.c | 21 +-
> arch/arm/mach-at91/at91sam9g45.c | 704 ++++++++------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> arch/arm/mach-at91/at91sam9n12.c | 196 +---
> arch/arm/mach-at91/at91sam9rl.c | 502 ++++++----
> arch/arm/mach-at91/at91sam9x5.c | 293 +-----
> arch/arm/mach-at91/board-1arm.c | 12 +-
> arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
> arch/arm/mach-at91/board-cam60.c | 13 +-
> arch/arm/mach-at91/board-carmeva.c | 13 +-
> arch/arm/mach-at91/board-cpu9krea.c | 12 +-
> arch/arm/mach-at91/board-cpuat91.c | 12 +-
> arch/arm/mach-at91/board-csb337.c | 11 +-
> arch/arm/mach-at91/board-csb637.c | 11 +-
> arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
> arch/arm/mach-at91/board-dt-sam9.c | 9 +-
> arch/arm/mach-at91/board-dt-sama5.c | 9 +-
> arch/arm/mach-at91/board-eb9200.c | 11 +-
> arch/arm/mach-at91/board-ecbat91.c | 12 +-
> arch/arm/mach-at91/board-eco920.c | 13 +-
> arch/arm/mach-at91/board-flexibity.c | 12 +-
> arch/arm/mach-at91/board-foxg20.c | 12 +-
> arch/arm/mach-at91/board-gsia18s.c | 8 +-
> arch/arm/mach-at91/board-kafa.c | 12 +-
> arch/arm/mach-at91/board-kb9202.c | 12 +-
> arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
> arch/arm/mach-at91/board-picotux200.c | 11 +-
> arch/arm/mach-at91/board-qil-a9260.c | 11 +-
> arch/arm/mach-at91/board-rm9200ek.c | 11 +-
> arch/arm/mach-at91/board-rsi-ews.c | 12 +-
> arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
> arch/arm/mach-at91/board-sam9260ek.c | 11 +-
> arch/arm/mach-at91/board-sam9261ek.c | 15 +-
> arch/arm/mach-at91/board-sam9263ek.c | 11 +-
> arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
> arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
> arch/arm/mach-at91/board-sam9rlek.c | 11 +-
> arch/arm/mach-at91/board-snapper9260.c | 12 +-
> arch/arm/mach-at91/board-stamp9g20.c | 15 +-
> arch/arm/mach-at91/board-yl-9200.c | 12 +-
> arch/arm/mach-at91/clock.c | 977 --------------------
> arch/arm/mach-at91/clock.h | 49 -
> arch/arm/mach-at91/generic.h | 10 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/pmc.c | 58 ++
> arch/arm/mach-at91/sama5d3.c | 344 +------
> arch/arm/mach-at91/setup.c | 38 +-
> arch/arm/mach-at91/stamp9g20.h | 2 +-
> drivers/clk/Makefile | 1 +
> drivers/clk/at91/Makefile | 11 +
> drivers/clk/at91/clk-main.c | 106 +++
> drivers/clk/at91/clk-master.c | 317 +++++++
> drivers/clk/at91/clk-peripheral.c | 371 ++++++++
> drivers/clk/at91/clk-pll.c | 438 +++++++++
> drivers/clk/at91/clk-plldiv.c | 125 +++
> drivers/clk/at91/clk-programmable.c | 368 ++++++++
> drivers/clk/at91/clk-smd.c | 157 ++++
> drivers/clk/at91/clk-system.c | 184 ++++
> drivers/clk/at91/clk-usb.c | 303 ++++++
> drivers/clk/at91/clk-utmi.c | 114 +++
> drivers/usb/gadget/at91_udc.c | 31 +-
> drivers/usb/gadget/at91_udc.h | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> drivers/usb/host/ohci-at91.c | 16 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 116 ++-
> 119 files changed, 8193 insertions(+), 3835 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
> create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
> delete mode 100644 arch/arm/mach-at91/clock.c
> delete mode 100644 arch/arm/mach-at91/clock.h
> create mode 100644 arch/arm/mach-at91/pmc.c
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
> create mode 100644 drivers/clk/at91/clk-master.c
> create mode 100644 drivers/clk/at91/clk-peripheral.c
> create mode 100644 drivers/clk/at91/clk-pll.c
> create mode 100644 drivers/clk/at91/clk-plldiv.c
> create mode 100644 drivers/clk/at91/clk-programmable.c
> create mode 100644 drivers/clk/at91/clk-smd.c
> create mode 100644 drivers/clk/at91/clk-system.c
> create mode 100644 drivers/clk/at91/clk-usb.c
> create mode 100644 drivers/clk/at91/clk-utmi.c
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (78%)
>
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-18 8:51 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-18 8:51 UTC (permalink / raw)
To: linux-arm-kernel
On 17/07/2013 15:34, Boris BREZILLON wrote:
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
This was tested on kizbox board too.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
> Boris BREZILLON (42):
> ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
> ARM: at91: add PMC main clock
> ARM: at91: add PMC pll clocks
> ARM: at91: add PMC master clock
> ARM: at91: add PMC system clocks
> ARM: at91: add PMC peripheral clocks
> ARM: at91: add PMC programmable clocks
> ARM: at91: add PMC utmi clock
> ARM: at91: add PMC usb clock
> ARM: at91: add PMC smd clock
> ARM: at91: add PMC clk device tree binding doc.
> ARM: at91: move to common clk framework
> ARM: at91: move at91rm9200 SoC to new at91 clk implem
> ARM: at91: move at91sam9260 SoC to new at91 clk implem
> ARM: at91: move at91sam9261 SoC to new at91 clk implem
> ARM: at91: move at91sam9263 SoC to new at91 clk implem
> ARM: at91: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91: move at91sam9rl SoC to new at91 clk implem
> ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91: move at91sam9 SoCs to new at91 clk implem
> ARM: at91: move sama5d3 SoCs to new at91 clk implem
> ARM: at91: move at91rm9200 boards to new at91 clk implem
> ARM: at91: move at91sam9 boards to new at91 clk implem
> ARM: at91: move pit timer to common clk framework
> USB: ohci-at91: add usb_clk for transition to common clk framework
> usb: gadget: at91_udc: add usb_clk for transition to common clk
> framework
> ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
> ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
> ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
> ARM: at91/dt: move rm9200 boards to new at91 clk implem
> ARM: at91/dt: move sam9263 boards to new at91 clk implem
> ARM: at91/dt: move sam9g45 boards to new at91 clk implem
> ARM: at91/dt: move sam9n12 boards to new at91 clk implem
> ARM: at91/dt: move sam9x5 boards to new at91 clk implem
> ARM: at91/dt: move sama5d3 boards to new at91 clk implem
>
> .../devicetree/bindings/clock/at91-clock.txt | 262 ++++++
> arch/arm/boot/dts/animeo_ip.dts | 17 +-
> arch/arm/boot/dts/at91-ariag25.dts | 17 +-
> arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++
> arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9260.dtsi | 236 +++++
> arch/arm/boot/dts/at91sam9263.dtsi | 237 +++++
> arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
> arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
> arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
> arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
> arch/arm/boot/dts/at91sam9g45.dtsi | 257 +++++
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9n12.dtsi | 251 +++++
> arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
> arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
> arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++--
> arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +
> arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +
> arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +
> arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 ++
> arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 ++
> arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++
> arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
> arch/arm/boot/dts/kizbox.dts | 5 +
> arch/arm/boot/dts/mpa1600.dts | 16 +-
> arch/arm/boot/dts/pm9g45.dts | 16 +-
> arch/arm/boot/dts/sama5d3.dtsi | 510 ++++++----
> arch/arm/boot/dts/sama5d31ek.dts | 4 +
> arch/arm/boot/dts/sama5d33ek.dts | 2 +
> arch/arm/boot/dts/sama5d34ek.dts | 4 +
> arch/arm/boot/dts/sama5d35ek.dts | 6 +
> arch/arm/boot/dts/sama5d3_can.dtsi | 71 ++
> arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++
> arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++
> arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 ++
> arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++
> arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +
> arch/arm/boot/dts/sama5d3_uart.dtsi | 46 +
> arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9263.dts | 17 +-
> arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/usb_a9263.dts | 17 +-
> arch/arm/mach-at91/Kconfig | 26 +
> arch/arm/mach-at91/Makefile | 2 +-
> arch/arm/mach-at91/at91rm9200.c | 568 +++++++-----
> arch/arm/mach-at91/at91sam9260.c | 689 +++++++++-----
> arch/arm/mach-at91/at91sam9261.c | 572 ++++++++----
> arch/arm/mach-at91/at91sam9263.c | 595 +++++++-----
> arch/arm/mach-at91/at91sam926x_time.c | 21 +-
> arch/arm/mach-at91/at91sam9g45.c | 704 ++++++++------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> arch/arm/mach-at91/at91sam9n12.c | 196 +---
> arch/arm/mach-at91/at91sam9rl.c | 502 ++++++----
> arch/arm/mach-at91/at91sam9x5.c | 293 +-----
> arch/arm/mach-at91/board-1arm.c | 12 +-
> arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
> arch/arm/mach-at91/board-cam60.c | 13 +-
> arch/arm/mach-at91/board-carmeva.c | 13 +-
> arch/arm/mach-at91/board-cpu9krea.c | 12 +-
> arch/arm/mach-at91/board-cpuat91.c | 12 +-
> arch/arm/mach-at91/board-csb337.c | 11 +-
> arch/arm/mach-at91/board-csb637.c | 11 +-
> arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
> arch/arm/mach-at91/board-dt-sam9.c | 9 +-
> arch/arm/mach-at91/board-dt-sama5.c | 9 +-
> arch/arm/mach-at91/board-eb9200.c | 11 +-
> arch/arm/mach-at91/board-ecbat91.c | 12 +-
> arch/arm/mach-at91/board-eco920.c | 13 +-
> arch/arm/mach-at91/board-flexibity.c | 12 +-
> arch/arm/mach-at91/board-foxg20.c | 12 +-
> arch/arm/mach-at91/board-gsia18s.c | 8 +-
> arch/arm/mach-at91/board-kafa.c | 12 +-
> arch/arm/mach-at91/board-kb9202.c | 12 +-
> arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
> arch/arm/mach-at91/board-picotux200.c | 11 +-
> arch/arm/mach-at91/board-qil-a9260.c | 11 +-
> arch/arm/mach-at91/board-rm9200ek.c | 11 +-
> arch/arm/mach-at91/board-rsi-ews.c | 12 +-
> arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
> arch/arm/mach-at91/board-sam9260ek.c | 11 +-
> arch/arm/mach-at91/board-sam9261ek.c | 15 +-
> arch/arm/mach-at91/board-sam9263ek.c | 11 +-
> arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
> arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
> arch/arm/mach-at91/board-sam9rlek.c | 11 +-
> arch/arm/mach-at91/board-snapper9260.c | 12 +-
> arch/arm/mach-at91/board-stamp9g20.c | 15 +-
> arch/arm/mach-at91/board-yl-9200.c | 12 +-
> arch/arm/mach-at91/clock.c | 977 --------------------
> arch/arm/mach-at91/clock.h | 49 -
> arch/arm/mach-at91/generic.h | 10 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/pmc.c | 58 ++
> arch/arm/mach-at91/sama5d3.c | 344 +------
> arch/arm/mach-at91/setup.c | 38 +-
> arch/arm/mach-at91/stamp9g20.h | 2 +-
> drivers/clk/Makefile | 1 +
> drivers/clk/at91/Makefile | 11 +
> drivers/clk/at91/clk-main.c | 106 +++
> drivers/clk/at91/clk-master.c | 317 +++++++
> drivers/clk/at91/clk-peripheral.c | 371 ++++++++
> drivers/clk/at91/clk-pll.c | 438 +++++++++
> drivers/clk/at91/clk-plldiv.c | 125 +++
> drivers/clk/at91/clk-programmable.c | 368 ++++++++
> drivers/clk/at91/clk-smd.c | 157 ++++
> drivers/clk/at91/clk-system.c | 184 ++++
> drivers/clk/at91/clk-usb.c | 303 ++++++
> drivers/clk/at91/clk-utmi.c | 114 +++
> drivers/usb/gadget/at91_udc.c | 31 +-
> drivers/usb/gadget/at91_udc.h | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> drivers/usb/host/ohci-at91.c | 16 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 116 ++-
> 119 files changed, 8193 insertions(+), 3835 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
> create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
> delete mode 100644 arch/arm/mach-at91/clock.c
> delete mode 100644 arch/arm/mach-at91/clock.h
> create mode 100644 arch/arm/mach-at91/pmc.c
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
> create mode 100644 drivers/clk/at91/clk-master.c
> create mode 100644 drivers/clk/at91/clk-peripheral.c
> create mode 100644 drivers/clk/at91/clk-pll.c
> create mode 100644 drivers/clk/at91/clk-plldiv.c
> create mode 100644 drivers/clk/at91/clk-programmable.c
> create mode 100644 drivers/clk/at91/clk-smd.c
> create mode 100644 drivers/clk/at91/clk-system.c
> create mode 100644 drivers/clk/at91/clk-usb.c
> create mode 100644 drivers/clk/at91/clk-utmi.c
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (78%)
>
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-26 14:10 ` Richard Genoud
-1 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-26 14:10 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, linux-kernel,
linux-arm-kernel
On 17/07/2013 15:34, Boris BREZILLON wrote:
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
Hi Boris,
First of all: Big thumbs up for this work !
Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems:
kernel is next-20130725 with the v4 serie of "ARM: at91: prepare transition to common clk framework"
and v2 serie of "ARM: at91: move to common clk framework"
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.11.0-rc2-next-20130725+ (rgenoud@lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
[ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] AT91: Detected soc type: at91sam9x5
[ 0.000000] AT91: Detected soc subtype: at91sam9g35
[ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
[ 0.000000] On node 0 totalpages: 32768
[ 0.000000] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000
[ 0.000000] Normal zone: 256 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 32768 pages, LIFO batch:7
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
[ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
[ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
[ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
[ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] AT91: PIT: mck rate = 0
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234()
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>] (warn_slowpath_common+0x5c/0x7c)
[ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
[ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
[ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
[ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104)
[ 0.000000] [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
[ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
[ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
[ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4)
[ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
[ 0.000000] [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
[ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
[ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[...]
Best regards,
Richard
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-26 14:10 ` Richard Genoud
0 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-26 14:10 UTC (permalink / raw)
To: linux-arm-kernel
On 17/07/2013 15:34, Boris BREZILLON wrote:
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
Hi Boris,
First of all: Big thumbs up for this work !
Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems:
kernel is next-20130725 with the v4 serie of "ARM: at91: prepare transition to common clk framework"
and v2 serie of "ARM: at91: move to common clk framework"
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.11.0-rc2-next-20130725+ (rgenoud at lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
[ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] AT91: Detected soc type: at91sam9x5
[ 0.000000] AT91: Detected soc subtype: at91sam9g35
[ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
[ 0.000000] On node 0 totalpages: 32768
[ 0.000000] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000
[ 0.000000] Normal zone: 256 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 32768 pages, LIFO batch:7
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
[ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
[ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
[ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
[ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] AT91: PIT: mck rate = 0
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234()
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>] (warn_slowpath_common+0x5c/0x7c)
[ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
[ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
[ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
[ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104)
[ 0.000000] [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
[ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
[ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
[ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
[ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
[ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4)
[ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
[ 0.000000] [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
[ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
[ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
[ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
[ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
[...]
Best regards,
Richard
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-26 14:10 ` Richard Genoud
@ 2013-07-26 15:44 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 15:44 UTC (permalink / raw)
To: Richard Genoud
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette, linux-kernel,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 8391 bytes --]
On 26/07/2013 16:10, Richard Genoud wrote:
> On 17/07/2013 15:34, Boris BREZILLON wrote:
>> Hello,
>>
>> This patch series is a proposal to move at91 clock implementation
>> to common clk framework.
>>
>> Most of the clock provided by the PMC (Power Management Controller) are
>> implemented :
>> - main clock (main oscillator)
>> - pll clocks
>> - master clock
>> - programmable clocks
>> - utmi clock
>> - peripheral clocks
>> - system clocks
>>
>> This implementation is compatible with device tree: the goal is
>> to define the whole clock tree in the device tree (all currently
>> available dt SoCs and boards are patched to support dt clocks).
>> Please feel free to comment the dt bindinds.
>>
>> I removed the register_clocks function in SoC supporting dt boards only:
>> - at91sam9x5 SoCs
>> - at91sam9n12 SoC
>> - sama5d3 SoCs
>>
>> This patch series is based on linux-next and has been tested on sama5d31ek
>> board using device tree. It compiles for other SoCs and both with and without
>> dt support, but it has not been tested.
>>
>> BTW could other people test it on other boards (I only have a kizbox and
>> a sama5d31ek dev kit).
>>
>> Best Regards,
>> Boris
>>
>> Changes since v1:
>> - fix bugs in pll, programmable and system clock implementations
>> (wrong bit position).
>> - add usb clock configuration support (ohci and udc drivers +
>> clk_lookup for non dt boards)
>> - rework of the system clock interfaces (no need to define a parent clock,
>> system clock is a gate with no rate info)
>> - change system, peripheral and programmable clk dt bindings (1 master node
>> and multiple child nodes each defining a system/peripheral or prog clock)
>> - fix bugs in sama5 dt definition
>>
> Hi Boris,
>
> First of all: Big thumbs up for this work !
>
> Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems:
> kernel is next-20130725 with the v4 serie of "ARM: at91: prepare transition to common clk framework"
> and v2 serie of "ARM: at91: move to common clk framework"
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 3.11.0-rc2-next-20130725+ (rgenoud@lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
> [ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> [ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] Memory policy: ECC disabled, Data cache writeback
> [ 0.000000] AT91: Detected soc type: at91sam9x5
> [ 0.000000] AT91: Detected soc subtype: at91sam9g35
> [ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
> [ 0.000000] On node 0 totalpages: 32768
> [ 0.000000] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000
> [ 0.000000] Normal zone: 256 pages used for memmap
> [ 0.000000] Normal zone: 0 pages reserved
> [ 0.000000] Normal zone: 32768 pages, LIFO batch:7
> [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
> [ 0.000000] pcpu-alloc: [0] 0
> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
> [ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
> [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> [ 0.000000] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
> [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
> [ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
> [ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
> [ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
> [ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
> [ 0.000000] AT91: PIT: mck rate = 0
> [ 0.000000] ------------[ cut here ]------------
> [ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234()
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>] (warn_slowpath_common+0x5c/0x7c)
> [ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
> [ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
> [ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
> [ 0.000000] Division by zero in kernel.
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104)
> [ 0.000000] [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [ 0.000000] Division by zero in kernel.
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4)
> [ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
> [ 0.000000] [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [...]
>
> Best regards,
> Richard
Hi Richard,
First, I'd like to thank you for your tests.
Regarding your problem, it seems that mck rate is calculated as 0, which
is either a bug in recalc_rate callback
of master clock driver or a bug in master clock parent clk (no parent
found or bug in the current parent clk recalc_rate function).
I checked the dts[i] files and I found a missing clock-frequency
property for main clock of some
at91sam9x5 boards (those including at91sam9x5cm.dtsi).
You'll find a patch adding this property in attachments.
Tell me if this works for you. If not I'll make a patch adding pr_info
to trace the bug.
Anyway, it should work without this property (main clock rate can be
computed using slow clock rate and MCFR register).
I will investigate this bug...
Best Regards,
Boris
[-- Attachment #2: 0001-ARM-at91-dt-at91sam9x5cm-fix-main-clock-frequency-de.patch --]
[-- Type: text/x-patch, Size: 1032 bytes --]
>From 0a2f054b54fb25d610c64da19220b952a8798805 Mon Sep 17 00:00:00 2001
From: Boris BREZILLON <b.brezillon@overkiz.com>
Date: Fri, 26 Jul 2013 17:30:47 +0200
Subject: [PATCH] ARM: at91/dt: at91sam9x5cm: fix main clock frequency
defintion
---
arch/arm/boot/dts/at91sam9x5cm.dtsi | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4a5ee5c..a613c8c 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -12,17 +12,6 @@
reg = <0x20000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
pinctrl@fffff400 {
@@ -32,6 +21,12 @@
};
};
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-26 15:44 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 15:44 UTC (permalink / raw)
To: linux-arm-kernel
On 26/07/2013 16:10, Richard Genoud wrote:
> On 17/07/2013 15:34, Boris BREZILLON wrote:
>> Hello,
>>
>> This patch series is a proposal to move at91 clock implementation
>> to common clk framework.
>>
>> Most of the clock provided by the PMC (Power Management Controller) are
>> implemented :
>> - main clock (main oscillator)
>> - pll clocks
>> - master clock
>> - programmable clocks
>> - utmi clock
>> - peripheral clocks
>> - system clocks
>>
>> This implementation is compatible with device tree: the goal is
>> to define the whole clock tree in the device tree (all currently
>> available dt SoCs and boards are patched to support dt clocks).
>> Please feel free to comment the dt bindinds.
>>
>> I removed the register_clocks function in SoC supporting dt boards only:
>> - at91sam9x5 SoCs
>> - at91sam9n12 SoC
>> - sama5d3 SoCs
>>
>> This patch series is based on linux-next and has been tested on sama5d31ek
>> board using device tree. It compiles for other SoCs and both with and without
>> dt support, but it has not been tested.
>>
>> BTW could other people test it on other boards (I only have a kizbox and
>> a sama5d31ek dev kit).
>>
>> Best Regards,
>> Boris
>>
>> Changes since v1:
>> - fix bugs in pll, programmable and system clock implementations
>> (wrong bit position).
>> - add usb clock configuration support (ohci and udc drivers +
>> clk_lookup for non dt boards)
>> - rework of the system clock interfaces (no need to define a parent clock,
>> system clock is a gate with no rate info)
>> - change system, peripheral and programmable clk dt bindings (1 master node
>> and multiple child nodes each defining a system/peripheral or prog clock)
>> - fix bugs in sama5 dt definition
>>
> Hi Boris,
>
> First of all: Big thumbs up for this work !
>
> Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see some problems:
> kernel is next-20130725 with the v4 serie of "ARM: at91: prepare transition to common clk framework"
> and v2 serie of "ARM: at91: move to common clk framework"
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 3.11.0-rc2-next-20130725+ (rgenoud at lnx-rg) (gcc version 4.7.3 (Buildroot 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
> [ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> [ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel AT91SAM9G35-EK
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] Memory policy: ECC disabled, Data cache writeback
> [ 0.000000] AT91: Detected soc type: at91sam9x5
> [ 0.000000] AT91: Detected soc subtype: at91sam9g35
> [ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
> [ 0.000000] On node 0 totalpages: 32768
> [ 0.000000] free_area_init_node: node 0, pgdat c039d208, node_mem_map c03b5000
> [ 0.000000] Normal zone: 256 pages used for memmap
> [ 0.000000] Normal zone: 0 pages reserved
> [ 0.000000] Normal zone: 32768 pages, LIFO batch:7
> [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
> [ 0.000000] pcpu-alloc: [0] 0
> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
> [ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8 ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
> [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> [ 0.000000] Memory: 126044K/131072K available (2804K kernel code, 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
> [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
> [ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
> [ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
> [ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
> [ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
> [ 0.000000] AT91: PIT: mck rate = 0
> [ 0.000000] ------------[ cut here ]------------
> [ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-at91/at91sam926x_time.c:259 at91sam926x_pit_init+0x114/0x234()
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>] (warn_slowpath_common+0x5c/0x7c)
> [ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
> [ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
> [ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
> [ 0.000000] Division by zero in kernel.
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104)
> [ 0.000000] [<c003b864>] (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [ 0.000000] Division by zero in kernel.
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 3.11.0-rc2-next-20130725+ #61
> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from [<c000b0f0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>] (Ldiv0_64+0x8/0x18)
> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4)
> [ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
> [ 0.000000] [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>] (__clocksource_register_scale+0xc/0x48)
> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48) from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from [<c035ca4c>] (time_init+0x1c/0x24)
> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>] (start_kernel+0x19c/0x2f4)
> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from [<20008040>] (0x20008040)
> [...]
>
> Best regards,
> Richard
Hi Richard,
First, I'd like to thank you for your tests.
Regarding your problem, it seems that mck rate is calculated as 0, which
is either a bug in recalc_rate callback
of master clock driver or a bug in master clock parent clk (no parent
found or bug in the current parent clk recalc_rate function).
I checked the dts[i] files and I found a missing clock-frequency
property for main clock of some
at91sam9x5 boards (those including at91sam9x5cm.dtsi).
You'll find a patch adding this property in attachments.
Tell me if this works for you. If not I'll make a patch adding pr_info
to trace the bug.
Anyway, it should work without this property (main clock rate can be
computed using slow clock rate and MCFR register).
I will investigate this bug...
Best Regards,
Boris
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-ARM-at91-dt-at91sam9x5cm-fix-main-clock-frequency-de.patch
Type: text/x-patch
Size: 1032 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130726/9e92f78f/attachment.bin>
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-26 15:44 ` boris brezillon
@ 2013-07-26 16:35 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 16:35 UTC (permalink / raw)
To: boris brezillon
Cc: Richard Genoud, Mike Turquette, Nicolas Ferre, linux-kernel,
Ludovic Desroches, Jean-Christophe Plagniol-Villard,
linux-arm-kernel
On 26/07/2013 17:44, boris brezillon wrote:
> On 26/07/2013 16:10, Richard Genoud wrote:
>> On 17/07/2013 15:34, Boris BREZILLON wrote:
>>> Hello,
>>>
>>> This patch series is a proposal to move at91 clock implementation
>>> to common clk framework.
>>>
>>> Most of the clock provided by the PMC (Power Management Controller) are
>>> implemented :
>>> - main clock (main oscillator)
>>> - pll clocks
>>> - master clock
>>> - programmable clocks
>>> - utmi clock
>>> - peripheral clocks
>>> - system clocks
>>>
>>> This implementation is compatible with device tree: the goal is
>>> to define the whole clock tree in the device tree (all currently
>>> available dt SoCs and boards are patched to support dt clocks).
>>> Please feel free to comment the dt bindinds.
>>>
>>> I removed the register_clocks function in SoC supporting dt boards only:
>>> - at91sam9x5 SoCs
>>> - at91sam9n12 SoC
>>> - sama5d3 SoCs
>>>
>>> This patch series is based on linux-next and has been tested on
>>> sama5d31ek
>>> board using device tree. It compiles for other SoCs and both with and
>>> without
>>> dt support, but it has not been tested.
>>>
>>> BTW could other people test it on other boards (I only have a kizbox and
>>> a sama5d31ek dev kit).
>>>
>>> Best Regards,
>>> Boris
>>>
>>> Changes since v1:
>>> - fix bugs in pll, programmable and system clock implementations
>>> (wrong bit position).
>>> - add usb clock configuration support (ohci and udc drivers +
>>> clk_lookup for non dt boards)
>>> - rework of the system clock interfaces (no need to define a parent
>>> clock,
>>> system clock is a gate with no rate info)
>>> - change system, peripheral and programmable clk dt bindings (1
>>> master node
>>> and multiple child nodes each defining a system/peripheral or
>>> prog clock)
>>> - fix bugs in sama5 dt definition
>>>
>> Hi Boris,
>>
>> First of all: Big thumbs up for this work !
>>
>> Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see
>> some problems:
>> kernel is next-20130725 with the v4 serie of "ARM: at91: prepare
>> transition to common clk framework"
>> and v2 serie of "ARM: at91: move to common clk framework"
>>
>> [ 0.000000] Booting Linux on physical CPU 0x0
>> [ 0.000000] Linux version 3.11.0-rc2-next-20130725+
>> (rgenoud@lnx-rg) (gcc version 4.7.3 (Buildroot
>> 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
>> [ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ),
>> cr=00053177
>> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
>> [ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel
>> AT91SAM9G35-EK
>> [ 0.000000] bootconsole [earlycon0] enabled
>> [ 0.000000] Memory policy: ECC disabled, Data cache writeback
>> [ 0.000000] AT91: Detected soc type: at91sam9x5
>> [ 0.000000] AT91: Detected soc subtype: at91sam9g35
>> [ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
>> [ 0.000000] On node 0 totalpages: 32768
>> [ 0.000000] free_area_init_node: node 0, pgdat c039d208,
>> node_mem_map c03b5000
>> [ 0.000000] Normal zone: 256 pages used for memmap
>> [ 0.000000] Normal zone: 0 pages reserved
>> [ 0.000000] Normal zone: 32768 pages, LIFO batch:7
>> [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
>> [ 0.000000] pcpu-alloc: [0] 0
>> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
>> Total pages: 32512
>> [ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8
>> ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
>> [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
>> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536
>> bytes)
>> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768
>> bytes)
>> [ 0.000000] Memory: 126044K/131072K available (2804K kernel code,
>> 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
>> [ 0.000000] Virtual kernel memory layout:
>> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
>> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
>> [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
>> [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
>> [ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
>> [ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
>> [ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
>> [ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
>> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
>> [ 0.000000] AT91: PIT: mck rate = 0
>> [ 0.000000] ------------[ cut here ]------------
>> [ 0.000000] WARNING: CPU: 0 PID: 0 at
>> arch/arm/mach-at91/at91sam926x_time.c:259
>> at91sam926x_pit_init+0x114/0x234()
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>]
>> (warn_slowpath_common+0x5c/0x7c)
>> [ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from
>> [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
>> [ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from
>> [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
>> [ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
>> [ 0.000000] Division by zero in kernel.
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>]
>> (Ldiv0_64+0x8/0x18)
>> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>]
>> (__clocksource_updatefreq_scale+0x30/0x104)
>> [ 0.000000] [<c003b864>]
>> (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>]
>> (__clocksource_register_scale+0xc/0x48)
>> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48)
>> from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
>> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [ 0.000000] Division by zero in kernel.
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>]
>> (Ldiv0_64+0x8/0x18)
>> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>]
>> (clocks_calc_mult_shift+0x70/0xa4)
>> [ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from
>> [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
>> [ 0.000000] [<c003b8e4>]
>> (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>]
>> (__clocksource_register_scale+0xc/0x48)
>> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48)
>> from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
>> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [...]
>>
>> Best regards,
>> Richard
> Hi Richard,
>
> First, I'd like to thank you for your tests.
>
> Regarding your problem, it seems that mck rate is calculated as 0, which
> is either a bug in recalc_rate callback
> of master clock driver or a bug in master clock parent clk (no parent
> found or bug in the current parent clk recalc_rate function).
>
> I checked the dts[i] files and I found a missing clock-frequency
> property for main clock of some
> at91sam9x5 boards (those including at91sam9x5cm.dtsi).
>
> You'll find a patch adding this property in attachments.
> Tell me if this works for you. If not I'll make a patch adding pr_info
> to trace the bug.
>
> Anyway, it should work without this property (main clock rate can be
> computed using slow clock rate and MCFR register).
> I will investigate this bug...
I found 2 bugs:
1) the main frequency ready test in recalc_rate function is wrong
2) the common clk framework uses the first match for dt clk registration
and main clk has this compatible property:
compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
As a result the main clk is always bound to the fixed-clock driver
which set the clock frequency to 0 if 'clock-frequency' property is
missing.
These bugs will be fixed in next version.
Tell me if you want need thesse patches for testing purpose.
>
> Best Regards,
> Boris
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-26 16:35 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-26 16:35 UTC (permalink / raw)
To: linux-arm-kernel
On 26/07/2013 17:44, boris brezillon wrote:
> On 26/07/2013 16:10, Richard Genoud wrote:
>> On 17/07/2013 15:34, Boris BREZILLON wrote:
>>> Hello,
>>>
>>> This patch series is a proposal to move at91 clock implementation
>>> to common clk framework.
>>>
>>> Most of the clock provided by the PMC (Power Management Controller) are
>>> implemented :
>>> - main clock (main oscillator)
>>> - pll clocks
>>> - master clock
>>> - programmable clocks
>>> - utmi clock
>>> - peripheral clocks
>>> - system clocks
>>>
>>> This implementation is compatible with device tree: the goal is
>>> to define the whole clock tree in the device tree (all currently
>>> available dt SoCs and boards are patched to support dt clocks).
>>> Please feel free to comment the dt bindinds.
>>>
>>> I removed the register_clocks function in SoC supporting dt boards only:
>>> - at91sam9x5 SoCs
>>> - at91sam9n12 SoC
>>> - sama5d3 SoCs
>>>
>>> This patch series is based on linux-next and has been tested on
>>> sama5d31ek
>>> board using device tree. It compiles for other SoCs and both with and
>>> without
>>> dt support, but it has not been tested.
>>>
>>> BTW could other people test it on other boards (I only have a kizbox and
>>> a sama5d31ek dev kit).
>>>
>>> Best Regards,
>>> Boris
>>>
>>> Changes since v1:
>>> - fix bugs in pll, programmable and system clock implementations
>>> (wrong bit position).
>>> - add usb clock configuration support (ohci and udc drivers +
>>> clk_lookup for non dt boards)
>>> - rework of the system clock interfaces (no need to define a parent
>>> clock,
>>> system clock is a gate with no rate info)
>>> - change system, peripheral and programmable clk dt bindings (1
>>> master node
>>> and multiple child nodes each defining a system/peripheral or
>>> prog clock)
>>> - fix bugs in sama5 dt definition
>>>
>> Hi Boris,
>>
>> First of all: Big thumbs up for this work !
>>
>> Then, I tested the serie on at91sam9g35ek (sam9x5 familly), and I see
>> some problems:
>> kernel is next-20130725 with the v4 serie of "ARM: at91: prepare
>> transition to common clk framework"
>> and v2 serie of "ARM: at91: move to common clk framework"
>>
>> [ 0.000000] Booting Linux on physical CPU 0x0
>> [ 0.000000] Linux version 3.11.0-rc2-next-20130725+
>> (rgenoud at lnx-rg) (gcc version 4.7.3 (Buildroot
>> 2013.05-00157-g6d1e60b-dirty) ) #61 Fri Jul 26 15:30:13 CEST 2013
>> [ 0.000000] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ),
>> cr=00053177
>> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
>> [ 0.000000] Machine: Atmel AT91SAM (Device Tree), model: Atmel
>> AT91SAM9G35-EK
>> [ 0.000000] bootconsole [earlycon0] enabled
>> [ 0.000000] Memory policy: ECC disabled, Data cache writeback
>> [ 0.000000] AT91: Detected soc type: at91sam9x5
>> [ 0.000000] AT91: Detected soc subtype: at91sam9g35
>> [ 0.000000] AT91: sram at 0x300000 of 0x8000 mapped at 0xfef70000
>> [ 0.000000] On node 0 totalpages: 32768
>> [ 0.000000] free_area_init_node: node 0, pgdat c039d208,
>> node_mem_map c03b5000
>> [ 0.000000] Normal zone: 256 pages used for memmap
>> [ 0.000000] Normal zone: 0 pages reserved
>> [ 0.000000] Normal zone: 32768 pages, LIFO batch:7
>> [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
>> [ 0.000000] pcpu-alloc: [0] 0
>> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
>> Total pages: 32512
>> [ 0.000000] Kernel command line: console=ttyS0,115200 loglevel=8
>> ip=dhcp root=/dev/nfs nfsroot=10.128.0.9:/nfsroot,v3 rw earlyprintk
>> [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
>> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536
>> bytes)
>> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768
>> bytes)
>> [ 0.000000] Memory: 126044K/131072K available (2804K kernel code,
>> 126K rwdata, 592K rodata, 141K init, 93K bss, 5028K reserved)
>> [ 0.000000] Virtual kernel memory layout:
>> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
>> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
>> [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
>> [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
>> [ 0.000000] .text : 0xc0008000 - 0xc0359550 (3398 kB)
>> [ 0.000000] .init : 0xc035a000 - 0xc037d61c ( 142 kB)
>> [ 0.000000] .data : 0xc037e000 - 0xc039d920 ( 127 kB)
>> [ 0.000000] .bss : 0xc039d920 - 0xc03b4ff4 ( 94 kB)
>> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
>> [ 0.000000] AT91: PIT: mck rate = 0
>> [ 0.000000] ------------[ cut here ]------------
>> [ 0.000000] WARNING: CPU: 0 PID: 0 at
>> arch/arm/mach-at91/at91sam926x_time.c:259
>> at91sam926x_pit_init+0x114/0x234()
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c00144e0>]
>> (warn_slowpath_common+0x5c/0x7c)
>> [ 0.000000] [<c00144e0>] (warn_slowpath_common+0x5c/0x7c) from
>> [<c00145b8>] (warn_slowpath_null+0x18/0x1c)
>> [ 0.000000] [<c00145b8>] (warn_slowpath_null+0x18/0x1c) from
>> [<c03607b0>] (at91sam926x_pit_init+0x114/0x234)
>> [ 0.000000] [<c03607b0>] (at91sam926x_pit_init+0x114/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
>> [ 0.000000] Division by zero in kernel.
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>]
>> (Ldiv0_64+0x8/0x18)
>> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b864>]
>> (__clocksource_updatefreq_scale+0x30/0x104)
>> [ 0.000000] [<c003b864>]
>> (__clocksource_updatefreq_scale+0x30/0x104) from [<c003b944>]
>> (__clocksource_register_scale+0xc/0x48)
>> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48)
>> from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
>> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [ 0.000000] Division by zero in kernel.
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
>> 3.11.0-rc2-next-20130725+ #61
>> [ 0.000000] [<c000ca18>] (unwind_backtrace+0x0/0xe0) from
>> [<c000b0f0>] (show_stack+0x10/0x14)
>> [ 0.000000] [<c000b0f0>] (show_stack+0x10/0x14) from [<c013f0a0>]
>> (Ldiv0_64+0x8/0x18)
>> [ 0.000000] [<c013f0a0>] (Ldiv0_64+0x8/0x18) from [<c003b76c>]
>> (clocks_calc_mult_shift+0x70/0xa4)
>> [ 0.000000] [<c003b76c>] (clocks_calc_mult_shift+0x70/0xa4) from
>> [<c003b8e4>] (__clocksource_updatefreq_scale+0xb0/0x104)
>> [ 0.000000] [<c003b8e4>]
>> (__clocksource_updatefreq_scale+0xb0/0x104) from [<c003b944>]
>> (__clocksource_register_scale+0xc/0x48)
>> [ 0.000000] [<c003b944>] (__clocksource_register_scale+0xc/0x48)
>> from [<c0360810>] (at91sam926x_pit_init+0x174/0x234)
>> [ 0.000000] [<c0360810>] (at91sam926x_pit_init+0x174/0x234) from
>> [<c035ca4c>] (time_init+0x1c/0x24)
>> [ 0.000000] [<c035ca4c>] (time_init+0x1c/0x24) from [<c035a650>]
>> (start_kernel+0x19c/0x2f4)
>> [ 0.000000] [<c035a650>] (start_kernel+0x19c/0x2f4) from
>> [<20008040>] (0x20008040)
>> [...]
>>
>> Best regards,
>> Richard
> Hi Richard,
>
> First, I'd like to thank you for your tests.
>
> Regarding your problem, it seems that mck rate is calculated as 0, which
> is either a bug in recalc_rate callback
> of master clock driver or a bug in master clock parent clk (no parent
> found or bug in the current parent clk recalc_rate function).
>
> I checked the dts[i] files and I found a missing clock-frequency
> property for main clock of some
> at91sam9x5 boards (those including at91sam9x5cm.dtsi).
>
> You'll find a patch adding this property in attachments.
> Tell me if this works for you. If not I'll make a patch adding pr_info
> to trace the bug.
>
> Anyway, it should work without this property (main clock rate can be
> computed using slow clock rate and MCFR register).
> I will investigate this bug...
I found 2 bugs:
1) the main frequency ready test in recalc_rate function is wrong
2) the common clk framework uses the first match for dt clk registration
and main clk has this compatible property:
compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
As a result the main clk is always bound to the fixed-clock driver
which set the clock frequency to 0 if 'clock-frequency' property is
missing.
These bugs will be fixed in next version.
Tell me if you want need thesse patches for testing purpose.
>
> Best Regards,
> Boris
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-26 16:35 ` boris brezillon
@ 2013-07-29 8:00 ` Richard Genoud
-1 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 8:00 UTC (permalink / raw)
To: boris brezillon
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
> On 26/07/2013 17:44, boris brezillon wrote:
> I found 2 bugs:
> 1) the main frequency ready test in recalc_rate function is wrong
> 2) the common clk framework uses the first match for dt clk registration
> and main clk has this compatible property:
> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
> As a result the main clk is always bound to the fixed-clock driver
> which set the clock frequency to 0 if 'clock-frequency' property is
> missing.
>
> These bugs will be fixed in next version.
> Tell me if you want need thesse patches for testing purpose.
Hi Boris,
I tested your patch, the clock is not at 0 anymore:
AT91: PIT: mck rate = 8333333
And it's booting correctly.
There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
not 27). (patch attached)
And yes, I could use your patches for some more tests !
Thanks,
Richard.
[-- Attachment #2: 0001-ARM-at91-dt-at91sam9x5-fix-wrong-SSC-clock-ID.patch --]
[-- Type: application/octet-stream, Size: 769 bytes --]
From 7e7693f284a607552c71f976c28d409926d0b73a Mon Sep 17 00:00:00 2001
From: Richard Genoud <richard.genoud@gmail.com>
Date: Mon, 29 Jul 2013 09:47:02 +0200
Subject: [PATCH] ARM: at91/dt: at91sam9x5: fix wrong SSC clock ID
SSC peripheral id is 28, not 27
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
---
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8e70980..d97626f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -286,8 +286,8 @@
id = <26>;
};
- ssc_clk@27 {
- id = <27>;
+ ssc_clk@28 {
+ id = <28>;
};
};
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 8:00 ` Richard Genoud
0 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 8:00 UTC (permalink / raw)
To: linux-arm-kernel
2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
> On 26/07/2013 17:44, boris brezillon wrote:
> I found 2 bugs:
> 1) the main frequency ready test in recalc_rate function is wrong
> 2) the common clk framework uses the first match for dt clk registration
> and main clk has this compatible property:
> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
> As a result the main clk is always bound to the fixed-clock driver
> which set the clock frequency to 0 if 'clock-frequency' property is
> missing.
>
> These bugs will be fixed in next version.
> Tell me if you want need thesse patches for testing purpose.
Hi Boris,
I tested your patch, the clock is not at 0 anymore:
AT91: PIT: mck rate = 8333333
And it's booting correctly.
There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
not 27). (patch attached)
And yes, I could use your patches for some more tests !
Thanks,
Richard.
-------------- next part --------------
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Type: application/octet-stream
Size: 769 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130729/d3e6ee98/attachment.obj>
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 8:00 ` Richard Genoud
@ 2013-07-29 9:25 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 9:25 UTC (permalink / raw)
To: Richard Genoud
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1234 bytes --]
On 29/07/2013 10:00, Richard Genoud wrote:
> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>> On 26/07/2013 17:44, boris brezillon wrote:
>> I found 2 bugs:
>> 1) the main frequency ready test in recalc_rate function is wrong
>> 2) the common clk framework uses the first match for dt clk registration
>> and main clk has this compatible property:
>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>> As a result the main clk is always bound to the fixed-clock driver
>> which set the clock frequency to 0 if 'clock-frequency' property is
>> missing.
>>
>> These bugs will be fixed in next version.
>> Tell me if you want need thesse patches for testing purpose.
> Hi Boris,
>
> I tested your patch, the clock is not at 0 anymore:
> AT91: PIT: mck rate = 8333333
>
> And it's booting correctly.
> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
> not 27). (patch attached)
>
> And yes, I could use your patches for some more tests !
>
> Thanks,
>
> Richard.
Hi Richard,
Thanks for the bug report.
You'll find in attachements the pre-v3 series fixing the detected bugs
(including the ssc clock id bug).
If you need anything else please let me know.
Best Regards,
Boris
[-- Attachment #2: at91-clk-v3.tgz --]
[-- Type: application/x-compressed-tar, Size: 61170 bytes --]
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 9:25 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 9:25 UTC (permalink / raw)
To: linux-arm-kernel
On 29/07/2013 10:00, Richard Genoud wrote:
> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>> On 26/07/2013 17:44, boris brezillon wrote:
>> I found 2 bugs:
>> 1) the main frequency ready test in recalc_rate function is wrong
>> 2) the common clk framework uses the first match for dt clk registration
>> and main clk has this compatible property:
>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>> As a result the main clk is always bound to the fixed-clock driver
>> which set the clock frequency to 0 if 'clock-frequency' property is
>> missing.
>>
>> These bugs will be fixed in next version.
>> Tell me if you want need thesse patches for testing purpose.
> Hi Boris,
>
> I tested your patch, the clock is not at 0 anymore:
> AT91: PIT: mck rate = 8333333
>
> And it's booting correctly.
> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
> not 27). (patch attached)
>
> And yes, I could use your patches for some more tests !
>
> Thanks,
>
> Richard.
Hi Richard,
Thanks for the bug report.
You'll find in attachements the pre-v3 series fixing the detected bugs
(including the ssc clock id bug).
If you need anything else please let me know.
Best Regards,
Boris
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^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 9:25 ` boris brezillon
@ 2013-07-29 14:18 ` Richard Genoud
-1 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 14:18 UTC (permalink / raw)
To: boris brezillon
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
> On 29/07/2013 10:00, Richard Genoud wrote:
>>
>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>
>>> On 26/07/2013 17:44, boris brezillon wrote:
>>> I found 2 bugs:
>>> 1) the main frequency ready test in recalc_rate function is wrong
>>> 2) the common clk framework uses the first match for dt clk registration
>>> and main clk has this compatible property:
>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>> As a result the main clk is always bound to the fixed-clock driver
>>> which set the clock frequency to 0 if 'clock-frequency' property is
>>> missing.
>>>
>>> These bugs will be fixed in next version.
>>> Tell me if you want need thesse patches for testing purpose.
>>
>> Hi Boris,
>>
>> I tested your patch, the clock is not at 0 anymore:
>> AT91: PIT: mck rate = 8333333
>>
>> And it's booting correctly.
>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>> not 27). (patch attached)
>>
>> And yes, I could use your patches for some more tests !
>>
>> Thanks,
>>
>> Richard.
>
> Hi Richard,
>
> Thanks for the bug report.
>
> You'll find in attachements the pre-v3 series fixing the detected bugs
> (including the ssc clock id bug).
>
> If you need anything else please let me know.
Working on sam9g35ek !
you can add my:
Tested-by: Richard Genoud <richard.genoud@gmail.com>
One remark though:
Maybe it would be interesting to keep using the defines in the device
tree for peripheral IDs.
For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
ssc_clk@28 {
id = <28>;
};
May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
IMHO, all AT91SAM9X5_ID_xxx in
arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
include/dt-bindings/ and used in at91sam9x5.dtsi
Best regards,
Richard.
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 14:18 ` Richard Genoud
0 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 14:18 UTC (permalink / raw)
To: linux-arm-kernel
2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
> On 29/07/2013 10:00, Richard Genoud wrote:
>>
>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>
>>> On 26/07/2013 17:44, boris brezillon wrote:
>>> I found 2 bugs:
>>> 1) the main frequency ready test in recalc_rate function is wrong
>>> 2) the common clk framework uses the first match for dt clk registration
>>> and main clk has this compatible property:
>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>> As a result the main clk is always bound to the fixed-clock driver
>>> which set the clock frequency to 0 if 'clock-frequency' property is
>>> missing.
>>>
>>> These bugs will be fixed in next version.
>>> Tell me if you want need thesse patches for testing purpose.
>>
>> Hi Boris,
>>
>> I tested your patch, the clock is not at 0 anymore:
>> AT91: PIT: mck rate = 8333333
>>
>> And it's booting correctly.
>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>> not 27). (patch attached)
>>
>> And yes, I could use your patches for some more tests !
>>
>> Thanks,
>>
>> Richard.
>
> Hi Richard,
>
> Thanks for the bug report.
>
> You'll find in attachements the pre-v3 series fixing the detected bugs
> (including the ssc clock id bug).
>
> If you need anything else please let me know.
Working on sam9g35ek !
you can add my:
Tested-by: Richard Genoud <richard.genoud@gmail.com>
One remark though:
Maybe it would be interesting to keep using the defines in the device
tree for peripheral IDs.
For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
ssc_clk at 28 {
id = <28>;
};
May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
IMHO, all AT91SAM9X5_ID_xxx in
arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
include/dt-bindings/ and used in at91sam9x5.dtsi
Best regards,
Richard.
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 14:18 ` Richard Genoud
@ 2013-07-29 14:34 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 14:34 UTC (permalink / raw)
To: Richard Genoud
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
On 29/07/2013 16:18, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 10:00, Richard Genoud wrote:
>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>> I found 2 bugs:
>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>> 2) the common clk framework uses the first match for dt clk registration
>>>> and main clk has this compatible property:
>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>> As a result the main clk is always bound to the fixed-clock driver
>>>> which set the clock frequency to 0 if 'clock-frequency' property is
>>>> missing.
>>>>
>>>> These bugs will be fixed in next version.
>>>> Tell me if you want need thesse patches for testing purpose.
>>> Hi Boris,
>>>
>>> I tested your patch, the clock is not at 0 anymore:
>>> AT91: PIT: mck rate = 8333333
>>>
>>> And it's booting correctly.
>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>> not 27). (patch attached)
>>>
>>> And yes, I could use your patches for some more tests !
>>>
>>> Thanks,
>>>
>>> Richard.
>> Hi Richard,
>>
>> Thanks for the bug report.
>>
>> You'll find in attachements the pre-v3 series fixing the detected bugs
>> (including the ssc clock id bug).
>>
>> If you need anything else please let me know.
> Working on sam9g35ek !
> you can add my:
> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>
>
> One remark though:
> Maybe it would be interesting to keep using the defines in the device
> tree for peripheral IDs.
> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
> ssc_clk@28 {
> id = <28>;
> };
> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>
> IMHO, all AT91SAM9X5_ID_xxx in
> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
> include/dt-bindings/ and used in at91sam9x5.dtsi
This was requested by Jean-Christophe too.
I'll add these macro files and make use of it in next version.
BTW where should I put these macro files
(include/dt-bindings/at91/'soc-name'/peripherals.h) ?
Should I use macros for address fied of clocks or just for id property
(or drop the address) ?
ssc_clk@AT91SAM9X5_ID_SSC {
id = <AT91SAM9X5_ID_SSC>;
};
or
ssc_clk@28 {
id = <AT91SAM9X5_ID_SSC>;
};
or
ssc_clk {
id = <AT91SAM9X5_ID_SSC>;
};
>
> Best regards,
> Richard.
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 14:34 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 14:34 UTC (permalink / raw)
To: linux-arm-kernel
On 29/07/2013 16:18, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 10:00, Richard Genoud wrote:
>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>> I found 2 bugs:
>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>> 2) the common clk framework uses the first match for dt clk registration
>>>> and main clk has this compatible property:
>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>> As a result the main clk is always bound to the fixed-clock driver
>>>> which set the clock frequency to 0 if 'clock-frequency' property is
>>>> missing.
>>>>
>>>> These bugs will be fixed in next version.
>>>> Tell me if you want need thesse patches for testing purpose.
>>> Hi Boris,
>>>
>>> I tested your patch, the clock is not at 0 anymore:
>>> AT91: PIT: mck rate = 8333333
>>>
>>> And it's booting correctly.
>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>> not 27). (patch attached)
>>>
>>> And yes, I could use your patches for some more tests !
>>>
>>> Thanks,
>>>
>>> Richard.
>> Hi Richard,
>>
>> Thanks for the bug report.
>>
>> You'll find in attachements the pre-v3 series fixing the detected bugs
>> (including the ssc clock id bug).
>>
>> If you need anything else please let me know.
> Working on sam9g35ek !
> you can add my:
> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>
>
> One remark though:
> Maybe it would be interesting to keep using the defines in the device
> tree for peripheral IDs.
> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
> ssc_clk at 28 {
> id = <28>;
> };
> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>
> IMHO, all AT91SAM9X5_ID_xxx in
> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
> include/dt-bindings/ and used in at91sam9x5.dtsi
This was requested by Jean-Christophe too.
I'll add these macro files and make use of it in next version.
BTW where should I put these macro files
(include/dt-bindings/at91/'soc-name'/peripherals.h) ?
Should I use macros for address fied of clocks or just for id property
(or drop the address) ?
ssc_clk at AT91SAM9X5_ID_SSC {
id = <AT91SAM9X5_ID_SSC>;
};
or
ssc_clk at 28 {
id = <AT91SAM9X5_ID_SSC>;
};
or
ssc_clk {
id = <AT91SAM9X5_ID_SSC>;
};
>
> Best regards,
> Richard.
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 14:34 ` boris brezillon
@ 2013-07-29 15:09 ` Richard Genoud
-1 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 15:09 UTC (permalink / raw)
To: boris brezillon
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
> On 29/07/2013 16:18, Richard Genoud wrote:
>>
>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>
>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>
>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>
>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>> I found 2 bugs:
>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>> 2) the common clk framework uses the first match for dt clk
>>>>> registration
>>>>> and main clk has this compatible property:
>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>> is
>>>>> missing.
>>>>>
>>>>> These bugs will be fixed in next version.
>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>
>>>> Hi Boris,
>>>>
>>>> I tested your patch, the clock is not at 0 anymore:
>>>> AT91: PIT: mck rate = 8333333
>>>>
>>>> And it's booting correctly.
>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>> not 27). (patch attached)
>>>>
>>>> And yes, I could use your patches for some more tests !
>>>>
>>>> Thanks,
>>>>
>>>> Richard.
>>>
>>> Hi Richard,
>>>
>>> Thanks for the bug report.
>>>
>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>> (including the ssc clock id bug).
>>>
>>> If you need anything else please let me know.
>>
>> Working on sam9g35ek !
>> you can add my:
>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>
>>
>> One remark though:
>> Maybe it would be interesting to keep using the defines in the device
>> tree for peripheral IDs.
>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>> ssc_clk@28 {
>> id = <28>;
>> };
>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>
>> IMHO, all AT91SAM9X5_ID_xxx in
>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>> include/dt-bindings/ and used in at91sam9x5.dtsi
>
> This was requested by Jean-Christophe too.
> I'll add these macro files and make use of it in next version.
>
> BTW where should I put these macro files
> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
That sounds correct I suppose.
> Should I use macros for address fied of clocks or just for id property (or
> drop the address) ?
>
> ssc_clk@AT91SAM9X5_ID_SSC {
> id = <AT91SAM9X5_ID_SSC>;
> };
>
> or
>
> ssc_clk@28 {
> id = <AT91SAM9X5_ID_SSC>;
> };
>
> or
>
> ssc_clk {
> id = <AT91SAM9X5_ID_SSC>;
> };
I would drop the address, since the names are always different (for
instance, dma0_clk and dma1_clk are used).
And the define should also be used here:
ssc0: ssc@f0010000 { [...]
clocks = <&periph AT91SAM9X5_ID_SSC>;
[...]
}
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 15:09 ` Richard Genoud
0 siblings, 0 replies; 129+ messages in thread
From: Richard Genoud @ 2013-07-29 15:09 UTC (permalink / raw)
To: linux-arm-kernel
2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
> On 29/07/2013 16:18, Richard Genoud wrote:
>>
>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>
>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>
>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>
>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>> I found 2 bugs:
>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>> 2) the common clk framework uses the first match for dt clk
>>>>> registration
>>>>> and main clk has this compatible property:
>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>> is
>>>>> missing.
>>>>>
>>>>> These bugs will be fixed in next version.
>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>
>>>> Hi Boris,
>>>>
>>>> I tested your patch, the clock is not at 0 anymore:
>>>> AT91: PIT: mck rate = 8333333
>>>>
>>>> And it's booting correctly.
>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>> not 27). (patch attached)
>>>>
>>>> And yes, I could use your patches for some more tests !
>>>>
>>>> Thanks,
>>>>
>>>> Richard.
>>>
>>> Hi Richard,
>>>
>>> Thanks for the bug report.
>>>
>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>> (including the ssc clock id bug).
>>>
>>> If you need anything else please let me know.
>>
>> Working on sam9g35ek !
>> you can add my:
>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>
>>
>> One remark though:
>> Maybe it would be interesting to keep using the defines in the device
>> tree for peripheral IDs.
>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>> ssc_clk at 28 {
>> id = <28>;
>> };
>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>
>> IMHO, all AT91SAM9X5_ID_xxx in
>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>> include/dt-bindings/ and used in at91sam9x5.dtsi
>
> This was requested by Jean-Christophe too.
> I'll add these macro files and make use of it in next version.
>
> BTW where should I put these macro files
> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
That sounds correct I suppose.
> Should I use macros for address fied of clocks or just for id property (or
> drop the address) ?
>
> ssc_clk at AT91SAM9X5_ID_SSC {
> id = <AT91SAM9X5_ID_SSC>;
> };
>
> or
>
> ssc_clk at 28 {
> id = <AT91SAM9X5_ID_SSC>;
> };
>
> or
>
> ssc_clk {
> id = <AT91SAM9X5_ID_SSC>;
> };
I would drop the address, since the names are always different (for
instance, dma0_clk and dma1_clk are used).
And the define should also be used here:
ssc0: ssc at f0010000 { [...]
clocks = <&periph AT91SAM9X5_ID_SSC>;
[...]
}
^ permalink raw reply [flat|nested] 129+ messages in thread* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 15:09 ` Richard Genoud
@ 2013-07-29 15:14 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 15:14 UTC (permalink / raw)
To: Richard Genoud
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
On 29/07/2013 17:09, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 16:18, Richard Genoud wrote:
>>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>>> I found 2 bugs:
>>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>>> 2) the common clk framework uses the first match for dt clk
>>>>>> registration
>>>>>> and main clk has this compatible property:
>>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>>> is
>>>>>> missing.
>>>>>>
>>>>>> These bugs will be fixed in next version.
>>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>> Hi Boris,
>>>>>
>>>>> I tested your patch, the clock is not at 0 anymore:
>>>>> AT91: PIT: mck rate = 8333333
>>>>>
>>>>> And it's booting correctly.
>>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>>> not 27). (patch attached)
>>>>>
>>>>> And yes, I could use your patches for some more tests !
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Richard.
>>>> Hi Richard,
>>>>
>>>> Thanks for the bug report.
>>>>
>>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>>> (including the ssc clock id bug).
>>>>
>>>> If you need anything else please let me know.
>>> Working on sam9g35ek !
>>> you can add my:
>>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>>
>>>
>>> One remark though:
>>> Maybe it would be interesting to keep using the defines in the device
>>> tree for peripheral IDs.
>>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>>> ssc_clk@28 {
>>> id = <28>;
>>> };
>>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>>
>>> IMHO, all AT91SAM9X5_ID_xxx in
>>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>>> include/dt-bindings/ and used in at91sam9x5.dtsi
>> This was requested by Jean-Christophe too.
>> I'll add these macro files and make use of it in next version.
>>
>> BTW where should I put these macro files
>> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
> That sounds correct I suppose.
Ok, I will use this path pattern.
>> Should I use macros for address fied of clocks or just for id property (or
>> drop the address) ?
>>
>> ssc_clk@AT91SAM9X5_ID_SSC {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk@28 {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
> I would drop the address, since the names are always different (for
> instance, dma0_clk and dma1_clk are used).
Ok, I'll drop the address.
> And the define should also be used here:
> ssc0: ssc@f0010000 { [...]
> clocks = <&periph AT91SAM9X5_ID_SSC>;
> [...]
> }
Yes of course, and it should be used for interrupt ids too (but this
will not be part of this series :)).
Thanks for your review.
Best Regards,
Boris
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 15:14 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 15:14 UTC (permalink / raw)
To: linux-arm-kernel
On 29/07/2013 17:09, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 16:18, Richard Genoud wrote:
>>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>>> I found 2 bugs:
>>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>>> 2) the common clk framework uses the first match for dt clk
>>>>>> registration
>>>>>> and main clk has this compatible property:
>>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>>> is
>>>>>> missing.
>>>>>>
>>>>>> These bugs will be fixed in next version.
>>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>> Hi Boris,
>>>>>
>>>>> I tested your patch, the clock is not at 0 anymore:
>>>>> AT91: PIT: mck rate = 8333333
>>>>>
>>>>> And it's booting correctly.
>>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>>> not 27). (patch attached)
>>>>>
>>>>> And yes, I could use your patches for some more tests !
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Richard.
>>>> Hi Richard,
>>>>
>>>> Thanks for the bug report.
>>>>
>>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>>> (including the ssc clock id bug).
>>>>
>>>> If you need anything else please let me know.
>>> Working on sam9g35ek !
>>> you can add my:
>>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>>
>>>
>>> One remark though:
>>> Maybe it would be interesting to keep using the defines in the device
>>> tree for peripheral IDs.
>>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>>> ssc_clk at 28 {
>>> id = <28>;
>>> };
>>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>>
>>> IMHO, all AT91SAM9X5_ID_xxx in
>>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>>> include/dt-bindings/ and used in at91sam9x5.dtsi
>> This was requested by Jean-Christophe too.
>> I'll add these macro files and make use of it in next version.
>>
>> BTW where should I put these macro files
>> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
> That sounds correct I suppose.
Ok, I will use this path pattern.
>> Should I use macros for address fied of clocks or just for id property (or
>> drop the address) ?
>>
>> ssc_clk at AT91SAM9X5_ID_SSC {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk at 28 {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
> I would drop the address, since the names are always different (for
> instance, dma0_clk and dma1_clk are used).
Ok, I'll drop the address.
> And the define should also be used here:
> ssc0: ssc at f0010000 { [...]
> clocks = <&periph AT91SAM9X5_ID_SSC>;
> [...]
> }
Yes of course, and it should be used for interrupt ids too (but this
will not be part of this series :)).
Thanks for your review.
Best Regards,
Boris
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-29 15:09 ` Richard Genoud
@ 2013-07-29 16:44 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 16:44 UTC (permalink / raw)
To: Richard Genoud
Cc: Mike Turquette, Nicolas Ferre, linux-kernel, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, linux-arm-kernel
On 29/07/2013 17:09, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 16:18, Richard Genoud wrote:
>>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>>> I found 2 bugs:
>>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>>> 2) the common clk framework uses the first match for dt clk
>>>>>> registration
>>>>>> and main clk has this compatible property:
>>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>>> is
>>>>>> missing.
>>>>>>
>>>>>> These bugs will be fixed in next version.
>>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>> Hi Boris,
>>>>>
>>>>> I tested your patch, the clock is not at 0 anymore:
>>>>> AT91: PIT: mck rate = 8333333
>>>>>
>>>>> And it's booting correctly.
>>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>>> not 27). (patch attached)
>>>>>
>>>>> And yes, I could use your patches for some more tests !
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Richard.
>>>> Hi Richard,
>>>>
>>>> Thanks for the bug report.
>>>>
>>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>>> (including the ssc clock id bug).
>>>>
>>>> If you need anything else please let me know.
>>> Working on sam9g35ek !
>>> you can add my:
>>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>>
>>>
>>> One remark though:
>>> Maybe it would be interesting to keep using the defines in the device
>>> tree for peripheral IDs.
>>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>>> ssc_clk@28 {
>>> id = <28>;
>>> };
>>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>>
>>> IMHO, all AT91SAM9X5_ID_xxx in
>>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>>> include/dt-bindings/ and used in at91sam9x5.dtsi
>> This was requested by Jean-Christophe too.
>> I'll add these macro files and make use of it in next version.
>>
>> BTW where should I put these macro files
>> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
> That sounds correct I suppose.
I guess I should do the same for system clks :-).
>> Should I use macros for address fied of clocks or just for id property (or
>> drop the address) ?
>>
>> ssc_clk@AT91SAM9X5_ID_SSC {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk@28 {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
> I would drop the address, since the names are always different (for
> instance, dma0_clk and dma1_clk are used).
> And the define should also be used here:
> ssc0: ssc@f0010000 { [...]
> clocks = <&periph AT91SAM9X5_ID_SSC>;
> [...]
> }
^ permalink raw reply [flat|nested] 129+ messages in thread* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-29 16:44 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-29 16:44 UTC (permalink / raw)
To: linux-arm-kernel
On 29/07/2013 17:09, Richard Genoud wrote:
> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>> On 29/07/2013 16:18, Richard Genoud wrote:
>>> 2013/7/29 boris brezillon <b.brezillon@overkiz.com>:
>>>> On 29/07/2013 10:00, Richard Genoud wrote:
>>>>> 2013/7/26 boris brezillon <b.brezillon@overkiz.com>:
>>>>>> On 26/07/2013 17:44, boris brezillon wrote:
>>>>>> I found 2 bugs:
>>>>>> 1) the main frequency ready test in recalc_rate function is wrong
>>>>>> 2) the common clk framework uses the first match for dt clk
>>>>>> registration
>>>>>> and main clk has this compatible property:
>>>>>> compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
>>>>>> As a result the main clk is always bound to the fixed-clock driver
>>>>>> which set the clock frequency to 0 if 'clock-frequency' property
>>>>>> is
>>>>>> missing.
>>>>>>
>>>>>> These bugs will be fixed in next version.
>>>>>> Tell me if you want need thesse patches for testing purpose.
>>>>> Hi Boris,
>>>>>
>>>>> I tested your patch, the clock is not at 0 anymore:
>>>>> AT91: PIT: mck rate = 8333333
>>>>>
>>>>> And it's booting correctly.
>>>>> There's a small bug I found in the at91sam9x5 dtsi file (ssc id is 28,
>>>>> not 27). (patch attached)
>>>>>
>>>>> And yes, I could use your patches for some more tests !
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Richard.
>>>> Hi Richard,
>>>>
>>>> Thanks for the bug report.
>>>>
>>>> You'll find in attachements the pre-v3 series fixing the detected bugs
>>>> (including the ssc clock id bug).
>>>>
>>>> If you need anything else please let me know.
>>> Working on sam9g35ek !
>>> you can add my:
>>> Tested-by: Richard Genoud <richard.genoud@gmail.com>
>>>
>>>
>>> One remark though:
>>> Maybe it would be interesting to keep using the defines in the device
>>> tree for peripheral IDs.
>>> For instance, in arch/arm/boot/dts/at91sam9x5.dtsi : (patch 33)
>>> ssc_clk at 28 {
>>> id = <28>;
>>> };
>>> May be more readable with the SSC id AT91SAM9X5_ID_SSC, as it was
>>> defined in arch/arm/mach-at91/at91sam9x5.c (removed with patch 20)
>>>
>>> IMHO, all AT91SAM9X5_ID_xxx in
>>> arch/arm/mach-at91/include/mach/at91sam9x5.h can me moved in
>>> include/dt-bindings/ and used in at91sam9x5.dtsi
>> This was requested by Jean-Christophe too.
>> I'll add these macro files and make use of it in next version.
>>
>> BTW where should I put these macro files
>> (include/dt-bindings/at91/'soc-name'/peripherals.h) ?
> That sounds correct I suppose.
I guess I should do the same for system clks :-).
>> Should I use macros for address fied of clocks or just for id property (or
>> drop the address) ?
>>
>> ssc_clk at AT91SAM9X5_ID_SSC {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk at 28 {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
>>
>> or
>>
>> ssc_clk {
>> id = <AT91SAM9X5_ID_SSC>;
>> };
> I would drop the address, since the names are always different (for
> instance, dma0_clk and dma1_clk are used).
> And the define should also be used here:
> ssc0: ssc at f0010000 { [...]
> clocks = <&periph AT91SAM9X5_ID_SSC>;
> [...]
> }
^ permalink raw reply [flat|nested] 129+ messages in thread
* Re: [PATCH v2 00/42] ARM: at91: move to common clk framework
2013-07-17 13:34 ` Boris BREZILLON
@ 2013-07-27 4:41 ` boris brezillon
-1 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-27 4:41 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Nicolas Ferre, Ludovic Desroches,
Jean-Christophe Plagniol-Villard, Mike Turquette,
linux-arm-kernel, linux-kernel
Hello,
This email is a feedback on the discussion I had with Jean-Christophe
last Wednesday.
As discussed with him, I will try to split this patch series in order to
1) limit the number of patches to review
2) limit the number of SoCs/boards to test
The new at91 clk support on non-dt boards was also discussed, and
Jean-Christophe thinks this is not mandatory (and should be dropped).
Does anyone see an interest in keeping this support in the next version
of the patch series ?
Here is how he though this patch series could be splitted:
1) at91 common clk implemenations + 1 SoC and the associated dt boards
2) 1 SoC and the associated dt boards
...)1 SoC and the associated dt boards
I tried to prepare the first new patch series by including only
at91sam9260/9g20 SoCs and boards but I failed. In fact I succeed but it
breaks multi-soc support (using dt) because we can't use both the common
clk framework and the at91 specific clk framework (they both provides
the same set of functions and structures definitions).
Should I break the multi-soc support to add at91 common clk ?
The only SoC that could be added without breaking multi-soc support is
the sama5 as it uses a different arm architecture (ARMv7) and thus
cannot be compiled in the same kernel as other at91 socs.
Should I choose the sama5 for the next patch series ?
Jean-Christophe, could you at least review the 11 first patches of this
series ?
I won't send any new version until I get some feedback from you on the
clk implementations and dt bindings...
Berst Regards,
Boris
Le 17/07/2013 15:34, Boris BREZILLON a écrit :
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
> Boris BREZILLON (42):
> ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
> ARM: at91: add PMC main clock
> ARM: at91: add PMC pll clocks
> ARM: at91: add PMC master clock
> ARM: at91: add PMC system clocks
> ARM: at91: add PMC peripheral clocks
> ARM: at91: add PMC programmable clocks
> ARM: at91: add PMC utmi clock
> ARM: at91: add PMC usb clock
> ARM: at91: add PMC smd clock
> ARM: at91: add PMC clk device tree binding doc.
> ARM: at91: move to common clk framework
> ARM: at91: move at91rm9200 SoC to new at91 clk implem
> ARM: at91: move at91sam9260 SoC to new at91 clk implem
> ARM: at91: move at91sam9261 SoC to new at91 clk implem
> ARM: at91: move at91sam9263 SoC to new at91 clk implem
> ARM: at91: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91: move at91sam9rl SoC to new at91 clk implem
> ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91: move at91sam9 SoCs to new at91 clk implem
> ARM: at91: move sama5d3 SoCs to new at91 clk implem
> ARM: at91: move at91rm9200 boards to new at91 clk implem
> ARM: at91: move at91sam9 boards to new at91 clk implem
> ARM: at91: move pit timer to common clk framework
> USB: ohci-at91: add usb_clk for transition to common clk framework
> usb: gadget: at91_udc: add usb_clk for transition to common clk
> framework
> ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
> ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
> ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
> ARM: at91/dt: move rm9200 boards to new at91 clk implem
> ARM: at91/dt: move sam9263 boards to new at91 clk implem
> ARM: at91/dt: move sam9g45 boards to new at91 clk implem
> ARM: at91/dt: move sam9n12 boards to new at91 clk implem
> ARM: at91/dt: move sam9x5 boards to new at91 clk implem
> ARM: at91/dt: move sama5d3 boards to new at91 clk implem
>
> .../devicetree/bindings/clock/at91-clock.txt | 262 ++++++
> arch/arm/boot/dts/animeo_ip.dts | 17 +-
> arch/arm/boot/dts/at91-ariag25.dts | 17 +-
> arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++
> arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9260.dtsi | 236 +++++
> arch/arm/boot/dts/at91sam9263.dtsi | 237 +++++
> arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
> arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
> arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
> arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
> arch/arm/boot/dts/at91sam9g45.dtsi | 257 +++++
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9n12.dtsi | 251 +++++
> arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
> arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
> arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++--
> arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +
> arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +
> arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +
> arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 ++
> arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 ++
> arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++
> arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
> arch/arm/boot/dts/kizbox.dts | 5 +
> arch/arm/boot/dts/mpa1600.dts | 16 +-
> arch/arm/boot/dts/pm9g45.dts | 16 +-
> arch/arm/boot/dts/sama5d3.dtsi | 510 ++++++----
> arch/arm/boot/dts/sama5d31ek.dts | 4 +
> arch/arm/boot/dts/sama5d33ek.dts | 2 +
> arch/arm/boot/dts/sama5d34ek.dts | 4 +
> arch/arm/boot/dts/sama5d35ek.dts | 6 +
> arch/arm/boot/dts/sama5d3_can.dtsi | 71 ++
> arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++
> arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++
> arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 ++
> arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++
> arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +
> arch/arm/boot/dts/sama5d3_uart.dtsi | 46 +
> arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9263.dts | 17 +-
> arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/usb_a9263.dts | 17 +-
> arch/arm/mach-at91/Kconfig | 26 +
> arch/arm/mach-at91/Makefile | 2 +-
> arch/arm/mach-at91/at91rm9200.c | 568 +++++++-----
> arch/arm/mach-at91/at91sam9260.c | 689 +++++++++-----
> arch/arm/mach-at91/at91sam9261.c | 572 ++++++++----
> arch/arm/mach-at91/at91sam9263.c | 595 +++++++-----
> arch/arm/mach-at91/at91sam926x_time.c | 21 +-
> arch/arm/mach-at91/at91sam9g45.c | 704 ++++++++------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> arch/arm/mach-at91/at91sam9n12.c | 196 +---
> arch/arm/mach-at91/at91sam9rl.c | 502 ++++++----
> arch/arm/mach-at91/at91sam9x5.c | 293 +-----
> arch/arm/mach-at91/board-1arm.c | 12 +-
> arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
> arch/arm/mach-at91/board-cam60.c | 13 +-
> arch/arm/mach-at91/board-carmeva.c | 13 +-
> arch/arm/mach-at91/board-cpu9krea.c | 12 +-
> arch/arm/mach-at91/board-cpuat91.c | 12 +-
> arch/arm/mach-at91/board-csb337.c | 11 +-
> arch/arm/mach-at91/board-csb637.c | 11 +-
> arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
> arch/arm/mach-at91/board-dt-sam9.c | 9 +-
> arch/arm/mach-at91/board-dt-sama5.c | 9 +-
> arch/arm/mach-at91/board-eb9200.c | 11 +-
> arch/arm/mach-at91/board-ecbat91.c | 12 +-
> arch/arm/mach-at91/board-eco920.c | 13 +-
> arch/arm/mach-at91/board-flexibity.c | 12 +-
> arch/arm/mach-at91/board-foxg20.c | 12 +-
> arch/arm/mach-at91/board-gsia18s.c | 8 +-
> arch/arm/mach-at91/board-kafa.c | 12 +-
> arch/arm/mach-at91/board-kb9202.c | 12 +-
> arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
> arch/arm/mach-at91/board-picotux200.c | 11 +-
> arch/arm/mach-at91/board-qil-a9260.c | 11 +-
> arch/arm/mach-at91/board-rm9200ek.c | 11 +-
> arch/arm/mach-at91/board-rsi-ews.c | 12 +-
> arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
> arch/arm/mach-at91/board-sam9260ek.c | 11 +-
> arch/arm/mach-at91/board-sam9261ek.c | 15 +-
> arch/arm/mach-at91/board-sam9263ek.c | 11 +-
> arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
> arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
> arch/arm/mach-at91/board-sam9rlek.c | 11 +-
> arch/arm/mach-at91/board-snapper9260.c | 12 +-
> arch/arm/mach-at91/board-stamp9g20.c | 15 +-
> arch/arm/mach-at91/board-yl-9200.c | 12 +-
> arch/arm/mach-at91/clock.c | 977 --------------------
> arch/arm/mach-at91/clock.h | 49 -
> arch/arm/mach-at91/generic.h | 10 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/pmc.c | 58 ++
> arch/arm/mach-at91/sama5d3.c | 344 +------
> arch/arm/mach-at91/setup.c | 38 +-
> arch/arm/mach-at91/stamp9g20.h | 2 +-
> drivers/clk/Makefile | 1 +
> drivers/clk/at91/Makefile | 11 +
> drivers/clk/at91/clk-main.c | 106 +++
> drivers/clk/at91/clk-master.c | 317 +++++++
> drivers/clk/at91/clk-peripheral.c | 371 ++++++++
> drivers/clk/at91/clk-pll.c | 438 +++++++++
> drivers/clk/at91/clk-plldiv.c | 125 +++
> drivers/clk/at91/clk-programmable.c | 368 ++++++++
> drivers/clk/at91/clk-smd.c | 157 ++++
> drivers/clk/at91/clk-system.c | 184 ++++
> drivers/clk/at91/clk-usb.c | 303 ++++++
> drivers/clk/at91/clk-utmi.c | 114 +++
> drivers/usb/gadget/at91_udc.c | 31 +-
> drivers/usb/gadget/at91_udc.h | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> drivers/usb/host/ohci-at91.c | 16 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 116 ++-
> 119 files changed, 8193 insertions(+), 3835 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
> create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
> delete mode 100644 arch/arm/mach-at91/clock.c
> delete mode 100644 arch/arm/mach-at91/clock.h
> create mode 100644 arch/arm/mach-at91/pmc.c
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
> create mode 100644 drivers/clk/at91/clk-master.c
> create mode 100644 drivers/clk/at91/clk-peripheral.c
> create mode 100644 drivers/clk/at91/clk-pll.c
> create mode 100644 drivers/clk/at91/clk-plldiv.c
> create mode 100644 drivers/clk/at91/clk-programmable.c
> create mode 100644 drivers/clk/at91/clk-smd.c
> create mode 100644 drivers/clk/at91/clk-system.c
> create mode 100644 drivers/clk/at91/clk-usb.c
> create mode 100644 drivers/clk/at91/clk-utmi.c
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (78%)
>
^ permalink raw reply [flat|nested] 129+ messages in thread
* [PATCH v2 00/42] ARM: at91: move to common clk framework
@ 2013-07-27 4:41 ` boris brezillon
0 siblings, 0 replies; 129+ messages in thread
From: boris brezillon @ 2013-07-27 4:41 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This email is a feedback on the discussion I had with Jean-Christophe
last Wednesday.
As discussed with him, I will try to split this patch series in order to
1) limit the number of patches to review
2) limit the number of SoCs/boards to test
The new at91 clk support on non-dt boards was also discussed, and
Jean-Christophe thinks this is not mandatory (and should be dropped).
Does anyone see an interest in keeping this support in the next version
of the patch series ?
Here is how he though this patch series could be splitted:
1) at91 common clk implemenations + 1 SoC and the associated dt boards
2) 1 SoC and the associated dt boards
...)1 SoC and the associated dt boards
I tried to prepare the first new patch series by including only
at91sam9260/9g20 SoCs and boards but I failed. In fact I succeed but it
breaks multi-soc support (using dt) because we can't use both the common
clk framework and the at91 specific clk framework (they both provides
the same set of functions and structures definitions).
Should I break the multi-soc support to add at91 common clk ?
The only SoC that could be added without breaking multi-soc support is
the sama5 as it uses a different arm architecture (ARMv7) and thus
cannot be compiled in the same kernel as other at91 socs.
Should I choose the sama5 for the next patch series ?
Jean-Christophe, could you at least review the 11 first patches of this
series ?
I won't send any new version until I get some feedback from you on the
clk implementations and dt bindings...
Berst Regards,
Boris
Le 17/07/2013 15:34, Boris BREZILLON a ?crit :
> Hello,
>
> This patch series is a proposal to move at91 clock implementation
> to common clk framework.
>
> Most of the clock provided by the PMC (Power Management Controller) are
> implemented :
> - main clock (main oscillator)
> - pll clocks
> - master clock
> - programmable clocks
> - utmi clock
> - peripheral clocks
> - system clocks
>
> This implementation is compatible with device tree: the goal is
> to define the whole clock tree in the device tree (all currently
> available dt SoCs and boards are patched to support dt clocks).
> Please feel free to comment the dt bindinds.
>
> I removed the register_clocks function in SoC supporting dt boards only:
> - at91sam9x5 SoCs
> - at91sam9n12 SoC
> - sama5d3 SoCs
>
> This patch series is based on linux-next and has been tested on sama5d31ek
> board using device tree. It compiles for other SoCs and both with and without
> dt support, but it has not been tested.
>
> BTW could other people test it on other boards (I only have a kizbox and
> a sama5d31ek dev kit).
>
> Best Regards,
> Boris
>
> Changes since v1:
> - fix bugs in pll, programmable and system clock implementations
> (wrong bit position).
> - add usb clock configuration support (ohci and udc drivers +
> clk_lookup for non dt boards)
> - rework of the system clock interfaces (no need to define a parent clock,
> system clock is a gate with no rate info)
> - change system, peripheral and programmable clk dt bindings (1 master node
> and multiple child nodes each defining a system/peripheral or prog clock)
> - fix bugs in sama5 dt definition
>
> Boris BREZILLON (42):
> ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
> ARM: at91: add PMC main clock
> ARM: at91: add PMC pll clocks
> ARM: at91: add PMC master clock
> ARM: at91: add PMC system clocks
> ARM: at91: add PMC peripheral clocks
> ARM: at91: add PMC programmable clocks
> ARM: at91: add PMC utmi clock
> ARM: at91: add PMC usb clock
> ARM: at91: add PMC smd clock
> ARM: at91: add PMC clk device tree binding doc.
> ARM: at91: move to common clk framework
> ARM: at91: move at91rm9200 SoC to new at91 clk implem
> ARM: at91: move at91sam9260 SoC to new at91 clk implem
> ARM: at91: move at91sam9261 SoC to new at91 clk implem
> ARM: at91: move at91sam9263 SoC to new at91 clk implem
> ARM: at91: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91: move at91sam9rl SoC to new at91 clk implem
> ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91: move at91sam9 SoCs to new at91 clk implem
> ARM: at91: move sama5d3 SoCs to new at91 clk implem
> ARM: at91: move at91rm9200 boards to new at91 clk implem
> ARM: at91: move at91sam9 boards to new at91 clk implem
> ARM: at91: move pit timer to common clk framework
> USB: ohci-at91: add usb_clk for transition to common clk framework
> usb: gadget: at91_udc: add usb_clk for transition to common clk
> framework
> ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
> ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
> ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
> ARM: at91/dt: move sama5d3 SoCs to new at91 clk implem
> ARM: at91/dt: move sam9260/sam9g20 to new at91 clk implem
> ARM: at91/dt: move rm9200 boards to new at91 clk implem
> ARM: at91/dt: move sam9263 boards to new at91 clk implem
> ARM: at91/dt: move sam9g45 boards to new at91 clk implem
> ARM: at91/dt: move sam9n12 boards to new at91 clk implem
> ARM: at91/dt: move sam9x5 boards to new at91 clk implem
> ARM: at91/dt: move sama5d3 boards to new at91 clk implem
>
> .../devicetree/bindings/clock/at91-clock.txt | 262 ++++++
> arch/arm/boot/dts/animeo_ip.dts | 17 +-
> arch/arm/boot/dts/at91-ariag25.dts | 17 +-
> arch/arm/boot/dts/at91rm9200.dtsi | 231 +++++
> arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9260.dtsi | 236 +++++
> arch/arm/boot/dts/at91sam9263.dtsi | 237 +++++
> arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9g15.dtsi | 1 +
> arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
> arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
> arch/arm/boot/dts/at91sam9g35.dtsi | 2 +
> arch/arm/boot/dts/at91sam9g45.dtsi | 257 +++++
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9n12.dtsi | 251 +++++
> arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
> arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
> arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
> arch/arm/boot/dts/at91sam9x5.dtsi | 319 +++++--
> arch/arm/boot/dts/at91sam9x5_can.dtsi | 26 +
> arch/arm/boot/dts/at91sam9x5_isi.dtsi | 22 +
> arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 28 +
> arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 66 ++
> arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 54 ++
> arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 58 ++
> arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
> arch/arm/boot/dts/kizbox.dts | 5 +
> arch/arm/boot/dts/mpa1600.dts | 16 +-
> arch/arm/boot/dts/pm9g45.dts | 16 +-
> arch/arm/boot/dts/sama5d3.dtsi | 510 ++++++----
> arch/arm/boot/dts/sama5d31ek.dts | 4 +
> arch/arm/boot/dts/sama5d33ek.dts | 2 +
> arch/arm/boot/dts/sama5d34ek.dts | 4 +
> arch/arm/boot/dts/sama5d35ek.dts | 6 +
> arch/arm/boot/dts/sama5d3_can.dtsi | 71 ++
> arch/arm/boot/dts/sama5d3_emac.dtsi | 54 ++
> arch/arm/boot/dts/sama5d3_gmac.dtsi | 87 ++
> arch/arm/boot/dts/sama5d3_lcd.dtsi | 69 ++
> arch/arm/boot/dts/sama5d3_mci2.dtsi | 57 ++
> arch/arm/boot/dts/sama5d3_tcb1.dtsi | 38 +
> arch/arm/boot/dts/sama5d3_uart.dtsi | 46 +
> arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/tny_a9263.dts | 17 +-
> arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
> arch/arm/boot/dts/usb_a9263.dts | 17 +-
> arch/arm/mach-at91/Kconfig | 26 +
> arch/arm/mach-at91/Makefile | 2 +-
> arch/arm/mach-at91/at91rm9200.c | 568 +++++++-----
> arch/arm/mach-at91/at91sam9260.c | 689 +++++++++-----
> arch/arm/mach-at91/at91sam9261.c | 572 ++++++++----
> arch/arm/mach-at91/at91sam9263.c | 595 +++++++-----
> arch/arm/mach-at91/at91sam926x_time.c | 21 +-
> arch/arm/mach-at91/at91sam9g45.c | 704 ++++++++------
> arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
> arch/arm/mach-at91/at91sam9n12.c | 196 +---
> arch/arm/mach-at91/at91sam9rl.c | 502 ++++++----
> arch/arm/mach-at91/at91sam9x5.c | 293 +-----
> arch/arm/mach-at91/board-1arm.c | 12 +-
> arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
> arch/arm/mach-at91/board-cam60.c | 13 +-
> arch/arm/mach-at91/board-carmeva.c | 13 +-
> arch/arm/mach-at91/board-cpu9krea.c | 12 +-
> arch/arm/mach-at91/board-cpuat91.c | 12 +-
> arch/arm/mach-at91/board-csb337.c | 11 +-
> arch/arm/mach-at91/board-csb637.c | 11 +-
> arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
> arch/arm/mach-at91/board-dt-sam9.c | 9 +-
> arch/arm/mach-at91/board-dt-sama5.c | 9 +-
> arch/arm/mach-at91/board-eb9200.c | 11 +-
> arch/arm/mach-at91/board-ecbat91.c | 12 +-
> arch/arm/mach-at91/board-eco920.c | 13 +-
> arch/arm/mach-at91/board-flexibity.c | 12 +-
> arch/arm/mach-at91/board-foxg20.c | 12 +-
> arch/arm/mach-at91/board-gsia18s.c | 8 +-
> arch/arm/mach-at91/board-kafa.c | 12 +-
> arch/arm/mach-at91/board-kb9202.c | 12 +-
> arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
> arch/arm/mach-at91/board-picotux200.c | 11 +-
> arch/arm/mach-at91/board-qil-a9260.c | 11 +-
> arch/arm/mach-at91/board-rm9200ek.c | 11 +-
> arch/arm/mach-at91/board-rsi-ews.c | 12 +-
> arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
> arch/arm/mach-at91/board-sam9260ek.c | 11 +-
> arch/arm/mach-at91/board-sam9261ek.c | 15 +-
> arch/arm/mach-at91/board-sam9263ek.c | 11 +-
> arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
> arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
> arch/arm/mach-at91/board-sam9rlek.c | 11 +-
> arch/arm/mach-at91/board-snapper9260.c | 12 +-
> arch/arm/mach-at91/board-stamp9g20.c | 15 +-
> arch/arm/mach-at91/board-yl-9200.c | 12 +-
> arch/arm/mach-at91/clock.c | 977 --------------------
> arch/arm/mach-at91/clock.h | 49 -
> arch/arm/mach-at91/generic.h | 10 +-
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm_slowclock.S | 2 +-
> arch/arm/mach-at91/pmc.c | 58 ++
> arch/arm/mach-at91/sama5d3.c | 344 +------
> arch/arm/mach-at91/setup.c | 38 +-
> arch/arm/mach-at91/stamp9g20.h | 2 +-
> drivers/clk/Makefile | 1 +
> drivers/clk/at91/Makefile | 11 +
> drivers/clk/at91/clk-main.c | 106 +++
> drivers/clk/at91/clk-master.c | 317 +++++++
> drivers/clk/at91/clk-peripheral.c | 371 ++++++++
> drivers/clk/at91/clk-pll.c | 438 +++++++++
> drivers/clk/at91/clk-plldiv.c | 125 +++
> drivers/clk/at91/clk-programmable.c | 368 ++++++++
> drivers/clk/at91/clk-smd.c | 157 ++++
> drivers/clk/at91/clk-system.c | 184 ++++
> drivers/clk/at91/clk-usb.c | 303 ++++++
> drivers/clk/at91/clk-utmi.c | 114 +++
> drivers/usb/gadget/at91_udc.c | 31 +-
> drivers/usb/gadget/at91_udc.h | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
> drivers/usb/host/ohci-at91.c | 16 +-
> .../mach/at91_pmc.h => include/linux/clk/at91.h | 116 ++-
> 119 files changed, 8193 insertions(+), 3835 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
> create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
> create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
> create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
> delete mode 100644 arch/arm/mach-at91/clock.c
> delete mode 100644 arch/arm/mach-at91/clock.h
> create mode 100644 arch/arm/mach-at91/pmc.c
> create mode 100644 drivers/clk/at91/Makefile
> create mode 100644 drivers/clk/at91/clk-main.c
> create mode 100644 drivers/clk/at91/clk-master.c
> create mode 100644 drivers/clk/at91/clk-peripheral.c
> create mode 100644 drivers/clk/at91/clk-pll.c
> create mode 100644 drivers/clk/at91/clk-plldiv.c
> create mode 100644 drivers/clk/at91/clk-programmable.c
> create mode 100644 drivers/clk/at91/clk-smd.c
> create mode 100644 drivers/clk/at91/clk-system.c
> create mode 100644 drivers/clk/at91/clk-usb.c
> create mode 100644 drivers/clk/at91/clk-utmi.c
> rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (78%)
>
^ permalink raw reply [flat|nested] 129+ messages in thread