[PATCH 1/4] powerpc/85xx: Add SEC6.0 device tree

[PATCH 1/4] powerpc/85xx: Add SEC6.0 device tree

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Add device tree for SEC 6.0 used on C29x silicon.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
---
Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi | 58 +++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
new file mode 100644
index 0000000..eb99a46
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
@@ -0,0 +1,58 @@
+/*
+ * QorIQ Sec/Crypto 6.0 device tree stub
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+	compatible = "fsl,sec-v6.0", "fsl,sec-v5.2",
+		     "fsl,sec-v5.0", "fsl,sec-v4.4",
+		     "fsl,sec-v4.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
-- 
1.8.0

[PATCH 2/4] powerpc/85xx: Add silicon device tree for C293

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
 arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 +++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
 2 files changed, 256 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
new file mode 100644
index 0000000..bd20832
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
@@ -0,0 +1,193 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <19 2 0 0>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0 255>;
+	clock-frequency = <33333333>;
+	interrupts = <16 2 0 0>;
+
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <16 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+			>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+	bus-frequency = <0>;		// Filled out by uboot.
+
+	ecm-law@0 {
+		compatible = "fsl,ecm-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <12>;
+	};
+
+	ecm@1000 {
+		compatible = "fsl,c293-ecm", "fsl,ecm";
+		reg = <0x1000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+	memory-controller@2000 {
+		compatible = "fsl,c293-memory-controller";
+		reg = <0x2000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+	spi0: spi@7000 {
+		fsl,espi-num-chipselects = <1>;
+	};
+
+/include/ "pq3-gpio-0.dtsi"
+	L2: l2-cache-controller@20000 {
+		compatible = "fsl,c293-l2-cache-controller";
+		reg = <0x20000 0x1000>;
+		cache-line-size = <32>;	// 32 bytes
+		cache-size = <0x80000>; // L2,512K
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+	sdhc@2e000 {
+		compatible = "fsl,c293-esdhc", "fsl,esdhc";
+		sdhci,auto-cmd12;
+	};
+
+	crypto@80000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@80000 {
+		reg = <0x80000 0x20000>;
+		ranges = <0x0 0x80000 0x20000>;
+
+		jr@1000{
+			interrupts = <45 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <57 2 0 0>;
+		};
+	};
+
+	crypto@a0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0x0 0xa0000 0x20000>;
+
+		jr@1000{
+			interrupts = <49 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <50 2 0 0>;
+		};
+	};
+
+	crypto@c0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@c0000 {
+		reg = <0xc0000 0x20000>;
+		ranges = <0x0 0xc0000 0x20000>;
+
+		jr@1000{
+			interrupts = <55 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <56 2 0 0>;
+		};
+	};
+
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			reg = <0x10000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			reg = <0x11000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+	global-utilities@e0000 {
+		compatible = "fsl,c293-guts";
+		reg = <0xe0000 0x1000>;
+		fsl,has-rstcr;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
new file mode 100644
index 0000000..065049d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,C293";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e500v2@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.8.0

[PATCH 3/4] powerpc/85xx: Add C293PCIE board support

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

C293PCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
---
Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
 arch/powerpc/boot/dts/c293pcie.dts     | 251 +++++++++++++++++++++++++++++++++
 arch/powerpc/platforms/85xx/Kconfig    |   7 +
 arch/powerpc/platforms/85xx/Makefile   |   1 +
 arch/powerpc/platforms/85xx/c293pcie.c |  82 +++++++++++
 4 files changed, 341 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/c293pcie.dts
 create mode 100644 arch/powerpc/platforms/85xx/c293pcie.c

diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
new file mode 100644
index 0000000..f2f6d76
--- /dev/null
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -0,0 +1,251 @@
+/*
+ * C293 PCIE Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/c293si-pre.dtsi"
+
+/ {
+	model = "fsl,C293PCIE";
+	compatible = "fsl,C293PCIE";
+
+	memory {
+		device_type = "memory";
+	};
+
+	ifc: ifc@fffe1e000 {
+		reg = <0xf 0xffe1e000 0 0x2000>;
+		ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+			  0x2 0x0 0xf 0xffdf0000 0x00010000>;
+
+	};
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&ifc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 1MB for DTB Image */
+			reg = <0x0 0x00100000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@100000 {
+			/* 8 MB for Linux Kernel Image */
+			reg = <0x00100000 0x00800000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@900000 {
+			/* 33MB for rootfs */
+			reg = <0x00900000 0x02100000>;
+			label = "NOR Rootfs Image";
+		};
+
+		partition@2a00000 {
+			/* 20MB for JFFS2 based Root file System */
+			reg = <0x02a00000 0x01400000>;
+			label = "NOR JFFS2 Root File System";
+		};
+
+		partition@3e00000 {
+			/* 1MB for blob encrypted key */
+			reg = <0x03e00000 0x00100000>;
+			label = "NOR blob encrypted key";
+		};
+
+		partition@3f00000 {
+			/* 512KB for u-boot Bootloader Image and evn */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,ifc-nand";
+		reg = <0x1 0x0 0x10000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 4MB for Linux Kernel Image */
+			reg = <0x00200000 0x00400000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@600000 {
+			/* 4MB for Compressed Root file System Image */
+			reg = <0x00600000 0x00400000>;
+			label = "NAND Compressed RFS Image";
+		};
+
+		partition@a00000 {
+			/* 15MB for JFFS2 based Root file System */
+			reg = <0x00a00000 0x00f00000>;
+			label = "NAND JFFS2 Root File System";
+		};
+
+		partition@1900000 {
+			/* 7MB for User Area */
+			reg = <0x01900000 0x00700000>;
+			label = "NAND User area";
+		};
+	};
+
+	cpld@2,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,c293pcie-cpld";
+		reg = <0x2 0x0 0x0000020>;
+		bank-width = <1>;
+		device-width = <1>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		eeprom@50 {
+			compatible = "st,24c1024";
+			reg = <0x50>;
+		};
+
+		adt7461@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+
+			partition@0 {
+				/* 1MB for u-boot Bootloader Image */
+				/* 1MB for Environment */
+				reg = <0x0 0x00100000>;
+				label = "SPI Flash U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 512KB for DTB Image */
+				reg = <0x00100000 0x00080000>;
+				label = "SPI Flash DTB Image";
+			};
+
+			partition@180000 {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00180000 0x00400000>;
+				label = "SPI Flash Linux Kernel Image";
+			};
+
+			partition@580000 {
+				/* 4MB for Compressed RFS Image */
+				reg = <0x00580000 0x00400000>;
+				label = "SPI Flash Compressed RFSImage";
+			};
+
+			partition@980000 {
+				/* 6.5MB for JFFS2 based RFS */
+				reg = <0x00980000 0x00680000>;
+				label = "SPI Flash JFFS2 RFS";
+			};
+		};
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <2 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x2>;
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
+/include/ "fsl/c293si-post.dtsi"
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a0dcd57..df26b21 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -32,6 +32,13 @@ config BSC9131_RDB
 	  StarCore SC3850 DSP
 	  Manufacturer : Freescale Semiconductor, Inc
 
+config C293_PCIE
+	  bool "Freescale C293PCIE"
+	  select DEFAULT_UIMAGE
+	  select SWIOTLB
+	  help
+	  This option enables support for the C293PCIE board
+
 config MPC8540_ADS
 	bool "Freescale MPC8540 ADS"
 	select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 07d0dbb..55b32cc 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_C293_PCIE)   += c293pcie.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
new file mode 100644
index 0000000..75dda12
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -0,0 +1,82 @@
+/*
+ * C293PCIE Board Setup
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init c293_pcie_pic_init(void)
+{
+	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+
+	mpic_init(mpic);
+}
+
+
+/*
+ * Setup the architecture
+ */
+static void __init c293_pcie_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("c293_pcie_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "C293 PCIE board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init c293_pcie_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+
+	if (of_flat_dt_is_compatible(root, "fsl,C293PCIE"))
+		return 1;
+	return 0;
+}
+
+define_machine(c293_pcie) {
+	.name			= "C293 PCIE",
+	.probe			= c293_pcie_probe,
+	.setup_arch		= c293_pcie_setup_arch,
+	.init_IRQ		= c293_pcie_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
-- 
1.8.0

[PATCH 4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
---
Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
 arch/powerpc/configs/mpc85xx_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cf815e8..ddc33a2 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -28,6 +28,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
-- 
1.8.0

Re: [1/4] powerpc/85xx: Add SEC6.0 device tree

[Scott Wood]

On Thu, Apr 25, 2013 at 09:54:14AM +0800, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> Add device tree for SEC 6.0 used on C29x silicon.
> 
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Singed-off-by: Po Liu <Po.Liu@freescale.com>

I've heard of patches being flamed, but here we want signing, not
singeing. :-)

Don't forget that you can use the -s option to have git add the signoff
for you.

> ---
> Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git

This URL is not accessible outside Freescale, so don't reference it when
posting patches publicly.

If your patch is against the latest upstream code, you don't need to say
anything special about that.  You only need to make a note when it's
against some other yet-to-be-merged tree or patch.

> +	compatible = "fsl,sec-v6.0", "fsl,sec-v5.2",
> +		     "fsl,sec-v5.0", "fsl,sec-v4.4",
> +		     "fsl,sec-v4.0";
> +	fsl,sec-era = <6>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	jr@1000 {
> +		compatible = "fsl,sec-v6.0-job-ring",
> +			     "fsl,sec-v5.2-job-ring",
> +			     "fsl,sec-v5.0-job-ring",
> +			     "fsl,sec-v4.4-job-ring",
> +			     "fsl,sec-v4.0-job-ring";
> +		reg	   = <0x1000 0x1000>;
> +	};
> +
> +	jr@2000 {
> +		compatible = "fsl,sec-v6.0-job-ring",
> +			     "fsl,sec-v5.2-job-ring",
> +			     "fsl,sec-v5.0-job-ring",
> +			     "fsl,sec-v4.4-job-ring",
> +			     "fsl,sec-v4.0-job-ring";
> +		reg	   = <0x2000 0x1000>;
> +	};

You claim compatibility with a bunch of prior SECs, but sec-v5.2 has four
job rings and an rtic node.  Likewise for the previous compatibles
listed.  This has two job rings and no rtic.

Can you point to where in the SEC v4.0 binding (I don't see a binding for
the subsequent versions), it says that these are optional?

-Scott

Re: [3/4] powerpc/85xx: Add C293PCIE board support

[Scott Wood]

On Thu, Apr 25, 2013 at 09:54:16AM +0800, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> C293PCIE board is a series of Freescale PCIe add-in cards to perform
> as public key crypto accelerator or secure key management module.
> 
>  - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
>  - 512MB soldered DDR3 32bit memory
>  - CPLD System Logic
>  - 64MB x16 NOR flash and 4GB x8 NAND flash
>  - 16MB SPI flash
> 
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Singed-off-by: Po Liu <Po.Liu@freescale.com>

Signed

> +		partition@900000 {
> +			/* 33MB for rootfs */
> +			reg = <0x00900000 0x02100000>;
> +			label = "NOR Rootfs Image";
> +		};
> +
> +		partition@2a00000 {
> +			/* 20MB for JFFS2 based Root file System */
> +			reg = <0x02a00000 0x01400000>;
> +			label = "NOR JFFS2 Root File System";
> +		};

Don't specify JFFS2.  Combine these two partitions into one.

> +		partition@600000 {
> +			/* 4MB for Compressed Root file System Image */
> +			reg = <0x00600000 0x00400000>;
> +			label = "NAND Compressed RFS Image";
> +		};
> +
> +		partition@a00000 {
> +			/* 15MB for JFFS2 based Root file System */
> +			reg = <0x00a00000 0x00f00000>;
> +			label = "NAND JFFS2 Root File System";
> +		};

Likewise.

> +		partition@1900000 {
> +			/* 7MB for User Area */
> +			reg = <0x01900000 0x00700000>;
> +			label = "NAND User area";
> +		};

Above you say there's 4 GiB of NAND, but here you define partitions that
only cover 32 MiB.

> +	};
> +
> +	cpld@2,0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "fsl,c293pcie-cpld";
> +		reg = <0x2 0x0 0x0000020>;
> +		bank-width = <1>;
> +		device-width = <1>;
> +	};

What do bank-width and device-width mean here?

Why all the leading zeroes in 0x0000020?

> +			partition@580000 {
> +				/* 4MB for Compressed RFS Image */
> +				reg = <0x00580000 0x00400000>;
> +				label = "SPI Flash Compressed RFSImage";
> +			};
> +
> +			partition@980000 {
> +				/* 6.5MB for JFFS2 based RFS */
> +				reg = <0x00980000 0x00680000>;
> +				label = "SPI Flash JFFS2 RFS";
> +			};

Again, merge these two and don't specify JFFS2.

> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index a0dcd57..df26b21 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -32,6 +32,13 @@ config BSC9131_RDB
>  	  StarCore SC3850 DSP
>  	  Manufacturer : Freescale Semiconductor, Inc
>  
> +config C293_PCIE
> +	  bool "Freescale C293PCIE"
> +	  select DEFAULT_UIMAGE
> +	  select SWIOTLB
> +	  help
> +	  This option enables support for the C293PCIE board

Why do you need SWIOTLB if the board has 512 MiB soldered RAM?

> diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
> new file mode 100644
> index 0000000..75dda12
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/c293pcie.c
> @@ -0,0 +1,82 @@
> +/*
> + * C293PCIE Board Setup
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +
> +#include "mpc85xx.h"

Are you sure you need all of these?  I don't see any delays, for example.

-Scott

Re: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE

[Scott Wood]

On Thu, Apr 25, 2013 at 09:54:17AM +0800, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> ---
> Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
>  arch/powerpc/configs/mpc85xx_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
> index cf815e8..ddc33a2 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -28,6 +28,7 @@ CONFIG_MPC85xx_MDS=y
>  CONFIG_MPC8536_DS=y
>  CONFIG_MPC85xx_DS=y
>  CONFIG_MPC85xx_RDB=y
> +CONFIG_C293_PCIE=y
>  CONFIG_P1010_RDB=y
>  CONFIG_P1022_DS=y
>  CONFIG_P1022_RDK=y

Please just merge this in with the patch that adds CONFIG_C293_PCIE
support, when you respin that patch.

-Scott

Re: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE

[Scott Wood]

On Thu, Apr 25, 2013 at 09:54:17AM +0800, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> 
> ---
> Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
>  arch/powerpc/configs/mpc85xx_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
> index cf815e8..ddc33a2 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -28,6 +28,7 @@ CONFIG_MPC85xx_MDS=y
>  CONFIG_MPC8536_DS=y
>  CONFIG_MPC85xx_DS=y
>  CONFIG_MPC85xx_RDB=y
> +CONFIG_C293_PCIE=y
>  CONFIG_P1010_RDB=y
>  CONFIG_P1022_DS=y
>  CONFIG_P1022_RDK=y

Also, why only mpc85xx_defconfig and mpc85xx_smp_defconfig?  Just because
this board isn't SMP doesn't mean it can't be supported by an SMP kernel.

-Scott

RE: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE

[Liu Po-B43644]

-----Original Message-----
From: Wood Scott-B07421=20
Sent: Tuesday, July 23, 2013 7:00 AM
To: Liu Po-B43644
Cc: linuxppc-dev@ozlabs.org; Hu Mingkai-B21284
Subject: Re: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE

On Thu, Apr 25, 2013 at 09:54:17AM +0800, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
>=20
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
>=20
> ---
> Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
>  arch/powerpc/configs/mpc85xx_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>=20
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig=20
> b/arch/powerpc/configs/mpc85xx_defconfig
> index cf815e8..ddc33a2 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -28,6 +28,7 @@ CONFIG_MPC85xx_MDS=3Dy  CONFIG_MPC8536_DS=3Dy =20
> CONFIG_MPC85xx_DS=3Dy  CONFIG_MPC85xx_RDB=3Dy
> +CONFIG_C293_PCIE=3Dy
>  CONFIG_P1010_RDB=3Dy
>  CONFIG_P1022_DS=3Dy
>  CONFIG_P1022_RDK=3Dy

Also, why only mpc85xx_defconfig and mpc85xx_smp_defconfig?  Just because t=
his board isn't SMP doesn't mean it can't be supported by an SMP kernel.
Action: I will add configure to  mpc85xx_smp_defconfig. And merge it to Add=
-C293PCIE-board-support.patch.
-Scott

RE: [3/4] powerpc/85xx: Add C293PCIE board support

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Tuesday, July 23, 2013 6:59 AM
>  To: Liu Po-B43644
>  Cc: linuxppc-dev@ozlabs.org; Hu Mingkai-B21284
>  Subject: Re: [3/4] powerpc/85xx: Add C293PCIE board support
> =20
>  On Thu, Apr 25, 2013 at 09:54:16AM +0800, Po Liu wrote:
>  > From: Mingkai Hu <Mingkai.Hu@freescale.com>
>  >
>  > C293PCIE board is a series of Freescale PCIe add-in cards to perform
>  > as public key crypto accelerator or secure key management module.
>  >
>  >  - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
>  >  - 512MB soldered DDR3 32bit memory
>  >  - CPLD System Logic
>  >  - 64MB x16 NOR flash and 4GB x8 NAND flash
>  >  - 16MB SPI flash
>  >
>  > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
>  > Singed-off-by: Po Liu <Po.Liu@freescale.com>
> =20
>  Signed
> =20
>  > +		partition@900000 {
>  > +			/* 33MB for rootfs */
>  > +			reg =3D <0x00900000 0x02100000>;
>  > +			label =3D "NOR Rootfs Image";
>  > +		};
>  > +
>  > +		partition@2a00000 {
>  > +			/* 20MB for JFFS2 based Root file System */
>  > +			reg =3D <0x02a00000 0x01400000>;
>  > +			label =3D "NOR JFFS2 Root File System";
>  > +		};
> =20
>  Don't specify JFFS2.  Combine these two partitions into one.
Ok, I'll merge up two partition.
> =20
>  > +		partition@600000 {
>  > +			/* 4MB for Compressed Root file System Image */
>  > +			reg =3D <0x00600000 0x00400000>;
>  > +			label =3D "NAND Compressed RFS Image";
>  > +		};
>  > +
>  > +		partition@a00000 {
>  > +			/* 15MB for JFFS2 based Root file System */
>  > +			reg =3D <0x00a00000 0x00f00000>;
>  > +			label =3D "NAND JFFS2 Root File System";
>  > +		};
> =20
>  Likewise.
> =20
>  > +		partition@1900000 {
>  > +			/* 7MB for User Area */
>  > +			reg =3D <0x01900000 0x00700000>;
>  > +			label =3D "NAND User area";
>  > +		};
> =20
>  Above you say there's 4 GiB of NAND, but here you define partitions that
>  only cover 32 MiB.
Can I set one partion include all other space(4GB- 32MB) with label name "O=
thers"?
> =20
>  > +	};
>  > +
>  > +	cpld@2,0 {
>  > +		#address-cells =3D <1>;
>  > +		#size-cells =3D <1>;
>  > +		compatible =3D "fsl,c293pcie-cpld";
>  > +		reg =3D <0x2 0x0 0x0000020>;
>  > +		bank-width =3D <1>;
>  > +		device-width =3D <1>;
>  > +	};
> =20
>  What do bank-width and device-width mean here?
I will remove these two lines? I thought I copy from other platform.
> =20
>  Why all the leading zeroes in 0x0000020?
I'll change to 0x20 from 0x0000020.
> =20
>  > +			partition@580000 {
>  > +				/* 4MB for Compressed RFS Image */
>  > +				reg =3D <0x00580000 0x00400000>;
>  > +				label =3D "SPI Flash Compressed RFSImage";
>  > +			};
>  > +
>  > +			partition@980000 {
>  > +				/* 6.5MB for JFFS2 based RFS */
>  > +				reg =3D <0x00980000 0x00680000>;
>  > +				label =3D "SPI Flash JFFS2 RFS";
>  > +			};
> =20
>  Again, merge these two and don't specify JFFS2.
Ok, thanks
> =20
>  > diff --git a/arch/powerpc/platforms/85xx/Kconfig
>  > b/arch/powerpc/platforms/85xx/Kconfig
>  > index a0dcd57..df26b21 100644
>  > --- a/arch/powerpc/platforms/85xx/Kconfig
>  > +++ b/arch/powerpc/platforms/85xx/Kconfig
>  > @@ -32,6 +32,13 @@ config BSC9131_RDB
>  >  	  StarCore SC3850 DSP
>  >  	  Manufacturer : Freescale Semiconductor, Inc
>  >
>  > +config C293_PCIE
>  > +	  bool "Freescale C293PCIE"
>  > +	  select DEFAULT_UIMAGE
>  > +	  select SWIOTLB
>  > +	  help
>  > +	  This option enables support for the C293PCIE board
> =20
>  Why do you need SWIOTLB if the board has 512 MiB soldered RAM?
I'll remove it.
> =20
>  > diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
>  > b/arch/powerpc/platforms/85xx/c293pcie.c
>  > new file mode 100644
>  > index 0000000..75dda12
>  > --- /dev/null
>  > +++ b/arch/powerpc/platforms/85xx/c293pcie.c
>  > @@ -0,0 +1,82 @@
>  > +/*
>  > + * C293PCIE Board Setup
>  > + *
>  > + * Copyright 2013 Freescale Semiconductor Inc.
>  > + *
>  > + * This program is free software; you can redistribute  it and/or
>  > +modify it
>  > + * under  the terms of  the GNU General  Public License as published
>  > +by the
>  > + * Free Software Foundation;  either version 2 of the  License, or
>  > +(at your
>  > + * option) any later version.
>  > + */
>  > +
>  > +#include <linux/stddef.h>
>  > +#include <linux/kernel.h>
>  > +#include <linux/pci.h>
>  > +#include <linux/delay.h>
>  > +#include <linux/interrupt.h>
>  > +#include <linux/of_platform.h>
>  > +
>  > +#include <asm/time.h>
>  > +#include <asm/machdep.h>
>  > +#include <asm/pci-bridge.h>
>  > +#include <mm/mmu_decl.h>
>  > +#include <asm/prom.h>
>  > +#include <asm/udbg.h>
>  > +#include <asm/mpic.h>
>  > +
>  > +#include <sysdev/fsl_soc.h>
>  > +#include <sysdev/fsl_pci.h>
>  > +
>  > +#include "mpc85xx.h"
> =20
>  Are you sure you need all of these?  I don't see any delays, for example=
.
Thanks, I'll test and remove redundant includes.
> =20
>  -Scott

RE: [1/4] powerpc/85xx: Add SEC6.0 device tree

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Tuesday, July 23, 2013 6:41 AM
>  To: Liu Po-B43644
>  Cc: linuxppc-dev@ozlabs.org; Hu Mingkai-B21284
>  Subject: Re: [1/4] powerpc/85xx: Add SEC6.0 device tree
> =20
>  On Thu, Apr 25, 2013 at 09:54:14AM +0800, Po Liu wrote:
>  > From: Mingkai Hu <Mingkai.Hu@freescale.com>
>  >
>  > Add device tree for SEC 6.0 used on C29x silicon.
>  >
>  > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
>  > Singed-off-by: Po Liu <Po.Liu@freescale.com>
> =20
>  I've heard of patches being flamed, but here we want signing, not
>  singeing. :-)
> =20
>  Don't forget that you can use the -s option to have git add the signoff
>  for you.
> =20
>  > ---
>  > Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
> =20
>  This URL is not accessible outside Freescale, so don't reference it when
>  posting patches publicly.
> =20
>  If your patch is against the latest upstream code, you don't need to say
>  anything special about that.  You only need to make a note when it's
>  against some other yet-to-be-merged tree or patch.
> =20
>  > +	compatible =3D "fsl,sec-v6.0", "fsl,sec-v5.2",
>  > +		     "fsl,sec-v5.0", "fsl,sec-v4.4",
>  > +		     "fsl,sec-v4.0";
>  > +	fsl,sec-era =3D <6>;
>  > +	#address-cells =3D <1>;
>  > +	#size-cells =3D <1>;
>  > +
>  > +	jr@1000 {
>  > +		compatible =3D "fsl,sec-v6.0-job-ring",
>  > +			     "fsl,sec-v5.2-job-ring",
>  > +			     "fsl,sec-v5.0-job-ring",
>  > +			     "fsl,sec-v4.4-job-ring",
>  > +			     "fsl,sec-v4.0-job-ring";
>  > +		reg	   =3D <0x1000 0x1000>;
>  > +	};
>  > +
>  > +	jr@2000 {
>  > +		compatible =3D "fsl,sec-v6.0-job-ring",
>  > +			     "fsl,sec-v5.2-job-ring",
>  > +			     "fsl,sec-v5.0-job-ring",
>  > +			     "fsl,sec-v4.4-job-ring",
>  > +			     "fsl,sec-v4.0-job-ring";
>  > +		reg	   =3D <0x2000 0x1000>;
>  > +	};
> =20
>  You claim compatibility with a bunch of prior SECs, but sec-v5.2 has fou=
r
>  job rings and an rtic node.  Likewise for the previous compatibles liste=
d.
>  This has two job rings and no rtic.
So, shall I remove "fsl,sec-v5.2","fsl,sec-v5.0", "fsl,sec-v4.4", "fsl,sec-=
v4.0" since all other SEC with 4 job rings? and only leave "fsl,sec-v6.0"?
> =20
>  Can you point to where in the SEC v4.0 binding (I don't see a binding fo=
r
>  the subsequent versions), it says that these are optional?
I found SEC V4.0 in file qoriq-sec4.0-0.dtsi. If "fsl,sec-v4.0" not in the =
compatible list, it is no use in this compatible list. But seems keep the "=
fsl,sec-v4.0-job-ring" job ring compatible is ok. Is that what you were ask=
?
> =20
>  -Scott

Re: [3/4] powerpc/85xx: Add C293PCIE board support

[Scott Wood]

On 07/23/2013 02:47:18 AM, Liu Po-B43644 wrote:
> >  > +		partition@1900000 {
> >  > +			/* 7MB for User Area */
> >  > +			reg =3D <0x01900000 0x00700000>;
> >  > +			label =3D "NAND User area";
> >  > +		};
> >
> >  Above you say there's 4 GiB of NAND, but here you define =20
> partitions that
> >  only cover 32 MiB.
> Can I set one partion include all other space(4GB- 32MB) with label =20
> name "Others"?

Are you sure you don't want to leave more room for the RFS?  And what =20
is the difference between "user area" and "others"?

> >  > diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
> >  > b/arch/powerpc/platforms/85xx/c293pcie.c
> >  > new file mode 100644
> >  > index 0000000..75dda12
> >  > --- /dev/null
> >  > +++ b/arch/powerpc/platforms/85xx/c293pcie.c
> >  > @@ -0,0 +1,82 @@
> >  > +/*
> >  > + * C293PCIE Board Setup
> >  > + *
> >  > + * Copyright 2013 Freescale Semiconductor Inc.
> >  > + *
> >  > + * This program is free software; you can redistribute  it =20
> and/or
> >  > +modify it
> >  > + * under  the terms of  the GNU General  Public License as =20
> published
> >  > +by the
> >  > + * Free Software Foundation;  either version 2 of the  License, =20
> or
> >  > +(at your
> >  > + * option) any later version.
> >  > + */
> >  > +
> >  > +#include <linux/stddef.h>
> >  > +#include <linux/kernel.h>
> >  > +#include <linux/pci.h>
> >  > +#include <linux/delay.h>
> >  > +#include <linux/interrupt.h>
> >  > +#include <linux/of_platform.h>
> >  > +
> >  > +#include <asm/time.h>
> >  > +#include <asm/machdep.h>
> >  > +#include <asm/pci-bridge.h>
> >  > +#include <mm/mmu_decl.h>
> >  > +#include <asm/prom.h>
> >  > +#include <asm/udbg.h>
> >  > +#include <asm/mpic.h>
> >  > +
> >  > +#include <sysdev/fsl_soc.h>
> >  > +#include <sysdev/fsl_pci.h>
> >  > +
> >  > +#include "mpc85xx.h"
> >
> >  Are you sure you need all of these?  I don't see any delays, for =20
> example.
> Thanks, I'll test and remove redundant includes.

Don't base it purely on testing -- you don't want to rely on =20
accidentally picking up a needed include from some other include (which =20
could change down the road).  Base it on whether this file uses =20
something declared by the header in question.

-Scott=

Re: [1/4] powerpc/85xx: Add SEC6.0 device tree

[Scott Wood]

On 07/23/2013 03:01:17 AM, Liu Po-B43644 wrote:
>=20
> >  -----Original Message-----
> >  From: Wood Scott-B07421
> >  Sent: Tuesday, July 23, 2013 6:41 AM
> >  To: Liu Po-B43644
> >  Cc: linuxppc-dev@ozlabs.org; Hu Mingkai-B21284
> >  Subject: Re: [1/4] powerpc/85xx: Add SEC6.0 device tree
> >
> >  On Thu, Apr 25, 2013 at 09:54:14AM +0800, Po Liu wrote:
> >  > From: Mingkai Hu <Mingkai.Hu@freescale.com>
> >  >
> >  > Add device tree for SEC 6.0 used on C29x silicon.
> >  >
> >  > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> >  > Singed-off-by: Po Liu <Po.Liu@freescale.com>
> >
> >  I've heard of patches being flamed, but here we want signing, not
> >  singeing. :-)
> >
> >  Don't forget that you can use the -s option to have git add the =20
> signoff
> >  for you.
> >
> >  > ---
> >  > Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
> >
> >  This URL is not accessible outside Freescale, so don't reference =20
> it when
> >  posting patches publicly.
> >
> >  If your patch is against the latest upstream code, you don't need =20
> to say
> >  anything special about that.  You only need to make a note when =20
> it's
> >  against some other yet-to-be-merged tree or patch.
> >
> >  > +	compatible =3D "fsl,sec-v6.0", "fsl,sec-v5.2",
> >  > +		     "fsl,sec-v5.0", "fsl,sec-v4.4",
> >  > +		     "fsl,sec-v4.0";
> >  > +	fsl,sec-era =3D <6>;
> >  > +	#address-cells =3D <1>;
> >  > +	#size-cells =3D <1>;
> >  > +
> >  > +	jr@1000 {
> >  > +		compatible =3D "fsl,sec-v6.0-job-ring",
> >  > +			     "fsl,sec-v5.2-job-ring",
> >  > +			     "fsl,sec-v5.0-job-ring",
> >  > +			     "fsl,sec-v4.4-job-ring",
> >  > +			     "fsl,sec-v4.0-job-ring";
> >  > +		reg	   =3D <0x1000 0x1000>;
> >  > +	};
> >  > +
> >  > +	jr@2000 {
> >  > +		compatible =3D "fsl,sec-v6.0-job-ring",
> >  > +			     "fsl,sec-v5.2-job-ring",
> >  > +			     "fsl,sec-v5.0-job-ring",
> >  > +			     "fsl,sec-v4.4-job-ring",
> >  > +			     "fsl,sec-v4.0-job-ring";
> >  > +		reg	   =3D <0x2000 0x1000>;
> >  > +	};
> >
> >  You claim compatibility with a bunch of prior SECs, but sec-v5.2 =20
> has four
> >  job rings and an rtic node.  Likewise for the previous compatibles =20
> listed.
> >  This has two job rings and no rtic.
> So, shall I remove "fsl,sec-v5.2","fsl,sec-v5.0", "fsl,sec-v4.4", =20
> "fsl,sec-v4.0" since all other SEC with 4 job rings? and only leave =20
> "fsl,sec-v6.0"?

Yes, I think so.

> >  Can you point to where in the SEC v4.0 binding (I don't see a =20
> binding for
> >  the subsequent versions), it says that these are optional?
> I found SEC V4.0 in file qoriq-sec4.0-0.dtsi. If "fsl,sec-v4.0" not =20
> in the compatible list, it is no use in this compatible list. But =20
> seems keep the "fsl,sec-v4.0-job-ring" job ring compatible is ok. Is =20
> that what you were ask?

No, I was talking about binding documents:
Documentation/devicetree/bindings/crypto/

-Scott=

[PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Add device tree for SEC 6.0 used on C29x silicon.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the compatible sec v4.0/v4.4/v5.0;
	- Add the device tree binding file fsl-sec6.txt;

 .../devicetree/bindings/crypto/fsl-sec6.txt        | 162 +++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi      |  56 +++++++
 2 files changed, 218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec6.txt
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
new file mode 100644
index 0000000..f6d2a69
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
@@ -0,0 +1,162 @@
+SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale powerpc chip C29X is embeded with SEC 6. 
+SEC 6 device tree binding include:
+   -SEC 6 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 6 Node
+
+Description
+
+    Node defines the base address of the SEC 6 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 6 block.
+    For example, In C293, we could see three SEC 6 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0"
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 6 configuration registers.
+          registers
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 6.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+
+EXAMPLE
+	crypto@a0000 {
+		compatible = "fsl,sec-v6.0";
+		fsl,sec-era = <6>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xa0000 0x20000>;
+		ranges = <0 0xa0000 0x20000>;
+	};
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 6 
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0-job-ring", if it is
+      back compatible with old version, better add them all.
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+          the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <49 2 0 0>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may embeded with more than one SEC 6, we abstract
+all the same properties into one file qoriq-sec6.0-0.dtsi. Each chip
+want to binding the node could simply include it in its own device
+node tree. Below is full example in C293PCIE:
+
+In qoriq-sec6.0-0.dtsi:
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
+
+In the C293 device tree, we add the include of public property:
+
+crypto@a0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0x0 0xa0000 0x20000>;
+
+		jr@1000{
+			interrupts = <49 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <50 2 0 0>;
+		};
+	};
+
+
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
new file mode 100644
index 0000000..f75b4f820
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
@@ -0,0 +1,56 @@
+/*
+ * QorIQ Sec/Crypto 6.0 device tree stub
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
-- 
1.8.0

[PATCH v2 2/3] powerpc/85xx: Add silicon device tree for C293

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- None

 arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 +++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
 2 files changed, 256 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
new file mode 100644
index 0000000..bd20832
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
@@ -0,0 +1,193 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <19 2 0 0>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0 255>;
+	clock-frequency = <33333333>;
+	interrupts = <16 2 0 0>;
+
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <16 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+			>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+	bus-frequency = <0>;		// Filled out by uboot.
+
+	ecm-law@0 {
+		compatible = "fsl,ecm-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <12>;
+	};
+
+	ecm@1000 {
+		compatible = "fsl,c293-ecm", "fsl,ecm";
+		reg = <0x1000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+	memory-controller@2000 {
+		compatible = "fsl,c293-memory-controller";
+		reg = <0x2000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+	spi0: spi@7000 {
+		fsl,espi-num-chipselects = <1>;
+	};
+
+/include/ "pq3-gpio-0.dtsi"
+	L2: l2-cache-controller@20000 {
+		compatible = "fsl,c293-l2-cache-controller";
+		reg = <0x20000 0x1000>;
+		cache-line-size = <32>;	// 32 bytes
+		cache-size = <0x80000>; // L2,512K
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+	sdhc@2e000 {
+		compatible = "fsl,c293-esdhc", "fsl,esdhc";
+		sdhci,auto-cmd12;
+	};
+
+	crypto@80000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@80000 {
+		reg = <0x80000 0x20000>;
+		ranges = <0x0 0x80000 0x20000>;
+
+		jr@1000{
+			interrupts = <45 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <57 2 0 0>;
+		};
+	};
+
+	crypto@a0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0x0 0xa0000 0x20000>;
+
+		jr@1000{
+			interrupts = <49 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <50 2 0 0>;
+		};
+	};
+
+	crypto@c0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@c0000 {
+		reg = <0xc0000 0x20000>;
+		ranges = <0x0 0xc0000 0x20000>;
+
+		jr@1000{
+			interrupts = <55 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <56 2 0 0>;
+		};
+	};
+
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			reg = <0x10000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			reg = <0x11000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+	global-utilities@e0000 {
+		compatible = "fsl,c293-guts";
+		reg = <0xe0000 0x1000>;
+		fsl,has-rstcr;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
new file mode 100644
index 0000000..065049d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,C293";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e500v2@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.8.0

[PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

C293PCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the JFFS2 partitions in NOR/NAND/SPI flash;
	- Implement the NAND partitions;
	- Remove the no use descriptions for cpld node;
	- Add mpc85xx_smp_defconfig and mpc85xx_defconfig for C293;
	- Remove the no use includes in c293pcie.c


 arch/powerpc/boot/dts/c293pcie.dts         | 243 +++++++++++++++++++++++++++++
 arch/powerpc/configs/mpc85xx_defconfig     |   1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig |   1 +
 arch/powerpc/platforms/85xx/Kconfig        |   6 +
 arch/powerpc/platforms/85xx/Makefile       |   1 +
 arch/powerpc/platforms/85xx/c293pcie.c     |  75 +++++++++
 6 files changed, 327 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/c293pcie.dts
 create mode 100644 arch/powerpc/platforms/85xx/c293pcie.c

diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
new file mode 100644
index 0000000..dc91c47
--- /dev/null
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -0,0 +1,243 @@
+/*
+ * C293 PCIE Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/c293si-pre.dtsi"
+
+/ {
+	model = "fsl,C293PCIE";
+	compatible = "fsl,C293PCIE";
+
+	memory {
+		device_type = "memory";
+	};
+
+	ifc: ifc@fffe1e000 {
+		reg = <0xf 0xffe1e000 0 0x2000>;
+		ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+			  0x2 0x0 0xf 0xffdf0000 0x00010000>;
+
+	};
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&ifc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 1MB for DTB Image */
+			reg = <0x0 0x00100000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@100000 {
+			/* 8 MB for Linux Kernel Image */
+			reg = <0x00100000 0x00800000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@900000 {
+			/* 53MB for rootfs */
+			reg = <0x00900000 0x03500000>;
+			label = "NOR Rootfs Image";
+		};
+
+		partition@3e00000 {
+			/* 1MB for blob encrypted key */
+			reg = <0x03e00000 0x00100000>;
+			label = "NOR blob encrypted key";
+		};
+
+		partition@3f00000 {
+			/* 512KB for u-boot Bootloader Image and evn */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,ifc-nand";
+		reg = <0x1 0x0 0x10000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 4MB for Linux Kernel Image */
+			reg = <0x00200000 0x00400000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@600000 {
+			/* 19MB for Compressed Root file System Image */
+			reg = <0x00600000 0x01300000>;
+			label = "NAND Compressed RFS Image";
+		};
+
+		partition@1900000 {
+			/* 7MB for User Area */
+			reg = <0x01900000 0x00700000>;
+			label = "NAND User area";
+		};
+
+		partition@2000000 {
+			/* 96MB for Root File System */
+			reg = <0x02000000 0x06000000>;
+			label = "NAND Root File System";
+		};
+
+		partition@8000000 {
+			/* 3968MB for Others */
+			reg = <0x08000000 0xF8000000>;
+			label = "NAND Others";
+		};
+	};
+
+	cpld@2,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,c293pcie-cpld";
+		reg = <0x2 0x0 0x20>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		eeprom@50 {
+			compatible = "st,24c1024";
+			reg = <0x50>;
+		};
+
+		adt7461@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+
+			partition@0 {
+				/* 1MB for u-boot Bootloader Image */
+				/* 1MB for Environment */
+				reg = <0x0 0x00100000>;
+				label = "SPI Flash U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 512KB for DTB Image */
+				reg = <0x00100000 0x00080000>;
+				label = "SPI Flash DTB Image";
+			};
+
+			partition@180000 {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00180000 0x00400000>;
+				label = "SPI Flash Linux Kernel Image";
+			};
+
+			partition@580000 {
+				/* 10.5MB for Compressed RFS Image */
+				reg = <0x00580000 0x00a80000>;
+				label = "SPI Flash Compressed RFSImage";
+			};
+		};
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <2 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x2>;
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
+/include/ "fsl/c293si-post.dtsi"
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 5a58882..1592f8c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -27,6 +27,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 152fa05..d6549ff 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index efdd37c..42fc72a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -32,6 +32,12 @@ config BSC9131_RDB
 	  StarCore SC3850 DSP
 	  Manufacturer : Freescale Semiconductor, Inc
 
+config C293_PCIE
+	  bool "Freescale C293PCIE"
+	  select DEFAULT_UIMAGE
+	  help
+	  This option enables support for the C293PCIE board
+
 config MPC8540_ADS
 	bool "Freescale MPC8540 ADS"
 	select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2eab37e..53c9f75 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_C293_PCIE)   += c293pcie.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
new file mode 100644
index 0000000..6208e49
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -0,0 +1,75 @@
+/*
+ * C293PCIE Board Setup
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init c293_pcie_pic_init(void)
+{
+	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+
+	mpic_init(mpic);
+}
+
+
+/*
+ * Setup the architecture
+ */
+static void __init c293_pcie_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("c293_pcie_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "C293 PCIE board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init c293_pcie_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+
+	if (of_flat_dt_is_compatible(root, "fsl,C293PCIE"))
+		return 1;
+	return 0;
+}
+
+define_machine(c293_pcie) {
+	.name			= "C293 PCIE",
+	.probe			= c293_pcie_probe,
+	.setup_arch		= c293_pcie_setup_arch,
+	.init_IRQ		= c293_pcie_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
-- 
1.8.0

Re: [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree

[Scott Wood]

On 07/25/2013 09:41:17 PM, Po Liu wrote:
> +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> +Job Ring (JR) Node
> +
> +    Child of the crypto node defines data processing interface to =20
> SEC 6
> +    across the peripheral bus for purposes of processing
> +    cryptographic descriptors. The specified address
> +    range can be made visible to one (or more) cores.
> +    The interrupt defined for this node is controlled within
> +    the address range of this node.
> +
> +  - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v6.0-job-ring", if it is
> +      back compatible with old version, better add them all.

Please don't use colloquialisms such as "[you'd] better do this" in a =20
formal specification.

Just say 'Must include "fsl,sec-v6.0-job-ring"' and leave it at that, =20
like the other bindings do.

> +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> +Full Example
> +
> +Since some chips may embeded with more than one SEC 6, we abstract
> +all the same properties into one file qoriq-sec6.0-0.dtsi. Each chip
> +want to binding the node could simply include it in its own device
> +node tree. Below is full example in C293PCIE:

Replace this with:

Since some chips may contain more than one SEC, the dtsi contains only =20
the node contents, not the node itself.  A chip using the SEC should =20
include the dtsi inside each SEC node.  Example:

> +In qoriq-sec6.0-0.dtsi:
> +
> +	compatible =3D "fsl,sec-v6.0";
> +	fsl,sec-era =3D <6>;
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +
> +	jr@1000 {
> +		compatible =3D "fsl,sec-v6.0-job-ring",
> +			     "fsl,sec-v5.2-job-ring",
> +			     "fsl,sec-v5.0-job-ring",
> +			     "fsl,sec-v4.4-job-ring",
> +			     "fsl,sec-v4.0-job-ring";
> +		reg	   =3D <0x1000 0x1000>;
> +	};
> +
> +	jr@2000 {
> +		compatible =3D "fsl,sec-v6.0-job-ring",
> +			     "fsl,sec-v5.2-job-ring",
> +			     "fsl,sec-v5.0-job-ring",
> +			     "fsl,sec-v4.4-job-ring",
> +			     "fsl,sec-v4.0-job-ring";
> +		reg	   =3D <0x2000 0x1000>;
> +	};
> +
> +In the C293 device tree, we add the include of public property:
> +
> +crypto@a0000 {
> +/include/ "qoriq-sec6.0-0.dtsi"
> +	};

Whitespace

> +
> +	crypto@a0000 {
> +		reg =3D <0xa0000 0x20000>;
> +		ranges =3D <0x0 0xa0000 0x20000>;
> +
> +		jr@1000{
> +			interrupts =3D <49 2 0 0>;
> +		};
> +		jr@2000{
> +			interrupts =3D <50 2 0 0>;
> +		};
> +	};

You could combine the above like this:

	crypto@a0000 {
		reg =3D <0xa0000 0x20000>;
		ranges =3D <0 0xa0000 0x20000>;

		/include/ "qoriq-sec6.0-0.dtsi"

		jr@1000 {
			interrupts =3D <49 2 0 0>;
		};

		jr@2000 {
			interrupts =3D <50 2 0 0>;
		};
	};

Why is it "qoriq-sec6.0-0.dtsi" and not "qoriq-sec6.0-dtsi"?

-Scott=

Re: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support

[Scott Wood]

On 07/25/2013 09:41:19 PM, Po Liu wrote:
> +		partition@1900000 {
> +			/* 7MB for User Area */
> +			reg =3D <0x01900000 0x00700000>;
> +			label =3D "NAND User area";
> +		};
> +
> +		partition@2000000 {
> +			/* 96MB for Root File System */
> +			reg =3D <0x02000000 0x06000000>;
> +			label =3D "NAND Root File System";
> +		};
> +
> +		partition@8000000 {
> +			/* 3968MB for Others */
> +			reg =3D <0x08000000 0xF8000000>;
> +			label =3D "NAND Others";
> +		};

Again, what is the difference between "user area" and "others"?  I'm =20
not even sure why it needs to be separate from "root file system", but =20
at least the root filesystem should be larger given the size of the =20
overall flash.

Also please use lowercase for hex.

> +	};
> +
> +	cpld@2,0 {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		compatible =3D "fsl,c293pcie-cpld";
> +		reg =3D <0x2 0x0 0x20>;
> +	};

Remove #address-cells/#size-cells

> +			partition@580000 {
> +				/* 10.5MB for Compressed RFS Image */
> +				reg =3D <0x00580000 0x00a80000>;
> +				label =3D "SPI Flash Compressed RFSImage";
> +			};

Space before "Image".  Why specifiy that it's compressed, versus some =20
other filesystem type?

-Scott=

RE: [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Saturday, July 27, 2013 5:55 AM
>  To: Liu Po-B43644
>  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming Andy-
>  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
>  Subject: Re: [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree
> =20
>  On 07/25/2013 09:41:17 PM, Po Liu wrote:
>  > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>  > +Job Ring (JR) Node
>  > +
>  > +    Child of the crypto node defines data processing interface to
>  > SEC 6
>  > +    across the peripheral bus for purposes of processing
>  > +    cryptographic descriptors. The specified address
>  > +    range can be made visible to one (or more) cores.
>  > +    The interrupt defined for this node is controlled within
>  > +    the address range of this node.
>  > +
>  > +  - compatible
>  > +      Usage: required
>  > +      Value type: <string>
>  > +      Definition: Must include "fsl,sec-v6.0-job-ring", if it is
>  > +      back compatible with old version, better add them all.
> =20
>  Please don't use colloquialisms such as "[you'd] better do this" in a
>  formal specification.
> =20
>  Just say 'Must include "fsl,sec-v6.0-job-ring"' and leave it at that,
>  like the other bindings do.
Ok, I'll remove redundant words.
> =20
>  > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>  > +Full Example
>  > +
>  > +Since some chips may embeded with more than one SEC 6, we abstract
>  > +all the same properties into one file qoriq-sec6.0-0.dtsi. Each chip
>  > +want to binding the node could simply include it in its own device
>  > +node tree. Below is full example in C293PCIE:
> =20
>  Replace this with:
> =20
>  Since some chips may contain more than one SEC, the dtsi contains only
>  the node contents, not the node itself.  A chip using the SEC should
>  include the dtsi inside each SEC node.  Example:
> =20
>  > +In qoriq-sec6.0-0.dtsi:
>  > +
>  > +	compatible =3D "fsl,sec-v6.0";
>  > +	fsl,sec-era =3D <6>;
>  > +	#address-cells =3D <1>;
>  > +	#size-cells =3D <1>;
>  > +
>  > +	jr@1000 {
>  > +		compatible =3D "fsl,sec-v6.0-job-ring",
>  > +			     "fsl,sec-v5.2-job-ring",
>  > +			     "fsl,sec-v5.0-job-ring",
>  > +			     "fsl,sec-v4.4-job-ring",
>  > +			     "fsl,sec-v4.0-job-ring";
>  > +		reg	   =3D <0x1000 0x1000>;
>  > +	};
>  > +
>  > +	jr@2000 {
>  > +		compatible =3D "fsl,sec-v6.0-job-ring",
>  > +			     "fsl,sec-v5.2-job-ring",
>  > +			     "fsl,sec-v5.0-job-ring",
>  > +			     "fsl,sec-v4.4-job-ring",
>  > +			     "fsl,sec-v4.0-job-ring";
>  > +		reg	   =3D <0x2000 0x1000>;
>  > +	};
>  > +
>  > +In the C293 device tree, we add the include of public property:
>  > +
>  > +crypto@a0000 {
>  > +/include/ "qoriq-sec6.0-0.dtsi"
>  > +	};
> =20
>  Whitespace
> =20
>  > +
>  > +	crypto@a0000 {
>  > +		reg =3D <0xa0000 0x20000>;
>  > +		ranges =3D <0x0 0xa0000 0x20000>;
>  > +
>  > +		jr@1000{
>  > +			interrupts =3D <49 2 0 0>;
>  > +		};
>  > +		jr@2000{
>  > +			interrupts =3D <50 2 0 0>;
>  > +		};
>  > +	};
> =20
>  You could combine the above like this:
> =20
>  	crypto@a0000 {
>  		reg =3D <0xa0000 0x20000>;
>  		ranges =3D <0 0xa0000 0x20000>;
> =20
>  		/include/ "qoriq-sec6.0-0.dtsi"
> =20
>  		jr@1000 {
>  			interrupts =3D <49 2 0 0>;
>  		};
> =20
>  		jr@2000 {
>  			interrupts =3D <50 2 0 0>;
>  		};
>  	};
> =20
>  Why is it "qoriq-sec6.0-0.dtsi" and not "qoriq-sec6.0-dtsi"?
Ok, I'll change to qoriq-sec6.0.dtsi
> =20
>  -Scott

RE: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Saturday, July 27, 2013 5:59 AM
>  To: Liu Po-B43644
>  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming Andy-
>  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
>  Subject: Re: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support
> =20
>  On 07/25/2013 09:41:19 PM, Po Liu wrote:
>  > +		partition@1900000 {
>  > +			/* 7MB for User Area */
>  > +			reg =3D <0x01900000 0x00700000>;
>  > +			label =3D "NAND User area";
>  > +		};
>  > +
>  > +		partition@2000000 {
>  > +			/* 96MB for Root File System */
>  > +			reg =3D <0x02000000 0x06000000>;
>  > +			label =3D "NAND Root File System";
>  > +		};
>  > +
>  > +		partition@8000000 {
>  > +			/* 3968MB for Others */
>  > +			reg =3D <0x08000000 0xF8000000>;
>  > +			label =3D "NAND Others";
>  > +		};
> =20
>  Again, what is the difference between "user area" and "others"?  I'm not
>  even sure why it needs to be separate from "root file system", but at
>  least the root filesystem should be larger given the size of the overall
>  flash.
Do you mean just merge up four partition into one "RFS"? Or merge up four p=
artition into "RFS" and "User area" is better?
> =20
>  Also please use lowercase for hex.
> =20
>  > +	};
>  > +
>  > +	cpld@2,0 {
>  > +		#address-cells =3D <1>;
>  > +		#size-cells =3D <1>;
>  > +		compatible =3D "fsl,c293pcie-cpld";
>  > +		reg =3D <0x2 0x0 0x20>;
>  > +	};
> =20
>  Remove #address-cells/#size-cells
> =20
>  > +			partition@580000 {
>  > +				/* 10.5MB for Compressed RFS Image */
>  > +				reg =3D <0x00580000 0x00a80000>;
>  > +				label =3D "SPI Flash Compressed RFSImage";
>  > +			};
> =20
>  Space before "Image".  Why specifiy that it's compressed, versus some
>  other filesystem type?
> =20
Remove all the "compressed" comments when express the RFS partition?
>  -Scott

Re: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support

[Scott Wood]

On 07/28/2013 09:20:11 PM, Liu Po-B43644 wrote:
>=20
>=20
> >  -----Original Message-----
> >  From: Wood Scott-B07421
> >  Sent: Saturday, July 27, 2013 5:59 AM
> >  To: Liu Po-B43644
> >  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming =20
> Andy-
> >  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> >  Subject: Re: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board =20
> support
> >
> >  On 07/25/2013 09:41:19 PM, Po Liu wrote:
> >  > +		partition@1900000 {
> >  > +			/* 7MB for User Area */
> >  > +			reg =3D <0x01900000 0x00700000>;
> >  > +			label =3D "NAND User area";
> >  > +		};
> >  > +
> >  > +		partition@2000000 {
> >  > +			/* 96MB for Root File System */
> >  > +			reg =3D <0x02000000 0x06000000>;
> >  > +			label =3D "NAND Root File System";
> >  > +		};
> >  > +
> >  > +		partition@8000000 {
> >  > +			/* 3968MB for Others */
> >  > +			reg =3D <0x08000000 0xF8000000>;
> >  > +			label =3D "NAND Others";
> >  > +		};
> >
> >  Again, what is the difference between "user area" and "others"?  =20
> I'm not
> >  even sure why it needs to be separate from "root file system", but =20
> at
> >  least the root filesystem should be larger given the size of the =20
> overall
> >  flash.
> Do you mean just merge up four partition into one "RFS"? Or merge up =20
> four partition into "RFS" and "User area" is better?

If you don't have a reason for separating them, then probably yes, =20
merge them all into one.  If you do keep RFS and "user area" separate, =20
then "user area" should be the larger of the two, but the RFS should be =20
more than just 96 MiB.

> >  > +			partition@580000 {
> >  > +				/* 10.5MB for Compressed RFS =20
> Image */
> >  > +				reg =3D <0x00580000 0x00a80000>;
> >  > +				label =3D "SPI Flash Compressed =20
> RFSImage";
> >  > +			};
> >
> >  Space before "Image".  Why specifiy that it's compressed, versus =20
> some
> >  other filesystem type?
> >
> Remove all the "compressed" comments when express the RFS partition?

Yes.

-Scott=

[PATCH v3 1/3] powerpc/85xx: Add SEC6.0 device tree

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Add device tree for SEC 6.0 used on C29x silicon.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the compatible sec v4.0/v4.4/v5.0;
	- Add the device tree binding file fsl-sec6.txt;
Changes for v3:
	- Change some comments in fsl-sec6.txt

 .../devicetree/bindings/crypto/fsl-sec6.txt        | 155 +++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi      |  56 ++++++++
 2 files changed, 211 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec6.txt
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
new file mode 100644
index 0000000..a2a78e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
@@ -0,0 +1,155 @@
+SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale powerpc chip C29X is embeded with SEC 6.
+SEC 6 device tree binding include:
+   -SEC 6 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 6 Node
+
+Description
+
+    Node defines the base address of the SEC 6 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 6 block.
+    For example, In C293, we could see three SEC 6 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 6 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 6.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+	crypto@a0000 {
+		compatible = "fsl,sec-v6.0";
+		fsl,sec-era = <6>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xa0000 0x20000>;
+		ranges = <0 0xa0000 0x20000>;
+	};
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 6
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <49 2 0 0>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In qoriq-sec6.0.dtsi:
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
+
+In the C293 device tree, we add the include of public property:
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0 0xa0000 0x20000>;
+
+		/include/ "qoriq-sec6.0.dtsi"
+
+		jr@1000 {
+			interrupts = <49 2 0 0>;
+		};
+
+		jr@2000 {
+			interrupts = <50 2 0 0>;
+		};
+	};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
new file mode 100644
index 0000000..f75b4f820
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
@@ -0,0 +1,56 @@
+/*
+ * QorIQ Sec/Crypto 6.0 device tree stub
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
-- 
1.8.0

[PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- None
Changes for v3:
	- None

 arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 +++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
 2 files changed, 256 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
new file mode 100644
index 0000000..bd20832
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
@@ -0,0 +1,193 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <19 2 0 0>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0 255>;
+	clock-frequency = <33333333>;
+	interrupts = <16 2 0 0>;
+
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <16 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+			>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+	bus-frequency = <0>;		// Filled out by uboot.
+
+	ecm-law@0 {
+		compatible = "fsl,ecm-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <12>;
+	};
+
+	ecm@1000 {
+		compatible = "fsl,c293-ecm", "fsl,ecm";
+		reg = <0x1000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+	memory-controller@2000 {
+		compatible = "fsl,c293-memory-controller";
+		reg = <0x2000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+	spi0: spi@7000 {
+		fsl,espi-num-chipselects = <1>;
+	};
+
+/include/ "pq3-gpio-0.dtsi"
+	L2: l2-cache-controller@20000 {
+		compatible = "fsl,c293-l2-cache-controller";
+		reg = <0x20000 0x1000>;
+		cache-line-size = <32>;	// 32 bytes
+		cache-size = <0x80000>; // L2,512K
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+	sdhc@2e000 {
+		compatible = "fsl,c293-esdhc", "fsl,esdhc";
+		sdhci,auto-cmd12;
+	};
+
+	crypto@80000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@80000 {
+		reg = <0x80000 0x20000>;
+		ranges = <0x0 0x80000 0x20000>;
+
+		jr@1000{
+			interrupts = <45 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <57 2 0 0>;
+		};
+	};
+
+	crypto@a0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0x0 0xa0000 0x20000>;
+
+		jr@1000{
+			interrupts = <49 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <50 2 0 0>;
+		};
+	};
+
+	crypto@c0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@c0000 {
+		reg = <0xc0000 0x20000>;
+		ranges = <0x0 0xc0000 0x20000>;
+
+		jr@1000{
+			interrupts = <55 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <56 2 0 0>;
+		};
+	};
+
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			reg = <0x10000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			reg = <0x11000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+	global-utilities@e0000 {
+		compatible = "fsl,c293-guts";
+		reg = <0xe0000 0x1000>;
+		fsl,has-rstcr;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
new file mode 100644
index 0000000..065049d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,C293";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e500v2@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.8.0

[PATCH v3 3/3] powerpc/85xx: Add C293PCIE board support

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

C293PCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the JFFS2 partitions in NOR/NAND/SPI flash;
	- Implement the NAND partitions;
	- Remove the no use descriptions for cpld node;
	- Add mpc85xx_smp_defconfig and mpc85xx_defconfig for C293;
	- Remove the no use includes in c293pcie.c
Changes for v3:
	- Remove some partitions for NAND, merge them into RFS
	- Modify the SPI RFS partition expression
	- Remove #address-cells #size-cells in cpld node

 arch/powerpc/boot/dts/c293pcie.dts         | 223 +++++++++++++++++++++++++++++
 arch/powerpc/configs/mpc85xx_defconfig     |   1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig |   1 +
 arch/powerpc/platforms/85xx/Kconfig        |   6 +
 arch/powerpc/platforms/85xx/Makefile       |   1 +
 arch/powerpc/platforms/85xx/c293pcie.c     |  75 ++++++++++
 6 files changed, 307 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/c293pcie.dts
 create mode 100644 arch/powerpc/platforms/85xx/c293pcie.c

diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
new file mode 100644
index 0000000..24a2cdd
--- /dev/null
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -0,0 +1,223 @@
+/*
+ * C293 PCIE Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/c293si-pre.dtsi"
+
+/ {
+	model = "fsl,C293PCIE";
+	compatible = "fsl,C293PCIE";
+
+	memory {
+		device_type = "memory";
+	};
+
+	ifc: ifc@fffe1e000 {
+		reg = <0xf 0xffe1e000 0 0x2000>;
+		ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+			  0x2 0x0 0xf 0xffdf0000 0x00010000>;
+
+	};
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&ifc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 1MB for DTB Image */
+			reg = <0x0 0x00100000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@100000 {
+			/* 8 MB for Linux Kernel Image */
+			reg = <0x00100000 0x00800000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@900000 {
+			/* 53MB for rootfs */
+			reg = <0x00900000 0x03500000>;
+			label = "NOR Rootfs Image";
+		};
+
+		partition@3e00000 {
+			/* 1MB for blob encrypted key */
+			reg = <0x03e00000 0x00100000>;
+			label = "NOR blob encrypted key";
+		};
+
+		partition@3f00000 {
+			/* 512KB for u-boot Bootloader Image and evn */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,ifc-nand";
+		reg = <0x1 0x0 0x10000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 4MB for Linux Kernel Image */
+			reg = <0x00200000 0x00400000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@600000 {
+			/* 4090MB for Root file System Image */
+			reg = <0x00600000 0xffa00000>;
+			label = "NAND RFS Image";
+		};
+	};
+
+	cpld@2,0 {
+		compatible = "fsl,c293pcie-cpld";
+		reg = <0x2 0x0 0x20>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		eeprom@50 {
+			compatible = "st,24c1024";
+			reg = <0x50>;
+		};
+
+		adt7461@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+
+			partition@0 {
+				/* 1MB for u-boot Bootloader Image */
+				/* 1MB for Environment */
+				reg = <0x0 0x00100000>;
+				label = "SPI Flash U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 512KB for DTB Image */
+				reg = <0x00100000 0x00080000>;
+				label = "SPI Flash DTB Image";
+			};
+
+			partition@180000 {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00180000 0x00400000>;
+				label = "SPI Flash Linux Kernel Image";
+			};
+
+			partition@580000 {
+				/* 10.5MB for RFS Image */
+				reg = <0x00580000 0x00a80000>;
+				label = "SPI Flash RFS Image";
+			};
+		};
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <2 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x2>;
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
+/include/ "fsl/c293si-post.dtsi"
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 5a58882..1592f8c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -27,6 +27,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 152fa05..d6549ff 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index efdd37c..42fc72a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -32,6 +32,12 @@ config BSC9131_RDB
 	  StarCore SC3850 DSP
 	  Manufacturer : Freescale Semiconductor, Inc
 
+config C293_PCIE
+	  bool "Freescale C293PCIE"
+	  select DEFAULT_UIMAGE
+	  help
+	  This option enables support for the C293PCIE board
+
 config MPC8540_ADS
 	bool "Freescale MPC8540 ADS"
 	select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2eab37e..53c9f75 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_C293_PCIE)   += c293pcie.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
new file mode 100644
index 0000000..6208e49
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -0,0 +1,75 @@
+/*
+ * C293PCIE Board Setup
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init c293_pcie_pic_init(void)
+{
+	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+
+	mpic_init(mpic);
+}
+
+
+/*
+ * Setup the architecture
+ */
+static void __init c293_pcie_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("c293_pcie_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "C293 PCIE board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init c293_pcie_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+
+	if (of_flat_dt_is_compatible(root, "fsl,C293PCIE"))
+		return 1;
+	return 0;
+}
+
+define_machine(c293_pcie) {
+	.name			= "C293 PCIE",
+	.probe			= c293_pcie_probe,
+	.setup_arch		= c293_pcie_setup_arch,
+	.init_IRQ		= c293_pcie_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
-- 
1.8.0

Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Scott Wood]

On 07/30/2013 03:49:22 AM, Po Liu wrote:
> From: Mingkai Hu <Mingkai.Hu@freescale.com>
>=20
> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
> Signed-off-by: Po Liu <Po.Liu@freescale.com>
> ---
> Changes for v2:
> 	- None
> Changes for v3:
> 	- None
>=20
>  arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 =20
> +++++++++++++++++++++++++++++
>  arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
>  2 files changed, 256 insertions(+)
>  create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
>  create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi =20
> b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> new file mode 100644
> index 0000000..bd20832
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> @@ -0,0 +1,193 @@
> +/*
> + * C293 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following =20
> conditions are met:
> + *     * Redistributions of source code must retain the above =20
> copyright
> + *       notice, this list of conditions and the following =20
> disclaimer.
> + *     * Redistributions in binary form must reproduce the above =20
> copyright
> + *       notice, this list of conditions and the following =20
> disclaimer in the
> + *       documentation and/or other materials provided with the =20
> distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =20
> products
> + *       derived from this software without specific prior written =20
> permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms =20
> of the
> + * GNU General Public License ("GPL") as published by the Free =20
> Software
> + * Foundation, either version 2 of that License or (at your option) =20
> any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' =20
> AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =20
> IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR =20
> PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =20
> FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR =20
> CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS =20
> OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =20
> CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT =20
> LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =20
> USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <19 2 0 0>;
> +};
> +
> +/* controller at 0xa000 */
> +&pci0 {
> +	compatible =3D "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0 255>;
> +	clock-frequency =3D <33333333>;
> +	interrupts =3D <16 2 0 0>;

Remove clock-frequency (surely PCIe is not running at 33 MHz).

> +	crypto@80000 {
> +/include/ "qoriq-sec6.0-0.dtsi"
> +	};
> +
> +	crypto@80000 {
> +		reg =3D <0x80000 0x20000>;
> +		ranges =3D <0x0 0x80000 0x20000>;
> +
> +		jr@1000{
> +			interrupts =3D <45 2 0 0>;
> +		};
> +		jr@2000{
> +			interrupts =3D <57 2 0 0>;
> +		};
> +	};

Do these inline the way the example shows.

-Scott=

Re: [PATCH v3 3/3] powerpc/85xx: Add C293PCIE board support

[Scott Wood]

On 07/30/2013 03:49:23 AM, Po Liu wrote:
> +	nand@1,0 {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		compatible =3D "fsl,ifc-nand";
> +		reg =3D <0x1 0x0 0x10000>;
> +
> +		partition@0 {
> +			/* This location must not be altered  */
> +			/* 1MB for u-boot Bootloader Image */
> +			reg =3D <0x0 0x00100000>;
> +			label =3D "NAND U-Boot Image";
> +			read-only;
> +		};
> +
> +		partition@100000 {
> +			/* 1MB for DTB Image */
> +			reg =3D <0x00100000 0x00100000>;
> +			label =3D "NAND DTB Image";
> +		};
> +
> +		partition@200000 {
> +			/* 4MB for Linux Kernel Image */
> +			reg =3D <0x00200000 0x00400000>;
> +			label =3D "NAND Linux Kernel Image";
> +		};
> +
> +		partition@600000 {
> +			/* 4090MB for Root file System Image */
> +			reg =3D <0x00600000 0xffa00000>;
> +			label =3D "NAND RFS Image";
> +		};
> +	};

Might want to leave a bit more room for the kernel image, given the =20
size of NAND.

-Scott=

RE: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Wednesday, July 31, 2013 2:28 AM
>  To: Liu Po-B43644
>  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming Andy-
>  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
>  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for
>  C293
> =20
>  On 07/30/2013 03:49:22 AM, Po Liu wrote:
>  > From: Mingkai Hu <Mingkai.Hu@freescale.com>
>  >
>  > Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
>  > Signed-off-by: Po Liu <Po.Liu@freescale.com>
>  > ---
>  > Changes for v2:
>  > 	- None
>  > Changes for v3:
>  > 	- None
>  >
>  >  arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193
>  > +++++++++++++++++++++++++++++
>  >  arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
>  >  2 files changed, 256 insertions(+)
>  >  create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
>  >  create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
>  >
>  > diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
>  > b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
>  > new file mode 100644
>  > index 0000000..bd20832
>  > --- /dev/null
>  > +++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
>  > @@ -0,0 +1,193 @@
>  > +/*
>  > + * C293 Silicon/SoC Device Tree Source (post include)
>  > + *
>  > + * Copyright 2012 Freescale Semiconductor Inc.
>  > + *
>  > + * Redistribution and use in source and binary forms, with or without
>  > + * modification, are permitted provided that the following
>  > conditions are met:
>  > + *     * Redistributions of source code must retain the above
>  > copyright
>  > + *       notice, this list of conditions and the following
>  > disclaimer.
>  > + *     * Redistributions in binary form must reproduce the above
>  > copyright
>  > + *       notice, this list of conditions and the following
>  > disclaimer in the
>  > + *       documentation and/or other materials provided with the
>  > distribution.
>  > + *     * Neither the name of Freescale Semiconductor nor the
>  > + *       names of its contributors may be used to endorse or promote
>  > products
>  > + *       derived from this software without specific prior written
>  > permission.
>  > + *
>  > + *
>  > + * ALTERNATIVELY, this software may be distributed under the terms
>  > of the
>  > + * GNU General Public License ("GPL") as published by the Free
>  > Software
>  > + * Foundation, either version 2 of that License or (at your option)
>  > any
>  > + * later version.
>  > + *
>  > + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''
>  > AND ANY
>  > + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>  > IMPLIED
>  > + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>  > PURPOSE ARE
>  > + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
>  > FOR ANY
>  > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
>  > CONSEQUENTIAL DAMAGES
>  > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
>  > OR SERVICES;
>  > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
>  > CAUSED AND
>  > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
>  > LIABILITY, OR TORT
>  > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
>  > USE OF THIS
>  > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  > + */
>  > +
>  > +&ifc {
>  > +	#address-cells =3D <2>;
>  > +	#size-cells =3D <1>;
>  > +	compatible =3D "fsl,ifc", "simple-bus";
>  > +	interrupts =3D <19 2 0 0>;
>  > +};
>  > +
>  > +/* controller at 0xa000 */
>  > +&pci0 {
>  > +	compatible =3D "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
>  > +	device_type =3D "pci";
>  > +	#size-cells =3D <2>;
>  > +	#address-cells =3D <3>;
>  > +	bus-range =3D <0 255>;
>  > +	clock-frequency =3D <33333333>;
>  > +	interrupts =3D <16 2 0 0>;
> =20
>  Remove clock-frequency (surely PCIe is not running at 33 MHz).
> =20
>  > +	crypto@80000 {
>  > +/include/ "qoriq-sec6.0-0.dtsi"
>  > +	};
>  > +
>  > +	crypto@80000 {
>  > +		reg =3D <0x80000 0x20000>;
>  > +		ranges =3D <0x0 0x80000 0x20000>;
>  > +
>  > +		jr@1000{
>  > +			interrupts =3D <45 2 0 0>;
>  > +		};
>  > +		jr@2000{
>  > +			interrupts =3D <57 2 0 0>;
>  > +		};
>  > +	};
> =20
>  Do these inline the way the example shows.
Sorry, Scott, I just remember in this way, the node can't be recognized by =
system when run Uboot. The include can't be in the crypto@80000. See the di=
scussion in http://git.am.freescale.net:8181/#/c/736/  .
Maybe I should re-modify the example file.
> =20
>  -Scott

Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Scott Wood]

On 07/30/2013 09:13:28 PM, Liu Po-B43644 wrote:
>=20
> >  -----Original Message-----
> >  From: Wood Scott-B07421
> >  Sent: Wednesday, July 31, 2013 2:28 AM
> >  To: Liu Po-B43644
> >  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming =20
> Andy-
> >  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> >  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree =20
> for
> >  C293
> >
> >  On 07/30/2013 03:49:22 AM, Po Liu wrote:
> >  > +	crypto@80000 {
> >  > +/include/ "qoriq-sec6.0-0.dtsi"
> >  > +	};
> >  > +
> >  > +	crypto@80000 {
> >  > +		reg =3D <0x80000 0x20000>;
> >  > +		ranges =3D <0x0 0x80000 0x20000>;
> >  > +
> >  > +		jr@1000{
> >  > +			interrupts =3D <45 2 0 0>;
> >  > +		};
> >  > +		jr@2000{
> >  > +			interrupts =3D <57 2 0 0>;
> >  > +		};
> >  > +	};
> >
> >  Do these inline the way the example shows.
> Sorry, Scott, I just remember in this way, the node can't be =20
> recognized by system when run Uboot. The include can't be in the =20
> crypto@80000. See the discussion in =20
> http://git.am.freescale.net:8181/#/c/736/  .
> Maybe I should re-modify the example file.

git.am.freescale.net is not accessible outside of Freescale; don't =20
reference it on external lists.  In any case, I don't know what =20
specifically you want me to look at there.  Just put the explanation =20
here.

I do not expect the dtc output to be any different between the two =20
methods.  Could you check this (by using dtc to decompile the dtb =20
afterward) and point out exactly how the output differs between the two =20
approaches?

-Scott=

RE: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Liu Po-B43644]

>  -----Original Message-----
>  From: Wood Scott-B07421
>  Sent: Wednesday, July 31, 2013 11:47 PM
>  To: Liu Po-B43644
>  Cc: Wood Scott-B07421; linuxppc-dev@ozlabs.org; galak@kernel.crashing.or=
g;
>  Fleming Andy-AFLEMING; Hu Mingkai-B21284
>  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for
>  C293
> =20
>  On 07/30/2013 09:13:28 PM, Liu Po-B43644 wrote:
>  >
>  > >  -----Original Message-----
>  > >  From: Wood Scott-B07421
>  > >  Sent: Wednesday, July 31, 2013 2:28 AM
>  > >  To: Liu Po-B43644
>  > >  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming
>  > Andy-
>  > >  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
>  > >  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree
>  > for
>  > >  C293
>  > >
>  > >  On 07/30/2013 03:49:22 AM, Po Liu wrote:
>  > >  > +	crypto@80000 {
>  > >  > +/include/ "qoriq-sec6.0-0.dtsi"
>  > >  > +	};
>  > >  > +
>  > >  > +	crypto@80000 {
>  > >  > +		reg =3D <0x80000 0x20000>;
>  > >  > +		ranges =3D <0x0 0x80000 0x20000>;
>  > >  > +
>  > >  > +		jr@1000{
>  > >  > +			interrupts =3D <45 2 0 0>;
>  > >  > +		};
>  > >  > +		jr@2000{
>  > >  > +			interrupts =3D <57 2 0 0>;
>  > >  > +		};
>  > >  > +	};
>  > >
>  > >  Do these inline the way the example shows.
>  > Sorry, Scott, I just remember in this way, the node can't be
>  > recognized by system when run Uboot. The include can't be in the
>  > crypto@80000. See the discussion in
>  > http://git.am.freescale.net:8181/#/c/736/  .
>  > Maybe I should re-modify the example file.
> =20
>  git.am.freescale.net is not accessible outside of Freescale; don't
>  reference it on external lists.  In any case, I don't know what
>  specifically you want me to look at there.  Just put the explanation her=
e.
Sorry, I've realize that.
The fact is that: when put the include into the crypto@xxxx, it can't compi=
le success(make c293pcie.dtb as example). Error will show as:

ERROR (duplicate_node_names): Duplicate node name /soc@fffe00000/crypto@800=
00/jr@1000
 =20
>  I do not expect the dtc output to be any different between the two
>  methods.  Could you check this (by using dtc to decompile the dtb
>  afterward) and point out exactly how the output differs between the two
>  approaches?
Since it will compile error in this way, so will not output .dtb file
> =20
>  -Scott

[PATCH v4 1/3] powerpc/85xx: Add SEC6.0 device tree

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Add device tree for SEC 6.0 used on C29x silicon.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the compatible sec v4.0/v4.4/v5.0;
	- Add the device tree binding file fsl-sec6.txt;
Changes for v3:
	- Change some comments in fsl-sec6.txt
Changes for v4:
	- Change the full example in fsl-sec6.txt

 .../devicetree/bindings/crypto/fsl-sec6.txt        | 157 +++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi      |  56 ++++++++
 2 files changed, 213 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec6.txt
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
new file mode 100644
index 0000000..c0a20cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
@@ -0,0 +1,157 @@
+SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale powerpc chip C29X is embeded with SEC 6.
+SEC 6 device tree binding include:
+   -SEC 6 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 6 Node
+
+Description
+
+    Node defines the base address of the SEC 6 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 6 block.
+    For example, In C293, we could see three SEC 6 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 6 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 6.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+	crypto@a0000 {
+		compatible = "fsl,sec-v6.0";
+		fsl,sec-era = <6>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xa0000 0x20000>;
+		ranges = <0 0xa0000 0x20000>;
+	};
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 6
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <49 2 0 0>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In qoriq-sec6.0.dtsi:
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
+
+In the C293 device tree, we add the include of public property:
+
+	crypto@a0000 {
+		/include/ "qoriq-sec6.0.dtsi"
+	}
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0 0xa0000 0x20000>;
+
+		jr@1000 {
+			interrupts = <49 2 0 0>;
+		};
+
+		jr@2000 {
+			interrupts = <50 2 0 0>;
+		};
+	};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
new file mode 100644
index 0000000..f75b4f820
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
@@ -0,0 +1,56 @@
+/*
+ * QorIQ Sec/Crypto 6.0 device tree stub
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+	compatible = "fsl,sec-v6.0";
+	fsl,sec-era = <6>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	jr@1000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x1000 0x1000>;
+	};
+
+	jr@2000 {
+		compatible = "fsl,sec-v6.0-job-ring",
+			     "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.4-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg	   = <0x2000 0x1000>;
+	};
-- 
1.8.0

[PATCH v4 2/3] powerpc/85xx: Add silicon device tree for C293

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- None
Changes for v3:
	- None
Changes for v4:
	- None

 arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193 +++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi  |  63 ++++++++++
 2 files changed, 256 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
new file mode 100644
index 0000000..bd20832
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
@@ -0,0 +1,193 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <19 2 0 0>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0 255>;
+	clock-frequency = <33333333>;
+	interrupts = <16 2 0 0>;
+
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <16 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+			>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+	bus-frequency = <0>;		// Filled out by uboot.
+
+	ecm-law@0 {
+		compatible = "fsl,ecm-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <12>;
+	};
+
+	ecm@1000 {
+		compatible = "fsl,c293-ecm", "fsl,ecm";
+		reg = <0x1000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+	memory-controller@2000 {
+		compatible = "fsl,c293-memory-controller";
+		reg = <0x2000 0x1000>;
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+	spi0: spi@7000 {
+		fsl,espi-num-chipselects = <1>;
+	};
+
+/include/ "pq3-gpio-0.dtsi"
+	L2: l2-cache-controller@20000 {
+		compatible = "fsl,c293-l2-cache-controller";
+		reg = <0x20000 0x1000>;
+		cache-line-size = <32>;	// 32 bytes
+		cache-size = <0x80000>; // L2,512K
+		interrupts = <16 2 0 0>;
+	};
+
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+	sdhc@2e000 {
+		compatible = "fsl,c293-esdhc", "fsl,esdhc";
+		sdhci,auto-cmd12;
+	};
+
+	crypto@80000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@80000 {
+		reg = <0x80000 0x20000>;
+		ranges = <0x0 0x80000 0x20000>;
+
+		jr@1000{
+			interrupts = <45 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <57 2 0 0>;
+		};
+	};
+
+	crypto@a0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@a0000 {
+		reg = <0xa0000 0x20000>;
+		ranges = <0x0 0xa0000 0x20000>;
+
+		jr@1000{
+			interrupts = <49 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <50 2 0 0>;
+		};
+	};
+
+	crypto@c0000 {
+/include/ "qoriq-sec6.0-0.dtsi"
+	};
+
+	crypto@c0000 {
+		reg = <0xc0000 0x20000>;
+		ranges = <0x0 0xc0000 0x20000>;
+
+		jr@1000{
+			interrupts = <55 2 0 0>;
+		};
+		jr@2000{
+			interrupts = <56 2 0 0>;
+		};
+	};
+
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			reg = <0x10000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			reg = <0x11000 0x1000>;
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+	global-utilities@e0000 {
+		compatible = "fsl,c293-guts";
+		reg = <0xe0000 0x1000>;
+		fsl,has-rstcr;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
new file mode 100644
index 0000000..065049d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * C293 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,C293";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e500v2@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.8.0

[PATCH v4 3/3] powerpc/85xx: Add C293PCIE board support

[Po Liu]

From: Mingkai Hu <Mingkai.Hu@freescale.com>

C293PCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
Changes for v2:
	- Remove the JFFS2 partitions in NOR/NAND/SPI flash;
	- Implement the NAND partitions;
	- Remove the no use descriptions for cpld node;
	- Add mpc85xx_smp_defconfig and mpc85xx_defconfig for C293;
	- Remove the no use includes in c293pcie.c
Changes for v3:
	- Remove some partitions for NAND, merge them into RFS
	- Modify the SPI RFS partition expression
	- Remove #address-cells #size-cells in cpld node
Changes for v4:
	- Set NAND kernel image partition to be 16MB size from 4MB

 arch/powerpc/boot/dts/c293pcie.dts         | 223 +++++++++++++++++++++++++++++
 arch/powerpc/configs/mpc85xx_defconfig     |   1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig |   1 +
 arch/powerpc/platforms/85xx/Kconfig        |   6 +
 arch/powerpc/platforms/85xx/Makefile       |   1 +
 arch/powerpc/platforms/85xx/c293pcie.c     |  75 ++++++++++
 6 files changed, 307 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/c293pcie.dts
 create mode 100644 arch/powerpc/platforms/85xx/c293pcie.c

diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
new file mode 100644
index 0000000..1238bda
--- /dev/null
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -0,0 +1,223 @@
+/*
+ * C293 PCIE Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/c293si-pre.dtsi"
+
+/ {
+	model = "fsl,C293PCIE";
+	compatible = "fsl,C293PCIE";
+
+	memory {
+		device_type = "memory";
+	};
+
+	ifc: ifc@fffe1e000 {
+		reg = <0xf 0xffe1e000 0 0x2000>;
+		ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+			  0x2 0x0 0xf 0xffdf0000 0x00010000>;
+
+	};
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&ifc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 1MB for DTB Image */
+			reg = <0x0 0x00100000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@100000 {
+			/* 8 MB for Linux Kernel Image */
+			reg = <0x00100000 0x00800000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@900000 {
+			/* 53MB for rootfs */
+			reg = <0x00900000 0x03500000>;
+			label = "NOR Rootfs Image";
+		};
+
+		partition@3e00000 {
+			/* 1MB for blob encrypted key */
+			reg = <0x03e00000 0x00100000>;
+			label = "NOR blob encrypted key";
+		};
+
+		partition@3f00000 {
+			/* 512KB for u-boot Bootloader Image and evn */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,ifc-nand";
+		reg = <0x1 0x0 0x10000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 16MB for Linux Kernel Image */
+			reg = <0x00200000 0x01000000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@1200000 {
+			/* 4078MB for Root file System Image */
+			reg = <0x00600000 0xfee00000>;
+			label = "NAND RFS Image";
+		};
+	};
+
+	cpld@2,0 {
+		compatible = "fsl,c293pcie-cpld";
+		reg = <0x2 0x0 0x20>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		eeprom@50 {
+			compatible = "st,24c1024";
+			reg = <0x50>;
+		};
+
+		adt7461@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <50000000>;
+
+			partition@0 {
+				/* 1MB for u-boot Bootloader Image */
+				/* 1MB for Environment */
+				reg = <0x0 0x00100000>;
+				label = "SPI Flash U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 512KB for DTB Image */
+				reg = <0x00100000 0x00080000>;
+				label = "SPI Flash DTB Image";
+			};
+
+			partition@180000 {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00180000 0x00400000>;
+				label = "SPI Flash Linux Kernel Image";
+			};
+
+			partition@580000 {
+				/* 10.5MB for RFS Image */
+				reg = <0x00580000 0x00a80000>;
+				label = "SPI Flash RFS Image";
+			};
+		};
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <2 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x2>;
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
+/include/ "fsl/c293si-post.dtsi"
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 5a58882..1592f8c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -27,6 +27,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 152fa05..d6549ff 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index efdd37c..42fc72a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -32,6 +32,12 @@ config BSC9131_RDB
 	  StarCore SC3850 DSP
 	  Manufacturer : Freescale Semiconductor, Inc
 
+config C293_PCIE
+	  bool "Freescale C293PCIE"
+	  select DEFAULT_UIMAGE
+	  help
+	  This option enables support for the C293PCIE board
+
 config MPC8540_ADS
 	bool "Freescale MPC8540 ADS"
 	select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2eab37e..53c9f75 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_C293_PCIE)   += c293pcie.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
new file mode 100644
index 0000000..6208e49
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -0,0 +1,75 @@
+/*
+ * C293PCIE Board Setup
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init c293_pcie_pic_init(void)
+{
+	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+
+	mpic_init(mpic);
+}
+
+
+/*
+ * Setup the architecture
+ */
+static void __init c293_pcie_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("c293_pcie_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "C293 PCIE board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init c293_pcie_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+
+	if (of_flat_dt_is_compatible(root, "fsl,C293PCIE"))
+		return 1;
+	return 0;
+}
+
+define_machine(c293_pcie) {
+	.name			= "C293 PCIE",
+	.probe			= c293_pcie_probe,
+	.setup_arch		= c293_pcie_setup_arch,
+	.init_IRQ		= c293_pcie_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
-- 
1.8.0

Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293

[Scott Wood]

On Wed, 2013-07-31 at 21:32 -0500, Liu Po-B43644 wrote:
> >  -----Original Message-----
> >  From: Wood Scott-B07421
> >  Sent: Wednesday, July 31, 2013 11:47 PM
> >  To: Liu Po-B43644
> >  Cc: Wood Scott-B07421; linuxppc-dev@ozlabs.org; galak@kernel.crashing.org;
> >  Fleming Andy-AFLEMING; Hu Mingkai-B21284
> >  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for
> >  C293
> >  
> >  On 07/30/2013 09:13:28 PM, Liu Po-B43644 wrote:
> >  >
> >  > >  -----Original Message-----
> >  > >  From: Wood Scott-B07421
> >  > >  Sent: Wednesday, July 31, 2013 2:28 AM
> >  > >  To: Liu Po-B43644
> >  > >  Cc: linuxppc-dev@ozlabs.org; galak@kernel.crashing.org; Fleming
> >  > Andy-
> >  > >  AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> >  > >  Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree
> >  > for
> >  > >  C293
> >  > >
> >  > >  On 07/30/2013 03:49:22 AM, Po Liu wrote:
> >  > >  > +	crypto@80000 {
> >  > >  > +/include/ "qoriq-sec6.0-0.dtsi"
> >  > >  > +	};
> >  > >  > +
> >  > >  > +	crypto@80000 {
> >  > >  > +		reg = <0x80000 0x20000>;
> >  > >  > +		ranges = <0x0 0x80000 0x20000>;
> >  > >  > +
> >  > >  > +		jr@1000{
> >  > >  > +			interrupts = <45 2 0 0>;
> >  > >  > +		};
> >  > >  > +		jr@2000{
> >  > >  > +			interrupts = <57 2 0 0>;
> >  > >  > +		};
> >  > >  > +	};
> >  > >
> >  > >  Do these inline the way the example shows.
> >  > Sorry, Scott, I just remember in this way, the node can't be
> >  > recognized by system when run Uboot. The include can't be in the
> >  > crypto@80000. See the discussion in
> >  > http://git.am.freescale.net:8181/#/c/736/  .
> >  > Maybe I should re-modify the example file.
> >  
> >  git.am.freescale.net is not accessible outside of Freescale; don't
> >  reference it on external lists.  In any case, I don't know what
> >  specifically you want me to look at there.  Just put the explanation here.
> Sorry, I've realize that.
> The fact is that: when put the include into the crypto@xxxx, it can't compile success(make c293pcie.dtb as example). Error will show as:
> 
> ERROR (duplicate_node_names): Duplicate node name /soc@fffe00000/crypto@80000/jr@1000

OK... It seems dtc will only merge duplicates when it's not the first
time it's seen the parent node.  We're probably relying on a side-effect
of the intended behavior of accepting duplicates between the multiple
instances of the parent node.

-Scott