* [PATCH 0/2] Use scratch register for PGD when MIPS_PGD_C0_CONTEXT is not set @ 2013-08-11 11:40 Jayachandran C 2013-08-11 11:40 ` [PATCH 1/2] MIPS: Move definition of SMP processor id register to header file Jayachandran C 2013-08-11 11:40 ` [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Jayachandran C 0 siblings, 2 replies; 9+ messages in thread From: Jayachandran C @ 2013-08-11 11:40 UTC (permalink / raw) To: ralf, linux-mips; +Cc: Jayachandran C These are the two pending patches in this series. I have reordered the changes so that the cleanup patch can be applied first. The second patch has the changes to use scratch registers when MIPS_PGD_C0_CONTEXT is not defined - this has not changed. JC. Jayachandran C (2): MIPS: Move definition of SMP processor id register to header file MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT arch/mips/include/asm/mmu_context.h | 22 ++---- arch/mips/include/asm/stackframe.h | 24 ++----- arch/mips/include/asm/thread_info.h | 33 ++++++++- arch/mips/mm/tlbex.c | 136 +++++++++++++++-------------------- 4 files changed, 103 insertions(+), 112 deletions(-) -- 1.7.9.5 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] MIPS: Move definition of SMP processor id register to header file 2013-08-11 11:40 [PATCH 0/2] Use scratch register for PGD when MIPS_PGD_C0_CONTEXT is not set Jayachandran C @ 2013-08-11 11:40 ` Jayachandran C 2013-08-11 11:40 ` [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Jayachandran C 1 sibling, 0 replies; 9+ messages in thread From: Jayachandran C @ 2013-08-11 11:40 UTC (permalink / raw) To: ralf, linux-mips; +Cc: Jayachandran C The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> --- arch/mips/include/asm/mmu_context.h | 16 ++++------ arch/mips/include/asm/stackframe.h | 24 ++++----------- arch/mips/include/asm/thread_info.h | 33 ++++++++++++++++++++- arch/mips/mm/tlbex.c | 56 ++++------------------------------- 4 files changed, 49 insertions(+), 80 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 3b29079..ab8e260 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -35,10 +35,11 @@ do { \ #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ + write_c0_xcontext((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ } while (0) -#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* * For the fast tlb miss handlers, we keep a per cpu array of pointers @@ -50,18 +51,11 @@ extern unsigned long pgd_current[]; #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ pgd_current[smp_processor_id()] = (unsigned long)(pgd) -#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 25); \ + write_c0_context((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT); \ back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif -#ifdef CONFIG_64BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 26); \ - back_to_back_c0_hazard(); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 23fc95e..4857e2c 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,6 +17,7 @@ #include <asm/asmmacro.h> #include <asm/mipsregs.h> #include <asm/asm-offsets.h> +#include <asm/thread_info.h> /* * For SMTC kernel, global IE should be left set, and interrupts @@ -93,21 +94,8 @@ .endm #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC -#define PTEBASE_SHIFT 19 /* TCBIND */ -#define CPU_ID_REG CP0_TCBIND -#define CPU_ID_MFC0 mfc0 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define PTEBASE_SHIFT 48 /* XCONTEXT */ -#define CPU_ID_REG CP0_XCONTEXT -#define CPU_ID_MFC0 MFC0 -#else -#define PTEBASE_SHIFT 23 /* CONTEXT */ -#define CPU_ID_REG CP0_CONTEXT -#define CPU_ID_MFC0 MFC0 -#endif .macro get_saved_sp /* SMP variation */ - CPU_ID_MFC0 k0, CPU_ID_REG + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -117,17 +105,17 @@ daddiu k1, %hi(kernelsp) dsll k1, 16 #endif - LONG_SRL k0, PTEBASE_SHIFT + LONG_SRL k0, SMP_CPUID_PTRSHIFT LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - CPU_ID_MFC0 \temp, CPU_ID_REG - LONG_SRL \temp, PTEBASE_SHIFT + ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG + LONG_SRL \temp, SMP_CPUID_PTRSHIFT LONG_S \stackp, kernelsp(\temp) .endm -#else +#else /* !CONFIG_SMP */ .macro get_saved_sp /* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 61215a3..e0c8cf3 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -147,6 +147,37 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ _TIF_WORK_SYSCALL_EXIT) -#endif /* __KERNEL__ */ +/* + * We stash processor id into a COP0 register to retrieve it fast + * at kernel exception entry. + */ +#if defined(CONFIG_MIPS_MT_SMTC) +#define SMP_CPUID_REG 2, 2 /* TCBIND */ +#define ASM_SMP_CPUID_REG $2, 2 +#define SMP_CPUID_PTRSHIFT 19 +#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#define SMP_CPUID_REG 20, 0 /* XCONTEXT */ +#define ASM_SMP_CPUID_REG $20 +#define SMP_CPUID_PTRSHIFT 48 +#else +#define SMP_CPUID_REG 4, 0 /* CONTEXT */ +#define ASM_SMP_CPUID_REG $4 +#define SMP_CPUID_PTRSHIFT 23 +#endif +#ifdef CONFIG_64BIT +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) +#else +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) +#endif + +#ifdef CONFIG_MIPS_MT_SMTC +#define ASM_CPUID_MFC0 mfc0 +#define UASM_i_CPUID_MFC0 uasm_i_mfc0 +#else +#define ASM_CPUID_MFC0 MFC0 +#define UASM_i_CPUID_MFC0 UASM_i_MFC0 +#endif + +#endif /* __KERNEL__ */ #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 556cb48..54f3270 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -337,10 +337,6 @@ static struct work_registers build_get_work_registers(u32 **p) { struct work_registers r; - int smp_processor_id_reg; - int smp_processor_id_sel; - int smp_processor_id_shift; - if (scratch_reg >= 0) { /* Save in CPU local C0_KScratch? */ UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); @@ -351,25 +347,9 @@ static struct work_registers build_get_work_registers(u32 **p) } if (num_possible_cpus() > 1) { -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - smp_processor_id_shift = 51; - smp_processor_id_reg = 20; /* XContext */ - smp_processor_id_sel = 0; -#else -# ifdef CONFIG_32BIT - smp_processor_id_shift = 25; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -# ifdef CONFIG_64BIT - smp_processor_id_shift = 26; - smp_processor_id_reg = 4; /* Context */ - smp_processor_id_sel = 0; -# endif -#endif /* Get smp_processor_id */ - UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); - UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); + UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); + UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); /* handler_reg_save index in K0 */ UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); @@ -834,20 +814,8 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_drotr(p, ptr, ptr, 11); } #elif defined(CONFIG_SMP) -# ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); - uasm_i_dsrl_safe(p, ptr, ptr, 19); -# else - /* - * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 - * stored in CONTEXT. - */ - uasm_i_dmfc0(p, ptr, C0_CONTEXT); - uasm_i_dsrl_safe(p, ptr, ptr, 23); -# endif + UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); + uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); UASM_i_LA_mostly(p, tmp, pgdc); uasm_i_daddu(p, ptr, ptr, tmp); uasm_i_dmfc0(p, tmp, C0_BADVADDR); @@ -954,21 +922,9 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC uses TCBind value as "CPU" index - */ - uasm_i_mfc0(p, ptr, C0_TCBIND); + uasm_i_mfc0(p, ptr, SMP_CPUID_REG); UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 19); -#else - /* - * smp_processor_id() << 2 is stored in CONTEXT. - */ - uasm_i_mfc0(p, ptr, C0_CONTEXT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, 23); -#endif + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); uasm_i_addu(p, ptr, tmp, ptr); #else UASM_i_LA_mostly(p, ptr, pgdc); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-08-11 11:40 [PATCH 0/2] Use scratch register for PGD when MIPS_PGD_C0_CONTEXT is not set Jayachandran C 2013-08-11 11:40 ` [PATCH 1/2] MIPS: Move definition of SMP processor id register to header file Jayachandran C @ 2013-08-11 11:40 ` Jayachandran C 2013-09-17 21:21 ` Ralf Baechle 2013-09-24 21:49 ` Hauke Mehrtens 1 sibling, 2 replies; 9+ messages in thread From: Jayachandran C @ 2013-08-11 11:40 UTC (permalink / raw) To: ralf, linux-mips; +Cc: Jayachandran C Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD. This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> --- arch/mips/include/asm/mmu_context.h | 6 +-- arch/mips/mm/tlbex.c | 88 +++++++++++++++++++++++------------ 2 files changed, 58 insertions(+), 36 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index ab8e260..e277bba 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -24,14 +24,13 @@ #endif /* SMTC */ #include <asm-generic/mm_hooks.h> -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ do { \ extern void tlbmiss_handler_setup_pgd(unsigned long); \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ } while (0) +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ @@ -48,9 +47,6 @@ do { \ */ extern unsigned long pgd_current[]; -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) - #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << \ SMP_CPUID_REGSHIFT); \ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 54f3270..40efded 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -796,11 +796,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, } /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); } else { +#if defined(CONFIG_MIPS_PGD_C0_CONTEXT) /* * &pgd << 11 stored in CONTEXT [23..63]. */ @@ -812,18 +812,18 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* 1 0 1 0 1 << 6 xkphys cached */ uasm_i_ori(p, ptr, ptr, 0x540); uasm_i_drotr(p, ptr, ptr, 11); - } #elif defined(CONFIG_SMP) - UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); - uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_daddu(p, ptr, ptr, tmp); - uasm_i_dmfc0(p, tmp, C0_BADVADDR); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); + uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_daddu(p, ptr, ptr, tmp); + uasm_i_dmfc0(p, tmp, C0_BADVADDR); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_LA_mostly(p, ptr, pgdc); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #endif + } uasm_l_vmalloc_done(l, *p); @@ -918,19 +918,25 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, static void __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { - long pgdc = (long)pgd_current; + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + } else { + long pgdc = (long)pgd_current; - /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP - uasm_i_mfc0(p, ptr, SMP_CPUID_REG); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); - uasm_i_addu(p, ptr, tmp, ptr); + uasm_i_mfc0(p, ptr, SMP_CPUID_REG); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + uasm_i_addu(p, ptr, tmp, ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); + UASM_i_LA_mostly(p, ptr, pgdc); #endif - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ - uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); + } uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1404,28 +1410,30 @@ static void build_r4000_tlb_refill_handler(void) extern u32 handle_tlbl[], handle_tlbl_end[]; extern u32 handle_tlbs[], handle_tlbs_end[]; extern u32 handle_tlbm[], handle_tlbm_end[]; - -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; -static void build_r4000_setup_pgd(void) +static void build_setup_pgd(void) { const int a0 = 4; - const int a1 = 5; + const int __maybe_unused a1 = 5; + const int __maybe_unused a2 = 6; u32 *p = tlbmiss_handler_setup_pgd; const int tlbmiss_handler_setup_pgd_size = tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; - struct uasm_label *l = labels; - struct uasm_reloc *r = relocs; +#ifndef CONFIG_MIPS_PGD_C0_CONTEXT + long pgdc = (long)pgd_current; +#endif memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * sizeof(tlbmiss_handler_setup_pgd[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); - pgd_reg = allocate_kscratch(); - +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg == -1) { + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + /* PGD << 11 in c0_Context */ /* * If it is a ckseg0 address, convert to a physical @@ -1447,6 +1455,26 @@ static void build_r4000_setup_pgd(void) uasm_i_jr(&p, 31); UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); } +#else +#ifdef CONFIG_SMP + /* Save PGD to pgd_current[smp_processor_id()] */ + UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); + UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_ADDU(&p, a2, a2, a1); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#else + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); +#endif /* SMP */ + uasm_i_jr(&p, 31); + + /* if pgd_reg is allocated, save PGD also to scratch register */ + if (pgd_reg != -1) + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); + else + uasm_i_nop(&p); +#endif if (p >= tlbmiss_handler_setup_pgd_end) panic("tlbmiss_handler_setup_pgd space exceeded"); @@ -1457,7 +1485,6 @@ static void build_r4000_setup_pgd(void) dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, tlbmiss_handler_setup_pgd_size); } -#endif static void iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -2185,6 +2212,7 @@ void build_tlb_refill_handler(void) if (!run_once) { if (!cpu_has_local_ebase) build_r3000_tlb_refill_handler(); + build_setup_pgd(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2208,9 +2236,7 @@ void build_tlb_refill_handler(void) default: if (!run_once) { scratch_reg = allocate_kscratch(); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - build_r4000_setup_pgd(); -#endif + build_setup_pgd(); build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-08-11 11:40 ` [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Jayachandran C @ 2013-09-17 21:21 ` Ralf Baechle 2013-09-18 7:59 ` Jayachandran C. 2013-09-24 21:49 ` Hauke Mehrtens 1 sibling, 1 reply; 9+ messages in thread From: Ralf Baechle @ 2013-09-17 21:21 UTC (permalink / raw) To: Jayachandran C; +Cc: linux-mips On Sun, Aug 11, 2013 at 05:10:17PM +0530, Jayachandran C wrote: > Allow usage of scratch register for current pgd even when > MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set > for 64r2 platforms to indicate availability of Xcontext for saving > cpuid, thus freeing Context to be used for saving PGD. This option > was also tied to using a scratch register for storing PGD. > > This commit will allow usage of scratch register to store the current > pgd if one can be allocated for the platform, even when > MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 > Context register in this case. > > The code to store the current pgd for the TLB miss handler is now > generated in all cases. When scratch register is available, the PGD > is also stored in the scratch register. This patch breaks the build for almost all platforms. Amusingly it doesn't break Cavium however which is why I didn't notice it right away. The build error is the same for all platforms: [...] LD init/built-in.o arch/mips/built-in.o: In function `per_cpu_trap_init': (.text+0x80e4): undefined reference to `tlbmiss_handler_setup_pgd' arch/mips/built-in.o: In function `build_setup_pgd': tlbex.c:(.text+0xe31c): undefined reference to `tlbmiss_handler_setup_pgd' tlbex.c:(.text+0xe328): undefined reference to `tlbmiss_handler_setup_pgd' tlbex.c:(.text+0xe324): undefined reference to `tlbmiss_handler_setup_pgd_end' tlbex.c:(.text+0xe32c): undefined reference to `tlbmiss_handler_setup_pgd_end' kernel/built-in.o: In function `__schedule': core.c:(.sched.text+0x1b74): undefined reference to `tlbmiss_handler_setup_pgd' mm/built-in.o: In function `use_mm': (.text+0x1a530): undefined reference to `tlbmiss_handler_setup_pgd' fs/built-in.o: In function `flush_old_exec': (.text+0x8da8): undefined reference to `tlbmiss_handler_setup_pgd' make[2]: *** [vmlinux] Error 1 make[1]: *** [sub-make] Error 2 make: *** [all] Error 2 make: Leaving directory `/home/ralf/src/linux/obj/cobalt-build' I'm reverting the patch now. Ralf ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-09-17 21:21 ` Ralf Baechle @ 2013-09-18 7:59 ` Jayachandran C. 2013-09-18 11:02 ` Ralf Baechle 0 siblings, 1 reply; 9+ messages in thread From: Jayachandran C. @ 2013-09-18 7:59 UTC (permalink / raw) To: Ralf Baechle; +Cc: linux-mips On Tue, Sep 17, 2013 at 11:21:13PM +0200, Ralf Baechle wrote: > On Sun, Aug 11, 2013 at 05:10:17PM +0530, Jayachandran C wrote: > > > Allow usage of scratch register for current pgd even when > > MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set > > for 64r2 platforms to indicate availability of Xcontext for saving > > cpuid, thus freeing Context to be used for saving PGD. This option > > was also tied to using a scratch register for storing PGD. > > > > This commit will allow usage of scratch register to store the current > > pgd if one can be allocated for the platform, even when > > MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 > > Context register in this case. > > > > The code to store the current pgd for the TLB miss handler is now > > generated in all cases. When scratch register is available, the PGD > > is also stored in the scratch register. > > This patch breaks the build for almost all platforms. Amusingly it > doesn't break Cavium however which is why I didn't notice it right away. > > The build error is the same for all platforms: > > [...] > LD init/built-in.o > arch/mips/built-in.o: In function `per_cpu_trap_init': > (.text+0x80e4): undefined reference to `tlbmiss_handler_setup_pgd' > arch/mips/built-in.o: In function `build_setup_pgd': > tlbex.c:(.text+0xe31c): undefined reference to `tlbmiss_handler_setup_pgd' > tlbex.c:(.text+0xe328): undefined reference to `tlbmiss_handler_setup_pgd' > tlbex.c:(.text+0xe324): undefined reference to `tlbmiss_handler_setup_pgd_end' > tlbex.c:(.text+0xe32c): undefined reference to `tlbmiss_handler_setup_pgd_end' > kernel/built-in.o: In function `__schedule': > core.c:(.sched.text+0x1b74): undefined reference to `tlbmiss_handler_setup_pgd' > mm/built-in.o: In function `use_mm': > (.text+0x1a530): undefined reference to `tlbmiss_handler_setup_pgd' > fs/built-in.o: In function `flush_old_exec': > (.text+0x8da8): undefined reference to `tlbmiss_handler_setup_pgd' > make[2]: *** [vmlinux] Error 1 > make[1]: *** [sub-make] Error 2 > make: *** [all] Error 2 > make: Leaving directory `/home/ralf/src/linux/obj/cobalt-build' > > I'm reverting the patch now. The commit 774b6175 "MIPS: tlbex: Guard tlbmiss_handler_setup_pgd" that went into 3.12-rc1 takes out tlbmiss_handler_setup_pgd definition when CONFIG_MIPS_PGD_C0_CONTEXT is not defined. That clashes with this change and caused the failure. You can revert 774b6175 before applying this and things should work, I had tested it with qemu on malta as well as on XLP. JC. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-09-18 7:59 ` Jayachandran C. @ 2013-09-18 11:02 ` Ralf Baechle 0 siblings, 0 replies; 9+ messages in thread From: Ralf Baechle @ 2013-09-18 11:02 UTC (permalink / raw) To: Jayachandran C.; +Cc: linux-mips On Wed, Sep 18, 2013 at 01:29:41PM +0530, Jayachandran C. wrote: > The commit 774b6175 "MIPS: tlbex: Guard tlbmiss_handler_setup_pgd" that > went into 3.12-rc1 takes out tlbmiss_handler_setup_pgd definition when > CONFIG_MIPS_PGD_C0_CONTEXT is not defined. That clashes with this change > and caused the failure. > > You can revert 774b6175 before applying this and things should work, I > had tested it with qemu on malta as well as on XLP. Done. Thanks! Ralf ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-08-11 11:40 ` [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Jayachandran C 2013-09-17 21:21 ` Ralf Baechle @ 2013-09-24 21:49 ` Hauke Mehrtens 2013-09-25 5:26 ` Jayachandran C. 1 sibling, 1 reply; 9+ messages in thread From: Hauke Mehrtens @ 2013-09-24 21:49 UTC (permalink / raw) To: Jayachandran C, ralf, linux-mips On 08/11/2013 01:40 PM, Jayachandran C wrote: > Allow usage of scratch register for current pgd even when > MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set > for 64r2 platforms to indicate availability of Xcontext for saving > cpuid, thus freeing Context to be used for saving PGD. This option > was also tied to using a scratch register for storing PGD. > > This commit will allow usage of scratch register to store the current > pgd if one can be allocated for the platform, even when > MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 > Context register in this case. > > The code to store the current pgd for the TLB miss handler is now > generated in all cases. When scratch register is available, the PGD > is also stored in the scratch register. > > Signed-off-by: Jayachandran C <jchandra@broadcom.com> This patch breaks booting for me on bcm47xx. I found this commit by bisecting and then reverted it and it made bcm47xx boot again. The boot process stops after: [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) The next message would be: [ 0.000000] Writing ErrCtl register=00000000 This issue was seen on bcm4716. This is the boot log: CFE> boot -tftp -elf 192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf Loader:elf Filesys:tftp Dev:eth0 File:192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf Options:(null) Loading: 0x80001000/4593328 0x804626b0/279760 Entry at 0x80264800 Closing network. Starting program at 0x80264800 [ 0.000000] Linux version 3.12.0-rc1+ (hauke@hauke-desktop) (gcc version 4.6.4 (OpenWrt/Linaro GCC 4.6-2013.05 r37948) ) #151 Tue Sep 24 23:35:35 CEST 2013 [ 0.000000] bootconsole [early0] enabled [ 0.000000] CPU revision is: 00019740 (MIPS 74Kc) [ 0.000000] bcm47xx: using bcma bus [ 0.000000] bcma: bus0: Found chip with id 0x4716, rev 0x01 and package 0x0A [ 0.000000] bcma: bus0: Core 0 found: ChipCommon (manuf 0x4BF, id 0x800, rev 0x1F, class 0x0) [ 0.000000] bcma: bus0: Core 3 found: MIPS 74K (manuf 0x4A7, id 0x82C, rev 0x01, class 0x0) [ 0.000000] bcma: bus0: Found M25P64 serial flash (size: 8192KiB, blocksize: 0x10000, blocks: 128) [ 0.000000] bcma: bus0: Early bus registered [ 0.000000] MIPS: machine is Netgear WNDR3400 V1 [ 0.000000] Determined physical RAM map: [ 0.000000] memory: 04000000 @ 00000000 (usable) [ 0.000000] Initrd not found or empty - disabling initrd [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x00000000-0x03ffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x00000000-0x03ffffff] [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256 [ 0.000000] Kernel command line: noinitrd console=ttyS0,115200 [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-09-24 21:49 ` Hauke Mehrtens @ 2013-09-25 5:26 ` Jayachandran C. 2013-09-25 8:25 ` Hauke Mehrtens 0 siblings, 1 reply; 9+ messages in thread From: Jayachandran C. @ 2013-09-25 5:26 UTC (permalink / raw) To: Hauke Mehrtens; +Cc: ralf, linux-mips [-- Attachment #1: Type: text/plain, Size: 3566 bytes --] On Tue, Sep 24, 2013 at 11:49:43PM +0200, Hauke Mehrtens wrote: > On 08/11/2013 01:40 PM, Jayachandran C wrote: > > Allow usage of scratch register for current pgd even when > > MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set > > for 64r2 platforms to indicate availability of Xcontext for saving > > cpuid, thus freeing Context to be used for saving PGD. This option > > was also tied to using a scratch register for storing PGD. > > > > This commit will allow usage of scratch register to store the current > > pgd if one can be allocated for the platform, even when > > MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 > > Context register in this case. > > > > The code to store the current pgd for the TLB miss handler is now > > generated in all cases. When scratch register is available, the PGD > > is also stored in the scratch register. > > > > Signed-off-by: Jayachandran C <jchandra@broadcom.com> > > This patch breaks booting for me on bcm47xx. I found this commit by > bisecting and then reverted it and it made bcm47xx boot again. The boot > process stops after: [ 0.000000] Inode-cache hash table entries: 4096 > (order: 2, 16384 bytes) > > The next message would be: [ 0.000000] Writing ErrCtl register=00000000 > > This issue was seen on bcm4716. > > This is the boot log: > > CFE> boot -tftp -elf > 192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf > Loader:elf Filesys:tftp Dev:eth0 > File:192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf > Options:(null) > Loading: 0x80001000/4593328 0x804626b0/279760 Entry at 0x80264800 > Closing network. > Starting program at 0x80264800 > [ 0.000000] Linux version 3.12.0-rc1+ (hauke@hauke-desktop) (gcc > version 4.6.4 (OpenWrt/Linaro GCC 4.6-2013.05 r37948) ) #151 Tue Sep 24 > 23:35:35 CEST 2013 > [ 0.000000] bootconsole [early0] enabled > [ 0.000000] CPU revision is: 00019740 (MIPS 74Kc) > [ 0.000000] bcm47xx: using bcma bus > [ 0.000000] bcma: bus0: Found chip with id 0x4716, rev 0x01 and > package 0x0A > [ 0.000000] bcma: bus0: Core 0 found: ChipCommon (manuf 0x4BF, id > 0x800, rev 0x1F, class 0x0) > [ 0.000000] bcma: bus0: Core 3 found: MIPS 74K (manuf 0x4A7, id > 0x82C, rev 0x01, class 0x0) > [ 0.000000] bcma: bus0: Found M25P64 serial flash (size: 8192KiB, > blocksize: 0x10000, blocks: 128) > [ 0.000000] bcma: bus0: Early bus registered > [ 0.000000] MIPS: machine is Netgear WNDR3400 V1 > [ 0.000000] Determined physical RAM map: > [ 0.000000] memory: 04000000 @ 00000000 (usable) > [ 0.000000] Initrd not found or empty - disabling initrd > [ 0.000000] Zone ranges: > [ 0.000000] Normal [mem 0x00000000-0x03ffffff] > [ 0.000000] Movable zone start for each node > [ 0.000000] Early memory node ranges > [ 0.000000] node 0: [mem 0x00000000-0x03ffffff] > [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 > bytes. > [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, > linesize 32 bytes > [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. > Total pages: 16256 > [ 0.000000] Kernel command line: noinitrd console=ttyS0,115200 > [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) > [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) > [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Can you please try the attached patch? This patch was made for a slightly older tlbex.c, and seems to have missed this. Thanks, JC. [-- Attachment #2: flush-fix.patch --] [-- Type: text/plain, Size: 544 bytes --] diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 73d17f4..fffa7fe 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2180,10 +2180,8 @@ static void flush_tlb_handlers(void) (unsigned long)handle_tlbs_end); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm_end); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, (unsigned long)tlbmiss_handler_setup_pgd_end); -#endif } void build_tlb_refill_handler(void) ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT 2013-09-25 5:26 ` Jayachandran C. @ 2013-09-25 8:25 ` Hauke Mehrtens 0 siblings, 0 replies; 9+ messages in thread From: Hauke Mehrtens @ 2013-09-25 8:25 UTC (permalink / raw) To: Jayachandran C.; +Cc: ralf, linux-mips On 09/25/2013 07:26 AM, Jayachandran C. wrote: > On Tue, Sep 24, 2013 at 11:49:43PM +0200, Hauke Mehrtens wrote: >> On 08/11/2013 01:40 PM, Jayachandran C wrote: >>> Allow usage of scratch register for current pgd even when >>> MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set >>> for 64r2 platforms to indicate availability of Xcontext for saving >>> cpuid, thus freeing Context to be used for saving PGD. This option >>> was also tied to using a scratch register for storing PGD. >>> >>> This commit will allow usage of scratch register to store the current >>> pgd if one can be allocated for the platform, even when >>> MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 >>> Context register in this case. >>> >>> The code to store the current pgd for the TLB miss handler is now >>> generated in all cases. When scratch register is available, the PGD >>> is also stored in the scratch register. >>> >>> Signed-off-by: Jayachandran C <jchandra@broadcom.com> >> >> This patch breaks booting for me on bcm47xx. I found this commit by >> bisecting and then reverted it and it made bcm47xx boot again. The boot >> process stops after: [ 0.000000] Inode-cache hash table entries: 4096 >> (order: 2, 16384 bytes) >> >> The next message would be: [ 0.000000] Writing ErrCtl register=00000000 >> >> This issue was seen on bcm4716. >> >> This is the boot log: >> >> CFE> boot -tftp -elf >> 192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf >> Loader:elf Filesys:tftp Dev:eth0 >> File:192.168.1.195:/brcm47xx/openwrt-brcm47xx-vmlinux-initramfs.elf >> Options:(null) >> Loading: 0x80001000/4593328 0x804626b0/279760 Entry at 0x80264800 >> Closing network. >> Starting program at 0x80264800 >> [ 0.000000] Linux version 3.12.0-rc1+ (hauke@hauke-desktop) (gcc >> version 4.6.4 (OpenWrt/Linaro GCC 4.6-2013.05 r37948) ) #151 Tue Sep 24 >> 23:35:35 CEST 2013 >> [ 0.000000] bootconsole [early0] enabled >> [ 0.000000] CPU revision is: 00019740 (MIPS 74Kc) >> [ 0.000000] bcm47xx: using bcma bus >> [ 0.000000] bcma: bus0: Found chip with id 0x4716, rev 0x01 and >> package 0x0A >> [ 0.000000] bcma: bus0: Core 0 found: ChipCommon (manuf 0x4BF, id >> 0x800, rev 0x1F, class 0x0) >> [ 0.000000] bcma: bus0: Core 3 found: MIPS 74K (manuf 0x4A7, id >> 0x82C, rev 0x01, class 0x0) >> [ 0.000000] bcma: bus0: Found M25P64 serial flash (size: 8192KiB, >> blocksize: 0x10000, blocks: 128) >> [ 0.000000] bcma: bus0: Early bus registered >> [ 0.000000] MIPS: machine is Netgear WNDR3400 V1 >> [ 0.000000] Determined physical RAM map: >> [ 0.000000] memory: 04000000 @ 00000000 (usable) >> [ 0.000000] Initrd not found or empty - disabling initrd >> [ 0.000000] Zone ranges: >> [ 0.000000] Normal [mem 0x00000000-0x03ffffff] >> [ 0.000000] Movable zone start for each node >> [ 0.000000] Early memory node ranges >> [ 0.000000] node 0: [mem 0x00000000-0x03ffffff] >> [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 >> bytes. >> [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, >> linesize 32 bytes >> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. >> Total pages: 16256 >> [ 0.000000] Kernel command line: noinitrd console=ttyS0,115200 >> [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) >> [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) >> [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) > > Can you please try the attached patch? This patch was made for a slightly > older tlbex.c, and seems to have missed this. Thanks, this patch fixes my problem, could you please summit it for inclusion in upstream-sfr. Hauke ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-09-25 8:25 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-08-11 11:40 [PATCH 0/2] Use scratch register for PGD when MIPS_PGD_C0_CONTEXT is not set Jayachandran C 2013-08-11 11:40 ` [PATCH 1/2] MIPS: Move definition of SMP processor id register to header file Jayachandran C 2013-08-11 11:40 ` [PATCH 2/2] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT Jayachandran C 2013-09-17 21:21 ` Ralf Baechle 2013-09-18 7:59 ` Jayachandran C. 2013-09-18 11:02 ` Ralf Baechle 2013-09-24 21:49 ` Hauke Mehrtens 2013-09-25 5:26 ` Jayachandran C. 2013-09-25 8:25 ` Hauke Mehrtens
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