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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 15/16] drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums
Date: Wed,  9 Oct 2013 19:18:09 +0300	[thread overview]
Message-ID: <1381335490-4906-16-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1381335490-4906-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Makes the intention more clear.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 022cd5b..7b52e39 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2371,11 +2371,11 @@ static unsigned int ilk_fbc_wm_max(void)
 	return 15;
 }
 
-static void ilk_wm_max(struct drm_device *dev,
-		       int level,
-		       const struct intel_wm_config *config,
-		       enum intel_ddb_partitioning ddb_partitioning,
-		       struct hsw_wm_maximums *max)
+static void ilk_compute_wm_maximums(struct drm_device *dev,
+				    int level,
+				    const struct intel_wm_config *config,
+				    enum intel_ddb_partitioning ddb_partitioning,
+				    struct hsw_wm_maximums *max)
 {
 	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
 	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
@@ -2626,7 +2626,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
 	struct hsw_wm_maximums max;
 
 	/* LP0 watermarks always use 1/2 DDB partitioning */
-	ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
+	ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
 
 	for (level = 0; level <= max_level; level++)
 		ilk_compute_wm_level(dev_priv, level, params,
@@ -2954,12 +2954,12 @@ static void haswell_update_wm(struct drm_crtc *crtc)
 
 	intel_crtc->wm.active = pipe_wm;
 
-	ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
+	ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
 	ilk_wm_merge(dev, &max, &lp_wm_1_2);
 
 	/* 5/6 split only in single pipe config on IVB+ */
 	if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) {
-		ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
+		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev, &max, &lp_wm_5_6);
 
 		best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
-- 
1.8.1.5

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  parent reply	other threads:[~2013-10-09 16:19 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-09 16:17 [PATCH 00/16] drm/i915: More HSW watermark prep work v2 ville.syrjala
2013-10-09 16:17 ` [PATCH v2 01/16] drm/i915: Add intel_pipe_wm and prepare for watermark pre-compute ville.syrjala
2013-10-10 21:43   ` Paulo Zanoni
2013-10-11  8:07     ` Ville Syrjälä
2013-10-11 13:51       ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 02/16] drm/i915: Don't re-compute pipe watermarks except for the affected pipe ville.syrjala
2013-10-10 21:57   ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 03/16] drm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results() ville.syrjala
2013-10-10 22:04   ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 04/16] drm/i915: Use intel_pipe_wm in hsw_find_best_results ville.syrjala
2013-10-10 22:20   ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 05/16] drm/i915: Move some computations out from hsw_compute_wm_parameters() ville.syrjala
2013-10-10 22:34   ` Paulo Zanoni
2013-10-11  8:26     ` Ville Syrjälä
2013-10-11 12:26       ` [PATCH 17/16] drm/i915: Check 5/6 DDB split only when sprites are enabled ville.syrjala
2013-10-11 17:21         ` Paulo Zanoni
2013-10-11 13:53       ` [PATCH 05/16] drm/i915: Move some computations out from hsw_compute_wm_parameters() Paulo Zanoni
2013-10-09 16:18 ` [PATCH 06/16] drm/i915: Don't compute 5/6 DDB split w/ zero active pipes ville.syrjala
2013-10-10 22:38   ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 07/16] drm/i915: Refactor wm_lp to level calculation ville.syrjala
2013-10-10 22:42   ` Paulo Zanoni
2013-10-11  8:10     ` Ville Syrjälä
2013-10-09 16:18 ` [PATCH 08/16] drm/i915: Kill fbc_wm_enabled from intel_wm_config ville.syrjala
2013-10-10 22:45   ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 09/16] drm/i915: Store current watermark state in dev_priv->wm ville.syrjala
2013-10-11 14:21   ` Paulo Zanoni
2013-10-15  8:24     ` Daniel Vetter
2013-10-15 16:49       ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 10/16] drm/i915: Improve watermark dirtyness checks ville.syrjala
2013-10-11 15:02   ` Paulo Zanoni
2013-10-11 15:48     ` Ville Syrjälä
2013-10-11 16:12       ` Paulo Zanoni
2013-10-11 16:39         ` [PATCH v2 " ville.syrjala
2013-10-11 17:57           ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 11/16] drm/i915: Init HSW watermark tracking in intel_modeset_setup_hw_state() ville.syrjala
2013-10-11 16:45   ` Paulo Zanoni
2013-10-11 17:15     ` Ville Syrjälä
2013-10-11 18:15       ` Paulo Zanoni
2013-10-11 19:12         ` Ville Syrjälä
2013-10-11 19:46           ` Paulo Zanoni
2013-10-14 11:21             ` Ville Syrjälä
2013-10-14 11:55     ` [PATCH v2 " ville.syrjala
2013-10-14 13:56       ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 12/16] drm/i915: Remove a somewhat silly debug print from watermark code ville.syrjala
2013-10-11 16:48   ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH v2 13/16] drm/i915: Adjust watermark register masks ville.syrjala
2013-10-11 17:02   ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 14/16] drm/i915: Add watermark tracepoints ville.syrjala
2013-10-11 19:40   ` Paulo Zanoni
2013-10-15  8:43     ` Daniel Vetter
2013-10-15 10:11       ` Ville Syrjälä
2013-10-15 10:59         ` Daniel Vetter
2013-10-09 16:18 ` ville.syrjala [this message]
2013-10-11 17:07   ` [PATCH 15/16] drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums Paulo Zanoni
2013-10-09 16:18 ` [PATCH 16/16] drm/i915: Rename ilk_check_wm to ilk_validate_wm_level ville.syrjala
2013-10-11 17:08   ` Paulo Zanoni
2013-10-15  9:16     ` Daniel Vetter
2013-10-15 17:01       ` Paulo Zanoni
2013-10-15 17:46         ` Ville Syrjälä

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