[U-Boot] TI xHCI updates

[U-Boot] TI xHCI updates

[Dan Murphy]

This patch series contains the following changes

- Moves the xhci-omap.h to a common location
- Fixes a compilation issue on OMAP5 when xHCI is defined when patch
"usb: new board-specific USB init interface" is applied
- Moves the TI USB PHY code out of the xhci-omap.c file and into
a new file called drivers/usb/phy/omap_usb_phy.c
- Enables the dra7xx xHCI controller
- Enables the AM437x xHCI controller
- Move OMAP5 MAC creation out of USB and into misc_init so that usbethaddr is
set on each boot or else the kernel sets a random MAC.

[U-Boot] [PATCH 1/6] usb: omap: Move the xhci-omap header file to common location

[Dan Murphy]

Moving the xhci-omap header to a more global location so that
other code can reference this code.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 arch/arm/include/asm/arch-omap5/xhci-omap.h |  124 ---------------------------
 drivers/usb/host/xhci-omap.c                |    2 +-
 include/linux/usb/xhci-omap.h               |  124 +++++++++++++++++++++++++++
 3 files changed, 125 insertions(+), 125 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-omap5/xhci-omap.h
 create mode 100644 include/linux/usb/xhci-omap.h

diff --git a/arch/arm/include/asm/arch-omap5/xhci-omap.h b/arch/arm/include/asm/arch-omap5/xhci-omap.h
deleted file mode 100644
index b557a43..0000000
--- a/arch/arm/include/asm/arch-omap5/xhci-omap.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Inc, <www.ti.com>
- *
- * Author: Dan Murphy <dmurphy@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_XHCI_OMAP_H_
-#define _ASM_ARCH_XHCI_OMAP_H_
-
-#define OMAP_XHCI_BASE 0x4a030000
-#define OMAP_OCP1_SCP_BASE 0x4a084c00
-#define OMAP_OTG_WRAPPER_BASE 0x4A020000
-
-/* Phy register MACRO definitions */
-#define	PLL_REGM_MASK		0x001FFE00
-#define	PLL_REGM_SHIFT		0x9
-#define	PLL_REGM_F_MASK		0x0003FFFF
-#define	PLL_REGM_F_SHIFT	0x0
-#define	PLL_REGN_MASK		0x000001FE
-#define	PLL_REGN_SHIFT		0x1
-#define	PLL_SELFREQDCO_MASK	0x0000000E
-#define	PLL_SELFREQDCO_SHIFT	0x1
-#define	PLL_SD_MASK		0x0003FC00
-#define	PLL_SD_SHIFT		0x9
-#define	SET_PLL_GO		0x1
-#define	PLL_TICOPWDN		0x10000
-#define	PLL_LOCK		0x2
-#define	PLL_IDLE		0x1
-
-#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
-#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
-#define USB3_PHY_PARTIAL_RX_POWERON     (1 << 6)
-#define USB3_PHY_RX_POWERON		(1 << 14)
-#define USB3_PHY_TX_POWERON		(1 << 15)
-#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
-#define USB3_PWRCTL_CLK_CMD_SHIFT   14
-#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
-
-/* USBOTGSS_WRAPPER definitions */
-#define USBOTGSS_WRAPRESET	(1 << 17)
-#define USBOTGSS_DMADISABLE (1 << 16)
-#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
-#define USBOTGSS_STANDBYMODE_SMRT		(1 << 5)
-#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
-#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
-#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
-#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
-
-/* USBOTGSS_IRQENABLE_SET_0 bit */
-#define USBOTGSS_COREIRQ_EN	(1 << 0)
-
-/* USBOTGSS_IRQENABLE_SET_1 bits */
-#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
-#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	(1 << 3)
-#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	(1 << 4)
-#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	(1 << 5)
-#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	(1 << 8)
-#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	(1 << 11)
-#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	(1 << 12)
-#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	(1 << 13)
-#define USBOTGSS_IRQ_SET_1_OEVT_EN	(1 << 16)
-#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	(1 << 17)
-
-/*
- * USBOTGSS_WRAPPER registers
- */
-struct omap_dwc_wrapper {
-	u32 revision;
-
-	u32 reserve_1[3];
-
-	u32 sysconfig; /* offset of 0x10 */
-
-	u32 reserve_2[3];
-	u16 reserve_3;
-
-	u32 irqstatus_raw_0; /* offset of 0x24 */
-	u32 irqstatus_0;
-	u32 irqenable_set_0;
-	u32 irqenable_clr_0;
-
-	u32 irqstatus_raw_1; /* offset of 0x34 */
-	u32 irqstatus_1;
-	u32 irqenable_set_1;
-	u32 irqenable_clr_1;
-
-	u32 reserve_4[15];
-
-	u32 utmi_otg_ctrl; /* offset of 0x80 */
-	u32 utmi_otg_status;
-
-	u32 reserve_5[30];
-
-	u32 mram_offset; /* offset of 0x100 */
-	u32 fladj;
-	u32 dbg_config;
-	u32 dbg_data;
-	u32 dev_ebc_en;
-};
-
-/* XHCI PHY register structure */
-struct omap_usb3_phy {
-	u32 reserve1;
-	u32 pll_status;
-	u32 pll_go;
-	u32 pll_config_1;
-	u32 pll_config_2;
-	u32 pll_config_3;
-	u32 pll_ssc_config_1;
-	u32 pll_ssc_config_2;
-	u32 pll_config_4;
-};
-
-struct omap_xhci {
-	struct omap_dwc_wrapper *otg_wrapper;
-	struct omap_usb3_phy *usb3_phy;
-	struct xhci_hccr *hcd;
-	struct dwc3 *dwc3_reg;
-};
-
-#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index f4e41fd..a8702da 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -15,10 +15,10 @@
 #include <asm/omap_common.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/xhci-omap.h>
 
 #include <linux/compat.h>
 #include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
 
 #include "xhci.h"
 
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
new file mode 100644
index 0000000..b557a43
--- /dev/null
+++ b/include/linux/usb/xhci-omap.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Inc, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_OMAP_H_
+#define _ASM_ARCH_XHCI_OMAP_H_
+
+#define OMAP_XHCI_BASE 0x4a030000
+#define OMAP_OCP1_SCP_BASE 0x4a084c00
+#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+
+/* Phy register MACRO definitions */
+#define	PLL_REGM_MASK		0x001FFE00
+#define	PLL_REGM_SHIFT		0x9
+#define	PLL_REGM_F_MASK		0x0003FFFF
+#define	PLL_REGM_F_SHIFT	0x0
+#define	PLL_REGN_MASK		0x000001FE
+#define	PLL_REGN_SHIFT		0x1
+#define	PLL_SELFREQDCO_MASK	0x0000000E
+#define	PLL_SELFREQDCO_SHIFT	0x1
+#define	PLL_SD_MASK		0x0003FC00
+#define	PLL_SD_SHIFT		0x9
+#define	SET_PLL_GO		0x1
+#define	PLL_TICOPWDN		0x10000
+#define	PLL_LOCK		0x2
+#define	PLL_IDLE		0x1
+
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     (1 << 6)
+#define USB3_PHY_RX_POWERON		(1 << 14)
+#define USB3_PHY_TX_POWERON		(1 << 15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	(1 << 17)
+#define USBOTGSS_DMADISABLE (1 << 16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
+#define USBOTGSS_STANDBYMODE_SMRT		(1 << 5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
+#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	(1 << 0)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	(1 << 3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	(1 << 4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	(1 << 5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	(1 << 8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	(1 << 11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	(1 << 12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	(1 << 13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN	(1 << 16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	(1 << 17)
+
+/*
+ * USBOTGSS_WRAPPER registers
+ */
+struct omap_dwc_wrapper {
+	u32 revision;
+
+	u32 reserve_1[3];
+
+	u32 sysconfig; /* offset of 0x10 */
+
+	u32 reserve_2[3];
+	u16 reserve_3;
+
+	u32 irqstatus_raw_0; /* offset of 0x24 */
+	u32 irqstatus_0;
+	u32 irqenable_set_0;
+	u32 irqenable_clr_0;
+
+	u32 irqstatus_raw_1; /* offset of 0x34 */
+	u32 irqstatus_1;
+	u32 irqenable_set_1;
+	u32 irqenable_clr_1;
+
+	u32 reserve_4[15];
+
+	u32 utmi_otg_ctrl; /* offset of 0x80 */
+	u32 utmi_otg_status;
+
+	u32 reserve_5[30];
+
+	u32 mram_offset; /* offset of 0x100 */
+	u32 fladj;
+	u32 dbg_config;
+	u32 dbg_data;
+	u32 dev_ebc_en;
+};
+
+/* XHCI PHY register structure */
+struct omap_usb3_phy {
+	u32 reserve1;
+	u32 pll_status;
+	u32 pll_go;
+	u32 pll_config_1;
+	u32 pll_config_2;
+	u32 pll_config_3;
+	u32 pll_ssc_config_1;
+	u32 pll_ssc_config_2;
+	u32 pll_config_4;
+};
+
+struct omap_xhci {
+	struct omap_dwc_wrapper *otg_wrapper;
+	struct omap_usb3_phy *usb3_phy;
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
-- 
1.7.9.5

[U-Boot] [PATCH 2/6] usb: omap5: Change the board_usb_init api to board_xhci_usb_init

[Dan Murphy]

Recent patches declares board_usb_init function prototype for a new
usb architecture.

Turning on the OMAP_XHCI defines cause a redefinition compiler failure.
So rename the API from board_usb_init to board_xhci_usb_init.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 board/ti/omap5_uevm/evm.c    |    4 ++--
 drivers/usb/host/xhci-omap.c |    6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 228df29..e85afdc 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -214,12 +214,12 @@ void usb_hub_reset_devices(int port)
 
 #ifdef CONFIG_USB_XHCI_OMAP
 /**
- * @brief board_usb_init - Configure EVM board specific configurations
+ * @brief board_xhci_host_init - Configure EVM board specific configurations
  * for the LDO's and clocks for the USB blocks.
  *
  * @return 0
  */
-int board_usb_init(void)
+int board_xhci_host_init(void)
 {
 	int ret;
 #ifdef CONFIG_PALMAS_USB_SS_PWR
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index a8702da..0093e63 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -182,11 +182,11 @@ static void omap_enable_phy_clocks(struct omap_xhci *omap)
 
 };
 
-inline int __board_usb_init(void)
+inline int __board_xhci_host_init(void)
 {
 	return 0;
 }
-int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+int board_xhci_host_init(void) __attribute__((weak, alias("__board_xhci_host_init")));
 
 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
 {
@@ -295,7 +295,7 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
 	ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
 	ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
 
-	ret = board_usb_init();
+	ret = board_xhci_host_init();
 	if (ret != 0) {
 		puts("Failed to initialize board for USB\n");
 		return ret;
-- 
1.7.9.5

[U-Boot] [PATCH 3/6] usb: omap: Move the usb phy code to the usb/phy directory

[Dan Murphy]

Moving the usb/phy code from xhci-omap to the usb/phy directory
and moving the associated phy code over to the new file.

Newer TI processors adding xHCI support will have different PHY configurations
so therefore abstracting this code away will prevent messing around with the
xhci-omap file itself.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 drivers/usb/host/xhci-omap.c   |  171 +---------------------------------
 drivers/usb/phy/Makefile       |    1 +
 drivers/usb/phy/omap_usb_phy.c |  197 ++++++++++++++++++++++++++++++++++++++++
 include/linux/usb/xhci-omap.h  |    6 ++
 4 files changed, 206 insertions(+), 169 deletions(-)
 create mode 100644 drivers/usb/phy/omap_usb_phy.c

diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 0093e63..513b9d8 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -27,161 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct omap_xhci omap;
 
-struct usb_dpll_params {
-	u16	m;
-	u8	n;
-	u8	freq:3;
-	u8	sd;
-	u32	mf;
-};
-
-#define	NUM_USB_CLKS		6
-
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
-	{1250, 5, 4, 20, 0},		/* 12 MHz */
-	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
-	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
-	{1250, 12, 4, 20, 0},		/* 26 MHz */
-	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
-	{1000, 7, 4, 10, 0},        /* 20 MHz */
-};
-
-static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
-{
-	u32 val;
-
-	writel(SET_PLL_GO, &phy_regs->pll_go);
-	do {
-		val = readl(&phy_regs->pll_status);
-			if (val & PLL_LOCK)
-				break;
-	} while (1);
-}
-
-static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
-{
-	u32 clk_index = get_sys_clk_index();
-	u32 val;
-
-	val = readl(&phy_regs->pll_config_1);
-	val &= ~PLL_REGN_MASK;
-	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
-	writel(val, &phy_regs->pll_config_1);
-
-	val = readl(&phy_regs->pll_config_2);
-	val &= ~PLL_SELFREQDCO_MASK;
-	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
-	writel(val, &phy_regs->pll_config_2);
-
-	val = readl(&phy_regs->pll_config_1);
-	val &= ~PLL_REGM_MASK;
-	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
-	writel(val, &phy_regs->pll_config_1);
-
-	val = readl(&phy_regs->pll_config_4);
-	val &= ~PLL_REGM_F_MASK;
-	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
-	writel(val, &phy_regs->pll_config_4);
-
-	val = readl(&phy_regs->pll_config_3);
-	val &= ~PLL_SD_MASK;
-	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
-	writel(val, &phy_regs->pll_config_3);
-
-	omap_usb_dpll_relock(phy_regs);
-}
-
-static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
-{
-	u32 rate = get_sys_clk_freq()/1000000;
-	u32 val;
-
-	val = readl((*ctrl)->control_phy_power_usb);
-	val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
-	val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
-	val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
-
-	writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-static void usb3_phy_power(int on)
-{
-	u32 val;
-
-	val = readl((*ctrl)->control_phy_power_usb);
-	if (on) {
-		val &= ~USB3_PWRCTL_CLK_CMD_MASK;
-		val |= USB3_PHY_TX_RX_POWERON;
-	} else {
-		val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
-	}
-
-	writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
-{
-	omap_usb_dpll_lock(phy_regs);
-
-	usb3_phy_partial_powerup(phy_regs);
-	/*
-	 * Give enough time for the PHY to partially power-up before
-	 * powering it up completely. delay value suggested by the HW
-	 * team.
-	 */
-	mdelay(100);
-	usb3_phy_power(1);
-}
-
-static void omap_enable_phy_clocks(struct omap_xhci *omap)
-{
-	u32	val;
-
-	/* Setting OCP2SCP1 register */
-	setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
-		     OCP2SCP1_CLKCTRL_MODULEMODE_HW);
-
-	/* Turn on 32K AON clk */
-	setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
-		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-	/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
-	writel(0x0, (*prcm)->cm_l3init_clkstctrl);
-
-	val = (USBOTGSS_DMADISABLE |
-			USBOTGSS_STANDBYMODE_SMRT_WKUP |
-			USBOTGSS_IDLEMODE_NOIDLE);
-	writel(val, &omap->otg_wrapper->sysconfig);
-
-	/* Clear the utmi OTG status */
-	val = readl(&omap->otg_wrapper->utmi_otg_status);
-	writel(val, &omap->otg_wrapper->utmi_otg_status);
-
-	/* Enable interrupts */
-	writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
-	val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
-			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
-			USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	|
-			USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	|
-			USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	|
-			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	|
-			USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
-			USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
-			USBOTGSS_IRQ_SET_1_OEVT_EN);
-	writel(val, &omap->otg_wrapper->irqenable_set_1);
-
-	/* Clear the IRQ status */
-	val = readl(&omap->otg_wrapper->irqstatus_1);
-	writel(val, &omap->otg_wrapper->irqstatus_1);
-	val = readl(&omap->otg_wrapper->irqstatus_0);
-	writel(val, &omap->otg_wrapper->irqstatus_0);
-
-	/* Enable the USB OTG Super speed clocks */
-	val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
-
-};
-
 inline int __board_xhci_host_init(void)
 {
 	return 0;
@@ -200,19 +45,7 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
 	/* Before Resetting PHY, put Core in Reset */
 	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
 
-	/* Assert USB3 PHY reset */
-	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-	/* Assert USB2 PHY reset */
-	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-	mdelay(100);
-
-	/* Clear USB3 PHY reset */
-	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-	/* Clear USB2 PHY reset */
-	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+	omap_reset_usb_phy(dwc3_reg);
 
 	/* After PHYs are stable we can take Core out of reset state */
 	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
@@ -266,7 +99,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 
 	omap_enable_phy_clocks(omap);
 
-	dwc_usb3_phy_init(omap->usb3_phy);
+	omap_usb3_phy_init(omap->usb3_phy);
 
 	ret = dwc3_core_init(omap->dwc3_reg);
 	if (ret) {
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index f93121a..5beec78 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libusb_phy.o
 
 COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
+COBJS-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
new file mode 100644
index 0000000..ed727bf
--- /dev/null
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -0,0 +1,197 @@
+/*
+ * OMAP USB PHY Support
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "../host/xhci.h"
+
+struct usb_dpll_params {
+	u16	m;
+	u8	n;
+	u8	freq:3;
+	u8	sd;
+	u32	mf;
+};
+
+#define	NUM_USB_CLKS		6
+
+static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
+	{1250, 5, 4, 20, 0},		/* 12 MHz */
+	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
+	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
+	{1250, 12, 4, 20, 0},		/* 26 MHz */
+	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
+	{1000, 7, 4, 10, 0},        /* 20 MHz */
+};
+
+static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
+{
+	u32 val;
+
+	writel(SET_PLL_GO, &phy_regs->pll_go);
+	do {
+		val = readl(&phy_regs->pll_status);
+			if (val & PLL_LOCK)
+				break;
+	} while (1);
+}
+
+static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
+{
+	u32 clk_index = get_sys_clk_index();
+	u32 val;
+
+	val = readl(&phy_regs->pll_config_1);
+	val &= ~PLL_REGN_MASK;
+	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+	writel(val, &phy_regs->pll_config_1);
+
+	val = readl(&phy_regs->pll_config_2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+	writel(val, &phy_regs->pll_config_2);
+
+	val = readl(&phy_regs->pll_config_1);
+	val &= ~PLL_REGM_MASK;
+	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+	writel(val, &phy_regs->pll_config_1);
+
+	val = readl(&phy_regs->pll_config_4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+	writel(val, &phy_regs->pll_config_4);
+
+	val = readl(&phy_regs->pll_config_3);
+	val &= ~PLL_SD_MASK;
+	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+	writel(val, &phy_regs->pll_config_3);
+
+	omap_usb_dpll_relock(phy_regs);
+}
+
+static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
+{
+	u32 rate = get_sys_clk_freq()/1000000;
+	u32 val;
+
+	val = readl((*ctrl)->control_phy_power_usb);
+	val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
+	val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
+	val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
+
+	writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void usb3_phy_power(int on)
+{
+	u32 val;
+
+	val = readl((*ctrl)->control_phy_power_usb);
+	if (on) {
+		val &= ~USB3_PWRCTL_CLK_CMD_MASK;
+		val |= USB3_PHY_TX_RX_POWERON;
+	} else {
+		val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
+	}
+
+	writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
+{
+	omap_usb_dpll_lock(phy_regs);
+
+	usb3_phy_partial_powerup(phy_regs);
+	/*
+	 * Give enough time for the PHY to partially power-up before
+	 * powering it up completely. delay value suggested by the HW
+	 * team.
+	 */
+	mdelay(100);
+	usb3_phy_power(1);
+}
+
+void omap_enable_phy_clocks(struct omap_xhci *omap)
+{
+	u32	val;
+
+	/* Setting OCP2SCP1 register */
+	setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
+		     OCP2SCP1_CLKCTRL_MODULEMODE_HW);
+
+	/* Turn on 32K AON clk */
+	setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
+		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
+	writel(0x0, (*prcm)->cm_l3init_clkstctrl);
+
+	val = (USBOTGSS_DMADISABLE |
+			USBOTGSS_STANDBYMODE_SMRT_WKUP |
+			USBOTGSS_IDLEMODE_NOIDLE);
+	writel(val, &omap->otg_wrapper->sysconfig);
+
+	/* Clear the utmi OTG status */
+	val = readl(&omap->otg_wrapper->utmi_otg_status);
+	writel(val, &omap->otg_wrapper->utmi_otg_status);
+
+	/* Enable interrupts */
+	writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
+	val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
+			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
+			USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	|
+			USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	|
+			USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	|
+			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	|
+			USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
+			USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
+			USBOTGSS_IRQ_SET_1_OEVT_EN);
+	writel(val, &omap->otg_wrapper->irqenable_set_1);
+
+	/* Clear the IRQ status */
+	val = readl(&omap->otg_wrapper->irqstatus_1);
+	writel(val, &omap->otg_wrapper->irqstatus_1);
+	val = readl(&omap->otg_wrapper->irqstatus_0);
+	writel(val, &omap->otg_wrapper->irqstatus_0);
+
+	/* Enable the USB OTG Super speed clocks */
+	val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
+	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
+
+};
+
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
+{
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(100);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+}
+
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index b557a43..a73c0f9 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -121,4 +121,10 @@ struct omap_xhci {
 	struct dwc3 *dwc3_reg;
 };
 
+/* USB PHY functions */
+void omap_enable_phy_clocks(struct omap_xhci *omap);
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb3_phy_power(int on);
+
 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */
-- 
1.7.9.5

[U-Boot] [PATCH 4/6] usb: dra7xx: Add support for dra7xx xhci USB host

[Dan Murphy]

Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 arch/arm/cpu/armv7/omap5/prcm-regs.c    |    1 +
 arch/arm/include/asm/arch-omap5/clock.h |    4 +++
 arch/arm/include/asm/omap_common.h      |    1 +
 board/ti/dra7xx/evm.c                   |    6 -----
 board/ti/dra7xx/mux_data.h              |    1 +
 drivers/usb/host/xhci-omap.c            |    6 ++---
 drivers/usb/phy/omap_usb_phy.c          |   45 +++++++++++++++++++++++++++++--
 include/configs/dra7xx_evm.h            |   11 ++++++++
 include/linux/usb/xhci-omap.h           |   12 ++++++---
 9 files changed, 72 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b48c65c..85a65be 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -795,6 +795,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_dsp			= 0x4a005234,
 	.cm_shadow_freq_config1			= 0x4a005260,
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
+	.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
 
 	/* cm1.mpu */
 	.cm_mpu_mpu_clkctrl			= 0x4a005320,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 5cbbc44..8869b50 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -202,6 +202,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET	(1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_12_MPU	0x23
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index bea1835..8a395e8 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -144,6 +144,7 @@ struct prcm_regs {
 	u32 cm_ssc_deltamstep_dpll_unipro;
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy_core_clkctrl;
+	u32 cm_coreaon_usb_phy2_core_clkctrl;
 
 	/* cm2.core */
 	u32 cm_coreaon_bandgap_clkctrl;
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9a114e2..9657c75 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -17,12 +17,6 @@
 
 #include "mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
 #endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 6965cc5..38de9d5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -61,5 +61,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
 	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
 	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 513b9d8..5c85885 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -97,9 +97,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 {
 	int ret = 0;
 
-	omap_enable_phy_clocks(omap);
-
-	omap_usb3_phy_init(omap->usb3_phy);
+	omap_enable_phy(omap);
 
 	ret = dwc3_core_init(omap->dwc3_reg);
 	if (ret) {
@@ -115,7 +113,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 
 static void omap_xhci_core_exit(struct omap_xhci *omap)
 {
-	usb3_phy_power(0);
+	usb_phy_power(0);
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index ed727bf..f1da73d 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -22,6 +22,7 @@
 
 #include "../host/xhci.h"
 
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
 struct usb_dpll_params {
 	u16	m;
 	u8	n;
@@ -99,7 +100,7 @@ static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
 	writel(val, (*ctrl)->control_phy_power_usb);
 }
 
-void usb3_phy_power(int on)
+void usb_phy_power(int on)
 {
 	u32 val;
 
@@ -128,7 +129,7 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
 	usb3_phy_power(1);
 }
 
-void omap_enable_phy_clocks(struct omap_xhci *omap)
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
 {
 	u32	val;
 
@@ -176,6 +177,35 @@ void omap_enable_phy_clocks(struct omap_xhci *omap)
 	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
 
 };
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+	int reg, val;
+
+	val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+	writel(val, (*ctrl)->control_srcomp_north_side);
+
+	setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+			USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+					(USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+					 OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+	/* This is an undocumented Reserved register */
+	reg = 0x4a0086c0;
+	val = readl(reg);
+	val |= 0x100;
+	setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+	return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
 
 void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
 {
@@ -195,3 +225,14 @@ void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
 
 }
 
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+	omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+	omap_enable_usb3_phy(omap);
+	omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 51e0e80..b56ea1c 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -67,4 +67,15 @@
 #define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index a73c0f9..c3fcc03 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -10,9 +10,16 @@
 #ifndef _ASM_ARCH_XHCI_OMAP_H_
 #define _ASM_ARCH_XHCI_OMAP_H_
 
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#else
+/* Default to the OMAP5 XHCI defines */
 #define OMAP_XHCI_BASE 0x4a030000
 #define OMAP_OCP1_SCP_BASE 0x4a084c00
 #define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
 
 /* Phy register MACRO definitions */
 #define	PLL_REGM_MASK		0x001FFE00
@@ -122,9 +129,8 @@ struct omap_xhci {
 };
 
 /* USB PHY functions */
-void omap_enable_phy_clocks(struct omap_xhci *omap);
-void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
+void omap_enable_phy(struct omap_xhci *omap);
 void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
-void usb3_phy_power(int on);
+void usb_phy_power(int on);
 
 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */
-- 
1.7.9.5

[U-Boot] [PATCH 5/6] usb: am437x: Add support for am437x xhci USB host

[Dan Murphy]

Add the support for the am437x xhci usb host.

The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |   10 +++++++++
 drivers/usb/phy/omap_usb_phy.c                     |   23 ++++++++++++++++++++
 include/configs/am43xx_evm.h                       |   11 ++++++++++
 include/linux/usb/xhci-omap.h                      |    4 ++++
 4 files changed, 48 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 303c594..3b665e6 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -51,4 +51,14 @@
 /* RTC base address */
 #define RTC_BASE			0x44E3E000
 
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN	(1 << 2)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN	(1 << 2)
+
 #endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f1da73d..20c4805 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -207,6 +207,25 @@ void usb_phy_power(int on)
 }
 #endif /* CONFIG_OMAP_USB2PHY2_HOST */
 
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
+{
+	int usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
+				USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+
+	writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
+	writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
+
+	writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
+	writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
+}
+
+void usb_phy_power(int on)
+{
+	return;
+}
+#endif /* CONFIG_AM437X_USB2PHY2_HOST */
+
 void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
 {
 	/* Assert USB3 PHY reset */
@@ -231,6 +250,10 @@ void omap_enable_phy(struct omap_xhci *omap)
 	omap_enable_usb2_phy2(omap);
 #endif
 
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+	am437x_enable_usb2_phy2(omap);
+#endif
+
 #ifdef CONFIG_OMAP_USB3PHY1_HOST
 	omap_enable_usb3_phy(omap);
 	omap_usb3_phy_init(omap->usb3_phy);
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5c802a1..64c4811 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -24,6 +24,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT		"U-Boot# "
 #define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_CACHELINE_SIZE 32
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
@@ -132,4 +133,14 @@
 /* Unsupported features */
 #undef CONFIG_USE_IRQ
 
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
 #endif	/* __CONFIG_AM43XX_EVM_H */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index c3fcc03..82630ad 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -14,6 +14,10 @@
 #define OMAP_XHCI_BASE 0x488d0000
 #define OMAP_OCP1_SCP_BASE 0x4A081000
 #define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
 #else
 /* Default to the OMAP5 XHCI defines */
 #define OMAP_XHCI_BASE 0x4a030000
-- 
1.7.9.5

[U-Boot] [PATCH 6/6] ARM: omap5-evm: Move MAC creation to misc_init

[Dan Murphy]

Move the MAC creation from the USB init to an function
that is called on every boot.  This will then populate the
usbethaddr mac that kernel driver can pick up from the
device tree blob.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
 board/ti/omap5_uevm/evm.c |   39 ++++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index e85afdc..9d983ac 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -110,10 +110,30 @@ static void enable_host_clocks(void)
  */
 int misc_init_r(void)
 {
+	int reg;
+	uint8_t device_mac[6];
+
 #ifdef CONFIG_PALMAS_POWER
 	palmas_init_settings();
 #endif
 
+	if (!getenv("usbethaddr")) {
+		reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+		/*
+		 * create a fake MAC address from the processor ID code.
+		 * first byte is 0x02 to signify locally administered.
+		 */
+		device_mac[0] = 0x02;
+		device_mac[1] = readl(reg + 0x10) & 0xff;
+		device_mac[2] = readl(reg + 0xC) & 0xff;
+		device_mac[3] = readl(reg + 0x8) & 0xff;
+		device_mac[4] = readl(reg) & 0xff;
+		device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+		eth_setenv_enetaddr("usbethaddr", device_mac);
+	}
+
 	return 0;
 }
 
@@ -162,28 +182,9 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
-	int reg;
-	uint8_t device_mac[6];
 
 	enable_host_clocks();
 
-	if (!getenv("usbethaddr")) {
-		reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
-		/*
-		 * create a fake MAC address from the processor ID code.
-		 * first byte is 0x02 to signify locally administered.
-		 */
-		device_mac[0] = 0x02;
-		device_mac[1] = readl(reg + 0x10) & 0xff;
-		device_mac[2] = readl(reg + 0xC) & 0xff;
-		device_mac[3] = readl(reg + 0x8) & 0xff;
-		device_mac[4] = readl(reg) & 0xff;
-		device_mac[5] = (readl(reg) >> 8) & 0xff;
-
-		eth_setenv_enetaddr("usbethaddr", device_mac);
-	}
-
 	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 	if (ret < 0) {
 		puts("Failed to initialize ehci\n");
-- 
1.7.9.5

[U-Boot] TI xHCI updates

[Dan Murphy]

On 10/09/2013 12:19 PM, Dan Murphy wrote:
> This patch series contains the following changes
>
> - Moves the xhci-omap.h to a common location
> - Fixes a compilation issue on OMAP5 when xHCI is defined when patch
> "usb: new board-specific USB init interface" is applied
> - Moves the TI USB PHY code out of the xhci-omap.c file and into
> a new file called drivers/usb/phy/omap_usb_phy.c
> - Enables the dra7xx xHCI controller
> - Enables the AM437x xHCI controller
> - Move OMAP5 MAC creation out of USB and into misc_init so that usbethaddr is
> set on each boot or else the kernel sets a random MAC.
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Forgot to mention this patchset is based on top of the uBoot USB next branch.

Dan

-- 
------------------
Dan Murphy

[U-Boot] TI xHCI updates

[Jagan Teki]

Hi,

What is this are you manually created this.
please use --cover-letter on git format-patch

Will list down the patches on the cover letter and this will be PATCH 0/6

On Wed, Oct 9, 2013 at 10:51 PM, Dan Murphy <dmurphy@ti.com> wrote:
> On 10/09/2013 12:19 PM, Dan Murphy wrote:
>> This patch series contains the following changes
>>
>> - Moves the xhci-omap.h to a common location
>> - Fixes a compilation issue on OMAP5 when xHCI is defined when patch
>> "usb: new board-specific USB init interface" is applied
>> - Moves the TI USB PHY code out of the xhci-omap.c file and into
>> a new file called drivers/usb/phy/omap_usb_phy.c
>> - Enables the dra7xx xHCI controller
>> - Enables the AM437x xHCI controller
>> - Move OMAP5 MAC creation out of USB and into misc_init so that usbethaddr is
>> set on each boot or else the kernel sets a random MAC.
>>
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
> Forgot to mention this patchset is based on top of the uBoot USB next branch.
>
> Dan
>
> --
> ------------------
> Dan Murphy
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[U-Boot] [PATCH 1/6] usb: omap: Move the xhci-omap header file to common location

[Marek Vasut]

Dear Dan Murphy,

> Moving the xhci-omap header to a more global location so that
> other code can reference this code.
> 
> Signed-off-by: Dan Murphy <dmurphy@ti.com>

Is this just a simple move? Can you please repost with git format-patch -M ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/6] usb: omap5: Change the board_usb_init api to board_xhci_usb_init

[Marek Vasut]

Dear Dan Murphy,

> Recent patches declares board_usb_init function prototype for a new
> usb architecture.
> 
> Turning on the OMAP_XHCI defines cause a redefinition compiler failure.
> So rename the API from board_usb_init to board_xhci_usb_init.
> 
> Signed-off-by: Dan Murphy <dmurphy@ti.com>

Can you not use board_usb_init() ? I believe the whole point of the usb rework 
was to avoid having various names for the same function.

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/6] usb: omap: Move the usb phy code to the usb/phy directory

[Marek Vasut]

Dear Dan Murphy,

> Moving the usb/phy code from xhci-omap to the usb/phy directory
> and moving the associated phy code over to the new file.
> 
> Newer TI processors adding xHCI support will have different PHY
> configurations so therefore abstracting this code away will prevent
> messing around with the xhci-omap file itself.
> 
> Signed-off-by: Dan Murphy <dmurphy@ti.com>

git format-patch -M would help here greatly too.

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/6] usb: omap: Move the usb phy code to the usb/phy directory

[Dan Murphy]

Marek

On 10/09/2013 06:38 PM, Marek Vasut wrote:
> Dear Dan Murphy,
>
>> Moving the usb/phy code from xhci-omap to the usb/phy directory
>> and moving the associated phy code over to the new file.
>>
>> Newer TI processors adding xHCI support will have different PHY
>> configurations so therefore abstracting this code away will prevent
>> messing around with the xhci-omap file itself.
>>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> git format-patch -M would help here greatly too.
>
> Best regards,
> Marek Vasut

-M gives no love here.  It shows the same diff that I posted.

Even with an 80% delta.

Dan

-- 
------------------
Dan Murphy

[U-Boot] [PATCH 1/6] usb: omap: Move the xhci-omap header file to common location

[Dan Murphy]

Marek

On 10/09/2013 06:37 PM, Marek Vasut wrote:
> Dear Dan Murphy,
>
>> Moving the xhci-omap header to a more global location so that
>> other code can reference this code.
>>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> Is this just a simple move? Can you please repost with git format-patch -M ?
>
> Best regards,
> Marek Vasut

OK SGTM I think I like that switch on the format-patch command.  Will post V2 with that switch enabled.

Can you look at the other patches in case V2 needs other changes?

Dan

-- 
------------------
Dan Murphy

[U-Boot] [PATCH 2/6] usb: omap5: Change the board_usb_init api to board_xhci_usb_init

[Dan Murphy]

Marek

On 10/09/2013 06:38 PM, Marek Vasut wrote:
> Dear Dan Murphy,
>
>> Recent patches declares board_usb_init function prototype for a new
>> usb architecture.
>>
>> Turning on the OMAP_XHCI defines cause a redefinition compiler failure.
>> So rename the API from board_usb_init to board_xhci_usb_init.
>>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> Can you not use board_usb_init() ? I believe the whole point of the usb rework 
> was to avoid having various names for the same function.
>
> Best regards,
> Marek Vasut

I will post the change in V2.

Dan

-- 
------------------
Dan Murphy

[U-Boot] TI xHCI updates

[Dan Murphy]

Jagan
On 10/09/2013 12:26 PM, Jagan Teki wrote:
> Hi,
>
> What is this are you manually created this.
> please use --cover-letter on git format-patch
>
> Will list down the patches on the cover letter and this will be PATCH 0/6
>
> On Wed, Oct 9, 2013 at 10:51 PM, Dan Murphy <dmurphy@ti.com> wrote:
>> On 10/09/2013 12:19 PM, Dan Murphy wrote:
>>> This patch series contains the following changes
>>>
>>> - Moves the xhci-omap.h to a common location
>>> - Fixes a compilation issue on OMAP5 when xHCI is defined when patch
>>> "usb: new board-specific USB init interface" is applied
>>> - Moves the TI USB PHY code out of the xhci-omap.c file and into
>>> a new file called drivers/usb/phy/omap_usb_phy.c
>>> - Enables the dra7xx xHCI controller
>>> - Enables the AM437x xHCI controller
>>> - Move OMAP5 MAC creation out of USB and into misc_init so that usbethaddr is
>>> set on each boot or else the kernel sets a random MAC.
>>>
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>> Forgot to mention this patchset is based on top of the uBoot USB next branch.
>>
>> Dan
>>
>> --
>> ------------------
>> Dan Murphy
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>

Yes I manually created this

And please bottom post on replies as well.

Dan

-- 
------------------
Dan Murphy

[U-Boot] [PATCH 5/6] usb: am437x: Add support for am437x xhci USB host

[Marek Vasut]

Dear Dan Murphy,

> Add the support for the am437x xhci usb host.
> 
> The xHCI host on AM437 is connected to a usb2 phy so need to
> add support to enable those clocks.
> 
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
>  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |   10 +++++++++
>  drivers/usb/phy/omap_usb_phy.c                     |   23
> ++++++++++++++++++++ include/configs/am43xx_evm.h                       | 
>  11 ++++++++++ include/linux/usb/xhci-omap.h                      |    4
> ++++
>  4 files changed, 48 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
> b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index
> 303c594..3b665e6 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
> @@ -51,4 +51,14 @@
>  /* RTC base address */
>  #define RTC_BASE			0x44E3E000
> 
> +/* USB Clock Control */
> +#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
> +#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
> +#define USBOTGSSX_CLKCTRL_MODULE_EN	(1 << 2)
> +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
> +
> +#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
> +#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
> +#define USBPHYOCPSCP_MODULE_EN	(1 << 2)
> +
>  #endif /* __AM43XX_HARDWARE_AM43XX_H */
> diff --git a/drivers/usb/phy/omap_usb_phy.c
> b/drivers/usb/phy/omap_usb_phy.c index f1da73d..20c4805 100644
> --- a/drivers/usb/phy/omap_usb_phy.c
> +++ b/drivers/usb/phy/omap_usb_phy.c
> @@ -207,6 +207,25 @@ void usb_phy_power(int on)
>  }
>  #endif /* CONFIG_OMAP_USB2PHY2_HOST */
> 
> +#ifdef CONFIG_AM437X_USB2PHY2_HOST
> +static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
> +{
> +	int usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
> +				USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);

Other than that it should be "const", it should also be at least unsigned. And 
prefferably u32 .

Best regards,
Marek Vasut

[U-Boot] TI xHCI updates

[Marek Vasut]

Dear Jagan Teki,

> Hi,
> 
> What is this are you manually created this.
> please use --cover-letter on git format-patch
> 
> Will list down the patches on the cover letter and this will be PATCH 0/6
[..]

Just a nitpick, but please do not top-post in the MLs. Thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/6] usb: omap: Move the xhci-omap header file to common location

[Marek Vasut]

Dear Dan Murphy,

> Marek
> 
> On 10/09/2013 06:37 PM, Marek Vasut wrote:
> > Dear Dan Murphy,
> > 
> >> Moving the xhci-omap header to a more global location so that
> >> other code can reference this code.
> >> 
> >> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> > 
> > Is this just a simple move? Can you please repost with git format-patch
> > -M ?
> > 
> > Best regards,
> > Marek Vasut
> 
> OK SGTM I think I like that switch on the format-patch command.  Will post
> V2 with that switch enabled.
> 
> Can you look at the other patches in case V2 needs other changes?

Sure, done.

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/6] usb: omap: Move the usb phy code to the usb/phy directory

[Marek Vasut]

Dear Dan Murphy,

> Marek
> 
> On 10/09/2013 06:38 PM, Marek Vasut wrote:
> > Dear Dan Murphy,
> > 
> >> Moving the usb/phy code from xhci-omap to the usb/phy directory
> >> and moving the associated phy code over to the new file.
> >> 
> >> Newer TI processors adding xHCI support will have different PHY
> >> configurations so therefore abstracting this code away will prevent
> >> messing around with the xhci-omap file itself.
> >> 
> >> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> > 
> > git format-patch -M would help here greatly too.
> > 
> > Best regards,
> > Marek Vasut
> 
> -M gives no love here.  It shows the same diff that I posted.
> 
> Even with an 80% delta.

Aaaaaargh ... what about splitting it into two patches then ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 3/6] usb: omap: Move the usb phy code to the usb/phy directory

[Dan Murphy]

Marek

On 10/09/2013 07:35 PM, Marek Vasut wrote:
> Dear Dan Murphy,
>
>> Marek
>>
>> On 10/09/2013 06:38 PM, Marek Vasut wrote:
>>> Dear Dan Murphy,
>>>
>>>> Moving the usb/phy code from xhci-omap to the usb/phy directory
>>>> and moving the associated phy code over to the new file.
>>>>
>>>> Newer TI processors adding xHCI support will have different PHY
>>>> configurations so therefore abstracting this code away will prevent
>>>> messing around with the xhci-omap file itself.
>>>>
>>>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
>>> git format-patch -M would help here greatly too.
>>>
>>> Best regards,
>>> Marek Vasut
>> -M gives no love here.  It shows the same diff that I posted.
>>
>> Even with an 80% delta.
> Aaaaaargh ... what about splitting it into two patches then ?
>
> Best regards,
> Marek Vasut

I will see what I can do to get an easier diff.

Dan

-- 
------------------
Dan Murphy