* [PATCH v6 0/8] ARM: imx27 pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Hi,
v6 updates the binding documentation.
this series implements a imx27 pinctrl driver. imx1/21/27 have a register
format that is not compatible with the rest of imx series processors. The
series adds a imx1 core driver for the different register layout.
Regards,
Markus
Markus Pargmann (8):
pinctrl: imx1 core driver
pinctrl: imx27: imx27 pincontrol driver
ARM: dts: imx27 pin functions
ARM: dts: imx27 pinctrl
ARM: dts: imx27 phyCARD-S pinctrl
ARM: dts: imx27 phycore move uart1 to rdk
ARM: dts: imx27 phycore pinctrl
ARM: imx27: enable pinctrl
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 +++
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 10 +
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 4 +
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 5 +
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 8 +-
arch/arm/boot/dts/imx27-pinfunc.h | 524 +++++++++++++++++
arch/arm/boot/dts/imx27.dtsi | 102 ++++
arch/arm/mach-imx/Kconfig | 2 +
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/pinctrl-imx1-core.c | 653 +++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1.h | 73 +++
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++
13 files changed, 1958 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 arch/arm/boot/dts/imx27-pinfunc.h
create mode 100644 drivers/pinctrl/pinctrl-imx1-core.c
create mode 100644 drivers/pinctrl/pinctrl-imx1.h
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
--
1.8.4.rc3
--
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 0/8] ARM: imx27 pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
v6 updates the binding documentation.
this series implements a imx27 pinctrl driver. imx1/21/27 have a register
format that is not compatible with the rest of imx series processors. The
series adds a imx1 core driver for the different register layout.
Regards,
Markus
Markus Pargmann (8):
pinctrl: imx1 core driver
pinctrl: imx27: imx27 pincontrol driver
ARM: dts: imx27 pin functions
ARM: dts: imx27 pinctrl
ARM: dts: imx27 phyCARD-S pinctrl
ARM: dts: imx27 phycore move uart1 to rdk
ARM: dts: imx27 phycore pinctrl
ARM: imx27: enable pinctrl
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 +++
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 10 +
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 4 +
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 5 +
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 8 +-
arch/arm/boot/dts/imx27-pinfunc.h | 524 +++++++++++++++++
arch/arm/boot/dts/imx27.dtsi | 102 ++++
arch/arm/mach-imx/Kconfig | 2 +
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/pinctrl-imx1-core.c | 653 +++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1.h | 73 +++
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++
13 files changed, 1958 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 arch/arm/boot/dts/imx27-pinfunc.h
create mode 100644 drivers/pinctrl/pinctrl-imx1-core.c
create mode 100644 drivers/pinctrl/pinctrl-imx1.h
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
--
1.8.4.rc3
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 1/8] pinctrl: imx1 core driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Core driver for register formats of imx1/imx21/imx27 processors.
The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx1-core.c | 653 ++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1.h | 73 ++++
4 files changed, 732 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-imx1-core.c
create mode 100644 drivers/pinctrl/pinctrl-imx1.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6e864e..8a02aa0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -80,6 +80,11 @@ config PINCTRL_IMX
select PINMUX
select PINCONF
+config PINCTRL_IMX1_CORE
+ bool
+ select PINMUX
+ select PINCONF
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 496d9bf..d7caf08 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
new file mode 100644
index 0000000..4d5a9e7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -0,0 +1,653 @@
+/*
+ * Core driver for the imx pin controller in imx1/21/27
+ *
+ * Copyright (C) 2013 Pengutronix
+ * Author: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * Based on pinctrl-imx.c:
+ * Author: Dong Aisheng <dong.aisheng-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-imx1.h"
+
+struct imx1_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct imx1_pinctrl_soc_info *info;
+};
+
+/*
+ * MX1 register offsets
+ */
+
+#define MX1_DDIR 0x00
+#define MX1_OCR 0x04
+#define MX1_ICONFA 0x0c
+#define MX1_ICONFB 0x10
+#define MX1_GIUS 0x20
+#define MX1_GPR 0x38
+#define MX1_PUEN 0x40
+
+#define MX1_PORT_STRIDE 0x100
+
+
+/*
+ * MUX_ID format defines
+ */
+#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
+#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
+#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
+#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
+#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
+#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
+
+
+/*
+ * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
+ * control register are seperated into function, output configuration, input
+ * configuration A, input configuration B, GPIO in use and data direction.
+ *
+ * Those controls that are represented by 1 bit have a direct mapping between
+ * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
+ * are in the first register and the upper 16 pins in the second (next)
+ * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
+ */
+
+/*
+ * Calculates the register offset from a pin_id
+ */
+static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
+{
+ unsigned int port = pin_id / 32;
+ return ipctl->base + port * MX1_PORT_STRIDE;
+}
+
+/*
+ * Write to a register with 2 bits per pin. The function will automatically
+ * use the next register if the pin is managed in the second register.
+ */
+static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
+ int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
+ u32 old_val;
+ u32 new_val;
+
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x3; /* Make sure value is really 2 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+ int mask = ~BIT_MASK(offset);
+ u32 old_val;
+ u32 new_val;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x1; /* Make sure value is really 1 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 16;
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
+}
+
+static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+
+ return !!(readl(reg) & BIT(offset));
+}
+
+static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
+ const struct imx1_pinctrl_soc_info *info,
+ const char *name)
+{
+ const struct imx1_pin_group *grp = NULL;
+ int i;
+
+ for (i = 0; i < info->ngroups; i++) {
+ if (!strcmp(info->groups[i].name, name)) {
+ grp = &info->groups[i];
+ break;
+ }
+ }
+
+ return grp;
+}
+
+static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->ngroups;
+}
+
+static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->groups[selector].name;
+}
+
+static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned int **pins,
+ unsigned *npins)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ if (selector >= info->ngroups)
+ return -EINVAL;
+
+ *pins = info->groups[selector].pin_ids;
+ *npins = info->groups[selector].npins;
+
+ return 0;
+}
+
+static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
+ imx1_read_bit(ipctl, offset, MX1_GIUS),
+ imx1_read_bit(ipctl, offset, MX1_GPR),
+ imx1_read_bit(ipctl, offset, MX1_DDIR),
+ imx1_read_2bit(ipctl, offset, MX1_OCR),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFA),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFB));
+}
+
+static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = imx1_pinctrl_find_group_by_name(info, np->name);
+ if (!grp) {
+ dev_err(info->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < grp->npins; i++)
+ map_num++;
+
+ new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->npins; i++) {
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, grp->pins[i].pin_id);
+ new_map[j].data.configs.configs = &grp->pins[i].config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops imx1_pctrl_ops = {
+ .get_groups_count = imx1_get_groups_count,
+ .get_group_name = imx1_get_group_name,
+ .get_group_pins = imx1_get_group_pins,
+ .pin_dbg_show = imx1_pin_dbg_show,
+ .dt_node_to_map = imx1_dt_node_to_map,
+ .dt_free_map = imx1_dt_free_map,
+
+};
+
+static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin *pins;
+ unsigned int npins;
+ int i;
+
+ /*
+ * Configure the mux mode for each pin in the group for a specific
+ * function.
+ */
+ pins = info->groups[group].pins;
+ npins = info->groups[group].npins;
+
+ WARN_ON(!pins || !npins);
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ info->functions[selector].name, info->groups[group].name);
+
+ for (i = 0; i < npins; i++) {
+ unsigned int mux = pins[i].mux_id;
+ unsigned int pin_id = pins[i].pin_id;
+ unsigned int afunction = MX1_MUX_FUNCTION(mux);
+ unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
+ unsigned int direction = MX1_MUX_DIR(mux);
+ unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
+ unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
+ unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
+
+ dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
+ __func__, pin_id, afunction, gpio_in_use,
+ direction, gpio_oconf, gpio_iconfa,
+ gpio_iconfb);
+
+ imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
+ imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
+
+ if (gpio_in_use) {
+ imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
+ MX1_ICONFA);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
+ MX1_ICONFB);
+ } else {
+ imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
+ }
+ }
+
+ return 0;
+}
+
+static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->nfunctions;
+}
+
+static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->functions[selector].name;
+}
+
+static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ *groups = info->functions[selector].groups;
+ *num_groups = info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct pinmux_ops imx1_pmx_ops = {
+ .get_functions_count = imx1_pmx_get_funcs_count,
+ .get_function_name = imx1_pmx_get_func_name,
+ .get_function_groups = imx1_pmx_get_groups,
+ .enable = imx1_pmx_enable,
+};
+
+static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
+
+ return 0;
+}
+
+static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ int i;
+
+ for (i = 0; i != num_configs; ++i) {
+ imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
+
+ dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
+ info->pins[pin_id].name);
+ }
+
+ return 0;
+}
+
+static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ unsigned long config;
+
+ imx1_pinconf_get(pctldev, pin_id, &config);
+ seq_printf(s, "0x%lx", config);
+}
+
+static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ struct imx1_pin_group *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group > info->ngroups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = &info->groups[group];
+ for (i = 0; i < grp->npins; i++) {
+ name = pin_get_name(pctldev, grp->pins[i].pin_id);
+ ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "%s: 0x%lx", name, config);
+ }
+}
+
+static const struct pinconf_ops imx1_pinconf_ops = {
+ .pin_config_get = imx1_pinconf_get,
+ .pin_config_set = imx1_pinconf_set,
+ .pin_config_dbg_show = imx1_pinconf_dbg_show,
+ .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx1_pinctrl_desc = {
+ .pctlops = &imx1_pctrl_ops,
+ .pmxops = &imx1_pmx_ops,
+ .confops = &imx1_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int imx1_pinctrl_parse_groups(struct device_node *np,
+ struct imx1_pin_group *grp,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ int size;
+ const __be32 *list;
+ int i;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ /* we do not check return since it's safe node passed down */
+ if (!size || size % 12) {
+ dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ grp->npins = size / 12;
+ grp->pins = devm_kzalloc(info->dev,
+ grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
+ grp->pin_ids = devm_kzalloc(info->dev,
+ grp->npins * sizeof(unsigned int), GFP_KERNEL);
+
+ if (!grp->pins || !grp->pin_ids)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ grp->pins[i].pin_id = be32_to_cpu(*list++);
+ grp->pins[i].mux_id = be32_to_cpu(*list++);
+ grp->pins[i].config = be32_to_cpu(*list++);
+
+ grp->pin_ids[i] = grp->pins[i].pin_id;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_functions(struct device_node *np,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ struct device_node *child;
+ struct imx1_pmx_func *func;
+ struct imx1_pin_group *grp;
+ int ret;
+ static u32 grp_index;
+ u32 i = 0;
+
+ dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &info->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = of_get_child_count(np);
+ if (func->num_groups <= 0)
+ return -EINVAL;
+
+ func->groups = devm_kzalloc(info->dev,
+ func->num_groups * sizeof(char *), GFP_KERNEL);
+
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &info->groups[grp_index++];
+ ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
+ if (ret == -ENOMEM)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
+ struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ int ret;
+ u32 nfuncs = 0;
+ u32 ngroups = 0;
+ u32 ifunc = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ for_each_child_of_node(np, child) {
+ ++nfuncs;
+ ngroups += of_get_child_count(child);
+ }
+
+ if (!nfuncs) {
+ dev_err(&pdev->dev, "No pin functions defined\n");
+ return -EINVAL;
+ }
+
+ info->nfunctions = nfuncs;
+ info->functions = devm_kzalloc(&pdev->dev,
+ nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
+
+ info->ngroups = ngroups;
+ info->groups = devm_kzalloc(&pdev->dev,
+ ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
+
+
+ if (!info->functions || !info->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
+ if (ret == -ENOMEM)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info)
+{
+ struct imx1_pinctrl *ipctl;
+ struct resource *res;
+ struct pinctrl_desc *pctl_desc;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+ info->dev = &pdev->dev;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
+
+ pctl_desc = &imx1_pinctrl_desc;
+ pctl_desc->name = dev_name(&pdev->dev);
+ pctl_desc->pins = info->pins;
+ pctl_desc->npins = info->npins;
+
+ ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ipctl->info = info;
+ ipctl->dev = info->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
+ if (!ipctl->pctl) {
+ dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx1_pinctrl_core_remove(struct platform_device *pdev)
+{
+ struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(ipctl->pctl);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/pinctrl-imx1.h
new file mode 100644
index 0000000..692a54c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1.h
@@ -0,0 +1,73 @@
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX1_H
+#define __DRIVERS_PINCTRL_IMX1_H
+
+struct platform_device;
+
+/**
+ * struct imx1_pin - describes an IMX1/21/27 pin.
+ * @pin_id: ID of the described pin.
+ * @mux_id: ID of the mux setup.
+ * @config: Configuration of the pin (currently only pullup-enable).
+ */
+struct imx1_pin {
+ unsigned int pin_id;
+ unsigned int mux_id;
+ unsigned long config;
+};
+
+/**
+ * struct imx1_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of imx1_pin structs used in this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ */
+struct imx1_pin_group {
+ const char *name;
+ unsigned int *pin_ids;
+ struct imx1_pin *pins;
+ unsigned npins;
+};
+
+/**
+ * struct imx1_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct imx1_pinctrl_soc_info {
+ struct device *dev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ struct imx1_pin_group *groups;
+ unsigned int ngroups;
+ struct imx1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info);
+int imx1_pinctrl_core_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX1_H */
--
1.8.4.rc3
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 1/8] pinctrl: imx1 core driver
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Core driver for register formats of imx1/imx21/imx27 processors.
The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx1-core.c | 653 ++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1.h | 73 ++++
4 files changed, 732 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-imx1-core.c
create mode 100644 drivers/pinctrl/pinctrl-imx1.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6e864e..8a02aa0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -80,6 +80,11 @@ config PINCTRL_IMX
select PINMUX
select PINCONF
+config PINCTRL_IMX1_CORE
+ bool
+ select PINMUX
+ select PINCONF
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 496d9bf..d7caf08 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
new file mode 100644
index 0000000..4d5a9e7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -0,0 +1,653 @@
+/*
+ * Core driver for the imx pin controller in imx1/21/27
+ *
+ * Copyright (C) 2013 Pengutronix
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * Based on pinctrl-imx.c:
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-imx1.h"
+
+struct imx1_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct imx1_pinctrl_soc_info *info;
+};
+
+/*
+ * MX1 register offsets
+ */
+
+#define MX1_DDIR 0x00
+#define MX1_OCR 0x04
+#define MX1_ICONFA 0x0c
+#define MX1_ICONFB 0x10
+#define MX1_GIUS 0x20
+#define MX1_GPR 0x38
+#define MX1_PUEN 0x40
+
+#define MX1_PORT_STRIDE 0x100
+
+
+/*
+ * MUX_ID format defines
+ */
+#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
+#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
+#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
+#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
+#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
+#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
+
+
+/*
+ * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
+ * control register are seperated into function, output configuration, input
+ * configuration A, input configuration B, GPIO in use and data direction.
+ *
+ * Those controls that are represented by 1 bit have a direct mapping between
+ * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
+ * are in the first register and the upper 16 pins in the second (next)
+ * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
+ */
+
+/*
+ * Calculates the register offset from a pin_id
+ */
+static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
+{
+ unsigned int port = pin_id / 32;
+ return ipctl->base + port * MX1_PORT_STRIDE;
+}
+
+/*
+ * Write to a register with 2 bits per pin. The function will automatically
+ * use the next register if the pin is managed in the second register.
+ */
+static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
+ int mask = ~(0x3 << offset); /* Mask for 2 bits@offset */
+ u32 old_val;
+ u32 new_val;
+
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x3; /* Make sure value is really 2 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+ int mask = ~BIT_MASK(offset);
+ u32 old_val;
+ u32 new_val;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x1; /* Make sure value is really 1 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 16;
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
+}
+
+static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+
+ return !!(readl(reg) & BIT(offset));
+}
+
+static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
+ const struct imx1_pinctrl_soc_info *info,
+ const char *name)
+{
+ const struct imx1_pin_group *grp = NULL;
+ int i;
+
+ for (i = 0; i < info->ngroups; i++) {
+ if (!strcmp(info->groups[i].name, name)) {
+ grp = &info->groups[i];
+ break;
+ }
+ }
+
+ return grp;
+}
+
+static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->ngroups;
+}
+
+static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->groups[selector].name;
+}
+
+static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned int **pins,
+ unsigned *npins)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ if (selector >= info->ngroups)
+ return -EINVAL;
+
+ *pins = info->groups[selector].pin_ids;
+ *npins = info->groups[selector].npins;
+
+ return 0;
+}
+
+static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
+ imx1_read_bit(ipctl, offset, MX1_GIUS),
+ imx1_read_bit(ipctl, offset, MX1_GPR),
+ imx1_read_bit(ipctl, offset, MX1_DDIR),
+ imx1_read_2bit(ipctl, offset, MX1_OCR),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFA),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFB));
+}
+
+static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = imx1_pinctrl_find_group_by_name(info, np->name);
+ if (!grp) {
+ dev_err(info->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < grp->npins; i++)
+ map_num++;
+
+ new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->npins; i++) {
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, grp->pins[i].pin_id);
+ new_map[j].data.configs.configs = &grp->pins[i].config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops imx1_pctrl_ops = {
+ .get_groups_count = imx1_get_groups_count,
+ .get_group_name = imx1_get_group_name,
+ .get_group_pins = imx1_get_group_pins,
+ .pin_dbg_show = imx1_pin_dbg_show,
+ .dt_node_to_map = imx1_dt_node_to_map,
+ .dt_free_map = imx1_dt_free_map,
+
+};
+
+static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin *pins;
+ unsigned int npins;
+ int i;
+
+ /*
+ * Configure the mux mode for each pin in the group for a specific
+ * function.
+ */
+ pins = info->groups[group].pins;
+ npins = info->groups[group].npins;
+
+ WARN_ON(!pins || !npins);
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ info->functions[selector].name, info->groups[group].name);
+
+ for (i = 0; i < npins; i++) {
+ unsigned int mux = pins[i].mux_id;
+ unsigned int pin_id = pins[i].pin_id;
+ unsigned int afunction = MX1_MUX_FUNCTION(mux);
+ unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
+ unsigned int direction = MX1_MUX_DIR(mux);
+ unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
+ unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
+ unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
+
+ dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
+ __func__, pin_id, afunction, gpio_in_use,
+ direction, gpio_oconf, gpio_iconfa,
+ gpio_iconfb);
+
+ imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
+ imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
+
+ if (gpio_in_use) {
+ imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
+ MX1_ICONFA);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
+ MX1_ICONFB);
+ } else {
+ imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
+ }
+ }
+
+ return 0;
+}
+
+static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->nfunctions;
+}
+
+static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->functions[selector].name;
+}
+
+static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ *groups = info->functions[selector].groups;
+ *num_groups = info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct pinmux_ops imx1_pmx_ops = {
+ .get_functions_count = imx1_pmx_get_funcs_count,
+ .get_function_name = imx1_pmx_get_func_name,
+ .get_function_groups = imx1_pmx_get_groups,
+ .enable = imx1_pmx_enable,
+};
+
+static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
+
+ return 0;
+}
+
+static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ int i;
+
+ for (i = 0; i != num_configs; ++i) {
+ imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
+
+ dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
+ info->pins[pin_id].name);
+ }
+
+ return 0;
+}
+
+static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ unsigned long config;
+
+ imx1_pinconf_get(pctldev, pin_id, &config);
+ seq_printf(s, "0x%lx", config);
+}
+
+static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ struct imx1_pin_group *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group > info->ngroups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = &info->groups[group];
+ for (i = 0; i < grp->npins; i++) {
+ name = pin_get_name(pctldev, grp->pins[i].pin_id);
+ ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "%s: 0x%lx", name, config);
+ }
+}
+
+static const struct pinconf_ops imx1_pinconf_ops = {
+ .pin_config_get = imx1_pinconf_get,
+ .pin_config_set = imx1_pinconf_set,
+ .pin_config_dbg_show = imx1_pinconf_dbg_show,
+ .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx1_pinctrl_desc = {
+ .pctlops = &imx1_pctrl_ops,
+ .pmxops = &imx1_pmx_ops,
+ .confops = &imx1_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int imx1_pinctrl_parse_groups(struct device_node *np,
+ struct imx1_pin_group *grp,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ int size;
+ const __be32 *list;
+ int i;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ /* we do not check return since it's safe node passed down */
+ if (!size || size % 12) {
+ dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ grp->npins = size / 12;
+ grp->pins = devm_kzalloc(info->dev,
+ grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
+ grp->pin_ids = devm_kzalloc(info->dev,
+ grp->npins * sizeof(unsigned int), GFP_KERNEL);
+
+ if (!grp->pins || !grp->pin_ids)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ grp->pins[i].pin_id = be32_to_cpu(*list++);
+ grp->pins[i].mux_id = be32_to_cpu(*list++);
+ grp->pins[i].config = be32_to_cpu(*list++);
+
+ grp->pin_ids[i] = grp->pins[i].pin_id;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_functions(struct device_node *np,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ struct device_node *child;
+ struct imx1_pmx_func *func;
+ struct imx1_pin_group *grp;
+ int ret;
+ static u32 grp_index;
+ u32 i = 0;
+
+ dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &info->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = of_get_child_count(np);
+ if (func->num_groups <= 0)
+ return -EINVAL;
+
+ func->groups = devm_kzalloc(info->dev,
+ func->num_groups * sizeof(char *), GFP_KERNEL);
+
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &info->groups[grp_index++];
+ ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
+ if (ret == -ENOMEM)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
+ struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ int ret;
+ u32 nfuncs = 0;
+ u32 ngroups = 0;
+ u32 ifunc = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ for_each_child_of_node(np, child) {
+ ++nfuncs;
+ ngroups += of_get_child_count(child);
+ }
+
+ if (!nfuncs) {
+ dev_err(&pdev->dev, "No pin functions defined\n");
+ return -EINVAL;
+ }
+
+ info->nfunctions = nfuncs;
+ info->functions = devm_kzalloc(&pdev->dev,
+ nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
+
+ info->ngroups = ngroups;
+ info->groups = devm_kzalloc(&pdev->dev,
+ ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
+
+
+ if (!info->functions || !info->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
+ if (ret == -ENOMEM)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info)
+{
+ struct imx1_pinctrl *ipctl;
+ struct resource *res;
+ struct pinctrl_desc *pctl_desc;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+ info->dev = &pdev->dev;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
+
+ pctl_desc = &imx1_pinctrl_desc;
+ pctl_desc->name = dev_name(&pdev->dev);
+ pctl_desc->pins = info->pins;
+ pctl_desc->npins = info->npins;
+
+ ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ipctl->info = info;
+ ipctl->dev = info->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
+ if (!ipctl->pctl) {
+ dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx1_pinctrl_core_remove(struct platform_device *pdev)
+{
+ struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(ipctl->pctl);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/pinctrl-imx1.h
new file mode 100644
index 0000000..692a54c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1.h
@@ -0,0 +1,73 @@
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX1_H
+#define __DRIVERS_PINCTRL_IMX1_H
+
+struct platform_device;
+
+/**
+ * struct imx1_pin - describes an IMX1/21/27 pin.
+ * @pin_id: ID of the described pin.
+ * @mux_id: ID of the mux setup.
+ * @config: Configuration of the pin (currently only pullup-enable).
+ */
+struct imx1_pin {
+ unsigned int pin_id;
+ unsigned int mux_id;
+ unsigned long config;
+};
+
+/**
+ * struct imx1_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of imx1_pin structs used in this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ */
+struct imx1_pin_group {
+ const char *name;
+ unsigned int *pin_ids;
+ struct imx1_pin *pins;
+ unsigned npins;
+};
+
+/**
+ * struct imx1_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct imx1_pinctrl_soc_info {
+ struct device *dev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ struct imx1_pin_group *groups;
+ unsigned int ngroups;
+ struct imx1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info);
+int imx1_pinctrl_core_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX1_H */
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
4 files changed, 575 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
new file mode 100644
index 0000000..32c81c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -0,0 +1,89 @@
+* Freescale IMX27 IOMUX Controller
+
+Required properties:
+- compatible: "fsl,imx27-iomuxc"
+
+The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
+
+Required properties for pin configuration node:
+- fsl,pins: three integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
+
+ PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ number on the specific port (between 0 and 31).
+
+ MUX_ID is
+ function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+
+ function: 0 - Primary function
+ 1 - Alternate function
+ 2 - GPIO
+ Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
+
+ direction: 0 - Input
+ 1 - Output
+ Register DDIR
+
+ gpio_oconf: 0 - A_IN
+ 1 - B_IN
+ 2 - C_IN
+ 3 - Data Register
+ Registers OCR1 and OCR2
+
+ gpio_iconfa/b: 0 - GPIO_IN
+ 1 - Interrupt Status Register
+ 2 - 0
+ 3 - 1
+ Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
+
+
+ CONFIG can be 0 or 1, meaning Pullup disable/enable.
+
+
+
+
+Example:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
+ 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
+ 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
+ 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
+ >;
+ };
+
+ ...
+ };
+};
+
+
+For convenience there are macros defined in imx27-pinfunc.h which provide PIN
+and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
+are defined in the i.MX27 reference manual.
+
+The above example using macros:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ ...
+ };
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8a02aa0..4c3e5d2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -85,6 +85,14 @@ config PINCTRL_IMX1_CORE
select PINMUX
select PINCONF
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d7caf08..5d23b71 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
new file mode 100644
index 0000000..417c992
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -0,0 +1,477 @@
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
+ MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
+ MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
+ MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
+ MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
+ MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
+ MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
+ MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
+ MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
+ MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
+ MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
+ MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
+ MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
+ MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
+ MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
+ MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
+ MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
+ MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
+ MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
+ MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+struct imx27_pinctrl_private {
+ int num_gpio_childs;
+ struct platform_device **gpio_dev;
+ struct mxc_gpio_platform_data *gpio_pdata;
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.8.4.rc3
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
4 files changed, 575 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
new file mode 100644
index 0000000..32c81c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -0,0 +1,89 @@
+* Freescale IMX27 IOMUX Controller
+
+Required properties:
+- compatible: "fsl,imx27-iomuxc"
+
+The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
+
+Required properties for pin configuration node:
+- fsl,pins: three integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
+
+ PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ number on the specific port (between 0 and 31).
+
+ MUX_ID is
+ function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+
+ function: 0 - Primary function
+ 1 - Alternate function
+ 2 - GPIO
+ Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
+
+ direction: 0 - Input
+ 1 - Output
+ Register DDIR
+
+ gpio_oconf: 0 - A_IN
+ 1 - B_IN
+ 2 - C_IN
+ 3 - Data Register
+ Registers OCR1 and OCR2
+
+ gpio_iconfa/b: 0 - GPIO_IN
+ 1 - Interrupt Status Register
+ 2 - 0
+ 3 - 1
+ Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
+
+
+ CONFIG can be 0 or 1, meaning Pullup disable/enable.
+
+
+
+
+Example:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
+ 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
+ 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
+ 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
+ >;
+ };
+
+ ...
+ };
+};
+
+
+For convenience there are macros defined in imx27-pinfunc.h which provide PIN
+and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
+are defined in the i.MX27 reference manual.
+
+The above example using macros:
+
+iomuxc: iomuxc at 10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ ...
+ };
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8a02aa0..4c3e5d2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -85,6 +85,14 @@ config PINCTRL_IMX1_CORE
select PINMUX
select PINCONF
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d7caf08..5d23b71 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
new file mode 100644
index 0000000..417c992
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -0,0 +1,477 @@
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
+ MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
+ MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
+ MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
+ MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
+ MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
+ MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
+ MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
+ MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
+ MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
+ MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
+ MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
+ MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
+ MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
+ MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
+ MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
+ MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
+ MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
+ MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
+ MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+struct imx27_pinctrl_private {
+ int num_gpio_childs;
+ struct platform_device **gpio_dev;
+ struct mxc_gpio_platform_data *gpio_pdata;
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 3/8] ARM: dts: imx27 pin functions
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx27-pinfunc.h | 524 ++++++++++++++++++++++++++++++++++++++
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx27-pinfunc.h
diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h
new file mode 100644
index 0000000..32bfcc2
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-pinfunc.h
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX27_PINFUNC_H
+#define __DTS_IMX27_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function: 0 - Primary function
+ * 1 - Alternate function
+ * 2 - GPIO
+ * direction: 0 - Input
+ * 1 - Output
+ * gpio_oconf: 0 - A_IN
+ * 1 - B_IN
+ * 2 - C_IN
+ * 3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ * 1 - Interrupt Status Register
+ * 2 - 0
+ * 3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
+#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x036
+#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
+#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x036
+#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
+#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x036
+#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
+#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x036
+#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
+#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x036
+#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
+#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x036
+#define MX27_PAD_LD0__LD0 0x06 0x004
+#define MX27_PAD_LD0__GPIO1_6 0x06 0x036
+#define MX27_PAD_LD1__LD1 0x07 0x004
+#define MX27_PAD_LD1__GPIO1_7 0x07 0x036
+#define MX27_PAD_LD2__LD2 0x08 0x004
+#define MX27_PAD_LD2__GPIO1_8 0x08 0x036
+#define MX27_PAD_LD3__LD3 0x09 0x004
+#define MX27_PAD_LD3__GPIO1_9 0x09 0x036
+#define MX27_PAD_LD4__LD4 0x0a 0x004
+#define MX27_PAD_LD4__GPIO1_10 0x0a 0x036
+#define MX27_PAD_LD5__LD5 0x0b 0x004
+#define MX27_PAD_LD5__GPIO1_11 0x0b 0x036
+#define MX27_PAD_LD6__LD6 0x0c 0x004
+#define MX27_PAD_LD6__GPIO1_12 0x0c 0x036
+#define MX27_PAD_LD7__LD7 0x0d 0x004
+#define MX27_PAD_LD7__GPIO1_13 0x0d 0x036
+#define MX27_PAD_LD8__LD8 0x0e 0x004
+#define MX27_PAD_LD8__GPIO1_14 0x0e 0x036
+#define MX27_PAD_LD9__LD9 0x0f 0x004
+#define MX27_PAD_LD9__GPIO1_15 0x0f 0x036
+#define MX27_PAD_LD10__LD10 0x10 0x004
+#define MX27_PAD_LD10__GPIO1_16 0x10 0x036
+#define MX27_PAD_LD11__LD11 0x11 0x004
+#define MX27_PAD_LD11__GPIO1_17 0x11 0x036
+#define MX27_PAD_LD12__LD12 0x12 0x004
+#define MX27_PAD_LD12__GPIO1_18 0x12 0x036
+#define MX27_PAD_LD13__LD13 0x13 0x004
+#define MX27_PAD_LD13__GPIO1_19 0x13 0x036
+#define MX27_PAD_LD14__LD14 0x14 0x004
+#define MX27_PAD_LD14__GPIO1_20 0x14 0x036
+#define MX27_PAD_LD15__LD15 0x15 0x004
+#define MX27_PAD_LD15__GPIO1_21 0x15 0x036
+#define MX27_PAD_LD16__LD16 0x16 0x004
+#define MX27_PAD_LD16__GPIO1_22 0x16 0x036
+#define MX27_PAD_LD17__LD17 0x17 0x004
+#define MX27_PAD_LD17__GPIO1_23 0x17 0x036
+#define MX27_PAD_REV__REV 0x18 0x004
+#define MX27_PAD_REV__GPIO1_24 0x18 0x036
+#define MX27_PAD_CLS__CLS 0x19 0x004
+#define MX27_PAD_CLS__GPIO1_25 0x19 0x036
+#define MX27_PAD_PS__PS 0x1a 0x004
+#define MX27_PAD_PS__GPIO1_26 0x1a 0x036
+#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
+#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x036
+#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
+#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x036
+#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
+#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x036
+#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
+#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x036
+#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
+#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x036
+#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
+#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x036
+#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
+#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x036
+#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
+#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x036
+#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
+#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x036
+#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
+#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
+#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x036
+#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
+#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
+#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x036
+#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
+#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
+#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x036
+#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
+#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
+#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x036
+#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
+#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
+#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x036
+#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
+#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
+#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x036
+#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
+#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
+#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x036
+#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
+#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
+#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x036
+#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
+#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
+#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x036
+#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
+#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
+#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x036
+#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
+#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x036
+#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
+#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x036
+#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
+#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x036
+#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
+#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x036
+#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
+#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
+#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x036
+#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
+#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
+#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x036
+#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
+#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
+#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x036
+#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
+#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
+#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x036
+#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
+#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x036
+#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
+#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x036
+#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
+#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x036
+#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
+#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x036
+#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
+#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
+#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x036
+#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
+#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x036
+#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
+#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
+#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x036
+#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
+#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
+#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x036
+#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
+#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x036
+#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
+#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
+#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x036
+#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
+#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x036
+#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
+#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x036
+#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
+#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x036
+#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
+#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x036
+#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
+#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x036
+#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
+#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x036
+#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
+#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x036
+#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
+#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x036
+#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
+#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x036
+#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
+#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x036
+#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
+#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x036
+#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
+#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x036
+#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
+#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x036
+#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
+#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x036
+#define MX27_PAD_TOUT__TOUT 0x4e 0x004
+#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x036
+#define MX27_PAD_TIN__TIN 0x4f 0x000
+#define MX27_PAD_TIN__GPIO3_15 0x4f 0x036
+#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
+#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x036
+#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
+#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x036
+#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
+#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x036
+#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
+#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x036
+#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
+#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x036
+#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
+#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x036
+#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
+#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x036
+#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
+#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x036
+#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
+#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
+#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x036
+#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
+#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
+#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x036
+#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
+#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
+#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x036
+#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
+#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
+#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x036
+#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
+#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
+#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x036
+#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
+#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
+#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x036
+#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
+#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
+#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x036
+#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
+#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
+#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x036
+#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
+#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
+#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x036
+#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
+#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
+#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
+#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x036
+#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
+#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
+#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
+#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x036
+#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
+#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
+#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
+#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x036
+#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
+#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
+#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
+#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x036
+#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
+#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
+#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
+#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x036
+#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
+#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
+#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
+#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x036
+#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
+#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
+#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
+#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x036
+#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
+#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
+#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x036
+#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
+#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
+#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
+#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x036
+#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
+#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
+#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
+#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x036
+#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
+#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
+#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
+#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x036
+#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
+#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
+#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
+#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x036
+#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
+#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
+#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
+#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x036
+#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
+#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
+#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
+#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x036
+#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
+#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
+#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
+#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x036
+#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
+#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
+#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
+#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x036
+#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
+#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x036
+#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
+#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x036
+#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
+#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
+#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x036
+#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
+#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
+#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x036
+#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
+#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
+#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x036
+#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
+#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
+#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x036
+#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
+#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
+#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x036
+#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
+#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
+#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x036
+#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
+#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x036
+#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
+#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
+#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x036
+#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
+#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x036
+#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
+#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x036
+#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
+#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x036
+#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
+#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x036
+#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
+#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x036
+#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
+#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
+#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x036
+#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
+#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
+#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x036
+#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
+#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
+#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x036
+#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
+#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
+#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x036
+#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
+#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
+#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x036
+#define MX27_PAD_PWMO__PWMO 0x85 0x004
+#define MX27_PAD_PWMO__GPIO5_5 0x85 0x036
+#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
+#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
+#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x036
+#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
+#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
+#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x036
+#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
+#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x036
+#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
+#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x036
+#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
+#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x036
+#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
+#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x036
+#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
+#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x036
+#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
+#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x036
+#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
+#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x036
+#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
+#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x036
+#define MX27_PAD_RTCK__RTCK 0x90 0x004
+#define MX27_PAD_RTCK__OWIRE 0x90 0x005
+#define MX27_PAD_RTCK__GPIO5_16 0x90 0x036
+#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
+#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x036
+#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
+#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
+#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x036
+#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
+#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x036
+#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
+#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x036
+#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
+#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
+#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x036
+#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
+#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
+#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x036
+#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
+#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
+#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x036
+#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
+#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x036
+#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
+#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x036
+#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
+#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x036
+#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
+#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x036
+#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
+#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x036
+#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
+#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x036
+#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
+#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x036
+#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
+#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x036
+#define MX27_PAD_NFRB__NFRB 0xa0 0x000
+#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
+#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x036
+#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
+#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
+#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x036
+#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
+#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
+#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x036
+#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
+#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
+#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x036
+#define MX27_PAD_NFALE__NFALE 0xa4 0x004
+#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
+#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x036
+#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
+#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
+#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x036
+#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
+#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
+#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x036
+#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
+#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
+#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x036
+#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
+#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
+#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x036
+#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
+#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
+#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x036
+#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
+#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
+#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x036
+#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
+#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
+#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x036
+#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
+#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
+#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x036
+#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
+#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
+#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x036
+#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
+#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
+#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x036
+#define MX27_PAD_CLKO__CLKO 0xaf 0x004
+#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x036
+#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
+#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
+#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x036
+#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
+#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
+#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x036
+#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
+#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
+#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x036
+#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
+#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
+#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x036
+#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
+#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
+#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x036
+#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
+#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
+#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x036
+#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
+#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
+#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x036
+#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
+#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
+#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
+#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x036
+#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
+#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x036
+#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
+#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x036
+#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
+#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x036
+#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
+#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x036
+#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
+#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x036
+#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
+#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x036
+#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
+#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x036
+#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
+#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x036
+
+#endif /* __DTS_IMX27_PINFUNC_H */
--
1.8.4.rc3
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 3/8] ARM: dts: imx27 pin functions
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boot/dts/imx27-pinfunc.h | 524 ++++++++++++++++++++++++++++++++++++++
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx27-pinfunc.h
diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h
new file mode 100644
index 0000000..32bfcc2
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-pinfunc.h
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX27_PINFUNC_H
+#define __DTS_IMX27_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function: 0 - Primary function
+ * 1 - Alternate function
+ * 2 - GPIO
+ * direction: 0 - Input
+ * 1 - Output
+ * gpio_oconf: 0 - A_IN
+ * 1 - B_IN
+ * 2 - C_IN
+ * 3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ * 1 - Interrupt Status Register
+ * 2 - 0
+ * 3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
+#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x036
+#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
+#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x036
+#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
+#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x036
+#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
+#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x036
+#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
+#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x036
+#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
+#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x036
+#define MX27_PAD_LD0__LD0 0x06 0x004
+#define MX27_PAD_LD0__GPIO1_6 0x06 0x036
+#define MX27_PAD_LD1__LD1 0x07 0x004
+#define MX27_PAD_LD1__GPIO1_7 0x07 0x036
+#define MX27_PAD_LD2__LD2 0x08 0x004
+#define MX27_PAD_LD2__GPIO1_8 0x08 0x036
+#define MX27_PAD_LD3__LD3 0x09 0x004
+#define MX27_PAD_LD3__GPIO1_9 0x09 0x036
+#define MX27_PAD_LD4__LD4 0x0a 0x004
+#define MX27_PAD_LD4__GPIO1_10 0x0a 0x036
+#define MX27_PAD_LD5__LD5 0x0b 0x004
+#define MX27_PAD_LD5__GPIO1_11 0x0b 0x036
+#define MX27_PAD_LD6__LD6 0x0c 0x004
+#define MX27_PAD_LD6__GPIO1_12 0x0c 0x036
+#define MX27_PAD_LD7__LD7 0x0d 0x004
+#define MX27_PAD_LD7__GPIO1_13 0x0d 0x036
+#define MX27_PAD_LD8__LD8 0x0e 0x004
+#define MX27_PAD_LD8__GPIO1_14 0x0e 0x036
+#define MX27_PAD_LD9__LD9 0x0f 0x004
+#define MX27_PAD_LD9__GPIO1_15 0x0f 0x036
+#define MX27_PAD_LD10__LD10 0x10 0x004
+#define MX27_PAD_LD10__GPIO1_16 0x10 0x036
+#define MX27_PAD_LD11__LD11 0x11 0x004
+#define MX27_PAD_LD11__GPIO1_17 0x11 0x036
+#define MX27_PAD_LD12__LD12 0x12 0x004
+#define MX27_PAD_LD12__GPIO1_18 0x12 0x036
+#define MX27_PAD_LD13__LD13 0x13 0x004
+#define MX27_PAD_LD13__GPIO1_19 0x13 0x036
+#define MX27_PAD_LD14__LD14 0x14 0x004
+#define MX27_PAD_LD14__GPIO1_20 0x14 0x036
+#define MX27_PAD_LD15__LD15 0x15 0x004
+#define MX27_PAD_LD15__GPIO1_21 0x15 0x036
+#define MX27_PAD_LD16__LD16 0x16 0x004
+#define MX27_PAD_LD16__GPIO1_22 0x16 0x036
+#define MX27_PAD_LD17__LD17 0x17 0x004
+#define MX27_PAD_LD17__GPIO1_23 0x17 0x036
+#define MX27_PAD_REV__REV 0x18 0x004
+#define MX27_PAD_REV__GPIO1_24 0x18 0x036
+#define MX27_PAD_CLS__CLS 0x19 0x004
+#define MX27_PAD_CLS__GPIO1_25 0x19 0x036
+#define MX27_PAD_PS__PS 0x1a 0x004
+#define MX27_PAD_PS__GPIO1_26 0x1a 0x036
+#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
+#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x036
+#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
+#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x036
+#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
+#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x036
+#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
+#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x036
+#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
+#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x036
+#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
+#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x036
+#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
+#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x036
+#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
+#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x036
+#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
+#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x036
+#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
+#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
+#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x036
+#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
+#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
+#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x036
+#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
+#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
+#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x036
+#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
+#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
+#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x036
+#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
+#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
+#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x036
+#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
+#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
+#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x036
+#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
+#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
+#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x036
+#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
+#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
+#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x036
+#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
+#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
+#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x036
+#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
+#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
+#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x036
+#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
+#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x036
+#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
+#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x036
+#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
+#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x036
+#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
+#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x036
+#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
+#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
+#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x036
+#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
+#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
+#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x036
+#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
+#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
+#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x036
+#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
+#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
+#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x036
+#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
+#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x036
+#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
+#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x036
+#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
+#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x036
+#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
+#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x036
+#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
+#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
+#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x036
+#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
+#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x036
+#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
+#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
+#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x036
+#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
+#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
+#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x036
+#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
+#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x036
+#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
+#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
+#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x036
+#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
+#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x036
+#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
+#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x036
+#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
+#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x036
+#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
+#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x036
+#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
+#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x036
+#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
+#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x036
+#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
+#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x036
+#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
+#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x036
+#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
+#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x036
+#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
+#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x036
+#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
+#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x036
+#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
+#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x036
+#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
+#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x036
+#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
+#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x036
+#define MX27_PAD_TOUT__TOUT 0x4e 0x004
+#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x036
+#define MX27_PAD_TIN__TIN 0x4f 0x000
+#define MX27_PAD_TIN__GPIO3_15 0x4f 0x036
+#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
+#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x036
+#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
+#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x036
+#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
+#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x036
+#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
+#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x036
+#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
+#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x036
+#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
+#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x036
+#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
+#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x036
+#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
+#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x036
+#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
+#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
+#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x036
+#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
+#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
+#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x036
+#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
+#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
+#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x036
+#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
+#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
+#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x036
+#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
+#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
+#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x036
+#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
+#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
+#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x036
+#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
+#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
+#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x036
+#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
+#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
+#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x036
+#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
+#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
+#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x036
+#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
+#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
+#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
+#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x036
+#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
+#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
+#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
+#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x036
+#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
+#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
+#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
+#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x036
+#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
+#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
+#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
+#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x036
+#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
+#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
+#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
+#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x036
+#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
+#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
+#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
+#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x036
+#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
+#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
+#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
+#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x036
+#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
+#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
+#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x036
+#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
+#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
+#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
+#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x036
+#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
+#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
+#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
+#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x036
+#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
+#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
+#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
+#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x036
+#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
+#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
+#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
+#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x036
+#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
+#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
+#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
+#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x036
+#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
+#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
+#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
+#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x036
+#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
+#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
+#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
+#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x036
+#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
+#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
+#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
+#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x036
+#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
+#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x036
+#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
+#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x036
+#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
+#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
+#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x036
+#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
+#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
+#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x036
+#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
+#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
+#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x036
+#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
+#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
+#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x036
+#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
+#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
+#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x036
+#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
+#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
+#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x036
+#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
+#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x036
+#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
+#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
+#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x036
+#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
+#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x036
+#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
+#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x036
+#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
+#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x036
+#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
+#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x036
+#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
+#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x036
+#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
+#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
+#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x036
+#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
+#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
+#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x036
+#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
+#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
+#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x036
+#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
+#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
+#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x036
+#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
+#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
+#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x036
+#define MX27_PAD_PWMO__PWMO 0x85 0x004
+#define MX27_PAD_PWMO__GPIO5_5 0x85 0x036
+#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
+#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
+#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x036
+#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
+#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
+#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x036
+#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
+#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x036
+#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
+#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x036
+#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
+#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x036
+#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
+#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x036
+#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
+#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x036
+#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
+#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x036
+#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
+#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x036
+#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
+#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x036
+#define MX27_PAD_RTCK__RTCK 0x90 0x004
+#define MX27_PAD_RTCK__OWIRE 0x90 0x005
+#define MX27_PAD_RTCK__GPIO5_16 0x90 0x036
+#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
+#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x036
+#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
+#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
+#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x036
+#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
+#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x036
+#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
+#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x036
+#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
+#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
+#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x036
+#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
+#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
+#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x036
+#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
+#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
+#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x036
+#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
+#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x036
+#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
+#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x036
+#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
+#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x036
+#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
+#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x036
+#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
+#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x036
+#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
+#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x036
+#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
+#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x036
+#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
+#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x036
+#define MX27_PAD_NFRB__NFRB 0xa0 0x000
+#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
+#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x036
+#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
+#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
+#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x036
+#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
+#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
+#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x036
+#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
+#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
+#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x036
+#define MX27_PAD_NFALE__NFALE 0xa4 0x004
+#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
+#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x036
+#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
+#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
+#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x036
+#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
+#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
+#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x036
+#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
+#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
+#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x036
+#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
+#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
+#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x036
+#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
+#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
+#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x036
+#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
+#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
+#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x036
+#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
+#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
+#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x036
+#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
+#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
+#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x036
+#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
+#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
+#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x036
+#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
+#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
+#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x036
+#define MX27_PAD_CLKO__CLKO 0xaf 0x004
+#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x036
+#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
+#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
+#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x036
+#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
+#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
+#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x036
+#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
+#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
+#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x036
+#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
+#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
+#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x036
+#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
+#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
+#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x036
+#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
+#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
+#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x036
+#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
+#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
+#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x036
+#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
+#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
+#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
+#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x036
+#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
+#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x036
+#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
+#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x036
+#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
+#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x036
+#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
+#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x036
+#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
+#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x036
+#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
+#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x036
+#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
+#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x036
+#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
+#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x036
+
+#endif /* __DTS_IMX27_PINFUNC_H */
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Pinctrl driver node and pin group definitions for other driver nodes.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx27.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index b7a1c6d..641a63d 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -10,6 +10,7 @@
*/
#include "skeleton.dtsi"
+#include "imx27-pinfunc.h"
/ {
aliases {
@@ -235,6 +236,12 @@
status = "disabled";
};
+ iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ };
+
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
@@ -467,3 +474,98 @@
};
};
};
+
+&iomuxc {
+ fec {
+ pinctrl_fec1_1: fec1-1 {
+ fsl,pins = <
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+ >;
+ };
+ };
+
+ i2c {
+ pinctrl_i2c1_1: i2c1-1 {
+ fsl,pins = <
+ MX27_PAD_I2C_DATA__I2C_DATA 0x0
+ MX27_PAD_I2C_CLK__I2C_CLK 0x0
+ >;
+ };
+
+ pinctrl_i2c2_1: i2c2-1 {
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
+ };
+ };
+
+ owire {
+ pinctrl_owire1_1: owire1-1 {
+ fsl,pins = <
+ MX27_PAD_RTCK__OWIRE 0x0
+ >;
+ };
+ };
+
+ uart {
+ pinctrl_uart1_1: uart1-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart1_rtscts_1: uart1-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart2_1: uart2-1 {
+ fsl,pins = <
+ MX27_PAD_UART2_TXD__UART2_TXD 0x0
+ MX27_PAD_UART2_RXD__UART2_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart2_rtscts_1: uart2-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART2_CTS__UART2_CTS 0x0
+ MX27_PAD_UART2_RTS__UART2_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart3_1: uart3-1 {
+ fsl,pins = <
+ MX27_PAD_UART3_TXD__UART3_TXD 0x0
+ MX27_PAD_UART3_RXD__UART3_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart3_rtscts_1: uart3-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART3_CTS__UART3_CTS 0x0
+ MX27_PAD_UART3_RTS__UART3_RTS 0x0
+ >;
+ };
+ };
+};
--
1.8.4.rc3
--
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Pinctrl driver node and pin group definitions for other driver nodes.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boot/dts/imx27.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index b7a1c6d..641a63d 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -10,6 +10,7 @@
*/
#include "skeleton.dtsi"
+#include "imx27-pinfunc.h"
/ {
aliases {
@@ -235,6 +236,12 @@
status = "disabled";
};
+ iomuxc: iomuxc at 10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ };
+
gpio1: gpio at 10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
@@ -467,3 +474,98 @@
};
};
};
+
+&iomuxc {
+ fec {
+ pinctrl_fec1_1: fec1-1 {
+ fsl,pins = <
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+ >;
+ };
+ };
+
+ i2c {
+ pinctrl_i2c1_1: i2c1-1 {
+ fsl,pins = <
+ MX27_PAD_I2C_DATA__I2C_DATA 0x0
+ MX27_PAD_I2C_CLK__I2C_CLK 0x0
+ >;
+ };
+
+ pinctrl_i2c2_1: i2c2-1 {
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
+ };
+ };
+
+ owire {
+ pinctrl_owire1_1: owire1-1 {
+ fsl,pins = <
+ MX27_PAD_RTCK__OWIRE 0x0
+ >;
+ };
+ };
+
+ uart {
+ pinctrl_uart1_1: uart1-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart1_rtscts_1: uart1-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart2_1: uart2-1 {
+ fsl,pins = <
+ MX27_PAD_UART2_TXD__UART2_TXD 0x0
+ MX27_PAD_UART2_RXD__UART2_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart2_rtscts_1: uart2-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART2_CTS__UART2_CTS 0x0
+ MX27_PAD_UART2_RTS__UART2_RTS 0x0
+ >;
+ };
+
+ pinctrl_uart3_1: uart3-1 {
+ fsl,pins = <
+ MX27_PAD_UART3_TXD__UART3_TXD 0x0
+ MX27_PAD_UART3_RXD__UART3_RXD 0x0
+ >;
+ };
+
+ pinctrl_uart3_rtscts_1: uart3-rtscts-1 {
+ fsl,pins = <
+ MX27_PAD_UART3_CTS__UART3_CTS 0x0
+ MX27_PAD_UART3_RTS__UART3_RTS 0x0
+ >;
+ };
+ };
+};
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 5/8] ARM: dts: imx27 phyCARD-S pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Enable pinctrl for phyCARD-S devices.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 10 ++++++++++
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 5a31c77..505e688 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -54,6 +54,8 @@
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
rtc@51 {
@@ -69,6 +71,8 @@
};
&owire {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_owire1_1>;
status = "okay";
};
@@ -79,15 +83,21 @@
&uart1 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1 &pinctrl_uart2_rtscts_1>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
index c8d57d1..0cee738 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -30,10 +30,14 @@
};
&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_1>;
status = "okay";
};
&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
at24@52 {
--
1.8.4.rc3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 5/8] ARM: dts: imx27 phyCARD-S pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Enable pinctrl for phyCARD-S devices.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 10 ++++++++++
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 5a31c77..505e688 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -54,6 +54,8 @@
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
rtc at 51 {
@@ -69,6 +71,8 @@
};
&owire {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_owire1_1>;
status = "okay";
};
@@ -79,15 +83,21 @@
&uart1 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1 &pinctrl_uart2_rtscts_1>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
index c8d57d1..0cee738 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -30,10 +30,14 @@
};
&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_1>;
status = "okay";
};
&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
at24 at 52 {
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 6/8] ARM: dts: imx27 phycore move uart1 to rdk
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
uart1 is not used on SOM. It is passed directly to the rdk board.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 1 +
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 4 ----
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 0fc6551..ad76d88 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -29,6 +29,7 @@
&uart1 {
fsl,uart-has-rtscts;
+ status = "okay";
};
&uart2 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 4ec402c..648541a 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -165,10 +165,6 @@
status = "okay";
};
-&uart1 {
- status = "okay";
-};
-
&weim {
status = "okay";
--
1.8.4.rc3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 6/8] ARM: dts: imx27 phycore move uart1 to rdk
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
uart1 is not used on SOM. It is passed directly to the rdk board.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 1 +
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 4 ----
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 0fc6551..ad76d88 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -29,6 +29,7 @@
&uart1 {
fsl,uart-has-rtscts;
+ status = "okay";
};
&uart2 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 4ec402c..648541a 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -165,10 +165,6 @@
status = "okay";
};
-&uart1 {
- status = "okay";
-};
-
&weim {
status = "okay";
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 7/8] ARM: dts: imx27 phycore pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Enable pinctrl for phycore devices.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ++++
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index ad76d88..d4e1022 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -29,11 +29,15 @@
&uart1 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1 &pinctrl_uart2_rtscts_1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 648541a..1aafc0d 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -135,11 +135,15 @@
&fec {
phy-reset-gpios = <&gpio3 30 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
at24@52 {
--
1.8.4.rc3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 7/8] ARM: dts: imx27 phycore pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Enable pinctrl for phycore devices.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ++++
arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index ad76d88..d4e1022 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -29,11 +29,15 @@
&uart1 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1 &pinctrl_uart2_rtscts_1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 648541a..1aafc0d 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -135,11 +135,15 @@
&fec {
phy-reset-gpios = <&gpio3 30 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
at24 at 52 {
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 8/8] ARM: imx27: enable pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 9:00 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/mach-imx/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 29a8af6..58726d5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -121,6 +121,8 @@ config SOC_IMX27
select IMX_HAVE_IOMUX_V1
select MACH_MX27
select MXC_AVIC
+ select PINCTRL
+ select PINCTRL_IMX27
config SOC_IMX31
bool
--
1.8.4.rc3
--
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v6 8/8] ARM: imx27: enable pinctrl
@ 2013-10-28 9:00 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 29a8af6..58726d5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -121,6 +121,8 @@ config SOC_IMX27
select IMX_HAVE_IOMUX_V1
select MACH_MX27
select MXC_AVIC
+ select PINCTRL
+ select PINCTRL_IMX27
config SOC_IMX31
bool
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-28 11:17 ` Kumar Gala
-1 siblings, 0 replies; 72+ messages in thread
From: Kumar Gala @ 2013-10-28 11:17 UTC (permalink / raw)
To: Markus Pargmann
Cc: devicetree, Sascha Hauer, Linus Walleij, Matt Sealey, Shawn Guo,
linux-arm-kernel
On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
> drivers/pinctrl/Kconfig | 8 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
> 4 files changed, 575 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> create mode 100644 drivers/pinctrl/pinctrl-imx27.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> new file mode 100644
> index 0000000..32c81c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> @@ -0,0 +1,89 @@
> +* Freescale IMX27 IOMUX Controller
> +
> +Required properties:
> +- compatible: "fsl,imx27-iomuxc"
> +
> +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
> +
> +Required properties for pin configuration node:
> +- fsl,pins: three integers array, represents a group of pins mux and config
> + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
> +
> + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
> + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
> + number on the specific port (between 0 and 31).
I might be coming late to this, so feel free to ignore if this has already been discussed.
Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
> +
> + MUX_ID is
> + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
> +
> + function: 0 - Primary function
> + 1 - Alternate function
> + 2 - GPIO
> + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
> +
> + direction: 0 - Input
> + 1 - Output
> + Register DDIR
> +
> + gpio_oconf: 0 - A_IN
> + 1 - B_IN
> + 2 - C_IN
> + 3 - Data Register
what does this mean?
> + Registers OCR1 and OCR2
> +
> + gpio_iconfa/b: 0 - GPIO_IN
> + 1 - Interrupt Status Register
> + 2 - 0
> + 3 - 1
What does any of these option mean (especially 2 & 3)?
> + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
> +
> +
Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
> + CONFIG can be 0 or 1, meaning Pullup disable/enable.
just for clarity do:
CONFIG: 0 - Pullup disabled
1 - Pullup enabled
> +
> +
> +
> +
> +Example:
> +
> +iomuxc: iomuxc@10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + uart {
> + pinctrl_uart1: uart-1 {
> + fsl,pins = <
> + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
> + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
> + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
> + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
> + >;
> + };
> +
> + ...
> + };
> +};
> +
> +
> +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
> +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
> +are defined in the i.MX27 reference manual.
> +
> +The above example using macros:
> +
> +iomuxc: iomuxc@10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + uart {
> + pinctrl_uart1: uart-1 {
> + fsl,pins = <
> + MX27_PAD_UART1_TXD__UART1_TXD 0x0
> + MX27_PAD_UART1_RXD__UART1_RXD 0x0
> + MX27_PAD_UART1_CTS__UART1_CTS 0x0
> + MX27_PAD_UART1_RTS__UART1_RTS 0x0
> + >;
> + };
> +
> + ...
> + };
> +};
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-28 11:17 ` Kumar Gala
0 siblings, 0 replies; 72+ messages in thread
From: Kumar Gala @ 2013-10-28 11:17 UTC (permalink / raw)
To: linux-arm-kernel
On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
> drivers/pinctrl/Kconfig | 8 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
> 4 files changed, 575 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> create mode 100644 drivers/pinctrl/pinctrl-imx27.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> new file mode 100644
> index 0000000..32c81c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> @@ -0,0 +1,89 @@
> +* Freescale IMX27 IOMUX Controller
> +
> +Required properties:
> +- compatible: "fsl,imx27-iomuxc"
> +
> +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
> +
> +Required properties for pin configuration node:
> +- fsl,pins: three integers array, represents a group of pins mux and config
> + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
> +
> + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
> + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
> + number on the specific port (between 0 and 31).
I might be coming late to this, so feel free to ignore if this has already been discussed.
Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
> +
> + MUX_ID is
> + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
> +
> + function: 0 - Primary function
> + 1 - Alternate function
> + 2 - GPIO
> + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
> +
> + direction: 0 - Input
> + 1 - Output
> + Register DDIR
> +
> + gpio_oconf: 0 - A_IN
> + 1 - B_IN
> + 2 - C_IN
> + 3 - Data Register
what does this mean?
> + Registers OCR1 and OCR2
> +
> + gpio_iconfa/b: 0 - GPIO_IN
> + 1 - Interrupt Status Register
> + 2 - 0
> + 3 - 1
What does any of these option mean (especially 2 & 3)?
> + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
> +
> +
Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
> + CONFIG can be 0 or 1, meaning Pullup disable/enable.
just for clarity do:
CONFIG: 0 - Pullup disabled
1 - Pullup enabled
> +
> +
> +
> +
> +Example:
> +
> +iomuxc: iomuxc at 10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + uart {
> + pinctrl_uart1: uart-1 {
> + fsl,pins = <
> + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
> + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
> + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
> + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
> + >;
> + };
> +
> + ...
> + };
> +};
> +
> +
> +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
> +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
> +are defined in the i.MX27 reference manual.
> +
> +The above example using macros:
> +
> +iomuxc: iomuxc at 10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + uart {
> + pinctrl_uart1: uart-1 {
> + fsl,pins = <
> + MX27_PAD_UART1_TXD__UART1_TXD 0x0
> + MX27_PAD_UART1_RXD__UART1_RXD 0x0
> + MX27_PAD_UART1_CTS__UART1_CTS 0x0
> + MX27_PAD_UART1_RTS__UART1_RTS 0x0
> + >;
> + };
> +
> + ...
> + };
> +};
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 11:17 ` Kumar Gala
@ 2013-10-28 16:43 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 16:43 UTC (permalink / raw)
To: Kumar Gala
Cc: Linus Walleij, Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Oct 28, 2013 at 06:17:41AM -0500, Kumar Gala wrote:
>
> On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
>
> > imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> > similar to other imx pincontrol drivers.
> >
> > Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > ---
> > .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
> > drivers/pinctrl/Kconfig | 8 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
> > 4 files changed, 575 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > create mode 100644 drivers/pinctrl/pinctrl-imx27.c
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > new file mode 100644
> > index 0000000..32c81c8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > @@ -0,0 +1,89 @@
> > +* Freescale IMX27 IOMUX Controller
> > +
> > +Required properties:
> > +- compatible: "fsl,imx27-iomuxc"
> > +
> > +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
>
> Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
Okay.
>
> > +
> > +Required properties for pin configuration node:
> > +- fsl,pins: three integers array, represents a group of pins mux and config
> > + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
> > +
> > + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
> > + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
> > + number on the specific port (between 0 and 31).
>
> I might be coming late to this, so feel free to ignore if this has already been discussed.
>
> Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
The port is still visible in the pin id as each port has 32 pins = 0x20.
So the ports start at 0x00, 0x20, 0x40, 0x60, 0x80 and 0xa0. So I am not
sure if it is necessary to seperate PORT and PORT_PIN, I personally
prefer only one PIN_ID field.
>
> > +
> > + MUX_ID is
> > + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
> > +
> > + function: 0 - Primary function
> > + 1 - Alternate function
> > + 2 - GPIO
> > + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
> > +
> > + direction: 0 - Input
> > + 1 - Output
> > + Register DDIR
> > +
> > + gpio_oconf: 0 - A_IN
> > + 1 - B_IN
> > + 2 - C_IN
> > + 3 - Data Register
>
> what does this mean?
These are additional output configurations for GPIO. 3 is normal GPIO,
0-2 are other pinfunctions that are mapped as output to this pin. It is
described in the i.MX27 reference manual in detail.
>
> > + Registers OCR1 and OCR2
> > +
> > + gpio_iconfa/b: 0 - GPIO_IN
> > + 1 - Interrupt Status Register
> > + 2 - 0
> > + 3 - 1
>
> What does any of these option mean (especially 2 & 3)?
This is the input configuration for a pin in GPIO mode. 0 will connect
it to GPIO input of the pad, 1 to the interrupt status register, 2 and 3
to constant low or high.
>
> > + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
> > +
> > +
>
> Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
I will add a little bit more documentation here. But in general the
corresponding reference manual chapters should be used to create a
correct MUX_ID. I don't think DT binding documentation is the right
place to describe the hardware.
>
> > + CONFIG can be 0 or 1, meaning Pullup disable/enable.
>
> just for clarity do:
> CONFIG: 0 - Pullup disabled
> 1 - Pullup enabled
Okay, will change.
Thanks,
Markus Pargmann
>
> > +
> > +
> > +
> > +
> > +Example:
> > +
> > +iomuxc: iomuxc@10015000 {
> > + compatible = "fsl,imx27-iomuxc";
> > + reg = <0x10015000 0x600>;
> > +
> > + uart {
> > + pinctrl_uart1: uart-1 {
> > + fsl,pins = <
> > + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
> > + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
> > + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
> > + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
> > + >;
> > + };
> > +
> > + ...
> > + };
> > +};
> > +
> > +
> > +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
> > +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
> > +are defined in the i.MX27 reference manual.
>
>
> > +
> > +The above example using macros:
> > +
> > +iomuxc: iomuxc@10015000 {
> > + compatible = "fsl,imx27-iomuxc";
> > + reg = <0x10015000 0x600>;
> > +
> > + uart {
> > + pinctrl_uart1: uart-1 {
> > + fsl,pins = <
> > + MX27_PAD_UART1_TXD__UART1_TXD 0x0
> > + MX27_PAD_UART1_RXD__UART1_RXD 0x0
> > + MX27_PAD_UART1_CTS__UART1_CTS 0x0
> > + MX27_PAD_UART1_RTS__UART1_RTS 0x0
> > + >;
> > + };
> > +
> > + ...
> > + };
> > +};
>
> - k
>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-28 16:43 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-28 16:43 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 28, 2013 at 06:17:41AM -0500, Kumar Gala wrote:
>
> On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
>
> > imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> > similar to other imx pincontrol drivers.
> >
> > Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> > Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> > Acked-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> > .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
> > drivers/pinctrl/Kconfig | 8 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
> > 4 files changed, 575 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > create mode 100644 drivers/pinctrl/pinctrl-imx27.c
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > new file mode 100644
> > index 0000000..32c81c8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
> > @@ -0,0 +1,89 @@
> > +* Freescale IMX27 IOMUX Controller
> > +
> > +Required properties:
> > +- compatible: "fsl,imx27-iomuxc"
> > +
> > +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
>
> Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
Okay.
>
> > +
> > +Required properties for pin configuration node:
> > +- fsl,pins: three integers array, represents a group of pins mux and config
> > + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
> > +
> > + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
> > + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
> > + number on the specific port (between 0 and 31).
>
> I might be coming late to this, so feel free to ignore if this has already been discussed.
>
> Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
The port is still visible in the pin id as each port has 32 pins = 0x20.
So the ports start at 0x00, 0x20, 0x40, 0x60, 0x80 and 0xa0. So I am not
sure if it is necessary to seperate PORT and PORT_PIN, I personally
prefer only one PIN_ID field.
>
> > +
> > + MUX_ID is
> > + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
> > +
> > + function: 0 - Primary function
> > + 1 - Alternate function
> > + 2 - GPIO
> > + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
> > +
> > + direction: 0 - Input
> > + 1 - Output
> > + Register DDIR
> > +
> > + gpio_oconf: 0 - A_IN
> > + 1 - B_IN
> > + 2 - C_IN
> > + 3 - Data Register
>
> what does this mean?
These are additional output configurations for GPIO. 3 is normal GPIO,
0-2 are other pinfunctions that are mapped as output to this pin. It is
described in the i.MX27 reference manual in detail.
>
> > + Registers OCR1 and OCR2
> > +
> > + gpio_iconfa/b: 0 - GPIO_IN
> > + 1 - Interrupt Status Register
> > + 2 - 0
> > + 3 - 1
>
> What does any of these option mean (especially 2 & 3)?
This is the input configuration for a pin in GPIO mode. 0 will connect
it to GPIO input of the pad, 1 to the interrupt status register, 2 and 3
to constant low or high.
>
> > + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
> > +
> > +
>
> Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
I will add a little bit more documentation here. But in general the
corresponding reference manual chapters should be used to create a
correct MUX_ID. I don't think DT binding documentation is the right
place to describe the hardware.
>
> > + CONFIG can be 0 or 1, meaning Pullup disable/enable.
>
> just for clarity do:
> CONFIG: 0 - Pullup disabled
> 1 - Pullup enabled
Okay, will change.
Thanks,
Markus Pargmann
>
> > +
> > +
> > +
> > +
> > +Example:
> > +
> > +iomuxc: iomuxc at 10015000 {
> > + compatible = "fsl,imx27-iomuxc";
> > + reg = <0x10015000 0x600>;
> > +
> > + uart {
> > + pinctrl_uart1: uart-1 {
> > + fsl,pins = <
> > + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
> > + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
> > + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
> > + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
> > + >;
> > + };
> > +
> > + ...
> > + };
> > +};
> > +
> > +
> > +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
> > +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
> > +are defined in the i.MX27 reference manual.
>
>
> > +
> > +The above example using macros:
> > +
> > +iomuxc: iomuxc at 10015000 {
> > + compatible = "fsl,imx27-iomuxc";
> > + reg = <0x10015000 0x600>;
> > +
> > + uart {
> > + pinctrl_uart1: uart-1 {
> > + fsl,pins = <
> > + MX27_PAD_UART1_TXD__UART1_TXD 0x0
> > + MX27_PAD_UART1_RXD__UART1_RXD 0x0
> > + MX27_PAD_UART1_CTS__UART1_CTS 0x0
> > + MX27_PAD_UART1_RTS__UART1_RTS 0x0
> > + >;
> > + };
> > +
> > + ...
> > + };
> > +};
>
> - k
>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 16:43 ` Markus Pargmann
@ 2013-10-28 19:28 ` Kumar Gala
-1 siblings, 0 replies; 72+ messages in thread
From: Kumar Gala @ 2013-10-28 19:28 UTC (permalink / raw)
To: Markus Pargmann
Cc: Linus Walleij, Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Oct 28, 2013, at 11:43 AM, Markus Pargmann wrote:
> On Mon, Oct 28, 2013 at 06:17:41AM -0500, Kumar Gala wrote:
>>
>> On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
>>
>>> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
>>> similar to other imx pincontrol drivers.
>>>
>>> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>>> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>>> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> ---
>>> .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
>>> drivers/pinctrl/Kconfig | 8 +
>>> drivers/pinctrl/Makefile | 1 +
>>> drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
>>> 4 files changed, 575 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> create mode 100644 drivers/pinctrl/pinctrl-imx27.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> new file mode 100644
>>> index 0000000..32c81c8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> @@ -0,0 +1,89 @@
>>> +* Freescale IMX27 IOMUX Controller
>>> +
>>> +Required properties:
>>> +- compatible: "fsl,imx27-iomuxc"
>>> +
>>> +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
>>
>> Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
>
> Okay.
>
>>
>>> +
>>> +Required properties for pin configuration node:
>>> +- fsl,pins: three integers array, represents a group of pins mux and config
>>> + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
>>> +
>>> + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
>>> + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
>>> + number on the specific port (between 0 and 31).
>>
>> I might be coming late to this, so feel free to ignore if this has already been discussed.
>>
>> Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
>
> The port is still visible in the pin id as each port has 32 pins = 0x20.
> So the ports start at 0x00, 0x20, 0x40, 0x60, 0x80 and 0xa0. So I am not
> sure if it is necessary to seperate PORT and PORT_PIN, I personally
> prefer only one PIN_ID field.
It goes to readability, but I guess its hidden by the #defines in imx27-pinfunc.h
>
>>
>>> +
>>> + MUX_ID is
>>> + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
>>> +
>>> + function: 0 - Primary function
>>> + 1 - Alternate function
>>> + 2 - GPIO
>>> + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
>>> +
>>> + direction: 0 - Input
>>> + 1 - Output
>>> + Register DDIR
>>> +
>>> + gpio_oconf: 0 - A_IN
>>> + 1 - B_IN
>>> + 2 - C_IN
>>> + 3 - Data Register
>>
>> what does this mean?
>
> These are additional output configurations for GPIO. 3 is normal GPIO,
> 0-2 are other pinfunctions that are mapped as output to this pin. It is
> described in the i.MX27 reference manual in detail.
>
>>
>>> + Registers OCR1 and OCR2
>>> +
>>> + gpio_iconfa/b: 0 - GPIO_IN
>>> + 1 - Interrupt Status Register
>>> + 2 - 0
>>> + 3 - 1
>>
>> What does any of these option mean (especially 2 & 3)?
>
> This is the input configuration for a pin in GPIO mode. 0 will connect
> it to GPIO input of the pad, 1 to the interrupt status register, 2 and 3
> to constant low or high.
>
>>
>>> + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
>>> +
>>> +
>>
>> Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
>
> I will add a little bit more documentation here. But in general the
> corresponding reference manual chapters should be used to create a
> correct MUX_ID. I don't think DT binding documentation is the right
> place to describe the hardware.
I'm not asking for full detail of the ref manual, but enough that I'm not scratching my head and have to actual pull up the manual to review the binding.
>>> + CONFIG can be 0 or 1, meaning Pullup disable/enable.
>>
>> just for clarity do:
>> CONFIG: 0 - Pullup disabled
>> 1 - Pullup enabled
>
> Okay, will change.
>
> Thanks,
>
> Markus Pargmann
>
>>
>>> +
>>> +
>>> +
>>> +
>>> +Example:
>>> +
>>> +iomuxc: iomuxc@10015000 {
>>> + compatible = "fsl,imx27-iomuxc";
>>> + reg = <0x10015000 0x600>;
>>> +
>>> + uart {
>>> + pinctrl_uart1: uart-1 {
>>> + fsl,pins = <
>>> + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
>>> + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
>>> + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
>>> + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>>> + >;
>>> + };
>>> +
>>> + ...
>>> + };
>>> +};
>>> +
>>> +
>>> +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
>>> +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
>>> +are defined in the i.MX27 reference manual.
>>
>>
>>> +
>>> +The above example using macros:
>>> +
>>> +iomuxc: iomuxc@10015000 {
>>> + compatible = "fsl,imx27-iomuxc";
>>> + reg = <0x10015000 0x600>;
>>> +
>>> + uart {
>>> + pinctrl_uart1: uart-1 {
>>> + fsl,pins = <
>>> + MX27_PAD_UART1_TXD__UART1_TXD 0x0
>>> + MX27_PAD_UART1_RXD__UART1_RXD 0x0
>>> + MX27_PAD_UART1_CTS__UART1_CTS 0x0
>>> + MX27_PAD_UART1_RTS__UART1_RTS 0x0
>>> + >;
>>> + };
>>> +
>>> + ...
>>> + };
>>> +};
>>
>> - k
>>
>> --
>> Employee of Qualcomm Innovation Center, Inc.
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>>
>>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-28 19:28 ` Kumar Gala
0 siblings, 0 replies; 72+ messages in thread
From: Kumar Gala @ 2013-10-28 19:28 UTC (permalink / raw)
To: linux-arm-kernel
On Oct 28, 2013, at 11:43 AM, Markus Pargmann wrote:
> On Mon, Oct 28, 2013 at 06:17:41AM -0500, Kumar Gala wrote:
>>
>> On Oct 28, 2013, at 4:00 AM, Markus Pargmann wrote:
>>
>>> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
>>> similar to other imx pincontrol drivers.
>>>
>>> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
>>> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
>>> Acked-by: Shawn Guo <shawn.guo@linaro.org>
>>> ---
>>> .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 89 ++++
>>> drivers/pinctrl/Kconfig | 8 +
>>> drivers/pinctrl/Makefile | 1 +
>>> drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
>>> 4 files changed, 575 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> create mode 100644 drivers/pinctrl/pinctrl-imx27.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> new file mode 100644
>>> index 0000000..32c81c8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
>>> @@ -0,0 +1,89 @@
>>> +* Freescale IMX27 IOMUX Controller
>>> +
>>> +Required properties:
>>> +- compatible: "fsl,imx27-iomuxc"
>>> +
>>> +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
>>
>> Here would probably be a good point to reference "pinctrl/pinctrl-bindings.txt"
>
> Okay.
>
>>
>>> +
>>> +Required properties for pin configuration node:
>>> +- fsl,pins: three integers array, represents a group of pins mux and config
>>> + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
>>> +
>>> + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
>>> + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
>>> + number on the specific port (between 0 and 31).
>>
>> I might be coming late to this, so feel free to ignore if this has already been discussed.
>>
>> Why not encode PORT in fsl,pins so it would be <PORT PORT_PIN MUX_ID CONFIG> ?
>
> The port is still visible in the pin id as each port has 32 pins = 0x20.
> So the ports start at 0x00, 0x20, 0x40, 0x60, 0x80 and 0xa0. So I am not
> sure if it is necessary to seperate PORT and PORT_PIN, I personally
> prefer only one PIN_ID field.
It goes to readability, but I guess its hidden by the #defines in imx27-pinfunc.h
>
>>
>>> +
>>> + MUX_ID is
>>> + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
>>> +
>>> + function: 0 - Primary function
>>> + 1 - Alternate function
>>> + 2 - GPIO
>>> + Registers GIUS (GPIO In Use) and GPR (General Purpose Register)
>>> +
>>> + direction: 0 - Input
>>> + 1 - Output
>>> + Register DDIR
>>> +
>>> + gpio_oconf: 0 - A_IN
>>> + 1 - B_IN
>>> + 2 - C_IN
>>> + 3 - Data Register
>>
>> what does this mean?
>
> These are additional output configurations for GPIO. 3 is normal GPIO,
> 0-2 are other pinfunctions that are mapped as output to this pin. It is
> described in the i.MX27 reference manual in detail.
>
>>
>>> + Registers OCR1 and OCR2
>>> +
>>> + gpio_iconfa/b: 0 - GPIO_IN
>>> + 1 - Interrupt Status Register
>>> + 2 - 0
>>> + 3 - 1
>>
>> What does any of these option mean (especially 2 & 3)?
>
> This is the input configuration for a pin in GPIO mode. 0 will connect
> it to GPIO input of the pad, 1 to the interrupt status register, 2 and 3
> to constant low or high.
>
>>
>>> + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
>>> +
>>> +
>>
>> Someone should be able to reasonable read this and determine how to set MUX_ID w/o having to reference the HW manual.
>
> I will add a little bit more documentation here. But in general the
> corresponding reference manual chapters should be used to create a
> correct MUX_ID. I don't think DT binding documentation is the right
> place to describe the hardware.
I'm not asking for full detail of the ref manual, but enough that I'm not scratching my head and have to actual pull up the manual to review the binding.
>>> + CONFIG can be 0 or 1, meaning Pullup disable/enable.
>>
>> just for clarity do:
>> CONFIG: 0 - Pullup disabled
>> 1 - Pullup enabled
>
> Okay, will change.
>
> Thanks,
>
> Markus Pargmann
>
>>
>>> +
>>> +
>>> +
>>> +
>>> +Example:
>>> +
>>> +iomuxc: iomuxc at 10015000 {
>>> + compatible = "fsl,imx27-iomuxc";
>>> + reg = <0x10015000 0x600>;
>>> +
>>> + uart {
>>> + pinctrl_uart1: uart-1 {
>>> + fsl,pins = <
>>> + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
>>> + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
>>> + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
>>> + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>>> + >;
>>> + };
>>> +
>>> + ...
>>> + };
>>> +};
>>> +
>>> +
>>> +For convenience there are macros defined in imx27-pinfunc.h which provide PIN
>>> +and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
>>> +are defined in the i.MX27 reference manual.
>>
>>
>>> +
>>> +The above example using macros:
>>> +
>>> +iomuxc: iomuxc at 10015000 {
>>> + compatible = "fsl,imx27-iomuxc";
>>> + reg = <0x10015000 0x600>;
>>> +
>>> + uart {
>>> + pinctrl_uart1: uart-1 {
>>> + fsl,pins = <
>>> + MX27_PAD_UART1_TXD__UART1_TXD 0x0
>>> + MX27_PAD_UART1_RXD__UART1_RXD 0x0
>>> + MX27_PAD_UART1_CTS__UART1_CTS 0x0
>>> + MX27_PAD_UART1_RTS__UART1_RTS 0x0
>>> + >;
>>> + };
>>> +
>>> + ...
>>> + };
>>> +};
>>
>> - k
>>
>> --
>> Employee of Qualcomm Innovation Center, Inc.
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>>
>>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 1/8] pinctrl: imx1 core driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-29 13:55 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 13:55 UTC (permalink / raw)
To: Markus Pargmann
Cc: Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Core driver for register formats of imx1/imx21/imx27 processors.
>
> The pins of those processors are grouped into ports. Each port has 32
> pins. The pins mux configuration is controlled by registers with 1 or 2
> bit per pin, depending on the specific control register.
>
> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Allright, as it is a new driver and I feel sorry for it being stuck in
DT review limbo, patch applied.
Yours,
Linus Walleij
--
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 1/8] pinctrl: imx1 core driver
@ 2013-10-29 13:55 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 13:55 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> Core driver for register formats of imx1/imx21/imx27 processors.
>
> The pins of those processors are grouped into ports. Each port has 32
> pins. The pins mux configuration is controlled by registers with 1 or 2
> bit per pin, depending on the specific control register.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Allright, as it is a new driver and I feel sorry for it being stuck in
DT review limbo, patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-29 14:03 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 14:03 UTC (permalink / raw)
To: Markus Pargmann
Cc: Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
I haven't applied this since there are still comments.
(If you prefer that the imx1 driver is not applied if this one
is not applied then tell me...)
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-29 14:03 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 14:03 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
I haven't applied this since there are still comments.
(If you prefer that the imx1 driver is not applied if this one
is not applied then tell me...)
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 1/8] pinctrl: imx1 core driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-29 14:09 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 14:09 UTC (permalink / raw)
To: Markus Pargmann
Cc: Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> +static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
> + unsigned pin_id, unsigned long *config)
> +{
> + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
> +
> + *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
> +
> + return 0;
> +}
> +
> +static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
> + unsigned pin_id, unsigned long *configs,
> + unsigned num_configs)
> +{
> + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
> + const struct imx1_pinctrl_soc_info *info = ipctl->info;
> + int i;
> +
> + for (i = 0; i != num_configs; ++i) {
> + imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
> +
> + dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
> + info->pins[pin_id].name);
> + }
> +
> + return 0;
> +}
I should mention that this is only acceptable if modeled after the
other i.MX drivers. If we got a new, unrelated driver today, we
would require that it used GENERIC_PINCONF for this,
especially for something that can apparently only do
pull-up and nothing else.
The generic pinconf has standardized DT bindings and share
code with other drivers so it is generally very nice.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 1/8] pinctrl: imx1 core driver
@ 2013-10-29 14:09 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 14:09 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> +static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
> + unsigned pin_id, unsigned long *config)
> +{
> + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
> +
> + *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
> +
> + return 0;
> +}
> +
> +static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
> + unsigned pin_id, unsigned long *configs,
> + unsigned num_configs)
> +{
> + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
> + const struct imx1_pinctrl_soc_info *info = ipctl->info;
> + int i;
> +
> + for (i = 0; i != num_configs; ++i) {
> + imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
> +
> + dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
> + info->pins[pin_id].name);
> + }
> +
> + return 0;
> +}
I should mention that this is only acceptable if modeled after the
other i.MX drivers. If we got a new, unrelated driver today, we
would require that it used GENERIC_PINCONF for this,
especially for something that can apparently only do
pull-up and nothing else.
The generic pinconf has standardized DT bindings and share
code with other drivers so it is generally very nice.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-10-28 9:00 ` Markus Pargmann
@ 2013-10-29 14:32 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-29 14:32 UTC (permalink / raw)
To: Linus Walleij, Shawn Guo
Cc: Sascha Hauer, Matt Sealey, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Hi,
another binding documentation update. The MUX_ID components are described more
detailed now.
Regards,
Markus Pargmann
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 99 +++++
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
4 files changed, 585 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
new file mode 100644
index 0000000..353eca0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -0,0 +1,99 @@
+* Freescale IMX27 IOMUX Controller
+
+Required properties:
+- compatible: "fsl,imx27-iomuxc"
+
+The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
+
+Required properties for pin configuration node:
+- fsl,pins: three integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
+
+ PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ number on the specific port (between 0 and 31).
+
+ MUX_ID is
+ function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+
+ function value is used to select the pin function.
+ Possible values:
+ 0 - Primary function
+ 1 - Alternate function
+ 2 - GPIO
+ Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
+
+ direction defines the data direction of the pin.
+ Possible values:
+ 0 - Input
+ 1 - Output
+ Register: DDIR
+
+ gpio_oconf configures the gpio submodule output signal. This does not
+ have any effect unless GPIO function is selected. A/B/C_IN are output
+ signals of function blocks A,B and C. Specific function blocks are
+ described in the reference manual.
+ Possible values:
+ 0 - A_IN
+ 1 - B_IN
+ 2 - C_IN
+ 3 - Data Register
+ Registers: OCR1, OCR2
+
+ gpio_iconfa/b configures the gpio submodule input to functionblocks A and
+ B. GPIO function should be selected if this is configured.
+ Possible values:
+ 0 - GPIO_IN
+ 1 - Interrupt Status Register
+ 2 - Pulldown
+ 3 - Pullup
+ Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
+
+ CONFIG can be 0 or 1, meaning Pullup disable/enable.
+
+
+
+Example:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
+ 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
+ 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
+ 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
+ >;
+ };
+
+ ...
+ };
+};
+
+
+For convenience there are macros defined in imx27-pinfunc.h which provide PIN
+and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
+are defined in the i.MX27 reference manual.
+
+The above example using macros:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ ...
+ };
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8a02aa0..4c3e5d2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -85,6 +85,14 @@ config PINCTRL_IMX1_CORE
select PINMUX
select PINCONF
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d7caf08..5d23b71 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
new file mode 100644
index 0000000..417c992
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -0,0 +1,477 @@
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
+ MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
+ MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
+ MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
+ MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
+ MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
+ MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
+ MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
+ MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
+ MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
+ MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
+ MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
+ MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
+ MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
+ MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
+ MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
+ MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
+ MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
+ MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
+ MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+struct imx27_pinctrl_private {
+ int num_gpio_childs;
+ struct platform_device **gpio_dev;
+ struct mxc_gpio_platform_data *gpio_pdata;
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.8.4.rc3
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-29 14:32 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-29 14:32 UTC (permalink / raw)
To: linux-arm-kernel
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
Hi,
another binding documentation update. The MUX_ID components are described more
detailed now.
Regards,
Markus Pargmann
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 99 +++++
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++
4 files changed, 585 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-imx27.c
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
new file mode 100644
index 0000000..353eca0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -0,0 +1,99 @@
+* Freescale IMX27 IOMUX Controller
+
+Required properties:
+- compatible: "fsl,imx27-iomuxc"
+
+The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
+
+Required properties for pin configuration node:
+- fsl,pins: three integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
+
+ PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ number on the specific port (between 0 and 31).
+
+ MUX_ID is
+ function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+
+ function value is used to select the pin function.
+ Possible values:
+ 0 - Primary function
+ 1 - Alternate function
+ 2 - GPIO
+ Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
+
+ direction defines the data direction of the pin.
+ Possible values:
+ 0 - Input
+ 1 - Output
+ Register: DDIR
+
+ gpio_oconf configures the gpio submodule output signal. This does not
+ have any effect unless GPIO function is selected. A/B/C_IN are output
+ signals of function blocks A,B and C. Specific function blocks are
+ described in the reference manual.
+ Possible values:
+ 0 - A_IN
+ 1 - B_IN
+ 2 - C_IN
+ 3 - Data Register
+ Registers: OCR1, OCR2
+
+ gpio_iconfa/b configures the gpio submodule input to functionblocks A and
+ B. GPIO function should be selected if this is configured.
+ Possible values:
+ 0 - GPIO_IN
+ 1 - Interrupt Status Register
+ 2 - Pulldown
+ 3 - Pullup
+ Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
+
+ CONFIG can be 0 or 1, meaning Pullup disable/enable.
+
+
+
+Example:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
+ 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
+ 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
+ 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
+ >;
+ };
+
+ ...
+ };
+};
+
+
+For convenience there are macros defined in imx27-pinfunc.h which provide PIN
+and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
+are defined in the i.MX27 reference manual.
+
+The above example using macros:
+
+iomuxc: iomuxc at 10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ ...
+ };
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8a02aa0..4c3e5d2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -85,6 +85,14 @@ config PINCTRL_IMX1_CORE
select PINMUX
select PINCONF
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d7caf08..5d23b71 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
new file mode 100644
index 0000000..417c992
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -0,0 +1,477 @@
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
+ MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
+ MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
+ MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
+ MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
+ MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
+ MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
+ MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
+ MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
+ MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
+ MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
+ MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
+ MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
+ MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
+ MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
+ MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
+ MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
+ MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
+ MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
+ MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+struct imx27_pinctrl_private {
+ int num_gpio_childs;
+ struct platform_device **gpio_dev;
+ struct mxc_gpio_platform_data *gpio_pdata;
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v6 1/8] pinctrl: imx1 core driver
2013-10-29 13:55 ` Linus Walleij
@ 2013-10-29 15:10 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-29 15:10 UTC (permalink / raw)
To: Linus Walleij
Cc: Shawn Guo, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tue, Oct 29, 2013 at 02:55:56PM +0100, Linus Walleij wrote:
> On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>
> > Core driver for register formats of imx1/imx21/imx27 processors.
> >
> > The pins of those processors are grouped into ports. Each port has 32
> > pins. The pins mux configuration is controlled by registers with 1 or 2
> > bit per pin, depending on the specific control register.
> >
> > Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Allright, as it is a new driver and I feel sorry for it being stuck in
> DT review limbo, patch applied.
Thanks for applying.
Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 1/8] pinctrl: imx1 core driver
@ 2013-10-29 15:10 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-10-29 15:10 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 29, 2013 at 02:55:56PM +0100, Linus Walleij wrote:
> On Mon, Oct 28, 2013 at 10:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
>
> > Core driver for register formats of imx1/imx21/imx27 processors.
> >
> > The pins of those processors are grouped into ports. Each port has 32
> > pins. The pins mux configuration is controlled by registers with 1 or 2
> > bit per pin, depending on the specific control register.
> >
> > Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> > Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> > Acked-by: Shawn Guo <shawn.guo@linaro.org>
>
> Allright, as it is a new driver and I feel sorry for it being stuck in
> DT review limbo, patch applied.
Thanks for applying.
Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-10-29 14:32 ` Markus Pargmann
@ 2013-10-29 16:00 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 16:00 UTC (permalink / raw)
To: Markus Pargmann
Cc: Shawn Guo, Sascha Hauer, Matt Sealey, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Hi,
>
> another binding documentation update. The MUX_ID components are described more
> detailed now.
Patch tentatively applied unless someone has very fundamental
issues with it, it stays in. I really want a full transfer of i.MX
pin controllers to the subsystem, using device tree so we can
get rid of the old i.MX cruft in arch/arm.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-10-29 16:00 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-10-29 16:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> similar to other imx pincontrol drivers.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> Hi,
>
> another binding documentation update. The MUX_ID components are described more
> detailed now.
Patch tentatively applied unless someone has very fundamental
issues with it, it stays in. I really want a full transfer of i.MX
pin controllers to the subsystem, using device tree so we can
get rid of the old i.MX cruft in arch/arm.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 0/8] ARM: imx27 pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-11-06 12:49 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-06 12:49 UTC (permalink / raw)
To: Shawn Guo
Cc: Linus Walleij, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Shawn,
On Mon, Oct 28, 2013 at 10:00:35AM +0100, Markus Pargmann wrote:
> Hi,
>
> v6 updates the binding documentation.
>
> this series implements a imx27 pinctrl driver. imx1/21/27 have a register
> format that is not compatible with the rest of imx series processors. The
> series adds a imx1 core driver for the different register layout.
>
> Regards,
>
> Markus
>
>
> Markus Pargmann (8):
> pinctrl: imx1 core driver
> pinctrl: imx27: imx27 pincontrol driver
> ARM: dts: imx27 pin functions
> ARM: dts: imx27 pinctrl
> ARM: dts: imx27 phyCARD-S pinctrl
> ARM: dts: imx27 phycore move uart1 to rdk
> ARM: dts: imx27 phycore pinctrl
> ARM: imx27: enable pinctrl
Linus applied the first two patches. Could you take the others?
Thanks,
Markus Pargmann
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 0/8] ARM: imx27 pinctrl
@ 2013-11-06 12:49 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-06 12:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
On Mon, Oct 28, 2013 at 10:00:35AM +0100, Markus Pargmann wrote:
> Hi,
>
> v6 updates the binding documentation.
>
> this series implements a imx27 pinctrl driver. imx1/21/27 have a register
> format that is not compatible with the rest of imx series processors. The
> series adds a imx1 core driver for the different register layout.
>
> Regards,
>
> Markus
>
>
> Markus Pargmann (8):
> pinctrl: imx1 core driver
> pinctrl: imx27: imx27 pincontrol driver
> ARM: dts: imx27 pin functions
> ARM: dts: imx27 pinctrl
> ARM: dts: imx27 phyCARD-S pinctrl
> ARM: dts: imx27 phycore move uart1 to rdk
> ARM: dts: imx27 phycore pinctrl
> ARM: imx27: enable pinctrl
Linus applied the first two patches. Could you take the others?
Thanks,
Markus Pargmann
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 0/8] ARM: imx27 pinctrl
2013-11-06 12:49 ` Markus Pargmann
@ 2013-11-06 13:27 ` Shawn Guo
-1 siblings, 0 replies; 72+ messages in thread
From: Shawn Guo @ 2013-11-06 13:27 UTC (permalink / raw)
To: Markus Pargmann
Cc: Linus Walleij, Sascha Hauer, Matt Sealey,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 06, 2013 at 01:49:06PM +0100, Markus Pargmann wrote:
> > Markus Pargmann (8):
> > pinctrl: imx1 core driver
> > pinctrl: imx27: imx27 pincontrol driver
> > ARM: dts: imx27 pin functions
> > ARM: dts: imx27 pinctrl
> > ARM: dts: imx27 phyCARD-S pinctrl
> > ARM: dts: imx27 phycore move uart1 to rdk
> > ARM: dts: imx27 phycore pinctrl
> > ARM: imx27: enable pinctrl
>
> Linus applied the first two patches. Could you take the others?
Oh, we just changed all IMX dts pinctrl nodes to be board specific with
series [1], which is now available on branch below. Can you please
respin your patches to use the new approach?
git://git.linaro.org/people/shawnguo/linux-2.6.git for-next
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/277649
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 0/8] ARM: imx27 pinctrl
@ 2013-11-06 13:27 ` Shawn Guo
0 siblings, 0 replies; 72+ messages in thread
From: Shawn Guo @ 2013-11-06 13:27 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 06, 2013 at 01:49:06PM +0100, Markus Pargmann wrote:
> > Markus Pargmann (8):
> > pinctrl: imx1 core driver
> > pinctrl: imx27: imx27 pincontrol driver
> > ARM: dts: imx27 pin functions
> > ARM: dts: imx27 pinctrl
> > ARM: dts: imx27 phyCARD-S pinctrl
> > ARM: dts: imx27 phycore move uart1 to rdk
> > ARM: dts: imx27 phycore pinctrl
> > ARM: imx27: enable pinctrl
>
> Linus applied the first two patches. Could you take the others?
Oh, we just changed all IMX dts pinctrl nodes to be board specific with
series [1], which is now available on branch below. Can you please
respin your patches to use the new approach?
git://git.linaro.org/people/shawnguo/linux-2.6.git for-next
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/277649
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-10-29 16:00 ` Linus Walleij
@ 2013-11-06 16:54 ` Matt Sealey
-1 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-06 16:54 UTC (permalink / raw)
To: Linus Walleij
Cc: Markus Pargmann, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tue, Oct 29, 2013 at 11:00 AM, Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>
>> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
>> similar to other imx pincontrol drivers.
>>
>> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>> Hi,
>>
>> another binding documentation update. The MUX_ID components are described more
>> detailed now.
>
> Patch tentatively applied unless someone has very fundamental
> issues with it, it stays in. I really want a full transfer of i.MX
> pin controllers to the subsystem, using device tree so we can
> get rid of the old i.MX cruft in arch/arm.
I think this is a rush-in patch. I actually read the manual last night
and found some serious weirdness.
The i.MX27 doesn't have a dedicated IOMUX controller so actually
having a whole separate node for it in the device tree - or even a
separate driver - makes very little sense. I understand pinctrl and
gpiolib are somewhat separated as software, but this is encoding a
Linuxism into the tree.
In fact, the binding will conflict with actual binding of the GPIO
(i.e. setting data, receiving interrupts) module since it's all one
register set, and the "fsl,imx27-iomuxc" compatible property does not
represent reality except to collect data in a different spot. There's
no reason for it except to cut the documentation and tree definition
in half, and have two nodes for Linux.
Would it be so bad to implement this as a regmap and have two drivers
access the same regmap on the Linux side? You don't need two nodes for
that, and the IOMUX definitions can live under the GPIO node. There is
NOTHING stopping two drivers on Linux matching the same compatible
property. Locking and coordination in software of a single IP block
used by two drivers shouldn't be arbitrated by the device tree.
Thanks,
Matt Sealey <neko-HhXTZounMxbZATc7fWT8Dg@public.gmane.org>
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-06 16:54 ` Matt Sealey
0 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-06 16:54 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 29, 2013 at 11:00 AM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
>
>> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
>> similar to other imx pincontrol drivers.
>>
>> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
>> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
>> Acked-by: Shawn Guo <shawn.guo@linaro.org>
>> ---
>> Hi,
>>
>> another binding documentation update. The MUX_ID components are described more
>> detailed now.
>
> Patch tentatively applied unless someone has very fundamental
> issues with it, it stays in. I really want a full transfer of i.MX
> pin controllers to the subsystem, using device tree so we can
> get rid of the old i.MX cruft in arch/arm.
I think this is a rush-in patch. I actually read the manual last night
and found some serious weirdness.
The i.MX27 doesn't have a dedicated IOMUX controller so actually
having a whole separate node for it in the device tree - or even a
separate driver - makes very little sense. I understand pinctrl and
gpiolib are somewhat separated as software, but this is encoding a
Linuxism into the tree.
In fact, the binding will conflict with actual binding of the GPIO
(i.e. setting data, receiving interrupts) module since it's all one
register set, and the "fsl,imx27-iomuxc" compatible property does not
represent reality except to collect data in a different spot. There's
no reason for it except to cut the documentation and tree definition
in half, and have two nodes for Linux.
Would it be so bad to implement this as a regmap and have two drivers
access the same regmap on the Linux side? You don't need two nodes for
that, and the IOMUX definitions can live under the GPIO node. There is
NOTHING stopping two drivers on Linux matching the same compatible
property. Locking and coordination in software of a single IP block
used by two drivers shouldn't be arbitrated by the device tree.
Thanks,
Matt Sealey <neko@bakuhatsu.net>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 4/8] ARM: dts: imx27 pinctrl
2013-10-28 9:00 ` Markus Pargmann
@ 2013-11-06 22:43 ` Matt Sealey
-1 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-06 22:43 UTC (permalink / raw)
To: Markus Pargmann
Cc: Linus Walleij, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Pinctrl driver node and pin group definitions for other driver nodes.
>
> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> arch/arm/boot/dts/imx27.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index b7a1c6d..641a63d 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -10,6 +10,7 @@
> */
>
> #include "skeleton.dtsi"
> +#include "imx27-pinfunc.h"
>
> / {
> aliases {
> @@ -235,6 +236,12 @@
> status = "disabled";
> };
>
> + iomuxc: iomuxc@10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + };
> +
> gpio1: gpio@10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
Linus,
Case in point, you can't have two nodes which overlap registers.
Probably the most reasonable way to effect this is to keep the GPIO
bindings, put pinctrl definitions in there (there's no reason pinctrl
and gpio drivers can't probe the same compatible property) and use
regmap internally on that single node.
On the good news side, this makes the pinctrl binding easier as every
single one would be is parented by a gpio instance (gpio1 as above,
for example), so it doesn't need to specify a port number anymore or
do any (port*32)+pin math - just a pin index within that port.
Schema guys: is the DT validator code prepped for checking for
overlapping register spaces, because this is totally undesirable
behavior in device trees..
Matt Sealey <neko-HhXTZounMxbZATc7fWT8Dg@public.gmane.org>
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
@ 2013-11-06 22:43 ` Matt Sealey
0 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-06 22:43 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> Pinctrl driver node and pin group definitions for other driver nodes.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boot/dts/imx27.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index b7a1c6d..641a63d 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -10,6 +10,7 @@
> */
>
> #include "skeleton.dtsi"
> +#include "imx27-pinfunc.h"
>
> / {
> aliases {
> @@ -235,6 +236,12 @@
> status = "disabled";
> };
>
> + iomuxc: iomuxc at 10015000 {
> + compatible = "fsl,imx27-iomuxc";
> + reg = <0x10015000 0x600>;
> +
> + };
> +
> gpio1: gpio at 10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
Linus,
Case in point, you can't have two nodes which overlap registers.
Probably the most reasonable way to effect this is to keep the GPIO
bindings, put pinctrl definitions in there (there's no reason pinctrl
and gpio drivers can't probe the same compatible property) and use
regmap internally on that single node.
On the good news side, this makes the pinctrl binding easier as every
single one would be is parented by a gpio instance (gpio1 as above,
for example), so it doesn't need to specify a port number anymore or
do any (port*32)+pin math - just a pin index within that port.
Schema guys: is the DT validator code prepped for checking for
overlapping register spaces, because this is totally undesirable
behavior in device trees..
Matt Sealey <neko@bakuhatsu.net>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-11-06 16:54 ` Matt Sealey
@ 2013-11-07 9:12 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-07 9:12 UTC (permalink / raw)
To: Matt Sealey
Cc: Linus Walleij, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
> On Tue, Oct 29, 2013 at 11:00 AM, Linus Walleij
> <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> >
> >> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> >> similar to other imx pincontrol drivers.
> >>
> >> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> >> Acked-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> >> Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >> ---
> >> Hi,
> >>
> >> another binding documentation update. The MUX_ID components are described more
> >> detailed now.
> >
> > Patch tentatively applied unless someone has very fundamental
> > issues with it, it stays in. I really want a full transfer of i.MX
> > pin controllers to the subsystem, using device tree so we can
> > get rid of the old i.MX cruft in arch/arm.
>
> I think this is a rush-in patch. I actually read the manual last night
> and found some serious weirdness.
>
> The i.MX27 doesn't have a dedicated IOMUX controller so actually
> having a whole separate node for it in the device tree - or even a
> separate driver - makes very little sense. I understand pinctrl and
> gpiolib are somewhat separated as software, but this is encoding a
> Linuxism into the tree.
>
> In fact, the binding will conflict with actual binding of the GPIO
> (i.e. setting data, receiving interrupts) module since it's all one
> register set, and the "fsl,imx27-iomuxc" compatible property does not
> represent reality except to collect data in a different spot. There's
> no reason for it except to cut the documentation and tree definition
> in half, and have two nodes for Linux.
Yes this is potentially conflicting. But in reality the used registers
are not the same. The GPIO driver uses GPIO Data Register, Data
Direction register and some interrupt registers. IOMUX is using input
configuration, output configuration, GPIO in use and data direction
registers. So it is conflicting in exactly one register that is
controlling the data direction.
>
> Would it be so bad to implement this as a regmap and have two drivers
> access the same regmap on the Linux side? You don't need two nodes for
> that, and the IOMUX definitions can live under the GPIO node. There is
> NOTHING stopping two drivers on Linux matching the same compatible
> property. Locking and coordination in software of a single IP block
> used by two drivers shouldn't be arbitrated by the device tree.
I am not sure if it is practical to use the GPIO nodes for the IOMUX
driver. There are actually 6 GPIO nodes. This would lead to 6
iomux controllers? The different pin functions may be distributed over
different controllers then.
The first version of this series [1] was designed to have a iomux node
with 6 gpio subnodes.
Regards,
Markus
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/257180/focus=257184
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-07 9:12 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-07 9:12 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
> On Tue, Oct 29, 2013 at 11:00 AM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
> > On Tue, Oct 29, 2013 at 7:32 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> >
> >> imx27 pincontrol driver using the imx1 core driver. The DT bindings are
> >> similar to other imx pincontrol drivers.
> >>
> >> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
> >> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> >> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> >> ---
> >> Hi,
> >>
> >> another binding documentation update. The MUX_ID components are described more
> >> detailed now.
> >
> > Patch tentatively applied unless someone has very fundamental
> > issues with it, it stays in. I really want a full transfer of i.MX
> > pin controllers to the subsystem, using device tree so we can
> > get rid of the old i.MX cruft in arch/arm.
>
> I think this is a rush-in patch. I actually read the manual last night
> and found some serious weirdness.
>
> The i.MX27 doesn't have a dedicated IOMUX controller so actually
> having a whole separate node for it in the device tree - or even a
> separate driver - makes very little sense. I understand pinctrl and
> gpiolib are somewhat separated as software, but this is encoding a
> Linuxism into the tree.
>
> In fact, the binding will conflict with actual binding of the GPIO
> (i.e. setting data, receiving interrupts) module since it's all one
> register set, and the "fsl,imx27-iomuxc" compatible property does not
> represent reality except to collect data in a different spot. There's
> no reason for it except to cut the documentation and tree definition
> in half, and have two nodes for Linux.
Yes this is potentially conflicting. But in reality the used registers
are not the same. The GPIO driver uses GPIO Data Register, Data
Direction register and some interrupt registers. IOMUX is using input
configuration, output configuration, GPIO in use and data direction
registers. So it is conflicting in exactly one register that is
controlling the data direction.
>
> Would it be so bad to implement this as a regmap and have two drivers
> access the same regmap on the Linux side? You don't need two nodes for
> that, and the IOMUX definitions can live under the GPIO node. There is
> NOTHING stopping two drivers on Linux matching the same compatible
> property. Locking and coordination in software of a single IP block
> used by two drivers shouldn't be arbitrated by the device tree.
I am not sure if it is practical to use the GPIO nodes for the IOMUX
driver. There are actually 6 GPIO nodes. This would lead to 6
iomux controllers? The different pin functions may be distributed over
different controllers then.
The first version of this series [1] was designed to have a iomux node
with 6 gpio subnodes.
Regards,
Markus
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/257180/focus=257184
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-11-07 9:12 ` Markus Pargmann
@ 2013-11-07 9:28 ` Lucas Stach
-1 siblings, 0 replies; 72+ messages in thread
From: Lucas Stach @ 2013-11-07 9:28 UTC (permalink / raw)
To: Markus Pargmann
Cc: Matt Sealey, Linus Walleij, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
> On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
[...]
> >
> > Would it be so bad to implement this as a regmap and have two drivers
> > access the same regmap on the Linux side? You don't need two nodes for
> > that, and the IOMUX definitions can live under the GPIO node. There is
> > NOTHING stopping two drivers on Linux matching the same compatible
> > property. Locking and coordination in software of a single IP block
> > used by two drivers shouldn't be arbitrated by the device tree.
>
> I am not sure if it is practical to use the GPIO nodes for the IOMUX
> driver. There are actually 6 GPIO nodes. This would lead to 6
> iomux controllers? The different pin functions may be distributed over
> different controllers then.
>
> The first version of this series [1] was designed to have a iomux node
> with 6 gpio subnodes.
Why was this changed? Having two different DT nodes requesting the same
IO region is certainly the wrong thing to do.
Regards,
Lucas
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-07 9:28 ` Lucas Stach
0 siblings, 0 replies; 72+ messages in thread
From: Lucas Stach @ 2013-11-07 9:28 UTC (permalink / raw)
To: linux-arm-kernel
Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
> On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
[...]
> >
> > Would it be so bad to implement this as a regmap and have two drivers
> > access the same regmap on the Linux side? You don't need two nodes for
> > that, and the IOMUX definitions can live under the GPIO node. There is
> > NOTHING stopping two drivers on Linux matching the same compatible
> > property. Locking and coordination in software of a single IP block
> > used by two drivers shouldn't be arbitrated by the device tree.
>
> I am not sure if it is practical to use the GPIO nodes for the IOMUX
> driver. There are actually 6 GPIO nodes. This would lead to 6
> iomux controllers? The different pin functions may be distributed over
> different controllers then.
>
> The first version of this series [1] was designed to have a iomux node
> with 6 gpio subnodes.
Why was this changed? Having two different DT nodes requesting the same
IO region is certainly the wrong thing to do.
Regards,
Lucas
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-11-07 9:28 ` Lucas Stach
@ 2013-11-07 10:38 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-07 10:38 UTC (permalink / raw)
To: Lucas Stach
Cc: Matt Sealey, Linus Walleij, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
> Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
> > On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
> [...]
> > >
> > > Would it be so bad to implement this as a regmap and have two drivers
> > > access the same regmap on the Linux side? You don't need two nodes for
> > > that, and the IOMUX definitions can live under the GPIO node. There is
> > > NOTHING stopping two drivers on Linux matching the same compatible
> > > property. Locking and coordination in software of a single IP block
> > > used by two drivers shouldn't be arbitrated by the device tree.
> >
> > I am not sure if it is practical to use the GPIO nodes for the IOMUX
> > driver. There are actually 6 GPIO nodes. This would lead to 6
> > iomux controllers? The different pin functions may be distributed over
> > different controllers then.
> >
> > The first version of this series [1] was designed to have a iomux node
> > with 6 gpio subnodes.
>
> Why was this changed? Having two different DT nodes requesting the same
> IO region is certainly the wrong thing to do.
It was suggested to map the same memory range from both drivers, so I
changed the layout completely. Perhaps it would have been better to keep
the DT node structure while not passing the memory to the gpio
subdevices.
Regards,
Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-07 10:38 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-07 10:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
> Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
> > On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
> [...]
> > >
> > > Would it be so bad to implement this as a regmap and have two drivers
> > > access the same regmap on the Linux side? You don't need two nodes for
> > > that, and the IOMUX definitions can live under the GPIO node. There is
> > > NOTHING stopping two drivers on Linux matching the same compatible
> > > property. Locking and coordination in software of a single IP block
> > > used by two drivers shouldn't be arbitrated by the device tree.
> >
> > I am not sure if it is practical to use the GPIO nodes for the IOMUX
> > driver. There are actually 6 GPIO nodes. This would lead to 6
> > iomux controllers? The different pin functions may be distributed over
> > different controllers then.
> >
> > The first version of this series [1] was designed to have a iomux node
> > with 6 gpio subnodes.
>
> Why was this changed? Having two different DT nodes requesting the same
> IO region is certainly the wrong thing to do.
It was suggested to map the same memory range from both drivers, so I
changed the layout completely. Perhaps it would have been better to keep
the DT node structure while not passing the memory to the gpio
subdevices.
Regards,
Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-11-07 10:38 ` Markus Pargmann
@ 2013-11-07 16:58 ` Matt Sealey
-1 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-07 16:58 UTC (permalink / raw)
To: Markus Pargmann
Cc: Lucas Stach, Linus Walleij, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Nov 7, 2013 at 4:38 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
>> Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
>> > On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
>> [...]
>> > >
>> > > Would it be so bad to implement this as a regmap and have two drivers
>> > > access the same regmap on the Linux side? You don't need two nodes for
>> > > that, and the IOMUX definitions can live under the GPIO node. There is
>> > > NOTHING stopping two drivers on Linux matching the same compatible
>> > > property. Locking and coordination in software of a single IP block
>> > > used by two drivers shouldn't be arbitrated by the device tree.
>> >
>> > I am not sure if it is practical to use the GPIO nodes for the IOMUX
>> > driver. There are actually 6 GPIO nodes. This would lead to 6
>> > iomux controllers? The different pin functions may be distributed over
>> > different controllers then.
>> >
>> > The first version of this series [1] was designed to have a iomux node
>> > with 6 gpio subnodes.
>>
>> Why was this changed? Having two different DT nodes requesting the same
>> IO region is certainly the wrong thing to do.
>
> It was suggested to map the same memory range from both drivers, so I
> changed the layout completely. Perhaps it would have been better to keep
> the DT node structure while not passing the memory to the gpio
> subdevices.
Mapping the same memory range is a function of the driver, NOT the
device tree. The DT should match the reality of the hardware, not try
and copy the internal driver structure. I am not sure if 6 independent
GPIO ports makes sense vs. 1 single all-encompassing GPIO node.. I
don't think it affects defining GPIO or mux configuration adversely
either way.
The docs for the memory map are there's one GPIO controller, with a
bank of registers from 0x10015000 to 0x10015FFF (4KiB). Internally it
may be 6 instantiations of the same IP block inside some fabric
wrapper, but the docs don't make any assertions to this effect except
by definition of the registers (in fact, the registers are documented
once, and the locations of each port register are documented within
the block).
I would suggest just one GPIO block, which contains all the pinctrl
definitions (refering to port, pin, mux, etc. and not just pin, mux)
and the GPIO binding gets modified to specify not only the pin number
but the port as well, in the same way, so that the driver can
calculate which register offset inside the controller it uses.
That's a bit of a driver rewrite to achieve, but it'd be worth it to
preserve the design details of the hardware and letting the drivers do
the work they should be doing instead of shunting the details into the
DT unecessarily.
Matt Sealey <neko-HhXTZounMxbZATc7fWT8Dg@public.gmane.org>
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-07 16:58 ` Matt Sealey
0 siblings, 0 replies; 72+ messages in thread
From: Matt Sealey @ 2013-11-07 16:58 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 7, 2013 at 4:38 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
>> Am Donnerstag, den 07.11.2013, 10:12 +0100 schrieb Markus Pargmann:
>> > On Wed, Nov 06, 2013 at 10:54:02AM -0600, Matt Sealey wrote:
>> [...]
>> > >
>> > > Would it be so bad to implement this as a regmap and have two drivers
>> > > access the same regmap on the Linux side? You don't need two nodes for
>> > > that, and the IOMUX definitions can live under the GPIO node. There is
>> > > NOTHING stopping two drivers on Linux matching the same compatible
>> > > property. Locking and coordination in software of a single IP block
>> > > used by two drivers shouldn't be arbitrated by the device tree.
>> >
>> > I am not sure if it is practical to use the GPIO nodes for the IOMUX
>> > driver. There are actually 6 GPIO nodes. This would lead to 6
>> > iomux controllers? The different pin functions may be distributed over
>> > different controllers then.
>> >
>> > The first version of this series [1] was designed to have a iomux node
>> > with 6 gpio subnodes.
>>
>> Why was this changed? Having two different DT nodes requesting the same
>> IO region is certainly the wrong thing to do.
>
> It was suggested to map the same memory range from both drivers, so I
> changed the layout completely. Perhaps it would have been better to keep
> the DT node structure while not passing the memory to the gpio
> subdevices.
Mapping the same memory range is a function of the driver, NOT the
device tree. The DT should match the reality of the hardware, not try
and copy the internal driver structure. I am not sure if 6 independent
GPIO ports makes sense vs. 1 single all-encompassing GPIO node.. I
don't think it affects defining GPIO or mux configuration adversely
either way.
The docs for the memory map are there's one GPIO controller, with a
bank of registers from 0x10015000 to 0x10015FFF (4KiB). Internally it
may be 6 instantiations of the same IP block inside some fabric
wrapper, but the docs don't make any assertions to this effect except
by definition of the registers (in fact, the registers are documented
once, and the locations of each port register are documented within
the block).
I would suggest just one GPIO block, which contains all the pinctrl
definitions (refering to port, pin, mux, etc. and not just pin, mux)
and the GPIO binding gets modified to specify not only the pin number
but the port as well, in the same way, so that the driver can
calculate which register offset inside the controller it uses.
That's a bit of a driver rewrite to achieve, but it'd be worth it to
preserve the design details of the hardware and letting the drivers do
the work they should be doing instead of shunting the details into the
DT unecessarily.
Matt Sealey <neko@bakuhatsu.net>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 4/8] ARM: dts: imx27 pinctrl
2013-11-06 22:43 ` Matt Sealey
@ 2013-11-08 9:45 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-08 9:45 UTC (permalink / raw)
To: Matt Sealey
Cc: Markus Pargmann, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 6, 2013 at 11:43 PM, Matt Sealey <neko-HhXTZounMxbZATc7fWT8Dg@public.gmane.org> wrote:
> On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>>
>> + iomuxc: iomuxc@10015000 {
>> + compatible = "fsl,imx27-iomuxc";
>> + reg = <0x10015000 0x600>;
>> +
>> + };
>> +
>> gpio1: gpio@10015000 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg = <0x10015000 0x100>;
>
> Linus,
>
> Case in point, you can't have two nodes which overlap registers.
>
> Probably the most reasonable way to effect this is to keep the GPIO
> bindings, put pinctrl definitions in there (there's no reason pinctrl
> and gpio drivers can't probe the same compatible property) and use
> regmap internally on that single node.
If the I/O region is tightly coupled across two subsystems like
that we usually merge the driver into one combined
pinctrl+gpio driver and put it into drivers/pinctrl/*.
This often solves more problems and make the code
simpler too.
An alternative if address 0x10015000- 0x100150ff is
really only used for GPIO is to map the pinctrl like
that:
reg = <0x10015100 0x500>
and rewrite all the base offset handling in the driver.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
@ 2013-11-08 9:45 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-08 9:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 6, 2013 at 11:43 PM, Matt Sealey <neko@bakuhatsu.net> wrote:
> On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
>>
>> + iomuxc: iomuxc at 10015000 {
>> + compatible = "fsl,imx27-iomuxc";
>> + reg = <0x10015000 0x600>;
>> +
>> + };
>> +
>> gpio1: gpio at 10015000 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg = <0x10015000 0x100>;
>
> Linus,
>
> Case in point, you can't have two nodes which overlap registers.
>
> Probably the most reasonable way to effect this is to keep the GPIO
> bindings, put pinctrl definitions in there (there's no reason pinctrl
> and gpio drivers can't probe the same compatible property) and use
> regmap internally on that single node.
If the I/O region is tightly coupled across two subsystems like
that we usually merge the driver into one combined
pinctrl+gpio driver and put it into drivers/pinctrl/*.
This often solves more problems and make the code
simpler too.
An alternative if address 0x10015000- 0x100150ff is
really only used for GPIO is to map the pinctrl like
that:
reg = <0x10015100 0x500>
and rewrite all the base offset handling in the driver.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 4/8] ARM: dts: imx27 pinctrl
2013-11-08 9:45 ` Linus Walleij
@ 2013-11-08 13:56 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-08 13:56 UTC (permalink / raw)
To: Linus Walleij
Cc: Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Fri, Nov 08, 2013 at 10:45:01AM +0100, Linus Walleij wrote:
> On Wed, Nov 6, 2013 at 11:43 PM, Matt Sealey <neko-HhXTZounMxbZATc7fWT8Dg@public.gmane.org> wrote:
> > On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> >>
> >> + iomuxc: iomuxc@10015000 {
> >> + compatible = "fsl,imx27-iomuxc";
> >> + reg = <0x10015000 0x600>;
> >> +
> >> + };
> >> +
> >> gpio1: gpio@10015000 {
> >> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> >> reg = <0x10015000 0x100>;
> >
> > Linus,
> >
> > Case in point, you can't have two nodes which overlap registers.
> >
> > Probably the most reasonable way to effect this is to keep the GPIO
> > bindings, put pinctrl definitions in there (there's no reason pinctrl
> > and gpio drivers can't probe the same compatible property) and use
> > regmap internally on that single node.
>
> If the I/O region is tightly coupled across two subsystems like
> that we usually merge the driver into one combined
> pinctrl+gpio driver and put it into drivers/pinctrl/*.
The gpio module does not necessarily include a pinctrl module. Most of
the imx SoCs have the same gpio function registers but without pinctrl.
They all use the same gpio driver.
>
> This often solves more problems and make the code
> simpler too.
>
> An alternative if address 0x10015000- 0x100150ff is
> really only used for GPIO is to map the pinctrl like
> that:
>
> reg = <0x10015100 0x500>
>
> and rewrite all the base offset handling in the driver.
There are 6 gpio modules in the memory region from 0x10015000 to
0x100155ff. pinctrl is in the same memory region.
I could change the bindings back to that from v1 [1]. One pinmux
controller over the full memory range (0x10015000 0x600) and the gpio
modules as subnodes using 0x100 each. This would preserve the currently
used references to the gpio nodes.
Regards,
Markus Pargmann
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/257180/focus=257184
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
@ 2013-11-08 13:56 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-08 13:56 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Nov 08, 2013 at 10:45:01AM +0100, Linus Walleij wrote:
> On Wed, Nov 6, 2013 at 11:43 PM, Matt Sealey <neko@bakuhatsu.net> wrote:
> > On Mon, Oct 28, 2013 at 4:00 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> >>
> >> + iomuxc: iomuxc at 10015000 {
> >> + compatible = "fsl,imx27-iomuxc";
> >> + reg = <0x10015000 0x600>;
> >> +
> >> + };
> >> +
> >> gpio1: gpio at 10015000 {
> >> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> >> reg = <0x10015000 0x100>;
> >
> > Linus,
> >
> > Case in point, you can't have two nodes which overlap registers.
> >
> > Probably the most reasonable way to effect this is to keep the GPIO
> > bindings, put pinctrl definitions in there (there's no reason pinctrl
> > and gpio drivers can't probe the same compatible property) and use
> > regmap internally on that single node.
>
> If the I/O region is tightly coupled across two subsystems like
> that we usually merge the driver into one combined
> pinctrl+gpio driver and put it into drivers/pinctrl/*.
The gpio module does not necessarily include a pinctrl module. Most of
the imx SoCs have the same gpio function registers but without pinctrl.
They all use the same gpio driver.
>
> This often solves more problems and make the code
> simpler too.
>
> An alternative if address 0x10015000- 0x100150ff is
> really only used for GPIO is to map the pinctrl like
> that:
>
> reg = <0x10015100 0x500>
>
> and rewrite all the base offset handling in the driver.
There are 6 gpio modules in the memory region from 0x10015000 to
0x100155ff. pinctrl is in the same memory region.
I could change the bindings back to that from v1 [1]. One pinmux
controller over the full memory range (0x10015000 0x600) and the gpio
modules as subnodes using 0x100 each. This would preserve the currently
used references to the gpio nodes.
Regards,
Markus Pargmann
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/257180/focus=257184
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
2013-11-07 10:38 ` Markus Pargmann
@ 2013-11-11 9:50 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-11 9:50 UTC (permalink / raw)
To: Markus Pargmann
Cc: Lucas Stach, Matt Sealey, Shawn Guo, Sascha Hauer, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Nov 7, 2013 at 11:38 AM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
>> > The first version of this series [1] was designed to have a iomux node
>> > with 6 gpio subnodes.
>>
>> Why was this changed? Having two different DT nodes requesting the same
>> IO region is certainly the wrong thing to do.
>
> It was suggested to map the same memory range from both drivers, so I
> changed the layout completely. Perhaps it would have been better to keep
> the DT node structure while not passing the memory to the gpio
> subdevices.
>From a pinctrl/GPIO point of view anything goes, it's a little bit like
big-endian vs little-endian.
I did merge the i.MX27 driver as it was ACKed by the subarch
maintainers.
So what do we do now, shall I revert this patch or can you refactor
it in accordance with the comments so it should be kept as a
base for the rewrite?
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v7] pinctrl: imx27: imx27 pincontrol driver
@ 2013-11-11 9:50 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-11 9:50 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 7, 2013 at 11:38 AM, Markus Pargmann <mpa@pengutronix.de> wrote:
> On Thu, Nov 07, 2013 at 10:28:01AM +0100, Lucas Stach wrote:
>> > The first version of this series [1] was designed to have a iomux node
>> > with 6 gpio subnodes.
>>
>> Why was this changed? Having two different DT nodes requesting the same
>> IO region is certainly the wrong thing to do.
>
> It was suggested to map the same memory range from both drivers, so I
> changed the layout completely. Perhaps it would have been better to keep
> the DT node structure while not passing the memory to the gpio
> subdevices.
>From a pinctrl/GPIO point of view anything goes, it's a little bit like
big-endian vs little-endian.
I did merge the i.MX27 driver as it was ACKed by the subarch
maintainers.
So what do we do now, shall I revert this patch or can you refactor
it in accordance with the comments so it should be kept as a
base for the rewrite?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v6 4/8] ARM: dts: imx27 pinctrl
2013-11-08 13:56 ` Markus Pargmann
@ 2013-11-11 10:29 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-11 10:29 UTC (permalink / raw)
To: Markus Pargmann
Cc: Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Fri, Nov 8, 2013 at 2:56 PM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Fri, Nov 08, 2013 at 10:45:01AM +0100, Linus Walleij wrote:
>> If the I/O region is tightly coupled across two subsystems like
>> that we usually merge the driver into one combined
>> pinctrl+gpio driver and put it into drivers/pinctrl/*.
>
> The gpio module does not necessarily include a pinctrl module. Most of
> the imx SoCs have the same gpio function registers but without pinctrl.
> They all use the same gpio driver.
Yeah but I'm only saying you could make a combined driver,
I didn't say you had to use both halves of it all the time.
pinctrl/pinctrl-imx1.c can very well handle both and only
supply GPIO functionality for some compatible-strings,
that's OK.
> There are 6 gpio modules in the memory region from 0x10015000 to
> 0x100155ff. pinctrl is in the same memory region.
OK I get it (I think).
> I could change the bindings back to that from v1 [1]. One pinmux
> controller over the full memory range (0x10015000 0x600) and the gpio
> modules as subnodes using 0x100 each. This would preserve the currently
> used references to the gpio nodes.
Hm I don't really have opinions on this, better let the DT-folks
say what they prefer. But that looks good to me.
Can you do this with an incremental patch?
Yours,
Linus Walleij
--
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v6 4/8] ARM: dts: imx27 pinctrl
@ 2013-11-11 10:29 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-11 10:29 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Nov 8, 2013 at 2:56 PM, Markus Pargmann <mpa@pengutronix.de> wrote:
> On Fri, Nov 08, 2013 at 10:45:01AM +0100, Linus Walleij wrote:
>> If the I/O region is tightly coupled across two subsystems like
>> that we usually merge the driver into one combined
>> pinctrl+gpio driver and put it into drivers/pinctrl/*.
>
> The gpio module does not necessarily include a pinctrl module. Most of
> the imx SoCs have the same gpio function registers but without pinctrl.
> They all use the same gpio driver.
Yeah but I'm only saying you could make a combined driver,
I didn't say you had to use both halves of it all the time.
pinctrl/pinctrl-imx1.c can very well handle both and only
supply GPIO functionality for some compatible-strings,
that's OK.
> There are 6 gpio modules in the memory region from 0x10015000 to
> 0x100155ff. pinctrl is in the same memory region.
OK I get it (I think).
> I could change the bindings back to that from v1 [1]. One pinmux
> controller over the full memory range (0x10015000 0x600) and the gpio
> modules as subnodes using 0x100 each. This would preserve the currently
> used references to the gpio nodes.
Hm I don't really have opinions on this, better let the DT-folks
say what they prefer. But that looks good to me.
Can you do this with an incremental patch?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
2013-11-11 10:29 ` Linus Walleij
@ 2013-11-11 18:19 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-11 18:19 UTC (permalink / raw)
To: Linus Walleij
Cc: Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Markus Pargmann
Support gpio devicetree subnodes to allow a more detailed DT hardware
description.
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Hi,
This is an incremental patch for the imx1-core and imx27-pinctrl patches to
support the gpio nodes as iomux subdevices.
Linus, I can resend this integrated into the other two patches if you want.
Regards,
Markus Pargmann
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 22 ++++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1-core.c | 7 +++++++
2 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
index 353eca0..d1706ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -52,12 +52,25 @@ Required properties for pin configuration node:
CONFIG can be 0 or 1, meaning Pullup disable/enable.
+The iomux controller has gpio child nodes which are embedded in the iomux
+control registers. They have to be defined as child nodes of the iomux device
+node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
+properties for the iomux device node are required.
Example:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio@10015000 {
+ ...
+ };
+
+ ...
uart {
pinctrl_uart1: uart-1 {
@@ -83,6 +96,15 @@ The above example using macros:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio@10015000 {
+ ...
+ };
+
+ ...
uart {
pinctrl_uart1: uart-1 {
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
index 4d5a9e7..2eadba7 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -638,6 +638,13 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev,
return -EINVAL;
}
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+ if (ret) {
+ pinctrl_unregister(ipctl->pctl);
+ dev_err(&pdev->dev, "Failed to populate subdevices\n");
+ return ret;
+ }
+
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return 0;
--
1.8.4.2
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^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-11 18:19 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-11 18:19 UTC (permalink / raw)
To: linux-arm-kernel
Support gpio devicetree subnodes to allow a more detailed DT hardware
description.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
---
Hi,
This is an incremental patch for the imx1-core and imx27-pinctrl patches to
support the gpio nodes as iomux subdevices.
Linus, I can resend this integrated into the other two patches if you want.
Regards,
Markus Pargmann
.../bindings/pinctrl/fsl,imx27-pinctrl.txt | 22 ++++++++++++++++++++++
drivers/pinctrl/pinctrl-imx1-core.c | 7 +++++++
2 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
index 353eca0..d1706ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
@@ -52,12 +52,25 @@ Required properties for pin configuration node:
CONFIG can be 0 or 1, meaning Pullup disable/enable.
+The iomux controller has gpio child nodes which are embedded in the iomux
+control registers. They have to be defined as child nodes of the iomux device
+node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
+properties for the iomux device node are required.
Example:
iomuxc: iomuxc at 10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio at 10015000 {
+ ...
+ };
+
+ ...
uart {
pinctrl_uart1: uart-1 {
@@ -83,6 +96,15 @@ The above example using macros:
iomuxc: iomuxc at 10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio at 10015000 {
+ ...
+ };
+
+ ...
uart {
pinctrl_uart1: uart-1 {
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
index 4d5a9e7..2eadba7 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -638,6 +638,13 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev,
return -EINVAL;
}
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+ if (ret) {
+ pinctrl_unregister(ipctl->pctl);
+ dev_err(&pdev->dev, "Failed to populate subdevices\n");
+ return ret;
+ }
+
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return 0;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH] pinctrl: imx1-core populate subdevices
2013-11-11 18:19 ` Markus Pargmann
@ 2013-11-19 20:01 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-19 20:01 UTC (permalink / raw)
To: Markus Pargmann
Cc: Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Support gpio devicetree subnodes to allow a more detailed DT hardware
> description.
>
> Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Looks good to me.
Tentatively applied this, the DT people may want to say something
about this.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-19 20:01 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2013-11-19 20:01 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann <mpa@pengutronix.de> wrote:
> Support gpio devicetree subnodes to allow a more detailed DT hardware
> description.
>
> Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Looks good to me.
Tentatively applied this, the DT people may want to say something
about this.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH] pinctrl: imx1-core populate subdevices
2013-11-19 20:01 ` Linus Walleij
@ 2013-11-27 3:33 ` Chris Ruehl
-1 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 3:33 UTC (permalink / raw)
To: Linus Walleij
Cc: Markus Pargmann, Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>
>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>> description.
>>
>> Signed-off-by: Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>
> Looks good to me.
>
> Tentatively applied this, the DT people may want to say something
> about this.
>
> Yours,
> Linus Walleij
> --
Hi,
I tried the new configuration but the kernel oops when probing the
dm9000 caused by insufficient resources more likely the real reason
that somehow the gpio6: triggers a problem
[ 0.115718] irq: no irq domain found for
/soc/aipi@10000000/iomuxc@10015000/gpio@10015500 !
[ 0.115768] ------------[ cut here ]------------
[ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
of_device_alloc+0x110/0x15c()
[ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
[ 0.121236] Failed to request board ext/int gpios
[ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
gpio6: gpio@10015500 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015500 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
Kernel Linux version 3.13.0-rc1-next-20131125-dirty
With kind regards
Chris
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-27 3:33 ` Chris Ruehl
0 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 3:33 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa@pengutronix.de> wrote:
>
>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>> description.
>>
>> Signed-off-by: Markus Pargmann<mpa@pengutronix.de>
>
> Looks good to me.
>
> Tentatively applied this, the DT people may want to say something
> about this.
>
> Yours,
> Linus Walleij
> --
Hi,
I tried the new configuration but the kernel oops when probing the
dm9000 caused by insufficient resources more likely the real reason
that somehow the gpio6: triggers a problem
[ 0.115718] irq: no irq domain found for
/soc/aipi at 10000000/iomuxc at 10015000/gpio at 10015500 !
[ 0.115768] ------------[ cut here ]------------
[ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
of_device_alloc+0x110/0x15c()
[ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
[ 0.121236] Failed to request board ext/int gpios
[ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
iomuxc: iomuxc at 10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio at 10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
gpio6: gpio at 10015500 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015500 0x100>;
interrupts = <8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
Kernel Linux version 3.13.0-rc1-next-20131125-dirty
With kind regards
Chris
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH] pinctrl: imx1-core populate subdevices
2013-11-27 3:33 ` Chris Ruehl
@ 2013-11-27 5:19 ` Chris Ruehl
-1 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 5:19 UTC (permalink / raw)
To: Linus Walleij
Cc: Markus Pargmann, Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wednesday, November 27, 2013 11:33 AM, Chris Ruehl wrote:
> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
>> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> wrote:
>>
>>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>>> description.
>>>
>>> Signed-off-by: Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>>
>> Looks good to me.
>>
>> Tentatively applied this, the DT people may want to say something
>> about this.
>>
>> Yours,
>> Linus Walleij
>> --
>
> Hi,
>
> I tried the new configuration but the kernel oops when probing the
> dm9000 caused by insufficient resources more likely the real reason
> that somehow the gpio6: triggers a problem
>
>
> [ 0.115718] irq: no irq domain found for
> /soc/aipi@10000000/iomuxc@10015000/gpio@10015500 !
> [ 0.115768] ------------[ cut here ]------------
> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
> of_device_alloc+0x110/0x15c()
> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
> [ 0.121236] Failed to request board ext/int gpios
> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
>
>
> iomuxc: iomuxc@10015000 {
> compatible = "fsl,imx27-iomuxc";
> reg = <0x10015000 0x600>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> gpio1: gpio@10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> ...
> gpio6: gpio@10015500 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015500 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> };
>
More info
board-dts-definition for the dm9000 which trigger the oops
/ {
model = "GTSYS IR module";
compatible = "gtsys,mx27gtsir","fsl,imx27";
memory {
reg = <0xa0000000 0x10000000>;
};
enet1: ethernet@d4000000 {
compatible = "davicom,dm9000";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x2
0xd4000004 0x2>;
interrupt-parent = <&gpio6>;
interrupts = <18 2>; /* DM9000IRQ IMX_GPIO_NR(6,18) 2
= high edge trigger */
local-mac-address = [00 00 00 00 00 00];
davicom,no-eeprom;
status = "okay";
};
> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>
> With kind regards
> Chris
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-27 5:19 ` Chris Ruehl
0 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 5:19 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday, November 27, 2013 11:33 AM, Chris Ruehl wrote:
> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
>> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa@pengutronix.de>
>> wrote:
>>
>>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>>> description.
>>>
>>> Signed-off-by: Markus Pargmann<mpa@pengutronix.de>
>>
>> Looks good to me.
>>
>> Tentatively applied this, the DT people may want to say something
>> about this.
>>
>> Yours,
>> Linus Walleij
>> --
>
> Hi,
>
> I tried the new configuration but the kernel oops when probing the
> dm9000 caused by insufficient resources more likely the real reason
> that somehow the gpio6: triggers a problem
>
>
> [ 0.115718] irq: no irq domain found for
> /soc/aipi at 10000000/iomuxc at 10015000/gpio at 10015500 !
> [ 0.115768] ------------[ cut here ]------------
> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
> of_device_alloc+0x110/0x15c()
> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
> [ 0.121236] Failed to request board ext/int gpios
> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
>
>
> iomuxc: iomuxc at 10015000 {
> compatible = "fsl,imx27-iomuxc";
> reg = <0x10015000 0x600>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> gpio1: gpio at 10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> ...
> gpio6: gpio at 10015500 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015500 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> };
>
More info
board-dts-definition for the dm9000 which trigger the oops
/ {
model = "GTSYS IR module";
compatible = "gtsys,mx27gtsir","fsl,imx27";
memory {
reg = <0xa0000000 0x10000000>;
};
enet1: ethernet at d4000000 {
compatible = "davicom,dm9000";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x2
0xd4000004 0x2>;
interrupt-parent = <&gpio6>;
interrupts = <18 2>; /* DM9000IRQ IMX_GPIO_NR(6,18) 2
= high edge trigger */
local-mac-address = [00 00 00 00 00 00];
davicom,no-eeprom;
status = "okay";
};
> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>
> With kind regards
> Chris
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH] pinctrl: imx1-core populate subdevices
2013-11-27 3:33 ` Chris Ruehl
@ 2013-11-27 7:31 ` Markus Pargmann
-1 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-27 7:31 UTC (permalink / raw)
To: Chris Ruehl
Cc: Linus Walleij, Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi,
On Wed, Nov 27, 2013 at 11:33:15AM +0800, Chris Ruehl wrote:
> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
> >On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> >
> >>Support gpio devicetree subnodes to allow a more detailed DT hardware
> >>description.
> >>
> >>Signed-off-by: Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> >
> >Looks good to me.
> >
> >Tentatively applied this, the DT people may want to say something
> >about this.
> >
> >Yours,
> >Linus Walleij
> >--
>
> Hi,
>
> I tried the new configuration but the kernel oops when probing the
> dm9000 caused by insufficient resources more likely the real reason
> that somehow the gpio6: triggers a problem
>
>
> [ 0.115718] irq: no irq domain found for
> /soc/aipi@10000000/iomuxc@10015000/gpio@10015500 !
> [ 0.115768] ------------[ cut here ]------------
> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
> of_device_alloc+0x110/0x15c()
> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
> [ 0.121236] Failed to request board ext/int gpios
> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
The imx27-pinctrl driver seems to be initialized after the irq is
requested. So this issue should be the same as in [1].
Regards,
Markus
[1] [PATCH] of/platform: Fix no irq domain found errors when populating interrupts
http://archive.arm.linux.org.uk/lurker/message/20131123.004335.61d5c21b.en.html
>
>
> iomuxc: iomuxc@10015000 {
> compatible = "fsl,imx27-iomuxc";
> reg = <0x10015000 0x600>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> gpio1: gpio@10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> ...
> gpio6: gpio@10015500 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015500 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> };
>
> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>
> With kind regards
> Chris
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-27 7:31 ` Markus Pargmann
0 siblings, 0 replies; 72+ messages in thread
From: Markus Pargmann @ 2013-11-27 7:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wed, Nov 27, 2013 at 11:33:15AM +0800, Chris Ruehl wrote:
> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
> >On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa@pengutronix.de> wrote:
> >
> >>Support gpio devicetree subnodes to allow a more detailed DT hardware
> >>description.
> >>
> >>Signed-off-by: Markus Pargmann<mpa@pengutronix.de>
> >
> >Looks good to me.
> >
> >Tentatively applied this, the DT people may want to say something
> >about this.
> >
> >Yours,
> >Linus Walleij
> >--
>
> Hi,
>
> I tried the new configuration but the kernel oops when probing the
> dm9000 caused by insufficient resources more likely the real reason
> that somehow the gpio6: triggers a problem
>
>
> [ 0.115718] irq: no irq domain found for
> /soc/aipi at 10000000/iomuxc at 10015000/gpio at 10015500 !
> [ 0.115768] ------------[ cut here ]------------
> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
> of_device_alloc+0x110/0x15c()
> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
> [ 0.121236] Failed to request board ext/int gpios
> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
The imx27-pinctrl driver seems to be initialized after the irq is
requested. So this issue should be the same as in [1].
Regards,
Markus
[1] [PATCH] of/platform: Fix no irq domain found errors when populating interrupts
http://archive.arm.linux.org.uk/lurker/message/20131123.004335.61d5c21b.en.html
>
>
> iomuxc: iomuxc at 10015000 {
> compatible = "fsl,imx27-iomuxc";
> reg = <0x10015000 0x600>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> gpio1: gpio at 10015000 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015000 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> ...
> gpio6: gpio at 10015500 {
> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
> reg = <0x10015500 0x100>;
> interrupts = <8>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> };
>
> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>
> With kind regards
> Chris
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH] pinctrl: imx1-core populate subdevices
2013-11-27 7:31 ` Markus Pargmann
@ 2013-11-27 8:45 ` Chris Ruehl
-1 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 8:45 UTC (permalink / raw)
To: Markus Pargmann
Cc: Linus Walleij, Matt Sealey, Shawn Guo, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wednesday, November 27, 2013 03:31 PM, Markus Pargmann wrote:
> Hi,
>
> On Wed, Nov 27, 2013 at 11:33:15AM +0800, Chris Ruehl wrote:
>> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
>>> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>>>
>>>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>>>> description.
>>>>
>>>> Signed-off-by: Markus Pargmann<mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>>>
>>> Looks good to me.
>>>
>>> Tentatively applied this, the DT people may want to say something
>>> about this.
>>>
>>> Yours,
>>> Linus Walleij
>>> --
>>
>> Hi,
>>
>> I tried the new configuration but the kernel oops when probing the
>> dm9000 caused by insufficient resources more likely the real reason
>> that somehow the gpio6: triggers a problem
>>
>>
>> [ 0.115718] irq: no irq domain found for
>> /soc/aipi@10000000/iomuxc@10015000/gpio@10015500 !
>> [ 0.115768] ------------[ cut here ]------------
>> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
>> of_device_alloc+0x110/0x15c()
>> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
>> [ 0.121236] Failed to request board ext/int gpios
>> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
>
> The imx27-pinctrl driver seems to be initialized after the irq is
> requested. So this issue should be the same as in [1].
>
> Regards,
>
> Markus
Markus,
Thank you for point this out! I patched the Linux-next and
my problems went away. I will test now a bit more..
Cheers
Chris
>
> [1] [PATCH] of/platform: Fix no irq domain found errors when populating interrupts
> http://archive.arm.linux.org.uk/lurker/message/20131123.004335.61d5c21b.en.html
>
>>
>>
>> iomuxc: iomuxc@10015000 {
>> compatible = "fsl,imx27-iomuxc";
>> reg =<0x10015000 0x600>;
>> #address-cells =<1>;
>> #size-cells =<1>;
>> ranges;
>>
>> gpio1: gpio@10015000 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg =<0x10015000 0x100>;
>> interrupts =<8>;
>> gpio-controller;
>> #gpio-cells =<2>;
>> interrupt-controller;
>> #interrupt-cells =<2>;
>> };
>> ...
>> gpio6: gpio@10015500 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg =<0x10015500 0x100>;
>> interrupts =<8>;
>> gpio-controller;
>> #gpio-cells =<2>;
>> interrupt-controller;
>> #interrupt-cells =<2>;
>> };
>> };
>>
>> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>>
>> With kind regards
>> Chris
>>
>>
>
--
GTSYS Limited RFID Technology
A01 24/F Gold King Industrial Bld
35-41 Tai Lin Pai Road, Kwai Chung, Hong Kong
Fax (852) 8167 4060 - Tel (852) 3598 9488
Disclaimer: http://www.gtsys.com.hk/email/classified.html
--
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^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH] pinctrl: imx1-core populate subdevices
@ 2013-11-27 8:45 ` Chris Ruehl
0 siblings, 0 replies; 72+ messages in thread
From: Chris Ruehl @ 2013-11-27 8:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday, November 27, 2013 03:31 PM, Markus Pargmann wrote:
> Hi,
>
> On Wed, Nov 27, 2013 at 11:33:15AM +0800, Chris Ruehl wrote:
>> On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
>>> On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmann<mpa@pengutronix.de> wrote:
>>>
>>>> Support gpio devicetree subnodes to allow a more detailed DT hardware
>>>> description.
>>>>
>>>> Signed-off-by: Markus Pargmann<mpa@pengutronix.de>
>>>
>>> Looks good to me.
>>>
>>> Tentatively applied this, the DT people may want to say something
>>> about this.
>>>
>>> Yours,
>>> Linus Walleij
>>> --
>>
>> Hi,
>>
>> I tried the new configuration but the kernel oops when probing the
>> dm9000 caused by insufficient resources more likely the real reason
>> that somehow the gpio6: triggers a problem
>>
>>
>> [ 0.115718] irq: no irq domain found for
>> /soc/aipi at 10000000/iomuxc at 10015000/gpio at 10015500 !
>> [ 0.115768] ------------[ cut here ]------------
>> [ 0.115853] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171
>> of_device_alloc+0x110/0x15c()
>> [ 0.117824] ---[ end trace 0e10ae727e6e0ab1 ]---
>> [ 0.121236] Failed to request board ext/int gpios
>> [ 0.152712] imx27-pinctrl 10015000.iomuxc: initialized IMX pinctrl driver
>
> The imx27-pinctrl driver seems to be initialized after the irq is
> requested. So this issue should be the same as in [1].
>
> Regards,
>
> Markus
Markus,
Thank you for point this out! I patched the Linux-next and
my problems went away. I will test now a bit more..
Cheers
Chris
>
> [1] [PATCH] of/platform: Fix no irq domain found errors when populating interrupts
> http://archive.arm.linux.org.uk/lurker/message/20131123.004335.61d5c21b.en.html
>
>>
>>
>> iomuxc: iomuxc at 10015000 {
>> compatible = "fsl,imx27-iomuxc";
>> reg =<0x10015000 0x600>;
>> #address-cells =<1>;
>> #size-cells =<1>;
>> ranges;
>>
>> gpio1: gpio at 10015000 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg =<0x10015000 0x100>;
>> interrupts =<8>;
>> gpio-controller;
>> #gpio-cells =<2>;
>> interrupt-controller;
>> #interrupt-cells =<2>;
>> };
>> ...
>> gpio6: gpio at 10015500 {
>> compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
>> reg =<0x10015500 0x100>;
>> interrupts =<8>;
>> gpio-controller;
>> #gpio-cells =<2>;
>> interrupt-controller;
>> #interrupt-cells =<2>;
>> };
>> };
>>
>> Kernel Linux version 3.13.0-rc1-next-20131125-dirty
>>
>> With kind regards
>> Chris
>>
>>
>
--
GTSYS Limited RFID Technology
A01 24/F Gold King Industrial Bld
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Fax (852) 8167 4060 - Tel (852) 3598 9488
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^ permalink raw reply [flat|nested] 72+ messages in thread
end of thread, other threads:[~2013-11-27 8:45 UTC | newest]
Thread overview: 72+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-10-28 9:00 [PATCH v6 0/8] ARM: imx27 pinctrl Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
[not found] ` <1382950843-26066-1-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-10-28 9:00 ` [PATCH v6 1/8] pinctrl: imx1 core driver Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
[not found] ` <1382950843-26066-2-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-10-29 13:55 ` Linus Walleij
2013-10-29 13:55 ` Linus Walleij
[not found] ` <CACRpkdZZhwYtvki-2AQFOSND4BQmOenZb6sSm2tOpQUYWwETgA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-10-29 15:10 ` Markus Pargmann
2013-10-29 15:10 ` Markus Pargmann
2013-10-29 14:09 ` Linus Walleij
2013-10-29 14:09 ` Linus Walleij
2013-10-28 9:00 ` [PATCH v6 2/8] pinctrl: imx27: imx27 pincontrol driver Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-10-28 11:17 ` Kumar Gala
2013-10-28 11:17 ` Kumar Gala
[not found] ` <B923ADBC-0C66-45D0-B9FE-F1038F93B176-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2013-10-28 16:43 ` Markus Pargmann
2013-10-28 16:43 ` Markus Pargmann
[not found] ` <20131028164338.GA20839-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-10-28 19:28 ` Kumar Gala
2013-10-28 19:28 ` Kumar Gala
[not found] ` <1382950843-26066-3-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-10-29 14:03 ` Linus Walleij
2013-10-29 14:03 ` Linus Walleij
2013-10-29 14:32 ` [PATCH v7] " Markus Pargmann
2013-10-29 14:32 ` Markus Pargmann
[not found] ` <1383057139-25304-1-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-10-29 16:00 ` Linus Walleij
2013-10-29 16:00 ` Linus Walleij
[not found] ` <CACRpkdYKgA5E4-APSTHsM=zVbb3X2R4v+V4EeK3+W1tKPR1FeA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-06 16:54 ` Matt Sealey
2013-11-06 16:54 ` Matt Sealey
[not found] ` <CAHCPf3v3dsTyk9Cd93GBLBKQLSQ+Mb0mpq134X7Ko4U8m-b-qg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-07 9:12 ` Markus Pargmann
2013-11-07 9:12 ` Markus Pargmann
[not found] ` <20131107091212.GH15098-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-07 9:28 ` Lucas Stach
2013-11-07 9:28 ` Lucas Stach
[not found] ` <1383816481.4115.2.camel-WzVe3FnzCwFR6QfukMTsflXZhhPuCNm+@public.gmane.org>
2013-11-07 10:38 ` Markus Pargmann
2013-11-07 10:38 ` Markus Pargmann
[not found] ` <20131107103859.GI15098-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-07 16:58 ` Matt Sealey
2013-11-07 16:58 ` Matt Sealey
2013-11-11 9:50 ` Linus Walleij
2013-11-11 9:50 ` Linus Walleij
2013-10-28 9:00 ` [PATCH v6 3/8] ARM: dts: imx27 pin functions Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-10-28 9:00 ` [PATCH v6 4/8] ARM: dts: imx27 pinctrl Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
[not found] ` <1382950843-26066-5-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-06 22:43 ` Matt Sealey
2013-11-06 22:43 ` Matt Sealey
[not found] ` <CAHCPf3sz6eOYrnNDfOTo5Z5dZP2U9+GtQMKYZEb-1WfuXepa6A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-08 9:45 ` Linus Walleij
2013-11-08 9:45 ` Linus Walleij
[not found] ` <CACRpkdazhujHpjVuOhee9UXfi=zV3Z7TjbxzQ_3H+gmFrgDmWA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-08 13:56 ` Markus Pargmann
2013-11-08 13:56 ` Markus Pargmann
[not found] ` <20131108135601.GA30263-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-11 10:29 ` Linus Walleij
2013-11-11 10:29 ` Linus Walleij
[not found] ` <CACRpkda2dO6DvurEhaTVGJv8nDyEGOEeLCap-_+1e1mHtD0XyQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-11 18:19 ` [PATCH] pinctrl: imx1-core populate subdevices Markus Pargmann
2013-11-11 18:19 ` Markus Pargmann
[not found] ` <1384193987-20740-1-git-send-email-mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-19 20:01 ` Linus Walleij
2013-11-19 20:01 ` Linus Walleij
[not found] ` <CACRpkdaQcY43wnfD_phsi6rCo3oUmOUcei+gb9phyGT7F1iZyA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-11-27 3:33 ` Chris Ruehl
2013-11-27 3:33 ` Chris Ruehl
[not found] ` <529567FB.5090501-CR359r9tUDPXPF5Rlphj1Q@public.gmane.org>
2013-11-27 5:19 ` Chris Ruehl
2013-11-27 5:19 ` Chris Ruehl
2013-11-27 7:31 ` Markus Pargmann
2013-11-27 7:31 ` Markus Pargmann
[not found] ` <20131127073152.GA28465-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-27 8:45 ` Chris Ruehl
2013-11-27 8:45 ` Chris Ruehl
2013-10-28 9:00 ` [PATCH v6 5/8] ARM: dts: imx27 phyCARD-S pinctrl Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-10-28 9:00 ` [PATCH v6 6/8] ARM: dts: imx27 phycore move uart1 to rdk Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-10-28 9:00 ` [PATCH v6 7/8] ARM: dts: imx27 phycore pinctrl Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-10-28 9:00 ` [PATCH v6 8/8] ARM: imx27: enable pinctrl Markus Pargmann
2013-10-28 9:00 ` Markus Pargmann
2013-11-06 12:49 ` [PATCH v6 0/8] ARM: imx27 pinctrl Markus Pargmann
2013-11-06 12:49 ` Markus Pargmann
[not found] ` <20131106124906.GG15098-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-11-06 13:27 ` Shawn Guo
2013-11-06 13:27 ` Shawn Guo
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