[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Laurent Pinchart]

Hello,

This patch set implements serial port support for the Lager reference board,
and adds early debugging support for the r8a7790 SoC.

The code is available in my git tree at

        git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager

The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've posted
earlier today.

Laurent Pinchart (3):
  ARM: shmobile: r8a7790: Add early debugging support
  ARM: shmobile: r8a7790: Add serial ports to the device tree
  ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

 arch/arm/Kconfig.debug                         |   8 ++
 arch/arm/boot/dts/r8a7790-lager.dts            |  24 +++++-
 arch/arm/boot/dts/r8a7790.dtsi                 | 100 +++++++++++++++++++++++++
 arch/arm/include/debug/r8a7790.S               |  43 +++++++++++
 arch/arm/mach-shmobile/board-lager-reference.c |  18 +----
 arch/arm/mach-shmobile/setup-r8a7790.c         |  12 +--
 6 files changed, 179 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm/include/debug/r8a7790.S

-- 
Regards,

Laurent Pinchart

[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Laurent Pinchart]

Hello,

This patch set implements serial port support for the Lager reference board,
and adds early debugging support for the r8a7790 SoC.

The code is available in my git tree at

        git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager

The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've posted
earlier today.

Laurent Pinchart (3):
  ARM: shmobile: r8a7790: Add early debugging support
  ARM: shmobile: r8a7790: Add serial ports to the device tree
  ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

 arch/arm/Kconfig.debug                         |   8 ++
 arch/arm/boot/dts/r8a7790-lager.dts            |  24 +++++-
 arch/arm/boot/dts/r8a7790.dtsi                 | 100 +++++++++++++++++++++++++
 arch/arm/include/debug/r8a7790.S               |  43 +++++++++++
 arch/arm/mach-shmobile/board-lager-reference.c |  18 +----
 arch/arm/mach-shmobile/setup-r8a7790.c         |  12 +--
 6 files changed, 179 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm/include/debug/r8a7790.S

-- 
Regards,

Laurent Pinchart

[PATCH 1/3] ARM: shmobile: r8a7790: Add early debugging support

[Laurent Pinchart]

Add serial port debug macros for the SCIF0 serial port on R8A7790.
Support for other serial ports can easily be added if needed.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/Kconfig.debug           |  8 ++++++++
 arch/arm/include/debug/r8a7790.S | 43 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 arch/arm/include/debug/r8a7790.S

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9762c84..f1b765a 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -493,6 +493,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on PXA UART1.
 
+	config DEBUG_R8A7790
+		bool "Kernel low-level debugging messages via SCIF0 on R8A7790 SoCs"
+		depends on ARCH_R8A7790
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Renesas R8A7790 based platforms.
+
 	config DEBUG_REALVIEW_STD_PORT
 		bool "RealView Default UART"
 		depends on ARCH_REALVIEW
@@ -901,6 +908,7 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_MSM8660_UART || \
 				 DEBUG_MSM8960_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+	default "debug/r8a7790.S" if DEBUG_R8A7790
 	default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
 	default "debug/sti.S" if DEBUG_STI_UART
 	default "debug/tegra.S" if DEBUG_TEGRA_UART
diff --git a/arch/arm/include/debug/r8a7790.S b/arch/arm/include/debug/r8a7790.S
new file mode 100644
index 0000000..4f1feb8
--- /dev/null
+++ b/arch/arm/include/debug/r8a7790.S
@@ -0,0 +1,43 @@
+/*
+ * Renesas R8A7790 debugging macro include header
+ *
+ * Copyright (C) 2012-2013 Renesas Electronics Corporation
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define FTDR	0x0c
+#define FSR	0x10
+
+#define TDFE	(1 << 5)
+#define TEND	(1 << 6)
+
+#define SCIF_PHYS	0xe6e60000
+#define SCIF_VIRT	0xffe60000
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =SCIF_PHYS
+	ldr	\rv, =SCIF_VIRT
+	.endm
+
+	.macro	waituart, rd, rx
+1001:	ldrh	\rd, [\rx, #FSR]
+	tst	\rd, #TDFE
+	beq	1001b
+	.endm
+
+	.macro	senduart, rd, rx
+	strb	\rd, [\rx, #FTDR]
+	ldrh	\rd, [\rx, #FSR]
+	bic	\rd, \rd, #TEND
+	strh	\rd, [\rx, #FSR]
+	.endm
+
+	.macro	busyuart, rd, rx
+1001:	ldrh	\rd, [\rx, #FSR]
+	tst	\rd, #TEND
+	beq	1001b
+	.endm
-- 
1.8.1.5

[PATCH 1/3] ARM: shmobile: r8a7790: Add early debugging support

[Laurent Pinchart]

Add serial port debug macros for the SCIF0 serial port on R8A7790.
Support for other serial ports can easily be added if needed.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/Kconfig.debug           |  8 ++++++++
 arch/arm/include/debug/r8a7790.S | 43 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 arch/arm/include/debug/r8a7790.S

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9762c84..f1b765a 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -493,6 +493,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on PXA UART1.
 
+	config DEBUG_R8A7790
+		bool "Kernel low-level debugging messages via SCIF0 on R8A7790 SoCs"
+		depends on ARCH_R8A7790
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Renesas R8A7790 based platforms.
+
 	config DEBUG_REALVIEW_STD_PORT
 		bool "RealView Default UART"
 		depends on ARCH_REALVIEW
@@ -901,6 +908,7 @@ config DEBUG_LL_INCLUDE
 				 DEBUG_MSM8660_UART || \
 				 DEBUG_MSM8960_UART
 	default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+	default "debug/r8a7790.S" if DEBUG_R8A7790
 	default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
 	default "debug/sti.S" if DEBUG_STI_UART
 	default "debug/tegra.S" if DEBUG_TEGRA_UART
diff --git a/arch/arm/include/debug/r8a7790.S b/arch/arm/include/debug/r8a7790.S
new file mode 100644
index 0000000..4f1feb8
--- /dev/null
+++ b/arch/arm/include/debug/r8a7790.S
@@ -0,0 +1,43 @@
+/*
+ * Renesas R8A7790 debugging macro include header
+ *
+ * Copyright (C) 2012-2013 Renesas Electronics Corporation
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define FTDR	0x0c
+#define FSR	0x10
+
+#define TDFE	(1 << 5)
+#define TEND	(1 << 6)
+
+#define SCIF_PHYS	0xe6e60000
+#define SCIF_VIRT	0xffe60000
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =SCIF_PHYS
+	ldr	\rv, =SCIF_VIRT
+	.endm
+
+	.macro	waituart, rd, rx
+1001:	ldrh	\rd, [\rx, #FSR]
+	tst	\rd, #TDFE
+	beq	1001b
+	.endm
+
+	.macro	senduart, rd, rx
+	strb	\rd, [\rx, #FTDR]
+	ldrh	\rd, [\rx, #FSR]
+	bic	\rd, \rd, #TEND
+	strh	\rd, [\rx, #FSR]
+	.endm
+
+	.macro	busyuart, rd, rx
+1001:	ldrh	\rd, [\rx, #FSR]
+	tst	\rd, #TEND
+	beq	1001b
+	.endm
-- 
1.8.1.5

[PATCH 2/3] ARM: shmobile: r8a7790: Add serial ports to the device tree

[Laurent Pinchart]

The platform code serial port instantiation mechanism is kept for the
non-DT platforms only.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi         | 100 +++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/setup-r8a7790.c |  12 ++--
 2 files changed, 106 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 94c8373..04a4992 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -287,6 +287,106 @@
 		status = "disabled";
 	};
 
+	scifa0: serial@e6c40000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		reg = <0 0xe6c40000 0 64>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 144 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifa1: serial@e6c50000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c50000 0 64>;
+		interrupts = <0 145 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifa2: serial@e6c60000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c60000 0 64>;
+		interrupts = <0 151 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb0: serial@e6c20000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c20000 0 64>;
+		interrupts = <0 148 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb1: serial@e6c30000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c30000 0 64>;
+		interrupts = <0 149 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb2: serial@e6ce0000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6ce0000 0 64>;
+		interrupts = <0 150 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scif0: serial@e6e60000 {
+		compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6e60000 0 64>;
+		interrupts = <0 152 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scif1: serial@e6e68000 {
+		compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6e68000 0 64>;
+		interrupts = <0 153 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	hscif0: serial@e62c0000 {
+		compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe62c0000 0 96>;
+		interrupts = <0 154 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	hscif1: serial@e62c8000 {
+		compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe62c8000 0 96>;
+		interrupts = <0 155 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c47bceb..8172a82 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -182,6 +182,12 @@ static const struct resource cmt00_resources[] __initconst = {
 
 void __init r8a7790_add_dt_devices(void)
 {
+	r8a7790_register_cmt(00);
+}
+
+void __init r8a7790_add_standard_devices(void)
+{
+	r8a7790_add_dt_devices();
 	r8a7790_register_scif(SCIFA0);
 	r8a7790_register_scif(SCIFA1);
 	r8a7790_register_scif(SCIFB0);
@@ -192,12 +198,6 @@ void __init r8a7790_add_dt_devices(void)
 	r8a7790_register_scif(SCIF1);
 	r8a7790_register_scif(HSCIF0);
 	r8a7790_register_scif(HSCIF1);
-	r8a7790_register_cmt(00);
-}
-
-void __init r8a7790_add_standard_devices(void)
-{
-	r8a7790_add_dt_devices();
 	r8a7790_register_irqc(0);
 	r8a7790_register_thermal();
 }
-- 
1.8.1.5

[PATCH 2/3] ARM: shmobile: r8a7790: Add serial ports to the device tree

[Laurent Pinchart]

The platform code serial port instantiation mechanism is kept for the
non-DT platforms only.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi         | 100 +++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/setup-r8a7790.c |  12 ++--
 2 files changed, 106 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 94c8373..04a4992 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -287,6 +287,106 @@
 		status = "disabled";
 	};
 
+	scifa0: serial at e6c40000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		reg = <0 0xe6c40000 0 64>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 144 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifa1: serial at e6c50000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c50000 0 64>;
+		interrupts = <0 145 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifa2: serial at e6c60000 {
+		compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c60000 0 64>;
+		interrupts = <0 151 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb0: serial at e6c20000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c20000 0 64>;
+		interrupts = <0 148 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb1: serial at e6c30000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6c30000 0 64>;
+		interrupts = <0 149 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scifb2: serial at e6ce0000 {
+		compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6ce0000 0 64>;
+		interrupts = <0 150 4>;
+		clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scif0: serial at e6e60000 {
+		compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6e60000 0 64>;
+		interrupts = <0 152 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	scif1: serial at e6e68000 {
+		compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe6e68000 0 64>;
+		interrupts = <0 153 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	hscif0: serial at e62c0000 {
+		compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe62c0000 0 96>;
+		interrupts = <0 154 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
+	hscif1: serial at e62c8000 {
+		compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
+		interrupt-parent = <&gic>;
+		reg = <0 0xe62c8000 0 96>;
+		interrupts = <0 155 4>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
+		clock-names = "sci_ick";
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c47bceb..8172a82 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -182,6 +182,12 @@ static const struct resource cmt00_resources[] __initconst = {
 
 void __init r8a7790_add_dt_devices(void)
 {
+	r8a7790_register_cmt(00);
+}
+
+void __init r8a7790_add_standard_devices(void)
+{
+	r8a7790_add_dt_devices();
 	r8a7790_register_scif(SCIFA0);
 	r8a7790_register_scif(SCIFA1);
 	r8a7790_register_scif(SCIFB0);
@@ -192,12 +198,6 @@ void __init r8a7790_add_dt_devices(void)
 	r8a7790_register_scif(SCIF1);
 	r8a7790_register_scif(HSCIF0);
 	r8a7790_register_scif(HSCIF1);
-	r8a7790_register_cmt(00);
-}
-
-void __init r8a7790_add_standard_devices(void)
-{
-	r8a7790_add_dt_devices();
 	r8a7790_register_irqc(0);
 	r8a7790_register_thermal();
 }
-- 
1.8.1.5

[PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Laurent Pinchart]

SCIF0 and SCIF1 are used as debug serial ports. Enable them and
configure pinmuxing appropriately. We can now remove the clkdev
registration hack for SCIF devices from the Lager reference board file.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++++++----
 arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index a923ab6..9830c87 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -16,8 +16,13 @@
 	model = "Lager";
 	compatible = "renesas,lager", "renesas,r8a7790";
 
+	aliases {
+		serial0 = &scif0;
+		serial1 = &scif1;
+	};
+
 	chosen {
-		bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "console=ttySC0,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
 	};
 
 	memory@40000000 {
@@ -58,9 +63,6 @@
 };
 
 &pfc {
-	pinctrl-0 = <&scif0_pins &scif1_pins>;
-	pinctrl-names = "default";
-
 	scif0_pins: scif0 {
 		renesas,groups = "scif0_data";
 		renesas,function = "scif0";
@@ -86,3 +88,17 @@
 	non-removable;
 	status = "okay";
 };
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif1 {
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index bc3d0d2..1f5d6e2 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -36,24 +36,10 @@ static void __init lager_init_time(void)
 static void __init lager_add_standard_devices(void)
 {
 	/*
-	 * This is a really crude hack to provide clkdev support to the SCIF
-	 * and CMT devices until they get moved to DT.
+	 * This is a really crude hack to provide clkdev support to the CMT
+	 * CMT device until it gets moved to DT.
 	 */
-	static const char * const scif_names[] = {
-		"scifa0", "scifa1", "scifb0", "scifb1",
-		"scifb2", "scifa2", "scif0", "scif1",
-		"hscif0", "hscif1",
-	};
 	struct clk *clk;
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
-		clk = clk_get(NULL, scif_names[i]);
-		if (clk) {
-			clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
-			clk_put(clk);
-		}
-	}
 
 	clk = clk_get(NULL, "cmt0");
 	if (clk) {
-- 
1.8.1.5

[PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Laurent Pinchart]

SCIF0 and SCIF1 are used as debug serial ports. Enable them and
configure pinmuxing appropriately. We can now remove the clkdev
registration hack for SCIF devices from the Lager reference board file.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++++++----
 arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index a923ab6..9830c87 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -16,8 +16,13 @@
 	model = "Lager";
 	compatible = "renesas,lager", "renesas,r8a7790";
 
+	aliases {
+		serial0 = &scif0;
+		serial1 = &scif1;
+	};
+
 	chosen {
-		bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		bootargs = "console=ttySC0,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
 	};
 
 	memory at 40000000 {
@@ -58,9 +63,6 @@
 };
 
 &pfc {
-	pinctrl-0 = <&scif0_pins &scif1_pins>;
-	pinctrl-names = "default";
-
 	scif0_pins: scif0 {
 		renesas,groups = "scif0_data";
 		renesas,function = "scif0";
@@ -86,3 +88,17 @@
 	non-removable;
 	status = "okay";
 };
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif1 {
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index bc3d0d2..1f5d6e2 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -36,24 +36,10 @@ static void __init lager_init_time(void)
 static void __init lager_add_standard_devices(void)
 {
 	/*
-	 * This is a really crude hack to provide clkdev support to the SCIF
-	 * and CMT devices until they get moved to DT.
+	 * This is a really crude hack to provide clkdev support to the CMT
+	 * CMT device until it gets moved to DT.
 	 */
-	static const char * const scif_names[] = {
-		"scifa0", "scifa1", "scifb0", "scifb1",
-		"scifb2", "scifa2", "scif0", "scif1",
-		"hscif0", "hscif1",
-	};
 	struct clk *clk;
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
-		clk = clk_get(NULL, scif_names[i]);
-		if (clk) {
-			clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
-			clk_put(clk);
-		}
-	}
 
 	clk = clk_get(NULL, "cmt0");
 	if (clk) {
-- 
1.8.1.5

Re: [PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Sergei Shtylyov]

On 29-10-2013 19:23, Laurent Pinchart wrote:

> SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> configure pinmuxing appropriately. We can now remove the clkdev
> registration hack for SCIF devices from the Lager reference board file.

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++++++----
>   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
>   2 files changed, 22 insertions(+), 20 deletions(-)

> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
> index a923ab6..9830c87 100644
> --- a/arch/arm/boot/dts/r8a7790-lager.dts
> +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -16,8 +16,13 @@
>   	model = "Lager";
>   	compatible = "renesas,lager", "renesas,r8a7790";
>
> +	aliases {
> +		serial0 = &scif0;
> +		serial1 = &scif1;
> +	};
> +
>   	chosen {
> -		bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
> +		bootargs = "console=ttySC0,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";

    Hm... is the rename a by-product of the SCIF device tree enablement?

[...]
> diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
> index bc3d0d2..1f5d6e2 100644
> --- a/arch/arm/mach-shmobile/board-lager-reference.c
> +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
>   static void __init lager_add_standard_devices(void)
>   {
>   	/*
> -	 * This is a really crude hack to provide clkdev support to the SCIF
> -	 * and CMT devices until they get moved to DT.
> +	 * This is a really crude hack to provide clkdev support to the CMT
> +	 * CMT device until it gets moved to DT.

    Minor nit: "CMT" repeated twice.

WBR, Sergei

[PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Sergei Shtylyov]

On 29-10-2013 19:23, Laurent Pinchart wrote:

> SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> configure pinmuxing appropriately. We can now remove the clkdev
> registration hack for SCIF devices from the Lager reference board file.

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++++++----
>   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
>   2 files changed, 22 insertions(+), 20 deletions(-)

> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
> index a923ab6..9830c87 100644
> --- a/arch/arm/boot/dts/r8a7790-lager.dts
> +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -16,8 +16,13 @@
>   	model = "Lager";
>   	compatible = "renesas,lager", "renesas,r8a7790";
>
> +	aliases {
> +		serial0 = &scif0;
> +		serial1 = &scif1;
> +	};
> +
>   	chosen {
> -		bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
> +		bootargs = "console=ttySC0,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";

    Hm... is the rename a by-product of the SCIF device tree enablement?

[...]
> diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
> index bc3d0d2..1f5d6e2 100644
> --- a/arch/arm/mach-shmobile/board-lager-reference.c
> +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
>   static void __init lager_add_standard_devices(void)
>   {
>   	/*
> -	 * This is a really crude hack to provide clkdev support to the SCIF
> -	 * and CMT devices until they get moved to DT.
> +	 * This is a really crude hack to provide clkdev support to the CMT
> +	 * CMT device until it gets moved to DT.

    Minor nit: "CMT" repeated twice.

WBR, Sergei

Re: [PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Laurent Pinchart]

Hi Sergei,

On Tuesday 29 October 2013 22:09:34 Sergei Shtylyov wrote:
> On 29-10-2013 19:23, Laurent Pinchart wrote:
> > SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> > configure pinmuxing appropriately. We can now remove the clkdev
> > registration hack for SCIF devices from the Lager reference board file.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > 
> >   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++----
> >   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
> >   2 files changed, 22 insertions(+), 20 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> > b/arch/arm/boot/dts/r8a7790-lager.dts index a923ab6..9830c87 100644
> > --- a/arch/arm/boot/dts/r8a7790-lager.dts
> > +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> > @@ -16,8 +16,13 @@
> >   	model = "Lager";
> >   	compatible = "renesas,lager", "renesas,r8a7790";
> > 
> > +	aliases {
> > +		serial0 = &scif0;
> > +		serial1 = &scif1;
> > +	};
> > +
> >   	chosen {
> > -		bootargs = "console=ttySC6,115200 ignore_loglevel rw
> > root=/dev/nfs ip=dhcp";
> > +		bootargs = "console=ttySC0,115200 ignore_loglevel rw
> > root=/dev/nfs ip=dhcp";
>
> Hm... is the rename a by-product of the SCIF device tree enablement?

I suppose we could keep the same serial port name using serial6 and serial7 in 
the aliases. However, moving to DT will get rid of all other serial ports, so 
we would be left with ttySC6 and ttySC7, without ttySC0 to ttySC5. I'm not 
sure if I like that.

(CC'ing Simon and Magnus to get their opinion on the subject)

> [...]
> 
> > diff --git a/arch/arm/mach-shmobile/board-lager-reference.c
> > b/arch/arm/mach-shmobile/board-lager-reference.c index bc3d0d2..1f5d6e2
> > 100644
> > --- a/arch/arm/mach-shmobile/board-lager-reference.c
> > +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> > @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
> > 
> >   static void __init lager_add_standard_devices(void)
> >   {
> >   	/*
> > -	 * This is a really crude hack to provide clkdev support to the SCIF
> > -	 * and CMT devices until they get moved to DT.
> > +	 * This is a really crude hack to provide clkdev support to the CMT
> > +	 * CMT device until it gets moved to DT.
> 
> Minor nit: "CMT" repeated twice.

I'll fix that. If no other change is required I won't repost the patch before 
sending the pull request.

-- 
Regards,

Laurent Pinchart

[PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Laurent Pinchart]

Hi Sergei,

On Tuesday 29 October 2013 22:09:34 Sergei Shtylyov wrote:
> On 29-10-2013 19:23, Laurent Pinchart wrote:
> > SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> > configure pinmuxing appropriately. We can now remove the clkdev
> > registration hack for SCIF devices from the Lager reference board file.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > 
> >   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++----
> >   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
> >   2 files changed, 22 insertions(+), 20 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> > b/arch/arm/boot/dts/r8a7790-lager.dts index a923ab6..9830c87 100644
> > --- a/arch/arm/boot/dts/r8a7790-lager.dts
> > +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> > @@ -16,8 +16,13 @@
> >   	model = "Lager";
> >   	compatible = "renesas,lager", "renesas,r8a7790";
> > 
> > +	aliases {
> > +		serial0 = &scif0;
> > +		serial1 = &scif1;
> > +	};
> > +
> >   	chosen {
> > -		bootargs = "console=ttySC6,115200 ignore_loglevel rw
> > root=/dev/nfs ip=dhcp";
> > +		bootargs = "console=ttySC0,115200 ignore_loglevel rw
> > root=/dev/nfs ip=dhcp";
>
> Hm... is the rename a by-product of the SCIF device tree enablement?

I suppose we could keep the same serial port name using serial6 and serial7 in 
the aliases. However, moving to DT will get rid of all other serial ports, so 
we would be left with ttySC6 and ttySC7, without ttySC0 to ttySC5. I'm not 
sure if I like that.

(CC'ing Simon and Magnus to get their opinion on the subject)

> [...]
> 
> > diff --git a/arch/arm/mach-shmobile/board-lager-reference.c
> > b/arch/arm/mach-shmobile/board-lager-reference.c index bc3d0d2..1f5d6e2
> > 100644
> > --- a/arch/arm/mach-shmobile/board-lager-reference.c
> > +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> > @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
> > 
> >   static void __init lager_add_standard_devices(void)
> >   {
> >   	/*
> > -	 * This is a really crude hack to provide clkdev support to the SCIF
> > -	 * and CMT devices until they get moved to DT.
> > +	 * This is a really crude hack to provide clkdev support to the CMT
> > +	 * CMT device until it gets moved to DT.
> 
> Minor nit: "CMT" repeated twice.

I'll fix that. If no other change is required I won't repost the patch before 
sending the pull request.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Simon Horman]

On Tue, Oct 29, 2013 at 07:30:05PM +0100, Laurent Pinchart wrote:
> Hi Sergei,
> 
> On Tuesday 29 October 2013 22:09:34 Sergei Shtylyov wrote:
> > On 29-10-2013 19:23, Laurent Pinchart wrote:
> > > SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> > > configure pinmuxing appropriately. We can now remove the clkdev
> > > registration hack for SCIF devices from the Lager reference board file.
> > > 
> > > Signed-off-by: Laurent Pinchart
> > > <laurent.pinchart+renesas@ideasonboard.com>
> > > ---
> > > 
> > >   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++----
> > >   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
> > >   2 files changed, 22 insertions(+), 20 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> > > b/arch/arm/boot/dts/r8a7790-lager.dts index a923ab6..9830c87 100644
> > > --- a/arch/arm/boot/dts/r8a7790-lager.dts
> > > +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> > > @@ -16,8 +16,13 @@
> > >   	model = "Lager";
> > >   	compatible = "renesas,lager", "renesas,r8a7790";
> > > 
> > > +	aliases {
> > > +		serial0 = &scif0;
> > > +		serial1 = &scif1;
> > > +	};
> > > +
> > >   	chosen {
> > > -		bootargs = "console=ttySC6,115200 ignore_loglevel rw
> > > root=/dev/nfs ip=dhcp";
> > > +		bootargs = "console=ttySC0,115200 ignore_loglevel rw
> > > root=/dev/nfs ip=dhcp";
> >
> > Hm... is the rename a by-product of the SCIF device tree enablement?
> 
> I suppose we could keep the same serial port name using serial6 and serial7 in 
> the aliases. However, moving to DT will get rid of all other serial ports, so 
> we would be left with ttySC6 and ttySC7, without ttySC0 to ttySC5. I'm not 
> sure if I like that.
> 
> (CC'ing Simon and Magnus to get their opinion on the subject)

It seems logical to me that if we only have two serial ports initialised
that they should be ttySC0 and ttySC1. Even if that leaves us with the pain
of switching over to use ttySC0 instead of ttySC6 as the console.

> 
> > [...]
> > 
> > > diff --git a/arch/arm/mach-shmobile/board-lager-reference.c
> > > b/arch/arm/mach-shmobile/board-lager-reference.c index bc3d0d2..1f5d6e2
> > > 100644
> > > --- a/arch/arm/mach-shmobile/board-lager-reference.c
> > > +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> > > @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
> > > 
> > >   static void __init lager_add_standard_devices(void)
> > >   {
> > >   	/*
> > > -	 * This is a really crude hack to provide clkdev support to the SCIF
> > > -	 * and CMT devices until they get moved to DT.
> > > +	 * This is a really crude hack to provide clkdev support to the CMT
> > > +	 * CMT device until it gets moved to DT.
> > 
> > Minor nit: "CMT" repeated twice.
> 
> I'll fix that. If no other change is required I won't repost the patch before 
> sending the pull request.
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

[PATCH 3/3] ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

[Simon Horman]

On Tue, Oct 29, 2013 at 07:30:05PM +0100, Laurent Pinchart wrote:
> Hi Sergei,
> 
> On Tuesday 29 October 2013 22:09:34 Sergei Shtylyov wrote:
> > On 29-10-2013 19:23, Laurent Pinchart wrote:
> > > SCIF0 and SCIF1 are used as debug serial ports. Enable them and
> > > configure pinmuxing appropriately. We can now remove the clkdev
> > > registration hack for SCIF devices from the Lager reference board file.
> > > 
> > > Signed-off-by: Laurent Pinchart
> > > <laurent.pinchart+renesas@ideasonboard.com>
> > > ---
> > > 
> > >   arch/arm/boot/dts/r8a7790-lager.dts            | 24 ++++++++++++++++----
> > >   arch/arm/mach-shmobile/board-lager-reference.c | 18 ++----------------
> > >   2 files changed, 22 insertions(+), 20 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> > > b/arch/arm/boot/dts/r8a7790-lager.dts index a923ab6..9830c87 100644
> > > --- a/arch/arm/boot/dts/r8a7790-lager.dts
> > > +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> > > @@ -16,8 +16,13 @@
> > >   	model = "Lager";
> > >   	compatible = "renesas,lager", "renesas,r8a7790";
> > > 
> > > +	aliases {
> > > +		serial0 = &scif0;
> > > +		serial1 = &scif1;
> > > +	};
> > > +
> > >   	chosen {
> > > -		bootargs = "console=ttySC6,115200 ignore_loglevel rw
> > > root=/dev/nfs ip=dhcp";
> > > +		bootargs = "console=ttySC0,115200 ignore_loglevel rw
> > > root=/dev/nfs ip=dhcp";
> >
> > Hm... is the rename a by-product of the SCIF device tree enablement?
> 
> I suppose we could keep the same serial port name using serial6 and serial7 in 
> the aliases. However, moving to DT will get rid of all other serial ports, so 
> we would be left with ttySC6 and ttySC7, without ttySC0 to ttySC5. I'm not 
> sure if I like that.
> 
> (CC'ing Simon and Magnus to get their opinion on the subject)

It seems logical to me that if we only have two serial ports initialised
that they should be ttySC0 and ttySC1. Even if that leaves us with the pain
of switching over to use ttySC0 instead of ttySC6 as the console.

> 
> > [...]
> > 
> > > diff --git a/arch/arm/mach-shmobile/board-lager-reference.c
> > > b/arch/arm/mach-shmobile/board-lager-reference.c index bc3d0d2..1f5d6e2
> > > 100644
> > > --- a/arch/arm/mach-shmobile/board-lager-reference.c
> > > +++ b/arch/arm/mach-shmobile/board-lager-reference.c
> > > @@ -36,24 +36,10 @@ static void __init lager_init_time(void)
> > > 
> > >   static void __init lager_add_standard_devices(void)
> > >   {
> > >   	/*
> > > -	 * This is a really crude hack to provide clkdev support to the SCIF
> > > -	 * and CMT devices until they get moved to DT.
> > > +	 * This is a really crude hack to provide clkdev support to the CMT
> > > +	 * CMT device until it gets moved to DT.
> > 
> > Minor nit: "CMT" repeated twice.
> 
> I'll fix that. If no other change is required I won't repost the patch before 
> sending the pull request.
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

Re: [PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Simon Horman]

On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> Hello,
> 
> This patch set implements serial port support for the Lager reference board,
> and adds early debugging support for the r8a7790 SoC.
> 
> The code is available in my git tree at
> 
>         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> 
> The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've posted
> earlier today.
> 
> Laurent Pinchart (3):
>   ARM: shmobile: r8a7790: Add early debugging support

The patch above could be applied now, right?
If so, Magnus, could you review it?

>   ARM: shmobile: r8a7790: Add serial ports to the device tree
>   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

I would like to ask you to repost these patches once their
pre-requisites have been merged.

[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Simon Horman]

On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> Hello,
> 
> This patch set implements serial port support for the Lager reference board,
> and adds early debugging support for the r8a7790 SoC.
> 
> The code is available in my git tree at
> 
>         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> 
> The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've posted
> earlier today.
> 
> Laurent Pinchart (3):
>   ARM: shmobile: r8a7790: Add early debugging support

The patch above could be applied now, right?
If so, Magnus, could you review it?

>   ARM: shmobile: r8a7790: Add serial ports to the device tree
>   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT

I would like to ask you to repost these patches once their
pre-requisites have been merged.

Re: [PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Laurent Pinchart]

Hi Simon,

On Thursday 31 October 2013 14:31:44 Simon Horman wrote:
> On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> > Hello,
> > 
> > This patch set implements serial port support for the Lager reference
> > board, and adds early debugging support for the r8a7790 SoC.
> > 
> > The code is available in my git tree at
> > 
> >         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> > 
> > The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> > multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've
> > posted earlier today.
> > 
> > Laurent Pinchart (3):
> >   ARM: shmobile: r8a7790: Add early debugging support
> 
> The patch above could be applied now, right?

That's correct. It will be useless though, as DEBUG_LL can only be used on 
multiarch.

Given that the SCIF/SCIFA/SCIFB port operate similarly, I wonder whether it 
wouldn't make more sense to add a generic DEBUG_SHMOBILE_SCIF implementation 
instead. We could then have sub-options to select the exact SoC type and port 
number, and compute the base address from that.

> If so, Magnus, could you review it?
> 
> >   ARM: shmobile: r8a7790: Add serial ports to the device tree
> >   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT
> 
> I would like to ask you to repost these patches once their
> pre-requisites have been merged.

Sure, no problem.

-- 
Regards,

Laurent Pinchart

[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Laurent Pinchart]

Hi Simon,

On Thursday 31 October 2013 14:31:44 Simon Horman wrote:
> On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> > Hello,
> > 
> > This patch set implements serial port support for the Lager reference
> > board, and adds early debugging support for the r8a7790 SoC.
> > 
> > The code is available in my git tree at
> > 
> >         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> > 
> > The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> > multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've
> > posted earlier today.
> > 
> > Laurent Pinchart (3):
> >   ARM: shmobile: r8a7790: Add early debugging support
> 
> The patch above could be applied now, right?

That's correct. It will be useless though, as DEBUG_LL can only be used on 
multiarch.

Given that the SCIF/SCIFA/SCIFB port operate similarly, I wonder whether it 
wouldn't make more sense to add a generic DEBUG_SHMOBILE_SCIF implementation 
instead. We could then have sub-options to select the exact SoC type and port 
number, and compute the base address from that.

> If so, Magnus, could you review it?
> 
> >   ARM: shmobile: r8a7790: Add serial ports to the device tree
> >   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT
> 
> I would like to ask you to repost these patches once their
> pre-requisites have been merged.

Sure, no problem.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Simon Horman]

[ CC Magnus ]

On Thu, Oct 31, 2013 at 01:21:23PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Thursday 31 October 2013 14:31:44 Simon Horman wrote:
> > On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> > > Hello,
> > > 
> > > This patch set implements serial port support for the Lager reference
> > > board, and adds early debugging support for the r8a7790 SoC.
> > > 
> > > The code is available in my git tree at
> > > 
> > >         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> > > 
> > > The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> > > multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've
> > > posted earlier today.
> > > 
> > > Laurent Pinchart (3):
> > >   ARM: shmobile: r8a7790: Add early debugging support
> > 
> > The patch above could be applied now, right?
> 
> That's correct. It will be useless though, as DEBUG_LL can only be used on 
> multiarch.

I will wait, especially in the light of the point you raise below.

> Given that the SCIF/SCIFA/SCIFB port operate similarly, I wonder whether it 
> wouldn't make more sense to add a generic DEBUG_SHMOBILE_SCIF implementation 
> instead. We could then have sub-options to select the exact SoC type and port 
> number, and compute the base address from that.

That makes a lot of sense to me.
Perhaps Magnus has an opinion?

> > If so, Magnus, could you review it?
> > 
> > >   ARM: shmobile: r8a7790: Add serial ports to the device tree
> > >   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT
> > 
> > I would like to ask you to repost these patches once their
> > pre-requisites have been merged.
> 
> Sure, no problem.
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 0/3] ARM: shmobile: Lager reference serial port support

[Simon Horman]

[ CC Magnus ]

On Thu, Oct 31, 2013 at 01:21:23PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Thursday 31 October 2013 14:31:44 Simon Horman wrote:
> > On Tue, Oct 29, 2013 at 04:23:10PM +0100, Laurent Pinchart wrote:
> > > Hello,
> > > 
> > > This patch set implements serial port support for the Lager reference
> > > board, and adds early debugging support for the r8a7790 SoC.
> > > 
> > > The code is available in my git tree at
> > > 
> > >         git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/serial-lager
> > > 
> > > The branch is based on a merge of renesas-devel-20131016, v3.12-rc7 and
> > > multiarch drivers, clk-prepare, r8a7790 CCF and sh-sci OF patches I've
> > > posted earlier today.
> > > 
> > > Laurent Pinchart (3):
> > >   ARM: shmobile: r8a7790: Add early debugging support
> > 
> > The patch above could be applied now, right?
> 
> That's correct. It will be useless though, as DEBUG_LL can only be used on 
> multiarch.

I will wait, especially in the light of the point you raise below.

> Given that the SCIF/SCIFA/SCIFB port operate similarly, I wonder whether it 
> wouldn't make more sense to add a generic DEBUG_SHMOBILE_SCIF implementation 
> instead. We could then have sub-options to select the exact SoC type and port 
> number, and compute the base address from that.

That makes a lot of sense to me.
Perhaps Magnus has an opinion?

> > If so, Magnus, could you review it?
> > 
> > >   ARM: shmobile: r8a7790: Add serial ports to the device tree
> > >   ARM: shmobile: lager: Enable SCIF0 and SCIF1 serial ports in DT
> > 
> > I would like to ask you to repost these patches once their
> > pre-requisites have been merged.
> 
> Sure, no problem.
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 1/3] ARM: shmobile: r8a7790: Add VIN clock support

[Valentine Barshak]

This adds VIN[0-3] clock support to R8A7790 SoC.

Changes in V2:
* none.

Changes in V3:
* capitalized ARM in the subject.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 arch/arm/mach-shmobile/clock-r8a7790.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a028f96..31c5ffa 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -197,6 +197,7 @@ enum {
 	MSTP931, MSTP930, MSTP929, MSTP928,
 	MSTP917,
 	MSTP813,
+	MSTP811, MSTP810, MSTP809, MSTP808,
 	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 	MSTP717, MSTP716,
 	MSTP704,
@@ -225,6 +226,10 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
+	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
+	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
+	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
+	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
 	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
 	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
 	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
@@ -309,6 +314,10 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
 	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
 	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
+	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
+	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
+	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
-- 
1.8.3.1

Re: [PATCH 1/3] ARM: shmobile: r8a7790: Add VIN clock support

[Simon Horman]

On Wed, Jan 08, 2014 at 08:31:23PM +0400, Valentine Barshak wrote:
> This adds VIN[0-3] clock support to R8A7790 SoC.

Please place Changes and similar annotations below a "---" line
to allow git to automatically strip them out for me when I apply your
patches.

---

> 
> Changes in V2:
> * none.
> 
> Changes in V3:
> * capitalized ARM in the subject.
> 
> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> ---
>  arch/arm/mach-shmobile/clock-r8a7790.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

There was some fuzz when applying this patch.
I have queued up the following. Please check that it is correct.

From: Valentine Barshak <valentine.barshak@cogentembedded.com>

ARM: shmobile: r8a7790: Add VIN clock support

This adds VIN[0-3] clock support to R8A7790 SoC.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
[horms+renesas@verge.net.au: manually applied]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 58f3dcf..b2b2323 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -197,6 +197,7 @@ enum {
 	MSTP931, MSTP930, MSTP929, MSTP928,
 	MSTP917,
 	MSTP813,
+	MSTP811, MSTP810, MSTP809, MSTP808,
 	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 	MSTP717, MSTP716,
 	MSTP704,
@@ -226,6 +227,10 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
+	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
+	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
+	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
+	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
 	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
 	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
 	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
@@ -312,6 +317,10 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
 	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
 	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
+	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
+	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
+	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),

Re: [PATCH 1/3] ARM: shmobile: r8a7790: Add VIN clock support

[Valentine]

On 01/09/2014 12:14 PM, Simon Horman wrote:
> On Wed, Jan 08, 2014 at 08:31:23PM +0400, Valentine Barshak wrote:
>> This adds VIN[0-3] clock support to R8A7790 SoC.
>
> Please place Changes and similar annotations below a "---" line
> to allow git to automatically strip them out for me when I apply your
> patches.

OK, thanks.

>
> ---
>
>>
>> Changes in V2:
>> * none.
>>
>> Changes in V3:
>> * capitalized ARM in the subject.
>>
>> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
>> ---
>>   arch/arm/mach-shmobile/clock-r8a7790.c | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>
> There was some fuzz when applying this patch.
> I have queued up the following. Please check that it is correct.

It is correct, thanks.

>
> From: Valentine Barshak <valentine.barshak@cogentembedded.com>
>
> ARM: shmobile: r8a7790: Add VIN clock support
>
> This adds VIN[0-3] clock support to R8A7790 SoC.
>
> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> [horms+renesas@verge.net.au: manually applied]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
> index 58f3dcf..b2b2323 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> @@ -197,6 +197,7 @@ enum {
>   	MSTP931, MSTP930, MSTP929, MSTP928,
>   	MSTP917,
>   	MSTP813,
> +	MSTP811, MSTP810, MSTP809, MSTP808,
>   	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
>   	MSTP717, MSTP716,
>   	MSTP704,
> @@ -226,6 +227,10 @@ static struct clk mstp_clks[MSTP_NR] = {
>   	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
>   	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
>   	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
> +	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
> +	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
> +	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
> +	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
>   	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
>   	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
>   	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
> @@ -312,6 +317,10 @@ static struct clk_lookup lookups[] = {
>   	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
>   	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
>   	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
> +	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
> +	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
> +	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
> +	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
>   	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
>   	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
>   	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
>

Thanks,
Val.

[PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Kuninori Morimoto]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm/boot/dts/r8a7790.dtsi            |   32 +++++++++++++++++++++++++++++
 include/dt-bindings/clock/r8a7790-clock.h |   26 +++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e990d3c..cb8a68d 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -835,6 +835,38 @@
 				"rcan1", "rcan0", "qspi_mod", "iic3",
 				"i2c3", "i2c2", "i2c1", "i2c0";
 		};
+		mstp10_clks: mstp10_clks@e6150998 {
+			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>, /* parent of SCU */
+				<&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
+				<&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>;
+
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7790_CLK_SCU
+				R8A7790_CLK_SSI
+				R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
+				R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
+				R8A7790_CLK_DVC1 R8A7790_CLK_DVC0
+				R8A7790_CLK_SRC9 R8A7790_CLK_SRC8 R8A7790_CLK_SRC7 R8A7790_CLK_SRC6 R8A7790_CLK_SRC5
+				R8A7790_CLK_SRC4 R8A7790_CLK_SRC3 R8A7790_CLK_SRC2 R8A7790_CLK_SRC1 R8A7790_CLK_SRC0
+			>;
+			clock-output-names +				"scu", "ssi",
+				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+				"dvc1", "dvc0",
+				"src9", "src8", "src7", "src6", "src5",
+				"src4", "src3", "src2", "src1", "src0";
+		};
 	};
 
 	qspi: spi@e6b10000 {
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 1118f7a..b4430b0 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -107,4 +107,30 @@
 #define R8A7790_CLK_I2C1		30
 #define R8A7790_CLK_I2C0		31
 
+/* MSTP10 */
+#define R8A7790_CLK_SSI			5
+#define R8A7790_CLK_SSI9		6
+#define R8A7790_CLK_SSI8		7
+#define R8A7790_CLK_SSI7		8
+#define R8A7790_CLK_SSI6		9
+#define R8A7790_CLK_SSI5		10
+#define R8A7790_CLK_SSI4		11
+#define R8A7790_CLK_SSI3		12
+#define R8A7790_CLK_SSI2		13
+#define R8A7790_CLK_SSI1		14
+#define R8A7790_CLK_SSI0		15
+#define R8A7790_CLK_SCU			17
+#define R8A7790_CLK_DVC1		18
+#define R8A7790_CLK_DVC0		19
+#define R8A7790_CLK_SRC9		22
+#define R8A7790_CLK_SRC8		23
+#define R8A7790_CLK_SRC7		24
+#define R8A7790_CLK_SRC6		25
+#define R8A7790_CLK_SRC5		26
+#define R8A7790_CLK_SRC4		27
+#define R8A7790_CLK_SRC3		28
+#define R8A7790_CLK_SRC2		29
+#define R8A7790_CLK_SRC1		30
+#define R8A7790_CLK_SRC0		31
+
 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
-- 
1.7.9.5

Re: [PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Geert Uytterhoeven]

Hi Morimoto-san,

On Tue, Jun 10, 2014 at 4:33 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -835,6 +835,38 @@
>                                 "rcan1", "rcan0", "qspi_mod", "iic3",
>                                 "i2c3", "i2c2", "i2c1", "i2c0";
>                 };
> +               mstp10_clks: mstp10_clks@e6150998 {
> +                       compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
> +                       clocks = <&p_clk>, /* parent of SCU */
> +                               <&p_clk>,
> +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>;
> +
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7790_CLK_SCU
> +                               R8A7790_CLK_SSI
> +                               R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
> +                               R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
> +                               R8A7790_CLK_DVC1 R8A7790_CLK_DVC0
> +                               R8A7790_CLK_SRC9 R8A7790_CLK_SRC8 R8A7790_CLK_SRC7 R8A7790_CLK_SRC6 R8A7790_CLK_SRC5
> +                               R8A7790_CLK_SRC4 R8A7790_CLK_SRC3 R8A7790_CLK_SRC2 R8A7790_CLK_SRC1 R8A7790_CLK_SRC0

I think we usually put these in numerical order here.

> +                       >;
> +                       clock-output-names > +                               "scu", "ssi",
> +                               "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
> +                               "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
> +                               "dvc1", "dvc0",
> +                               "src9", "src8", "src7", "src6", "src5",
> +                               "src4", "src3", "src2", "src1", "src0";
> +               };
>         };
>
>         qspi: spi@e6b10000 {
> diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
> index 1118f7a..b4430b0 100644
> --- a/include/dt-bindings/clock/r8a7790-clock.h
> +++ b/include/dt-bindings/clock/r8a7790-clock.h
> @@ -107,4 +107,30 @@
>  #define R8A7790_CLK_I2C1               30
>  #define R8A7790_CLK_I2C0               31
>
> +/* MSTP10 */
> +#define R8A7790_CLK_SSI                        5

Should this be called R8A7790_CLK_SSI_ALL?

> +#define R8A7790_CLK_SSI9               6
> +#define R8A7790_CLK_SSI8               7
> +#define R8A7790_CLK_SSI7               8
> +#define R8A7790_CLK_SSI6               9
> +#define R8A7790_CLK_SSI5               10
> +#define R8A7790_CLK_SSI4               11
> +#define R8A7790_CLK_SSI3               12
> +#define R8A7790_CLK_SSI2               13
> +#define R8A7790_CLK_SSI1               14
> +#define R8A7790_CLK_SSI0               15
> +#define R8A7790_CLK_SCU                        17

Should this be called R8A7790_CLK_SCU_ALL?

> +#define R8A7790_CLK_DVC1               18
> +#define R8A7790_CLK_DVC0               19

"#define R8A7790_CLK_SCU_CTU1x_MIX1 20" and
"#define R8A7790_CLK_SCU_CTU0x_MIX0 21" are missing?

> +#define R8A7790_CLK_SRC9               22
> +#define R8A7790_CLK_SRC8               23
> +#define R8A7790_CLK_SRC7               24
> +#define R8A7790_CLK_SRC6               25
> +#define R8A7790_CLK_SRC5               26
> +#define R8A7790_CLK_SRC4               27
> +#define R8A7790_CLK_SRC3               28
> +#define R8A7790_CLK_SRC2               29
> +#define R8A7790_CLK_SRC1               30
> +#define R8A7790_CLK_SRC0               31

Should these be called R8A7790_CLK_SCU_SRC[0-9]?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Geert Uytterhoeven]

On Tue, Jun 10, 2014 at 9:32 AM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>> +#define R8A7790_CLK_SSI                        5
>
> Should this be called R8A7790_CLK_SSI_ALL?

>> +#define R8A7790_CLK_SCU                        17
>
> Should this be called R8A7790_CLK_SCU_ALL?

>> +#define R8A7790_CLK_SRC9               22
>> +#define R8A7790_CLK_SRC8               23
>> +#define R8A7790_CLK_SRC7               24
>> +#define R8A7790_CLK_SRC6               25
>> +#define R8A7790_CLK_SRC5               26
>> +#define R8A7790_CLK_SRC4               27
>> +#define R8A7790_CLK_SRC3               28
>> +#define R8A7790_CLK_SRC2               29
>> +#define R8A7790_CLK_SRC1               30
>> +#define R8A7790_CLK_SRC0               31
>
> Should these be called R8A7790_CLK_SCU_SRC[0-9]?

If forgot: in case the above are changed, the values in "clock-output-names"
should be renamed, too.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Kuninori Morimoto]

Hi Geert

> > +               mstp10_clks: mstp10_clks@e6150998 {
> > +                       compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
> > +                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
> > +                       clocks = <&p_clk>, /* parent of SCU */
> > +                               <&p_clk>,
> > +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> > +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>;
> > +
> > +                       #clock-cells = <1>;
> > +                       clock-indices = <
> > +                               R8A7790_CLK_SCU
> > +                               R8A7790_CLK_SSI
> > +                               R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
> > +                               R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
> > +                               R8A7790_CLK_DVC1 R8A7790_CLK_DVC0
> > +                               R8A7790_CLK_SRC9 R8A7790_CLK_SRC8 R8A7790_CLK_SRC7 R8A7790_CLK_SRC6 R8A7790_CLK_SRC5
> > +                               R8A7790_CLK_SRC4 R8A7790_CLK_SRC3 R8A7790_CLK_SRC2 R8A7790_CLK_SRC1 R8A7790_CLK_SRC0
> 
> I think we usually put these in numerical order here.

Do you mean R8A7790_CLK_SCU is out-of-order ?
If so, Unfortunately, we need put "R8A7790_CLK_SCU" before "R8A7790_CLK_SRCx",
because SCU(ALL) is parent clock of SRCn.

> > +#define R8A7790_CLK_DVC1               18
> > +#define R8A7790_CLK_DVC0               19
> 
> "#define R8A7790_CLK_SCU_CTU1x_MIX1 20" and
> "#define R8A7790_CLK_SCU_CTU0x_MIX0 21" are missing?

Yes, CTU/MIX is not supported at this point in sound driver.
I don't know I should add it or not

> > +/* MSTP10 */
> > +#define R8A7790_CLK_SSI                        5
> 
> Should this be called R8A7790_CLK_SSI_ALL?
(snip)
> > +#define R8A7790_CLK_SCU                        17
> 
> Should this be called R8A7790_CLK_SCU_ALL?
(snip)
> > +#define R8A7790_CLK_SRC9               22
> > +#define R8A7790_CLK_SRC8               23
> > +#define R8A7790_CLK_SRC7               24
> > +#define R8A7790_CLK_SRC6               25
> > +#define R8A7790_CLK_SRC5               26
> > +#define R8A7790_CLK_SRC4               27
> > +#define R8A7790_CLK_SRC3               28
> > +#define R8A7790_CLK_SRC2               29
> > +#define R8A7790_CLK_SRC1               30
> > +#define R8A7790_CLK_SRC0               31
> 
> Should these be called R8A7790_CLK_SCU_SRC[0-9]?

Using datasheet name will not create new confusion.
Thank you, will fix.

Re: [PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Geert Uytterhoeven]

Hi Morimoto-san,

On Tue, Jun 10, 2014 at 9:48 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
>> > +               mstp10_clks: mstp10_clks@e6150998 {
>> > +                       compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>> > +                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
>> > +                       clocks = <&p_clk>, /* parent of SCU */
>> > +                               <&p_clk>,
>> > +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
>> > +                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>,
>> > +                               <&mstp10_clks R8A7790_CLK_SCU>, <&mstp10_clks R8A7790_CLK_SCU>;
>> > +
>> > +                       #clock-cells = <1>;
>> > +                       clock-indices = <
>> > +                               R8A7790_CLK_SCU
>> > +                               R8A7790_CLK_SSI
>> > +                               R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
>> > +                               R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
>> > +                               R8A7790_CLK_DVC1 R8A7790_CLK_DVC0
>> > +                               R8A7790_CLK_SRC9 R8A7790_CLK_SRC8 R8A7790_CLK_SRC7 R8A7790_CLK_SRC6 R8A7790_CLK_SRC5
>> > +                               R8A7790_CLK_SRC4 R8A7790_CLK_SRC3 R8A7790_CLK_SRC2 R8A7790_CLK_SRC1 R8A7790_CLK_SRC0
>>
>> I think we usually put these in numerical order here.
>
> Do you mean R8A7790_CLK_SCU is out-of-order ?

I mean they should be in the same order as listed in
include/dt-bindings/clock/r8a7790-clock.h

> If so, Unfortunately, we need put "R8A7790_CLK_SCU" before "R8A7790_CLK_SRCx",
> because SCU(ALL) is parent clock of SRCn.

IC. I didn't look up the parent clock relations.
However, SCU_ALL = 17, while its children are 18-31, so numerical order
should be fine.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] ARM: shmobile: r8a7790: add MSTP10 support on DTSI

[Kuninori Morimoto]

Hi Geert, Simon


> > If so, Unfortunately, we need put "R8A7790_CLK_SCU" before "R8A7790_CLK_SRCx",
> > because SCU(ALL) is parent clock of SRCn.
> 
> IC. I didn't look up the parent clock relations.
> However, SCU_ALL = 17, while its children are 18-31, so numerical order
> should be fine.

Hmm.. indeed
I had been confused about it.

I sent v2 patches before getting your feedback...
Before sending v3 patches, I want to get Simon's opinion.
I will send v3 patches if Simon can accept [1/3][2/3] (and [3/3] too?) now.
If not, I will say "Thank you for your feedback" to Geert,
but, not send v3. because this is [RFC] patches.

[PATCH 1/3] ARM: shmobile: r8a7790: Add IPMMU DT nodes

[Laurent Pinchart]

Add the six IPMMU instances found in the r8a7790 to DT with a disabled
status.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r8a7790.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 56847bf09c3b..a9e601053bbb 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1473,4 +1473,55 @@
 			ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
 		};
 	};
+
+	ipmmu_sy0: mmu@e6280000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xe6280000 0 0x1000>;
+		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 224 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
+	ipmmu_sy1: mmu@e6290000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xe6290000 0 0x1000>;
+		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
+	ipmmu_ds: mmu@e6740000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xe6740000 0 0x1000>;
+		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 199 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
+	ipmmu_mp: mmu@ec680000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xec680000 0 0x1000>;
+		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
+	ipmmu_mx: mmu@fe951000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xfe951000 0 0x1000>;
+		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
+	ipmmu_rt: mmu@ffc80000 {
+		compatible = "renesas,ipmmu-vmsa";
+		reg = <0 0xffc80000 0 0x1000>;
+		interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
 };
-- 
2.0.5