* [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers
@ 2013-10-31 2:07 York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver York Sun
` (5 more replies)
0 siblings, 6 replies; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
This patch set attempts to move Freescale DDR and IFC drivers to common drivers,
to prepare sharing between powerpc-based and ARM-based SoCs.
[Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common
[Patch v1 2/6] Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
[Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM
[Patch v1 4/6] powerpc/mpc8xxx: Extend DDR registers' fields
[Patch v1 5/6] Driver/DDR: Update DDR driver to allow non-zero base
[Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
@ 2013-10-31 2:07 ` York Sun
2013-11-09 0:48 ` Scott Wood
2013-10-31 2:07 ` [U-Boot] [Patch v1 2/6] Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx York Sun
` (4 subsequent siblings)
5 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
---
Makefile | 4 +-
README | 39 ++++++++++++++--
arch/powerpc/cpu/mpc83xx/Makefile | 8 +---
arch/powerpc/cpu/mpc85xx/Makefile | 42 -----------------
arch/powerpc/cpu/mpc85xx/cpu.c | 16 +++----
arch/powerpc/cpu/mpc85xx/mp.c | 2 +-
arch/powerpc/cpu/mpc86xx/Makefile | 3 --
arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 45 ------------------
arch/powerpc/include/asm/config.h | 6 +++
arch/powerpc/include/asm/config_mpc85xx.h | 13 ++++++
arch/powerpc/include/asm/config_mpc86xx.h | 2 +
arch/powerpc/include/asm/immap_83xx.h | 2 +-
arch/powerpc/include/asm/immap_85xx.h | 6 +--
arch/powerpc/include/asm/immap_86xx.h | 4 +-
board/exmeritus/hww1u1a/ddr.c | 4 +-
board/exmeritus/hww1u1a/hww1u1a.c | 4 +-
board/freescale/b4860qds/ddr.c | 6 +--
board/freescale/bsc9131rdb/ddr.c | 4 +-
board/freescale/bsc9131rdb/spl_minimal.c | 4 +-
board/freescale/bsc9132qds/bsc9132qds.c | 4 +-
board/freescale/bsc9132qds/ddr.c | 4 +-
board/freescale/bsc9132qds/spl_minimal.c | 4 +-
board/freescale/c29xpcie/ddr.c | 4 +-
board/freescale/corenet_ds/ddr.c | 4 +-
board/freescale/corenet_ds/eth_p4080.c | 2 +-
board/freescale/corenet_ds/p3041ds_ddr.c | 2 +-
board/freescale/corenet_ds/p4080ds_ddr.c | 2 +-
board/freescale/corenet_ds/p5020ds_ddr.c | 2 +-
board/freescale/corenet_ds/p5040ds_ddr.c | 2 +-
board/freescale/mpc8349emds/ddr.c | 4 +-
board/freescale/mpc8349emds/mpc8349emds.c | 2 +-
board/freescale/mpc8536ds/ddr.c | 4 +-
board/freescale/mpc8536ds/mpc8536ds.c | 2 +-
board/freescale/mpc8540ads/ddr.c | 4 +-
board/freescale/mpc8540ads/mpc8540ads.c | 4 +-
board/freescale/mpc8541cds/ddr.c | 4 +-
board/freescale/mpc8541cds/mpc8541cds.c | 2 +-
board/freescale/mpc8544ds/ddr.c | 4 +-
board/freescale/mpc8544ds/mpc8544ds.c | 2 +-
board/freescale/mpc8548cds/ddr.c | 4 +-
board/freescale/mpc8548cds/mpc8548cds.c | 2 +-
board/freescale/mpc8555cds/ddr.c | 4 +-
board/freescale/mpc8555cds/mpc8555cds.c | 2 +-
board/freescale/mpc8560ads/ddr.c | 4 +-
board/freescale/mpc8560ads/mpc8560ads.c | 4 +-
board/freescale/mpc8568mds/ddr.c | 4 +-
board/freescale/mpc8568mds/mpc8568mds.c | 2 +-
board/freescale/mpc8569mds/ddr.c | 4 +-
board/freescale/mpc8569mds/mpc8569mds.c | 4 +-
board/freescale/mpc8572ds/ddr.c | 4 +-
board/freescale/mpc8572ds/mpc8572ds.c | 2 +-
board/freescale/mpc8610hpcd/ddr.c | 4 +-
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +-
board/freescale/mpc8641hpcn/ddr.c | 4 +-
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +-
board/freescale/p1010rdb/ddr.c | 4 +-
board/freescale/p1010rdb/spl_minimal.c | 4 +-
board/freescale/p1022ds/ddr.c | 4 +-
board/freescale/p1022ds/p1022ds.c | 2 +-
board/freescale/p1022ds/spl_minimal.c | 2 +-
board/freescale/p1023rdb/ddr.c | 4 +-
board/freescale/p1023rdb/p1023rdb.c | 2 +-
board/freescale/p1023rds/p1023rds.c | 4 +-
board/freescale/p1_p2_rdb/ddr.c | 2 +-
board/freescale/p1_p2_rdb_pc/ddr.c | 4 +-
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +-
board/freescale/p1_twr/ddr.c | 4 +-
board/freescale/p1_twr/p1_twr.c | 2 +-
board/freescale/p2020come/ddr.c | 4 +-
board/freescale/p2020ds/ddr.c | 4 +-
board/freescale/p2020ds/p2020ds.c | 4 +-
board/freescale/p2041rdb/ddr.c | 4 +-
board/freescale/t1040qds/ddr.c | 4 +-
board/freescale/t4qds/ddr.c | 4 +-
board/freescale/t4qds/eth.c | 2 +-
board/gdsys/p1022/controlcenterd.c | 2 +-
board/gdsys/p1022/ddr.c | 4 +-
board/keymile/kmp204x/ddr.c | 4 +-
board/sbc8548/ddr.c | 6 +--
board/sbc8548/sbc8548.c | 2 +-
board/sbc8641d/ddr.c | 4 +-
board/sbc8641d/sbc8641d.c | 2 +-
board/socrates/ddr.c | 4 +-
board/socrates/sdram.c | 4 +-
board/stx/stxgp3/ddr.c | 4 +-
board/stx/stxgp3/stxgp3.c | 2 +-
board/stx/stxssa/ddr.c | 4 +-
board/stx/stxssa/stxssa.c | 2 +-
board/xes/xpedite517x/ddr.c | 4 +-
board/xes/xpedite517x/xpedite517x.c | 2 +-
board/xes/xpedite520x/ddr.c | 4 +-
board/xes/xpedite537x/ddr.c | 4 +-
board/xes/xpedite550x/ddr.c | 4 +-
drivers/ddr/fsl/Makefile | 49 ++++++++++++++++++++
.../mpc8xxx/ddr => drivers/ddr/fsl}/ctrl_regs.c | 8 ++--
.../ddr => drivers/ddr/fsl}/ddr1_dimm_params.c | 4 +-
.../ddr => drivers/ddr/fsl}/ddr2_dimm_params.c | 4 +-
.../ddr => drivers/ddr/fsl}/ddr3_dimm_params.c | 4 +-
.../mpc8xxx/ddr => drivers/ddr/fsl}/interactive.c | 5 +-
.../ddr/fsl}/lc_common_dimm_params.c | 4 +-
.../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/main.c | 4 +-
.../ddr/fsl/mpc85xx_ddr_gen1.c | 6 +--
.../ddr/fsl/mpc85xx_ddr_gen2.c | 4 +-
.../ddr/fsl/mpc85xx_ddr_gen3.c | 16 +++----
.../ddr-8641.c => drivers/ddr/fsl/mpc86xx_ddr.c | 6 +--
.../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/options.c | 4 +-
.../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/util.c | 10 ++--
.../mpc8xxx/ddr => include}/common_timing_params.h | 0
.../cpu/mpc8xxx/ddr/ddr.h => include/fsl_ddr.h | 6 +--
.../include/asm => include}/fsl_ddr_dimm_params.h | 0
.../include/asm => include}/fsl_ddr_sdram.h | 0
nand_spl/board/freescale/mpc8569mds/nand_boot.c | 2 +-
nand_spl/board/freescale/p1023rds/nand_boot.c | 4 +-
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 2 +-
spl/Makefile | 2 +-
116 files changed, 304 insertions(+), 298 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/Makefile
create mode 100644 drivers/ddr/fsl/Makefile
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ctrl_regs.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr1_dimm_params.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr2_dimm_params.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr3_dimm_params.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/interactive.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/lc_common_dimm_params.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/main.c (99%)
rename arch/powerpc/cpu/mpc85xx/ddr-gen1.c => drivers/ddr/fsl/mpc85xx_ddr_gen1.c (93%)
rename arch/powerpc/cpu/mpc85xx/ddr-gen2.c => drivers/ddr/fsl/mpc85xx_ddr_gen2.c (96%)
rename arch/powerpc/cpu/mpc85xx/ddr-gen3.c => drivers/ddr/fsl/mpc85xx_ddr_gen3.c (97%)
rename arch/powerpc/cpu/mpc86xx/ddr-8641.c => drivers/ddr/fsl/mpc86xx_ddr.c (95%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/options.c (99%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/util.c (96%)
rename {arch/powerpc/cpu/mpc8xxx/ddr => include}/common_timing_params.h (100%)
rename arch/powerpc/cpu/mpc8xxx/ddr/ddr.h => include/fsl_ddr.h (97%)
rename {arch/powerpc/include/asm => include}/fsl_ddr_dimm_params.h (100%)
rename {arch/powerpc/include/asm => include}/fsl_ddr_sdram.h (100%)
diff --git a/Makefile b/Makefile
index 2d18d27..4dd2e2e 100644
--- a/Makefile
+++ b/Makefile
@@ -291,19 +291,17 @@ LIBS-y += drivers/spi/libspi.o
LIBS-y += drivers/dfu/libdfu.o
ifeq ($(CPU),mpc83xx)
LIBS-y += drivers/qe/libqe.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc85xx)
LIBS-y += drivers/qe/libqe.o
LIBS-y += drivers/net/fm/libfm.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
+LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/libddr.o
LIBS-y += drivers/rtc/librtc.o
LIBS-y += drivers/serial/libserial.o
LIBS-y += drivers/sound/libsound.o
diff --git a/README b/README
index 91c3ac0..fc5107f 100644
--- a/README
+++ b/README
@@ -423,16 +423,45 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
- CONFIG_SYS_FSL_DDR_EMU
- Specify emulator support for DDR. Some DDR features such as
- deskew training are not available.
-
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
values is arch specific.
+ CONFIG_SYS_FSL_DDR
+ Freescale DDR driver in use. This type of DDR controller is
+ found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+ SoCs.
+
+ CONFIG_SYS_FSL_DDR_ADDR
+ Freescale DDR memory-mapped register base.
+
+ CONFIG_SYS_FSL_DDR_EMU
+ Specify emulator support for DDR. Some DDR features such as
+ deskew training are not available.
+
+ CONFIG_SYS_FSL_DDR_PPC_GEN1
+ Freescale DDR1 controller.
+
+ CONFIG_SYS_FSL_DDR_PPC_GEN2
+ Freescale DDR2 controller.
+
+ CONFIG_SYS_FSL_DDR_PPC_GEN3
+ Freescale DDR3 controller.
+
+ CONFIG_FSL_DDR1
+ User config to use DDR1. It can be enabled for SoCs with
+ Freescale DDR1 or DDR2 controllers.
+
+ CONFIG_FSL_DDR2
+ User config to use DDR2. It can be eanbeld for SoCs with
+ Freescale DDR2 or DDR3 controllers.
+
+ CONFIG_FSL_DDR3
+ User config to use DDR3. It can be enabled for SoCs with
+ Freescale DDR3 controllers.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
@@ -3139,7 +3168,7 @@ FIT uImage format:
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
- arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+ drivers/ddr/fsl/libddr.o in SPL binary.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 6341cd4..8837da2 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -61,14 +61,8 @@ all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
-$(obj)ddr-gen1.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
-
$(obj)ddr-gen2.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
-
-$(obj)ddr-gen3.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
+ ln -sf $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.c $(obj)ddr-gen2.c
#########################################################################
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f70f0d7..5515767 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -34,48 +34,6 @@ SOBJS = $(SOBJS-y)
COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
COBJS-$(CONFIG_CPM2) += commproc.o
-# supports ddr1
-COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
-
-# supports ddr1/2
-COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
-COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
-COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
-
-# supports ddr1/2/3
-COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o
-COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
-COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
-COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
-COBJS-$(CONFIG_P1010) += ddr-gen3.o
-COBJS-$(CONFIG_P1011) += ddr-gen3.o
-COBJS-$(CONFIG_P1012) += ddr-gen3.o
-COBJS-$(CONFIG_P1013) += ddr-gen3.o
-COBJS-$(CONFIG_P1014) += ddr-gen3.o
-COBJS-$(CONFIG_P1020) += ddr-gen3.o
-COBJS-$(CONFIG_P1021) += ddr-gen3.o
-COBJS-$(CONFIG_P1022) += ddr-gen3.o
-COBJS-$(CONFIG_P1023) += ddr-gen3.o
-COBJS-$(CONFIG_P1024) += ddr-gen3.o
-COBJS-$(CONFIG_P1025) += ddr-gen3.o
-COBJS-$(CONFIG_P2010) += ddr-gen3.o
-COBJS-$(CONFIG_P2020) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
-COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
-COBJS-$(CONFIG_BSC9132) += ddr-gen3.o
-COBJS-$(CONFIG_PPC_T1040) += ddr-gen3.o
-
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_CORENET) += liodn.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1a0196c..552acc6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -22,7 +22,7 @@
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
- ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+ ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 5f198eb..88c8e65 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
index 04271b0..2ce16ad 100644
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ b/arch/powerpc/cpu/mpc86xx/Makefile
@@ -20,9 +20,6 @@ SOBJS-$(CONFIG_MP) += release.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
-# 8610 & 8641 are identical w/regards to DDR
-COBJS-$(CONFIG_MPC8610) += ddr-8641.o
-COBJS-$(CONFIG_MPC8641) += ddr-8641.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_MP) += mp.o
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
deleted file mode 100644
index 29523aa..0000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# Copyright 2008-2011 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)libddr.o
-
-COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-ifdef SPD
-COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
-endif
-
-COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
-
-SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 3c17c99..423a6fb 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,10 +9,16 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
+#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
+#define CONFIG_SYS_FSL_DDR
+#endif
+
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4cc12ee..37ab960 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -40,17 +40,20 @@
#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDR_PPC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDR_PPC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDR_PPC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@@ -59,6 +62,7 @@
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDR_PPC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@@ -77,17 +81,20 @@
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDR_PPC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8560)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
+#define CONFIG_SYS_FSL_DDR_PPC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8568)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
+#define CONFIG_SYS_FSL_DDR_PPC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
@@ -737,4 +744,10 @@
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
#endif
+#if !defined(CONFIG_SYS_FSL_DDR_PPC_GEN1) && \
+ !defined(CONFIG_SYS_FSL_DDR_PPC_GEN2) && \
+ !defined(CONFIG_SYS_FSL_DDR_PPC_GEN3)
+#define CONFIG_SYS_FSL_DDR_PPC_GEN3
+#endif
+
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index 694b110..4f9b225 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,6 +7,8 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
+#define CONFIG_SYS_FSL_DDR_86XX
+
/* SoC specific defines for Freescale MPC86xx processors */
#if defined(CONFIG_MPC8610)
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 3c86ff6..86c2dcb 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -1024,7 +1024,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 060e0d7..cc3414b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3045,11 +3045,11 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
+#define CONFIG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
+#define CONFIG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 2a704fe..046a434 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1253,9 +1253,9 @@ typedef struct immap {
extern immap_t *immr;
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
index 23a71d5..e1f6865 100644
--- a/board/exmeritus/hww1u1a/ddr.c
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 7c11e38..104987a 100644
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -13,7 +13,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -89,7 +89,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 2d14923..187c3b3 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -9,11 +9,11 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
+#include <fsl_ddr.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index a9e92f2..339c576 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
index dd5ea95..9746271 100644
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index a895e4e..31bbf62 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -20,7 +20,7 @@
#include <asm/fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#ifdef CONFIG_PCI
#include <pci.h>
@@ -134,7 +134,7 @@ void dsp_ddr_configure(void)
*to the DSP DDR controller as connected DDR memories are similar.
*/
ccsr_ddr_t __iomem *pa_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_ddr_t temp_ddr;
ccsr_ddr_t __iomem *dsp_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index b3130be..43f163a 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
index 2bf0a0c..0249dc5 100644
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -10,14 +10,14 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 57a9b61..968655c 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include "cpld.h"
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 18e2ff6..e7e893a 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index e5beb55..5cbec7f 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
index 5a8ed94..4dead9c 100644
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 844e1d7..d572a5f 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
index e65de36..9aaf6db 100644
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
index e65de36..9aaf6db 100644
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index 3d257d0..aae003d 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ec48487..1fe75c6 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -13,7 +13,7 @@
#include <spi.h>
#include <miiphy.h>
#ifdef CONFIG_FSL_DDR2
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index d10370c..ebe3ba4 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 5daab69..59e9a35 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 175eefc..97a5d19 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -168,7 +168,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 78d73b0..d2ac6c4 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 8115e5c..7b264dd 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -11,7 +11,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 6cf9bc1..aa30cab 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index dfd8fa6..1b33db6 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -11,7 +11,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index 996ffe2..b31ea34 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 51e4bb5..ca9b43c 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 78d73b0..d2ac6c4 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index e2093d1..de5f566 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 90a2522..7104e33 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
@@ -373,7 +373,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index b1f4f1f..6db92ef 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index ae80697..a8fdcb5 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 68f686b..ef404b1 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index c928a96..60f5577 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
@@ -231,7 +231,7 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 52e4f42..2bfc1a1 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 657df6a..2fb4257 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 6cf9bc1..aa30cab 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ffdcf24..aa99623 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -10,7 +10,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 651652a..7cd0395 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 46a543e..0cd9df1 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index ab1b41d..b0d95ea 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index d0e712e..aa2a344 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index 94d2c2b..09212bc 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 3d1951c..ba789a4 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index 8b34396..6c7e1ac 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
const static u32 sysclk_tbl[] = {
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
index 9fb61fd..d587df5 100644
--- a/board/freescale/p1023rdb/ddr.c
+++ b/board/freescale/p1023rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index b52b092..d2d4f83 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 7c54b65..2cfcdc4 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -58,7 +58,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 5bee22e..17d3bea 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -8,7 +8,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 81cc093..946d503 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -10,8 +10,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 50553da..966abb2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index adfa7b1..92437bc 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 67f69d7..a2ce75a 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index ea8db6f..0e0d058 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
index da80477..b642e12 100644
--- a/board/freescale/p2020come/ddr.c
+++ b/board/freescale/p2020come/ddr.c
@@ -5,8 +5,8 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index b12141f..3254e70 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 58a4223..dd8c6b1 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -68,7 +68,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index cc1bfae..b8bbcdf 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
struct board_specific_parameters {
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 4fd17da..da89a36 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -8,8 +8,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index d70c310..7586cc3 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index b5f488b..24cf907 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 81c22bc..8ccd9ce 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -29,7 +29,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
index 4a652de..7596736 100644
--- a/board/gdsys/p1022/ddr.c
+++ b/board/gdsys/p1022/ddr.c
@@ -12,8 +12,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index bd425aa..34ac697 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -11,8 +11,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 9508561..8817103 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
@@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 3cd945f..d584276 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 996ffe2..b31ea34 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 0b5e8dc..8160c7b 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index e9db476..6bad4da 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 313efae..356e8e8 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
@@ -24,7 +24,7 @@
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
index 9e79815..41d4cfe 100644
--- a/board/stx/stxgp3/ddr.c
+++ b/board/stx/stxgp3/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index bd683f6..c80d525 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
index 71be3bf..1ccd4c5 100644
--- a/board/stx/stxssa/ddr.c
+++ b/board/stx/stxssa/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index c08a18b..f5c3d75 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -19,7 +19,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index f48c02f..fd602ea 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -7,8 +7,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 1782042..b7ad349 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <fdt_support.h>
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index 3671cb8..5c5eadc 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index f41ae73..56b5a18 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 9fc6f04..0c0605e 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
new file mode 100644
index 0000000..cbbd178
--- /dev/null
+++ b/drivers/ddr/fsl/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright 2008-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# Version 2 as published by the Free Software Foundation.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libddr.o
+
+COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+
+COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+
+COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
+endif
+
+COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN1) += mpc85xx_ddr_gen1.o
+COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN2) += mpc85xx_ddr_gen2.o
+COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN3) += mpc85xx_ddr_gen3.o
+COBJS-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
+COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
rename to drivers/ddr/fsl/ctrl_regs.c
index dcfc48a..9651c39 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -11,11 +11,13 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
-#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
static u32 fsl_ddr_get_version(void)
{
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
rename to drivers/ddr/fsl/ddr1_dimm_params.c
index f137fce..7df27b9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -7,9 +7,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
rename to drivers/ddr/fsl/ddr2_dimm_params.c
index e4d02e8..d865df7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -7,9 +7,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
* Returned size is in bytes.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
rename to drivers/ddr/fsl/ddr3_dimm_params.c
index 4c8645d..a4b8c10 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/drivers/ddr/fsl/ddr3_dimm_params.c
@@ -12,9 +12,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Calculate the Density of each Physical Rank.
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/drivers/ddr/fsl/interactive.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
rename to drivers/ddr/fsl/interactive.c
index 3b66112..322c051 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -14,9 +14,10 @@
#include <common.h>
#include <linux/ctype.h>
#include <asm/types.h>
+#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
/* Option parameter Structures */
struct options_string {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
rename to drivers/ddr/fsl/lc_common_dimm_params.c
index 332fe25..cd9894d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -7,9 +7,9 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
#if defined(CONFIG_FSL_DDR3)
static unsigned int
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/drivers/ddr/fsl/main.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/main.c
rename to drivers/ddr/fsl/main.c
index 34d8bc3a..c1cdbdf 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -14,10 +14,10 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
similarity index 93%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen1.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 4dd8c0b..ff7d979 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -73,7 +73,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
void
ddr_enable_ecc(unsigned int dram_size)
{
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
similarity index 96%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen2.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index 542bc84..c22dea5 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -19,7 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
- ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
similarity index 97%
rename from arch/powerpc/cpu/mpc85xx/ddr-gen3.c
rename to drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1be51d3..7b4e8ec 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -42,21 +42,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/drivers/ddr/fsl/mpc86xx_ddr.c
similarity index 95%
rename from arch/powerpc/cpu/mpc86xx/ddr-8641.c
rename to drivers/ddr/fsl/mpc86xx_ddr.c
index 33a91f9..caffbaf 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/drivers/ddr/fsl/mpc86xx_ddr.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
case 1:
- ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/drivers/ddr/fsl/options.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/ddr/options.c
rename to drivers/ddr/fsl/options.c
index 1297845..2dcd721 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <hwconfig.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
/*
* Use our own stack based buffer before relocation to allow accessing longer
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/drivers/ddr/fsl/util.c
similarity index 96%
rename from arch/powerpc/cpu/mpc8xxx/ddr/util.c
rename to drivers/ddr/fsl/util.c
index acfe1f0..712bf01 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -10,7 +10,9 @@
#include <asm/fsl_law.h>
#include <div64.h>
-#include "ddr.h"
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
/* To avoid 64-bit full-divides, we factor this here */
#define ULL_2E12 2000000000000ULL
@@ -133,7 +135,7 @@ u32 fsl_ddr_get_intl3r(void)
void board_add_ram_info(int use_default)
{
- ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
@@ -146,13 +148,13 @@ void board_add_ram_info(int use_default)
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
- ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+ ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
- ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+ ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/include/common_timing_params.h
similarity index 100%
rename from arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
rename to include/common_timing_params.h
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/include/fsl_ddr.h
similarity index 97%
rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
rename to include/fsl_ddr.h
index e3b414e..e03f9db 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/include/fsl_ddr.h
@@ -9,10 +9,10 @@
#ifndef FSL_DDR_MAIN_H
#define FSL_DDR_MAIN_H
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
-#include "common_timing_params.h"
+#include <common_timing_params.h>
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_ddr_dimm_params.h
rename to include/fsl_ddr_dimm_params.h
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_ddr_sdram.h
rename to include/fsl_ddr_sdram.h
diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
index 716b737..ce7f619 100644
--- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c
+++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#define SYSCLK_66 66666666
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 9468000..58e6cbf 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -10,7 +10,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
index 3244c8f..f7e8438 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#define SYSCLK_MASK 0x00200000
diff --git a/spl/Makefile b/spl/Makefile
index b366ac2..df15cf7 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -63,7 +63,7 @@ endif
ifeq ($(CPU),mpc85xx)
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/libddr.o
endif
endif
ifeq ($(CPU),mpc86xx)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 2/6] Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver York Sun
@ 2013-10-31 2:07 ` York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM York Sun
` (3 subsequent siblings)
5 siblings, 0 replies; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.
Signed-off-by: York Sun <yorksun@freescale.com>
---
arch/powerpc/cpu/mpc83xx/ecc.c | 4 +-
arch/powerpc/cpu/mpc85xx/cpu.c | 4 +-
arch/powerpc/include/asm/immap_83xx.h | 106 ++---------------------
arch/powerpc/include/asm/immap_85xx.h | 100 +---------------------
arch/powerpc/include/asm/immap_86xx.h | 74 +---------------
board/exmeritus/hww1u1a/hww1u1a.c | 3 +-
board/freescale/bsc9131rdb/spl_minimal.c | 3 +-
board/freescale/bsc9132qds/bsc9132qds.c | 14 ++--
board/freescale/bsc9132qds/spl_minimal.c | 3 +-
board/freescale/mpc8536ds/mpc8536ds.c | 2 +-
board/freescale/mpc8540ads/mpc8540ads.c | 3 +-
board/freescale/mpc8569mds/mpc8569mds.c | 3 +-
board/freescale/mpc8572ds/mpc8572ds.c | 2 +-
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +-
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +-
board/freescale/p1010rdb/spl_minimal.c | 3 +-
board/freescale/p1023rds/p1023rds.c | 3 +-
board/freescale/p2020ds/p2020ds.c | 3 +-
board/sbc8548/ddr.c | 3 +-
board/sbc8641d/sbc8641d.c | 6 +-
board/socrates/sdram.c | 3 +-
drivers/ddr/fsl/ctrl_regs.c | 2 +-
drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 6 +-
drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 3 +-
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +-
drivers/ddr/fsl/mpc86xx_ddr.c | 4 +-
drivers/ddr/fsl/util.c | 3 +-
include/fsl_immap.h | 112 +++++++++++++++++++++++++
nand_spl/board/freescale/p1023rds/nand_boot.c | 3 +-
29 files changed, 173 insertions(+), 308 deletions(-)
create mode 100644 include/fsl_immap.h
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 120b37b..25b7261 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -16,7 +16,7 @@ void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
- ccsr_ddr_t *ddr = &immap->ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif
@@ -100,7 +100,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
- ccsr_ddr_t *ddr = &immap->ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 552acc6..b5a0242 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void)
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
@@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
- for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+ for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 86c2dcb..8d73dcb 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -14,6 +14,7 @@
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
+#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
@@ -277,107 +278,10 @@ typedef struct qesba83xx {
} qesba83xx_t;
/*
- * DDR Memory Controller Memory Map
+ * DDR Memory Controller Memory Map for DDR1
+ * The structure of DDR2, or DDR3 is defined in fsl_immap.h
*/
-#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-typedef struct ccsr_ddr {
- u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
- u8 res1[4];
- u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
- u8 res2[4];
- u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
- u8 res3[4];
- u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
- u8 res4[100];
- u32 cs0_config; /* Chip Select Configuration */
- u32 cs1_config; /* Chip Select Configuration */
- u32 cs2_config; /* Chip Select Configuration */
- u32 cs3_config; /* Chip Select Configuration */
- u8 res4a[48];
- u32 cs0_config_2; /* Chip Select Configuration 2 */
- u32 cs1_config_2; /* Chip Select Configuration 2 */
- u32 cs2_config_2; /* Chip Select Configuration 2 */
- u32 cs3_config_2; /* Chip Select Configuration 2 */
- u8 res5[48];
- u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
- u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
- u32 sdram_cfg; /* SDRAM Control Configuration */
- u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
- u32 sdram_mode; /* SDRAM Mode Configuration */
- u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
- u32 sdram_md_cntl; /* SDRAM Mode Control */
- u32 sdram_interval; /* SDRAM Interval Configuration */
- u32 sdram_data_init; /* SDRAM Data initialization */
- u8 res6[4];
- u32 sdram_clk_cntl; /* SDRAM Clock Control */
- u8 res7[20];
- u32 init_addr; /* training init addr */
- u32 init_ext_addr; /* training init extended addr */
- u8 res8_1[16];
- u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
- u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg8_1a[8];
- u32 ddr_zq_cntl; /* ZQ calibration control*/
- u32 ddr_wrlvl_cntl; /* write leveling control*/
- u8 reg8_1aa[4];
- u32 ddr_sr_cntr; /* self refresh counter */
- u32 ddr_sdram_rcw_1; /* Control Words 1 */
- u32 ddr_sdram_rcw_2; /* Control Words 2 */
- u8 reg_1ab[8];
- u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
- u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res8_1b[104];
- u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
- u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
- u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
- u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
- u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
- u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res8_1ba[0x908];
- u32 ddr_dsr1; /* Debug Status 1 */
- u32 ddr_dsr2; /* Debug Status 2 */
- u32 ddr_cdr1; /* Control Driver 1 */
- u32 ddr_cdr2; /* Control Driver 2 */
- u8 res8_1c[200];
- u32 ip_rev1; /* IP Block Revision 1 */
- u32 ip_rev2; /* IP Block Revision 2 */
- u32 eor; /* Enhanced Optimization Register */
- u8 res8_2[252];
- u32 mtcr; /* Memory Test Control Register */
- u8 res8_3[28];
- u32 mtp1; /* Memory Test Pattern 1 */
- u32 mtp2; /* Memory Test Pattern 2 */
- u32 mtp3; /* Memory Test Pattern 3 */
- u32 mtp4; /* Memory Test Pattern 4 */
- u32 mtp5; /* Memory Test Pattern 5 */
- u32 mtp6; /* Memory Test Pattern 6 */
- u32 mtp7; /* Memory Test Pattern 7 */
- u32 mtp8; /* Memory Test Pattern 8 */
- u32 mtp9; /* Memory Test Pattern 9 */
- u32 mtp10; /* Memory Test Pattern 10 */
- u8 res8_4[184];
- u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
- u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
- u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
- u8 res9[20];
- u32 capture_data_hi; /* Data Path Read Capture High */
- u32 capture_data_lo; /* Data Path Read Capture Low */
- u32 capture_ecc; /* Data Path Read Capture ECC */
- u8 res10[20];
- u32 err_detect; /* Error Detect */
- u32 err_disable; /* Error Disable */
- u32 err_int_en;
- u32 capture_attributes; /* Error Attrs Capture */
- u32 capture_address; /* Error Addr Capture */
- u32 capture_ext_address; /* Error Extended Addr Capture */
- u32 err_sbe; /* Single-Bit ECC Error Management */
- u8 res11[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res12[128];
-} ccsr_ddr_t;
-#else
+#if !defined(CONFIG_FSL_DDR2) && !defined(CONFIG_FSL_DDR3)
typedef struct ddr_cs_bnds {
u32 csbnds;
u8 res0[4];
@@ -740,7 +644,7 @@ typedef struct immap {
u8 dll_lbc[0x100];
u8 res1[0xE00];
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
- ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
+ struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
#else
ddr83xx_t ddr; /* DDR Memory Controller Memory */
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index cc3414b..b451f2a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -18,6 +18,7 @@
#include <asm/fsl_ifc.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
+#include <fsl_immap.h>
typedef struct ccsr_local {
u32 ccsrbarh; /* CCSR Base Addr High */
@@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm {
u8 res24[492];
} ccsr_local_ecm_t;
-/* DDR memory controller registers */
-typedef struct ccsr_ddr {
- u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
- u8 res1[4];
- u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
- u8 res2[4];
- u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
- u8 res3[4];
- u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
- u8 res4[100];
- u32 cs0_config; /* Chip Select Configuration */
- u32 cs1_config; /* Chip Select Configuration */
- u32 cs2_config; /* Chip Select Configuration */
- u32 cs3_config; /* Chip Select Configuration */
- u8 res4a[48];
- u32 cs0_config_2; /* Chip Select Configuration 2 */
- u32 cs1_config_2; /* Chip Select Configuration 2 */
- u32 cs2_config_2; /* Chip Select Configuration 2 */
- u32 cs3_config_2; /* Chip Select Configuration 2 */
- u8 res5[48];
- u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
- u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
- u32 sdram_cfg; /* SDRAM Control Configuration */
- u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
- u32 sdram_mode; /* SDRAM Mode Configuration */
- u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
- u32 sdram_md_cntl; /* SDRAM Mode Control */
- u32 sdram_interval; /* SDRAM Interval Configuration */
- u32 sdram_data_init; /* SDRAM Data initialization */
- u8 res6[4];
- u32 sdram_clk_cntl; /* SDRAM Clock Control */
- u8 res7[20];
- u32 init_addr; /* training init addr */
- u32 init_ext_addr; /* training init extended addr */
- u8 res8_1[16];
- u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
- u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg8_1a[8];
- u32 ddr_zq_cntl; /* ZQ calibration control*/
- u32 ddr_wrlvl_cntl; /* write leveling control*/
- u8 reg8_1aa[4];
- u32 ddr_sr_cntr; /* self refresh counter */
- u32 ddr_sdram_rcw_1; /* Control Words 1 */
- u32 ddr_sdram_rcw_2; /* Control Words 2 */
- u8 reg_1ab[8];
- u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
- u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res8_1b[104];
- u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
- u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
- u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
- u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
- u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
- u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res8_1ba[0x908];
- u32 ddr_dsr1; /* Debug Status 1 */
- u32 ddr_dsr2; /* Debug Status 2 */
- u32 ddr_cdr1; /* Control Driver 1 */
- u32 ddr_cdr2; /* Control Driver 2 */
- u8 res8_1c[200];
- u32 ip_rev1; /* IP Block Revision 1 */
- u32 ip_rev2; /* IP Block Revision 2 */
- u32 eor; /* Enhanced Optimization Register */
- u8 res8_2[252];
- u32 mtcr; /* Memory Test Control Register */
- u8 res8_3[28];
- u32 mtp1; /* Memory Test Pattern 1 */
- u32 mtp2; /* Memory Test Pattern 2 */
- u32 mtp3; /* Memory Test Pattern 3 */
- u32 mtp4; /* Memory Test Pattern 4 */
- u32 mtp5; /* Memory Test Pattern 5 */
- u32 mtp6; /* Memory Test Pattern 6 */
- u32 mtp7; /* Memory Test Pattern 7 */
- u32 mtp8; /* Memory Test Pattern 8 */
- u32 mtp9; /* Memory Test Pattern 9 */
- u32 mtp10; /* Memory Test Pattern 10 */
- u8 res8_4[184];
- u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
- u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
- u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
- u8 res9[20];
- u32 capture_data_hi; /* Data Path Read Capture High */
- u32 capture_data_lo; /* Data Path Read Capture Low */
- u32 capture_ecc; /* Data Path Read Capture ECC */
- u8 res10[20];
- u32 err_detect; /* Error Detect */
- u32 err_disable; /* Error Disable */
- u32 err_int_en;
- u32 capture_attributes; /* Error Attrs Capture */
- u32 capture_address; /* Error Addr Capture */
- u32 capture_ext_address; /* Error Extended Addr Capture */
- u32 err_sbe; /* Single-Bit ECC Error Management */
- u8 res11[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res12[128];
-} ccsr_ddr_t;
-
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 046a434..177918b 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -10,6 +10,7 @@
#ifndef __IMMAP_86xx__
#define __IMMAP_86xx__
+#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_lbc.h>
@@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm {
char res31[488];
} ccsr_local_mcm_t;
-/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
-
-typedef struct ccsr_ddr {
- uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
- char res1[4];
- uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
- char res2[4];
- uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
- char res3[4];
- uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
- char res4[4];
- uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
- char res5[4];
- uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
- char res6[84];
- uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
- uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
- uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
- uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
- uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
- uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
- char res7[104];
- uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
- uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
- uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
- uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
- uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
- uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
- uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
- uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
- uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
- uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
- uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
- char res8[4];
- uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
- char res9[12];
- uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
- uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
- uint init_addr; /* 0x2148 - DDR training initialzation address */
- uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
- char res10[2728];
- uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
- uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
- char res11[512];
- uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
- uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
- uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
- char res12[20];
- uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
- uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
- uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
- char res13[20];
- uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
- uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
- uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
- uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
- uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
- uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
- uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
- char res14[164];
- uint debug_1; /* 0x2f00 */
- uint debug_2;
- uint debug_3;
- uint debug_4;
- uint debug_5;
- char res15[236];
-} ccsr_ddr_t;
-
-
/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
struct fsl_i2c i2c[2];
@@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt {
typedef struct immap {
ccsr_local_mcm_t im_local_mcm;
- ccsr_ddr_t im_ddr1;
+ struct ccsr_ddr im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
fsl_lbc_t im_lbc;
- ccsr_ddr_t im_ddr2;
+ struct ccsr_ddr im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
ccsr_pex_t im_pex2;
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 104987a..97b84b3 100644
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -37,6 +37,7 @@ int checkboard(void)
unsigned int gpio_low = 0;
unsigned int gpio_in = 0;
unsigned int i;
+ struct ccsr_ddr __iomem *ddr;
puts("Board: HWW-1U-1A ");
@@ -89,7 +90,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
index 9746271..bd8560b 100644
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 31bbf62..c1ebcf8 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -133,16 +133,16 @@ void dsp_ddr_configure(void)
*copy the ddr controller settings from PowerPC side DDR controller
*to the DSP DDR controller as connected DDR memories are similar.
*/
- ccsr_ddr_t __iomem *pa_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- ccsr_ddr_t temp_ddr;
- ccsr_ddr_t __iomem *dsp_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+ struct ccsr_ddr __iomem *pa_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr temp_ddr;
+ struct ccsr_ddr __iomem *dsp_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
- memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
+ memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
- memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
+ memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
index 0249dc5..8f71431 100644
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -17,7 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 59e9a35..467f4f2 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -90,7 +90,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 97a5d19..93288c7 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -168,7 +168,8 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 60f5577..cb55e1c 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -231,7 +231,8 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 2fb4257..5686322 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -62,7 +62,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index aa99623..d8740dd 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 0cd9df1..a58b5f9 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -64,7 +64,7 @@ fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index aa2a344..39a5a0f 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -19,7 +19,8 @@ DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 2cfcdc4..d8c8745 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -58,7 +58,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index dd8c6b1..a0cf927 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -68,7 +68,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 8817103..24cc776 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 8160c7b..4906be4 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -93,7 +93,7 @@ long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
@@ -111,7 +111,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
@@ -142,7 +142,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 356e8e8..aebd02f 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -24,7 +24,8 @@
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9651c39..0258903 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -21,7 +21,7 @@
static u32 fsl_ddr_get_version(void)
{
- ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
u32 ver_major_minor_errata;
ddr = (void *)_DDR_ADDR;
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index ff7d979..8dd4a91 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -18,7 +18,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -73,7 +74,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
void
ddr_enable_ecc(unsigned int dram_size)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index c22dea5..988b4a4 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -19,7 +19,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
- ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 7b4e8ec..9f04133 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -29,7 +29,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
- volatile ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
index caffbaf..4551ed8 100644
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ b/drivers/ddr/fsl/mpc86xx_ddr.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr;
+ struct ccsr_ddr __iomem *ddr;
switch (ctrl_num) {
case 0:
@@ -58,7 +58,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
- out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 712bf01..5d6b362 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -135,7 +135,8 @@ u32 fsl_ddr_get_intl3r(void)
void board_add_ram_info(int use_default)
{
- ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
new file mode 100644
index 0000000..00902ca
--- /dev/null
+++ b/include/fsl_immap.h
@@ -0,0 +1,112 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_IMMAP_H
+#define __FSL_IMMAP_H
+/*
+ * DDR memory controller registers
+ * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ */
+struct ccsr_ddr {
+ u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
+ u8 res_04[4];
+ u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
+ u8 res_0c[4];
+ u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
+ u8 res_14[4];
+ u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
+ u8 res_1c[100];
+ u32 cs0_config; /* Chip Select Configuration */
+ u32 cs1_config; /* Chip Select Configuration */
+ u32 cs2_config; /* Chip Select Configuration */
+ u32 cs3_config; /* Chip Select Configuration */
+ u8 res_90[48];
+ u32 cs0_config_2; /* Chip Select Configuration 2 */
+ u32 cs1_config_2; /* Chip Select Configuration 2 */
+ u32 cs2_config_2; /* Chip Select Configuration 2 */
+ u32 cs3_config_2; /* Chip Select Configuration 2 */
+ u8 res_d0[48];
+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ u32 sdram_cfg; /* SDRAM Control Configuration */
+ u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ u32 sdram_mode; /* SDRAM Mode Configuration */
+ u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ u32 sdram_md_cntl; /* SDRAM Mode Control */
+ u32 sdram_interval; /* SDRAM Interval Configuration */
+ u32 sdram_data_init; /* SDRAM Data initialization */
+ u8 res_12c[4];
+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
+ u8 res_134[20];
+ u32 init_addr; /* training init addr */
+ u32 init_ext_addr; /* training init extended addr */
+ u8 res_150[16];
+ u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ u8 reg_168[8];
+ u32 ddr_zq_cntl; /* ZQ calibration control*/
+ u32 ddr_wrlvl_cntl; /* write leveling control*/
+ u8 reg_178[4];
+ u32 ddr_sr_cntr; /* self refresh counter */
+ u32 ddr_sdram_rcw_1; /* Control Words 1 */
+ u32 ddr_sdram_rcw_2; /* Control Words 2 */
+ u8 reg_188[8];
+ u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ u8 res_198[104];
+ u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ u8 res_218[0x908];
+ u32 ddr_dsr1; /* Debug Status 1 */
+ u32 ddr_dsr2; /* Debug Status 2 */
+ u32 ddr_cdr1; /* Control Driver 1 */
+ u32 ddr_cdr2; /* Control Driver 2 */
+ u8 res_b30[200];
+ u32 ip_rev1; /* IP Block Revision 1 */
+ u32 ip_rev2; /* IP Block Revision 2 */
+ u32 eor; /* Enhanced Optimization Register */
+ u8 res_c04[252];
+ u32 mtcr; /* Memory Test Control Register */
+ u8 res_d04[28];
+ u32 mtp1; /* Memory Test Pattern 1 */
+ u32 mtp2; /* Memory Test Pattern 2 */
+ u32 mtp3; /* Memory Test Pattern 3 */
+ u32 mtp4; /* Memory Test Pattern 4 */
+ u32 mtp5; /* Memory Test Pattern 5 */
+ u32 mtp6; /* Memory Test Pattern 6 */
+ u32 mtp7; /* Memory Test Pattern 7 */
+ u32 mtp8; /* Memory Test Pattern 8 */
+ u32 mtp9; /* Memory Test Pattern 9 */
+ u32 mtp10; /* Memory Test Pattern 10 */
+ u8 res_d48[184];
+ u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
+ u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
+ u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ u8 res_e0c[20];
+ u32 capture_data_hi; /* Data Path Read Capture High */
+ u32 capture_data_lo; /* Data Path Read Capture Low */
+ u32 capture_ecc; /* Data Path Read Capture ECC */
+ u8 res_e2c[20];
+ u32 err_detect; /* Error Detect */
+ u32 err_disable; /* Error Disable */
+ u32 err_int_en;
+ u32 capture_attributes; /* Error Attrs Capture */
+ u32 capture_address; /* Error Addr Capture */
+ u32 capture_ext_address; /* Error Extended Addr Capture */
+ u32 err_sbe; /* Single-Bit ECC Error Management */
+ u8 res_e5c[164];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res_f80[128];
+};
+#endif /* __FSL_IMMAP_H */
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 58e6cbf..d9afa6d 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -18,7 +18,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 2/6] Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx York Sun
@ 2013-10-31 2:07 ` York Sun
2013-11-09 0:51 ` Scott Wood
2013-10-31 2:07 ` [U-Boot] [Patch v1 4/6] powerpc/mpc8xxx: Extend DDR registers' fields York Sun
` (2 subsequent siblings)
5 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.
Signed-off-by: York Sun <yorksun@freescale.com>
---
drivers/ddr/fsl/Makefile | 1 +
drivers/ddr/fsl/arm_ddr_gen3.c | 213 ++++++++++++++++++++++++++++++++++++++++
drivers/ddr/fsl/main.c | 12 ++-
drivers/ddr/fsl/util.c | 4 +
4 files changed, 227 insertions(+), 3 deletions(-)
create mode 100644 drivers/ddr/fsl/arm_ddr_gen3.c
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index cbbd178..381ec6c 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN1) += mpc85xx_ddr_gen1.o
COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN2) += mpc85xx_ddr_gen2.o
COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN3) += mpc85xx_ddr_gen3.o
COBJS-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
+COBJS-$(CONFIG_SYS_FSL_DDR_ARM_GEN3) += arm_ddr_gen3.o
COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
new file mode 100644
index 0000000..bf11390
--- /dev/null
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_immap.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num, int step)
+{
+ unsigned int i, bus_width;
+ struct ccsr_ddr __iomem *ddr;
+ u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ case 1:
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+ case 2:
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+ case 3:
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+ return;
+ }
+
+ if (step == 2)
+ goto step2;
+
+ if (regs->ddr_eor)
+ out_be32(&ddr->eor, regs->ddr_eor);
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs0_config, regs->cs[i].config);
+ out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+ } else if (i == 1) {
+ out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs1_config, regs->cs[i].config);
+ out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+ } else if (i == 2) {
+ out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs2_config, regs->cs[i].config);
+ out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+ } else if (i == 3) {
+ out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs3_config, regs->cs[i].config);
+ out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ }
+ }
+
+ out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+ out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+ out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
+ if (regs->ddr_wrlvl_cntl_2)
+ out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+ out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ out_be32(&ddr->err_disable, regs->err_disable);
+ out_be32(&ddr->err_int_en, regs->err_int_en);
+ for (i = 0; i < 32; i++) {
+ if (regs->debug[i]) {
+ debug("Write to debug_%d as %08x\n", i + 1,
+ regs->debug[i]);
+ out_be32(&ddr->debug[i], regs->debug[i]);
+ }
+ }
+
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+ /*
+ * 500 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
+ */
+ udelay(500);
+ asm volatile("dsb sy;isb");
+
+ /* Let the controller go */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ asm volatile("dsb sy;isb");
+
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (regs->cs[0].config & 0x20000000) {
+ /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ }
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 1;
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
+}
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index c1cdbdf..b4988e1 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -15,16 +15,18 @@
#include <common.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
#include <fsl_ddr.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_law.h>
+
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
-void fsl_ddr_set_intl3r(const unsigned int granule_size);
+#endif
+void fsl_ddr_set_intl3r(const unsigned int granule_size);
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -549,7 +551,9 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
phys_size_t fsl_ddr_sdram(void)
{
unsigned int i;
+#ifdef CONFIG_PPC
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
+#endif
unsigned long long total_memory;
fsl_ddr_info_t info;
int deassert_reset;
@@ -621,6 +625,7 @@ phys_size_t fsl_ddr_sdram(void)
}
}
+#ifdef CONFIG_PPC
/* program LAWs */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (info.memctl_opts[i].memctl_interleaving) {
@@ -681,6 +686,7 @@ phys_size_t fsl_ddr_sdram(void)
law_memctl, i);
}
}
+#endif
debug("total_memory by %s = %llu\n", __func__, total_memory);
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 5d6b362..0658261 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -7,7 +7,9 @@
*/
#include <common.h>
+#ifdef CONFIG_PPC
#include <asm/fsl_law.h>
+#endif
#include <div64.h>
#include <fsl_ddr.h>
@@ -79,6 +81,7 @@ unsigned int mclk_to_picos(unsigned int mclk)
return get_memory_clk_period_ps() * mclk;
}
+#ifdef CONFIG_PPC
void
__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int law_memctl,
@@ -113,6 +116,7 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
+#endif
void fsl_ddr_set_intl3r(const unsigned int granule_size)
{
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 4/6] powerpc/mpc8xxx: Extend DDR registers' fields
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
` (2 preceding siblings ...)
2013-10-31 2:07 ` [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM York Sun
@ 2013-10-31 2:07 ` York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 5/6] Driver/DDR: Update DDR driver to allow non-zero base address York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver York Sun
5 siblings, 0 replies; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
---
drivers/ddr/fsl/ctrl_regs.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 0258903..096c14e 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -325,10 +325,10 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
| ((twrt_mclk & 0x3) << 28) /* WRT */
| ((trrt_mclk & 0x3) << 26) /* RRT */
| ((twwt_mclk & 0x3) << 24) /* WWT */
- | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
+ | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
| ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
| ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
- | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
+ | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
}
@@ -338,7 +338,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
- unsigned int cas_latency)
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
@@ -350,6 +351,8 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
unsigned int ext_refrec;
/* Extended MCAS latency from READ cmd */
unsigned int ext_caslat = 0;
+ /* Extended additive latency */
+ unsigned int ext_add_lat = 0;
/* Extended last data to precharge interval (tWR) */
unsigned int ext_wrrec = 0;
/* Control Adjust */
@@ -359,6 +362,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
+ ext_add_lat = additive_latency >> 4;
ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
@@ -370,6 +374,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
+ | ((ext_add_lat & 0x1) << 10)
| ((ext_wrrec & 0x1) << 8)
| ((cntl_adj & 0x7) << 0)
);
@@ -531,8 +536,6 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
if (rd_to_pre < 4)
rd_to_pre = 4;
#endif
- if (additive_latency)
- rd_to_pre += additive_latency;
if (popts->otf_burst_chop_en)
rd_to_pre += 2; /* according to UM */
@@ -1592,8 +1595,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
if (cs_en) {
ddr->cs[i].bnds = (0
- | ((sa & 0xFFF) << 16)/* starting address MSB */
- | ((ea & 0xFFF) << 0) /* ending address MSB */
+ | ((sa & 0xffff) << 16) /* starting address */
+ | ((ea & 0xffff) << 0) /* ending address */
);
} else {
/* setting bnds to 0xffffffff for inactive CS */
@@ -1618,7 +1621,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_timing_cfg_0(ddr, popts, dimm_params);
#endif
- set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+ additive_latency);
set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
set_timing_cfg_2(ddr, popts, common_dimm,
cas_latency, additive_latency);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 5/6] Driver/DDR: Update DDR driver to allow non-zero base address
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
` (3 preceding siblings ...)
2013-10-31 2:07 ` [U-Boot] [Patch v1 4/6] powerpc/mpc8xxx: Extend DDR registers' fields York Sun
@ 2013-10-31 2:07 ` York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver York Sun
5 siblings, 0 replies; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <yorksun@freescale.com>
---
drivers/ddr/fsl/main.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index b4988e1..d0cd589 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -255,7 +255,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
- current_mem_base = 0ull;
+ current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
}
}
- total_mem = 1 + (((unsigned long long)max_end << 24ULL)
- | 0xFFFFFFULL);
+ total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+ 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
}
return total_mem;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
` (4 preceding siblings ...)
2013-10-31 2:07 ` [U-Boot] [Patch v1 5/6] Driver/DDR: Update DDR driver to allow non-zero base address York Sun
@ 2013-10-31 2:07 ` York Sun
2013-10-31 3:27 ` Prabhakar Kushwaha
5 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-10-31 2:07 UTC (permalink / raw)
To: u-boot
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/mtd
and fix the header file includes.
Signed-off-by: York Sun <yorksun@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu.c | 2 +-
arch/powerpc/cpu/mpc85xx/spl_minimal.c | 2 +-
arch/powerpc/cpu/mpc8xxx/Makefile | 1 -
arch/powerpc/include/asm/immap_85xx.h | 2 +-
board/freescale/bsc9132qds/bsc9132qds.c | 2 +-
board/freescale/c29xpcie/c29xpcie.c | 2 +-
board/freescale/p1010rdb/p1010rdb.c | 2 +-
drivers/mtd/Makefile | 1 +
.../powerpc/cpu/mpc8xxx => drivers/mtd}/fsl_ifc.c | 2 +-
drivers/mtd/nand/fsl_ifc_nand.c | 2 +-
drivers/mtd/nand/fsl_ifc_spl.c | 2 +-
{arch/powerpc/include/asm => include}/fsl_ifc.h | 6 +++---
12 files changed, 13 insertions(+), 13 deletions(-)
rename {arch/powerpc/cpu/mpc8xxx => drivers/mtd}/fsl_ifc.c (99%)
rename {arch/powerpc/include/asm => include}/fsl_ifc.h (99%)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index b5a0242..3e99b07 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -17,7 +17,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 199b33e..9e4c6c9 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 3dc8e05..3e8a4eb 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -29,7 +29,6 @@ COBJS-y += cpu.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
COBJS-$(CONFIG_SYS_SRIO) += srio.o
COBJS-$(CONFIG_FSL_LAW) += law.o
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b451f2a..0f9cdae 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -15,7 +15,7 @@
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_i2c.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
#include <fsl_immap.h>
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index c1ebcf8..9377280 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -17,7 +17,7 @@
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 48c4b30..f964d61 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -18,7 +18,7 @@
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include "cpld.h"
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index e940d22..62caf67 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -19,7 +19,7 @@
#include <netdev.h>
#include <pci.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include <hwconfig.h>
#include <i2c.h>
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index d2c3bda..c75bb4d 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -22,6 +22,7 @@ COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
COBJS-$(CONFIG_ST_SMI) += st_smi.o
+COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/drivers/mtd/fsl_ifc.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
rename to drivers/mtd/fsl_ifc.c
index 2d0fb43..507c4de 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/drivers/mtd/fsl_ifc.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
void print_ifc_regs(void)
{
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 98a09c0..3b845b9 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -17,7 +17,7 @@
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#define FSL_IFC_V1_1_0 0x01010000
#define MAX_BANKS 4
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index d462265..3c8278d 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <linux/mtd/nand.h>
static inline int is_blank(uchar *addr, int page_size)
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/include/fsl_ifc.h
similarity index 99%
rename from arch/powerpc/include/asm/fsl_ifc.h
rename to include/fsl_ifc.h
index a945e4b..3e9b01b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __ASM_PPC_FSL_IFC_H
-#define __ASM_PPC_FSL_IFC_H
+#ifndef __FSL_IFC_H
+#define __FSL_IFC_H
#ifdef CONFIG_FSL_IFC
#include <config.h>
@@ -983,4 +983,4 @@ struct fsl_ifc {
#endif /* CONFIG_FSL_IFC */
#endif /* __ASSEMBLY__ */
-#endif /* __ASM_PPC_FSL_IFC_H */
+#endif /* __FSL_IFC_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-10-31 2:07 ` [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver York Sun
@ 2013-10-31 3:27 ` Prabhakar Kushwaha
2013-11-09 0:44 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Prabhakar Kushwaha @ 2013-10-31 3:27 UTC (permalink / raw)
To: u-boot
On 10/31/2013 7:37 AM, York Sun wrote:
> Freescale IFC controller has been used for mpc8xxx. It will be used
> for ARM-based SoC as well. This patch moves the driver to driver/mtd
> and fix the header file includes.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
>
Thanks York for this patch. This was pending from long time.
This patch moves fsl_ifc.c from powerpc to driver/mtd
I am not sure having 2 files for IFC controller in driver/mtd/ is
correct. Although fsl_ifc.c is for IFC Controller(NOR, NAND machine) and
fsl_ifc_nand.c is only for IFC - NAND machine.
I am asking this question as same changes will be applicable in Linux also.
Also,
We have to move changes of arch/powerpc/cpu/mpc85xx/speed.c to fsl_ifc.c
. This will make a IFC driver generic.
As this patch has impact on all IFC platforms, has this been tested on
few platforms?
Thanks,
Prabhakar
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-10-31 3:27 ` Prabhakar Kushwaha
@ 2013-11-09 0:44 ` Scott Wood
2013-11-09 0:52 ` Prabhakar Kushwaha
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-09 0:44 UTC (permalink / raw)
To: u-boot
On Thu, 2013-10-31 at 08:57 +0530, Prabhakar Kushwaha wrote:
> On 10/31/2013 7:37 AM, York Sun wrote:
> > Freescale IFC controller has been used for mpc8xxx. It will be used
> > for ARM-based SoC as well. This patch moves the driver to driver/mtd
> > and fix the header file includes.
> >
> > Signed-off-by: York Sun <yorksun@freescale.com>
> >
> Thanks York for this patch. This was pending from long time.
>
> This patch moves fsl_ifc.c from powerpc to driver/mtd
> I am not sure having 2 files for IFC controller in driver/mtd/ is
> correct. Although fsl_ifc.c is for IFC Controller(NOR, NAND machine) and
> fsl_ifc_nand.c is only for IFC - NAND machine.
> I am asking this question as same changes will be applicable in Linux also.
>
> Also,
> We have to move changes of arch/powerpc/cpu/mpc85xx/speed.c to fsl_ifc.c
> . This will make a IFC driver generic.
>
> As this patch has impact on all IFC platforms, has this been tested on
> few platforms?
I'm not sure that drivers/mtd is the right place for it as it doesn't
expose an mtd interface.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-10-31 2:07 ` [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver York Sun
@ 2013-11-09 0:48 ` Scott Wood
2013-11-09 2:25 ` york sun
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-09 0:48 UTC (permalink / raw)
To: u-boot
On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
> Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
> The similar DDR controllers will be used for ARM-based SoCs.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> Makefile | 4 +-
> README | 39 ++++++++++++++--
> arch/powerpc/cpu/mpc83xx/Makefile | 8 +---
> arch/powerpc/cpu/mpc85xx/Makefile | 42 -----------------
> arch/powerpc/cpu/mpc85xx/cpu.c | 16 +++----
> arch/powerpc/cpu/mpc85xx/mp.c | 2 +-
> arch/powerpc/cpu/mpc86xx/Makefile | 3 --
> arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 45 ------------------
> arch/powerpc/include/asm/config.h | 6 +++
> arch/powerpc/include/asm/config_mpc85xx.h | 13 ++++++
> arch/powerpc/include/asm/config_mpc86xx.h | 2 +
> arch/powerpc/include/asm/immap_83xx.h | 2 +-
> arch/powerpc/include/asm/immap_85xx.h | 6 +--
> arch/powerpc/include/asm/immap_86xx.h | 4 +-
> board/exmeritus/hww1u1a/ddr.c | 4 +-
> board/exmeritus/hww1u1a/hww1u1a.c | 4 +-
> board/freescale/b4860qds/ddr.c | 6 +--
> board/freescale/bsc9131rdb/ddr.c | 4 +-
> board/freescale/bsc9131rdb/spl_minimal.c | 4 +-
> board/freescale/bsc9132qds/bsc9132qds.c | 4 +-
> board/freescale/bsc9132qds/ddr.c | 4 +-
> board/freescale/bsc9132qds/spl_minimal.c | 4 +-
> board/freescale/c29xpcie/ddr.c | 4 +-
> board/freescale/corenet_ds/ddr.c | 4 +-
> board/freescale/corenet_ds/eth_p4080.c | 2 +-
> board/freescale/corenet_ds/p3041ds_ddr.c | 2 +-
> board/freescale/corenet_ds/p4080ds_ddr.c | 2 +-
> board/freescale/corenet_ds/p5020ds_ddr.c | 2 +-
> board/freescale/corenet_ds/p5040ds_ddr.c | 2 +-
> board/freescale/mpc8349emds/ddr.c | 4 +-
> board/freescale/mpc8349emds/mpc8349emds.c | 2 +-
> board/freescale/mpc8536ds/ddr.c | 4 +-
> board/freescale/mpc8536ds/mpc8536ds.c | 2 +-
> board/freescale/mpc8540ads/ddr.c | 4 +-
> board/freescale/mpc8540ads/mpc8540ads.c | 4 +-
> board/freescale/mpc8541cds/ddr.c | 4 +-
> board/freescale/mpc8541cds/mpc8541cds.c | 2 +-
> board/freescale/mpc8544ds/ddr.c | 4 +-
> board/freescale/mpc8544ds/mpc8544ds.c | 2 +-
> board/freescale/mpc8548cds/ddr.c | 4 +-
> board/freescale/mpc8548cds/mpc8548cds.c | 2 +-
> board/freescale/mpc8555cds/ddr.c | 4 +-
> board/freescale/mpc8555cds/mpc8555cds.c | 2 +-
> board/freescale/mpc8560ads/ddr.c | 4 +-
> board/freescale/mpc8560ads/mpc8560ads.c | 4 +-
> board/freescale/mpc8568mds/ddr.c | 4 +-
> board/freescale/mpc8568mds/mpc8568mds.c | 2 +-
> board/freescale/mpc8569mds/ddr.c | 4 +-
> board/freescale/mpc8569mds/mpc8569mds.c | 4 +-
> board/freescale/mpc8572ds/ddr.c | 4 +-
> board/freescale/mpc8572ds/mpc8572ds.c | 2 +-
> board/freescale/mpc8610hpcd/ddr.c | 4 +-
> board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +-
> board/freescale/mpc8641hpcn/ddr.c | 4 +-
> board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +-
> board/freescale/p1010rdb/ddr.c | 4 +-
> board/freescale/p1010rdb/spl_minimal.c | 4 +-
> board/freescale/p1022ds/ddr.c | 4 +-
> board/freescale/p1022ds/p1022ds.c | 2 +-
> board/freescale/p1022ds/spl_minimal.c | 2 +-
> board/freescale/p1023rdb/ddr.c | 4 +-
> board/freescale/p1023rdb/p1023rdb.c | 2 +-
> board/freescale/p1023rds/p1023rds.c | 4 +-
> board/freescale/p1_p2_rdb/ddr.c | 2 +-
> board/freescale/p1_p2_rdb_pc/ddr.c | 4 +-
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
> board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +-
> board/freescale/p1_twr/ddr.c | 4 +-
> board/freescale/p1_twr/p1_twr.c | 2 +-
> board/freescale/p2020come/ddr.c | 4 +-
> board/freescale/p2020ds/ddr.c | 4 +-
> board/freescale/p2020ds/p2020ds.c | 4 +-
> board/freescale/p2041rdb/ddr.c | 4 +-
> board/freescale/t1040qds/ddr.c | 4 +-
> board/freescale/t4qds/ddr.c | 4 +-
> board/freescale/t4qds/eth.c | 2 +-
> board/gdsys/p1022/controlcenterd.c | 2 +-
> board/gdsys/p1022/ddr.c | 4 +-
> board/keymile/kmp204x/ddr.c | 4 +-
> board/sbc8548/ddr.c | 6 +--
> board/sbc8548/sbc8548.c | 2 +-
> board/sbc8641d/ddr.c | 4 +-
> board/sbc8641d/sbc8641d.c | 2 +-
> board/socrates/ddr.c | 4 +-
> board/socrates/sdram.c | 4 +-
> board/stx/stxgp3/ddr.c | 4 +-
> board/stx/stxgp3/stxgp3.c | 2 +-
> board/stx/stxssa/ddr.c | 4 +-
> board/stx/stxssa/stxssa.c | 2 +-
> board/xes/xpedite517x/ddr.c | 4 +-
> board/xes/xpedite517x/xpedite517x.c | 2 +-
> board/xes/xpedite520x/ddr.c | 4 +-
> board/xes/xpedite537x/ddr.c | 4 +-
> board/xes/xpedite550x/ddr.c | 4 +-
> drivers/ddr/fsl/Makefile | 49 ++++++++++++++++++++
> .../mpc8xxx/ddr => drivers/ddr/fsl}/ctrl_regs.c | 8 ++--
> .../ddr => drivers/ddr/fsl}/ddr1_dimm_params.c | 4 +-
> .../ddr => drivers/ddr/fsl}/ddr2_dimm_params.c | 4 +-
> .../ddr => drivers/ddr/fsl}/ddr3_dimm_params.c | 4 +-
> .../mpc8xxx/ddr => drivers/ddr/fsl}/interactive.c | 5 +-
> .../ddr/fsl}/lc_common_dimm_params.c | 4 +-
> .../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/main.c | 4 +-
> .../ddr/fsl/mpc85xx_ddr_gen1.c | 6 +--
> .../ddr/fsl/mpc85xx_ddr_gen2.c | 4 +-
> .../ddr/fsl/mpc85xx_ddr_gen3.c | 16 +++----
> .../ddr-8641.c => drivers/ddr/fsl/mpc86xx_ddr.c | 6 +--
> .../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/options.c | 4 +-
> .../cpu/mpc8xxx/ddr => drivers/ddr/fsl}/util.c | 10 ++--
> .../mpc8xxx/ddr => include}/common_timing_params.h | 0
> .../cpu/mpc8xxx/ddr/ddr.h => include/fsl_ddr.h | 6 +--
> .../include/asm => include}/fsl_ddr_dimm_params.h | 0
> .../include/asm => include}/fsl_ddr_sdram.h | 0
> nand_spl/board/freescale/mpc8569mds/nand_boot.c | 2 +-
> nand_spl/board/freescale/p1023rds/nand_boot.c | 4 +-
> nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 2 +-
> spl/Makefile | 2 +-
> 116 files changed, 304 insertions(+), 298 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/Makefile
> create mode 100644 drivers/ddr/fsl/Makefile
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ctrl_regs.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr1_dimm_params.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr2_dimm_params.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/ddr3_dimm_params.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/interactive.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/lc_common_dimm_params.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/main.c (99%)
> rename arch/powerpc/cpu/mpc85xx/ddr-gen1.c => drivers/ddr/fsl/mpc85xx_ddr_gen1.c (93%)
> rename arch/powerpc/cpu/mpc85xx/ddr-gen2.c => drivers/ddr/fsl/mpc85xx_ddr_gen2.c (96%)
> rename arch/powerpc/cpu/mpc85xx/ddr-gen3.c => drivers/ddr/fsl/mpc85xx_ddr_gen3.c (97%)
> rename arch/powerpc/cpu/mpc86xx/ddr-8641.c => drivers/ddr/fsl/mpc86xx_ddr.c (95%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/options.c (99%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => drivers/ddr/fsl}/util.c (96%)
> rename {arch/powerpc/cpu/mpc8xxx/ddr => include}/common_timing_params.h (100%)
> rename arch/powerpc/cpu/mpc8xxx/ddr/ddr.h => include/fsl_ddr.h (97%)
> rename {arch/powerpc/include/asm => include}/fsl_ddr_dimm_params.h (100%)
> rename {arch/powerpc/include/asm => include}/fsl_ddr_sdram.h (100%)
>
> diff --git a/Makefile b/Makefile
> index 2d18d27..4dd2e2e 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -291,19 +291,17 @@ LIBS-y += drivers/spi/libspi.o
> LIBS-y += drivers/dfu/libdfu.o
> ifeq ($(CPU),mpc83xx)
> LIBS-y += drivers/qe/libqe.o
> -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
> LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
> endif
> ifeq ($(CPU),mpc85xx)
> LIBS-y += drivers/qe/libqe.o
> LIBS-y += drivers/net/fm/libfm.o
> -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
> LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
> endif
> ifeq ($(CPU),mpc86xx)
> -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
> LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
> endif
> +LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/libddr.o
> LIBS-y += drivers/rtc/librtc.o
> LIBS-y += drivers/serial/libserial.o
> LIBS-y += drivers/sound/libsound.o
> diff --git a/README b/README
> index 91c3ac0..fc5107f 100644
> --- a/README
> +++ b/README
> @@ -423,16 +423,45 @@ The following options need to be configured:
> CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
> This value denotes start offset of DSP CCSR space.
>
> - CONFIG_SYS_FSL_DDR_EMU
> - Specify emulator support for DDR. Some DDR features such as
> - deskew training are not available.
> -
> - Generic CPU options:
> CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
>
> Defines the endianess of the CPU. Implementation of those
> values is arch specific.
>
> + CONFIG_SYS_FSL_DDR
> + Freescale DDR driver in use. This type of DDR controller is
> + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
> + SoCs.
> +
> + CONFIG_SYS_FSL_DDR_ADDR
> + Freescale DDR memory-mapped register base.
> +
> + CONFIG_SYS_FSL_DDR_EMU
> + Specify emulator support for DDR. Some DDR features such as
> + deskew training are not available.
> +
> + CONFIG_SYS_FSL_DDR_PPC_GEN1
> + Freescale DDR1 controller.
> +
> + CONFIG_SYS_FSL_DDR_PPC_GEN2
> + Freescale DDR2 controller.
> +
> + CONFIG_SYS_FSL_DDR_PPC_GEN3
> + Freescale DDR3 controller.
Why is there "PPC" in the name if this is to be common for PPC and ARM?
The description is more generic than the config symbol...
> + CONFIG_FSL_DDR1
> + User config to use DDR1. It can be enabled for SoCs with
> + Freescale DDR1 or DDR2 controllers.
> +
> + CONFIG_FSL_DDR2
> + User config to use DDR2. It can be eanbeld for SoCs with
> + Freescale DDR2 or DDR3 controllers.
> +
> + CONFIG_FSL_DDR3
> + User config to use DDR3. It can be enabled for SoCs with
> + Freescale DDR3 controllers.
How is this user config, rather than a description of the type of DDR
that is present?
> diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
> index 694b110..4f9b225 100644
> --- a/arch/powerpc/include/asm/config_mpc86xx.h
> +++ b/arch/powerpc/include/asm/config_mpc86xx.h
> @@ -7,6 +7,8 @@
> #ifndef _ASM_MPC86xx_CONFIG_H_
> #define _ASM_MPC86xx_CONFIG_H_
>
> +#define CONFIG_SYS_FSL_DDR_86XX
This doesn't qualify as one of the "PPC_GEN" controllers?
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM
2013-10-31 2:07 ` [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM York Sun
@ 2013-11-09 0:51 ` Scott Wood
2013-11-09 2:29 ` york sun
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-09 0:51 UTC (permalink / raw)
To: u-boot
On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
> Make PowerPC specific code conditional so ARM SoCs can reuse
> this driver. Add DDR3 driver for ARM.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> drivers/ddr/fsl/Makefile | 1 +
> drivers/ddr/fsl/arm_ddr_gen3.c | 213 ++++++++++++++++++++++++++++++++++++++++
> drivers/ddr/fsl/main.c | 12 ++-
> drivers/ddr/fsl/util.c | 4 +
> 4 files changed, 227 insertions(+), 3 deletions(-)
> create mode 100644 drivers/ddr/fsl/arm_ddr_gen3.c
>
> diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
> index cbbd178..381ec6c 100644
> --- a/drivers/ddr/fsl/Makefile
> +++ b/drivers/ddr/fsl/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN1) += mpc85xx_ddr_gen1.o
> COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN2) += mpc85xx_ddr_gen2.o
> COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN3) += mpc85xx_ddr_gen3.o
> COBJS-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
> +COBJS-$(CONFIG_SYS_FSL_DDR_ARM_GEN3) += arm_ddr_gen3.o
> COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
I'm confused -- is this hardware the same across CPU families or not?
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-11-09 0:44 ` Scott Wood
@ 2013-11-09 0:52 ` Prabhakar Kushwaha
2013-11-09 1:00 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Prabhakar Kushwaha @ 2013-11-09 0:52 UTC (permalink / raw)
To: u-boot
On 11/9/2013 6:14 AM, Scott Wood wrote:
> On Thu, 2013-10-31 at 08:57 +0530, Prabhakar Kushwaha wrote:
>> On 10/31/2013 7:37 AM, York Sun wrote:
>>> Freescale IFC controller has been used for mpc8xxx. It will be used
>>> for ARM-based SoC as well. This patch moves the driver to driver/mtd
>>> and fix the header file includes.
>>>
>>> Signed-off-by: York Sun <yorksun@freescale.com>
>>>
>> Thanks York for this patch. This was pending from long time.
>>
>> This patch moves fsl_ifc.c from powerpc to driver/mtd
>> I am not sure having 2 files for IFC controller in driver/mtd/ is
>> correct. Although fsl_ifc.c is for IFC Controller(NOR, NAND machine) and
>> fsl_ifc_nand.c is only for IFC - NAND machine.
>> I am asking this question as same changes will be applicable in Linux also.
>>
>> Also,
>> We have to move changes of arch/powerpc/cpu/mpc85xx/speed.c to fsl_ifc.c
>> . This will make a IFC driver generic.
>>
>> As this patch has impact on all IFC platforms, has this been tested on
>> few platforms?
> I'm not sure that drivers/mtd is the right place for it as it doesn't
> expose an mtd interface.
>
>
Yes Scott, I am also agree with you. But we are not sure about the right
place for it.
one suggestion, may we merge fsl_ifc in fsl_ifc_nand.c & fsl_ifc_spl.c?
Please advice
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-11-09 0:52 ` Prabhakar Kushwaha
@ 2013-11-09 1:00 ` Scott Wood
2013-11-11 11:13 ` Prabhakar Kushwaha
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-09 1:00 UTC (permalink / raw)
To: u-boot
On Sat, 2013-11-09 at 06:22 +0530, Prabhakar Kushwaha wrote:
> On 11/9/2013 6:14 AM, Scott Wood wrote:
> > On Thu, 2013-10-31 at 08:57 +0530, Prabhakar Kushwaha wrote:
> >> On 10/31/2013 7:37 AM, York Sun wrote:
> >>> Freescale IFC controller has been used for mpc8xxx. It will be used
> >>> for ARM-based SoC as well. This patch moves the driver to driver/mtd
> >>> and fix the header file includes.
> >>>
> >>> Signed-off-by: York Sun <yorksun@freescale.com>
> >>>
> >> Thanks York for this patch. This was pending from long time.
> >>
> >> This patch moves fsl_ifc.c from powerpc to driver/mtd
> >> I am not sure having 2 files for IFC controller in driver/mtd/ is
> >> correct. Although fsl_ifc.c is for IFC Controller(NOR, NAND machine) and
> >> fsl_ifc_nand.c is only for IFC - NAND machine.
> >> I am asking this question as same changes will be applicable in Linux also.
> >>
> >> Also,
> >> We have to move changes of arch/powerpc/cpu/mpc85xx/speed.c to fsl_ifc.c
> >> . This will make a IFC driver generic.
> >>
> >> As this patch has impact on all IFC platforms, has this been tested on
> >> few platforms?
> > I'm not sure that drivers/mtd is the right place for it as it doesn't
> > expose an mtd interface.
> >
> >
>
> Yes Scott, I am also agree with you. But we are not sure about the right
> place for it.
This is similar to the question of where to put CPM/QE code. A place
will need to be identified for glue code that doesn't fit cleanly into
an existing subsystem. drivers/misc is probably the right place, though
IIRC on the Linux side the drivers/misc maintainer was generally opposed
to its existence and pushed back on new things being added to it.
> one suggestion, may we merge fsl_ifc in fsl_ifc_nand.c & fsl_ifc_spl.c?
No.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-09 0:48 ` Scott Wood
@ 2013-11-09 2:25 ` york sun
2013-11-11 18:49 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: york sun @ 2013-11-09 2:25 UTC (permalink / raw)
To: u-boot
On Nov 8, 2013, at 4:48 PM, Scott Wood wrote:
> On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
>>
>> + CONFIG_SYS_FSL_DDR
>> + Freescale DDR driver in use. This type of DDR controller is
>> + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
>> + SoCs.
>> +
>> + CONFIG_SYS_FSL_DDR_ADDR
>> + Freescale DDR memory-mapped register base.
>> +
>> + CONFIG_SYS_FSL_DDR_EMU
>> + Specify emulator support for DDR. Some DDR features such as
>> + deskew training are not available.
>> +
>> + CONFIG_SYS_FSL_DDR_PPC_GEN1
>> + Freescale DDR1 controller.
>> +
>> + CONFIG_SYS_FSL_DDR_PPC_GEN2
>> + Freescale DDR2 controller.
>> +
>> + CONFIG_SYS_FSL_DDR_PPC_GEN3
>> + Freescale DDR3 controller.
>
> Why is there "PPC" in the name if this is to be common for PPC and ARM?
> The description is more generic than the config symbol...
This patch moves the DDR driver out of powerpc. I should deal with the common part for ARM and PPC later. Good point.
>
>> + CONFIG_FSL_DDR1
>> + User config to use DDR1. It can be enabled for SoCs with
>> + Freescale DDR1 or DDR2 controllers.
>> +
>> + CONFIG_FSL_DDR2
>> + User config to use DDR2. It can be eanbeld for SoCs with
>> + Freescale DDR2 or DDR3 controllers.
>> +
>> + CONFIG_FSL_DDR3
>> + User config to use DDR3. It can be enabled for SoCs with
>> + Freescale DDR3 controllers.
>
> How is this user config, rather than a description of the type of DDR
> that is present?
The DDR controller may support more than one type of memory. DDR2 controllers support both DDR1 and DDR2, and some DDR3 controllers support both DDR2 and DDR3. It's user's option to choose which type of DDR devices to use. The driver needs to deal with them differently. You may argue the driver should detect them and choose the algorithm differently. But that will increase the code size considerably. It makes less sense to do so because once the board is designed, it is either this or that.
>
>> diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
>> index 694b110..4f9b225 100644
>> --- a/arch/powerpc/include/asm/config_mpc86xx.h
>> +++ b/arch/powerpc/include/asm/config_mpc86xx.h
>> @@ -7,6 +7,8 @@
>> #ifndef _ASM_MPC86xx_CONFIG_H_
>> #define _ASM_MPC86xx_CONFIG_H_
>>
>> +#define CONFIG_SYS_FSL_DDR_86XX
>
> This doesn't qualify as one of the "PPC_GEN" controllers?
>
The common part is shared for all controllers. The final writing register function is different. I didn't try to merge 86xx with 85xx, because 85xx is messy, with a lot of workaround. And most importantly, 86xx driver stay with DDR2 while 85xx driver mainly supports DDR3.
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM
2013-11-09 0:51 ` Scott Wood
@ 2013-11-09 2:29 ` york sun
0 siblings, 0 replies; 23+ messages in thread
From: york sun @ 2013-11-09 2:29 UTC (permalink / raw)
To: u-boot
On Nov 8, 2013, at 4:51 PM, Scott Wood wrote:
> On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
>> Make PowerPC specific code conditional so ARM SoCs can reuse
>> this driver. Add DDR3 driver for ARM.
>>
>> Signed-off-by: York Sun <yorksun@freescale.com>
>> ---
>> drivers/ddr/fsl/Makefile | 1 +
>> drivers/ddr/fsl/arm_ddr_gen3.c | 213 ++++++++++++++++++++++++++++++++++++++++
>> drivers/ddr/fsl/main.c | 12 ++-
>> drivers/ddr/fsl/util.c | 4 +
>> 4 files changed, 227 insertions(+), 3 deletions(-)
>> create mode 100644 drivers/ddr/fsl/arm_ddr_gen3.c
>>
>> diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
>> index cbbd178..381ec6c 100644
>> --- a/drivers/ddr/fsl/Makefile
>> +++ b/drivers/ddr/fsl/Makefile
>> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN1) += mpc85xx_ddr_gen1.o
>> COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN2) += mpc85xx_ddr_gen2.o
>> COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN3) += mpc85xx_ddr_gen3.o
>> COBJS-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
>> +COBJS-$(CONFIG_SYS_FSL_DDR_ARM_GEN3) += arm_ddr_gen3.o
>> COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
>
> I'm confused -- is this hardware the same across CPU families or not?
The algorithm is the same for all DDR controllers. The final part of writing to registers is slightly different. For example, 85xx SoCs have LAWs, ARM parts don't. 85xx driver needs to deal with both DDR2 and DDR3, while ARM driver doesn't. I also don't want to carry some messy workarounds from 85xx to ARM driver. It's much cleaner to keep them separated. The final part is very small in size.
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver
2013-11-09 1:00 ` Scott Wood
@ 2013-11-11 11:13 ` Prabhakar Kushwaha
0 siblings, 0 replies; 23+ messages in thread
From: Prabhakar Kushwaha @ 2013-11-11 11:13 UTC (permalink / raw)
To: u-boot
On 11/9/2013 6:30 AM, Scott Wood wrote:
> On Sat, 2013-11-09 at 06:22 +0530, Prabhakar Kushwaha wrote:
>> On 11/9/2013 6:14 AM, Scott Wood wrote:
>>> On Thu, 2013-10-31 at 08:57 +0530, Prabhakar Kushwaha wrote:
>>>> On 10/31/2013 7:37 AM, York Sun wrote:
>>>>> Freescale IFC controller has been used for mpc8xxx. It will be used
>>>>> for ARM-based SoC as well. This patch moves the driver to driver/mtd
>>>>> and fix the header file includes.
>>>>>
>>>>> Signed-off-by: York Sun <yorksun@freescale.com>
>>>>>
>>>> Thanks York for this patch. This was pending from long time.
>>>>
>>>> This patch moves fsl_ifc.c from powerpc to driver/mtd
>>>> I am not sure having 2 files for IFC controller in driver/mtd/ is
>>>> correct. Although fsl_ifc.c is for IFC Controller(NOR, NAND machine) and
>>>> fsl_ifc_nand.c is only for IFC - NAND machine.
>>>> I am asking this question as same changes will be applicable in Linux also.
>>>>
>>>> Also,
>>>> We have to move changes of arch/powerpc/cpu/mpc85xx/speed.c to fsl_ifc.c
>>>> . This will make a IFC driver generic.
>>>>
>>>> As this patch has impact on all IFC platforms, has this been tested on
>>>> few platforms?
>>> I'm not sure that drivers/mtd is the right place for it as it doesn't
>>> expose an mtd interface.
>>>
>>>
>> Yes Scott, I am also agree with you. But we are not sure about the right
>> place for it.
> This is similar to the question of where to put CPM/QE code. A place
> will need to be identified for glue code that doesn't fit cleanly into
> an existing subsystem. drivers/misc is probably the right place, though
> IIRC on the Linux side the drivers/misc maintainer was generally opposed
> to its existence and pushed back on new things being added to it.
looks like putting fsl_ifc.c in driver/mtd is not good way of handle it.
I should sent on RFC of putting this in driver/misc for Linux and see
the response. May be I get a better solution there.
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-09 2:25 ` york sun
@ 2013-11-11 18:49 ` Scott Wood
2013-11-11 19:05 ` York Sun
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-11 18:49 UTC (permalink / raw)
To: u-boot
On Fri, 2013-11-08 at 20:25 -0600, sun york-R58495 wrote:
> On Nov 8, 2013, at 4:48 PM, Scott Wood wrote:
>
> > On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
> >>
> >> + CONFIG_SYS_FSL_DDR
> >> + Freescale DDR driver in use. This type of DDR controller is
> >> + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
> >> + SoCs.
> >> +
> >> + CONFIG_SYS_FSL_DDR_ADDR
> >> + Freescale DDR memory-mapped register base.
> >> +
> >> + CONFIG_SYS_FSL_DDR_EMU
> >> + Specify emulator support for DDR. Some DDR features such as
> >> + deskew training are not available.
> >> +
> >> + CONFIG_SYS_FSL_DDR_PPC_GEN1
> >> + Freescale DDR1 controller.
> >> +
> >> + CONFIG_SYS_FSL_DDR_PPC_GEN2
> >> + Freescale DDR2 controller.
> >> +
> >> + CONFIG_SYS_FSL_DDR_PPC_GEN3
> >> + Freescale DDR3 controller.
> >
> > Why is there "PPC" in the name if this is to be common for PPC and ARM?
> > The description is more generic than the config symbol...
>
> This patch moves the DDR driver out of powerpc. I should deal with the common part for ARM and PPC later. Good point.
>
> >
> >> + CONFIG_FSL_DDR1
> >> + User config to use DDR1. It can be enabled for SoCs with
> >> + Freescale DDR1 or DDR2 controllers.
> >> +
> >> + CONFIG_FSL_DDR2
> >> + User config to use DDR2. It can be eanbeld for SoCs with
> >> + Freescale DDR2 or DDR3 controllers.
> >> +
> >> + CONFIG_FSL_DDR3
> >> + User config to use DDR3. It can be enabled for SoCs with
> >> + Freescale DDR3 controllers.
> >
> > How is this user config, rather than a description of the type of DDR
> > that is present?
>
> The DDR controller may support more than one type of memory. DDR2
> controllers support both DDR1 and DDR2, and some DDR3 controllers
> support both DDR2 and DDR3. It's user's option to choose which type of
> DDR devices to use. The driver needs to deal with them differently. You
> may argue the driver should detect them and choose the algorithm
> differently. But that will increase the code size considerably. It
> makes less sense to do so because once the board is designed, it is
> either this or that.
My point is that the type of DDR that is present is hardware
description, just as much as the type of DDR controller. "User config"
means things users can choose purely in software, without a
corresponding hardware change.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 18:49 ` Scott Wood
@ 2013-11-11 19:05 ` York Sun
2013-11-11 19:35 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-11-11 19:05 UTC (permalink / raw)
To: u-boot
On 11/11/2013 10:49 AM, Scott Wood wrote:
> On Fri, 2013-11-08 at 20:25 -0600, sun york-R58495 wrote:
>> On Nov 8, 2013, at 4:48 PM, Scott Wood wrote:
>>
>>> On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
>>>>
>>>> + CONFIG_SYS_FSL_DDR
>>>> + Freescale DDR driver in use. This type of DDR controller is
>>>> + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
>>>> + SoCs.
>>>> +
>>>> + CONFIG_SYS_FSL_DDR_ADDR
>>>> + Freescale DDR memory-mapped register base.
>>>> +
>>>> + CONFIG_SYS_FSL_DDR_EMU
>>>> + Specify emulator support for DDR. Some DDR features such as
>>>> + deskew training are not available.
>>>> +
>>>> + CONFIG_SYS_FSL_DDR_PPC_GEN1
>>>> + Freescale DDR1 controller.
>>>> +
>>>> + CONFIG_SYS_FSL_DDR_PPC_GEN2
>>>> + Freescale DDR2 controller.
>>>> +
>>>> + CONFIG_SYS_FSL_DDR_PPC_GEN3
>>>> + Freescale DDR3 controller.
>>>
>>> Why is there "PPC" in the name if this is to be common for PPC and ARM?
>>> The description is more generic than the config symbol...
>>
>> This patch moves the DDR driver out of powerpc. I should deal with the common part for ARM and PPC later. Good point.
>>
>>>
>>>> + CONFIG_FSL_DDR1
>>>> + User config to use DDR1. It can be enabled for SoCs with
>>>> + Freescale DDR1 or DDR2 controllers.
>>>> +
>>>> + CONFIG_FSL_DDR2
>>>> + User config to use DDR2. It can be eanbeld for SoCs with
>>>> + Freescale DDR2 or DDR3 controllers.
>>>> +
>>>> + CONFIG_FSL_DDR3
>>>> + User config to use DDR3. It can be enabled for SoCs with
>>>> + Freescale DDR3 controllers.
>>>
>>> How is this user config, rather than a description of the type of DDR
>>> that is present?
>>
>> The DDR controller may support more than one type of memory. DDR2
>> controllers support both DDR1 and DDR2, and some DDR3 controllers
>> support both DDR2 and DDR3. It's user's option to choose which type of
>> DDR devices to use. The driver needs to deal with them differently. You
>> may argue the driver should detect them and choose the algorithm
>> differently. But that will increase the code size considerably. It
>> makes less sense to do so because once the board is designed, it is
>> either this or that.
>
> My point is that the type of DDR that is present is hardware
> description, just as much as the type of DDR controller. "User config"
> means things users can choose purely in software, without a
> corresponding hardware change.
>
This is a board-level configuration, not SoC level. Should we use
CONFIG_SYS_ as well? If so, we need to come up with a new name, such as
CONFIG_SYS_FSL_DDR_MEM_GEN3.
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 19:05 ` York Sun
@ 2013-11-11 19:35 ` Scott Wood
2013-11-11 19:37 ` York Sun
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-11 19:35 UTC (permalink / raw)
To: u-boot
On Mon, 2013-11-11 at 11:05 -0800, York Sun wrote:
> On 11/11/2013 10:49 AM, Scott Wood wrote:
> > My point is that the type of DDR that is present is hardware
> > description, just as much as the type of DDR controller. "User config"
> > means things users can choose purely in software, without a
> > corresponding hardware change.
> >
>
> This is a board-level configuration, not SoC level. Should we use
> CONFIG_SYS_ as well?
Yes.
> If so, we need to come up with a new name, such as CONFIG_SYS_FSL_DDR_MEM_GEN3.
How about CONFIG_SYS_FSL_DDR3 for the memory, and
CONFIG_SYS_FSL_DDR_CTRL3 for the controller?
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 19:35 ` Scott Wood
@ 2013-11-11 19:37 ` York Sun
2013-11-11 19:59 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-11-11 19:37 UTC (permalink / raw)
To: u-boot
On 11/11/2013 11:35 AM, Scott Wood wrote:
> On Mon, 2013-11-11 at 11:05 -0800, York Sun wrote:
>> On 11/11/2013 10:49 AM, Scott Wood wrote:
>>> My point is that the type of DDR that is present is hardware
>>> description, just as much as the type of DDR controller. "User config"
>>> means things users can choose purely in software, without a
>>> corresponding hardware change.
>>>
>>
>> This is a board-level configuration, not SoC level. Should we use
>> CONFIG_SYS_ as well?
>
> Yes.
>
>> If so, we need to come up with a new name, such as CONFIG_SYS_FSL_DDR_MEM_GEN3.
>
> How about CONFIG_SYS_FSL_DDR3 for the memory, and
> CONFIG_SYS_FSL_DDR_CTRL3 for the controller?
>
I am reluctant to change existing macro to different meaning. How about
CONFIG_SYS_FSL_DDR3_MEM, or CONFIG_SYS_FSL_MEM_DDR3?
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 19:37 ` York Sun
@ 2013-11-11 19:59 ` Scott Wood
2013-11-11 20:15 ` York Sun
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2013-11-11 19:59 UTC (permalink / raw)
To: u-boot
On Mon, 2013-11-11 at 11:37 -0800, York Sun wrote:
> On 11/11/2013 11:35 AM, Scott Wood wrote:
> > On Mon, 2013-11-11 at 11:05 -0800, York Sun wrote:
> >> On 11/11/2013 10:49 AM, Scott Wood wrote:
> >>> My point is that the type of DDR that is present is hardware
> >>> description, just as much as the type of DDR controller. "User config"
> >>> means things users can choose purely in software, without a
> >>> corresponding hardware change.
> >>>
> >>
> >> This is a board-level configuration, not SoC level. Should we use
> >> CONFIG_SYS_ as well?
> >
> > Yes.
> >
> >> If so, we need to come up with a new name, such as CONFIG_SYS_FSL_DDR_MEM_GEN3.
> >
> > How about CONFIG_SYS_FSL_DDR3 for the memory, and
> > CONFIG_SYS_FSL_DDR_CTRL3 for the controller?
> >
>
> I am reluctant to change existing macro to different meaning. How about
> CONFIG_SYS_FSL_DDR3_MEM, or CONFIG_SYS_FSL_MEM_DDR3?
CONFIG_SYS_FSL_DDR3 is not an existing macro.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 19:59 ` Scott Wood
@ 2013-11-11 20:15 ` York Sun
2013-11-11 20:25 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: York Sun @ 2013-11-11 20:15 UTC (permalink / raw)
To: u-boot
On 11/11/2013 11:59 AM, Scott Wood wrote:
> On Mon, 2013-11-11 at 11:37 -0800, York Sun wrote:
>> On 11/11/2013 11:35 AM, Scott Wood wrote:
>>> On Mon, 2013-11-11 at 11:05 -0800, York Sun wrote:
>>>> On 11/11/2013 10:49 AM, Scott Wood wrote:
>>>>> My point is that the type of DDR that is present is hardware
>>>>> description, just as much as the type of DDR controller. "User config"
>>>>> means things users can choose purely in software, without a
>>>>> corresponding hardware change.
>>>>>
>>>>
>>>> This is a board-level configuration, not SoC level. Should we use
>>>> CONFIG_SYS_ as well?
>>>
>>> Yes.
>>>
>>>> If so, we need to come up with a new name, such as CONFIG_SYS_FSL_DDR_MEM_GEN3.
>>>
>>> How about CONFIG_SYS_FSL_DDR3 for the memory, and
>>> CONFIG_SYS_FSL_DDR_CTRL3 for the controller?
>>>
>>
>> I am reluctant to change existing macro to different meaning. How about
>> CONFIG_SYS_FSL_DDR3_MEM, or CONFIG_SYS_FSL_MEM_DDR3?
>
> CONFIG_SYS_FSL_DDR3 is not an existing macro.
>
Oh. My mistake. We can use CONFIG_SYS_FSL_DDR3 for the memory. But I
prefer to keep CONFIG_SYS_FSL_DDR_PPC_GEN3 or use
CONFIG_SYS_FSL_DDRC_GEN3 if it can be merged with ARM controller. CTRL3
is misleading. It makes me thinking of controller #3.
York
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver
2013-11-11 20:15 ` York Sun
@ 2013-11-11 20:25 ` Scott Wood
0 siblings, 0 replies; 23+ messages in thread
From: Scott Wood @ 2013-11-11 20:25 UTC (permalink / raw)
To: u-boot
On Mon, 2013-11-11 at 12:15 -0800, York Sun wrote:
> On 11/11/2013 11:59 AM, Scott Wood wrote:
> > On Mon, 2013-11-11 at 11:37 -0800, York Sun wrote:
> >> On 11/11/2013 11:35 AM, Scott Wood wrote:
> >>> On Mon, 2013-11-11 at 11:05 -0800, York Sun wrote:
> >>>> On 11/11/2013 10:49 AM, Scott Wood wrote:
> >>>>> My point is that the type of DDR that is present is hardware
> >>>>> description, just as much as the type of DDR controller. "User config"
> >>>>> means things users can choose purely in software, without a
> >>>>> corresponding hardware change.
> >>>>>
> >>>>
> >>>> This is a board-level configuration, not SoC level. Should we use
> >>>> CONFIG_SYS_ as well?
> >>>
> >>> Yes.
> >>>
> >>>> If so, we need to come up with a new name, such as CONFIG_SYS_FSL_DDR_MEM_GEN3.
> >>>
> >>> How about CONFIG_SYS_FSL_DDR3 for the memory, and
> >>> CONFIG_SYS_FSL_DDR_CTRL3 for the controller?
> >>>
> >>
> >> I am reluctant to change existing macro to different meaning. How about
> >> CONFIG_SYS_FSL_DDR3_MEM, or CONFIG_SYS_FSL_MEM_DDR3?
> >
> > CONFIG_SYS_FSL_DDR3 is not an existing macro.
> >
>
> Oh. My mistake. We can use CONFIG_SYS_FSL_DDR3 for the memory. But I
> prefer to keep CONFIG_SYS_FSL_DDR_PPC_GEN3 or use
> CONFIG_SYS_FSL_DDRC_GEN3 if it can be merged with ARM controller. CTRL3
> is misleading. It makes me thinking of controller #3.
OK.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2013-11-11 20:25 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-10-31 2:07 [U-Boot] [Patch v1 0/6] Move Freescale DDR and IFC drivers to common drivers York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 1/6] Driver/DDR: Moving Freescale DDR driver to a common driver York Sun
2013-11-09 0:48 ` Scott Wood
2013-11-09 2:25 ` york sun
2013-11-11 18:49 ` Scott Wood
2013-11-11 19:05 ` York Sun
2013-11-11 19:35 ` Scott Wood
2013-11-11 19:37 ` York Sun
2013-11-11 19:59 ` Scott Wood
2013-11-11 20:15 ` York Sun
2013-11-11 20:25 ` Scott Wood
2013-10-31 2:07 ` [U-Boot] [Patch v1 2/6] Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 3/6] Driver/DDR: Add Freescale DDR driver for ARM York Sun
2013-11-09 0:51 ` Scott Wood
2013-11-09 2:29 ` york sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 4/6] powerpc/mpc8xxx: Extend DDR registers' fields York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 5/6] Driver/DDR: Update DDR driver to allow non-zero base address York Sun
2013-10-31 2:07 ` [U-Boot] [Patch v1 6/6] Driver/IFC: Move Freescale IFC driver to a common driver York Sun
2013-10-31 3:27 ` Prabhakar Kushwaha
2013-11-09 0:44 ` Scott Wood
2013-11-09 0:52 ` Prabhakar Kushwaha
2013-11-09 1:00 ` Scott Wood
2013-11-11 11:13 ` Prabhakar Kushwaha
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.