[PATCH 00/62] Broadwell kernel driver support

[PATCH 00/62] Broadwell kernel driver support

[Ben Widawsky]

It is my honor and privilege to submit basic Broadwell support on behalf
of Intel.

The patch series includes support for Broadwell which should bring it up
to feature parity with Haswell. As you'll note, the patches have
received some revisions and review already. This is due to our new
process (more on this below). We will be rolling out the new Broadwell
goodness over time.

Broadwell represents the next generation (GEN8) in Intel graphics
processing hardware. Broadwell graphics bring some of the biggest
changes we've seen on the execution and memory management side of the
GPU. (There are equally large and exciting changes for the userspace
drivers.)

My request to reviewers is: I haven't touched these much at all since
submitting to the internal mailing list. Most changes are due to rebase.
Try to keep bikesheds to a minimum. We want to try to get this code in
the 3.13 kernel, so we have a nice base to actually stabilize and
improve features for the 3.14 release. Remember, we have that handy
'preliminary hardware support' to allow people to opt-in to this early
enabling code. So I'm shooting for stable "end-userable" BDW code in
3.14.

Note that the last few workarounds likely won't be needed, but I think
we can include them until we know for sure otherwise.

Aside from the usual set of things we need to update when simply
enabling a new platform, What follows are some of the major changes from
HSW->BDW:

* There is no longer a forcewake write FIFO. *Most* writes must explicitly
wake the GPU.

* Interrupt registers have been completely reorganized.

* PTEs format and cachability settings have changed to more resemble x86
PTEs, and PAT
  * Address space increases, and as such many commands require changing

* Page table structures have changed for the Per Process GTT. The new
structure more resembles traditional page tables with registers defining
page directory base.

The latter two changes were the real challenge in enabling the platform
and getting things to actually work - though in hindsight, they seem so
trivial :-)

You may find these patches here:
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell

I'll be posting patches for libdrm, and intel-gpu-tools in the next day
or two.  They are also ready to go, I just need to do a quick once over.
At this point, feel free to stop reading.




I wanted to talk a bit about some of the changes on the development side
which are enabling us to get code out way before silicon ships. Again,
I'd like to point out that the amount of changes on BDW dwarfs any other
silicon iteration during my tenure, and certainly can compete with the
likes of the gen3->gen4 changes.

Broadwell development for the i915 driver began last November, 2012.
With the help of some awesome people we managed to enable a simulation
environment for Linux graphics development. While this was not the first
time the OTC teams had used simulation for development, it did mark the
first time we were using it to simulate and run the entire software
stack and model most of the HW. The previous use of simulation really
didn't provide anything useful for the kernel driver, and faked enough
of the relevant user space interactions to cause some worry.

Another new process was the invention and usage of an internal mailing
list, where we could talk about, and review code that we did not yet
have permission to open source.

Sometime around mid December, we had code which could run glxgears. The
magic is really what happened after. For the last 10 months (give or
take), Daniel Vetter has been maintaining our internal repository for
development. Providing continuous rebases on the very fast based
upstream tree (and less rapid internal development). In addition, we've
gotten support from our QA team to test our code internally on the
simulator. We've even gotten other groups in Intel (outside of OTC) to
contribute to all parts of the stack.

For the foreseeable future, all future platforms will follow this same
enabling procedure that allows us to get better, more stable code, well
before silicon ships. The goal is to get stable drivers in the kernel
release that coincides with the time silicon ships.

As such, a quick thanks:
* Daniel Vetter, for the incredible job he did on maintaining our
internal repository.

* Chris Wilson, for getting me a mostly functional DDX within days of a
working kernel - for that oh so cool glxgears screenshot.

* Ken Graunke, for actually making mesa work with the absurd amount of
changes on the EUs. (and therefore, also enabling said screenshot).

* The Intel internal simulation team, for helping to provide us the
necessary tools to make it all happen.

* The Intel [Windows] graphics team, for providing support, and easing
the process for open source approval

Art Runyan (1):
  drm/i915/bdw: Add BDW DDI buffer translation values

Ben Widawsky (44):
  drm/i915/bdw: IS_GEN8 definition
  drm/i915/bdw: Handle forcewake for writes on gen8
  drm/i915/bdw: Add device IDs
  drm/i915/bdw: Fences on gen8 look just like gen7
  drm/i915/bdw: Swizzling support
  drm/i915/bdw: HW context support
  drm/i915/bdw: Clock gating init
  drm/i915/bdw: display stuff
  drm/i915/bdw: support GMS and GGMS changes
  drm/i915/bdw: Implement interrupt changes
  drm/i915/bdw: Add interrupt info to debugfs
  drm/i915/bdw: Support 64b relocations
  drm/i915/bdw: dispatch updates (64b related)
  drm/i915/bdw: Update MI_FLUSH_DW
  drm/i915/bdw: debugfs updates
  drm/i915/bdw: Update relevant error state
  drm/i915/bdw: Make gen8_gmch_probe
  drm/i915/bdw: Create gen8_gtt_pte_t
  drm/i915/bdw: Add GTT functions
  drm/i915/bdw: Support BDW caching
  drm/i915/bdw: Implement Full Force Miss disables
  drm/i915/bdw: PPGTT init & cleanup
  drm/i915/bdw: Initialize the PDEs
  drm/i915/bdw: Implement PPGTT clear range
  drm/i915/bdw: Implement PPGTT insert
  drm/i915/bdw: Implement PPGTT enable
  drm/i915/bdw: unleash PPGTT
  drm/i915/bdw: Render ring flushing
  drm/i915/bdw: BSD init for gen8 also
  drm/i915/bdw: ppgtt info in debugfs
  drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
  drm/i915/bdw: Use The GT mailbox for IPS enable/disable
  drm/i915/bdw: Support eDP PSR
  drm/i915/bdw: Use HSW formula for ring freq scaling
  drm/i915/bdw: Don't wait for c0 threads on forcewake
  drm/i915/bdw: Create a separate BDW rps enable
  drm/i915/bdw: Disable semaphores
  drm/i915/bdw: Implement edp PSR workarounds
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: Sampler power bypass disable
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints

Damien Lespiau (2):
  drm/i915/bdw: Broadwell has 3 pipes
  drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI

Daniel Vetter (1):
  drm/i915/bdw: Disable PPGTT for now

Paulo Zanoni (11):
  drm/i915/bdw: add IS_BROADWELL macro
  drm/i915/bdw: add Broadwell sprite/plane/cursor checks
  drm/i915/bdw: Broadwell also has the "power down well"
  drm/i915/bdw: pretend we have LPT LP on Broadwell
  drm/i915/bdw: get the correct LCPLL frequency on Broadwell
  drm/i915/bdw: on Broadwell, the panel fitter is on the pipe
  drm/i915/bdw: Broadwell has PIPEMISC
  drm/i915/bdw: add BDW DDI buf translations for eDP
  drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis
  drm/i915/bdw: BDW also has only 2 FDI lanes
  drm/i915/bdw: check DPD on port D when setting the DDI buffers

Ville Syrjälä (3):
  drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
  drm/i915/bdw: Use pipe CSC on Broadwell
  drm/i915/bdw: Add Broadwell display FIFO limits

 arch/x86/kernel/early-quirks.c             |  12 +
 drivers/gpu/drm/i915/i915_debugfs.c        | 109 ++++++-
 drivers/gpu/drm/i915/i915_drv.c            |  34 +-
 drivers/gpu/drm/i915/i915_drv.h            |  36 ++-
 drivers/gpu/drm/i915/i915_gem.c            |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c    |   3 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  35 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 500 +++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_gpu_error.c      |   2 +
 drivers/gpu/drm/i915/i915_irq.c            | 327 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            | 117 ++++++-
 drivers/gpu/drm/i915/intel_ddi.c           | 126 ++++++--
 drivers/gpu/drm/i915/intel_display.c       |  80 ++++-
 drivers/gpu/drm/i915/intel_dp.c            |  55 +++-
 drivers/gpu/drm/i915/intel_hdmi.c          |   2 +-
 drivers/gpu/drm/i915/intel_pm.c            | 168 +++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c    | 187 ++++++++++-
 drivers/gpu/drm/i915/intel_sprite.c        |   5 +-
 drivers/gpu/drm/i915/intel_uncore.c        |  56 +++-
 include/drm/i915_drm.h                     |   4 +
 include/drm/i915_pciids.h                  |  27 ++
 21 files changed, 1771 insertions(+), 117 deletions(-)

-- 
1.8.4.2

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[PATCH 01/62] drm/i915/bdw: IS_GEN8 definition

[Ben Widawsky]

No PCI ids yet, so nothing should happen.

Rebase-Note: This one needs replacement ;-)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2731fbb..c1b178a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1747,6 +1747,7 @@ struct drm_i915_file_private {
 #define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
 #define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
+#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
 
 #define RENDER_RING		(1<<RCS)
 #define BSD_RING		(1<<VCS)
-- 
1.8.4.2

[PATCH 02/62] drm/i915/bdw: Handle forcewake for writes on gen8

[Ben Widawsky]

GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.

How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:

If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]

If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.

While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.

Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.

[1] We could implement a SW queue the way the GT FIFO used to work if
desired.

NOTE: Compile tested only until we get real silicon.

v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
  MMIO as soon as possible.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 52 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f6fae35..fa06ce4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -93,7 +93,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 {
 	u32 forcewake_ack;
 
-	if (IS_HASWELL(dev_priv->dev))
+	if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
 		forcewake_ack = FORCEWAKE_ACK_HSW;
 	else
 		forcewake_ack = FORCEWAKE_MT_ACK;
@@ -459,6 +459,47 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 }
 
+static const u32 gen8_optimized_regs[] = {
+	FORCEWAKE_MT,
+	GEN6_RPNSWREQ,
+	GEN6_RC_VIDEO_FREQ,
+	RING_TAIL(RENDER_RING_BASE),
+	RING_TAIL(GEN6_BSD_RING_BASE),
+	RING_TAIL(VEBOX_RING_BASE),
+	RING_TAIL(BLT_RING_BASE),
+	/* TODO: Other registers are not yet used */
+};
+
+static bool is_gen8_optimized(struct drm_i915_private *dev_priv, u32 reg)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(gen8_optimized_regs); i++)
+		if (reg == gen8_optimized_regs[i])
+			return false;
+
+	return true;
+}
+
+#define __gen8_write(x) \
+static void \
+gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	bool __needs_put = false; \
+	REG_WRITE_HEADER; \
+	__needs_put = is_gen8_optimized(dev_priv, reg); \
+	if (__needs_put) { \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv); \
+	} \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	if (__needs_put) { \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv); \
+	} \
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+}
+
+__gen8_write(8)
+__gen8_write(16)
+__gen8_write(32)
+__gen8_write(64)
 __hsw_write(8)
 __hsw_write(16)
 __hsw_write(32)
@@ -476,6 +517,7 @@ __gen4_write(16)
 __gen4_write(32)
 __gen4_write(64)
 
+#undef __gen8_write
 #undef __hsw_write
 #undef __gen6_write
 #undef __gen5_write
@@ -534,6 +576,15 @@ void intel_uncore_init(struct drm_device *dev)
 	}
 
 	switch (INTEL_INFO(dev)->gen) {
+	default:
+		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
+		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
+		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
+		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
+		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
+		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
+		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
+		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
 	case 7:
 	case 6:
 		if (IS_HASWELL(dev)) {
-- 
1.8.4.2

[PATCH 03/62] drm/i915/bdw: Disable PPGTT for now

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

This will be changed once the gen8 code is fully implemented.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c4c42e7..77b3c74 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -410,6 +410,8 @@ static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 
 	if (INTEL_INFO(dev)->gen < 8)
 		ret = gen6_ppgtt_init(ppgtt);
+	else if (IS_GEN8(dev))
+		ret = -ENXIO;
 	else
 		BUG();
 
-- 
1.8.4.2

[PATCH 04/62] drm/i915/bdw: Add device IDs

[Ben Widawsky]

v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.

v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>

v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.

v4: Replace Halo by its marketing moniker Iris. Requested by Ben.

v5: Switch from info->has*ring to info->ring_mask.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 22 +++++++++++++++++++++-
 include/drm/i915_pciids.h       | 27 +++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 770c9f8..1ff169e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -336,6 +336,24 @@ static const struct intel_device_info intel_haswell_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 };
 
+static const struct intel_device_info intel_broadwell_d_info = {
+	.is_preliminary = 1,
+	.gen = 8,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
+static const struct intel_device_info intel_broadwell_m_info = {
+	.is_preliminary = 1,
+	.gen = 8, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -367,7 +385,9 @@ static const struct intel_device_info intel_haswell_m_info = {
 	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
-	INTEL_VLV_D_IDS(&intel_valleyview_d_info)
+	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
+	INTEL_BDW_PCI_IDS_M(&intel_broadwell_m_info),	\
+	INTEL_BDW_PCI_IDS_D(&intel_broadwell_d_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 8a10f5c..d35bc0b 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -208,4 +208,31 @@
 #define INTEL_VLV_D_IDS(info) \
 	INTEL_VGA_DEVICE(0x0155, info)
 
+#define _INTEL_BDW_PCI_ID_M(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+#define _INTEL_BDW_PCI_ID_D(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+
+#define INTEL_BDW_PCI_ID_M(gt, info) \
+	_INTEL_BDW_PCI_ID_M(gt, 0x1606, info), /* ULT */ \
+	_INTEL_BDW_PCI_ID_M(gt, 0x160B, info), /* Iris */ \
+	_INTEL_BDW_PCI_ID_M(gt, 0x160E, info) /* ULX */
+
+#define INTEL_BDW_PCI_ID_D(gt, info) \
+	_INTEL_BDW_PCI_ID_M(gt, 0x160A, info), /* Server */ \
+	_INTEL_BDW_PCI_ID_M(gt, 0x160D, info) /* Workstation */
+
+#define INTEL_BDW_PCI_IDS_M(info) \
+	INTEL_BDW_PCI_ID_M(1, info), \
+	INTEL_BDW_PCI_ID_M(2, info), \
+	INTEL_BDW_PCI_ID_M(3, info), \
+	INTEL_VGA_DEVICE(0x0BD0, info) /* Simulator GT1 */
+
+#define INTEL_BDW_PCI_IDS_D(info) \
+	INTEL_BDW_PCI_ID_D(1, info), \
+	INTEL_BDW_PCI_ID_D(2, info), \
+	INTEL_BDW_PCI_ID_D(3, info), \
+	INTEL_VGA_DEVICE(0x0BD1, info), /* Simulator GT2 */ \
+	INTEL_VGA_DEVICE(0x0BD2, info)  /*/Simulator GT3 */
+
 #endif /* _I915_PCIIDS_H */
-- 
1.8.4.2

[PATCH 05/62] drm/i915/bdw: Fences on gen8 look just like gen7

[Ben Widawsky]

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem.c       | 1 +
 drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7b39d7..5be1a15 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2954,6 +2954,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
 	     obj->stride, obj->tiling_mode);
 
 	switch (INTEL_INFO(dev)->gen) {
+	case 8:
 	case 7:
 	case 6:
 	case 5:
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5dde810..3d01eae 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -623,6 +623,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
 
 	/* Fences */
 	switch (INTEL_INFO(dev)->gen) {
+	case 8:
 	case 7:
 	case 6:
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
-- 
1.8.4.2

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[PATCH 06/62] drm/i915/bdw: Swizzling support

[Ben Widawsky]

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5be1a15..12bbd5e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4362,6 +4362,8 @@ void i915_gem_init_swizzling(struct drm_device *dev)
 		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 	else if (IS_GEN7(dev))
 		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+	else if (IS_GEN8(dev))
+		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
 	else
 		BUG();
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6799d53..b6b1c78 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -655,6 +655,8 @@
 #define ARB_MODE		0x04030
 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
+#define GAMTARBMODE		0x04a08
+#define   ARB_MODE_SWIZZLE_BDW	(1<<1)
 #define RENDER_HWS_PGA_GEN7	(0x04080)
 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
-- 
1.8.4.2

[PATCH 07/62] drm/i915/bdw: HW context support

[Ben Widawsky]

BDW context sizes varies a bit.

v2: Squash in fixup for the hw context size from Ben.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index cc619c1..72a3df3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -117,6 +117,9 @@ static int get_context_size(struct drm_device *dev)
 		else
 			ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
 		break;
+	case 8:
+		ret = GEN8_CXT_TOTAL_SIZE;
+		break;
 	default:
 		BUG();
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b6b1c78..fb6ad89 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1821,6 +1821,9 @@
  * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
  */
 #define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
+/* Same as Haswell, but 72064 bytes now. */
+#define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
+
 
 #define VLV_CLK_CTL2			0x101104
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
-- 
1.8.4.2

[PATCH 08/62] drm/i915/bdw: Clock gating init

[Ben Widawsky]

Clock gating init is really a catch all function for registers we need
to write early in loading the driver.

Atm just the bare metal stuff we need, more will surely come.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d2a640c..abc51ea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5181,6 +5181,15 @@ static void lpt_suspend_hw(struct drm_device *dev)
 	}
 }
 
+static void gen8_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(WM3_LP_ILK, 0);
+	I915_WRITE(WM2_LP_ILK, 0);
+	I915_WRITE(WM1_LP_ILK, 0);
+}
+
 static void haswell_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5833,6 +5842,8 @@ void intel_init_pm(struct drm_device *dev)
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+		} else if (INTEL_INFO(dev)->gen == 8) {
+			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.8.4.2

[PATCH 09/62] drm/i915/bdw: display stuff

[Ben Widawsky]

Just enough to make the code not barf...

Init BDW display to look like HSW. For the simulator this should be
fine, but this will probably require more work.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0c2e83c..436b750 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10308,7 +10308,7 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.write_eld = ironlake_write_eld;
 			dev_priv->display.modeset_global_resources =
 				ivb_modeset_global_resources;
-		} else if (IS_HASWELL(dev)) {
+		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
 			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 			dev_priv->display.write_eld = haswell_write_eld;
 			dev_priv->display.modeset_global_resources =
@@ -10339,6 +10339,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
 	case 7:
+	case 8:
 		dev_priv->display.queue_flip = intel_gen7_queue_flip;
 		break;
 	}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6..f8b265c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1092,6 +1092,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 		break;
 
 	case 7:
+	case 8:
 		if (IS_IVYBRIDGE(dev)) {
 			intel_plane->can_scale = true;
 			intel_plane->max_downscale = 2;
-- 
1.8.4.2

[PATCH 10/62] drm/i915/bdw: support GMS and GGMS changes

[Ben Widawsky]

All the BARs have the ability to grow.

v2: Pulled out the simulator workaround to a separate patch.
Rebased.

v3: Rebase onto latest vlv patches from Jesse.

v4: Rebased on top of the early stolen quirk patch from Jesse.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 arch/x86/kernel/early-quirks.c      | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++++---
 include/drm/i915_drm.h              |  4 ++++
 3 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b3cd3eb..71fc26b 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -313,6 +313,16 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
 	return gmch_ctrl << 25; /* 32 MB units */
 }
 
+static inline size_t gen8_stolen_size(int num, int slot, int func)
+{
+	u16 gmch_ctrl;
+
+	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
+	gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
+	gmch_ctrl &= BDW_GMCH_GMS_MASK;
+	return gmch_ctrl << 25; /* 32 MB units */
+}
+
 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 
 static struct pci_device_id intel_stolen_ids[] __initdata = {
@@ -336,6 +346,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_IVB_D_IDS(gen6_stolen_size),
 	INTEL_HSW_D_IDS(gen6_stolen_size),
 	INTEL_HSW_M_IDS(gen6_stolen_size),
+	INTEL_BDW_PCI_IDS_M(gen8_stolen_size),
+	INTEL_BDW_PCI_IDS_D(gen8_stolen_size)
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 77b3c74..19016b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -869,6 +869,15 @@ static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 	return snb_gmch_ctl << 20;
 }
 
+static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+{
+	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
+	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
+	if (bdw_gmch_ctl)
+		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+	return bdw_gmch_ctl << 20;
+}
+
 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
@@ -876,6 +885,13 @@ static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 	return snb_gmch_ctl << 25; /* 32 MB units */
 }
 
+static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
+{
+	bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
+	bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
+	return bdw_gmch_ctl << 25; /* 32 MB units */
+}
+
 static int gen6_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -903,10 +919,16 @@ static int gen6_gmch_probe(struct drm_device *dev,
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
-	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 
-	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
-	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+	if (IS_GEN8(dev)) {
+		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+		*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+	} else {
+		gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
+		*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
+	}
 
 	/* For Modern GENs the PTEs and register space are split in the BAR */
 	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
@@ -916,6 +938,7 @@ static int gen6_gmch_probe(struct drm_device *dev,
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
+
 	}
 
 	ret = setup_scratch_page(dev);
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 3abfa6e..97d5497 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -49,6 +49,10 @@ extern bool i915_gpu_turbo_disable(void);
 #define    SNB_GMCH_GGMS_MASK	0x3
 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
 #define    SNB_GMCH_GMS_MASK    0x1f
+#define    BDW_GMCH_GGMS_SHIFT	6
+#define    BDW_GMCH_GGMS_MASK	0x3
+#define    BDW_GMCH_GMS_SHIFT   8
+#define    BDW_GMCH_GMS_MASK    0xff
 
 #define I830_GMCH_CTRL			0x52
 
-- 
1.8.4.2

[PATCH 11/62] drm/i915/bdw: Implement interrupt changes

[Ben Widawsky]

The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.

The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.

For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).

The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).

Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.

v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.

v3: fix DE_MISC IER offset

v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.

v5: Rebased on to of recent pch hotplug setup changes.

v6: Fixup on top of moving num_pipes to intel_info.

v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.

v8: Rebase on top of Jani's asle handling rework.

v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/

v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>

v11: Rebase on top of the interrupt cleanups in upstream.

v12: Rebase on top of Ben's DPF changes in upstream.

v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h         |   5 +-
 drivers/gpu/drm/i915/i915_irq.c         | 327 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h         |  63 ++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c |  90 +++++++--
 4 files changed, 473 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c1b178a..83d016c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1315,7 +1315,10 @@ typedef struct drm_i915_private {
 	struct mutex dpio_lock;
 
 	/** Cached value of IMR to avoid reads in updating the bitfield */
-	u32 irq_mask;
+	union {
+		u32 irq_mask;
+		u32 de_irq_mask[I915_MAX_PIPES];
+	};
 	u32 gt_irq_mask;
 	u32 pm_irq_mask;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a9f0cb6..3f0c9e3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1118,6 +1118,56 @@ static void snb_gt_irq_handler(struct drm_device *dev,
 		ivybridge_parity_error_irq_handler(dev, gt_iir);
 }
 
+static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
+				struct drm_i915_private *dev_priv,
+				u32 master_ctl)
+{
+	u32 rcs, bcs, vcs;
+	uint32_t tmp = 0;
+	irqreturn_t ret = IRQ_NONE;
+
+	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
+		tmp = I915_READ(GEN8_GT_IIR(0));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
+			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
+			if (rcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[RCS]);
+			if (bcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[BCS]);
+			I915_WRITE(GEN8_GT_IIR(0), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT0)!\n");
+	}
+
+	if (master_ctl & GEN8_GT_VCS1_IRQ) {
+		tmp = I915_READ(GEN8_GT_IIR(1));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
+			if (vcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[VCS]);
+			I915_WRITE(GEN8_GT_IIR(1), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT1)!\n");
+	}
+
+	if (master_ctl & GEN8_GT_VECS_IRQ) {
+		tmp = I915_READ(GEN8_GT_IIR(3));
+		if (tmp) {
+			ret = IRQ_HANDLED;
+			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
+			if (vcs & GT_RENDER_USER_INTERRUPT)
+				notify_ring(dev, &dev_priv->ring[VECS]);
+			I915_WRITE(GEN8_GT_IIR(3), tmp);
+		} else
+			DRM_ERROR("The master control interrupt lied (GT3)!\n");
+	}
+
+	return ret;
+}
+
 #define HPD_STORM_DETECT_PERIOD 1000
 #define HPD_STORM_THRESHOLD 5
 
@@ -1699,6 +1749,85 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	return ret;
 }
 
+static irqreturn_t gen8_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl;
+	irqreturn_t ret = IRQ_NONE;
+	uint32_t tmp = 0;
+
+	atomic_inc(&dev_priv->irq_received);
+
+	master_ctl = I915_READ(GEN8_MASTER_IRQ);
+	master_ctl &= ~DE_MASTER_IRQ_CONTROL;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	if ((master_ctl & ~GEN8_RSVD_IRQS) == 0) {
+		DRM_ERROR("Only received RSVD IRQs 0x%08x\n", master_ctl);
+		return IRQ_NONE;
+	}
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+
+	/* NB: Posting read isn't necessary here because we're required to do
+	 * another read no matter what
+	POSTING_READ(GEN8_MASTER_IRQ);
+	*/
+
+	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+
+	if (master_ctl & GEN8_DE_MISC_IRQ) {
+		tmp = I915_READ(GEN8_DE_MISC_IIR);
+		if (tmp) {
+			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
+			ret = IRQ_HANDLED;
+		}
+
+		if (tmp & GEN8_DE_MISC_GSE)
+			intel_opregion_asle_intr(dev);
+		else if (tmp)
+			DRM_ERROR("Unexpected DE Misc interrupt\n");
+		else
+			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+
+	}
+
+	if (master_ctl & GEN8_DE_IRQS) {
+		int de_ret = 0;
+		int pipe;
+		for_each_pipe(pipe) {
+			uint32_t pipe_iir;
+
+		        pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+			if (pipe_iir & _PIPE_VBLANK) {
+				drm_handle_vblank(dev, pipe);
+			}
+			if (pipe_iir & _PIPE_FLIP_DONE) {
+				intel_prepare_page_flip(dev, pipe);
+				intel_finish_page_flip_plane(dev, pipe);
+			}
+
+			if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
+				DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
+
+			if (pipe_iir) {
+				de_ret++;
+				ret = IRQ_HANDLED;
+				I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
+			}
+		}
+		if (!de_ret)
+			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
+	}
+
+	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return ret;
+}
+
 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
 			       bool reset_completed)
 {
@@ -2052,6 +2181,25 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
 	return 0;
 }
 
+static int gen8_enable_vblank(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long irqflags;
+	uint32_t imr;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
+	if ((imr & _PIPE_VBLANK) == 1) {
+		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~_PIPE_VBLANK);
+		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	}
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+	return 0;
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -2100,6 +2248,24 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+static void gen8_disable_vblank(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long irqflags;
+	uint32_t imr;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
+	if ((imr & _PIPE_VBLANK) == 0) {
+		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | _PIPE_VBLANK);
+		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	}
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 static u32
 ring_last_seqno(struct intel_ring_buffer *ring)
 {
@@ -2430,6 +2596,51 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 	POSTING_READ(VLV_IER);
 }
 
+static void gen8_irq_preinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	atomic_set(&dev_priv->irq_received, 0);
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	/* IIR can theoretically queue up two events. Be paranoid */
+#define GEN8_IRQ_INIT_NDX(type, which) \
+	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
+	POSTING_READ(GEN8_##type##_IMR(which)); \
+	I915_WRITE(GEN8_##type##_IER(which), 0); \
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
+	POSTING_READ(GEN8_##type##_IIR(which)); \
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff)
+
+#define GEN8_IRQ_INIT(type) \
+	I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
+	POSTING_READ(GEN8_##type##_IMR); \
+	I915_WRITE(GEN8_##type##_IER, 0); \
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
+	POSTING_READ(GEN8_##type##_IIR); \
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff)
+
+	GEN8_IRQ_INIT_NDX(GT, 0);
+	GEN8_IRQ_INIT_NDX(GT, 1);
+	GEN8_IRQ_INIT_NDX(GT, 2);
+	GEN8_IRQ_INIT_NDX(GT, 3);
+
+	for_each_pipe(pipe) {
+		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
+	}
+
+	GEN8_IRQ_INIT(DE_PORT);
+	GEN8_IRQ_INIT(DE_MISC);
+	GEN8_IRQ_INIT(PCU);
+#undef GEN8_IRQ_INIT
+#undef GEN8_IRQ_INIT_NDX
+
+	POSTING_READ(GEN8_PCU_IIR);
+}
+
 static void ibx_hpd_irq_setup(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2635,6 +2846,114 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	int i;
+
+	/* These are interrupts we'll toggle with the ring mask register */
+	uint32_t gt_interrupts[] = {
+		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
+			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
+		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
+			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
+		0,
+		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
+		};
+
+	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
+		u32 tmp = I915_READ(GEN8_GT_IIR(i));
+		if (tmp)
+			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
+				  i, tmp);
+		I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
+		I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
+	}
+	POSTING_READ(GEN8_GT_IER(0));
+}
+
+static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	uint32_t de_pipe_enables = _PIPE_FLIP_DONE |
+				   _PIPE_SCAN_LINE_EVENT |
+				   _PIPE_VBLANK |
+				   GEN8_DE_PIPE_IRQ_ERRORS;
+	int pipe;
+	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
+	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
+	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
+
+	for_each_pipe(pipe) {
+		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		if (tmp)
+			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
+				  pipe, tmp);
+		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+		I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
+	}
+	POSTING_READ(GEN8_DE_PIPE_ISR(0));
+
+	I915_WRITE(GEN8_DE_PORT_IMR, ~_PORT_DP_A_HOTPLUG);
+	I915_WRITE(GEN8_DE_PORT_IER, _PORT_DP_A_HOTPLUG);
+	POSTING_READ(GEN8_DE_PORT_IER);
+}
+
+static int gen8_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	gen8_gt_irq_postinstall(dev_priv);
+	gen8_de_irq_postinstall(dev_priv);
+
+	ibx_irq_postinstall(dev);
+
+	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(GEN8_MASTER_IRQ);
+
+	return 0;
+}
+
+static void gen8_irq_uninstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	if (!dev_priv)
+		return;
+
+	atomic_set(&dev_priv->irq_received, 0);
+
+	I915_WRITE(GEN8_MASTER_IRQ, 0);
+
+#define GEN8_IRQ_FINI_NDX(type, which) \
+	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
+	I915_WRITE(GEN8_##type##_IER(which), 0); \
+	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff)
+
+#define GEN8_IRQ_FINI(type) \
+	I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
+	I915_WRITE(GEN8_##type##_IER, 0); \
+	I915_WRITE(GEN8_##type##_IIR, 0xffffffff)
+
+	GEN8_IRQ_FINI_NDX(GT, 0);
+	GEN8_IRQ_FINI_NDX(GT, 1);
+	GEN8_IRQ_FINI_NDX(GT, 2);
+	GEN8_IRQ_FINI_NDX(GT, 3);
+
+	for_each_pipe(pipe) {
+		GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
+	}
+
+	GEN8_IRQ_FINI(DE_PORT);
+	GEN8_IRQ_FINI(DE_MISC);
+	GEN8_IRQ_FINI(PCU);
+#undef GEN8_IRQ_FINI
+#undef GEN8_IRQ_FINI_NDX
+
+	POSTING_READ(GEN8_PCU_IIR);
+}
+
 static void valleyview_irq_uninstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3414,6 +3733,14 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->enable_vblank = valleyview_enable_vblank;
 		dev->driver->disable_vblank = valleyview_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (IS_GEN8(dev)) {
+		dev->driver->irq_handler = gen8_irq_handler;
+		dev->driver->irq_preinstall = gen8_irq_preinstall;
+		dev->driver->irq_postinstall = gen8_irq_postinstall;
+		dev->driver->irq_uninstall = gen8_irq_uninstall;
+		dev->driver->enable_vblank = gen8_enable_vblank;
+		dev->driver->disable_vblank = gen8_disable_vblank;
+		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb6ad89..b801b88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3989,6 +3989,69 @@
 #define GTIIR   0x44018
 #define GTIER   0x4401c
 
+#define GEN8_MASTER_IRQ			0x44200
+#define  GEN8_PCU_IRQ			(1<<30)
+#define  GEN8_DE_PCH_IRQ		(1<<23)
+#define  GEN8_DE_MISC_IRQ		(1<<22)
+#define  GEN8_DE_PORT_IRQ		(1<<20)
+#define  GEN8_DE_PIPE_C_IRQ		(1<<18)
+#define  GEN8_DE_PIPE_B_IRQ		(1<<17)
+#define  GEN8_DE_PIPE_A_IRQ		(1<<16)
+#define  GEN8_GT_VECS_IRQ		(1<<6)
+#define  GEN8_GT_VCS2_IRQ		(1<<3)
+#define  GEN8_GT_VCS1_IRQ		(1<<2)
+#define  GEN8_GT_BCS_IRQ		(1<<1)
+#define  GEN8_GT_RCS_IRQ		(1<<0)
+/* Lazy definition */
+#define  GEN8_GT_IRQS			0x000000ff
+#define  GEN8_DE_IRQS			0x01ff0000
+#define  GEN8_RSVD_IRQS			0xB700ff00
+
+#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
+#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
+#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
+#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
+
+#define GEN8_BCS_IRQ_SHIFT 16
+#define GEN8_RCS_IRQ_SHIFT 0
+#define GEN8_VCS2_IRQ_SHIFT 16
+#define GEN8_VCS1_IRQ_SHIFT 0
+#define GEN8_VECS_IRQ_SHIFT 0
+
+#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
+#define  _PIPE_UNDERRUN			(1 << 31)
+#define  _PIPE_CDCLK_CRC_ERROR		(1 << 29)
+#define  _PIPE_CURSOR_FAULT		(1 << 10)
+#define  _PIPE_SPRITE_FAULT		(1 << 9)
+#define  _PIPE_PRIMARY_FAULT		(1 << 8)
+#define  _PIPE_SPRITE_FLIP_DONE		(1 << 5)
+#define  _PIPE_FLIP_DONE		(1 << 4)
+#define  _PIPE_SCAN_LINE_EVENT		(1 << 3)
+#define  _PIPE_VBLANK			(1 << 0)
+#define GEN8_DE_PIPE_IRQ_ERRORS	(_PIPE_UNDERRUN | _PIPE_CDCLK_CRC_ERROR | \
+				_PIPE_CURSOR_FAULT | _PIPE_SPRITE_FAULT | \
+				_PIPE_PRIMARY_FAULT)
+
+#define GEN8_DE_PORT_ISR 0x44440
+#define GEN8_DE_PORT_IMR 0x44444
+#define GEN8_DE_PORT_IIR 0x44448
+#define GEN8_DE_PORT_IER 0x4444c
+#define  _PORT_DP_A_HOTPLUG		(1 << 3)
+
+#define GEN8_DE_MISC_ISR 0x44460
+#define GEN8_DE_MISC_IMR 0x44464
+#define GEN8_DE_MISC_IIR 0x44468
+#define GEN8_DE_MISC_IER 0x4446c
+#define  GEN8_DE_MISC_GSE		(1 << 27)
+
+#define GEN8_PCU_ISR 0x444e0
+#define GEN8_PCU_IMR 0x444e4
+#define GEN8_PCU_IIR 0x444e8
+#define GEN8_PCU_IER 0x444ec
+
 #define ILK_DISPLAY_CHICKEN2	0x42004
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2dec134..b2161f2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1066,6 +1066,48 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 }
 
+static bool
+gen8_ring_get_irq(struct intel_ring_buffer *ring)
+{
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long flags;
+
+	if (!dev->irq_enabled)
+	       return false;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, flags);
+	if (ring->irq_refcount++ == 0) {
+		if (HAS_L3_DPF(dev) && ring->id == RCS)
+			I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
+						GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
+		else
+			I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
+		POSTING_READ(RING_IMR(ring->mmio_base));
+	}
+	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+	return true;
+}
+
+static void
+gen8_ring_put_irq(struct intel_ring_buffer *ring)
+{
+	struct drm_device *dev = ring->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, flags);
+	if (--ring->irq_refcount == 0) {
+		if (HAS_L3_DPF(dev) && ring->id == RCS)
+			I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+		else
+			I915_WRITE_IMR(ring, ~0);
+		POSTING_READ(RING_IMR(ring->mmio_base));
+	}
+	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
+
 static int
 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			 u32 offset, u32 length,
@@ -1732,8 +1774,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		ring->flush = gen7_render_ring_flush;
 		if (INTEL_INFO(dev)->gen == 6)
 			ring->flush = gen6_render_ring_flush;
-		ring->irq_get = gen6_ring_get_irq;
-		ring->irq_put = gen6_ring_put_irq;
+		if (INTEL_INFO(dev)->gen >= 8) {
+			ring->irq_get = gen8_ring_get_irq;
+			ring->irq_put = gen8_ring_put_irq;
+		} else {
+			ring->irq_get = gen6_ring_get_irq;
+			ring->irq_put = gen6_ring_put_irq;
+		}
 		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
 		ring->get_seqno = gen6_ring_get_seqno;
 		ring->set_seqno = ring_set_seqno;
@@ -1897,9 +1944,15 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 		ring->add_request = gen6_add_request;
 		ring->get_seqno = gen6_ring_get_seqno;
 		ring->set_seqno = ring_set_seqno;
-		ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
-		ring->irq_get = gen6_ring_get_irq;
-		ring->irq_put = gen6_ring_put_irq;
+		if (INTEL_INFO(dev)->gen >= 8) {
+			ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
+			ring->irq_get = gen8_ring_get_irq;
+			ring->irq_put = gen8_ring_put_irq;
+		} else {
+			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+			ring->irq_get = gen6_ring_get_irq;
+			ring->irq_put = gen6_ring_put_irq;
+		}
 		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 		ring->sync_to = gen6_ring_sync;
 		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
@@ -1946,9 +1999,15 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
-	ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
-	ring->irq_get = gen6_ring_get_irq;
-	ring->irq_put = gen6_ring_put_irq;
+	if (INTEL_INFO(dev)->gen >= 8) {
+		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
+		ring->irq_get = gen8_ring_get_irq;
+		ring->irq_put = gen8_ring_put_irq;
+	} else {
+		ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
+		ring->irq_get = gen6_ring_get_irq;
+		ring->irq_put = gen6_ring_put_irq;
+	}
 	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	ring->sync_to = gen6_ring_sync;
 	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
@@ -1978,10 +2037,19 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
-	ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
-	ring->irq_get = hsw_vebox_get_irq;
-	ring->irq_put = hsw_vebox_put_irq;
 	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+
+	if (INTEL_INFO(dev)->gen >= 8) {
+		ring->irq_enable_mask =
+			(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT) |
+			GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
+		ring->irq_get = gen8_ring_get_irq;
+		ring->irq_put = gen8_ring_put_irq;
+	} else {
+		ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
+		ring->irq_get = hsw_vebox_get_irq;
+		ring->irq_put = hsw_vebox_put_irq;
+	}
 	ring->sync_to = gen6_ring_sync;
 	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
 	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
-- 
1.8.4.2

[PATCH 12/62] drm/i915/bdw: Add interrupt info to debugfs

[Ben Widawsky]

v2: Add missed ring interrupt info

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 50 +++++++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5c45e9e..d6cda9c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -586,7 +586,53 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	if (ret)
 		return ret;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (INTEL_INFO(dev)->gen >= 8) {
+		int i;
+		seq_printf(m, "Master Interrupt Control:\t%08x\n",
+			   I915_READ(GEN8_MASTER_IRQ));
+
+		for (i = 0; i < 4; i++) {
+			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IMR(i)));
+			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IIR(i)));
+			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+				   i, I915_READ(GEN8_GT_IER(i)));
+		}
+
+		for_each_pipe(i) {
+			seq_printf(m, "Pipe %c IMR:\t%08x\n",
+				   pipe_name(i),
+				   I915_READ(GEN8_DE_PIPE_IMR(i)));
+			seq_printf(m, "Pipe %c IIR:\t%08x\n",
+				   pipe_name(i),
+				   I915_READ(GEN8_DE_PIPE_IIR(i)));
+			seq_printf(m, "Pipe %c IER:\t%08x\n",
+				   pipe_name(i),
+				   I915_READ(GEN8_DE_PIPE_IER(i)));
+		}
+
+		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IMR));
+		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IIR));
+		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IER));
+
+		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IMR));
+		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IIR));
+		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IER));
+
+		seq_printf(m, "PCU interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_PCU_IMR));
+		seq_printf(m, "PCU interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_PCU_IIR));
+		seq_printf(m, "PCU interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_PCU_IER));
+	} else if (IS_VALLEYVIEW(dev)) {
 		seq_printf(m, "Display IER:\t%08x\n",
 			   I915_READ(VLV_IER));
 		seq_printf(m, "Display IIR:\t%08x\n",
@@ -658,7 +704,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	seq_printf(m, "Interrupts received: %d\n",
 		   atomic_read(&dev_priv->irq_received));
 	for_each_ring(ring, dev_priv, i) {
-		if (IS_GEN6(dev) || IS_GEN7(dev)) {
+		if (INTEL_INFO(dev)->gen >= 6) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
 				   ring->name, I915_READ_IMR(ring));
-- 
1.8.4.2

[PATCH 13/62] drm/i915/bdw: Support 64b relocations

[Ben Widawsky]

We don't actually return any to userspace yet, however we can pretend
like we do now so userspace will support it when it happens.

This is just to please Chris as the code itself isn't ready for > 64b
relocations.

v2: Rebase on top of the refactored relocate_entry_gtt|cpu functions.

v3: Squash in fixup from Rafal Barbalho for 64 byte relocs using cpu
relocs and those crossing a page boundary.

v4: Squash in a fixup for the fixup from Rafael.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Barbalho, Rafael <rafael.barbalho@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 32 +++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 0ce0d47..78786c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -212,6 +212,7 @@ static int
 relocate_entry_cpu(struct drm_i915_gem_object *obj,
 		   struct drm_i915_gem_relocation_entry *reloc)
 {
+	struct drm_device *dev = obj->base.dev;
 	uint32_t page_offset = offset_in_page(reloc->offset);
 	char *vaddr;
 	int ret = -EINVAL;
@@ -223,6 +224,19 @@ relocate_entry_cpu(struct drm_i915_gem_object *obj,
 	vaddr = kmap_atomic(i915_gem_object_get_page(obj,
 				reloc->offset >> PAGE_SHIFT));
 	*(uint32_t *)(vaddr + page_offset) = reloc->delta;
+
+	if (INTEL_INFO(dev)->gen >= 8) {
+		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
+
+		if (page_offset == 0) {
+			kunmap_atomic(vaddr);
+			vaddr = kmap_atomic(i915_gem_object_get_page(obj,
+			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
+		}
+
+		*(uint32_t *)(vaddr + page_offset) = 0;
+	}
+
 	kunmap_atomic(vaddr);
 
 	return 0;
@@ -253,6 +267,21 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj,
 	reloc_entry = (uint32_t __iomem *)
 		(reloc_page + offset_in_page(reloc->offset));
 	iowrite32(reloc->delta, reloc_entry);
+
+	if (INTEL_INFO(dev)->gen >= 8) {
+		reloc_entry += 1;
+
+		if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) {
+			io_mapping_unmap_atomic(reloc_page);
+			reloc_page = io_mapping_map_atomic_wc(
+					dev_priv->gtt.mappable,
+					reloc->offset + sizeof(uint32_t));
+			reloc_entry = reloc_page;
+		}
+
+		iowrite32(0, reloc_entry);
+	}
+
 	io_mapping_unmap_atomic(reloc_page);
 
 	return 0;
@@ -323,7 +352,8 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 		return 0;
 
 	/* Check that the relocation address is valid... */
-	if (unlikely(reloc->offset > obj->base.size - 4)) {
+	if (unlikely(reloc->offset >
+		obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
 		DRM_DEBUG("Relocation beyond object bounds: "
 			  "obj %p target %d offset %d size %d.\n",
 			  obj, reloc->target_handle,
-- 
1.8.4.2

[PATCH 14/62] drm/i915/bdw: dispatch updates (64b related)

[Ben Widawsky]

The command to emit batch buffers has changed to address 48b addresses.
It seemed reasonable that we could still use the old instruction where
emitting 0 for length would do the right thing, but it seems to bother
the simulator when the code does that.

Now the second dword in the command has the upper 16b of the address of
the batchbuffer.

v2: Remove duplicated vfun assignment.

v3: Squash in VECS support changes from Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +++++++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b2161f2..60ef8ff 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1684,6 +1684,27 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
 }
 
 static int
+gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
+			      u32 offset, u32 len,
+			      unsigned flags)
+{
+	int ret;
+
+	ret = intel_ring_begin(ring, 4);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, MI_BATCH_BUFFER_START | 1);
+	/* bit0-7 is the length on GEN6+ */
+	intel_ring_emit(ring, offset);
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int
 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			      u32 offset, u32 len,
 			      unsigned flags)
@@ -1822,6 +1843,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 	ring->write_tail = ring_write_tail;
 	if (IS_HASWELL(dev))
 		ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
+	else if (IS_GEN8(dev))
+		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 	else if (INTEL_INFO(dev)->gen >= 6)
 		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	else if (INTEL_INFO(dev)->gen >= 4)
@@ -1948,12 +1971,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 			ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
 			ring->irq_get = gen8_ring_get_irq;
 			ring->irq_put = gen8_ring_put_irq;
+			ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 		} else {
 			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
 			ring->irq_get = gen6_ring_get_irq;
 			ring->irq_put = gen6_ring_put_irq;
+			ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 		}
-		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 		ring->sync_to = gen6_ring_sync;
 		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
 		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
@@ -2003,12 +2027,13 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
 		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 		ring->irq_get = gen8_ring_get_irq;
 		ring->irq_put = gen8_ring_put_irq;
+		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 	} else {
 		ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
+		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	}
-	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	ring->sync_to = gen6_ring_sync;
 	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
 	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
@@ -2037,7 +2062,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
-	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 
 	if (INTEL_INFO(dev)->gen >= 8) {
 		ring->irq_enable_mask =
@@ -2045,10 +2069,12 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
 			GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
 		ring->irq_get = gen8_ring_get_irq;
 		ring->irq_put = gen8_ring_put_irq;
+		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 	} else {
 		ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
 		ring->irq_get = hsw_vebox_get_irq;
 		ring->irq_put = hsw_vebox_put_irq;
+		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
 	}
 	ring->sync_to = gen6_ring_sync;
 	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
-- 
1.8.4.2

[PATCH 15/62] drm/i915/bdw: Update MI_FLUSH_DW

[Ben Widawsky]

The code is more verbose than necessary for the reader's sake, hopefully
the compiler optimizes away the if.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 60ef8ff..0d56d1a5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1666,6 +1666,8 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
+	if (INTEL_INFO(ring->dev)->gen >= 8)
+		cmd += 1;
 	/*
 	 * Bspec vol 1c.5 - video engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
@@ -1677,8 +1679,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
 			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-	intel_ring_emit(ring, 0);
-	intel_ring_emit(ring, MI_NOOP);
+	if (INTEL_INFO(ring->dev)->gen >= 8) {
+		intel_ring_emit(ring, 0); /* upper addr */
+		intel_ring_emit(ring, 0); /* value */
+	} else  {
+		intel_ring_emit(ring, 0);
+		intel_ring_emit(ring, MI_NOOP);
+	}
 	intel_ring_advance(ring);
 	return 0;
 }
@@ -1760,6 +1767,8 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
+	if (INTEL_INFO(ring->dev)->gen >= 8)
+		cmd += 1;
 	/*
 	 * Bspec vol 1c.3 - blitter engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
@@ -1771,8 +1780,13 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
 			MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-	intel_ring_emit(ring, 0);
-	intel_ring_emit(ring, MI_NOOP);
+	if (INTEL_INFO(ring->dev)->gen >= 8) {
+		intel_ring_emit(ring, 0); /* upper addr */
+		intel_ring_emit(ring, 0); /* value */
+	} else  {
+		intel_ring_emit(ring, 0);
+		intel_ring_emit(ring, MI_NOOP);
+	}
 	intel_ring_advance(ring);
 
 	if (IS_GEN7(dev) && flush)
-- 
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 16/62] drm/i915/bdw: debugfs updates

[Ben Widawsky]

All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
later, I am certain.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d6cda9c..fa3492f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1623,7 +1623,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ16(C0DRB3));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
 			   I915_READ16(C1DRB3));
-	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   I915_READ(MAD_DIMM_C0));
 		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
@@ -1632,8 +1632,12 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ(MAD_DIMM_C2));
 		seq_printf(m, "TILECTL = 0x%08x\n",
 			   I915_READ(TILECTL));
-		seq_printf(m, "ARB_MODE = 0x%08x\n",
-			   I915_READ(ARB_MODE));
+		if (IS_GEN8(dev))
+			seq_printf(m, "ARB_MODE = 0x%08x\n",
+				   I915_READ(GAMTARBMODE));
+		else
+			seq_printf(m, "ARB_MODE = 0x%08x\n",
+				   I915_READ(ARB_MODE));
 		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
 			   I915_READ(DISP_ARB_CTL));
 	}
-- 
1.8.4.2

[PATCH 17/62] drm/i915/bdw: Update relevant error state

[Ben Widawsky]

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3d01eae..a55ebe8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1043,6 +1043,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
 	default:
 		WARN_ONCE(1, "Unsupported platform\n");
 	case 7:
+	case 8:
 		instdone[0] = I915_READ(GEN7_INSTDONE_1);
 		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
-- 
1.8.4.2

[PATCH 18/62] drm/i915/bdw: Make gen8_gmch_probe

[Ben Widawsky]

Probing gen8 is similar to gen6. To make the code cleaner and more
maintainable however we can use the probe functions to split it out.

v2: Rebased on top of update gtt probe infrastructure.

v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.

V4: Resolve conflicts with Ben's latest ppgtt patches, also switch to
gen < 8 testing instead of gen <= 7.

v5: Resolve conflicts with address space vfunc changes in upstream.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++++++++++++++++++++++++++----------
 1 file changed, 68 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 19016b7..c6d38d0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -892,6 +892,66 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 25; /* 32 MB units */
 }
 
+static int ggtt_probe_common(struct drm_device *dev,
+			     size_t gtt_size)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	phys_addr_t gtt_bus_addr;
+	int ret;
+
+	/* For Modern GENs the PTEs and register space are split in the BAR */
+	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
+		(pci_resource_len(dev->pdev, 0) / 2);
+
+	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
+	if (!dev_priv->gtt.gsm) {
+		DRM_ERROR("Failed to map the gtt page table\n");
+		return -ENOMEM;
+	}
+
+	ret = setup_scratch_page(dev);
+	if (ret) {
+		DRM_ERROR("Scratch setup failed\n");
+		/* iounmap will also get called at remove, but meh */
+		iounmap(dev_priv->gtt.gsm);
+	}
+
+	return ret;
+}
+
+static int gen8_gmch_probe(struct drm_device *dev,
+			   size_t *gtt_total,
+			   size_t *stolen,
+			   phys_addr_t *mappable_base,
+			   unsigned long *mappable_end)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned int gtt_size;
+	u16 snb_gmch_ctl;
+	int ret;
+
+	/* TODO: We're not aware of mappable constraints on gen8 yet */
+	*mappable_base = pci_resource_start(dev->pdev, 2);
+	*mappable_end = pci_resource_len(dev->pdev, 2);
+
+	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
+		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
+
+	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+
+	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+
+	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+
+	ret = ggtt_probe_common(dev, gtt_size);
+
+	dev_priv->gtt.base.clear_range = NULL;
+	dev_priv->gtt.base.insert_entries = NULL;
+
+	return ret;
+}
+
 static int gen6_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -899,7 +959,6 @@ static int gen6_gmch_probe(struct drm_device *dev,
 			   unsigned long *mappable_end)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	phys_addr_t gtt_bus_addr;
 	unsigned int gtt_size;
 	u16 snb_gmch_ctl;
 	int ret;
@@ -920,30 +979,12 @@ static int gen6_gmch_probe(struct drm_device *dev,
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	if (IS_GEN8(dev)) {
-		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
-		*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
-		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
-	} else {
-		gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
-		*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
-		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
-	}
-
-	/* For Modern GENs the PTEs and register space are split in the BAR */
-	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
-		(pci_resource_len(dev->pdev, 0) / 2);
-
-	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
-	if (!dev_priv->gtt.gsm) {
-		DRM_ERROR("Failed to map the gtt page table\n");
-		return -ENOMEM;
+	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
 
-	}
+	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
+	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 
-	ret = setup_scratch_page(dev);
-	if (ret)
-		DRM_ERROR("Scratch setup failed\n");
+	ret = ggtt_probe_common(dev, gtt_size);
 
 	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
@@ -997,7 +1038,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen <= 5) {
 		gtt->gtt_probe = i915_gmch_probe;
 		gtt->base.cleanup = i915_gmch_remove;
-	} else {
+	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
 		if (IS_HASWELL(dev) && dev_priv->ellc_size)
@@ -1010,6 +1051,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
 			gtt->base.pte_encode = ivb_pte_encode;
 		else
 			gtt->base.pte_encode = snb_pte_encode;
+	} else {
+		dev_priv->gtt.gtt_probe = gen8_gmch_probe;
+		dev_priv->gtt.base.cleanup = gen6_gmch_remove;
 	}
 
 	ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
-- 
1.8.4.2

[PATCH 19/62] drm/i915/bdw: Create gen8_gtt_pte_t

[Ben Widawsky]

With gen6 PTE type in place, pave the way for the new gen8 type.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6d38d0..8bf2184 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -30,6 +30,7 @@
 
 #define GEN6_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
+typedef uint64_t gen8_gtt_pte_t;
 
 /* PPGTT stuff */
 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
@@ -942,7 +943,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
 	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
 
 	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
-	*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
 	ret = ggtt_probe_common(dev, gtt_size);
 
-- 
1.8.4.2

[PATCH 20/62] drm/i915/bdw: Add GTT functions

[Ben Widawsky]

With the PTE clarifications, the bind and clear functions can now be
added for gen8.

v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.

v3: Drop dev argument to pte encode functions, upstream lost it. Also
rebase on top of the scratch page movement.

v4: Rebase on top of the new address space vfuncs.

v5: Add the bool use_scratch argument to clear_range and the bool valid argument
to the PTE encode function to follow upstream changes.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++++++++++++++++++++++++++++++++++--
 1 file changed, 85 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8bf2184..df992dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -58,6 +58,15 @@ typedef uint64_t gen8_gtt_pte_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
+					     enum i915_cache_level level,
+					     bool valid)
+{
+	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+	pte |= addr;
+	return pte;
+}
+
 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 				     enum i915_cache_level level,
 				     bool valid)
@@ -576,6 +585,56 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 	return 0;
 }
 
+static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
+{
+#ifdef writeq
+	writeq(pte, addr);
+#else
+	iowrite32((u32)pte, addr);
+	iowrite32(pte >> 32, addr + 4);
+#endif
+}
+
+static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
+				     struct sg_table *st,
+				     unsigned int first_entry,
+				     enum i915_cache_level level)
+{
+	struct drm_i915_private *dev_priv = vm->dev->dev_private;
+	gen8_gtt_pte_t __iomem *gtt_entries =
+		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
+	int i = 0;
+	struct sg_page_iter sg_iter;
+	dma_addr_t addr;
+
+	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
+		addr = sg_dma_address(sg_iter.sg) +
+			(sg_iter.sg_pgoffset << PAGE_SHIFT);
+		gen8_set_pte(&gtt_entries[i],
+			     gen8_pte_encode(addr, level, true));
+		i++;
+	}
+
+	/* XXX: This serves as a posting read to make sure that the PTE has
+	 * actually been updated. There is some concern that even though
+	 * registers and PTEs are within the same BAR that they are potentially
+	 * of NUMA access patterns. Therefore, even with the way we assume
+	 * hardware should work, we must keep this posting read for paranoia.
+	 */
+	if (i != 0)
+		WARN_ON(readl(&gtt_entries[i-1])
+			!= gen8_pte_encode(addr, level, true));
+
+#if 0 /* TODO: Still needed on GEN8? */
+	/* This next bit makes the above posting read even more important. We
+	 * want to flush the TLBs only after we're certain all the PTE updates
+	 * have finished.
+	 */
+	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+#endif
+}
+
 /*
  * Binds an object into the global gtt with the specified cache level. The object
  * will be accessible to the GPU via commands whose operands reference offsets
@@ -618,6 +677,30 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
 }
 
+static void gen8_ggtt_clear_range(struct i915_address_space *vm,
+				  unsigned int first_entry,
+				  unsigned int num_entries,
+				  bool use_scratch)
+{
+	struct drm_i915_private *dev_priv = vm->dev->dev_private;
+	gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
+		(gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
+	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
+	int i;
+
+	if (WARN(num_entries > max_entries,
+		 "First entry = %d; Num entries = %d (max=%d)\n",
+		 first_entry, num_entries, max_entries))
+		num_entries = max_entries;
+
+	scratch_pte = gen8_pte_encode(vm->scratch.addr,
+				      I915_CACHE_LLC,
+				      use_scratch);
+	for (i = 0; i < num_entries; i++)
+		gen8_set_pte(&gtt_base[i], scratch_pte);
+	readl(gtt_base);
+}
+
 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 				  unsigned int first_entry,
 				  unsigned int num_entries,
@@ -641,7 +724,6 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 	readl(gtt_base);
 }
 
-
 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     unsigned int pg_start,
@@ -947,8 +1029,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
 
 	ret = ggtt_probe_common(dev, gtt_size);
 
-	dev_priv->gtt.base.clear_range = NULL;
-	dev_priv->gtt.base.insert_entries = NULL;
+	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
+	dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
 
 	return ret;
 }
-- 
1.8.4.2

[PATCH 21/62] drm/i915/bdw: Support BDW caching

[Ben Widawsky]

BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HSW and before.

v2: Tiny bikeshed as discussed on internal irc.

v3: Squash in patch from Ville to mirror the x86 PAT setup more like
in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
uncached.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  1 +
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index df992dc..02de12d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -58,12 +58,21 @@ typedef uint64_t gen8_gtt_pte_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
+#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
+#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
+#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
+
 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 					     enum i915_cache_level level,
 					     bool valid)
 {
 	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 	pte |= addr;
+	if (level != I915_CACHE_NONE)
+		pte |= PPAT_CACHED_INDEX;
+	else
+		pte |= PPAT_UNCACHED_INDEX;
 	return pte;
 }
 
@@ -805,6 +814,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
 			*end -= 4096;
 	}
 }
+
 void i915_gem_setup_global_gtt(struct drm_device *dev,
 			       unsigned long start,
 			       unsigned long mappable_end,
@@ -1002,6 +1012,36 @@ static int ggtt_probe_common(struct drm_device *dev,
 	return ret;
 }
 
+/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
+ * bits. When using advanced contexts each context stores its own PAT, but
+ * writing this data shouldn't be harmful even in those cases. */
+static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+#define GEN8_PPAT_UC		(0<<0)
+#define GEN8_PPAT_WC		(1<<0)
+#define GEN8_PPAT_WT		(2<<0)
+#define GEN8_PPAT_WB		(3<<0)
+#define GEN8_PPAT_ELLC_OVERRIDE	(0<<2)
+#define GEN8_PPAT_LLC		(1<<2)
+#define GEN8_PPAT_LLCELLC	(2<<2)
+#define GEN8_PPAT_LLCeLLC	(3<<2) /* BSPEC mistake? */
+#define GEN8_PPAT_AGE(x)	(x<<4)
+#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
+	uint64_t pat;
+
+	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
+	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
+	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
+	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
+	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
+	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
+	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
+	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+
+	I915_WRITE(GEN8_PRIVATE_PAT, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+}
+
 static int gen8_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -1027,6 +1067,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
 	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
+	gen8_setup_private_ppat(dev_priv);
+
 	ret = ggtt_probe_common(dev, gtt_size);
 
 	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b801b88..9929750 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -664,6 +664,7 @@
 #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
 #define DONE_REG		0x40b0
+#define GEN8_PRIVATE_PAT	0x40e0
 #define BSD_HWS_PGA_GEN7	(0x04180)
 #define BLT_HWS_PGA_GEN7	(0x04280)
 #define VEBOX_HWS_PGA_GEN7	(0x04380)
-- 
1.8.4.2

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 22/62] drm/i915/bdw: Implement Full Force Miss disables

[Ben Widawsky]

Implements WaVSRefCountFullforceMissDisable
Implements WaDSRefCountFullforceMissDisable

v2: Rebased on the HSW patch (which fixed the bug from v1)
commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Sat Jan 26 11:52:00 2013 -0800

    drm/i915: Implement WaVSRefCountFullforceMissDisable

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9929750..68b877d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -990,6 +990,7 @@
 
 #define GEN7_FF_THREAD_MODE		0x20a0
 #define   GEN7_FF_SCHED_MASK		0x0077070
+#define   GEN7_FF_DS_REF_CNT_FFME	(1 << 19)
 #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
 #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index abc51ea..81ec2c3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5147,6 +5147,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	if (IS_HASWELL(dev_priv->dev))
 		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
 
+	/* WaVSRefCountFullforceMissDisable|WaDSRefCountFullforceMissDisable */
+	if (IS_GEN8(dev_priv->dev))
+		reg &= ~(GEN7_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
+
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
-- 
1.8.4.2

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[PATCH 23/62] drm/i915/bdw: PPGTT init & cleanup

[Ben Widawsky]

Aside from the potential size increase of the PPGTT, the primary
difference from previous hardware is the Page Directories are no longer
carved out of the Global GTT.

Note that the PDE allocation is done as a 8MB contiguous allocation,
this needs to be eventually fixed (since driver reloading will be a
pain otherwise). Also, this will be a no-go for real PPGTT support.

v2: Move vtable initialization

v3: Resolve conflicts due to patch series reordering.

v4: Rebase on top of the address space refactoring of the PPGTT
support. Drop Imre's r-b tag for v2, too outdated by now.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h     |  19 ++++--
 drivers/gpu/drm/i915/i915_gem_gtt.c | 123 +++++++++++++++++++++++++++++++++++-
 2 files changed, 137 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83d016c..97b0905 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -572,10 +572,21 @@ struct i915_gtt {
 struct i915_hw_ppgtt {
 	struct i915_address_space base;
 	unsigned num_pd_entries;
-	struct page **pt_pages;
-	uint32_t pd_offset;
-	dma_addr_t *pt_dma_addr;
-
+	union {
+		struct page **pt_pages;
+		struct page *gen8_pt_pages;
+	};
+	struct page *pd_pages;
+	int num_pd_pages;
+	int num_pt_pages;
+	union {
+		uint32_t pd_offset;
+		dma_addr_t pd_dma_addr[4];
+	};
+	union {
+		dma_addr_t *pt_dma_addr;
+		dma_addr_t *gen8_pt_dma_addr[4];
+	};
 	int (*enable)(struct drm_device *dev);
 };
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 02de12d..4a11f51 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -31,6 +31,7 @@
 #define GEN6_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
 typedef uint64_t gen8_gtt_pte_t;
+typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 
 /* PPGTT stuff */
 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
@@ -58,6 +59,9 @@ typedef uint64_t gen8_gtt_pte_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+#define GEN8_PDES_PER_PAGE		(PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
+#define GEN8_LEGACY_PDPS		4
+
 #define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
 #define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
@@ -177,6 +181,123 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	int i, j;
+
+	for (i = 0; i < ppgtt->num_pd_pages ; i++) {
+		if (ppgtt->pd_dma_addr[i]) {
+			pci_unmap_page(ppgtt->base.dev->pdev,
+				       ppgtt->pd_dma_addr[i],
+				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+
+			for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+				dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+				if (addr)
+					pci_unmap_page(ppgtt->base.dev->pdev,
+						       addr,
+						       PAGE_SIZE,
+						       PCI_DMA_BIDIRECTIONAL);
+
+			}
+		}
+		kfree(ppgtt->gen8_pt_dma_addr[i]);
+	}
+
+	__free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages));
+	__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages));
+}
+
+/**
+ * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
+ * net effect resembling a 2-level page table in normal x86 terms. Each PDP
+ * represents 1GB of memory
+ * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
+ *
+ * TODO: Do something with the size parameter
+ **/
+static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
+{
+	struct page *pt_pages;
+	int i, j, ret = -ENOMEM;
+	const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
+	const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
+
+	if (size % (1<<30))
+		DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
+
+	/* FIXME: split allocation into smaller pieces. For now we only ever do
+	 * this once, but with full PPGTT, the multiple contiguous allocations
+	 * will be bad.
+	 */
+	ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
+	if (!ppgtt->pd_pages)
+		return -ENOMEM;
+
+	pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
+	if (!pt_pages) {
+		__free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
+		return -ENOMEM;
+	}
+
+	ppgtt->gen8_pt_pages = pt_pages;
+	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
+	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
+	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+	ppgtt->base.clear_range = NULL;
+	ppgtt->base.insert_entries = NULL;
+	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
+
+	BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
+
+	/*
+	 * - Create a mapping for the page directories.
+	 * - For each page directory:
+	 *      allocate space for page table mappings.
+	 *      map each page table
+	 */
+	for (i = 0; i < max_pdp; i++) {
+		dma_addr_t temp;
+		temp = pci_map_page(ppgtt->base.dev->pdev,
+				    &ppgtt->pd_pages[i], 0,
+				    PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+		if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+			goto err_out;
+
+		ppgtt->pd_dma_addr[i] = temp;
+
+		ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
+		if (!ppgtt->gen8_pt_dma_addr[i])
+			goto err_out;
+
+		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+			struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
+			temp = pci_map_page(ppgtt->base.dev->pdev,
+					    p, 0, PAGE_SIZE,
+					    PCI_DMA_BIDIRECTIONAL);
+
+			if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+				goto err_out;
+
+			ppgtt->gen8_pt_dma_addr[i][j] = temp;
+		}
+	}
+
+	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
+			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
+	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
+			 ppgtt->num_pt_pages,
+			 (ppgtt->num_pt_pages - num_pt_pages) +
+			 size % (1<<30));
+	return -ENOSYS; /* Not ready yet */
+
+err_out:
+	ppgtt->base.cleanup(&ppgtt->base);
+	return ret;
+}
+
 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 {
 	struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
@@ -430,7 +551,7 @@ static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 8)
 		ret = gen6_ppgtt_init(ppgtt);
 	else if (IS_GEN8(dev))
-		ret = -ENXIO;
+		ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 	else
 		BUG();
 
-- 
1.8.4.2

[PATCH 24/62] drm/i915/bdw: Initialize the PDEs

[Ben Widawsky]

The upcoming clear and insert routines will expect that PDEs all point
to valid Page Directories. Doing that lazily doesn't really buy us
anything.

The page allocation is done regardless earlier in init so it shouldn't
hurt set the PDEs.

v2: Squash in patches to implement fixed PDE write function:

- If I had done this in the first place, the bug that's going to be
  fixed in an upcoming patch would have been much easier to find.

- Use WB for PDEs.

  The PAT bit is used for page size. 2ME PDEs aren't even supported in
  BDW, so this was completely invalid. The solution is to make our
  PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess,
  this change won't matter for performance.

  Thanks to Ville for the quick correction when discussing on IRC.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4a11f51..bae71b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -80,6 +80,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static inline gen8_gtt_pte_t gen8_pde_encode(struct drm_device *dev,
+					     dma_addr_t addr,
+					     enum i915_cache_level level)
+{
+	gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+	pde |= addr;
+	if (level != I915_CACHE_NONE)
+		pde |= PPAT_CACHED_PDE_INDEX;
+	else
+		pde |= PPAT_UNCACHED_INDEX;
+	return pde;
+}
+
 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 				     enum i915_cache_level level,
 				     bool valid)
@@ -285,6 +298,20 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 		}
 	}
 
+	/* For now, the PPGTT helper functions all require that the PDEs are
+	 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
+	 * will never need to touch the PDEs again */
+	for (i = 0; i < max_pdp; i++) {
+		gen8_ppgtt_pde_t *pd_vaddr;
+		pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
+		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+			dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
+						      I915_CACHE_LLC);
+		}
+		kunmap_atomic(pd_vaddr);
+	}
+
 	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
-- 
1.8.4.2

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[PATCH 25/62] drm/i915/bdw: Implement PPGTT clear range

[Ben Widawsky]

GEN8 PPGTT range clearing is very similar to GEN6 if we assume that our
PDEs are all valid, which they should be.

v2: Rebase on top of the address space refactoring.

v3: Rebase on top of the bool use_scratch addition to the clear_range interface.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 42 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bae71b4..7097d4d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -59,6 +59,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+#define GEN8_PTES_PER_PAGE		(PAGE_SIZE / sizeof(gen8_gtt_pte_t))
 #define GEN8_PDES_PER_PAGE		(PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
 #define GEN8_LEGACY_PDPS		4
 
@@ -194,6 +195,41 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
+				   unsigned first_entry,
+				   unsigned num_entries,
+				   bool use_scratch)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	gen8_gtt_pte_t *pt_vaddr, scratch_pte;
+	unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
+	unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
+	unsigned last_pte, i;
+
+	scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
+				      I915_CACHE_LLC, use_scratch);
+
+	while (num_entries) {
+		struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
+
+		last_pte = first_pte + num_entries;
+		if (last_pte > GEN8_PTES_PER_PAGE)
+			last_pte = GEN8_PTES_PER_PAGE;
+
+		pt_vaddr = kmap_atomic(page_table);
+
+		for (i = first_pte; i < last_pte; i++)
+			pt_vaddr[i] = scratch_pte;
+
+		kunmap_atomic(pt_vaddr);
+
+		num_entries -= last_pte - first_pte;
+		first_pte = 0;
+		act_pt++;
+	}
+}
+
 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 {
 	struct i915_hw_ppgtt *ppgtt =
@@ -259,7 +295,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
-	ppgtt->base.clear_range = NULL;
+	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 	ppgtt->base.insert_entries = NULL;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 
@@ -312,6 +348,10 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 		kunmap_atomic(pd_vaddr);
 	}
 
+	ppgtt->base.clear_range(&ppgtt->base, 0,
+				ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
+				true);
+
 	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
-- 
1.8.4.2

[PATCH 26/62] drm/i915/bdw: Implement PPGTT insert

[Ben Widawsky]

GEN8 insertion is very similar to GEN6.

v2: Rebase on top of Imre's for_each_sg_page helpers.

v3: Fixup my conversion (spotted by Ville).

v4: Rebase on top of the address space refactoring.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7097d4d..27e157d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -230,6 +230,37 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 	}
 }
 
+static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
+				      struct sg_table *pages,
+				      unsigned first_entry,
+				      enum i915_cache_level cache_level)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	gen8_gtt_pte_t *pt_vaddr;
+	unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
+	unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
+	struct sg_page_iter sg_iter;
+
+	pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
+	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
+		dma_addr_t page_addr;
+
+		page_addr = sg_dma_address(sg_iter.sg) +
+				(sg_iter.sg_pgoffset << PAGE_SHIFT);
+		pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
+						    true);
+		if (++act_pte == GEN8_PTES_PER_PAGE) {
+			kunmap_atomic(pt_vaddr);
+			act_pt++;
+			pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
+			act_pte = 0;
+
+		}
+	}
+	kunmap_atomic(pt_vaddr);
+}
+
 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 {
 	struct i915_hw_ppgtt *ppgtt =
@@ -296,7 +327,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
-	ppgtt->base.insert_entries = NULL;
+	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 
 	BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
-- 
1.8.4.2

[PATCH 27/62] drm/i915/bdw: Implement PPGTT enable

[Ben Widawsky]

Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
Since all rings are using the same address space with the current code
the logic is simply to program all the tables we've setup for the PPGTT.

v2: Turn on PPGTT in GFX_MODE

v3: v2 was the wrong patch

v4: Resolve conflicts due to patch series reordering.

v5: Squash in fixup from Ben: Use LRI to write PDPs

The docs (and simulator seems to back up) suggest that we can only
program legacy PPGTT PDPs with LRI commands.

v4: Rebase around context differences conflicts.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v3)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 50 +++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 27e157d..07892e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -195,6 +195,55 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+/* Broadwell Page Directory Pointer Descriptors */
+static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
+			   uint64_t val)
+{
+	int ret;
+
+	BUG_ON(entry >= 4);
+
+	ret = intel_ring_begin(ring, 6);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, ring->mmio_base + 0x270 + (entry * 8) + 4);
+	intel_ring_emit(ring, (u32)(val >> 32));
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, ring->mmio_base + 0x270 + (entry * 8));
+	intel_ring_emit(ring, (u32)(val));
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int gen8_ppgtt_enable(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int i, j, ret;
+
+	/* bit of a hack to find the actual last used pd */
+	int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
+
+	for_each_ring(ring, dev_priv, j) {
+		I915_WRITE(RING_MODE_GEN7(ring),
+			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	}
+
+	for (i = used_pd - 1; i >= 0; i--) {
+		dma_addr_t addr = ppgtt->pd_dma_addr[i];
+		for_each_ring(ring, dev_priv, j) {
+			ret = gen8_write_pdp(ring, i, addr);
+			if (ret)
+				return ret;
+		}
+	}
+	return 0;
+}
+
 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 				   unsigned first_entry,
 				   unsigned num_entries,
@@ -326,6 +375,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+	ppgtt->enable = gen8_ppgtt_enable;
 	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
-- 
1.8.4.2

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[PATCH 28/62] drm/i915/bdw: unleash PPGTT

[Ben Widawsky]

v2: Squash in fix from Ben: Set PPGTT batches as necessary

This fixes the regression in the last couple of days when we enabled
PPGTT.

v3: Squash in fixup to still use GTT for secure batches from Ville:

BDW doesn't have a separate secure vs. non-secure bit in
MI_BATCH_BUFFER_START. So for secure batches we have to simply
leave the PPGTT bit unset. Fortunately older generations (except
HSW) had similar limitations so execbuffer already creates a GTT
mapping for all secure batches.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +--
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c    | 5 ++++-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 78786c4..885d595 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1146,8 +1146,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 
 	/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
 	 * batch" bit. Hence we need to pin secure batches into the global gtt.
-	 * hsw should have this fixed, but let's be paranoid and do it
-	 * unconditionally for now. */
+	 * hsw should have this fixed, but bdw mucks it up again. */
 	if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
 		i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 07892e2..2eaa0df 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -439,7 +439,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 			 ppgtt->num_pt_pages,
 			 (ppgtt->num_pt_pages - num_pt_pages) +
 			 size % (1<<30));
-	return -ENOSYS; /* Not ready yet */
+	return 0;
 
 err_out:
 	ppgtt->base.cleanup(&ppgtt->base);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0d56d1a5..481aa8d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1695,13 +1695,16 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			      u32 offset, u32 len,
 			      unsigned flags)
 {
+	struct drm_i915_private *dev_priv = ring->dev->dev_private;
+	bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
+		!(flags & I915_DISPATCH_SECURE);
 	int ret;
 
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		return ret;
 
-	intel_ring_emit(ring, MI_BATCH_BUFFER_START | 1);
+	intel_ring_emit(ring, MI_BATCH_BUFFER_START | (ppgtt<<8) | 1);
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
 	intel_ring_emit(ring, 0);
-- 
1.8.4.2

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[PATCH 29/62] drm/i915/bdw: Render ring flushing

[Ben Widawsky]

PIPE_CONTROL added the high address dword. I'm not sure how the
simulator let me get away with this. I've explicitly left out all the
workarounds from Gen7 because in the minimal digging that I did, most
don't seem necessary, and the simulator doesn't complain without them

Note that BLT and BSD ring commands had already been updated previously.
Just render/pipe_control should have been broken.

v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL
updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs.
PPGTT for the PIPE_CONTROL QW/DW write."

v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch
buffer object instead of an opaque ring->private where everyone stores
the same stuff inside.

Reported-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (for the fixup)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 42 +++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 481aa8d..b97d019 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -360,6 +360,47 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
 	return 0;
 }
 
+static int
+gen8_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32 invalidate_domains, u32 flush_domains)
+{
+	u32 flags = 0;
+	u32 scratch_addr = ring->scratch.gtt_offset + 128;
+	int ret;
+
+	flags |= PIPE_CONTROL_CS_STALL;
+
+	if (flush_domains) {
+		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+	}
+	if (invalidate_domains) {
+		flags |= PIPE_CONTROL_TLB_INVALIDATE;
+		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+	}
+
+	ret = intel_ring_begin(ring, 6);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+	intel_ring_emit(ring, flags);
+	intel_ring_emit(ring, scratch_addr);
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, 0);
+	intel_ring_advance(ring);
+
+	return 0;
+
+}
+
 static void ring_write_tail(struct intel_ring_buffer *ring,
 			    u32 value)
 {
@@ -1813,6 +1854,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		if (INTEL_INFO(dev)->gen == 6)
 			ring->flush = gen6_render_ring_flush;
 		if (INTEL_INFO(dev)->gen >= 8) {
+			ring->flush = gen8_render_ring_flush;
 			ring->irq_get = gen8_ring_get_irq;
 			ring->irq_put = gen8_ring_put_irq;
 		} else {
-- 
1.8.4.2

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[PATCH 30/62] drm/i915/bdw: BSD init for gen8 also

[Ben Widawsky]

This was an oversight and should have been in a previous series
somewhere.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b97d019..fd84656 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2017,7 +2017,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 	ring->id = VCS;
 
 	ring->write_tail = ring_write_tail;
-	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	if (INTEL_INFO(dev)->gen >= 6) {
 		ring->mmio_base = GEN6_BSD_RING_BASE;
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev))
-- 
1.8.4.2

[PATCH 31/62] drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails

[Ben Widawsky]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: Resolve rebase conflicts and switch to gen < 8 color for GenX
checking.

v3: Rebase on top of the address space refactoring.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2eaa0df..d9e7196 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1181,7 +1181,8 @@ void i915_gem_init_global_gtt(struct drm_device *dev)
 
 		DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 		drm_mm_takedown(&dev_priv->gtt.base.mm);
-		gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
+		if (INTEL_INFO(dev)->gen < 8)
+			gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE;
 	}
 	i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 }
-- 
1.8.4.2

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[PATCH 32/62] drm/i915/bdw: ppgtt info in debugfs

[Ben Widawsky]

It's not so much that the information is terribly useful, but rather
that the gen6/7 information is completely useless.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++++++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fa3492f..060dbf2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1646,18 +1646,37 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 	return 0;
 }
 
-static int i915_ppgtt_info(struct seq_file *m, void *data)
+static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
 {
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
-	int i, ret;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int unused, i;
 
+	if (!ppgtt)
+		return;
+
+	seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
+	seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
+	for_each_ring(ring, dev_priv, unused) {
+		seq_printf(m, "%s\n", ring->name);
+		for (i = 0; i < 4; i++) {
+			u32 offset = 0x270 + i * 8;
+			u64 pdp = I915_READ(ring->mmio_base + offset + 4);
+			pdp <<= 32;
+			pdp |= I915_READ(ring->mmio_base + offset);
+			for (i = 0; i < 4; i++)
+				seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
+		}
+	}
+}
+
+static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	int i;
 
-	ret = mutex_lock_interruptible(&dev->struct_mutex);
-	if (ret)
-		return ret;
 	if (INTEL_INFO(dev)->gen == 6)
 		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
 
@@ -1676,6 +1695,22 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
 		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
 	}
 	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
+}
+
+static int i915_ppgtt_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+
+	int ret = mutex_lock_interruptible(&dev->struct_mutex);
+	if (ret)
+		return ret;
+
+	if (INTEL_INFO(dev)->gen >= 8)
+		gen8_ppgtt_info(m, dev);
+	else if (INTEL_INFO(dev)->gen >= 6)
+		gen6_ppgtt_info(m, dev);
+
 	mutex_unlock(&dev->struct_mutex);
 
 	return 0;
-- 
1.8.4.2

[PATCH 33/62] drm/i915/bdw: add IS_BROADWELL macro

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

For now it's just equivalent to IS_GEN8, but in the future we might
want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
IS_IVYBRIDGE and IS_HASWELL).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97b0905..64a3a8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1740,6 +1740,7 @@ struct drm_i915_file_private {
 				 (dev)->pdev->device == 0x010A)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
+#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->gen == 8)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 ((dev)->pdev->device & 0xFF00) == 0x0C00)
-- 
1.8.4.2

[PATCH 34/62] drm/i915/bdw: Broadwell has 3 pipes

[Ben Widawsky]

From: Damien Lespiau <damien.lespiau@intel.com>

v2: Rebase (Paulo Zanoni)

v3: Rebase on top of num_pipes having moved to intel_device_info.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ff169e..c86d44b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -338,7 +338,7 @@ static const struct intel_device_info intel_haswell_m_info = {
 
 static const struct intel_device_info intel_broadwell_d_info = {
 	.is_preliminary = 1,
-	.gen = 8,
+	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
@@ -347,7 +347,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
 
 static const struct intel_device_info intel_broadwell_m_info = {
 	.is_preliminary = 1,
-	.gen = 8, .is_mobile = 1,
+	.gen = 8, .is_mobile = 1, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
-- 
1.8.4.2

[PATCH 35/62] drm/i915/bdw: add Broadwell sprite/plane/cursor checks

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Just make Broadwell follow the same code paths as Haswell here,
instead of running code for the even-older platforms.

v2: Shuffle around Ben's vma prep work.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 436b750..7729c88 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2176,7 +2176,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	I915_MODIFY_DISPBASE(DSPSURF(plane),
 			     i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
-	if (IS_HASWELL(dev)) {
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
 	} else {
 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@ -7198,7 +7198,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
 	if (!visible && !intel_crtc->cursor_visible)
 		return;
 
-	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		I915_WRITE(CURPOS_IVB(pipe), pos);
 		ivb_update_cursor(crtc, base);
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f8b265c..fec1e4b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -306,7 +306,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 	 * register */
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 	else if (obj->tiling_mode != I915_TILING_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
-- 
1.8.4.2

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[PATCH 36/62] drm/i915/bdw: Broadwell also has the "power down well"

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Just like Haswell, but with the small twist that the panel fitter for pipe A is
now also in the always-on power well.

v2: Use the new HAS_POWER_WELL macro.

v3: Rebase on top of intel_using_power_well patches.

v4: This time actually update the PFIT check correctly so that the
pipe A pfit is in the always-on domain.

v5: Rebase on top of the VGA power domain addition.

v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
message a bit while at it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64a3a8c..1a2e967 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -117,6 +117,10 @@ enum intel_display_power_domain {
 #define HSW_ALWAYS_ON_POWER_DOMAINS (		\
 	BIT(POWER_DOMAIN_PIPE_A) |		\
 	BIT(POWER_DOMAIN_TRANSCODER_EDP))
+#define BDW_ALWAYS_ON_POWER_DOMAINS (		\
+	BIT(POWER_DOMAIN_PIPE_A) |		\
+	BIT(POWER_DOMAIN_TRANSCODER_EDP) |	\
+	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
 
 enum hpd_pin {
 	HPD_NONE = 0,
@@ -1802,7 +1806,7 @@ struct drm_i915_file_private {
 #define HAS_IPS(dev)		(IS_ULT(dev))
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
-#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
+#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(IS_HASWELL(dev))
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 81ec2c3..caf31b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5524,7 +5524,9 @@ static bool is_always_on_power_domain(struct drm_device *dev,
 
 	BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
 
-	if (IS_HASWELL(dev)) {
+	if (IS_GEN8(dev)) {
+		always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
+	} else if (IS_HASWELL(dev)) {
 		always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
 	} else {
 		WARN_ON(1);
@@ -6010,4 +6012,3 @@ void intel_pm_init(struct drm_device *dev)
 	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
 			  intel_gen6_powersave_work);
 }
-
-- 
1.8.4.2

[PATCH 37/62] drm/i915/bdw: pretend we have LPT LP on Broadwell

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The platforms we currently have all have LPT LP on them. As such, we
have no way to identify the new WPT PCH that will ship with Broadwell.

NOTE: For all purposes relevant to the driver that this point, LPT and
WPT are equivalent. Therefore there should be no need to actually change
this for some time.

v2: Don't assign dev_priv->num_pch_pll any more.

v3: Rebase on top of the PCH detection changes for virtualized
enviroments.

v4 (Ben): Wrote commit message

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c86d44b..590d999 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -453,6 +453,12 @@ void intel_detect_pch(struct drm_device *dev)
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(!IS_ULT(dev));
+			} else if (IS_BROADWELL(dev)) {
+				dev_priv->pch_type = PCH_LPT;
+				dev_priv->pch_id =
+					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
+				DRM_DEBUG_KMS("This is Broadwell, assuming "
+					      "LynxPoint LP PCH\n");
 			} else {
 				goto check_next;
 			}
-- 
1.8.4.2

[PATCH 38/62] drm/i915/bdw: get the correct LCPLL frequency on Broadwell

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

v2: Rebased onto Paulo's MHz->kHz change.

v3: Rebased on top of the Haswell pc8+ adjustements.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++++++-------
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68b877d..d5995dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5282,6 +5282,9 @@
 #define  LCPLL_PLL_LOCK			(1<<30)
 #define  LCPLL_CLK_FREQ_MASK		(3<<26)
 #define  LCPLL_CLK_FREQ_450		(0<<26)
+#define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
+#define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
+#define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
 #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
 #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 31f4fe2..d464fd2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1156,18 +1156,29 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 
 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
 	uint32_t lcpll = I915_READ(LCPLL_CTL);
+	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 
-	if (lcpll & LCPLL_CD_SOURCE_FCLK)
+	if (lcpll & LCPLL_CD_SOURCE_FCLK) {
 		return 800000;
-	else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
+	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
 		return 450000;
-	else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
+	} else if (freq == LCPLL_CLK_FREQ_450) {
 		return 450000;
-	else if (IS_ULT(dev_priv->dev))
-		return 337500;
-	else
-		return 540000;
+	} else if (IS_HASWELL(dev)) {
+		if (IS_ULT(dev))
+			return 338000;
+		else
+			return 540000;
+	} else {
+		if (freq == LCPLL_CLK_FREQ_54O_BDW)
+			return 540000;
+		else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
+			return 338000;
+		else
+			return 675000;
+	}
 }
 
 void intel_ddi_pll_init(struct drm_device *dev)
-- 
1.8.4.2

[PATCH 39/62] drm/i915/bdw: on Broadwell, the panel fitter is on the pipe

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So you can use the panel fitter while the power well is disabled and
you also don't need to set the "pipe" bit.

v2: Rebased on top of Jesse's pfit refactor, which moved pfit state
into the pipe_config.

v3: Rebase on top of the latest Haswell/panel fitter rework, which
neatly resolves a FIXME we have in this patch here:

v4: Rebase on top of the new power domain framework.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d464fd2..db848a9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -756,7 +756,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 	struct drm_encoder *encoder = &intel_encoder->base;
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe = intel_crtc->pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
@@ -792,10 +793,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 	if (cpu_transcoder == TRANSCODER_EDP) {
 		switch (pipe) {
 		case PIPE_A:
-			/* Can only use the always-on power well for eDP when
-			 * not using the panel fitter, and when not using motion
-			  * blur mitigation (which we don't support). */
-			if (intel_crtc->config.pch_pfit.enabled)
+			/* On Haswell, can only use the always-on power well for
+			 * eDP when not using the panel fitter, and when not
+			 * using motion blur mitigation (which we don't
+			 * support). */
+			if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
 				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 			else
 				temp |= TRANS_DDI_EDP_INPUT_A_ON;
-- 
1.8.4.2

[PATCH 40/62] drm/i915/bdw: Broadwell has PIPEMISC

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
on previous gens).

v2: Rebase on to of the pipe config bpp handling rework.

v3: Rebased on top of the pipe_config->dither refactoring.

v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
now also build up PIPECONF completely ourselves - keeping around
random stuff set by the BIOS just isn't a good idea. I've checked BDW
BSpec and we already set all relevant bits.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h      | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++--
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5995dd..4131223 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3224,6 +3224,18 @@
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
+#define _PIPE_MISC_A			0x70030
+#define _PIPE_MISC_B			0x71030
+#define   PIPEMISC_DITHER_BPC_MASK	(7<<5)
+#define   PIPEMISC_DITHER_8_BPC		(0<<5)
+#define   PIPEMISC_DITHER_10_BPC	(1<<5)
+#define   PIPEMISC_DITHER_6_BPC		(2<<5)
+#define   PIPEMISC_DITHER_12_BPC	(3<<5)
+#define   PIPEMISC_DITHER_ENABLE	(1<<4)
+#define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
+#define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
+#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
+
 #define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
 #define   PIPEB_HLINE_INT_EN			(1<<28)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7729c88..134ae66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5772,14 +5772,16 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
 
 static void haswell_set_pipeconf(struct drm_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 	uint32_t val;
 
 	val = 0;
 
-	if (intel_crtc->config.dither)
+	if (IS_HASWELL(dev) && intel_crtc->config.dither)
 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
 	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
@@ -5792,6 +5794,33 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
 
 	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
+
+	if (IS_BROADWELL(dev)) {
+		val = 0;
+
+		switch (intel_crtc->config.pipe_bpp) {
+		case 18:
+			val |= PIPEMISC_DITHER_6_BPC;
+			break;
+		case 24:
+			val |= PIPEMISC_DITHER_8_BPC;
+			break;
+		case 30:
+			val |= PIPEMISC_DITHER_10_BPC;
+			break;
+		case 36:
+			val |= PIPEMISC_DITHER_12_BPC;
+			break;
+		default:
+			/* Case prevented by pipe_config_set_bpp. */
+			BUG();
+		}
+
+		if (intel_crtc->config.dither)
+			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
+
+		I915_WRITE(PIPEMISC(pipe), val);
+	}
 }
 
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
-- 
1.8.4.2

[PATCH 41/62] drm/i915/bdw: Use pipe CSC on Broadwell

[Ben Widawsky]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Route cursor and sprite data through the pipe CSC unit on BDW.
Primary plane data is already sent through the pipe CSC.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 134ae66..193ce3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7171,7 +7171,7 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
 			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
 			cntl |= CURSOR_MODE_DISABLE;
 		}
-		if (IS_HASWELL(dev)) {
+		if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 			cntl |= CURSOR_PIPE_CSC_ENABLE;
 			cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
 		}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index fec1e4b..b63135b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -267,7 +267,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	sprctl |= SPRITE_ENABLE;
 
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
 	intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
-- 
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority

[Ben Widawsky]

GEN8 also needs this workaround.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index caf31b7..68dc363 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5192,6 +5192,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
+
+	/* WaSwitchSolVfFArbitrationPriority */
+	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)
-- 
1.8.4.2

[PATCH 43/62] drm/i915/bdw: Add BDW DDI buffer translation values

[Ben Widawsky]

From: Art Runyan <arthur.j.runyan@intel.com>

Many of the DDI buffer translation values have changed for BDW.
Add new translation tables and selection between HSW and BDW.

v2: s/BUG/WARN/ to avoid breaking future GENs.

v3: Rebase on top of the hdmi translation table changes.

Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c | 52 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db848a9..4baf3cd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -72,6 +72,32 @@ static const u32 hsw_ddi_translations_hdmi[] = {
 	0x80FFFFFF, 0x00030002, /* 11:	1000		1000		0   */
 };
 
+static const u32 bdw_ddi_translations_dp[] = {
+	0x00FFFFFF, 0x0007000E,		/* DP parameters */
+	0x00D75FFF, 0x000E000A,
+	0x00BEFFFF, 0x00140006,
+	0x00FFFFFF, 0x000E000A,
+	0x00D75FFF, 0x00180004,
+	0x80CB2FFF, 0x001B0002,
+	0x00F7DFFF, 0x00180004,
+	0x80D75FFF, 0x001B0002,
+	0x80FFFFFF, 0x001B0002,
+	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
+
+static const u32 bdw_ddi_translations_fdi[] = {
+	0x00FFFFFF, 0x0001000E,		/* FDI parameters */
+	0x00D75FFF, 0x0004000A,
+	0x00C30FFF, 0x00070006,
+	0x00AAAFFF, 0x000C0000,
+	0x00FFFFFF, 0x0004000A,
+	0x00D75FFF, 0x00090004,
+	0x00C30FFF, 0x000C0000,
+	0x00FFFFFF, 0x00070006,
+	0x00D75FFF, 0x000C0000,
+	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
+
 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
@@ -92,8 +118,8 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 	}
 }
 
-/* On Haswell, DDI port buffers must be programmed with correct values
- * in advance. The buffer values are different for FDI and DP modes,
+/* Starting with Haswell, DDI port buffers must be programmed with correct
+ * values in advance. The buffer values are different for FDI and DP modes,
  * but the HDMI/DVI fields are shared among those. So we program the DDI
  * in either FDI or DP modes only, as HDMI connections will work with both
  * of those
@@ -103,10 +129,26 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg;
 	int i;
-	const u32 *ddi_translations = (port == PORT_E) ?
-		hsw_ddi_translations_fdi :
-		hsw_ddi_translations_dp;
 	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
+	const u32 *ddi_translations_fdi;
+	const u32 *ddi_translations_dp;
+	const u32 *ddi_translations;
+
+	if (IS_BROADWELL(dev)) {
+		ddi_translations_fdi = bdw_ddi_translations_fdi;
+		ddi_translations_dp = bdw_ddi_translations_dp;
+	} else if (IS_HASWELL(dev)) {
+		ddi_translations_fdi = hsw_ddi_translations_fdi;
+		ddi_translations_dp = hsw_ddi_translations_dp;
+	} else {
+		WARN(1, "ddi translation table missing\n");
+		ddi_translations_fdi = bdw_ddi_translations_fdi;
+		ddi_translations_dp = bdw_ddi_translations_dp;
+	}
+
+	ddi_translations = ((port == PORT_E) ?
+		ddi_translations_fdi :
+		ddi_translations_dp);
 
 	for (i = 0, reg = DDI_BUF_TRANS(port);
 	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
-- 
1.8.4.2

[PATCH 44/62] drm/i915/bdw: add BDW DDI buf translations for eDP

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Broadwell has different DDI buffer translations for eDP and DP, so add
support for the missing eDP and keep Haswell the same.

A future patch addresses the suggestion from Art to check for eDP on
port D and use the eDP values there, too.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 38 +++++++++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4baf3cd..3868ed9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -72,6 +72,19 @@ static const u32 hsw_ddi_translations_hdmi[] = {
 	0x80FFFFFF, 0x00030002, /* 11:	1000		1000		0   */
 };
 
+static const u32 bdw_ddi_translations_edp[] = {
+	0x00FFFFFF, 0x00000012,		/* DP parameters */
+	0x00EBAFFF, 0x00020011,
+	0x00C71FFF, 0x0006000F,
+	0x00FFFFFF, 0x00020011,
+	0x00DB6FFF, 0x0005000F,
+	0x00BEEFFF, 0x000A000C,
+	0x00FFFFFF, 0x0005000F,
+	0x00DB6FFF, 0x000A000C,
+	0x00FFFFFF, 0x000A000C,
+	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
+};
+
 static const u32 bdw_ddi_translations_dp[] = {
 	0x00FFFFFF, 0x0007000E,		/* DP parameters */
 	0x00D75FFF, 0x000E000A,
@@ -132,26 +145,41 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 	const u32 *ddi_translations_fdi;
 	const u32 *ddi_translations_dp;
+	const u32 *ddi_translations_edp;
 	const u32 *ddi_translations;
 
 	if (IS_BROADWELL(dev)) {
 		ddi_translations_fdi = bdw_ddi_translations_fdi;
 		ddi_translations_dp = bdw_ddi_translations_dp;
+		ddi_translations_edp = bdw_ddi_translations_edp;
 	} else if (IS_HASWELL(dev)) {
 		ddi_translations_fdi = hsw_ddi_translations_fdi;
 		ddi_translations_dp = hsw_ddi_translations_dp;
+		ddi_translations_edp = hsw_ddi_translations_dp;
 	} else {
 		WARN(1, "ddi translation table missing\n");
+		ddi_translations_edp = bdw_ddi_translations_dp;
 		ddi_translations_fdi = bdw_ddi_translations_fdi;
 		ddi_translations_dp = bdw_ddi_translations_dp;
 	}
 
-	ddi_translations = ((port == PORT_E) ?
-		ddi_translations_fdi :
-		ddi_translations_dp);
+	switch (port) {
+	case PORT_A:
+		ddi_translations = ddi_translations_edp;
+		break;
+	case PORT_B:
+	case PORT_C:
+	case PORT_D:
+		ddi_translations = ddi_translations_dp;
+		break;
+	case PORT_E:
+		ddi_translations = ddi_translations_fdi;
+		break;
+	default:
+		BUG();
+	}
 
-	for (i = 0, reg = DDI_BUF_TRANS(port);
-	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+	for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 		I915_WRITE(reg, ddi_translations[i]);
 		reg += 4;
 	}
-- 
1.8.4.2

[PATCH 45/62] drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

They're not the same as the Haswell ones.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++
 drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++---
 2 files changed, 63 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4131223..6f834b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5176,6 +5176,7 @@
 #define DDI_BUF_CTL_B				0x64100
 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1<<31)
+/* Haswell */
 #define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
 #define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
 #define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
@@ -5185,6 +5186,16 @@
 #define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
 #define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
 #define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
+/* Broadwell */
+#define  DDI_BUF_EMP_400MV_0DB_BDW		(0<<24)   /* Sel0 */
+#define  DDI_BUF_EMP_400MV_3_5DB_BDW		(1<<24)   /* Sel1 */
+#define  DDI_BUF_EMP_400MV_6DB_BDW		(2<<24)   /* Sel2 */
+#define  DDI_BUF_EMP_600MV_0DB_BDW		(3<<24)   /* Sel3 */
+#define  DDI_BUF_EMP_600MV_3_5DB_BDW		(4<<24)   /* Sel4 */
+#define  DDI_BUF_EMP_600MV_6DB_BDW		(5<<24)   /* Sel5 */
+#define  DDI_BUF_EMP_800MV_0DB_BDW		(6<<24)   /* Sel6 */
+#define  DDI_BUF_EMP_800MV_3_5DB_BDW		(7<<24)   /* Sel7 */
+#define  DDI_BUF_EMP_1200MV_0DB_BDW		(8<<24)   /* Sel8 */
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
 #define  DDI_BUF_PORT_REVERSAL			(1<<16)
 #define  DDI_BUF_IS_IDLE			(1<<7)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b3cc333..7725f81 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1950,7 +1950,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	enum port port = dp_to_dig_port(intel_dp)->port;
 
-	if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
 		return DP_TRAIN_VOLTAGE_SWING_1200;
 	else if (IS_GEN7(dev) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_800;
@@ -1966,7 +1966,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	enum port port = dp_to_dig_port(intel_dp)->port;
 
-	if (HAS_DDI(dev)) {
+	if (IS_BROADWELL(dev)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
+		}
+	} else if (IS_HASWELL(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_9_5;
@@ -2278,6 +2289,41 @@ intel_hsw_signal_levels(uint8_t train_set)
 	}
 }
 
+static uint32_t
+intel_bdw_signal_levels(uint8_t train_set)
+{
+	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	switch (signal_levels) {
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_400MV_3_5DB_BDW;	/* Sel1 */
+	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+		return DDI_BUF_EMP_400MV_6DB_BDW;	/* Sel2 */
+
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_600MV_0DB_BDW;	/* Sel3 */
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_600MV_3_5DB_BDW;	/* Sel4 */
+	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
+		return DDI_BUF_EMP_600MV_6DB_BDW;	/* Sel5 */
+
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_800MV_0DB_BDW;	/* Sel6 */
+	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+		return DDI_BUF_EMP_800MV_3_5DB_BDW;	/* Sel7 */
+
+	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
+		return DDI_BUF_EMP_1200MV_0DB_BDW;	/* Sel8 */
+
+	default:
+		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
+			      "0x%x\n", signal_levels);
+		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
+	}
+}
+
 /* Properly updates "DP" with the correct signal levels. */
 static void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
@@ -2288,7 +2334,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 	uint32_t signal_levels, mask;
 	uint8_t train_set = intel_dp->train_set[0];
 
-	if (HAS_DDI(dev)) {
+	if (IS_BROADWELL(dev)) {
+		signal_levels = intel_bdw_signal_levels(train_set);
+		mask = DDI_BUF_EMP_MASK;
+	} else if (IS_HASWELL(dev)) {
 		signal_levels = intel_hsw_signal_levels(train_set);
 		mask = DDI_BUF_EMP_MASK;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.8.4.2

[PATCH 46/62] drm/i915/bdw: BDW also has only 2 FDI lanes

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So treat it like Haswell.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 193ce3d..fce3b0d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4198,7 +4198,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
 		return false;
 	}
 
-	if (IS_HASWELL(dev)) {
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		if (pipe_config->fdi_lanes > 2) {
 			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
 				      pipe_config->fdi_lanes);
-- 
1.8.4.2

[PATCH 47/62] drm/i915/bdw: check DPD on port D when setting the DDI buffers

[Ben Widawsky]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Use the eDP values on platforms where port D is eDP. This doesn't
affect Haswell since it uses the same DDI buffer values for eDP and
DP.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3868ed9..a4ddc7f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -169,9 +169,14 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 		break;
 	case PORT_B:
 	case PORT_C:
-	case PORT_D:
 		ddi_translations = ddi_translations_dp;
 		break;
+	case PORT_D:
+		if (intel_dpd_is_edp(dev))
+			ddi_translations = ddi_translations_edp;
+		else
+			ddi_translations = ddi_translations_dp;
+		break;
 	case PORT_E:
 		ddi_translations = ddi_translations_fdi;
 		break;
-- 
1.8.4.2

[PATCH 48/62] drm/i915/bdw: Add Broadwell display FIFO limits

[Ben Widawsky]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Broadwell has bigger display FIFOs than Haswell. Otherwise the
two are very similar.

v2: Fix FBC WM_LP shift for BDW

v3: Rebase on top of the big Haswell wm rework.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 33 ++++++++++++++++++++++++---------
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f834b3..2a65f92 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3366,6 +3366,7 @@
 #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
 #define  WM1_LP_FBC_MASK	(0xf<<20)
 #define  WM1_LP_FBC_SHIFT	20
+#define  WM1_LP_FBC_SHIFT_BDW	19
 #define  WM1_LP_SR_MASK		(0x7ff<<8)
 #define  WM1_LP_SR_SHIFT	8
 #define  WM1_LP_CURSOR_MASK	(0xff)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 68dc363..6d14182 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2291,7 +2291,9 @@ static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
 
 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
 {
-	if (INTEL_INFO(dev)->gen >= 7)
+	if (INTEL_INFO(dev)->gen >= 8)
+		return 3072;
+	else if (INTEL_INFO(dev)->gen >= 7)
 		return 768;
 	else
 		return 512;
@@ -2336,7 +2338,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 	}
 
 	/* clamp to max that the registers can hold */
-	if (INTEL_INFO(dev)->gen >= 7)
+	if (INTEL_INFO(dev)->gen >= 8)
+		max = level == 0 ? 255 : 2047;
+	else if (INTEL_INFO(dev)->gen >= 7)
 		/* IVB/HSW primary/sprite plane watermarks */
 		max = level == 0 ? 127 : 1023;
 	else if (!is_sprite)
@@ -2366,10 +2370,13 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
 }
 
 /* Calculate the maximum FBC watermark */
-static unsigned int ilk_fbc_wm_max(void)
+static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
 {
 	/* max that registers can hold */
-	return 15;
+	if (INTEL_INFO(dev)->gen >= 8)
+		return 31;
+	else
+		return 15;
 }
 
 static void ilk_compute_wm_maximums(struct drm_device *dev,
@@ -2381,7 +2388,7 @@ static void ilk_compute_wm_maximums(struct drm_device *dev,
 	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
 	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
 	max->cur = ilk_cursor_wm_max(dev, level, config);
-	max->fbc = ilk_fbc_wm_max();
+	max->fbc = ilk_fbc_wm_max(dev);
 }
 
 static bool ilk_validate_wm_level(int level,
@@ -2722,10 +2729,18 @@ static void hsw_compute_wm_results(struct drm_device *dev,
 		if (!r->enable)
 			break;
 
-		results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
-							  r->fbc_val,
-							  r->pri_val,
-							  r->cur_val);
+		results->wm_lp[wm_lp - 1] = WM3_LP_EN |
+			((level * 2) << WM1_LP_LATENCY_SHIFT) |
+			(r->pri_val << WM1_LP_SR_SHIFT) |
+			r->cur_val;
+
+		if (INTEL_INFO(dev)->gen >= 8)
+			results->wm_lp[wm_lp - 1] |=
+				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
+		else
+			results->wm_lp[wm_lp - 1] |=
+				r->fbc_val << WM1_LP_FBC_SHIFT;
+
 		results->wm_lp_spr[wm_lp - 1] = r->spr_val;
 	}
 
-- 
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 49/62] drm/i915/bdw: Use The GT mailbox for IPS enable/disable

[Ben Widawsky]

v2: Squash in fixup from Ben to synchronize the GT mailbox commands.

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++----------
 3 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a2e967..f222eb4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1803,7 +1803,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
-#define HAS_IPS(dev)		(IS_ULT(dev))
+#define HAS_IPS(dev)		(IS_ULT(dev) || IS_BROADWELL(dev))
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a65f92..65f9631 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4932,6 +4932,7 @@
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   DISPLAY_IPS_CONTROL			0x19
 #define GEN6_PCODE_DATA				0x138128
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fce3b0d..fc4b4cf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3347,15 +3347,26 @@ void hsw_enable_ips(struct intel_crtc *crtc)
 	 * only after intel_enable_plane. And intel_enable_plane already waits
 	 * for a vblank, so all we need to do here is to enable the IPS bit. */
 	assert_plane_enabled(dev_priv, crtc->plane);
-	I915_WRITE(IPS_CTL, IPS_ENABLE);
-
-	/* The bit only becomes 1 in the next vblank, so this wait here is
-	 * essentially intel_wait_for_vblank. If we don't have this and don't
-	 * wait for vblanks until the end of crtc_enable, then the HW state
-	 * readout code will complain that the expected IPS_CTL value is not the
-	 * one we read. */
-	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
-		DRM_ERROR("Timed out waiting for IPS enable\n");
+	if (IS_BROADWELL(crtc->base.dev)) {
+		mutex_lock(&dev_priv->rps.hw_lock);
+		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		/* Quoting Art Runyan: "its not safe to expect any particular
+		 * value in IPS_CTL bit 31 after enabling IPS through the
+		 * mailbox." Therefore we need to defer waiting on the state
+		 * change.
+		 * TODO: need to fix this for state checker
+		 */
+	} else {
+		I915_WRITE(IPS_CTL, IPS_ENABLE);
+		/* The bit only becomes 1 in the next vblank, so this wait here
+		 * is essentially intel_wait_for_vblank. If we don't have this
+		 * and don't wait for vblanks until the end of crtc_enable, then
+		 * the HW state readout code will complain that the expected
+		 * IPS_CTL value is not the one we read. */
+		if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
+			DRM_ERROR("Timed out waiting for IPS enable\n");
+	}
 }
 
 void hsw_disable_ips(struct intel_crtc *crtc)
@@ -3367,7 +3378,12 @@ void hsw_disable_ips(struct intel_crtc *crtc)
 		return;
 
 	assert_plane_enabled(dev_priv, crtc->plane);
-	I915_WRITE(IPS_CTL, 0);
+	if (IS_BROADWELL(crtc->base.dev)) {
+		mutex_lock(&dev_priv->rps.hw_lock);
+		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else
+		I915_WRITE(IPS_CTL, 0);
 	POSTING_READ(IPS_CTL);
 
 	/* We need to wait for a vblank before we can disable the plane. */
-- 
1.8.4.2

[PATCH 50/62] drm/i915/bdw: Support eDP PSR

[Ben Widawsky]

Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.

Note that Broadwell provides additional PSR support. This is not
addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f222eb4..dc79a0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev))
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65f9631..f97836e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1956,8 +1956,8 @@
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
-/* HSW eDP PSR registers */
-#define EDP_PSR_BASE(dev)			0x64800
+/* HSW+ eDP PSR registers */
+#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
 #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   EDP_PSR_LINK_DISABLE			(0<<27)
-- 
1.8.4.2

[PATCH 51/62] drm/i915/bdw: Use HSW formula for ring freq scaling

[Ben Widawsky]

The current formula we use for HSW is not what is in current docs.
However, changing to the HSW formula on my HSW does not improve power
usage, and decreases performance by about 5% in limited xonotic testing.

For gen8, until we know otherwise, or run experiments, let's use
the HSW formula - which should be the same used in the Windows driver
(and thus help make an apples-applies comparison) on gen8.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6d14182..3dd30f7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3924,7 +3924,10 @@ void gen6_update_ring_freq(struct drm_device *dev)
 		int diff = dev_priv->rps.max_delay - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (IS_HASWELL(dev)) {
+		if (INTEL_INFO(dev)->gen > 7) {
+			/* max(2 * GT, DDR). NB: GT is 50MHz units */
+			ring_freq = max(min_ring_freq, gpu_freq);
+		} else if (IS_HASWELL(dev)) {
 			ring_freq = mult_frac(gpu_freq, 5, 4);
 			ring_freq = max(min_ring_freq, ring_freq);
 			/* leave ia_freq as the default, chosen by cpufreq */
-- 
1.8.4.2

[PATCH 52/62] drm/i915/bdw: Don't wait for c0 threads on forcewake

[Ben Widawsky]

It's no longer a required workaround on BDW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Move compile fix from a later patch to this one.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index fa06ce4..727cf30 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -112,7 +112,8 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 
 	/* WaRsForcewakeWaitTC0:ivb,hsw */
-	__gen6_gt_wait_for_thread_c0(dev_priv);
+	if (INTEL_INFO(dev_priv->dev)->gen < 8)
+		__gen6_gt_wait_for_thread_c0(dev_priv);
 }
 
 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
-- 
1.8.4.2

[PATCH 53/62] drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI

[Ben Widawsky]

From: Damien Lespiau <damien.lespiau@intel.com>

Just like HSW.

This means we can scan out a mode with a 300Mhz pixel clock with a depth
of 24 bits, but only a 200Mhz one with a 36bits depth.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 51a8336..03f9ca7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -847,7 +847,7 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
 
 	if (IS_G4X(dev))
 		return 165000;
-	else if (IS_HASWELL(dev))
+	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 		return 300000;
 	else
 		return 225000;
-- 
1.8.4.2

[PATCH 54/62] drm/i915/bdw: Create a separate BDW rps enable

[Ben Widawsky]

This is mostly what we have for HSW with the exceptions of:
no writes:
  GEN6_RC1_WAKE_RATE_LIMIT
  GEN6_RC6pp_WAKE_RATE_LIMIT
  GEN6_RC1e_THRESHOLD
  GEN6_RC6p_THRESHOLD
  GEN6_RC6pp_THRESHOLD

GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s

Don't try to overclock, or program ring/IA frequency tables since we
don't quite have sufficient docs yet.

NOTE: These values do not reflect the changes made recently by Chris.
Since we have no evidence yet what the proper way to tweak for this
platform is, I think it is good to go, and can be optimized by Chris, or
whomever, later.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Drop spurious hunk and drop TODO - having per-platform rps
register frobbing code is in my opinion preferred, now that all the
infrastructure functions are extracted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_pm.c | 75 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3dd30f7..0245985 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3762,6 +3762,78 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
 	I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
 }
 
+static void gen8_enable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	uint32_t rc6_mask = 0, rp_state_cap;
+	int unused;
+
+	/* 1a: Software RC state - RC0 */
+	I915_WRITE(GEN6_RC_STATE, 0);
+
+	/* 1c & 1d: Get forcewake during program sequence. Although the driver
+	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+	gen6_gt_force_wake_get(dev_priv);
+
+	/* 2a: Disable RC states. */
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+
+	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+
+	/* 2b: Program RC6 thresholds.*/
+	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+	for_each_ring(ring, dev_priv, unused)
+		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+	I915_WRITE(GEN6_RC_SLEEP, 0);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
+	/* 3: Enable RC6 */
+	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
+	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
+	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+			GEN6_RC_CTL_EI_MODE(1) |
+			rc6_mask);
+
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
+	I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
+	/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
+
+	/* Docs recommend 900MHz, and 300 MHz respectively */
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
+		   dev_priv->rps.max_delay << 24 |
+		   dev_priv->rps.min_delay << 16);
+
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
+	I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_TURBO |
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	/* 6: Ring frequency + overclocking (our driver does this later */
+
+	gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
+
+	gen6_enable_rps_interrupts(dev);
+
+	gen6_gt_force_wake_put(dev_priv);
+}
+
 static void gen6_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4891,6 +4963,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 
 	if (IS_VALLEYVIEW(dev)) {
 		valleyview_enable_rps(dev);
+	} else if (IS_BROADWELL(dev)) {
+		gen8_enable_rps(dev);
+		gen6_update_ring_freq(dev);
 	} else {
 		gen6_enable_rps(dev);
 		gen6_update_ring_freq(dev);
-- 
1.8.4.2

[PATCH 55/62] drm/i915/bdw: Disable semaphores

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

We've done insufficient testing on them thus far, so keep them disabled
until we do test.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 590d999..efb63b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -478,6 +478,12 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 6)
 		return 0;
 
+	/* Until we get further testing... */
+	if (IS_GEN8(dev)) {
+		DRM_INFO("Semaphores disabled GEN8\n");
+		return 0;
+	}
+
 	if (i915_semaphores >= 0)
 		return i915_semaphores;
 
-- 
1.8.4.2

[PATCH 56/62] drm/i915/bdw: Implement edp PSR workarounds

[Ben Widawsky]

This implements a workaround for PSR dealing with some vblank issue.

WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD

v2: forgot to git add bogus whitespace fix

v3: Update with workaround names.
Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)

Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
 drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f97836e..9608f96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4092,8 +4092,14 @@
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
 
 #define CHICKEN_PAR1_1		0x42080
+#define  DPA_MASK_VBLANK_SRD	(1 << 15)
 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
 
+#define _CHICKEN_PIPESL_1_A	0x420b0
+#define _CHICKEN_PIPESL_1_B	0x420b4
+#define  DPRS_MASK_VBLANK_SRD	(1 << 0)
+#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+
 #define DISP_ARB_CTL	0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0245985..63f6e59 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5288,6 +5288,23 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 
 	/* WaSwitchSolVfFArbitrationPriority */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+
+	if (IS_BROADWELL(dev)) {
+		enum pipe i;
+
+		/* WaPsrDPAMaskVBlankInSRD */
+		I915_WRITE(CHICKEN_PAR1_1,
+			   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
+
+		/* WaPsrDPRSUnmaskVBlankInSRD */
+		for_each_pipe(i) {
+			I915_WRITE(CHICKEN_PIPESL_1(i),
+				   I915_READ(CHICKEN_PIPESL_1(i) |
+					     DPRS_MASK_VBLANK_SRD));
+		}
+	}
+
+
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)
-- 
1.8.4.2

[PATCH 57/62] drm/i915/bdw: BWGTLB clock gate disable

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

Wa???

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9608f96..2d16363 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -656,6 +656,7 @@
 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
 #define GAMTARBMODE		0x04a08
+#define   ARB_MODE_BWGTLB_DISABLE (1<<9)
 #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
 #define RENDER_HWS_PGA_GEN7	(0x04080)
 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 63f6e59..e6e12e1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 
+	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
+
 	/* WaSwitchSolVfFArbitrationPriority */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
-- 
1.8.4.2

[PATCH 58/62] drm/i915/bdw: Disable centroid pixel perf optimization

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

BDW-A workaround

BDW Bug #1899532

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d16363..8080a4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4986,6 +4986,9 @@
 #define HSW_ROW_CHICKEN3		0xe49c
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
+#define HALF_SLICE_CHICKEN3		0xe184
+#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
+
 #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
 #define INTEL_AUDIO_DEVCL		0x808629FB
 #define INTEL_AUDIO_DEVBLC		0x80862801
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6e12e1..dd0d375 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 
+	I915_WRITE(HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
 	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
 	/* WaSwitchSolVfFArbitrationPriority */
-- 
1.8.4.2

[PATCH 59/62] drm/i915/bdw: Sampler power bypass disable

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

BDW-A workaround.

BDW Bug #1899812

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8080a4d..3ae3751 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4988,6 +4988,7 @@
 
 #define HALF_SLICE_CHICKEN3		0xe184
 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
+#define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
 
 #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
 #define INTEL_AUDIO_DEVCL		0x808629FB
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd0d375..48ffe54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5288,6 +5288,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(HALF_SLICE_CHICKEN3,
 		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
+	I915_WRITE(HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
 	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
 	/* WaSwitchSolVfFArbitrationPriority */
-- 
1.8.4.2

[PATCH 60/62] drm/i915/bdw: Limit SDE poly depth FIFO to 2

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

BDW-A workaround

BDW Bug #1899155

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ae3751..9d194b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -777,6 +777,7 @@
 #define _3D_CHICKEN3	0x02090
 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
+#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1)
 
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 48ffe54..b3d709c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5292,6 +5292,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
 	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
+	I915_WRITE(_3D_CHICKEN3,
+		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
+
 	/* WaSwitchSolVfFArbitrationPriority */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
-- 
1.8.4.2

[PATCH 61/62] drm/i915/bdw: conservative SBE VUE cache mode

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

Hold vertex data in cache until last reference

BDW-A workaround

? BUG

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d194b6..1c40fc4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4112,6 +4112,8 @@
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
+#define COMMON_SLICE_CHICKEN2			0x7014
+# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3d709c..0602ace 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5295,6 +5295,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(_3D_CHICKEN3,
 		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
 
+	I915_WRITE(COMMON_SLICE_CHICKEN2,
+		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
+
 	/* WaSwitchSolVfFArbitrationPriority */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
-- 
1.8.4.2

[PATCH 62/62] drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

Implement WaSingleSubspanDispatchOnAALinesAndPoints

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c40fc4..1659ff6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4980,6 +4980,7 @@
 #define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
 #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
 #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
+#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
 
 #define GEN7_ROW_CHICKEN2		0xe4f4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0602ace..dd39c9f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5298,6 +5298,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(COMMON_SLICE_CHICKEN2,
 		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
 
+	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+		   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
+
 	/* WaSwitchSolVfFArbitrationPriority */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
-- 
1.8.4.2

Re: [PATCH 00/62] Broadwell kernel driver support

[Daniel Vetter]

On Sat, Nov 02, 2013 at 09:06:58PM -0700, Ben Widawsky wrote:
> It is my honor and privilege to submit basic Broadwell support on behalf
> of Intel.
> 
> The patch series includes support for Broadwell which should bring it up
> to feature parity with Haswell. As you'll note, the patches have
> received some revisions and review already. This is due to our new
> process (more on this below). We will be rolling out the new Broadwell
> goodness over time.
> 
> Broadwell represents the next generation (GEN8) in Intel graphics
> processing hardware. Broadwell graphics bring some of the biggest
> changes we've seen on the execution and memory management side of the
> GPU. (There are equally large and exciting changes for the userspace
> drivers.)
> 
> My request to reviewers is: I haven't touched these much at all since
> submitting to the internal mailing list. Most changes are due to rebase.
> Try to keep bikesheds to a minimum. We want to try to get this code in
> the 3.13 kernel, so we have a nice base to actually stabilize and
> improve features for the 3.14 release. Remember, we have that handy
> 'preliminary hardware support' to allow people to opt-in to this early
> enabling code. So I'm shooting for stable "end-userable" BDW code in
> 3.14.
> 
> Note that the last few workarounds likely won't be needed, but I think
> we can include them until we know for sure otherwise.
> 
> Aside from the usual set of things we need to update when simply
> enabling a new platform, What follows are some of the major changes from
> HSW->BDW:
> 
> * There is no longer a forcewake write FIFO. *Most* writes must explicitly
> wake the GPU.
> 
> * Interrupt registers have been completely reorganized.
> 
> * PTEs format and cachability settings have changed to more resemble x86
> PTEs, and PAT
>   * Address space increases, and as such many commands require changing
> 
> * Page table structures have changed for the Per Process GTT. The new
> structure more resembles traditional page tables with registers defining
> page directory base.
> 
> The latter two changes were the real challenge in enabling the platform
> and getting things to actually work - though in hindsight, they seem so
> trivial :-)
> 
> You may find these patches here:
> http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell
> 
> I'll be posting patches for libdrm, and intel-gpu-tools in the next day
> or two.  They are also ready to go, I just need to do a quick once over.
> At this point, feel free to stop reading.

Also note that we've spent a decent amount of time refactoring the
relevant areas in upstream, so now the massive changes for bdw mostly just
plug in ...

Anyway, review plan. Like Ben said this is still hidden behind the
preliminary hw support knob. Also I want to get this all merged, final
testing done and pull request sent by the end of the week. That way we can
easily get it into 3.13 and that should also reduce the mess I currently
have with the -internal branch. So
- Please check register defines really through-roughly.
- Check for erregious logic fumbles (e.g. in cleanup paths).
- For everything else which can't be fixed quickly please just propose a
  FIXME comment.

I've just grabbed a bunch of names from our team and then tried to not
come up with a too bad split for reviewing:
Mika: Patches 1-6
Chris: Patches 7-12
Paulo: Patches 13-17
Imre: Patches 18-23
Damien: Patches 24-29
Rodrigo: Patches 30-35
Ville: Patches 36-42
Ben: Patches 43-47
Jani: Patches 48-53
Jesse: Patches 54-58
Daniel: Patche 59-62

If the patches already has an r-b and hasn't been rebased like crazy since
then you're lucky ;-)

Please do the all the review on Mon/Tue so that I can spend Wed
merging (and if needed, fixing up patches) and then we'll have 2 days or
so for a bit of final integration testing.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 36/62] drm/i915/bdw: Broadwell also has the "power down well"

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:34PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Just like Haswell, but with the small twist that the panel fitter for pipe A is
> now also in the always-on power well.
> 
> v2: Use the new HAS_POWER_WELL macro.
> 
> v3: Rebase on top of intel_using_power_well patches.
> 
> v4: This time actually update the PFIT check correctly so that the
> pipe A pfit is in the always-on domain.
> 
> v5: Rebase on top of the VGA power domain addition.
> 
> v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
> message a bit while at it.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 64a3a8c..1a2e967 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -117,6 +117,10 @@ enum intel_display_power_domain {
>  #define HSW_ALWAYS_ON_POWER_DOMAINS (		\
>  	BIT(POWER_DOMAIN_PIPE_A) |		\
>  	BIT(POWER_DOMAIN_TRANSCODER_EDP))
> +#define BDW_ALWAYS_ON_POWER_DOMAINS (		\
> +	BIT(POWER_DOMAIN_PIPE_A) |		\
> +	BIT(POWER_DOMAIN_TRANSCODER_EDP) |	\
> +	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
>  
>  enum hpd_pin {
>  	HPD_NONE = 0,
> @@ -1802,7 +1806,7 @@ struct drm_i915_file_private {
>  #define HAS_IPS(dev)		(IS_ULT(dev))
>  
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
> -#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
> +#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))

IS_BROADWELL() please.

>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev)		(IS_HASWELL(dev))
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 81ec2c3..caf31b7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5524,7 +5524,9 @@ static bool is_always_on_power_domain(struct drm_device *dev,
>  
>  	BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
>  
> -	if (IS_HASWELL(dev)) {
> +	if (IS_GEN8(dev)) {

Here too.

> +		always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
> +	} else if (IS_HASWELL(dev)) {
>  		always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
>  	} else {
>  		WARN_ON(1);
> @@ -6010,4 +6012,3 @@ void intel_pm_init(struct drm_device *dev)
>  	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
>  			  intel_gen6_powersave_work);
>  }
> -
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 38/62] drm/i915/bdw: get the correct LCPLL frequency on Broadwell

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:36PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> v2: Rebased onto Paulo's MHz->kHz change.
> 
> v3: Rebased on top of the Haswell pc8+ adjustements.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++++++-------
>  2 files changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68b877d..d5995dd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5282,6 +5282,9 @@
>  #define  LCPLL_PLL_LOCK			(1<<30)
>  #define  LCPLL_CLK_FREQ_MASK		(3<<26)
>  #define  LCPLL_CLK_FREQ_450		(0<<26)
> +#define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
> +#define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
> +#define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
>  #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
>  #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
>  #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 31f4fe2..d464fd2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1156,18 +1156,29 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>  
>  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  {
> +	struct drm_device *dev = dev_priv->dev;
>  	uint32_t lcpll = I915_READ(LCPLL_CTL);
> +	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
>  
> -	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> +	if (lcpll & LCPLL_CD_SOURCE_FCLK) {
>  		return 800000;

I couldn't find this 800 MHz number anywhere, even in HSW docs. But
I guess it doesn't really matter since fclk shouldn't be selected
for normal operation.

> -	else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
> +	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
>  		return 450000;

I think this is actually incorrect for even HSW. The strap only tells
you what is allowed, but it doesn't affect the actual frequency. You
could still select the alternate frequencies, even though you shouldn't.

> -	else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
> +	} else if (freq == LCPLL_CLK_FREQ_450) {
>  		return 450000;
> -	else if (IS_ULT(dev_priv->dev))
> -		return 337500;
> -	else
> -		return 540000;
> +	} else if (IS_HASWELL(dev)) {
> +		if (IS_ULT(dev))
> +			return 338000;
> +		else
> +			return 540000;
> +	} else {
> +		if (freq == LCPLL_CLK_FREQ_54O_BDW)
> +			return 540000;
> +		else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> +			return 338000;

337500

> +		else
> +			return 675000;
> +	}
>  }
>  
>  void intel_ddi_pll_init(struct drm_device *dev)
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:40PM -0700, Ben Widawsky wrote:
> GEN8 also needs this workaround.

Not according to the w/a database.

But the register description is the same for both HSW and BDW. Also for
HSW, the w/a doesn't actually say whether we should set or clear the bit.
the default is listed to be 0, so I guess we should set it, but then
it's unclear why BDW wouldn't need the w/a. Once again a very poorly
docuemnted w/a :(

> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index caf31b7..68dc363 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5192,6 +5192,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM3_LP_ILK, 0);
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
> +
> +	/* WaSwitchSolVfFArbitrationPriority */
> +	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  }
>  
>  static void haswell_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 40/62] drm/i915/bdw: Broadwell has PIPEMISC

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:38PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
> on previous gens).
> 
> v2: Rebase on to of the pipe config bpp handling rework.
> 
> v3: Rebased on top of the pipe_config->dither refactoring.
> 
> v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
> now also build up PIPECONF completely ourselves - keeping around
> random stuff set by the BIOS just isn't a good idea. I've checked BDW
> BSpec and we already set all relevant bits.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++--
>  2 files changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d5995dd..4131223 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3224,6 +3224,18 @@
>  #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
>  #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
>  
> +#define _PIPE_MISC_A			0x70030
> +#define _PIPE_MISC_B			0x71030
> +#define   PIPEMISC_DITHER_BPC_MASK	(7<<5)
> +#define   PIPEMISC_DITHER_8_BPC		(0<<5)
> +#define   PIPEMISC_DITHER_10_BPC	(1<<5)
> +#define   PIPEMISC_DITHER_6_BPC		(2<<5)
> +#define   PIPEMISC_DITHER_12_BPC	(3<<5)
> +#define   PIPEMISC_DITHER_ENABLE	(1<<4)
> +#define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
> +#define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
> +#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
> +
>  #define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
>  #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
>  #define   PIPEB_HLINE_INT_EN			(1<<28)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7729c88..134ae66 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5772,14 +5772,16 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
>  
>  static void haswell_set_pipeconf(struct drm_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
>  	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
>  	uint32_t val;
>  
>  	val = 0;
>  
> -	if (intel_crtc->config.dither)
> +	if (IS_HASWELL(dev) && intel_crtc->config.dither)
>  		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>  
>  	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> @@ -5792,6 +5794,33 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
>  
>  	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
>  	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
> +
> +	if (IS_BROADWELL(dev)) {
> +		val = 0;
> +
> +		switch (intel_crtc->config.pipe_bpp) {
> +		case 18:
> +			val |= PIPEMISC_DITHER_6_BPC;
> +			break;
> +		case 24:
> +			val |= PIPEMISC_DITHER_8_BPC;
> +			break;
> +		case 30:
> +			val |= PIPEMISC_DITHER_10_BPC;
> +			break;
> +		case 36:
> +			val |= PIPEMISC_DITHER_12_BPC;
> +			break;
> +		default:
> +			/* Case prevented by pipe_config_set_bpp. */
> +			BUG();
> +		}
> +
> +		if (intel_crtc->config.dither)
> +			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
> +
> +		I915_WRITE(PIPEMISC(pipe), val);
> +	}
>  }
>  
>  static bool ironlake_compute_clocks(struct drm_crtc *crtc,
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 37/62] drm/i915/bdw: pretend we have LPT LP on Broadwell

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:35PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> The platforms we currently have all have LPT LP on them. As such, we
> have no way to identify the new WPT PCH that will ship with Broadwell.
> 
> NOTE: For all purposes relevant to the driver that this point, LPT and
> WPT are equivalent. Therefore there should be no need to actually change
> this for some time.
> 
> v2: Don't assign dev_priv->num_pch_pll any more.
> 
> v3: Rebase on top of the PCH detection changes for virtualized
> enviroments.
> 
> v4 (Ben): Wrote commit message
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---

I would have probably placed the hack to the if (!pch) block in the
end, but since it's a hack anyway I guess it's good enough.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c86d44b..590d999 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -453,6 +453,12 @@ void intel_detect_pch(struct drm_device *dev)
>  				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>  				WARN_ON(!IS_HASWELL(dev));
>  				WARN_ON(!IS_ULT(dev));
> +			} else if (IS_BROADWELL(dev)) {
> +				dev_priv->pch_type = PCH_LPT;
> +				dev_priv->pch_id =
> +					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
> +				DRM_DEBUG_KMS("This is Broadwell, assuming "
> +					      "LynxPoint LP PCH\n");
>  			} else {
>  				goto check_next;
>  			}
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 39/62] drm/i915/bdw: on Broadwell, the panel fitter is on the pipe

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:37PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> So you can use the panel fitter while the power well is disabled and
> you also don't need to set the "pipe" bit.
> 
> v2: Rebased on top of Jesse's pfit refactor, which moved pfit state
> into the pipe_config.
> 
> v3: Rebase on top of the latest Haswell/panel fitter rework, which
> neatly resolves a FIXME we have in this patch here:
> 
> v4: Rebase on top of the new power domain framework.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index d464fd2..db848a9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -756,7 +756,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>  	struct drm_encoder *encoder = &intel_encoder->base;
> -	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum pipe pipe = intel_crtc->pipe;
>  	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
>  	enum port port = intel_ddi_get_encoder_port(intel_encoder);
> @@ -792,10 +793,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
>  	if (cpu_transcoder == TRANSCODER_EDP) {
>  		switch (pipe) {
>  		case PIPE_A:
> -			/* Can only use the always-on power well for eDP when
> -			 * not using the panel fitter, and when not using motion
> -			  * blur mitigation (which we don't support). */
> -			if (intel_crtc->config.pch_pfit.enabled)
> +			/* On Haswell, can only use the always-on power well for
> +			 * eDP when not using the panel fitter, and when not
> +			 * using motion blur mitigation (which we don't
> +			 * support). */
> +			if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
>  				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
>  			else
>  				temp |= TRANS_DDI_EDP_INPUT_A_ON;
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 36/62] drm/i915/bdw: Broadwell also has the "power down well"

[Daniel Vetter]

On Sun, Nov 03, 2013 at 01:05:11PM +0200, Ville Syrjälä wrote:
> On Sat, Nov 02, 2013 at 09:07:34PM -0700, Ben Widawsky wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > Just like Haswell, but with the small twist that the panel fitter for pipe A is
> > now also in the always-on power well.
> > 
> > v2: Use the new HAS_POWER_WELL macro.
> > 
> > v3: Rebase on top of intel_using_power_well patches.
> > 
> > v4: This time actually update the PFIT check correctly so that the
> > pipe A pfit is in the always-on domain.
> > 
> > v5: Rebase on top of the VGA power domain addition.
> > 
> > v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
> > message a bit while at it.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
> >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> >  2 files changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 64a3a8c..1a2e967 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -117,6 +117,10 @@ enum intel_display_power_domain {
> >  #define HSW_ALWAYS_ON_POWER_DOMAINS (		\
> >  	BIT(POWER_DOMAIN_PIPE_A) |		\
> >  	BIT(POWER_DOMAIN_TRANSCODER_EDP))
> > +#define BDW_ALWAYS_ON_POWER_DOMAINS (		\
> > +	BIT(POWER_DOMAIN_PIPE_A) |		\
> > +	BIT(POWER_DOMAIN_TRANSCODER_EDP) |	\
> > +	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
> >  
> >  enum hpd_pin {
> >  	HPD_NONE = 0,
> > @@ -1802,7 +1806,7 @@ struct drm_i915_file_private {
> >  #define HAS_IPS(dev)		(IS_ULT(dev))
> >  
> >  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
> > -#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
> > +#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
> 
> IS_BROADWELL() please.

Yeah, that's an artifact of how the patches have been merged. I've moved
the IS_BROADWELL macro up in the series, but didn't fix all the patches.
R-b if I bikeshed this while applying?
-Daniel

> 
> >  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> >  #define HAS_PSR(dev)		(IS_HASWELL(dev))
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 81ec2c3..caf31b7 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5524,7 +5524,9 @@ static bool is_always_on_power_domain(struct drm_device *dev,
> >  
> >  	BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
> >  
> > -	if (IS_HASWELL(dev)) {
> > +	if (IS_GEN8(dev)) {
> 
> Here too.
> 
> > +		always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
> > +	} else if (IS_HASWELL(dev)) {
> >  		always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
> >  	} else {
> >  		WARN_ON(1);
> > @@ -6010,4 +6012,3 @@ void intel_pm_init(struct drm_device *dev)
> >  	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
> >  			  intel_gen6_powersave_work);
> >  }
> > -
> > -- 
> > 1.8.4.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 36/62] drm/i915/bdw: Broadwell also has the "power down well"

[Ville Syrjälä]

On Sun, Nov 03, 2013 at 12:24:13PM +0100, Daniel Vetter wrote:
> On Sun, Nov 03, 2013 at 01:05:11PM +0200, Ville Syrjälä wrote:
> > On Sat, Nov 02, 2013 at 09:07:34PM -0700, Ben Widawsky wrote:
> > > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > 
> > > Just like Haswell, but with the small twist that the panel fitter for pipe A is
> > > now also in the always-on power well.
> > > 
> > > v2: Use the new HAS_POWER_WELL macro.
> > > 
> > > v3: Rebase on top of intel_using_power_well patches.
> > > 
> > > v4: This time actually update the PFIT check correctly so that the
> > > pipe A pfit is in the always-on domain.
> > > 
> > > v5: Rebase on top of the VGA power domain addition.
> > > 
> > > v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
> > > message a bit while at it.
> > > 
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h | 6 +++++-
> > >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> > >  2 files changed, 8 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 64a3a8c..1a2e967 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -117,6 +117,10 @@ enum intel_display_power_domain {
> > >  #define HSW_ALWAYS_ON_POWER_DOMAINS (		\
> > >  	BIT(POWER_DOMAIN_PIPE_A) |		\
> > >  	BIT(POWER_DOMAIN_TRANSCODER_EDP))
> > > +#define BDW_ALWAYS_ON_POWER_DOMAINS (		\
> > > +	BIT(POWER_DOMAIN_PIPE_A) |		\
> > > +	BIT(POWER_DOMAIN_TRANSCODER_EDP) |	\
> > > +	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
> > >  
> > >  enum hpd_pin {
> > >  	HPD_NONE = 0,
> > > @@ -1802,7 +1806,7 @@ struct drm_i915_file_private {
> > >  #define HAS_IPS(dev)		(IS_ULT(dev))
> > >  
> > >  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
> > > -#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
> > > +#define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
> > 
> > IS_BROADWELL() please.
> 
> Yeah, that's an artifact of how the patches have been merged. I've moved
> the IS_BROADWELL macro up in the series, but didn't fix all the patches.
> R-b if I bikeshed this while applying?

Yep.

> -Daniel
> 
> > 
> > >  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> > >  #define HAS_PSR(dev)		(IS_HASWELL(dev))
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 81ec2c3..caf31b7 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5524,7 +5524,9 @@ static bool is_always_on_power_domain(struct drm_device *dev,
> > >  
> > >  	BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
> > >  
> > > -	if (IS_HASWELL(dev)) {
> > > +	if (IS_GEN8(dev)) {
> > 
> > Here too.
> > 
> > > +		always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
> > > +	} else if (IS_HASWELL(dev)) {
> > >  		always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
> > >  	} else {
> > >  		WARN_ON(1);
> > > @@ -6010,4 +6012,3 @@ void intel_pm_init(struct drm_device *dev)
> > >  	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
> > >  			  intel_gen6_powersave_work);
> > >  }
> > > -
> > > -- 
> > > 1.8.4.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

[PATCH 63/62] drm/i915/bdw: Enable trickle feed on Broadwell

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Like on HSW, trickle feed should always be enabled on BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
Not sure this applies directly, I just put it together on top of -nightly.
Thus it's not even compile tested.

 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f34252d..4539550 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2156,7 +2156,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 	else
 		dspcntr &= ~DISPPLANE_TILED;
 
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
 	else
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6..2bcee75 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -260,7 +260,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	if (obj->tiling_mode != I915_TILING_NONE)
 		sprctl |= SPRITE_TILED;
 
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 	else
 		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
-- 
1.8.1.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority

[Ben Widawsky]

On Sun, Nov 03, 2013 at 01:07:58PM +0200, Ville Syrjälä wrote:
> On Sat, Nov 02, 2013 at 09:07:40PM -0700, Ben Widawsky wrote:
> > GEN8 also needs this workaround.
> 
> Not according to the w/a database.
> 
> But the register description is the same for both HSW and BDW. Also for
> HSW, the w/a doesn't actually say whether we should set or clear the bit.
> the default is listed to be 0, so I guess we should set it, but then
> it's unclear why BDW wouldn't need the w/a. Once again a very poorly
> docuemnted w/a :(

Just an FYI: all workarounds for Broadwell came from the bspec, as the
workaround database did not exist for Broadwell at that time.

Also, I was informally told not to trust the workaround database yet.

[snip]

-- 
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/62] drm/i915/bdw: Add device IDs

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:02PM -0700, Ben Widawsky wrote:
> @@ -367,7 +385,9 @@ static const struct intel_device_info intel_haswell_m_info = {
>  	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
>  	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
>  	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
> -	INTEL_VLV_D_IDS(&intel_valleyview_d_info)
> +	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
> +	INTEL_BDW_PCI_IDS_M(&intel_broadwell_m_info),	\
> +	INTEL_BDW_PCI_IDS_D(&intel_broadwell_d_info)

Inconsistent naming scheme post Jesse-rebase.
  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_PCI_IDS,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 8a10f5c..d35bc0b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -208,4 +208,31 @@
>  #define INTEL_VLV_D_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0155, info)
>  
> +#define _INTEL_BDW_PCI_ID_M(gt, id, info) \
> +	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
> +#define _INTEL_BDW_PCI_ID_D(gt, id, info) \
> +	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
> +
> +#define INTEL_BDW_PCI_ID_M(gt, info) \
> +	_INTEL_BDW_PCI_ID_M(gt, 0x1606, info), /* ULT */ \
> +	_INTEL_BDW_PCI_ID_M(gt, 0x160B, info), /* Iris */ \
> +	_INTEL_BDW_PCI_ID_M(gt, 0x160E, info) /* ULX */
> +
> +#define INTEL_BDW_PCI_ID_D(gt, info) \
> +	_INTEL_BDW_PCI_ID_M(gt, 0x160A, info), /* Server */ \
> +	_INTEL_BDW_PCI_ID_M(gt, 0x160D, info) /* Workstation */
> +
> +#define INTEL_BDW_PCI_IDS_M(info) \
> +	INTEL_BDW_PCI_ID_M(1, info), \
> +	INTEL_BDW_PCI_ID_M(2, info), \
> +	INTEL_BDW_PCI_ID_M(3, info), \
> +	INTEL_VGA_DEVICE(0x0BD0, info) /* Simulator GT1 */
> +
> +#define INTEL_BDW_PCI_IDS_D(info) \
> +	INTEL_BDW_PCI_ID_D(1, info), \
> +	INTEL_BDW_PCI_ID_D(2, info), \
> +	INTEL_BDW_PCI_ID_D(3, info), \
> +	INTEL_VGA_DEVICE(0x0BD1, info), /* Simulator GT2 */ \
> +	INTEL_VGA_DEVICE(0x0BD2, info)  /*/Simulator GT3 */

I thought we weren't adding internal simulator ids upstream?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH 04/62] [v6] drm/i915/bdw: Add device IDs

[Ben Widawsky]

v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.

v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>

v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.

v4: Replace Halo by its marketing moniker Iris. Requested by Ben.

v5: Switch from info->has*ring to info->ring_mask.

v6: Add 0x16X2 variant (which is newer than this patch)
Rename to use new naming scheme (Chris)
Remove Simulator PCI ids. These snuck in during rebase (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 22 +++++++++++++++++++++-
 include/drm/i915_pciids.h       | 25 +++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 770c9f8..50891cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -336,6 +336,24 @@ static const struct intel_device_info intel_haswell_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 };
 
+static const struct intel_device_info intel_broadwell_d_info = {
+	.is_preliminary = 1,
+	.gen = 8,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
+static const struct intel_device_info intel_broadwell_m_info = {
+	.is_preliminary = 1,
+	.gen = 8, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -367,7 +385,9 @@ static const struct intel_device_info intel_haswell_m_info = {
 	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
-	INTEL_VLV_D_IDS(&intel_valleyview_d_info)
+	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
+	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
+	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 8a10f5c..ba630c8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -208,4 +208,29 @@
 #define INTEL_VLV_D_IDS(info) \
 	INTEL_VGA_DEVICE(0x0155, info)
 
+#define _INTEL_BDW_M(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+#define _INTEL_BDW_D(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+
+#define _INTEL_BDW_M(gt, info) \
+	_INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
+	_INTEL_BDW_M(gt, 0x160E, info) /* ULX */
+
+#define _INTEL_BDW_D(gt, info) \
+	_INTEL_BDW_M(gt, 0x160A, info), /* Server */ \
+	_INTEL_BDW_M(gt, 0x160D, info) /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+	_INTEL_BDW_M(1, info), \
+	_INTEL_BDW_M(2, info), \
+	_INTEL_BDW_M(3, info)
+
+#define INTEL_BDW_D_IDS(info) \
+	_INTEL_BDW_D(1, info), \
+	_INTEL_BDW_D(2, info), \
+	_INTEL_BDW_D(3, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
1.8.4.2

Re: [PATCH 04/62] drm/i915/bdw: Add device IDs

[Ben Widawsky]

On Sun, Nov 03, 2013 at 09:58:00PM +0000, Chris Wilson wrote:
> On Sat, Nov 02, 2013 at 09:07:02PM -0700, Ben Widawsky wrote:
> > @@ -367,7 +385,9 @@ static const struct intel_device_info intel_haswell_m_info = {
> >  	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
> >  	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
> >  	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
> > -	INTEL_VLV_D_IDS(&intel_valleyview_d_info)
> > +	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
> > +	INTEL_BDW_PCI_IDS_M(&intel_broadwell_m_info),	\
> > +	INTEL_BDW_PCI_IDS_D(&intel_broadwell_d_info)
> 
> Inconsistent naming scheme post Jesse-rebase.
>   
> >  static const struct pci_device_id pciidlist[] = {		/* aka */
> >  	INTEL_PCI_IDS,
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 8a10f5c..d35bc0b 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -208,4 +208,31 @@
> >  #define INTEL_VLV_D_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x0155, info)
> >  
> > +#define _INTEL_BDW_PCI_ID_M(gt, id, info) \
> > +	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
> > +#define _INTEL_BDW_PCI_ID_D(gt, id, info) \
> > +	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
> > +
> > +#define INTEL_BDW_PCI_ID_M(gt, info) \
> > +	_INTEL_BDW_PCI_ID_M(gt, 0x1606, info), /* ULT */ \
> > +	_INTEL_BDW_PCI_ID_M(gt, 0x160B, info), /* Iris */ \
> > +	_INTEL_BDW_PCI_ID_M(gt, 0x160E, info) /* ULX */
> > +
> > +#define INTEL_BDW_PCI_ID_D(gt, info) \
> > +	_INTEL_BDW_PCI_ID_M(gt, 0x160A, info), /* Server */ \
> > +	_INTEL_BDW_PCI_ID_M(gt, 0x160D, info) /* Workstation */

Tsk tsk - you missed this one.

> > +
> > +#define INTEL_BDW_PCI_IDS_M(info) \
> > +	INTEL_BDW_PCI_ID_M(1, info), \
> > +	INTEL_BDW_PCI_ID_M(2, info), \
> > +	INTEL_BDW_PCI_ID_M(3, info), \
> > +	INTEL_VGA_DEVICE(0x0BD0, info) /* Simulator GT1 */
> > +
> > +#define INTEL_BDW_PCI_IDS_D(info) \
> > +	INTEL_BDW_PCI_ID_D(1, info), \
> > +	INTEL_BDW_PCI_ID_D(2, info), \
> > +	INTEL_BDW_PCI_ID_D(3, info), \
> > +	INTEL_VGA_DEVICE(0x0BD1, info), /* Simulator GT2 */ \
> > +	INTEL_VGA_DEVICE(0x0BD2, info)  /*/Simulator GT3 */
> 
> I thought we weren't adding internal simulator ids upstream?
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Ben Widawsky, Intel Open Source Technology Center

[PATCH 04/62] [v7] drm/i915/bdw: Add device IDs

[Ben Widawsky]

v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.

v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>

v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.

v4: Replace Halo by its marketing moniker Iris. Requested by Ben.

v5: Switch from info->has*ring to info->ring_mask.

v6: Add 0x16X2 variant (which is newer than this patch)
Rename to use new naming scheme (Chris)
Remove Simulator PCI ids. These snuck in during rebase (Chris)

v7: Fix poor sed job from v6
Make the desktop variants use the desktop macro (Rebase error). Notice
that this makes no functional difference - it's just confusing.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c | 22 +++++++++++++++++++++-
 include/drm/i915_pciids.h       | 25 +++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 770c9f8..50891cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -336,6 +336,24 @@ static const struct intel_device_info intel_haswell_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 };
 
+static const struct intel_device_info intel_broadwell_d_info = {
+	.is_preliminary = 1,
+	.gen = 8,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
+static const struct intel_device_info intel_broadwell_m_info = {
+	.is_preliminary = 1,
+	.gen = 8, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+	.has_llc = 1,
+	.has_ddi = 1,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -367,7 +385,9 @@ static const struct intel_device_info intel_haswell_m_info = {
 	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
-	INTEL_VLV_D_IDS(&intel_valleyview_d_info)
+	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
+	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\
+	INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_PCI_IDS,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 8a10f5c..940ece4 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -208,4 +208,29 @@
 #define INTEL_VLV_D_IDS(info) \
 	INTEL_VGA_DEVICE(0x0155, info)
 
+#define _INTEL_BDW_M(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+#define _INTEL_BDW_D(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+
+#define _INTEL_BDW_M_IDS(gt, info) \
+	_INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
+	_INTEL_BDW_M(gt, 0x160E, info) /* ULX */
+
+#define _INTEL_BDW_D_IDS(gt, info) \
+	_INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
+	_INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+	_INTEL_BDW_M_IDS(1, info), \
+	_INTEL_BDW_M_IDS(2, info), \
+	_INTEL_BDW_M_IDS(3, info)
+
+#define INTEL_BDW_D_IDS(info) \
+	_INTEL_BDW_D_IDS(1, info), \
+	_INTEL_BDW_D_IDS(2, info), \
+	_INTEL_BDW_D_IDS(3, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
1.8.4.2

[PATCH 10/62] [v5] drm/i915/bdw: support GMS and GGMS changes

[Ben Widawsky]

All the BARs have the ability to grow.

v2: Pulled out the simulator workaround to a separate patch.
Rebased.

v3: Rebase onto latest vlv patches from Jesse.

v4: Rebased on top of the early stolen quirk patch from Jesse.

v5: Use the new macro names.
s/INTEL_BDW_PCI_IDS_D/INTEL_BDW_D_IDS
s/INTEL_BDW_PCI_IDS_M/INTEL_BDW_M_IDS
It's Jesse's fault for not following the convention I originally set.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 arch/x86/kernel/early-quirks.c      | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++++---
 include/drm/i915_drm.h              |  4 ++++
 3 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b3cd3eb..96f958d 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -313,6 +313,16 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
 	return gmch_ctrl << 25; /* 32 MB units */
 }
 
+static inline size_t gen8_stolen_size(int num, int slot, int func)
+{
+	u16 gmch_ctrl;
+
+	gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
+	gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
+	gmch_ctrl &= BDW_GMCH_GMS_MASK;
+	return gmch_ctrl << 25; /* 32 MB units */
+}
+
 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 
 static struct pci_device_id intel_stolen_ids[] __initdata = {
@@ -336,6 +346,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
 	INTEL_IVB_D_IDS(gen6_stolen_size),
 	INTEL_HSW_D_IDS(gen6_stolen_size),
 	INTEL_HSW_M_IDS(gen6_stolen_size),
+	INTEL_BDW_M_IDS(gen8_stolen_size),
+	INTEL_BDW_D_IDS(gen8_stolen_size)
 };
 
 static void __init intel_graphics_stolen(int num, int slot, int func)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 77b3c74..19016b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -869,6 +869,15 @@ static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 	return snb_gmch_ctl << 20;
 }
 
+static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+{
+	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
+	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
+	if (bdw_gmch_ctl)
+		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+	return bdw_gmch_ctl << 20;
+}
+
 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
@@ -876,6 +885,13 @@ static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 	return snb_gmch_ctl << 25; /* 32 MB units */
 }
 
+static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
+{
+	bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
+	bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
+	return bdw_gmch_ctl << 25; /* 32 MB units */
+}
+
 static int gen6_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -903,10 +919,16 @@ static int gen6_gmch_probe(struct drm_device *dev,
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
-	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 
-	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
-	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+	if (IS_GEN8(dev)) {
+		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+		*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+	} else {
+		gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
+		*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
+	}
 
 	/* For Modern GENs the PTEs and register space are split in the BAR */
 	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
@@ -916,6 +938,7 @@ static int gen6_gmch_probe(struct drm_device *dev,
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
+
 	}
 
 	ret = setup_scratch_page(dev);
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 3abfa6e..97d5497 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -49,6 +49,10 @@ extern bool i915_gpu_turbo_disable(void);
 #define    SNB_GMCH_GGMS_MASK	0x3
 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
 #define    SNB_GMCH_GMS_MASK    0x1f
+#define    BDW_GMCH_GGMS_SHIFT	6
+#define    BDW_GMCH_GGMS_MASK	0x3
+#define    BDW_GMCH_GMS_SHIFT   8
+#define    BDW_GMCH_GMS_MASK    0xff
 
 #define I830_GMCH_CTRL			0x52
 
-- 
1.8.4.2

Re: [PATCH 48/62] drm/i915/bdw: Add Broadwell display FIFO limits

[Jani Nikula]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Broadwell has bigger display FIFOs than Haswell. Otherwise the
> two are very similar.
>
> v2: Fix FBC WM_LP shift for BDW
>
> v3: Rebase on top of the big Haswell wm rework.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 33 ++++++++++++++++++++++++---------
>  2 files changed, 25 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6f834b3..2a65f92 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3366,6 +3366,7 @@
>  #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
>  #define  WM1_LP_FBC_MASK	(0xf<<20)
>  #define  WM1_LP_FBC_SHIFT	20
> +#define  WM1_LP_FBC_SHIFT_BDW	19
>  #define  WM1_LP_SR_MASK		(0x7ff<<8)

Meh, the above _MASKs would need some love too. WM1_LP_SR_MASK is wrong
for HSW already I think. But nobody's using them, so not a blocker for
this patch.

>  #define  WM1_LP_SR_SHIFT	8
>  #define  WM1_LP_CURSOR_MASK	(0xff)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 68dc363..6d14182 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2291,7 +2291,9 @@ static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
>  
>  static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
>  {
> -	if (INTEL_INFO(dev)->gen >= 7)
> +	if (INTEL_INFO(dev)->gen >= 8)
> +		return 3072;

It's probably just me, but I couldn't find this in the spec, so can't
verify. Apart from that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

...but read on, some non-blocking bikeshedding below.

> +	else if (INTEL_INFO(dev)->gen >= 7)
>  		return 768;
>  	else
>  		return 512;
> @@ -2336,7 +2338,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>  	}
>  
>  	/* clamp to max that the registers can hold */
> -	if (INTEL_INFO(dev)->gen >= 7)
> +	if (INTEL_INFO(dev)->gen >= 8)
> +		max = level == 0 ? 255 : 2047;

Not having looked at the WM stuff before, it took me a while to find the
registers and check the maximums. Which made me wonder why we don't fix
the masks and use them here, so it would be bloody obvious what we're
referring to?

if (level)
	max = WM1_LP_SR_MASK_BDW >> WM1_LP_SR_SHIFT_BDW;
else
	max = WM0_PIPE_PLANE_MASK_BDW >> WM0_PIPE_PLANE_SHIFT;

> +	else if (INTEL_INFO(dev)->gen >= 7)
>  		/* IVB/HSW primary/sprite plane watermarks */
>  		max = level == 0 ? 127 : 1023;
>  	else if (!is_sprite)
> @@ -2366,10 +2370,13 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
>  }
>  
>  /* Calculate the maximum FBC watermark */
> -static unsigned int ilk_fbc_wm_max(void)
> +static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
>  {
>  	/* max that registers can hold */
> -	return 15;
> +	if (INTEL_INFO(dev)->gen >= 8)
> +		return 31;
> +	else
> +		return 15;
>  }
>  
>  static void ilk_compute_wm_maximums(struct drm_device *dev,
> @@ -2381,7 +2388,7 @@ static void ilk_compute_wm_maximums(struct drm_device *dev,
>  	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
>  	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
>  	max->cur = ilk_cursor_wm_max(dev, level, config);
> -	max->fbc = ilk_fbc_wm_max();
> +	max->fbc = ilk_fbc_wm_max(dev);
>  }
>  
>  static bool ilk_validate_wm_level(int level,
> @@ -2722,10 +2729,18 @@ static void hsw_compute_wm_results(struct drm_device *dev,
>  		if (!r->enable)
>  			break;
>  
> -		results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
> -							  r->fbc_val,
> -							  r->pri_val,
> -							  r->cur_val);

This leaves HSW_WM_LP_VAL() macro unused.

> +		results->wm_lp[wm_lp - 1] = WM3_LP_EN |
> +			((level * 2) << WM1_LP_LATENCY_SHIFT) |
> +			(r->pri_val << WM1_LP_SR_SHIFT) |
> +			r->cur_val;
> +
> +		if (INTEL_INFO(dev)->gen >= 8)
> +			results->wm_lp[wm_lp - 1] |=
> +				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> +		else
> +			results->wm_lp[wm_lp - 1] |=
> +				r->fbc_val << WM1_LP_FBC_SHIFT;
> +
>  		results->wm_lp_spr[wm_lp - 1] = r->spr_val;
>  	}
>  
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 49/62] drm/i915/bdw: Use The GT mailbox for IPS enable/disable

[Jani Nikula]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
>
> CC: Art Runyan <arthur.j.runyan@intel.com>
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

The WARN_ON()s may be a bit loud, but

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++----------
>  3 files changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a2e967..f222eb4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1803,7 +1803,7 @@ struct drm_i915_file_private {
>  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
>  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>  
> -#define HAS_IPS(dev)		(IS_ULT(dev))
> +#define HAS_IPS(dev)		(IS_ULT(dev) || IS_BROADWELL(dev))
>  
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a65f92..65f9631 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4932,6 +4932,7 @@
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   DISPLAY_IPS_CONTROL			0x19
>  #define GEN6_PCODE_DATA				0x138128
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fce3b0d..fc4b4cf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3347,15 +3347,26 @@ void hsw_enable_ips(struct intel_crtc *crtc)
>  	 * only after intel_enable_plane. And intel_enable_plane already waits
>  	 * for a vblank, so all we need to do here is to enable the IPS bit. */
>  	assert_plane_enabled(dev_priv, crtc->plane);
> -	I915_WRITE(IPS_CTL, IPS_ENABLE);
> -
> -	/* The bit only becomes 1 in the next vblank, so this wait here is
> -	 * essentially intel_wait_for_vblank. If we don't have this and don't
> -	 * wait for vblanks until the end of crtc_enable, then the HW state
> -	 * readout code will complain that the expected IPS_CTL value is not the
> -	 * one we read. */
> -	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
> -		DRM_ERROR("Timed out waiting for IPS enable\n");
> +	if (IS_BROADWELL(crtc->base.dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +		/* Quoting Art Runyan: "its not safe to expect any particular
> +		 * value in IPS_CTL bit 31 after enabling IPS through the
> +		 * mailbox." Therefore we need to defer waiting on the state
> +		 * change.
> +		 * TODO: need to fix this for state checker
> +		 */
> +	} else {
> +		I915_WRITE(IPS_CTL, IPS_ENABLE);
> +		/* The bit only becomes 1 in the next vblank, so this wait here
> +		 * is essentially intel_wait_for_vblank. If we don't have this
> +		 * and don't wait for vblanks until the end of crtc_enable, then
> +		 * the HW state readout code will complain that the expected
> +		 * IPS_CTL value is not the one we read. */
> +		if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
> +			DRM_ERROR("Timed out waiting for IPS enable\n");
> +	}
>  }
>  
>  void hsw_disable_ips(struct intel_crtc *crtc)
> @@ -3367,7 +3378,12 @@ void hsw_disable_ips(struct intel_crtc *crtc)
>  		return;
>  
>  	assert_plane_enabled(dev_priv, crtc->plane);
> -	I915_WRITE(IPS_CTL, 0);
> +	if (IS_BROADWELL(crtc->base.dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else
> +		I915_WRITE(IPS_CTL, 0);
>  	POSTING_READ(IPS_CTL);
>  
>  	/* We need to wait for a vblank before we can disable the plane. */
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 50/62] drm/i915/bdw: Support eDP PSR

[Jani Nikula]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> Broadwell PSR support is a superset of Haswell. With this simple
> register base calculation, everything that worked on HSW for eDP PSR
> should work on BDW.

Per bspec, EDP_PSR_CTL register EDP_PSR_MIN_LINK_ENTRY_TIME_* bits are
reserved/MBZ on BDW, but intel_edp_psr_enable_source() sets them.

With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Note that Broadwell provides additional PSR support. This is not
> addressed at this time.
>
> v2: Make the HAS_PSR include BDW
>
> v3: Use the correct offset (I had incorrectly used one from my faulty
> brain) (Art!)
>
> v4: It helps if you git add
>
> CC: Art Runyan <arthur.j.runyan@intel.com>
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f222eb4..dc79a0f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)		(IS_HASWELL(dev))
> +#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65f9631..f97836e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1956,8 +1956,8 @@
>  #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
>  #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>  
> -/* HSW eDP PSR registers */
> -#define EDP_PSR_BASE(dev)			0x64800
> +/* HSW+ eDP PSR registers */
> +#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
>  #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   EDP_PSR_LINK_DISABLE			(0<<27)
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 58/62] drm/i915/bdw: Disable centroid pixel perf optimization

[Paulo Zanoni]

2013/11/3 Ben Widawsky <benjamin.widawsky@intel.com>:
> From: Ben Widawsky <ben@bwidawsk.net>
>
> BDW-A workaround
>
> BDW Bug #1899532
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2d16363..8080a4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4986,6 +4986,9 @@
>  #define HSW_ROW_CHICKEN3               0xe49c
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>
> +#define HALF_SLICE_CHICKEN3            0xe184
> +#define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
> +
>  #define G4X_AUD_VID_DID                        (dev_priv->info->display_mmio_offset + 0x62020)
>  #define INTEL_AUDIO_DEVCL              0x808629FB
>  #define INTEL_AUDIO_DEVBLC             0x80862801
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e6e12e1..dd0d375 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(WM2_LP_ILK, 0);
>         I915_WRITE(WM1_LP_ILK, 0);
>
> +       I915_WRITE(HALF_SLICE_CHICKEN3,
> +                  _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));

Shouldn't we add a comment saying this is, so far, only to
pre-production machines and we might want to remove this later?
Hunting down these things later won't be easy if we don't have nice
comments helping us. We all have seen many cases where WAs that apply
only to pre-production machines only get removed a long long time
after we should have removed.


>         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
>
>         /* WaSwitchSolVfFArbitrationPriority */
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 53/62] drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI

[Jani Nikula]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> Just like HSW.
>
> This means we can scan out a mode with a 300Mhz pixel clock with a depth
> of 24 bits, but only a 200Mhz one with a 36bits depth.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 51a8336..03f9ca7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -847,7 +847,7 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
>  
>  	if (IS_G4X(dev))
>  		return 165000;
> -	else if (IS_HASWELL(dev))
> +	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
>  		return 300000;
>  	else
>  		return 225000;
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 52/62] drm/i915/bdw: Don't wait for c0 threads on forcewake

[Jani Nikula]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> It's no longer a required workaround on BDW.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> [danvet: Move compile fix from a later patch to this one.]
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index fa06ce4..727cf30 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -112,7 +112,8 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
>  		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>  
>  	/* WaRsForcewakeWaitTC0:ivb,hsw */
> -	__gen6_gt_wait_for_thread_c0(dev_priv);
> +	if (INTEL_INFO(dev_priv->dev)->gen < 8)
> +		__gen6_gt_wait_for_thread_c0(dev_priv);
>  }
>  
>  static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 48/62] drm/i915/bdw: Add Broadwell display FIFO limits

[Ville Syrjälä]

On Mon, Nov 04, 2013 at 11:39:56AM +0200, Jani Nikula wrote:
> On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Broadwell has bigger display FIFOs than Haswell. Otherwise the
> > two are very similar.
> >
> > v2: Fix FBC WM_LP shift for BDW
> >
> > v3: Rebase on top of the big Haswell wm rework.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 33 ++++++++++++++++++++++++---------
> >  2 files changed, 25 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6f834b3..2a65f92 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3366,6 +3366,7 @@
> >  #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
> >  #define  WM1_LP_FBC_MASK	(0xf<<20)
> >  #define  WM1_LP_FBC_SHIFT	20
> > +#define  WM1_LP_FBC_SHIFT_BDW	19
> >  #define  WM1_LP_SR_MASK		(0x7ff<<8)
> 
> Meh, the above _MASKs would need some love too. WM1_LP_SR_MASK is wrong
> for HSW already I think. But nobody's using them, so not a blocker for
> this patch.
> 
> >  #define  WM1_LP_SR_SHIFT	8
> >  #define  WM1_LP_CURSOR_MASK	(0xff)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 68dc363..6d14182 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2291,7 +2291,9 @@ static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
> >  
> >  static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
> >  {
> > -	if (INTEL_INFO(dev)->gen >= 7)
> > +	if (INTEL_INFO(dev)->gen >= 8)
> > +		return 3072;
> 
> It's probably just me, but I couldn't find this in the spec, so can't
> verify.

Looks like it's not spelled out there anymore. But you can figure it out
by looking at the single pipe primary:sprite 1:1 split numbers
(1536 * 2 = 3072) or the multi pipe primary only numbers (1024 * 3 = 3072).

> Apart from that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> ...but read on, some non-blocking bikeshedding below.
> 
> > +	else if (INTEL_INFO(dev)->gen >= 7)
> >  		return 768;
> >  	else
> >  		return 512;
> > @@ -2336,7 +2338,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
> >  	}
> >  
> >  	/* clamp to max that the registers can hold */
> > -	if (INTEL_INFO(dev)->gen >= 7)
> > +	if (INTEL_INFO(dev)->gen >= 8)
> > +		max = level == 0 ? 255 : 2047;
> 
> Not having looked at the WM stuff before, it took me a while to find the
> registers and check the maximums. Which made me wonder why we don't fix
> the masks and use them here, so it would be bloody obvious what we're
> referring to?
> 
> if (level)
> 	max = WM1_LP_SR_MASK_BDW >> WM1_LP_SR_SHIFT_BDW;
> else
> 	max = WM0_PIPE_PLANE_MASK_BDW >> WM0_PIPE_PLANE_SHIFT;

I just extended the masks to cover all platforms. That makes hw
state readout a bit simpler since I don't need to worry about the
differences between generations there. But that means the masks
don't necessarily correspond to any specific platform, and so we
can't use them here. I could define per-platforms masks too, but
that seems rather pointless since there would be but one user.

> 
> > +	else if (INTEL_INFO(dev)->gen >= 7)
> >  		/* IVB/HSW primary/sprite plane watermarks */
> >  		max = level == 0 ? 127 : 1023;
> >  	else if (!is_sprite)
> > @@ -2366,10 +2370,13 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
> >  }
> >  
> >  /* Calculate the maximum FBC watermark */
> > -static unsigned int ilk_fbc_wm_max(void)
> > +static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
> >  {
> >  	/* max that registers can hold */
> > -	return 15;
> > +	if (INTEL_INFO(dev)->gen >= 8)
> > +		return 31;
> > +	else
> > +		return 15;
> >  }
> >  
> >  static void ilk_compute_wm_maximums(struct drm_device *dev,
> > @@ -2381,7 +2388,7 @@ static void ilk_compute_wm_maximums(struct drm_device *dev,
> >  	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
> >  	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
> >  	max->cur = ilk_cursor_wm_max(dev, level, config);
> > -	max->fbc = ilk_fbc_wm_max();
> > +	max->fbc = ilk_fbc_wm_max(dev);
> >  }
> >  
> >  static bool ilk_validate_wm_level(int level,
> > @@ -2722,10 +2729,18 @@ static void hsw_compute_wm_results(struct drm_device *dev,
> >  		if (!r->enable)
> >  			break;
> >  
> > -		results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
> > -							  r->fbc_val,
> > -							  r->pri_val,
> > -							  r->cur_val);
> 
> This leaves HSW_WM_LP_VAL() macro unused.

Yeah. I should just kill it.

> 
> > +		results->wm_lp[wm_lp - 1] = WM3_LP_EN |
> > +			((level * 2) << WM1_LP_LATENCY_SHIFT) |
> > +			(r->pri_val << WM1_LP_SR_SHIFT) |
> > +			r->cur_val;
> > +
> > +		if (INTEL_INFO(dev)->gen >= 8)
> > +			results->wm_lp[wm_lp - 1] |=
> > +				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> > +		else
> > +			results->wm_lp[wm_lp - 1] |=
> > +				r->fbc_val << WM1_LP_FBC_SHIFT;
> > +
> >  		results->wm_lp_spr[wm_lp - 1] = r->spr_val;
> >  	}
> >  
> > -- 
> > 1.8.4.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 24/62] drm/i915/bdw: Initialize the PDEs

[Damien Lespiau]

On Sat, Nov 02, 2013 at 09:07:22PM -0700, Ben Widawsky wrote:
> The upcoming clear and insert routines will expect that PDEs all point
> to valid Page Directories. Doing that lazily doesn't really buy us
> anything.
> 
> The page allocation is done regardless earlier in init so it shouldn't
> hurt set the PDEs.
> 
> v2: Squash in patches to implement fixed PDE write function:
> 
> - If I had done this in the first place, the bug that's going to be
>   fixed in an upcoming patch would have been much easier to find.
> 
> - Use WB for PDEs.
> 
>   The PAT bit is used for page size. 2ME PDEs aren't even supported in
>   BDW, so this was completely invalid. The solution is to make our
>   PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess,
>   this change won't matter for performance.
> 
>   Thanks to Ville for the quick correction when discussing on IRC.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

With the small bikeshed below:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4a11f51..bae71b4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -80,6 +80,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
>  	return pte;
>  }
>  
> +static inline gen8_gtt_pte_t gen8_pde_encode(struct drm_device *dev,
> +					     dma_addr_t addr,
> +					     enum i915_cache_level level)

Should be returning a gen8_ppgtt_pde_t (not a bug as they are the same
size, of course).

> +{
> +	gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
> +	pde |= addr;
> +	if (level != I915_CACHE_NONE)
> +		pde |= PPAT_CACHED_PDE_INDEX;
> +	else
> +		pde |= PPAT_UNCACHED_INDEX;
> +	return pde;
> +}
> +
>  static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
>  				     enum i915_cache_level level,
>  				     bool valid)
> @@ -285,6 +298,20 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
>  		}
>  	}
>  
> +	/* For now, the PPGTT helper functions all require that the PDEs are
> +	 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
> +	 * will never need to touch the PDEs again */
> +	for (i = 0; i < max_pdp; i++) {
> +		gen8_ppgtt_pde_t *pd_vaddr;
> +		pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
> +		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
> +			dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
> +			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
> +						      I915_CACHE_LLC);
> +		}
> +		kunmap_atomic(pd_vaddr);
> +	}
> +
>  	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
>  			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
>  	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
> -- 
> 1.8.4.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 00/62] Broadwell kernel driver support

[Jani Nikula]

On Sun, 03 Nov 2013, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Sat, Nov 02, 2013 at 09:06:58PM -0700, Ben Widawsky wrote:
>> It is my honor and privilege to submit basic Broadwell support on behalf
>> of Intel.
>> 
>> The patch series includes support for Broadwell which should bring it up
>> to feature parity with Haswell. As you'll note, the patches have
>> received some revisions and review already. This is due to our new
>> process (more on this below). We will be rolling out the new Broadwell
>> goodness over time.
>> 
>> Broadwell represents the next generation (GEN8) in Intel graphics
>> processing hardware. Broadwell graphics bring some of the biggest
>> changes we've seen on the execution and memory management side of the
>> GPU. (There are equally large and exciting changes for the userspace
>> drivers.)
>> 
>> My request to reviewers is: I haven't touched these much at all since
>> submitting to the internal mailing list. Most changes are due to rebase.
>> Try to keep bikesheds to a minimum. We want to try to get this code in
>> the 3.13 kernel, so we have a nice base to actually stabilize and
>> improve features for the 3.14 release. Remember, we have that handy
>> 'preliminary hardware support' to allow people to opt-in to this early
>> enabling code. So I'm shooting for stable "end-userable" BDW code in
>> 3.14.
>> 
>> Note that the last few workarounds likely won't be needed, but I think
>> we can include them until we know for sure otherwise.
>> 
>> Aside from the usual set of things we need to update when simply
>> enabling a new platform, What follows are some of the major changes from
>> HSW->BDW:
>> 
>> * There is no longer a forcewake write FIFO. *Most* writes must explicitly
>> wake the GPU.
>> 
>> * Interrupt registers have been completely reorganized.
>> 
>> * PTEs format and cachability settings have changed to more resemble x86
>> PTEs, and PAT
>>   * Address space increases, and as such many commands require changing
>> 
>> * Page table structures have changed for the Per Process GTT. The new
>> structure more resembles traditional page tables with registers defining
>> page directory base.
>> 
>> The latter two changes were the real challenge in enabling the platform
>> and getting things to actually work - though in hindsight, they seem so
>> trivial :-)
>> 
>> You may find these patches here:
>> http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell
>> 
>> I'll be posting patches for libdrm, and intel-gpu-tools in the next day
>> or two.  They are also ready to go, I just need to do a quick once over.
>> At this point, feel free to stop reading.
>
> Also note that we've spent a decent amount of time refactoring the
> relevant areas in upstream, so now the massive changes for bdw mostly just
> plug in ...
>
> Anyway, review plan. Like Ben said this is still hidden behind the
> preliminary hw support knob. Also I want to get this all merged, final
> testing done and pull request sent by the end of the week. That way we can
> easily get it into 3.13 and that should also reduce the mess I currently
> have with the -internal branch. So
> - Please check register defines really through-roughly.
> - Check for erregious logic fumbles (e.g. in cleanup paths).
> - For everything else which can't be fixed quickly please just propose a
>   FIXME comment.
>
> I've just grabbed a bunch of names from our team and then tried to not
> come up with a too bad split for reviewing:
> Mika: Patches 1-6
> Chris: Patches 7-12
> Paulo: Patches 13-17
> Imre: Patches 18-23
> Damien: Patches 24-29
> Rodrigo: Patches 30-35
> Ville: Patches 36-42
> Ben: Patches 43-47
> Jani: Patches 48-53

I admit defeat with patch 51, maybe someone who's looked at ring
frequencies before could have a peek?

Jani.


> Jesse: Patches 54-58
> Daniel: Patche 59-62
>
> If the patches already has an r-b and hasn't been rebased like crazy since
> then you're lucky ;-)
>
> Please do the all the review on Mon/Tue so that I can spend Wed
> merging (and if needed, fixing up patches) and then we'll have 2 days or
> so for a bit of final integration testing.
>
> Thanks, Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 02/62] drm/i915/bdw: Handle forcewake for writes on gen8

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:00PM -0700, Ben Widawsky wrote:
> +static bool is_gen8_optimized(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	int i;
> +	for (i = 0; i < ARRAY_SIZE(gen8_optimized_regs); i++)
> +		if (reg == gen8_optimized_regs[i])
> +			return false;
> +
> +	return true;
> +}

The sense of this function is reversed, it really should be
is_gen8_legacy_register()? I'd prefer this to be an explicit switch() in
ascending order -- the compiler should emit an efficient bsearch.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority

[Ville Syrjälä]

On Sun, Nov 03, 2013 at 09:44:56AM -0800, Ben Widawsky wrote:
> On Sun, Nov 03, 2013 at 01:07:58PM +0200, Ville Syrjälä wrote:
> > On Sat, Nov 02, 2013 at 09:07:40PM -0700, Ben Widawsky wrote:
> > > GEN8 also needs this workaround.
> > 
> > Not according to the w/a database.
> > 
> > But the register description is the same for both HSW and BDW. Also for
> > HSW, the w/a doesn't actually say whether we should set or clear the bit.
> > the default is listed to be 0, so I guess we should set it, but then
> > it's unclear why BDW wouldn't need the w/a. Once again a very poorly
> > docuemnted w/a :(
> 
> Just an FYI: all workarounds for Broadwell came from the bspec, as the
> workaround database did not exist for Broadwell at that time.
> 
> Also, I was informally told not to trust the workaround database yet.

I can't find this w/a in bspec either, not even for HSW.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 16/62] drm/i915/bdw: debugfs updates

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:14PM -0700, Ben Widawsky wrote:
> All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
> later, I am certain.

Looks like this could be squashed into patch 2 as they both attach the
same infrastructure (swizzling).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 19/62] drm/i915/bdw: Create gen8_gtt_pte_t

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:17PM -0700, Ben Widawsky wrote:
> With gen6 PTE type in place, pave the way for the new gen8 type.

Wouldn't this patch make more sense before patch 18, so that we always
use sizeof(gen8_gtt_pte_t) rather than 8?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 21/62] drm/i915/bdw: Support BDW caching

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:19PM -0700, Ben Widawsky wrote:
> +static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
> +{
> +#define GEN8_PPAT_UC		(0<<0)
> +#define GEN8_PPAT_WC		(1<<0)
> +#define GEN8_PPAT_WT		(2<<0)
> +#define GEN8_PPAT_WB		(3<<0)
> +#define GEN8_PPAT_ELLC_OVERRIDE	(0<<2)
> +#define GEN8_PPAT_LLC		(1<<2)
> +#define GEN8_PPAT_LLCELLC	(2<<2)
> +#define GEN8_PPAT_LLCeLLC	(3<<2) /* BSPEC mistake? */
> +#define GEN8_PPAT_AGE(x)	(x<<4)
> +#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
> +	uint64_t pat;
> +
> +	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
> +	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
> +	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
> +	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
> +	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
> +	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
> +	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
> +	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> +
> +	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);

I915_WRITE64() or a scary-ass comment to explain why we cannot.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 03/62] drm/i915/bdw: Disable PPGTT for now

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:01PM -0700, Ben Widawsky wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> This will be changed once the gen8 code is fully implemented.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c4c42e7..77b3c74 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -410,6 +410,8 @@ static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
>  
>  	if (INTEL_INFO(dev)->gen < 8)
>  		ret = gen6_ppgtt_init(ppgtt);
> +	else if (IS_GEN8(dev))
> +		ret = -ENXIO;

Later on we use ENOSYS for disabling PPGTT before it is ready. Pick one.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 27/62] drm/i915/bdw: Implement PPGTT enable

[Damien Lespiau]

On Sat, Nov 02, 2013 at 09:07:25PM -0700, Ben Widawsky wrote:
> Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
> Since all rings are using the same address space with the current code
> the logic is simply to program all the tables we've setup for the PPGTT.
> 
> v2: Turn on PPGTT in GFX_MODE
> 
> v3: v2 was the wrong patch
> 
> v4: Resolve conflicts due to patch series reordering.
> 
> v5: Squash in fixup from Ben: Use LRI to write PDPs
> 
> The docs (and simulator seems to back up) suggest that we can only
> program legacy PPGTT PDPs with LRI commands.
> 
> v4: Rebase around context differences conflicts.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v3)
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

The bikeshed is a welcomed documentation addition (in a separate patch
or not)

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 50 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 27e157d..07892e2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -195,6 +195,55 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
>  	return pte;
>  }
>  
> +/* Broadwell Page Directory Pointer Descriptors */
> +static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
> +			   uint64_t val)
> +{
> +	int ret;
> +
> +	BUG_ON(entry >= 4);
> +
> +	ret = intel_ring_begin(ring, 6);
> +	if (ret)
> +		return ret;
> +
> +	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> +	intel_ring_emit(ring, ring->mmio_base + 0x270 + (entry * 8) + 4);
> +	intel_ring_emit(ring, (u32)(val >> 32));
> +	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> +	intel_ring_emit(ring, ring->mmio_base + 0x270 + (entry * 8));
> +	intel_ring_emit(ring, (u32)(val));
> +	intel_ring_advance(ring);

Could use a per ring define for this register (which is PDP0 afaict).

> +
> +	return 0;
> +}
> +
> +static int gen8_ppgtt_enable(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	struct intel_ring_buffer *ring;
> +	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
> +	int i, j, ret;
> +
> +	/* bit of a hack to find the actual last used pd */
> +	int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
> +
> +	for_each_ring(ring, dev_priv, j) {
> +		I915_WRITE(RING_MODE_GEN7(ring),
> +			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> +	}
> +
> +	for (i = used_pd - 1; i >= 0; i--) {
> +		dma_addr_t addr = ppgtt->pd_dma_addr[i];
> +		for_each_ring(ring, dev_priv, j) {
> +			ret = gen8_write_pdp(ring, i, addr);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +	return 0;
> +}
> +
>  static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
>  				   unsigned first_entry,
>  				   unsigned num_entries,
> @@ -326,6 +375,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
>  	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
>  	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
>  	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
> +	ppgtt->enable = gen8_ppgtt_enable;
>  	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
>  	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
>  	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/62] [v6] drm/i915/bdw: Add device IDs

[Chris Wilson]

On Sun, Nov 03, 2013 at 04:36:58PM -0800, Ben Widawsky wrote:
> v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
> suggested by Damien.
> 
> v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
> 
> v4: Rebase on top of Jesse's patch to extract all pci ids to
> include/drm/i915_pciids.h.
> 
> v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
> 
> v5: Switch from info->has*ring to info->ring_mask.
> 
> v6: Add 0x16X2 variant (which is newer than this patch)
> Rename to use new naming scheme (Chris)
> Remove Simulator PCI ids. These snuck in during rebase (Chris)
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

As a paranoid question, are we sure we have all pci-ids reserved?

The actual addition of the pci-ids should be the last patch in the
series.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 23/62] drm/i915/bdw: PPGTT init & cleanup

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 7502 bytes --]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> Aside from the potential size increase of the PPGTT, the primary
> difference from previous hardware is the Page Directories are no longer
> carved out of the Global GTT.
> 
> Note that the PDE allocation is done as a 8MB contiguous allocation,
> this needs to be eventually fixed (since driver reloading will be a
> pain otherwise). Also, this will be a no-go for real PPGTT support.
> 
> v2: Move vtable initialization
> 
> v3: Resolve conflicts due to patch series reordering.
> 
> v4: Rebase on top of the address space refactoring of the PPGTT
> support. Drop Imre's r-b tag for v2, too outdated by now.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v2)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     |  19 ++++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 123 +++++++++++++++++++++++++++++++++++-
>  2 files changed, 137 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 83d016c..97b0905 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -572,10 +572,21 @@ struct i915_gtt {
>  struct i915_hw_ppgtt {
>  	struct i915_address_space base;
>  	unsigned num_pd_entries;
> -	struct page **pt_pages;
> -	uint32_t pd_offset;
> -	dma_addr_t *pt_dma_addr;
> -
> +	union {
> +		struct page **pt_pages;
> +		struct page *gen8_pt_pages;
> +	};
> +	struct page *pd_pages;
> +	int num_pd_pages;
> +	int num_pt_pages;
> +	union {
> +		uint32_t pd_offset;
> +		dma_addr_t pd_dma_addr[4];
> +	};
> +	union {
> +		dma_addr_t *pt_dma_addr;
> +		dma_addr_t *gen8_pt_dma_addr[4];
> +	};
>  	int (*enable)(struct drm_device *dev);
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 02de12d..4a11f51 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -31,6 +31,7 @@
>  #define GEN6_PPGTT_PD_ENTRIES 512
>  #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
>  typedef uint64_t gen8_gtt_pte_t;
> +typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
>  
>  /* PPGTT stuff */
>  #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
> @@ -58,6 +59,9 @@ typedef uint64_t gen8_gtt_pte_t;
>  #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
>  #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
>  
> +#define GEN8_PDES_PER_PAGE		(PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
> +#define GEN8_LEGACY_PDPS		4
> +
>  #define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
>  #define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
>  #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
> @@ -177,6 +181,123 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
>  	return pte;
>  }
>  
> +static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> +{
> +	struct i915_hw_ppgtt *ppgtt =
> +		container_of(vm, struct i915_hw_ppgtt, base);
> +	int i, j;
> +
> +	for (i = 0; i < ppgtt->num_pd_pages ; i++) {
> +		if (ppgtt->pd_dma_addr[i]) {
> +			pci_unmap_page(ppgtt->base.dev->pdev,
> +				       ppgtt->pd_dma_addr[i],
> +				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
> +
> +			for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
> +				dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
> +				if (addr)
> +					pci_unmap_page(ppgtt->base.dev->pdev,
> +						       addr,
> +						       PAGE_SIZE,
> +						       PCI_DMA_BIDIRECTIONAL);
> +
> +			}
> +		}
> +		kfree(ppgtt->gen8_pt_dma_addr[i]);
> +	}
> +
> +	__free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages));
> +	__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages));

get_order takes size not a page count. With that fixed:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +}
> +
> +/**
> + * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
> + * net effect resembling a 2-level page table in normal x86 terms. Each PDP
> + * represents 1GB of memory
> + * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
> + *
> + * TODO: Do something with the size parameter
> + **/
> +static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
> +{
> +	struct page *pt_pages;
> +	int i, j, ret = -ENOMEM;
> +	const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
> +	const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
> +
> +	if (size % (1<<30))
> +		DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
> +
> +	/* FIXME: split allocation into smaller pieces. For now we only ever do
> +	 * this once, but with full PPGTT, the multiple contiguous allocations
> +	 * will be bad.
> +	 */
> +	ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
> +	if (!ppgtt->pd_pages)
> +		return -ENOMEM;
> +
> +	pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
> +	if (!pt_pages) {
> +		__free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
> +		return -ENOMEM;
> +	}
> +
> +	ppgtt->gen8_pt_pages = pt_pages;
> +	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
> +	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
> +	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
> +	ppgtt->base.clear_range = NULL;
> +	ppgtt->base.insert_entries = NULL;
> +	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
> +
> +	BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
> +
> +	/*
> +	 * - Create a mapping for the page directories.
> +	 * - For each page directory:
> +	 *      allocate space for page table mappings.
> +	 *      map each page table
> +	 */
> +	for (i = 0; i < max_pdp; i++) {
> +		dma_addr_t temp;
> +		temp = pci_map_page(ppgtt->base.dev->pdev,
> +				    &ppgtt->pd_pages[i], 0,
> +				    PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
> +		if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
> +			goto err_out;
> +
> +		ppgtt->pd_dma_addr[i] = temp;
> +
> +		ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
> +		if (!ppgtt->gen8_pt_dma_addr[i])
> +			goto err_out;
> +
> +		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
> +			struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
> +			temp = pci_map_page(ppgtt->base.dev->pdev,
> +					    p, 0, PAGE_SIZE,
> +					    PCI_DMA_BIDIRECTIONAL);
> +
> +			if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
> +				goto err_out;
> +
> +			ppgtt->gen8_pt_dma_addr[i][j] = temp;
> +		}
> +	}
> +
> +	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
> +			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
> +	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
> +			 ppgtt->num_pt_pages,
> +			 (ppgtt->num_pt_pages - num_pt_pages) +
> +			 size % (1<<30));
> +	return -ENOSYS; /* Not ready yet */
> +
> +err_out:
> +	ppgtt->base.cleanup(&ppgtt->base);
> +	return ret;
> +}
> +
>  static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
>  {
>  	struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
> @@ -430,7 +551,7 @@ static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen < 8)
>  		ret = gen6_ppgtt_init(ppgtt);
>  	else if (IS_GEN8(dev))
> -		ret = -ENXIO;
> +		ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
>  	else
>  		BUG();
>  


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_______________________________________________
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Re: [PATCH 00/62] Broadwell kernel driver support

[Damien Lespiau]

On Sun, Nov 03, 2013 at 09:45:49AM +0100, Daniel Vetter wrote:
> Damien: Patches 24-29

Patches were reviewed, had a glance at them to try to spot anything a
rebase could have done to them with two small improvements that can be
addressed with 2 patches on top if we want to merge things in the next 2
days.

-- 
Damien

Re: [PATCH 63/62] drm/i915/bdw: Enable trickle feed on Broadwell

[Damien Lespiau]

On Sun, Nov 03, 2013 at 01:47:27PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Like on HSW, trickle feed should always be enabled on BDW.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
> Not sure this applies directly, I just put it together on top of -nightly.
> Thus it's not even compile tested.
> 
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f34252d..4539550 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2156,7 +2156,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
>  	else
>  		dspcntr &= ~DISPPLANE_TILED;
>  
> -	if (IS_HASWELL(dev))
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
>  	else
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8afaad6..2bcee75 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -260,7 +260,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	if (obj->tiling_mode != I915_TILING_NONE)
>  		sprctl |= SPRITE_TILED;
>  
> -	if (IS_HASWELL(dev))
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
>  	else
>  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
> -- 
> 1.8.1.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/62] [v6] drm/i915/bdw: Add device IDs

[Daniel Vetter]

On Mon, Nov 04, 2013 at 02:49:21PM +0000, Chris Wilson wrote:
> On Sun, Nov 03, 2013 at 04:36:58PM -0800, Ben Widawsky wrote:
> > v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
> > suggested by Damien.
> > 
> > v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
> > 
> > v4: Rebase on top of Jesse's patch to extract all pci ids to
> > include/drm/i915_pciids.h.
> > 
> > v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
> > 
> > v5: Switch from info->has*ring to info->ring_mask.
> > 
> > v6: Add 0x16X2 variant (which is newer than this patch)
> > Rename to use new naming scheme (Chris)
> > Remove Simulator PCI ids. These snuck in during rebase (Chris)
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> As a paranoid question, are we sure we have all pci-ids reserved?
> 
> The actual addition of the pci-ids should be the last patch in the
> series.

Since all of bdw is currently hidden behind the preliminary hw support
knob the actual order doesn't actually matter. And imo it's fairly natural
to have the pci ids as one of the first things, since for bringup getting
the display going is fairly late work usually.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 04/62] [v6] drm/i915/bdw: Add device IDs

[Chris Wilson]

On Mon, Nov 04, 2013 at 04:49:54PM +0100, Daniel Vetter wrote:
> On Mon, Nov 04, 2013 at 02:49:21PM +0000, Chris Wilson wrote:
> > On Sun, Nov 03, 2013 at 04:36:58PM -0800, Ben Widawsky wrote:
> > > v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
> > > suggested by Damien.
> > > 
> > > v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
> > > 
> > > v4: Rebase on top of Jesse's patch to extract all pci ids to
> > > include/drm/i915_pciids.h.
> > > 
> > > v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
> > > 
> > > v5: Switch from info->has*ring to info->ring_mask.
> > > 
> > > v6: Add 0x16X2 variant (which is newer than this patch)
> > > Rename to use new naming scheme (Chris)
> > > Remove Simulator PCI ids. These snuck in during rebase (Chris)
> > > 
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > 
> > As a paranoid question, are we sure we have all pci-ids reserved?
> > 
> > The actual addition of the pci-ids should be the last patch in the
> > series.
> 
> Since all of bdw is currently hidden behind the preliminary hw support
> knob the actual order doesn't actually matter. And imo it's fairly natural
> to have the pci ids as one of the first things, since for bringup getting
> the display going is fairly late work usually.

It more that we disable core functionality after this patch. That feels
wrong, even with the prelim knob we shouldn't be expecting this patch to
cause the hw or kernel to explode.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 04/62] [v6] drm/i915/bdw: Add device IDs

[Ben Widawsky]

On Mon, Nov 04, 2013 at 02:49:21PM +0000, Chris Wilson wrote:
> On Sun, Nov 03, 2013 at 04:36:58PM -0800, Ben Widawsky wrote:
> > v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
> > suggested by Damien.
> > 
> > v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
> > 
> > v4: Rebase on top of Jesse's patch to extract all pci ids to
> > include/drm/i915_pciids.h.
> > 
> > v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
> > 
> > v5: Switch from info->has*ring to info->ring_mask.
> > 
> > v6: Add 0x16X2 variant (which is newer than this patch)
> > Rename to use new naming scheme (Chris)
> > Remove Simulator PCI ids. These snuck in during rebase (Chris)
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> As a paranoid question, are we sure we have all pci-ids reserved?
> 

I'll never say I am sure. This includes everything in the bspec, and
ones which aren't supposed to ship. I feel bad about adding those, since
in theory - they could end up in some other product. Since we saw it
happen on HSW though, I figured better safe than sorry.

> 
-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 55/62] drm/i915/bdw: Disable semaphores

[Jesse Barnes]

On Sat,  2 Nov 2013 21:07:53 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> From: Ben Widawsky <ben@bwidawsk.net>
> 
> We've done insufficient testing on them thus far, so keep them disabled
> until we do test.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 590d999..efb63b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -478,6 +478,12 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen < 6)
>  		return 0;
>  
> +	/* Until we get further testing... */
> +	if (IS_GEN8(dev)) {
> +		DRM_INFO("Semaphores disabled GEN8\n");
> +		return 0;
> +	}
> +
>  	if (i915_semaphores >= 0)
>  		return i915_semaphores;
>  

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Side note; for stuff like this where we disable a critical feature
(e.g. PPGTT, semaphores) with the intention of enabling it later, maybe
we should do a WARN or something if preliminary hw support is enabled.
Or somehow catch it so we have to address it before declaring the bits
good.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 54/62] drm/i915/bdw: Create a separate BDW rps enable

[Jesse Barnes]

On Sat,  2 Nov 2013 21:07:52 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> This is mostly what we have for HSW with the exceptions of:
> no writes:
>   GEN6_RC1_WAKE_RATE_LIMIT
>   GEN6_RC6pp_WAKE_RATE_LIMIT
>   GEN6_RC1e_THRESHOLD
>   GEN6_RC6p_THRESHOLD
>   GEN6_RC6pp_THRESHOLD
> 
> GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s
> 
> Don't try to overclock, or program ring/IA frequency tables since we
> don't quite have sufficient docs yet.
> 
> NOTE: These values do not reflect the changes made recently by Chris.
> Since we have no evidence yet what the proper way to tweak for this
> platform is, I think it is good to go, and can be optimized by Chris, or
> whomever, later.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> [danvet: Drop spurious hunk and drop TODO - having per-platform rps
> register frobbing code is in my opinion preferred, now that all the
> infrastructure functions are extracted.]
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 75 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3dd30f7..0245985 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3762,6 +3762,78 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
>  	I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
>  }
>  
> +static void gen8_enable_rps(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_ring_buffer *ring;
> +	uint32_t rc6_mask = 0, rp_state_cap;
> +	int unused;
> +
> +	/* 1a: Software RC state - RC0 */
> +	I915_WRITE(GEN6_RC_STATE, 0);
> +
> +	/* 1c & 1d: Get forcewake during program sequence. Although the driver
> +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> +	gen6_gt_force_wake_get(dev_priv);
> +
> +	/* 2a: Disable RC states. */
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> +	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> +
> +	/* 2b: Program RC6 thresholds.*/
> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> +	for_each_ring(ring, dev_priv, unused)
> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +	I915_WRITE(GEN6_RC_SLEEP, 0);
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> +
> +	/* 3: Enable RC6 */
> +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
> +		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> +	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
> +	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +			GEN6_RC_CTL_EI_MODE(1) |
> +			rc6_mask);
> +
> +	/* 4 Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
> +	I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
> +	/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
> +
> +	/* Docs recommend 900MHz, and 300 MHz respectively */
> +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> +		   dev_priv->rps.max_delay << 24 |
> +		   dev_priv->rps.min_delay << 16);
> +
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
> +	I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
> +	I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
> +
> +	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> +	/* 5: Enable RPS */
> +	I915_WRITE(GEN6_RP_CONTROL,
> +		   GEN6_RP_MEDIA_TURBO |
> +		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> +		   GEN6_RP_MEDIA_IS_GFX |
> +		   GEN6_RP_ENABLE |
> +		   GEN6_RP_UP_BUSY_AVG |
> +		   GEN6_RP_DOWN_IDLE_AVG);
> +
> +	/* 6: Ring frequency + overclocking (our driver does this later */
> +
> +	gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
> +
> +	gen6_enable_rps_interrupts(dev);
> +
> +	gen6_gt_force_wake_put(dev_priv);
> +}
> +
>  static void gen6_enable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4891,6 +4963,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		valleyview_enable_rps(dev);
> +	} else if (IS_BROADWELL(dev)) {
> +		gen8_enable_rps(dev);
> +		gen6_update_ring_freq(dev);
>  	} else {
>  		gen6_enable_rps(dev);
>  		gen6_update_ring_freq(dev);

Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 18/62] drm/i915/bdw: Make gen8_gmch_probe

[Imre Deak]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> Probing gen8 is similar to gen6. To make the code cleaner and more
> maintainable however we can use the probe functions to split it out.
> 
> v2: Rebased on top of update gtt probe infrastructure.
> 
> v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.
> 
> V4: Resolve conflicts with Ben's latest ppgtt patches, also switch to
> gen < 8 testing instead of gen <= 7.
> 
> v5: Resolve conflicts with address space vfunc changes in upstream.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++++++++++++++++++++++++++----------
>  1 file changed, 68 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 19016b7..c6d38d0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -892,6 +892,66 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
>  	return bdw_gmch_ctl << 25; /* 32 MB units */
>  }
>  
> +static int ggtt_probe_common(struct drm_device *dev,
> +			     size_t gtt_size)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	phys_addr_t gtt_bus_addr;
> +	int ret;
> +
> +	/* For Modern GENs the PTEs and register space are split in the BAR */
> +	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
> +		(pci_resource_len(dev->pdev, 0) / 2);
> +
> +	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
> +	if (!dev_priv->gtt.gsm) {
> +		DRM_ERROR("Failed to map the gtt page table\n");
> +		return -ENOMEM;
> +	}
> +
> +	ret = setup_scratch_page(dev);
> +	if (ret) {
> +		DRM_ERROR("Scratch setup failed\n");
> +		/* iounmap will also get called at remove, but meh */
> +		iounmap(dev_priv->gtt.gsm);
> +	}
> +
> +	return ret;
> +}
> +
> +static int gen8_gmch_probe(struct drm_device *dev,
> +			   size_t *gtt_total,
> +			   size_t *stolen,
> +			   phys_addr_t *mappable_base,
> +			   unsigned long *mappable_end)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned int gtt_size;
> +	u16 snb_gmch_ctl;
> +	int ret;
> +
> +	/* TODO: We're not aware of mappable constraints on gen8 yet */
> +	*mappable_base = pci_resource_start(dev->pdev, 2);
> +	*mappable_end = pci_resource_len(dev->pdev, 2);
> +
> +	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
> +		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));

Not that this would be a practical problem, but according to bspec the
maximum physical address size is 39 bits for all PTE formats. Is that a
documentation error? (SNB supported 40 bits)

Other than this the patch looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
> +
> +	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
> +
> +	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
> +	*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
> +
> +	ret = ggtt_probe_common(dev, gtt_size);
> +
> +	dev_priv->gtt.base.clear_range = NULL;
> +	dev_priv->gtt.base.insert_entries = NULL;
> +
> +	return ret;
> +}
> +
>  static int gen6_gmch_probe(struct drm_device *dev,
>  			   size_t *gtt_total,
>  			   size_t *stolen,
> @@ -899,7 +959,6 @@ static int gen6_gmch_probe(struct drm_device *dev,
>  			   unsigned long *mappable_end)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	phys_addr_t gtt_bus_addr;
>  	unsigned int gtt_size;
>  	u16 snb_gmch_ctl;
>  	int ret;
> @@ -920,30 +979,12 @@ static int gen6_gmch_probe(struct drm_device *dev,
>  		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
>  	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
>  
> -	if (IS_GEN8(dev)) {
> -		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
> -		*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
> -		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
> -	} else {
> -		gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
> -		*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
> -		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
> -	}
> -
> -	/* For Modern GENs the PTEs and register space are split in the BAR */
> -	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
> -		(pci_resource_len(dev->pdev, 0) / 2);
> -
> -	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
> -	if (!dev_priv->gtt.gsm) {
> -		DRM_ERROR("Failed to map the gtt page table\n");
> -		return -ENOMEM;
> +	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
>  
> -	}
> +	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
> +	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
>  
> -	ret = setup_scratch_page(dev);
> -	if (ret)
> -		DRM_ERROR("Scratch setup failed\n");
> +	ret = ggtt_probe_common(dev, gtt_size);
>  
>  	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
>  	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
> @@ -997,7 +1038,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen <= 5) {
>  		gtt->gtt_probe = i915_gmch_probe;
>  		gtt->base.cleanup = i915_gmch_remove;
> -	} else {
> +	} else if (INTEL_INFO(dev)->gen < 8) {
>  		gtt->gtt_probe = gen6_gmch_probe;
>  		gtt->base.cleanup = gen6_gmch_remove;
>  		if (IS_HASWELL(dev) && dev_priv->ellc_size)
> @@ -1010,6 +1051,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
>  			gtt->base.pte_encode = ivb_pte_encode;
>  		else
>  			gtt->base.pte_encode = snb_pte_encode;
> +	} else {
> +		dev_priv->gtt.gtt_probe = gen8_gmch_probe;
> +		dev_priv->gtt.base.cleanup = gen6_gmch_remove;
>  	}
>  
>  	ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,

Re: [PATCH 19/62] drm/i915/bdw: Create gen8_gtt_pte_t

[Imre Deak]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> With gen6 PTE type in place, pave the way for the new gen8 type.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c6d38d0..8bf2184 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -30,6 +30,7 @@
>  
>  #define GEN6_PPGTT_PD_ENTRIES 512
>  #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
> +typedef uint64_t gen8_gtt_pte_t;
>  
>  /* PPGTT stuff */
>  #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
> @@ -942,7 +943,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
>  	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
>  
>  	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
> -	*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
> +	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
>  
>  	ret = ggtt_probe_common(dev, gtt_size);
>  

Re: [PATCH 20/62] drm/i915/bdw: Add GTT functions

[Imre Deak]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> With the PTE clarifications, the bind and clear functions can now be
> added for gen8.
> 
> v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.
> 
> v3: Drop dev argument to pte encode functions, upstream lost it. Also
> rebase on top of the scratch page movement.
> 
> v4: Rebase on top of the new address space vfuncs.
> 
> v5: Add the bool use_scratch argument to clear_range and the bool valid argument
> to the PTE encode function to follow upstream changes.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++++++++++++++++++++++++++++++++++--
>  1 file changed, 85 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8bf2184..df992dc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -58,6 +58,15 @@ typedef uint64_t gen8_gtt_pte_t;
>  #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
>  #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
>  
> +static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
> +					     enum i915_cache_level level,
> +					     bool valid)
> +{
> +	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
> +	pte |= addr;
> +	return pte;
> +}
> +
>  static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
>  				     enum i915_cache_level level,
>  				     bool valid)
> @@ -576,6 +585,56 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
>  	return 0;
>  }
>  
> +static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
> +{
> +#ifdef writeq
> +	writeq(pte, addr);
> +#else
> +	iowrite32((u32)pte, addr);
> +	iowrite32(pte >> 32, addr + 4);
> +#endif
> +}
> +
> +static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> +				     struct sg_table *st,
> +				     unsigned int first_entry,
> +				     enum i915_cache_level level)
> +{
> +	struct drm_i915_private *dev_priv = vm->dev->dev_private;
> +	gen8_gtt_pte_t __iomem *gtt_entries =
> +		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
> +	int i = 0;
> +	struct sg_page_iter sg_iter;
> +	dma_addr_t addr;
> +
> +	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
> +		addr = sg_dma_address(sg_iter.sg) +
> +			(sg_iter.sg_pgoffset << PAGE_SHIFT);
> +		gen8_set_pte(&gtt_entries[i],
> +			     gen8_pte_encode(addr, level, true));
> +		i++;
> +	}
> +
> +	/* XXX: This serves as a posting read to make sure that the PTE has
> +	 * actually been updated. There is some concern that even though
> +	 * registers and PTEs are within the same BAR that they are potentially
> +	 * of NUMA access patterns. Therefore, even with the way we assume
> +	 * hardware should work, we must keep this posting read for paranoia.
> +	 */
> +	if (i != 0)
> +		WARN_ON(readl(&gtt_entries[i-1])
> +			!= gen8_pte_encode(addr, level, true));
> +
> +#if 0 /* TODO: Still needed on GEN8? */
> +	/* This next bit makes the above posting read even more important. We
> +	 * want to flush the TLBs only after we're certain all the PTE updates
> +	 * have finished.
> +	 */
> +	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> +	POSTING_READ(GFX_FLSH_CNTL_GEN6);
> +#endif
> +}
> +
>  /*
>   * Binds an object into the global gtt with the specified cache level. The object
>   * will be accessible to the GPU via commands whose operands reference offsets
> @@ -618,6 +677,30 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
>  	POSTING_READ(GFX_FLSH_CNTL_GEN6);
>  }
>  
> +static void gen8_ggtt_clear_range(struct i915_address_space *vm,
> +				  unsigned int first_entry,
> +				  unsigned int num_entries,
> +				  bool use_scratch)
> +{
> +	struct drm_i915_private *dev_priv = vm->dev->dev_private;
> +	gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
> +		(gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
> +	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
> +	int i;
> +
> +	if (WARN(num_entries > max_entries,
> +		 "First entry = %d; Num entries = %d (max=%d)\n",
> +		 first_entry, num_entries, max_entries))
> +		num_entries = max_entries;
> +
> +	scratch_pte = gen8_pte_encode(vm->scratch.addr,
> +				      I915_CACHE_LLC,
> +				      use_scratch);
> +	for (i = 0; i < num_entries; i++)
> +		gen8_set_pte(&gtt_base[i], scratch_pte);
> +	readl(gtt_base);
> +}
> +
>  static void gen6_ggtt_clear_range(struct i915_address_space *vm,
>  				  unsigned int first_entry,
>  				  unsigned int num_entries,
> @@ -641,7 +724,6 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
>  	readl(gtt_base);
>  }
>  
> -
>  static void i915_ggtt_insert_entries(struct i915_address_space *vm,
>  				     struct sg_table *st,
>  				     unsigned int pg_start,
> @@ -947,8 +1029,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
>  
>  	ret = ggtt_probe_common(dev, gtt_size);
>  
> -	dev_priv->gtt.base.clear_range = NULL;
> -	dev_priv->gtt.base.insert_entries = NULL;
> +	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
> +	dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
>  
>  	return ret;
>  }

Re: [PATCH 43/62] drm/i915/bdw: Add BDW DDI buffer translation values

[Ben Widawsky]

On Sat, Nov 02, 2013 at 09:07:41PM -0700, Ben Widawsky wrote:
> From: Art Runyan <arthur.j.runyan@intel.com>
> 
> Many of the DDI buffer translation values have changed for BDW.
> Add new translation tables and selection between HSW and BDW.
> 
> v2: s/BUG/WARN/ to avoid breaking future GENs.
> 
> v3: Rebase on top of the hdmi translation table changes.
> 
> Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 52 ++++++++++++++++++++++++++++++++++++----
>  1 file changed, 47 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index db848a9..4baf3cd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -72,6 +72,32 @@ static const u32 hsw_ddi_translations_hdmi[] = {
>  	0x80FFFFFF, 0x00030002, /* 11:	1000		1000		0   */
>  };
>  
> +static const u32 bdw_ddi_translations_dp[] = {
> +	0x00FFFFFF, 0x0007000E,		/* DP parameters */
> +	0x00D75FFF, 0x000E000A,
> +	0x00BEFFFF, 0x00140006,
> +	0x00FFFFFF, 0x000E000A,
> +	0x00D75FFF, 0x00180004,
> +	0x80CB2FFF, 0x001B0002,
> +	0x00F7DFFF, 0x00180004,
> +	0x80D75FFF, 0x001B0002,
> +	0x80FFFFFF, 0x001B0002,
> +	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
> +};
> +
> +static const u32 bdw_ddi_translations_fdi[] = {
> +	0x00FFFFFF, 0x0001000E,		/* FDI parameters */
> +	0x00D75FFF, 0x0004000A,
> +	0x00C30FFF, 0x00070006,
> +	0x00AAAFFF, 0x000C0000,
> +	0x00FFFFFF, 0x0004000A,
> +	0x00D75FFF, 0x00090004,
> +	0x00C30FFF, 0x000C0000,
> +	0x00FFFFFF, 0x00070006,
> +	0x00D75FFF, 0x000C0000,
> +	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
> +};
> +
>  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>  {
>  	struct drm_encoder *encoder = &intel_encoder->base;
> @@ -92,8 +118,8 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
>  	}
>  }
>  
> -/* On Haswell, DDI port buffers must be programmed with correct values
> - * in advance. The buffer values are different for FDI and DP modes,
> +/* Starting with Haswell, DDI port buffers must be programmed with correct
> + * values in advance. The buffer values are different for FDI and DP modes,
>   * but the HDMI/DVI fields are shared among those. So we program the DDI
>   * in either FDI or DP modes only, as HDMI connections will work with both
>   * of those
> @@ -103,10 +129,26 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 reg;
>  	int i;
> -	const u32 *ddi_translations = (port == PORT_E) ?
> -		hsw_ddi_translations_fdi :
> -		hsw_ddi_translations_dp;
>  	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> +	const u32 *ddi_translations_fdi;
> +	const u32 *ddi_translations_dp;
> +	const u32 *ddi_translations;
> +
> +	if (IS_BROADWELL(dev)) {
> +		ddi_translations_fdi = bdw_ddi_translations_fdi;
> +		ddi_translations_dp = bdw_ddi_translations_dp;
> +	} else if (IS_HASWELL(dev)) {
> +		ddi_translations_fdi = hsw_ddi_translations_fdi;
> +		ddi_translations_dp = hsw_ddi_translations_dp;
> +	} else {
> +		WARN(1, "ddi translation table missing\n");
> +		ddi_translations_fdi = bdw_ddi_translations_fdi;
> +		ddi_translations_dp = bdw_ddi_translations_dp;
> +	}
> +
> +	ddi_translations = ((port == PORT_E) ?
> +		ddi_translations_fdi :
> +		ddi_translations_dp);
>  
>  	for (i = 0, reg = DDI_BUF_TRANS(port);
>  	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {

I guess this should be ARRAY_SIZE - 1 since we seem to overwrite the 10th
entry regardless of what VBT tells us. Not this patches'  problem
though. Similarly, added all 10 entries to the table seems weird to me.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>


-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 44/62] drm/i915/bdw: add BDW DDI buf translations for eDP

[Ben Widawsky]

On Sat, Nov 02, 2013 at 09:07:42PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Broadwell has different DDI buffer translations for eDP and DP, so add
> support for the missing eDP and keep Haswell the same.
> 
> A future patch addresses the suggestion from Art to check for eDP on
> port D and use the eDP values there, too.
> 
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 38 +++++++++++++++++++++++++++++++++-----
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 4baf3cd..3868ed9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -72,6 +72,19 @@ static const u32 hsw_ddi_translations_hdmi[] = {
>  	0x80FFFFFF, 0x00030002, /* 11:	1000		1000		0   */
>  };
>  
> +static const u32 bdw_ddi_translations_edp[] = {
> +	0x00FFFFFF, 0x00000012,		/* DP parameters */
> +	0x00EBAFFF, 0x00020011,
> +	0x00C71FFF, 0x0006000F,
> +	0x00FFFFFF, 0x00020011,
> +	0x00DB6FFF, 0x0005000F,
> +	0x00BEEFFF, 0x000A000C,
> +	0x00FFFFFF, 0x0005000F,
> +	0x00DB6FFF, 0x000A000C,
> +	0x00FFFFFF, 0x000A000C,
> +	0x00FFFFFF, 0x00140006		/* HDMI parameters 800mV 0dB*/
> +};
> +
>  static const u32 bdw_ddi_translations_dp[] = {
>  	0x00FFFFFF, 0x0007000E,		/* DP parameters */
>  	0x00D75FFF, 0x000E000A,
> @@ -132,26 +145,41 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
>  	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  	const u32 *ddi_translations_fdi;
>  	const u32 *ddi_translations_dp;
> +	const u32 *ddi_translations_edp;
>  	const u32 *ddi_translations;
>  
>  	if (IS_BROADWELL(dev)) {
>  		ddi_translations_fdi = bdw_ddi_translations_fdi;
>  		ddi_translations_dp = bdw_ddi_translations_dp;
> +		ddi_translations_edp = bdw_ddi_translations_edp;
>  	} else if (IS_HASWELL(dev)) {
>  		ddi_translations_fdi = hsw_ddi_translations_fdi;
>  		ddi_translations_dp = hsw_ddi_translations_dp;
> +		ddi_translations_edp = hsw_ddi_translations_dp;
>  	} else {
>  		WARN(1, "ddi translation table missing\n");
> +		ddi_translations_edp = bdw_ddi_translations_dp;
>  		ddi_translations_fdi = bdw_ddi_translations_fdi;
>  		ddi_translations_dp = bdw_ddi_translations_dp;
>  	}
>  
> -	ddi_translations = ((port == PORT_E) ?
> -		ddi_translations_fdi :
> -		ddi_translations_dp);
> +	switch (port) {
> +	case PORT_A:
> +		ddi_translations = ddi_translations_edp;
> +		break;
> +	case PORT_B:
> +	case PORT_C:
> +	case PORT_D:
> +		ddi_translations = ddi_translations_dp;
> +		break;
> +	case PORT_E:
> +		ddi_translations = ddi_translations_fdi;
> +		break;
> +	default:
> +		BUG();
> +	}
>  
> -	for (i = 0, reg = DDI_BUF_TRANS(port);
> -	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> +	for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {

Daniel, maybe fix up this for checkpatch in merge? I don't care either
way.

>  		I915_WRITE(reg, ddi_translations[i]);
>  		reg += 4;
>  	}

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 45/62] drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis

[Ben Widawsky]

On Sat, Nov 02, 2013 at 09:07:43PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> They're not the same as the Haswell ones.
> 
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++
>  drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++---
>  2 files changed, 63 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4131223..6f834b3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5176,6 +5176,7 @@
>  #define DDI_BUF_CTL_B				0x64100
>  #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
>  #define  DDI_BUF_CTL_ENABLE			(1<<31)
> +/* Haswell */
>  #define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
>  #define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
>  #define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
> @@ -5185,6 +5186,16 @@
>  #define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
>  #define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
>  #define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
> +/* Broadwell */
> +#define  DDI_BUF_EMP_400MV_0DB_BDW		(0<<24)   /* Sel0 */
> +#define  DDI_BUF_EMP_400MV_3_5DB_BDW		(1<<24)   /* Sel1 */
> +#define  DDI_BUF_EMP_400MV_6DB_BDW		(2<<24)   /* Sel2 */
> +#define  DDI_BUF_EMP_600MV_0DB_BDW		(3<<24)   /* Sel3 */
> +#define  DDI_BUF_EMP_600MV_3_5DB_BDW		(4<<24)   /* Sel4 */
> +#define  DDI_BUF_EMP_600MV_6DB_BDW		(5<<24)   /* Sel5 */

Maybe I am misreading this, isn't this:
600mV, 4.5dB?

> +#define  DDI_BUF_EMP_800MV_0DB_BDW		(6<<24)   /* Sel6 */

850, .5

> +#define  DDI_BUF_EMP_800MV_3_5DB_BDW		(7<<24)   /* Sel7 */

750, 2.5

> +#define  DDI_BUF_EMP_1200MV_0DB_BDW		(8<<24)   /* Sel8 */

1000, 0

Sorry if I just misunderstood how you're getting these values.

>  #define  DDI_BUF_EMP_MASK			(0xf<<24)
>  #define  DDI_BUF_PORT_REVERSAL			(1<<16)
>  #define  DDI_BUF_IS_IDLE			(1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b3cc333..7725f81 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1950,7 +1950,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	enum port port = dp_to_dig_port(intel_dp)->port;
>  
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
>  		return DP_TRAIN_VOLTAGE_SWING_1200;
>  	else if (IS_GEN7(dev) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_800;
> @@ -1966,7 +1966,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	enum port port = dp_to_dig_port(intel_dp)->port;
>  
> -	if (HAS_DDI(dev)) {
> +	if (IS_BROADWELL(dev)) {
> +		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +		case DP_TRAIN_VOLTAGE_SWING_400:
> +		case DP_TRAIN_VOLTAGE_SWING_600:
> +			return DP_TRAIN_PRE_EMPHASIS_6;
> +		case DP_TRAIN_VOLTAGE_SWING_800:
> +			return DP_TRAIN_PRE_EMPHASIS_3_5;
> +		case DP_TRAIN_VOLTAGE_SWING_1200:
> +		default:
> +			return DP_TRAIN_PRE_EMPHASIS_0;
> +		}
> +	} else if (IS_HASWELL(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_400:
>  			return DP_TRAIN_PRE_EMPHASIS_9_5;
> @@ -2278,6 +2289,41 @@ intel_hsw_signal_levels(uint8_t train_set)
>  	}
>  }
>  
> +static uint32_t
> +intel_bdw_signal_levels(uint8_t train_set)
> +{
> +	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> +					 DP_TRAIN_PRE_EMPHASIS_MASK);
> +	switch (signal_levels) {
> +	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> +		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
> +	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +		return DDI_BUF_EMP_400MV_3_5DB_BDW;	/* Sel1 */
> +	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> +		return DDI_BUF_EMP_400MV_6DB_BDW;	/* Sel2 */
> +
> +	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> +		return DDI_BUF_EMP_600MV_0DB_BDW;	/* Sel3 */
> +	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +		return DDI_BUF_EMP_600MV_3_5DB_BDW;	/* Sel4 */
> +	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> +		return DDI_BUF_EMP_600MV_6DB_BDW;	/* Sel5 */
> +
> +	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> +		return DDI_BUF_EMP_800MV_0DB_BDW;	/* Sel6 */
> +	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> +		return DDI_BUF_EMP_800MV_3_5DB_BDW;	/* Sel7 */
> +
> +	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
> +		return DDI_BUF_EMP_1200MV_0DB_BDW;	/* Sel8 */
> +
> +	default:
> +		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> +			      "0x%x\n", signal_levels);
> +		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
> +	}
> +}
> +
>  /* Properly updates "DP" with the correct signal levels. */
>  static void
>  intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
> @@ -2288,7 +2334,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>  	uint32_t signal_levels, mask;
>  	uint8_t train_set = intel_dp->train_set[0];
>  
> -	if (HAS_DDI(dev)) {
> +	if (IS_BROADWELL(dev)) {
> +		signal_levels = intel_bdw_signal_levels(train_set);
> +		mask = DDI_BUF_EMP_MASK;
> +	} else if (IS_HASWELL(dev)) {
>  		signal_levels = intel_hsw_signal_levels(train_set);
>  		mask = DDI_BUF_EMP_MASK;
>  	} else if (IS_VALLEYVIEW(dev)) {

Forgive my ignorance, but I really have no idea how to review this
patch. Daniel, I think we have to settle for Art's r-b on this one, or
finds someone who understands why this programming is the way it is. (Or
wait)

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 47/62] drm/i915/bdw: check DPD on port D when setting the DDI buffers

[Ben Widawsky]

On Sat, Nov 02, 2013 at 09:07:45PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Use the eDP values on platforms where port D is eDP. This doesn't
> affect Haswell since it uses the same DDI buffer values for eDP and
> DP.
> 
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3868ed9..a4ddc7f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -169,9 +169,14 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
>  		break;
>  	case PORT_B:
>  	case PORT_C:
> -	case PORT_D:
>  		ddi_translations = ddi_translations_dp;
>  		break;
> +	case PORT_D:
> +		if (intel_dpd_is_edp(dev))
> +			ddi_translations = ddi_translations_edp;
> +		else
> +			ddi_translations = ddi_translations_dp;
> +		break;
>  	case PORT_E:
>  		ddi_translations = ddi_translations_fdi;
>  		break;

46 & 47 are:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 16/62] drm/i915/bdw: debugfs updates

[Ben Widawsky]

On Mon, Nov 04, 2013 at 02:28:55PM +0000, Chris Wilson wrote:
> On Sat, Nov 02, 2013 at 09:07:14PM -0700, Ben Widawsky wrote:
> > All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
> > later, I am certain.
> 
> Looks like this could be squashed into patch 2 as they both attach the
> same infrastructure (swizzling).
> -Chris
> 

Daniel, do you mind making the decision on this, and if you opt to
squash, do that on merge?

-- 
Ben Widawsky, Intel Open Source Technology Center

[PATCH 18/62] [v6] drm/i915/bdw: Make gen8_gmch_probe

[Ben Widawsky]

Probing gen8 is similar to gen6. To make the code cleaner and more
maintainable however we can use the probe functions to split it out.

v2: Rebased on top of update gtt probe infrastructure.

v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.

V4: Resolve conflicts with Ben's latest ppgtt patches, also switch to
gen < 8 testing instead of gen <= 7.

v5: Resolve conflicts with address space vfunc changes in upstream.

v6: Use 39b DMA mask. At least, for this mode, it is the correct mask.
(Imre)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++++++++++++++++++++++++++----------
 1 file changed, 68 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 19016b7..df6144e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -892,6 +892,66 @@ static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
 	return bdw_gmch_ctl << 25; /* 32 MB units */
 }
 
+static int ggtt_probe_common(struct drm_device *dev,
+			     size_t gtt_size)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	phys_addr_t gtt_bus_addr;
+	int ret;
+
+	/* For Modern GENs the PTEs and register space are split in the BAR */
+	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
+		(pci_resource_len(dev->pdev, 0) / 2);
+
+	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
+	if (!dev_priv->gtt.gsm) {
+		DRM_ERROR("Failed to map the gtt page table\n");
+		return -ENOMEM;
+	}
+
+	ret = setup_scratch_page(dev);
+	if (ret) {
+		DRM_ERROR("Scratch setup failed\n");
+		/* iounmap will also get called at remove, but meh */
+		iounmap(dev_priv->gtt.gsm);
+	}
+
+	return ret;
+}
+
+static int gen8_gmch_probe(struct drm_device *dev,
+			   size_t *gtt_total,
+			   size_t *stolen,
+			   phys_addr_t *mappable_base,
+			   unsigned long *mappable_end)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned int gtt_size;
+	u16 snb_gmch_ctl;
+	int ret;
+
+	/* TODO: We're not aware of mappable constraints on gen8 yet */
+	*mappable_base = pci_resource_start(dev->pdev, 2);
+	*mappable_end = pci_resource_len(dev->pdev, 2);
+
+	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
+		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
+
+	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+
+	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+
+	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
+
+	ret = ggtt_probe_common(dev, gtt_size);
+
+	dev_priv->gtt.base.clear_range = NULL;
+	dev_priv->gtt.base.insert_entries = NULL;
+
+	return ret;
+}
+
 static int gen6_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -899,7 +959,6 @@ static int gen6_gmch_probe(struct drm_device *dev,
 			   unsigned long *mappable_end)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	phys_addr_t gtt_bus_addr;
 	unsigned int gtt_size;
 	u16 snb_gmch_ctl;
 	int ret;
@@ -920,30 +979,12 @@ static int gen6_gmch_probe(struct drm_device *dev,
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	if (IS_GEN8(dev)) {
-		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
-		*gtt_total = (gtt_size / 8) << PAGE_SHIFT;
-		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
-	} else {
-		gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
-		*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
-		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
-	}
+	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
 
-	/* For Modern GENs the PTEs and register space are split in the BAR */
-	gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
-		(pci_resource_len(dev->pdev, 0) / 2);
+	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
+	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 
-	dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
-	if (!dev_priv->gtt.gsm) {
-		DRM_ERROR("Failed to map the gtt page table\n");
-		return -ENOMEM;
-
-	}
-
-	ret = setup_scratch_page(dev);
-	if (ret)
-		DRM_ERROR("Scratch setup failed\n");
+	ret = ggtt_probe_common(dev, gtt_size);
 
 	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
@@ -997,7 +1038,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen <= 5) {
 		gtt->gtt_probe = i915_gmch_probe;
 		gtt->base.cleanup = i915_gmch_remove;
-	} else {
+	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
 		if (IS_HASWELL(dev) && dev_priv->ellc_size)
@@ -1010,6 +1051,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
 			gtt->base.pte_encode = ivb_pte_encode;
 		else
 			gtt->base.pte_encode = snb_pte_encode;
+	} else {
+		dev_priv->gtt.gtt_probe = gen8_gmch_probe;
+		dev_priv->gtt.base.cleanup = gen6_gmch_remove;
 	}
 
 	ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
-- 
1.8.4.2

[PATCH 55/62] [v2] drm/i915/bdw: Disable semaphores

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

We've done insufficient testing on them thus far, so keep them disabled
until we do test.

v2: Use WARN when not enabling preliminary HW support as this should
only be disabled for that case.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e0a061b..45981c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -478,6 +478,13 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 6)
 		return 0;
 
+	/* Until we get further testing... */
+	if (IS_GEN8(dev)) {
+		WARN_ON(!i915_preliminary_hw_support);
+		DRM_INFO("Semaphores disabled GEN8\n");
+		return 0;
+	}
+
 	if (i915_semaphores >= 0)
 		return i915_semaphores;
 
-- 
1.8.4.2

[PATCH 21/62] [v4] drm/i915/bdw: Support BDW caching

[Ben Widawsky]

BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HSW and before.

v2: Tiny bikeshed as discussed on internal irc.

v3: Squash in patch from Ville to mirror the x86 PAT setup more like
in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
uncached.

v4: Comment for reason to not use a 64b write on the PPAT.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 44 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  1 +
 2 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ff52c48..57b21c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -58,12 +58,21 @@ typedef uint64_t gen8_gtt_pte_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
+#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
+#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
+#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
+
 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 					     enum i915_cache_level level,
 					     bool valid)
 {
 	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 	pte |= addr;
+	if (level != I915_CACHE_NONE)
+		pte |= PPAT_CACHED_INDEX;
+	else
+		pte |= PPAT_UNCACHED_INDEX;
 	return pte;
 }
 
@@ -805,6 +814,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
 			*end -= 4096;
 	}
 }
+
 void i915_gem_setup_global_gtt(struct drm_device *dev,
 			       unsigned long start,
 			       unsigned long mappable_end,
@@ -1002,6 +1012,38 @@ static int ggtt_probe_common(struct drm_device *dev,
 	return ret;
 }
 
+/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
+ * bits. When using advanced contexts each context stores its own PAT, but
+ * writing this data shouldn't be harmful even in those cases. */
+static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+#define GEN8_PPAT_UC		(0<<0)
+#define GEN8_PPAT_WC		(1<<0)
+#define GEN8_PPAT_WT		(2<<0)
+#define GEN8_PPAT_WB		(3<<0)
+#define GEN8_PPAT_ELLC_OVERRIDE	(0<<2)
+#define GEN8_PPAT_LLC		(1<<2)
+#define GEN8_PPAT_LLCELLC	(2<<2)
+#define GEN8_PPAT_LLCeLLC	(3<<2) /* BSPEC mistake? */
+#define GEN8_PPAT_AGE(x)	(x<<4)
+#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
+	uint64_t pat;
+
+	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
+	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
+	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
+	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
+	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
+	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
+	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
+	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+
+	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
+	 * write would work. */
+	I915_WRITE(GEN8_PRIVATE_PAT, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+}
+
 static int gen8_gmch_probe(struct drm_device *dev,
 			   size_t *gtt_total,
 			   size_t *stolen,
@@ -1027,6 +1069,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
 	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
 
+	gen8_setup_private_ppat(dev_priv);
+
 	ret = ggtt_probe_common(dev, gtt_size);
 
 	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b801b88..9929750 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -664,6 +664,7 @@
 #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
 #define DONE_REG		0x40b0
+#define GEN8_PRIVATE_PAT	0x40e0
 #define BSD_HWS_PGA_GEN7	(0x04180)
 #define BLT_HWS_PGA_GEN7	(0x04280)
 #define VEBOX_HWS_PGA_GEN7	(0x04380)
-- 
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/bdw: PPGTT init & cleanup

[Ben Widawsky]

Aside from the potential size increase of the PPGTT, the primary
difference from previous hardware is the Page Directories are no longer
carved out of the Global GTT.

Note that the PDE allocation is done as a 8MB contiguous allocation,
this needs to be eventually fixed (since driver reloading will be a
pain otherwise). Also, this will be a no-go for real PPGTT support.

v2: Move vtable initialization

v3: Resolve conflicts due to patch series reordering.

v4: Rebase on top of the address space refactoring of the PPGTT
support. Drop Imre's r-b tag for v2, too outdated by now.

v5: Free the correct amount of memory, "get_order takes size not a page
count." (Imre)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h     |  19 ++++--
 drivers/gpu/drm/i915/i915_gem_gtt.c | 123 +++++++++++++++++++++++++++++++++++-
 2 files changed, 137 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83d016c..97b0905 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -572,10 +572,21 @@ struct i915_gtt {
 struct i915_hw_ppgtt {
 	struct i915_address_space base;
 	unsigned num_pd_entries;
-	struct page **pt_pages;
-	uint32_t pd_offset;
-	dma_addr_t *pt_dma_addr;
-
+	union {
+		struct page **pt_pages;
+		struct page *gen8_pt_pages;
+	};
+	struct page *pd_pages;
+	int num_pd_pages;
+	int num_pt_pages;
+	union {
+		uint32_t pd_offset;
+		dma_addr_t pd_dma_addr[4];
+	};
+	union {
+		dma_addr_t *pt_dma_addr;
+		dma_addr_t *gen8_pt_dma_addr[4];
+	};
 	int (*enable)(struct drm_device *dev);
 };
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 57b21c3..66e96ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -31,6 +31,7 @@
 #define GEN6_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
 typedef uint64_t gen8_gtt_pte_t;
+typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 
 /* PPGTT stuff */
 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
@@ -58,6 +59,9 @@ typedef uint64_t gen8_gtt_pte_t;
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 
+#define GEN8_PDES_PER_PAGE		(PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
+#define GEN8_LEGACY_PDPS		4
+
 #define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
 #define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
@@ -177,6 +181,123 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	int i, j;
+
+	for (i = 0; i < ppgtt->num_pd_pages ; i++) {
+		if (ppgtt->pd_dma_addr[i]) {
+			pci_unmap_page(ppgtt->base.dev->pdev,
+				       ppgtt->pd_dma_addr[i],
+				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+
+			for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+				dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+				if (addr)
+					pci_unmap_page(ppgtt->base.dev->pdev,
+						       addr,
+						       PAGE_SIZE,
+						       PCI_DMA_BIDIRECTIONAL);
+
+			}
+		}
+		kfree(ppgtt->gen8_pt_dma_addr[i]);
+	}
+
+	__free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);
+	__free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);
+}
+
+/**
+ * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
+ * net effect resembling a 2-level page table in normal x86 terms. Each PDP
+ * represents 1GB of memory
+ * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
+ *
+ * TODO: Do something with the size parameter
+ **/
+static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
+{
+	struct page *pt_pages;
+	int i, j, ret = -ENOMEM;
+	const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
+	const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
+
+	if (size % (1<<30))
+		DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
+
+	/* FIXME: split allocation into smaller pieces. For now we only ever do
+	 * this once, but with full PPGTT, the multiple contiguous allocations
+	 * will be bad.
+	 */
+	ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
+	if (!ppgtt->pd_pages)
+		return -ENOMEM;
+
+	pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
+	if (!pt_pages) {
+		__free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
+		return -ENOMEM;
+	}
+
+	ppgtt->gen8_pt_pages = pt_pages;
+	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
+	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
+	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+	ppgtt->base.clear_range = NULL;
+	ppgtt->base.insert_entries = NULL;
+	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
+
+	BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
+
+	/*
+	 * - Create a mapping for the page directories.
+	 * - For each page directory:
+	 *      allocate space for page table mappings.
+	 *      map each page table
+	 */
+	for (i = 0; i < max_pdp; i++) {
+		dma_addr_t temp;
+		temp = pci_map_page(ppgtt->base.dev->pdev,
+				    &ppgtt->pd_pages[i], 0,
+				    PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+		if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+			goto err_out;
+
+		ppgtt->pd_dma_addr[i] = temp;
+
+		ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
+		if (!ppgtt->gen8_pt_dma_addr[i])
+			goto err_out;
+
+		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+			struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
+			temp = pci_map_page(ppgtt->base.dev->pdev,
+					    p, 0, PAGE_SIZE,
+					    PCI_DMA_BIDIRECTIONAL);
+
+			if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+				goto err_out;
+
+			ppgtt->gen8_pt_dma_addr[i][j] = temp;
+		}
+	}
+
+	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
+			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
+	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
+			 ppgtt->num_pt_pages,
+			 (ppgtt->num_pt_pages - num_pt_pages) +
+			 size % (1<<30));
+	return -ENOSYS; /* Not ready yet */
+
+err_out:
+	ppgtt->base.cleanup(&ppgtt->base);
+	return ret;
+}
+
 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 {
 	struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
@@ -430,7 +551,7 @@ static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 8)
 		ret = gen6_ppgtt_init(ppgtt);
 	else if (IS_GEN8(dev))
-		ret = -ENXIO;
+		ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 	else
 		BUG();
 
-- 
1.8.4.2

[PATCH 24/62] [v3] drm/i915/bdw: Initialize the PDEs

[Ben Widawsky]

The upcoming clear and insert routines will expect that PDEs all point
to valid Page Directories. Doing that lazily doesn't really buy us
anything.

The page allocation is done regardless earlier in init so it shouldn't
hurt set the PDEs.

v2: Squash in patches to implement fixed PDE write function:

- If I had done this in the first place, the bug that's going to be
  fixed in an upcoming patch would have been much easier to find.

- Use WB for PDEs.

  The PAT bit is used for page size. 2ME PDEs aren't even supported in
  BDW, so this was completely invalid. The solution is to make our
  PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess,
  this change won't matter for performance.

  Thanks to Ville for the quick correction when discussing on IRC.

v3: Return the pde type for pde encoding (Damien)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 66e96ab..0174d4e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -80,6 +80,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
+					     dma_addr_t addr,
+					     enum i915_cache_level level)
+{
+	gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+	pde |= addr;
+	if (level != I915_CACHE_NONE)
+		pde |= PPAT_CACHED_PDE_INDEX;
+	else
+		pde |= PPAT_UNCACHED_INDEX;
+	return pde;
+}
+
 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 				     enum i915_cache_level level,
 				     bool valid)
@@ -285,6 +298,20 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 		}
 	}
 
+	/* For now, the PPGTT helper functions all require that the PDEs are
+	 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
+	 * will never need to touch the PDEs again */
+	for (i = 0; i < max_pdp; i++) {
+		gen8_ppgtt_pde_t *pd_vaddr;
+		pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
+		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+			dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
+						      I915_CACHE_LLC);
+		}
+		kunmap_atomic(pd_vaddr);
+	}
+
 	DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 			 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 	DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
-- 
1.8.4.2

[PATCH 27/62] [v7] drm/i915/bdw: Implement PPGTT enable

[Ben Widawsky]

Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
Since all rings are using the same address space with the current code
the logic is simply to program all the tables we've setup for the PPGTT.

v2: Turn on PPGTT in GFX_MODE

v3: v2 was the wrong patch

v4: Resolve conflicts due to patch series reordering.

v5: Squash in fixup from Ben: Use LRI to write PDPs

The docs (and simulator seems to back up) suggest that we can only
program legacy PPGTT PDPs with LRI commands.

v6: Rebase around context differences conflicts.

v7: Use #defines for per ring PDPs. (Damien)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 50 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  3 +++
 2 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 022af18..0984a62 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -195,6 +195,55 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 	return pte;
 }
 
+/* Broadwell Page Directory Pointer Descriptors */
+static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
+			   uint64_t val)
+{
+	int ret;
+
+	BUG_ON(entry >= 4);
+
+	ret = intel_ring_begin(ring, 6);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
+	intel_ring_emit(ring, (u32)(val >> 32));
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
+	intel_ring_emit(ring, (u32)(val));
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int gen8_ppgtt_enable(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int i, j, ret;
+
+	/* bit of a hack to find the actual last used pd */
+	int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
+
+	for_each_ring(ring, dev_priv, j) {
+		I915_WRITE(RING_MODE_GEN7(ring),
+			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	}
+
+	for (i = used_pd - 1; i >= 0; i--) {
+		dma_addr_t addr = ppgtt->pd_dma_addr[i];
+		for_each_ring(ring, dev_priv, j) {
+			ret = gen8_write_pdp(ring, i, addr);
+			if (ret)
+				return ret;
+		}
+	}
+	return 0;
+}
+
 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 				   unsigned first_entry,
 				   unsigned num_entries,
@@ -326,6 +375,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 	ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 	ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+	ppgtt->enable = gen8_ppgtt_enable;
 	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68b877d..b212897 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -110,6 +110,9 @@
 #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
 #define   PP_DIR_DCLV_2G		0xffffffff
 
+#define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))
+#define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
+
 #define GAM_ECOCHK			0x4090
 #define   ECOCHK_SNB_BIT		(1<<10)
 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
-- 
1.8.4.2

[PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR

[Ben Widawsky]

Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.

Note that Broadwell provides additional PSR support. This is not
addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

v5: Be explicit about not setting min link entry time for BDW. This
should be no functional change over v4 (Jani)

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f222eb4..dc79a0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev))
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ba1fe7e..3761c80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1959,8 +1959,8 @@
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
-/* HSW eDP PSR registers */
-#define EDP_PSR_BASE(dev)			0x64800
+/* HSW+ eDP PSR registers */
+#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
 #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   EDP_PSR_LINK_DISABLE			(0<<27)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7725f81..6e4246f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1603,6 +1603,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t max_sleep_time = 0x1f;
 	uint32_t idle_frames = 1;
 	uint32_t val = 0x0;
+	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_LINK_STANDBY;
@@ -1613,7 +1614,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_LINK_DISABLE;
 
 	I915_WRITE(EDP_PSR_CTL(dev), val |
-		   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
+		   IS_BROADWELL(dev) ? 0 : link_entry_time |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 		   EDP_PSR_ENABLE);
-- 
1.8.4.2

[PATCH] drm/i915/bdw: Disable centroid pixel perf optimization

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

BDW-A workaround

BDW Bug #1899532

v2: WARN on when not using preliminary HW support

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 050f8c1..98961ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4989,6 +4989,9 @@
 #define HSW_ROW_CHICKEN3		0xe49c
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
+#define HALF_SLICE_CHICKEN3		0xe184
+#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
+
 #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
 #define INTEL_AUDIO_DEVCL		0x808629FB
 #define INTEL_AUDIO_DEVBLC		0x80862801
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6e12e1..66b5a1c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5286,6 +5286,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 
+	WARN(!i915_preliminary_hw_support,
+	     "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
+	I915_WRITE(HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
 	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
 	/* WaSwitchSolVfFArbitrationPriority */
-- 
1.8.4.2

[PATCH 64/62] drm/i915/bdw: Change dp aux timeout to 600us on DDIA

[Ben Widawsky]

Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_dp.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6e4246f..dc216e7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -405,6 +405,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	uint32_t status;
 	int try, precharge, clock = 0;
 	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
+	uint32_t timeout;
 
 	/* dp aux is extremely sensitive to irq latency, hence request the
 	 * lowest possible wakeup latency and so prevent the cpu from going into
@@ -419,6 +420,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	else
 		precharge = 5;
 
+	if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
+		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
+	else
+		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
+
 	intel_aux_display_runtime_get(dev_priv);
 
 	/* Try to wait for any previous AUX channel activity */
@@ -454,7 +460,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 			I915_WRITE(ch_ctl,
 				   DP_AUX_CH_CTL_SEND_BUSY |
 				   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
-				   DP_AUX_CH_CTL_TIME_OUT_400us |
+				   timeout |
 				   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 				   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 				   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
-- 
1.8.4.2

Re: [PATCH 02/62] drm/i915/bdw: Handle forcewake for writes on gen8

[Mika Kuoppala]

Ben Widawsky <benjamin.widawsky@intel.com> writes:

> GEN8 removes the GT FIFO which we've all come to know and love. Instead
> it offers a wider range of optimized registers which always keep a
> shadowed copy, and are fed to the GPU when it wakes.
>
> How this is implemented in hardware is still somewhat of a mystery. As
> far as I can tell, the basic design is as follows:
>
> If the register is not optimized, you must use the old forcewake
> mechanism to bring the GT out of sleep. [1]
>
> If register is in the optimized list the write will signal that the
> GT should begin to come out of whatever sleep state it is in.
>
> While the GT is coming out of sleep, the requested write will be stored
> in an intermediate shadow register.
>
> Do to the fact that the implementation details are not clear, I see
> several risks:
> 1. Order is not preserved as it is with GT FIFO. If we issue multiple
> writes to optimized registers, where order matters, we may need to
> serialize it with forcewake.
> 2. The optimized registers have only 1 shadowed slot, meaning if we
> issue multiple writes to the same register, and those values need to
> reach the GPU in order, forcewake will be required.
>
> [1] We could implement a SW queue the way the GT FIFO used to work if
> desired.
>
> NOTE: Compile tested only until we get real silicon.
>
> v2:
> - Use a default case to make future platforms also work.
> - Get rid of IS_BROADWELL since that's not yet defined, but we want to
>   MMIO as soon as possible.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index f6fae35..fa06ce4 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -93,7 +93,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
>  {
>  	u32 forcewake_ack;
>  
> -	if (IS_HASWELL(dev_priv->dev))
> +	if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
>  		forcewake_ack = FORCEWAKE_ACK_HSW;
>  	else
>  		forcewake_ack = FORCEWAKE_MT_ACK;
> @@ -459,6 +459,47 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
>  }
>  
> +static const u32 gen8_optimized_regs[] = {
> +	FORCEWAKE_MT,
> +	GEN6_RPNSWREQ,
> +	GEN6_RC_VIDEO_FREQ,
> +	RING_TAIL(RENDER_RING_BASE),
> +	RING_TAIL(GEN6_BSD_RING_BASE),
> +	RING_TAIL(VEBOX_RING_BASE),
> +	RING_TAIL(BLT_RING_BASE),
> +	/* TODO: Other registers are not yet used */
> +};
> +

s/optimized/shadowed would make more sense i think.

> +static bool is_gen8_optimized(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	int i;
> +	for (i = 0; i < ARRAY_SIZE(gen8_optimized_regs); i++)
> +		if (reg == gen8_optimized_regs[i])
> +			return false;

The logic is reversed here with regards to function name.

> +
> +	return true;
> +}
> +
> +#define __gen8_write(x) \
> +static void \
> +gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +	bool __needs_put = false; \
                       
This initialization is unnecessary.

> +	REG_WRITE_HEADER; \
> +	__needs_put = is_gen8_optimized(dev_priv, reg); \

This logic is backwards.
Please consider:

        __needs_put = !is_gen8_shadowed(dev_priv, reg);


-- Mika

> +	if (__needs_put) { \
> +		dev_priv->uncore.funcs.force_wake_get(dev_priv); \
> +	} \
> +	__raw_i915_write##x(dev_priv, reg, val); \
> +	if (__needs_put) { \
> +		dev_priv->uncore.funcs.force_wake_put(dev_priv); \
> +	} \
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
> +}
> +
> +__gen8_write(8)
> +__gen8_write(16)
> +__gen8_write(32)
> +__gen8_write(64)
>  __hsw_write(8)
>  __hsw_write(16)
>  __hsw_write(32)
> @@ -476,6 +517,7 @@ __gen4_write(16)
>  __gen4_write(32)
>  __gen4_write(64)
>  
> +#undef __gen8_write
>  #undef __hsw_write
>  #undef __gen6_write
>  #undef __gen5_write
> @@ -534,6 +576,15 @@ void intel_uncore_init(struct drm_device *dev)
>  	}
>  
>  	switch (INTEL_INFO(dev)->gen) {
> +	default:
> +		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
> +		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
> +		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
> +		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
> +		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
> +		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
> +		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
> +		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
>  	case 7:
>  	case 6:
>  		if (IS_HASWELL(dev)) {
> -- 
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 06/62] drm/i915/bdw: Swizzling support

[Mika Kuoppala]

Ben Widawsky <benjamin.widawsky@intel.com> writes:

> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Re: [PATCH 45/62] drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis

[Paulo Zanoni]

2013/11/4 Ben Widawsky <ben@bwidawsk.net>:
> On Sat, Nov 02, 2013 at 09:07:43PM -0700, Ben Widawsky wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> They're not the same as the Haswell ones.
>>
>> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++
>>  drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++---
>>  2 files changed, 63 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 4131223..6f834b3 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5176,6 +5176,7 @@
>>  #define DDI_BUF_CTL_B                                0x64100
>>  #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
>>  #define  DDI_BUF_CTL_ENABLE                  (1<<31)
>> +/* Haswell */
>>  #define  DDI_BUF_EMP_400MV_0DB_HSW           (0<<24)   /* Sel0 */
>>  #define  DDI_BUF_EMP_400MV_3_5DB_HSW         (1<<24)   /* Sel1 */
>>  #define  DDI_BUF_EMP_400MV_6DB_HSW           (2<<24)   /* Sel2 */
>> @@ -5185,6 +5186,16 @@
>>  #define  DDI_BUF_EMP_600MV_6DB_HSW           (6<<24)   /* Sel6 */
>>  #define  DDI_BUF_EMP_800MV_0DB_HSW           (7<<24)   /* Sel7 */
>>  #define  DDI_BUF_EMP_800MV_3_5DB_HSW         (8<<24)   /* Sel8 */
>> +/* Broadwell */
>> +#define  DDI_BUF_EMP_400MV_0DB_BDW           (0<<24)   /* Sel0 */
>> +#define  DDI_BUF_EMP_400MV_3_5DB_BDW         (1<<24)   /* Sel1 */
>> +#define  DDI_BUF_EMP_400MV_6DB_BDW           (2<<24)   /* Sel2 */
>> +#define  DDI_BUF_EMP_600MV_0DB_BDW           (3<<24)   /* Sel3 */
>> +#define  DDI_BUF_EMP_600MV_3_5DB_BDW         (4<<24)   /* Sel4 */
>> +#define  DDI_BUF_EMP_600MV_6DB_BDW           (5<<24)   /* Sel5 */
>
> Maybe I am misreading this, isn't this:
> 600mV, 4.5dB?
>

The DP spec defines voltage swing and pre-emphasis "levels" (0 to 3),
and each level has a "Min", "Nom" and "Max" value. The definitions on
the DRM layer (include/drm/drm_dp_helper.h) don't use the level
numbers, they use the "Nom" values to identify the levels (e.g, level
1 is 3.5dB). Our HW doesn't use the exact "Nom" values for each of the
levels, so there is some inconsistency. The correct thing to do is to
patch the DRM macros and then all the drivers that use them, but for
BDW I didn't want a huge patch, so the strategy was to just name our
own macros in a way that they would match the DRM macros, so the code
wouldn't look confusing. Ideally, after we fix the DRM layer, we
should use just LEVEL{0,1,2,3} for everything on our driver too and
completely ignore the real mV and dB used by the HW.


>> +#define  DDI_BUF_EMP_800MV_0DB_BDW           (6<<24)   /* Sel6 */
>
> 850, .5
>
>> +#define  DDI_BUF_EMP_800MV_3_5DB_BDW         (7<<24)   /* Sel7 */
>
> 750, 2.5
>
>> +#define  DDI_BUF_EMP_1200MV_0DB_BDW          (8<<24)   /* Sel8 */
>
> 1000, 0
>
> Sorry if I just misunderstood how you're getting these values.

This is confusing, I agree.


>
>>  #define  DDI_BUF_EMP_MASK                    (0xf<<24)
>>  #define  DDI_BUF_PORT_REVERSAL                       (1<<16)
>>  #define  DDI_BUF_IS_IDLE                     (1<<7)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index b3cc333..7725f81 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1950,7 +1950,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>>       struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>       enum port port = dp_to_dig_port(intel_dp)->port;
>>
>> -     if (IS_VALLEYVIEW(dev))
>> +     if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
>>               return DP_TRAIN_VOLTAGE_SWING_1200;
>>       else if (IS_GEN7(dev) && port == PORT_A)
>>               return DP_TRAIN_VOLTAGE_SWING_800;
>> @@ -1966,7 +1966,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>       struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>       enum port port = dp_to_dig_port(intel_dp)->port;
>>
>> -     if (HAS_DDI(dev)) {
>> +     if (IS_BROADWELL(dev)) {
>> +             switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>> +             case DP_TRAIN_VOLTAGE_SWING_400:
>> +             case DP_TRAIN_VOLTAGE_SWING_600:
>> +                     return DP_TRAIN_PRE_EMPHASIS_6;
>> +             case DP_TRAIN_VOLTAGE_SWING_800:
>> +                     return DP_TRAIN_PRE_EMPHASIS_3_5;
>> +             case DP_TRAIN_VOLTAGE_SWING_1200:
>> +             default:
>> +                     return DP_TRAIN_PRE_EMPHASIS_0;
>> +             }
>> +     } else if (IS_HASWELL(dev)) {
>>               switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>               case DP_TRAIN_VOLTAGE_SWING_400:
>>                       return DP_TRAIN_PRE_EMPHASIS_9_5;
>> @@ -2278,6 +2289,41 @@ intel_hsw_signal_levels(uint8_t train_set)
>>       }
>>  }
>>
>> +static uint32_t
>> +intel_bdw_signal_levels(uint8_t train_set)
>> +{
>> +     int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>> +                                      DP_TRAIN_PRE_EMPHASIS_MASK);
>> +     switch (signal_levels) {
>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
>> +             return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
>> +             return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
>> +             return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
>> +
>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
>> +             return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
>> +             return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
>> +             return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
>> +
>> +     case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
>> +             return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
>> +     case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
>> +             return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
>> +
>> +     case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
>> +             return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
>> +
>> +     default:
>> +             DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
>> +                           "0x%x\n", signal_levels);
>> +             return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
>> +     }
>> +}
>> +
>>  /* Properly updates "DP" with the correct signal levels. */
>>  static void
>>  intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>> @@ -2288,7 +2334,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>>       uint32_t signal_levels, mask;
>>       uint8_t train_set = intel_dp->train_set[0];
>>
>> -     if (HAS_DDI(dev)) {
>> +     if (IS_BROADWELL(dev)) {
>> +             signal_levels = intel_bdw_signal_levels(train_set);
>> +             mask = DDI_BUF_EMP_MASK;
>> +     } else if (IS_HASWELL(dev)) {
>>               signal_levels = intel_hsw_signal_levels(train_set);
>>               mask = DDI_BUF_EMP_MASK;
>>       } else if (IS_VALLEYVIEW(dev)) {
>
> Forgive my ignorance, but I really have no idea how to review this
> patch. Daniel, I think we have to settle for Art's r-b on this one, or
> finds someone who understands why this programming is the way it is. (Or
> wait)
>
> --
> Ben Widawsky, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 04/62] [v7] drm/i915/bdw: Add device IDs

[Mika Kuoppala]

Ben Widawsky <benjamin.widawsky@intel.com> writes:

> v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
> suggested by Damien.
>
> v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>
>
> v4: Rebase on top of Jesse's patch to extract all pci ids to
> include/drm/i915_pciids.h.
>
> v4: Replace Halo by its marketing moniker Iris. Requested by Ben.
>
> v5: Switch from info->has*ring to info->ring_mask.
>
> v6: Add 0x16X2 variant (which is newer than this patch)
> Rename to use new naming scheme (Chris)
> Remove Simulator PCI ids. These snuck in during rebase (Chris)
>
> v7: Fix poor sed job from v6
> Make the desktop variants use the desktop macro (Rebase error). Notice
> that this makes no functional difference - it's just confusing.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Re: [PATCH 00/62] Broadwell kernel driver support

[Daniel Vetter]

Hi all,

Just a quick update:

I've started to merge patches into the bdw-stage1 branch of my official
repo. It's also integrated into drm-intel-nightly for integration testing.

I won't reply to individual patches when I do fixups to the patches while
applying since it'll make the massive thread we already have even worse
;-) Instead I'll just poke people on irc when I don't fully follow their
suggestions.

There's still a big chunk of reviews outstanding, so please hurry up.

Thanks, Daniel

On Sun, Nov 03, 2013 at 09:45:49AM +0100, Daniel Vetter wrote:
> On Sat, Nov 02, 2013 at 09:06:58PM -0700, Ben Widawsky wrote:
> > It is my honor and privilege to submit basic Broadwell support on behalf
> > of Intel.
> > 
> > The patch series includes support for Broadwell which should bring it up
> > to feature parity with Haswell. As you'll note, the patches have
> > received some revisions and review already. This is due to our new
> > process (more on this below). We will be rolling out the new Broadwell
> > goodness over time.
> > 
> > Broadwell represents the next generation (GEN8) in Intel graphics
> > processing hardware. Broadwell graphics bring some of the biggest
> > changes we've seen on the execution and memory management side of the
> > GPU. (There are equally large and exciting changes for the userspace
> > drivers.)
> > 
> > My request to reviewers is: I haven't touched these much at all since
> > submitting to the internal mailing list. Most changes are due to rebase.
> > Try to keep bikesheds to a minimum. We want to try to get this code in
> > the 3.13 kernel, so we have a nice base to actually stabilize and
> > improve features for the 3.14 release. Remember, we have that handy
> > 'preliminary hardware support' to allow people to opt-in to this early
> > enabling code. So I'm shooting for stable "end-userable" BDW code in
> > 3.14.
> > 
> > Note that the last few workarounds likely won't be needed, but I think
> > we can include them until we know for sure otherwise.
> > 
> > Aside from the usual set of things we need to update when simply
> > enabling a new platform, What follows are some of the major changes from
> > HSW->BDW:
> > 
> > * There is no longer a forcewake write FIFO. *Most* writes must explicitly
> > wake the GPU.
> > 
> > * Interrupt registers have been completely reorganized.
> > 
> > * PTEs format and cachability settings have changed to more resemble x86
> > PTEs, and PAT
> >   * Address space increases, and as such many commands require changing
> > 
> > * Page table structures have changed for the Per Process GTT. The new
> > structure more resembles traditional page tables with registers defining
> > page directory base.
> > 
> > The latter two changes were the real challenge in enabling the platform
> > and getting things to actually work - though in hindsight, they seem so
> > trivial :-)
> > 
> > You may find these patches here:
> > http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell
> > 
> > I'll be posting patches for libdrm, and intel-gpu-tools in the next day
> > or two.  They are also ready to go, I just need to do a quick once over.
> > At this point, feel free to stop reading.
> 
> Also note that we've spent a decent amount of time refactoring the
> relevant areas in upstream, so now the massive changes for bdw mostly just
> plug in ...
> 
> Anyway, review plan. Like Ben said this is still hidden behind the
> preliminary hw support knob. Also I want to get this all merged, final
> testing done and pull request sent by the end of the week. That way we can
> easily get it into 3.13 and that should also reduce the mess I currently
> have with the -internal branch. So
> - Please check register defines really through-roughly.
> - Check for erregious logic fumbles (e.g. in cleanup paths).
> - For everything else which can't be fixed quickly please just propose a
>   FIXME comment.
> 
> I've just grabbed a bunch of names from our team and then tried to not
> come up with a too bad split for reviewing:
> Mika: Patches 1-6
> Chris: Patches 7-12
> Paulo: Patches 13-17
> Imre: Patches 18-23
> Damien: Patches 24-29
> Rodrigo: Patches 30-35
> Ville: Patches 36-42
> Ben: Patches 43-47
> Jani: Patches 48-53
> Jesse: Patches 54-58
> Daniel: Patche 59-62
> 
> If the patches already has an r-b and hasn't been rebased like crazy since
> then you're lucky ;-)
> 
> Please do the all the review on Mon/Tue so that I can spend Wed
> merging (and if needed, fixing up patches) and then we'll have 2 days or
> so for a bit of final integration testing.
> 
> Thanks, Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 21/62] drm/i915/bdw: Support BDW caching

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 5050 bytes --]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> BDW caching works differently than the previous generations. Instead of
> having bits in the PTE which directly control how the page is cached,
> the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
> register 0x40e0. This style of caching is functionally equivalent to how
> it works on HSW and before.
> 
> v2: Tiny bikeshed as discussed on internal irc.
> 
> v3: Squash in patch from Ville to mirror the x86 PAT setup more like
> in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
> uncached.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h     |  1 +
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index df992dc..02de12d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -58,12 +58,21 @@ typedef uint64_t gen8_gtt_pte_t;
>  #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
>  #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
>  
> +#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
> +#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
> +#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
> +#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
> +
>  static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
>  					     enum i915_cache_level level,
>  					     bool valid)
>  {
>  	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
>  	pte |= addr;
> +	if (level != I915_CACHE_NONE)
> +		pte |= PPAT_CACHED_INDEX;
> +	else
> +		pte |= PPAT_UNCACHED_INDEX;
>  	return pte;
>  }
>  
> @@ -805,6 +814,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
>  			*end -= 4096;
>  	}
>  }
> +
>  void i915_gem_setup_global_gtt(struct drm_device *dev,
>  			       unsigned long start,
>  			       unsigned long mappable_end,
> @@ -1002,6 +1012,36 @@ static int ggtt_probe_common(struct drm_device *dev,
>  	return ret;
>  }
>  
> +/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
> + * bits. When using advanced contexts each context stores its own PAT, but
> + * writing this data shouldn't be harmful even in those cases. */
> +static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
> +{
> +#define GEN8_PPAT_UC		(0<<0)
> +#define GEN8_PPAT_WC		(1<<0)
> +#define GEN8_PPAT_WT		(2<<0)
> +#define GEN8_PPAT_WB		(3<<0)
> +#define GEN8_PPAT_ELLC_OVERRIDE	(0<<2)
> +#define GEN8_PPAT_LLC		(1<<2)
> +#define GEN8_PPAT_LLCELLC	(2<<2)
> +#define GEN8_PPAT_LLCeLLC	(3<<2) /* BSPEC mistake? */

The LLC, LLCELLC encodings don't match the bspec either. If the above
are the correct values it would be nice to have a comment after those
too. Otherwise looks ok:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +#define GEN8_PPAT_AGE(x)	(x<<4)
> +#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
> +	uint64_t pat;
> +
> +	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
> +	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
> +	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
> +	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
> +	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
> +	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
> +	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
> +	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> +
> +	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
> +}
> +
>  static int gen8_gmch_probe(struct drm_device *dev,
>  			   size_t *gtt_total,
>  			   size_t *stolen,
> @@ -1027,6 +1067,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
>  	gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
>  	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
>  
> +	gen8_setup_private_ppat(dev_priv);
> +
>  	ret = ggtt_probe_common(dev, gtt_size);
>  
>  	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b801b88..9929750 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -664,6 +664,7 @@
>  #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
>  #define   RING_FAULT_VALID	(1<<0)
>  #define DONE_REG		0x40b0
> +#define GEN8_PRIVATE_PAT	0x40e0
>  #define BSD_HWS_PGA_GEN7	(0x04180)
>  #define BLT_HWS_PGA_GEN7	(0x04280)
>  #define VEBOX_HWS_PGA_GEN7	(0x04380)


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Re: [PATCH 22/62] drm/i915/bdw: Implement Full Force Miss disables

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 1912 bytes --]

On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> Implements WaVSRefCountFullforceMissDisable
> Implements WaDSRefCountFullforceMissDisable
> 
> v2: Rebased on the HSW patch (which fixed the bug from v1)
> commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7
> Author: Ben Widawsky <ben@bwidawsk.net>
> Date:   Sat Jan 26 11:52:00 2013 -0800
> 
>     drm/i915: Implement WaVSRefCountFullforceMissDisable
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9929750..68b877d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -990,6 +990,7 @@
>  
>  #define GEN7_FF_THREAD_MODE		0x20a0
>  #define   GEN7_FF_SCHED_MASK		0x0077070
> +#define   GEN7_FF_DS_REF_CNT_FFME	(1 << 19)
>  #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
>  #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
>  #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index abc51ea..81ec2c3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5147,6 +5147,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>  	if (IS_HASWELL(dev_priv->dev))
>  		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
>  
> +	/* WaVSRefCountFullforceMissDisable|WaDSRefCountFullforceMissDisable */
> +	if (IS_GEN8(dev_priv->dev))
> +		reg &= ~(GEN7_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
> +
>  	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
>  }

gen7_setup_fixed_func_scheduler() isn't called for GEN8.

--Imre


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Re: [PATCH 14/62] drm/i915/bdw: dispatch updates (64b related)

[Paulo Zanoni]

2013/11/3 Ben Widawsky <benjamin.widawsky@intel.com>:
> The command to emit batch buffers has changed to address 48b addresses.
> It seemed reasonable that we could still use the old instruction where
> emitting 0 for length would do the right thing, but it seems to bother
> the simulator when the code does that.
>
> Now the second dword in the command has the upper 16b of the address of
> the batchbuffer.
>
> v2: Remove duplicated vfun assignment.
>
> v3: Squash in VECS support changes from Zhao Yakui <yakui.zhao@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Looks like I was assigned to review this patch. I am not familiar with
this code at all, so please forgive my stupid questions.


> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +++++++++++++++++++++++++++++---
>  1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index b2161f2..60ef8ff 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1684,6 +1684,27 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
>  }
>
>  static int
> +gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
> +                             u32 offset, u32 len,
> +                             unsigned flags)
> +{
> +       int ret;
> +
> +       ret = intel_ring_begin(ring, 4);
> +       if (ret)
> +               return ret;
> +
> +       intel_ring_emit(ring, MI_BATCH_BUFFER_START | 1);

What about bit 8? The other distpatch_execbuffer functions seem to set
it conditionally based on the I915_DISPATCH_SECURE flag. Why do we
ignore it now?

Not a problem, just an observation: I also couldn't find a sign of the
existence of MI_BATCH_PPGTT_HSW: poor bit, survived for just 1 gen :(.


> +       /* bit0-7 is the length on GEN6+ */
> +       intel_ring_emit(ring, offset);
> +       intel_ring_emit(ring, 0);
> +       intel_ring_emit(ring, MI_NOOP);
> +       intel_ring_advance(ring);
> +
> +       return 0;
> +}
> +
> +static int
>  hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
>                               u32 offset, u32 len,
>                               unsigned flags)
> @@ -1822,6 +1843,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>         ring->write_tail = ring_write_tail;
>         if (IS_HASWELL(dev))
>                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
> +       else if (IS_GEN8(dev))
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         else if (INTEL_INFO(dev)->gen >= 6)
>                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         else if (INTEL_INFO(dev)->gen >= 4)
> @@ -1948,12 +1971,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>                         ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
>                         ring->irq_get = gen8_ring_get_irq;
>                         ring->irq_put = gen8_ring_put_irq;
> +                       ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>                 } else {
>                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>                         ring->irq_get = gen6_ring_get_irq;
>                         ring->irq_put = gen6_ring_put_irq;
> +                       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>                 }
> -               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>                 ring->sync_to = gen6_ring_sync;
>                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
>                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> @@ -2003,12 +2027,13 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
>                 ring->irq_get = gen8_ring_get_irq;
>                 ring->irq_put = gen8_ring_put_irq;
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         } else {
>                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>                 ring->irq_get = gen6_ring_get_irq;
>                 ring->irq_put = gen6_ring_put_irq;
> +               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         }
> -       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         ring->sync_to = gen6_ring_sync;
>         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
>         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> @@ -2037,7 +2062,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>         ring->add_request = gen6_add_request;
>         ring->get_seqno = gen6_ring_get_seqno;
>         ring->set_seqno = ring_set_seqno;
> -       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>
>         if (INTEL_INFO(dev)->gen >= 8) {
>                 ring->irq_enable_mask =
> @@ -2045,10 +2069,12 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>                         GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
>                 ring->irq_get = gen8_ring_get_irq;
>                 ring->irq_put = gen8_ring_put_irq;
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         } else {
>                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>                 ring->irq_get = hsw_vebox_get_irq;
>                 ring->irq_put = hsw_vebox_put_irq;
> +               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         }
>         ring->sync_to = gen6_ring_sync;
>         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 00/62] Broadwell kernel driver support

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 173 bytes --]

On Sun, 2013-11-03 at 09:45 +0100, Daniel Vetter wrote:
>[...]
> Imre: Patches 18-23

I added my r-b to the above except patch 22, which has a minor issue.

--Imre


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Re: [PATCH 22/62] drm/i915/bdw: Implement Full Force Miss disables

[Daniel Vetter]

On Tue, Nov 05, 2013 at 05:41:21PM +0200, Imre Deak wrote:
> On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> > Implements WaVSRefCountFullforceMissDisable
> > Implements WaDSRefCountFullforceMissDisable
> > 
> > v2: Rebased on the HSW patch (which fixed the bug from v1)
> > commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7
> > Author: Ben Widawsky <ben@bwidawsk.net>
> > Date:   Sat Jan 26 11:52:00 2013 -0800
> > 
> >     drm/i915: Implement WaVSRefCountFullforceMissDisable
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 9929750..68b877d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -990,6 +990,7 @@
> >  
> >  #define GEN7_FF_THREAD_MODE		0x20a0
> >  #define   GEN7_FF_SCHED_MASK		0x0077070
> > +#define   GEN7_FF_DS_REF_CNT_FFME	(1 << 19)
> >  #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
> >  #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
> >  #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index abc51ea..81ec2c3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5147,6 +5147,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> >  	if (IS_HASWELL(dev_priv->dev))
> >  		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
> >  
> > +	/* WaVSRefCountFullforceMissDisable|WaDSRefCountFullforceMissDisable */
> > +	if (IS_GEN8(dev_priv->dev))
> > +		reg &= ~(GEN7_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
> > +
> >  	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
> >  }
> 
> gen7_setup_fixed_func_scheduler() isn't called for GEN8.

I've just looked at the history of the quilt tree and it's been like that
ever since I've merged the patch apparently. Probably mis-wiggled while
applying ... Ben, should I just move this to the gen8 clock gating?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 16/62] drm/i915/bdw: debugfs updates

[Paulo Zanoni]

2013/11/3 Ben Widawsky <benjamin.widawsky@intel.com>:
> All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
> later, I am certain.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d6cda9c..fa3492f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1623,7 +1623,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>                            I915_READ16(C0DRB3));
>                 seq_printf(m, "C1DRB3 = 0x%04x\n",
>                            I915_READ16(C1DRB3));
> -       } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
> +       } else if (INTEL_INFO(dev)->gen >= 6) {
>                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
>                            I915_READ(MAD_DIMM_C0));
>                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
> @@ -1632,8 +1632,12 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>                            I915_READ(MAD_DIMM_C2));
>                 seq_printf(m, "TILECTL = 0x%08x\n",
>                            I915_READ(TILECTL));
> -               seq_printf(m, "ARB_MODE = 0x%08x\n",
> -                          I915_READ(ARB_MODE));
> +               if (IS_GEN8(dev))
> +                       seq_printf(m, "ARB_MODE = 0x%08x\n",
> +                                  I915_READ(GAMTARBMODE));

IMHO this could be misleading since ARB_MODE still exists and has a
different address. I'd print "GAMTARBMODE" to make it clear we're not
printing the value of 0x4030.


> +               else
> +                       seq_printf(m, "ARB_MODE = 0x%08x\n",
> +                                  I915_READ(ARB_MODE));
>                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
>                            I915_READ(DISP_ARB_CTL));
>         }
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 17/62] drm/i915/bdw: Update relevant error state

[Paulo Zanoni]

2013/11/3 Ben Widawsky <benjamin.widawsky@intel.com>:
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3d01eae..a55ebe8 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1043,6 +1043,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
>         default:
>                 WARN_ONCE(1, "Unsupported platform\n");
>         case 7:
> +       case 8:
>                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
>                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
>                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 56/62] drm/i915/bdw: Implement edp PSR workarounds

[Jesse Barnes]

On Sat,  2 Nov 2013 21:07:54 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> This implements a workaround for PSR dealing with some vblank issue.
> 
> WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD
> 
> v2: forgot to git add bogus whitespace fix
> 
> v3: Update with workaround names.
> Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)
> 
> Cc: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
>  drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
>  2 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f97836e..9608f96 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4092,8 +4092,14 @@
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
>  
>  #define CHICKEN_PAR1_1		0x42080
> +#define  DPA_MASK_VBLANK_SRD	(1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
>  
> +#define _CHICKEN_PIPESL_1_A	0x420b0
> +#define _CHICKEN_PIPESL_1_B	0x420b4
> +#define  DPRS_MASK_VBLANK_SRD	(1 << 0)
> +#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> +
>  #define DISP_ARB_CTL	0x45000
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0245985..63f6e59 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5288,6 +5288,23 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  
>  	/* WaSwitchSolVfFArbitrationPriority */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> +
> +	if (IS_BROADWELL(dev)) {
> +		enum pipe i;
> +
> +		/* WaPsrDPAMaskVBlankInSRD */
> +		I915_WRITE(CHICKEN_PAR1_1,
> +			   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> +
> +		/* WaPsrDPRSUnmaskVBlankInSRD */
> +		for_each_pipe(i) {
> +			I915_WRITE(CHICKEN_PIPESL_1(i),
> +				   I915_READ(CHICKEN_PIPESL_1(i) |
> +					     DPRS_MASK_VBLANK_SRD));
> +		}
> +	}
> +
> +
>  }
>  
>  static void haswell_init_clock_gating(struct drm_device *dev)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 57/62] drm/i915/bdw: BWGTLB clock gate disable

[Jesse Barnes]

On Sat,  2 Nov 2013 21:07:55 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> From: Ben Widawsky <ben@bwidawsk.net>
> 
> Wa???
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9608f96..2d16363 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -656,6 +656,7 @@
>  #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
>  #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
>  #define GAMTARBMODE		0x04a08
> +#define   ARB_MODE_BWGTLB_DISABLE (1<<9)
>  #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
>  #define RENDER_HWS_PGA_GEN7	(0x04080)
>  #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 63f6e59..e6e12e1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> +	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
> +
>  	/* WaSwitchSolVfFArbitrationPriority */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  

We really need some rev checking for workarounds like these that don't
apply to every version, or I'm afraid we'll forget them, like we've
done on previous gens (not that it's particularly critical for simple
clock gating ones like this, but for perf critical ones it can be).

Otherwise,
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH] drm/i915/bdw: Disable centroid pixel perf optimization

[Jesse Barnes]

On Mon,  4 Nov 2013 22:52:39 -0800
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> From: Ben Widawsky <ben@bwidawsk.net>
> 
> BDW-A workaround
> 
> BDW Bug #1899532
> 
> v2: WARN on when not using preliminary HW support
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 050f8c1..98961ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4989,6 +4989,9 @@
>  #define HSW_ROW_CHICKEN3		0xe49c
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>  
> +#define HALF_SLICE_CHICKEN3		0xe184
> +#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
> +
>  #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e6e12e1..66b5a1c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5286,6 +5286,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> +	WARN(!i915_preliminary_hw_support,
> +	     "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
> +	I915_WRITE(HALF_SLICE_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
>  	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
>  
>  	/* WaSwitchSolVfFArbitrationPriority */

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 45/62] drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis

[Todd Previte]

On 11/5/2013 6:01 AM, Paulo Zanoni wrote:
> 2013/11/4 Ben Widawsky <ben@bwidawsk.net>:
>> On Sat, Nov 02, 2013 at 09:07:43PM -0700, Ben Widawsky wrote:
>>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>>
>>> They're not the same as the Haswell ones.
>>>
>>> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
>>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++
>>>   drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++---
>>>   2 files changed, 63 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 4131223..6f834b3 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -5176,6 +5176,7 @@
>>>   #define DDI_BUF_CTL_B                                0x64100
>>>   #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
>>>   #define  DDI_BUF_CTL_ENABLE                  (1<<31)
>>> +/* Haswell */
>>>   #define  DDI_BUF_EMP_400MV_0DB_HSW           (0<<24)   /* Sel0 */
>>>   #define  DDI_BUF_EMP_400MV_3_5DB_HSW         (1<<24)   /* Sel1 */
>>>   #define  DDI_BUF_EMP_400MV_6DB_HSW           (2<<24)   /* Sel2 */
>>> @@ -5185,6 +5186,16 @@
>>>   #define  DDI_BUF_EMP_600MV_6DB_HSW           (6<<24)   /* Sel6 */
>>>   #define  DDI_BUF_EMP_800MV_0DB_HSW           (7<<24)   /* Sel7 */
>>>   #define  DDI_BUF_EMP_800MV_3_5DB_HSW         (8<<24)   /* Sel8 */
>>> +/* Broadwell */
>>> +#define  DDI_BUF_EMP_400MV_0DB_BDW           (0<<24)   /* Sel0 */
>>> +#define  DDI_BUF_EMP_400MV_3_5DB_BDW         (1<<24)   /* Sel1 */
>>> +#define  DDI_BUF_EMP_400MV_6DB_BDW           (2<<24)   /* Sel2 */
>>> +#define  DDI_BUF_EMP_600MV_0DB_BDW           (3<<24)   /* Sel3 */
>>> +#define  DDI_BUF_EMP_600MV_3_5DB_BDW         (4<<24)   /* Sel4 */
>>> +#define  DDI_BUF_EMP_600MV_6DB_BDW           (5<<24)   /* Sel5 */
>> Maybe I am misreading this, isn't this:
>> 600mV, 4.5dB?
>>
> The DP spec defines voltage swing and pre-emphasis "levels" (0 to 3),
> and each level has a "Min", "Nom" and "Max" value. The definitions on
> the DRM layer (include/drm/drm_dp_helper.h) don't use the level
> numbers, they use the "Nom" values to identify the levels (e.g, level
> 1 is 3.5dB). Our HW doesn't use the exact "Nom" values for each of the
> levels, so there is some inconsistency. The correct thing to do is to
> patch the DRM macros and then all the drivers that use them, but for
> BDW I didn't want a huge patch, so the strategy was to just name our
> own macros in a way that they would match the DRM macros, so the code
> wouldn't look confusing. Ideally, after we fix the DRM layer, we
> should use just LEVEL{0,1,2,3} for everything on our driver too and
> completely ignore the real mV and dB used by the HW.

I'm in agreement Paulo's assessment above. Eventually we want to 
standardize on the concept of the driver using "levels" not values for 
voltage swing and preemphasis.  This solution works for BDW in the near 
term, though, so I'm good with it.

Reviewed-by: Todd Previte <tprevite@gmail.com>

>
>>> +#define  DDI_BUF_EMP_800MV_0DB_BDW           (6<<24)   /* Sel6 */
>> 850, .5
>>
>>> +#define  DDI_BUF_EMP_800MV_3_5DB_BDW         (7<<24)   /* Sel7 */
>> 750, 2.5
>>
>>> +#define  DDI_BUF_EMP_1200MV_0DB_BDW          (8<<24)   /* Sel8 */
>> 1000, 0
>>
>> Sorry if I just misunderstood how you're getting these values.
> This is confusing, I agree.
>
>
>>>   #define  DDI_BUF_EMP_MASK                    (0xf<<24)
>>>   #define  DDI_BUF_PORT_REVERSAL                       (1<<16)
>>>   #define  DDI_BUF_IS_IDLE                     (1<<7)
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index b3cc333..7725f81 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -1950,7 +1950,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>>>        struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>>        enum port port = dp_to_dig_port(intel_dp)->port;
>>>
>>> -     if (IS_VALLEYVIEW(dev))
>>> +     if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
>>>                return DP_TRAIN_VOLTAGE_SWING_1200;
>>>        else if (IS_GEN7(dev) && port == PORT_A)
>>>                return DP_TRAIN_VOLTAGE_SWING_800;
>>> @@ -1966,7 +1966,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>>        struct drm_device *dev = intel_dp_to_dev(intel_dp);
>>>        enum port port = dp_to_dig_port(intel_dp)->port;
>>>
>>> -     if (HAS_DDI(dev)) {
>>> +     if (IS_BROADWELL(dev)) {
>>> +             switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>> +             case DP_TRAIN_VOLTAGE_SWING_400:
>>> +             case DP_TRAIN_VOLTAGE_SWING_600:
>>> +                     return DP_TRAIN_PRE_EMPHASIS_6;
>>> +             case DP_TRAIN_VOLTAGE_SWING_800:
>>> +                     return DP_TRAIN_PRE_EMPHASIS_3_5;
>>> +             case DP_TRAIN_VOLTAGE_SWING_1200:
>>> +             default:
>>> +                     return DP_TRAIN_PRE_EMPHASIS_0;
>>> +             }
>>> +     } else if (IS_HASWELL(dev)) {
>>>                switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>>                case DP_TRAIN_VOLTAGE_SWING_400:
>>>                        return DP_TRAIN_PRE_EMPHASIS_9_5;
>>> @@ -2278,6 +2289,41 @@ intel_hsw_signal_levels(uint8_t train_set)
>>>        }
>>>   }
>>>
>>> +static uint32_t
>>> +intel_bdw_signal_levels(uint8_t train_set)
>>> +{
>>> +     int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>>> +                                      DP_TRAIN_PRE_EMPHASIS_MASK);
>>> +     switch (signal_levels) {
>>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
>>> +             return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
>>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
>>> +             return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
>>> +     case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
>>> +             return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
>>> +
>>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
>>> +             return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
>>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
>>> +             return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
>>> +     case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
>>> +             return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
>>> +
>>> +     case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
>>> +             return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
>>> +     case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
>>> +             return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
>>> +
>>> +     case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
>>> +             return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
>>> +
>>> +     default:
>>> +             DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
>>> +                           "0x%x\n", signal_levels);
>>> +             return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
>>> +     }
>>> +}
>>> +
>>>   /* Properly updates "DP" with the correct signal levels. */
>>>   static void
>>>   intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>>> @@ -2288,7 +2334,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
>>>        uint32_t signal_levels, mask;
>>>        uint8_t train_set = intel_dp->train_set[0];
>>>
>>> -     if (HAS_DDI(dev)) {
>>> +     if (IS_BROADWELL(dev)) {
>>> +             signal_levels = intel_bdw_signal_levels(train_set);
>>> +             mask = DDI_BUF_EMP_MASK;
>>> +     } else if (IS_HASWELL(dev)) {
>>>                signal_levels = intel_hsw_signal_levels(train_set);
>>>                mask = DDI_BUF_EMP_MASK;
>>>        } else if (IS_VALLEYVIEW(dev)) {
>> Forgive my ignorance, but I really have no idea how to review this
>> patch. Daniel, I think we have to settle for Art's r-b on this one, or
>> finds someone who understands why this programming is the way it is. (Or
>> wait)
>>
>> --
>> Ben Widawsky, Intel Open Source Technology Center
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>

Re: [PATCH 09/62] drm/i915/bdw: display stuff

[Daniel Vetter]

On Sat, Nov 02, 2013 at 09:07:07PM -0700, Ben Widawsky wrote:
> Just enough to make the code not barf...
> 
> Init BDW display to look like HSW. For the simulator this should be
> fine, but this will probably require more work.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0c2e83c..436b750 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10308,7 +10308,7 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.write_eld = ironlake_write_eld;
>  			dev_priv->display.modeset_global_resources =
>  				ivb_modeset_global_resources;
> -		} else if (IS_HASWELL(dev)) {
> +		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
>  			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>  			dev_priv->display.write_eld = haswell_write_eld;
>  			dev_priv->display.modeset_global_resources =
> @@ -10339,6 +10339,7 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.queue_flip = intel_gen6_queue_flip;
>  		break;
>  	case 7:
> +	case 8:
>  		dev_priv->display.queue_flip = intel_gen7_queue_flip;

Since this patch's inception we've enabled RCS flips on gen7. I've added a
FIMXE(BDW) comment that this needs to be tested.
-Daniel

>  		break;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8afaad6..f8b265c 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1092,6 +1092,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  		break;
>  
>  	case 7:
> +	case 8:
>  		if (IS_IVYBRIDGE(dev)) {
>  			intel_plane->can_scale = true;
>  			intel_plane->max_downscale = 2;
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 20/62] drm/i915/bdw: Add GTT functions

[Bloomfield, Jon]

> -----Original Message-----
> From: intel-gfx-bounces@lists.freedesktop.org [mailto:intel-gfx-
> bounces@lists.freedesktop.org] On Behalf Of Ben Widawsky
> Sent: Sunday, November 03, 2013 4:07 AM
> To: Intel GFX
> Cc: Daniel Vetter; Ben Widawsky; Widawsky, Benjamin
> Subject: [Intel-gfx] [PATCH 20/62] drm/i915/bdw: Add GTT functions
> 
> With the PTE clarifications, the bind and clear functions can now be added for
> gen8.
> 
> v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.
> 
> v3: Drop dev argument to pte encode functions, upstream lost it. Also rebase
> on top of the scratch page movement.
> 
> v4: Rebase on top of the new address space vfuncs.
> 
> v5: Add the bool use_scratch argument to clear_range and the bool valid
> argument to the PTE encode function to follow upstream changes.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 88
> +++++++++++++++++++++++++++++++++++--
>  1 file changed, 85 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8bf2184..df992dc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -58,6 +58,15 @@ typedef uint64_t gen8_gtt_pte_t;
>  #define HSW_WB_ELLC_LLC_AGE0
> 	HSW_CACHEABILITY_CONTROL(0xb)
>  #define HSW_WT_ELLC_LLC_AGE0
> 	HSW_CACHEABILITY_CONTROL(0x6)
> 
> +static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
> +					     enum i915_cache_level level,
> +					     bool valid)
> +{
> +	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
> +	pte |= addr;
> +	return pte;
> +}
> +
>  static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
>  				     enum i915_cache_level level,
>  				     bool valid)
> @@ -576,6 +585,56 @@ int i915_gem_gtt_prepare_object(struct
> drm_i915_gem_object *obj)
>  	return 0;
>  }
> 
> +static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
> +{ #ifdef writeq
> +	writeq(pte, addr);
> +#else
> +	iowrite32((u32)pte, addr);
> +	iowrite32(pte >> 32, addr + 4);
> +#endif
> +}
> +
> +static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> +				     struct sg_table *st,
> +				     unsigned int first_entry,
> +				     enum i915_cache_level level)
> +{
> +	struct drm_i915_private *dev_priv = vm->dev->dev_private;
> +	gen8_gtt_pte_t __iomem *gtt_entries =
> +		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
> first_entry;
> +	int i = 0;
> +	struct sg_page_iter sg_iter;
> +	dma_addr_t addr;
> +
> +	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
> +		addr = sg_dma_address(sg_iter.sg) +
> +			(sg_iter.sg_pgoffset << PAGE_SHIFT);
> +		gen8_set_pte(&gtt_entries[i],
> +			     gen8_pte_encode(addr, level, true));
> +		i++;
> +	}
> +
> +	/* XXX: This serves as a posting read to make sure that the PTE has
> +	 * actually been updated. There is some concern that even though
> +	 * registers and PTEs are within the same BAR that they are
> potentially
> +	 * of NUMA access patterns. Therefore, even with the way we
> assume
> +	 * hardware should work, we must keep this posting read for
> paranoia.
> +	 */
> +	if (i != 0)
> +		WARN_ON(readl(&gtt_entries[i-1])
> +			!= gen8_pte_encode(addr, level, true));
Comparing a u32 with a 64-bit page-table entry ? 

Re: [PATCH 11/62] drm/i915/bdw: Implement interrupt changes

[Daniel Vetter]

On Sat, Nov 02, 2013 at 09:07:09PM -0700, Ben Widawsky wrote:
> The interrupt handling implementation remains the same as previous
> generations with the 4 types of registers, status, identity, mask, and
> enable. However the layout of where the bits go have changed entirely.
> To address these changes, all of the interrupt vfuncs needed special
> gen8 code.
> 
> The way it works is there is a top level status register now which
> informs the interrupt service routine which unit caused the interrupt,
> and therefore which interrupt registers to read to process the
> interrupt. For display the division is quite logical, a set of interrupt
> registers for each pipe, and in addition to those, a set each for "misc"
> and port.
> 
> For GT the things get a bit hairy, as seen by the code. Each of the GT
> units has it's own bits defined. They all look *very similar* and
> resides in 16 bits of a GT register. As an example, RCS and BCS share
> register 0. To compact the code a bit, at a slight expense to
> complexity, this is exactly how the code works as well. 2 structures are
> added to the ring buffer so that our ring buffer interrupt handling code
> knows which ring shares the interrupt registers, and a shift value (ie.
> the top or bottom 16 bits of the register).
> 
> The above allows us to kept the interrupt register caching scheme, the
> per interrupt enables, and the code to mask and unmask interrupts
> relatively clean (again at the cost of some more complexity).
> 
> Most of the GT units mentioned above are command streamers, and so the
> symmetry should work quite well for even the yet to be implemented rings
> which Broadwell adds.
> 
> v2: Fixes up a couple of bugs, and is more verbose about errors in the
> Broadwell interrupt handler.
> 
> v3: fix DE_MISC IER offset
> 
> v4: Simplify interrupts:
> I totally misread the docs the first time I implemented interrupts, and
> so this should greatly simplify the mess. Unlike GEN6, we never touch
> the regular mask registers in irq_get/put.
> 
> v5: Rebased on to of recent pch hotplug setup changes.
> 
> v6: Fixup on top of moving num_pipes to intel_info.
> 
> v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
> wired up ibx_hpd_irq_setup for gen8.
> 
> v8: Rebase on top of Jani's asle handling rework.
> 
> v9: Rebase on top of Ben's VECS enabling for Haswell, where he
> unfortunately went OCD on the gt irq #defines. Not that they're still
> not yet fully consistent:
> - Used the GT_RENDER_ #defines + bdw shifts.
> - Dropped the shift from the L3_PARITY stuff, seemed clearer.
> - s/irq_refcount/irq_refcount.gt/
> 
> v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
> refactoring from Zhao Yakui <yakui.zhao@intel.com>
> 
> v11: Rebase on top of the interrupt cleanups in upstream.
> 
> v12: Rebase on top of Ben's DPF changes in upstream.
> 
> v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
> exactly needs to be done. Requested by Ben.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

I've had to fix quite a few things here, and I've made myself a todo for
patches to write on top of this one here. See the v14 changelog entry.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h         |   5 +-
>  drivers/gpu/drm/i915/i915_irq.c         | 327 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h         |  63 ++++++
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  90 +++++++--
>  4 files changed, 473 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c1b178a..83d016c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1315,7 +1315,10 @@ typedef struct drm_i915_private {
>  	struct mutex dpio_lock;
>  
>  	/** Cached value of IMR to avoid reads in updating the bitfield */
> -	u32 irq_mask;
> +	union {
> +		u32 irq_mask;
> +		u32 de_irq_mask[I915_MAX_PIPES];
> +	};
>  	u32 gt_irq_mask;
>  	u32 pm_irq_mask;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a9f0cb6..3f0c9e3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1118,6 +1118,56 @@ static void snb_gt_irq_handler(struct drm_device *dev,
>  		ivybridge_parity_error_irq_handler(dev, gt_iir);
>  }
>  
> +static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
> +				struct drm_i915_private *dev_priv,
> +				u32 master_ctl)
> +{
> +	u32 rcs, bcs, vcs;
> +	uint32_t tmp = 0;
> +	irqreturn_t ret = IRQ_NONE;
> +
> +	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> +		tmp = I915_READ(GEN8_GT_IIR(0));
> +		if (tmp) {
> +			ret = IRQ_HANDLED;
> +			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
> +			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
> +			if (rcs & GT_RENDER_USER_INTERRUPT)
> +				notify_ring(dev, &dev_priv->ring[RCS]);
> +			if (bcs & GT_RENDER_USER_INTERRUPT)
> +				notify_ring(dev, &dev_priv->ring[BCS]);
> +			I915_WRITE(GEN8_GT_IIR(0), tmp);
> +		} else
> +			DRM_ERROR("The master control interrupt lied (GT0)!\n");
> +	}
> +
> +	if (master_ctl & GEN8_GT_VCS1_IRQ) {
> +		tmp = I915_READ(GEN8_GT_IIR(1));
> +		if (tmp) {
> +			ret = IRQ_HANDLED;
> +			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
> +			if (vcs & GT_RENDER_USER_INTERRUPT)
> +				notify_ring(dev, &dev_priv->ring[VCS]);
> +			I915_WRITE(GEN8_GT_IIR(1), tmp);
> +		} else
> +			DRM_ERROR("The master control interrupt lied (GT1)!\n");
> +	}
> +
> +	if (master_ctl & GEN8_GT_VECS_IRQ) {
> +		tmp = I915_READ(GEN8_GT_IIR(3));
> +		if (tmp) {
> +			ret = IRQ_HANDLED;
> +			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
> +			if (vcs & GT_RENDER_USER_INTERRUPT)
> +				notify_ring(dev, &dev_priv->ring[VECS]);
> +			I915_WRITE(GEN8_GT_IIR(3), tmp);
> +		} else
> +			DRM_ERROR("The master control interrupt lied (GT3)!\n");
> +	}
> +
> +	return ret;
> +}
> +
>  #define HPD_STORM_DETECT_PERIOD 1000
>  #define HPD_STORM_THRESHOLD 5
>  
> @@ -1699,6 +1749,85 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	return ret;
>  }
>  
> +static irqreturn_t gen8_irq_handler(int irq, void *arg)
> +{
> +	struct drm_device *dev = arg;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 master_ctl;
> +	irqreturn_t ret = IRQ_NONE;
> +	uint32_t tmp = 0;
> +
> +	atomic_inc(&dev_priv->irq_received);
> +
> +	master_ctl = I915_READ(GEN8_MASTER_IRQ);
> +	master_ctl &= ~DE_MASTER_IRQ_CONTROL;
> +	if (!master_ctl)
> +		return IRQ_NONE;
> +
> +	if ((master_ctl & ~GEN8_RSVD_IRQS) == 0) {
> +		DRM_ERROR("Only received RSVD IRQs 0x%08x\n", master_ctl);
> +		return IRQ_NONE;
> +	}
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +
> +	/* NB: Posting read isn't necessary here because we're required to do
> +	 * another read no matter what
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +	*/
> +
> +	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +
> +	if (master_ctl & GEN8_DE_MISC_IRQ) {
> +		tmp = I915_READ(GEN8_DE_MISC_IIR);
> +		if (tmp) {
> +			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
> +			ret = IRQ_HANDLED;
> +		}
> +
> +		if (tmp & GEN8_DE_MISC_GSE)
> +			intel_opregion_asle_intr(dev);
> +		else if (tmp)
> +			DRM_ERROR("Unexpected DE Misc interrupt\n");
> +		else
> +			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
> +
> +	}
> +
> +	if (master_ctl & GEN8_DE_IRQS) {
> +		int de_ret = 0;
> +		int pipe;
> +		for_each_pipe(pipe) {
> +			uint32_t pipe_iir;
> +
> +		        pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
> +			if (pipe_iir & _PIPE_VBLANK) {
> +				drm_handle_vblank(dev, pipe);
> +			}
> +			if (pipe_iir & _PIPE_FLIP_DONE) {
> +				intel_prepare_page_flip(dev, pipe);
> +				intel_finish_page_flip_plane(dev, pipe);
> +			}
> +
> +			if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
> +				DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
> +
> +			if (pipe_iir) {
> +				de_ret++;
> +				ret = IRQ_HANDLED;
> +				I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
> +			}
> +		}
> +		if (!de_ret)
> +			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
> +	}
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return ret;
> +}
> +
>  static void i915_error_wake_up(struct drm_i915_private *dev_priv,
>  			       bool reset_completed)
>  {
> @@ -2052,6 +2181,25 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
>  	return 0;
>  }
>  
> +static int gen8_enable_vblank(struct drm_device *dev, int pipe)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long irqflags;
> +	uint32_t imr;
> +
> +	if (!i915_pipe_enabled(dev, pipe))
> +		return -EINVAL;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
> +	if ((imr & _PIPE_VBLANK) == 1) {
> +		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~_PIPE_VBLANK);
> +		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> +	}
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +	return 0;
> +}
> +
>  /* Called from drm generic code, passed 'crtc' which
>   * we use as a pipe index
>   */
> @@ -2100,6 +2248,24 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +static void gen8_disable_vblank(struct drm_device *dev, int pipe)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long irqflags;
> +	uint32_t imr;
> +
> +	if (!i915_pipe_enabled(dev, pipe))
> +		return;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
> +	if ((imr & _PIPE_VBLANK) == 0) {
> +		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | _PIPE_VBLANK);
> +		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
> +	}
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  static u32
>  ring_last_seqno(struct intel_ring_buffer *ring)
>  {
> @@ -2430,6 +2596,51 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
>  	POSTING_READ(VLV_IER);
>  }
>  
> +static void gen8_irq_preinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	atomic_set(&dev_priv->irq_received, 0);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	/* IIR can theoretically queue up two events. Be paranoid */
> +#define GEN8_IRQ_INIT_NDX(type, which) \
> +	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> +	POSTING_READ(GEN8_##type##_IMR(which)); \
> +	I915_WRITE(GEN8_##type##_IER(which), 0); \
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
> +	POSTING_READ(GEN8_##type##_IIR(which)); \
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff)
> +
> +#define GEN8_IRQ_INIT(type) \
> +	I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
> +	POSTING_READ(GEN8_##type##_IMR); \
> +	I915_WRITE(GEN8_##type##_IER, 0); \
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
> +	POSTING_READ(GEN8_##type##_IIR); \
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff)
> +
> +	GEN8_IRQ_INIT_NDX(GT, 0);
> +	GEN8_IRQ_INIT_NDX(GT, 1);
> +	GEN8_IRQ_INIT_NDX(GT, 2);
> +	GEN8_IRQ_INIT_NDX(GT, 3);
> +
> +	for_each_pipe(pipe) {
> +		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
> +	}
> +
> +	GEN8_IRQ_INIT(DE_PORT);
> +	GEN8_IRQ_INIT(DE_MISC);
> +	GEN8_IRQ_INIT(PCU);
> +#undef GEN8_IRQ_INIT
> +#undef GEN8_IRQ_INIT_NDX
> +
> +	POSTING_READ(GEN8_PCU_IIR);
> +}
> +
>  static void ibx_hpd_irq_setup(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -2635,6 +2846,114 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  	return 0;
>  }
>  
> +static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	int i;
> +
> +	/* These are interrupts we'll toggle with the ring mask register */
> +	uint32_t gt_interrupts[] = {
> +		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> +			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
> +			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
> +		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
> +			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
> +		0,
> +		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
> +		};
> +
> +	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
> +		u32 tmp = I915_READ(GEN8_GT_IIR(i));
> +		if (tmp)
> +			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
> +				  i, tmp);
> +		I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
> +		I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
> +	}
> +	POSTING_READ(GEN8_GT_IER(0));
> +}
> +
> +static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	uint32_t de_pipe_enables = _PIPE_FLIP_DONE |
> +				   _PIPE_SCAN_LINE_EVENT |
> +				   _PIPE_VBLANK |
> +				   GEN8_DE_PIPE_IRQ_ERRORS;
> +	int pipe;
> +	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
> +	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
> +	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
> +
> +	for_each_pipe(pipe) {
> +		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
> +		if (tmp)
> +			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
> +				  pipe, tmp);
> +		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> +		I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
> +	}
> +	POSTING_READ(GEN8_DE_PIPE_ISR(0));
> +
> +	I915_WRITE(GEN8_DE_PORT_IMR, ~_PORT_DP_A_HOTPLUG);
> +	I915_WRITE(GEN8_DE_PORT_IER, _PORT_DP_A_HOTPLUG);
> +	POSTING_READ(GEN8_DE_PORT_IER);
> +}
> +
> +static int gen8_irq_postinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	gen8_gt_irq_postinstall(dev_priv);
> +	gen8_de_irq_postinstall(dev_priv);
> +
> +	ibx_irq_postinstall(dev);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> +	POSTING_READ(GEN8_MASTER_IRQ);
> +
> +	return 0;
> +}
> +
> +static void gen8_irq_uninstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	if (!dev_priv)
> +		return;
> +
> +	atomic_set(&dev_priv->irq_received, 0);
> +
> +	I915_WRITE(GEN8_MASTER_IRQ, 0);
> +
> +#define GEN8_IRQ_FINI_NDX(type, which) \
> +	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> +	I915_WRITE(GEN8_##type##_IER(which), 0); \
> +	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff)
> +
> +#define GEN8_IRQ_FINI(type) \
> +	I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
> +	I915_WRITE(GEN8_##type##_IER, 0); \
> +	I915_WRITE(GEN8_##type##_IIR, 0xffffffff)
> +
> +	GEN8_IRQ_FINI_NDX(GT, 0);
> +	GEN8_IRQ_FINI_NDX(GT, 1);
> +	GEN8_IRQ_FINI_NDX(GT, 2);
> +	GEN8_IRQ_FINI_NDX(GT, 3);
> +
> +	for_each_pipe(pipe) {
> +		GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
> +	}
> +
> +	GEN8_IRQ_FINI(DE_PORT);
> +	GEN8_IRQ_FINI(DE_MISC);
> +	GEN8_IRQ_FINI(PCU);
> +#undef GEN8_IRQ_FINI
> +#undef GEN8_IRQ_FINI_NDX
> +
> +	POSTING_READ(GEN8_PCU_IIR);
> +}
> +
>  static void valleyview_irq_uninstall(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -3414,6 +3733,14 @@ void intel_irq_init(struct drm_device *dev)
>  		dev->driver->enable_vblank = valleyview_enable_vblank;
>  		dev->driver->disable_vblank = valleyview_disable_vblank;
>  		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (IS_GEN8(dev)) {
> +		dev->driver->irq_handler = gen8_irq_handler;
> +		dev->driver->irq_preinstall = gen8_irq_preinstall;
> +		dev->driver->irq_postinstall = gen8_irq_postinstall;
> +		dev->driver->irq_uninstall = gen8_irq_uninstall;
> +		dev->driver->enable_vblank = gen8_enable_vblank;
> +		dev->driver->disable_vblank = gen8_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		dev->driver->irq_handler = ironlake_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_preinstall;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb6ad89..b801b88 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3989,6 +3989,69 @@
>  #define GTIIR   0x44018
>  #define GTIER   0x4401c
>  
> +#define GEN8_MASTER_IRQ			0x44200
> +#define  GEN8_PCU_IRQ			(1<<30)
> +#define  GEN8_DE_PCH_IRQ		(1<<23)
> +#define  GEN8_DE_MISC_IRQ		(1<<22)
> +#define  GEN8_DE_PORT_IRQ		(1<<20)
> +#define  GEN8_DE_PIPE_C_IRQ		(1<<18)
> +#define  GEN8_DE_PIPE_B_IRQ		(1<<17)
> +#define  GEN8_DE_PIPE_A_IRQ		(1<<16)
> +#define  GEN8_GT_VECS_IRQ		(1<<6)
> +#define  GEN8_GT_VCS2_IRQ		(1<<3)
> +#define  GEN8_GT_VCS1_IRQ		(1<<2)
> +#define  GEN8_GT_BCS_IRQ		(1<<1)
> +#define  GEN8_GT_RCS_IRQ		(1<<0)
> +/* Lazy definition */
> +#define  GEN8_GT_IRQS			0x000000ff
> +#define  GEN8_DE_IRQS			0x01ff0000
> +#define  GEN8_RSVD_IRQS			0xB700ff00
> +
> +#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
> +#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
> +#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
> +#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
> +
> +#define GEN8_BCS_IRQ_SHIFT 16
> +#define GEN8_RCS_IRQ_SHIFT 0
> +#define GEN8_VCS2_IRQ_SHIFT 16
> +#define GEN8_VCS1_IRQ_SHIFT 0
> +#define GEN8_VECS_IRQ_SHIFT 0
> +
> +#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
> +#define  _PIPE_UNDERRUN			(1 << 31)
> +#define  _PIPE_CDCLK_CRC_ERROR		(1 << 29)
> +#define  _PIPE_CURSOR_FAULT		(1 << 10)
> +#define  _PIPE_SPRITE_FAULT		(1 << 9)
> +#define  _PIPE_PRIMARY_FAULT		(1 << 8)
> +#define  _PIPE_SPRITE_FLIP_DONE		(1 << 5)
> +#define  _PIPE_FLIP_DONE		(1 << 4)
> +#define  _PIPE_SCAN_LINE_EVENT		(1 << 3)
> +#define  _PIPE_VBLANK			(1 << 0)
> +#define GEN8_DE_PIPE_IRQ_ERRORS	(_PIPE_UNDERRUN | _PIPE_CDCLK_CRC_ERROR | \
> +				_PIPE_CURSOR_FAULT | _PIPE_SPRITE_FAULT | \
> +				_PIPE_PRIMARY_FAULT)
> +
> +#define GEN8_DE_PORT_ISR 0x44440
> +#define GEN8_DE_PORT_IMR 0x44444
> +#define GEN8_DE_PORT_IIR 0x44448
> +#define GEN8_DE_PORT_IER 0x4444c
> +#define  _PORT_DP_A_HOTPLUG		(1 << 3)
> +
> +#define GEN8_DE_MISC_ISR 0x44460
> +#define GEN8_DE_MISC_IMR 0x44464
> +#define GEN8_DE_MISC_IIR 0x44468
> +#define GEN8_DE_MISC_IER 0x4446c
> +#define  GEN8_DE_MISC_GSE		(1 << 27)
> +
> +#define GEN8_PCU_ISR 0x444e0
> +#define GEN8_PCU_IMR 0x444e4
> +#define GEN8_PCU_IIR 0x444e8
> +#define GEN8_PCU_IER 0x444ec
> +
>  #define ILK_DISPLAY_CHICKEN2	0x42004
>  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
>  #define  ILK_ELPIN_409_SELECT	(1 << 25)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2dec134..b2161f2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1066,6 +1066,48 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
>  }
>  
> +static bool
> +gen8_ring_get_irq(struct intel_ring_buffer *ring)
> +{
> +	struct drm_device *dev = ring->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long flags;
> +
> +	if (!dev->irq_enabled)
> +	       return false;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, flags);
> +	if (ring->irq_refcount++ == 0) {
> +		if (HAS_L3_DPF(dev) && ring->id == RCS)
> +			I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
> +						GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
> +		else
> +			I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
> +		POSTING_READ(RING_IMR(ring->mmio_base));
> +	}
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> +
> +	return true;
> +}
> +
> +static void
> +gen8_ring_put_irq(struct intel_ring_buffer *ring)
> +{
> +	struct drm_device *dev = ring->dev;
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, flags);
> +	if (--ring->irq_refcount == 0) {
> +		if (HAS_L3_DPF(dev) && ring->id == RCS)
> +			I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> +		else
> +			I915_WRITE_IMR(ring, ~0);
> +		POSTING_READ(RING_IMR(ring->mmio_base));
> +	}
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> +}
> +
>  static int
>  i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
>  			 u32 offset, u32 length,
> @@ -1732,8 +1774,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  		ring->flush = gen7_render_ring_flush;
>  		if (INTEL_INFO(dev)->gen == 6)
>  			ring->flush = gen6_render_ring_flush;
> -		ring->irq_get = gen6_ring_get_irq;
> -		ring->irq_put = gen6_ring_put_irq;
> +		if (INTEL_INFO(dev)->gen >= 8) {
> +			ring->irq_get = gen8_ring_get_irq;
> +			ring->irq_put = gen8_ring_put_irq;
> +		} else {
> +			ring->irq_get = gen6_ring_get_irq;
> +			ring->irq_put = gen6_ring_put_irq;
> +		}
>  		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>  		ring->get_seqno = gen6_ring_get_seqno;
>  		ring->set_seqno = ring_set_seqno;
> @@ -1897,9 +1944,15 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  		ring->add_request = gen6_add_request;
>  		ring->get_seqno = gen6_ring_get_seqno;
>  		ring->set_seqno = ring_set_seqno;
> -		ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> -		ring->irq_get = gen6_ring_get_irq;
> -		ring->irq_put = gen6_ring_put_irq;
> +		if (INTEL_INFO(dev)->gen >= 8) {
> +			ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
> +			ring->irq_get = gen8_ring_get_irq;
> +			ring->irq_put = gen8_ring_put_irq;
> +		} else {
> +			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> +			ring->irq_get = gen6_ring_get_irq;
> +			ring->irq_put = gen6_ring_put_irq;
> +		}
>  		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  		ring->sync_to = gen6_ring_sync;
>  		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> @@ -1946,9 +1999,15 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>  	ring->add_request = gen6_add_request;
>  	ring->get_seqno = gen6_ring_get_seqno;
>  	ring->set_seqno = ring_set_seqno;
> -	ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> -	ring->irq_get = gen6_ring_get_irq;
> -	ring->irq_put = gen6_ring_put_irq;
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> +		ring->irq_get = gen8_ring_get_irq;
> +		ring->irq_put = gen8_ring_put_irq;
> +	} else {
> +		ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> +		ring->irq_get = gen6_ring_get_irq;
> +		ring->irq_put = gen6_ring_put_irq;
> +	}
>  	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  	ring->sync_to = gen6_ring_sync;
>  	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> @@ -1978,10 +2037,19 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>  	ring->add_request = gen6_add_request;
>  	ring->get_seqno = gen6_ring_get_seqno;
>  	ring->set_seqno = ring_set_seqno;
> -	ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> -	ring->irq_get = hsw_vebox_get_irq;
> -	ring->irq_put = hsw_vebox_put_irq;
>  	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> +
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		ring->irq_enable_mask =
> +			(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT) |
> +			GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
> +		ring->irq_get = gen8_ring_get_irq;
> +		ring->irq_put = gen8_ring_put_irq;
> +	} else {
> +		ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> +		ring->irq_get = hsw_vebox_get_irq;
> +		ring->irq_put = hsw_vebox_put_irq;
> +	}
>  	ring->sync_to = gen6_ring_sync;
>  	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
>  	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
> -- 
> 1.8.4.2
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 22/62] drm/i915/bdw: Implement Full Force Miss disables

[Daniel Vetter]

On Tue, Nov 05, 2013 at 05:17:26PM +0100, Daniel Vetter wrote:
> On Tue, Nov 05, 2013 at 05:41:21PM +0200, Imre Deak wrote:
> > On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> > > Implements WaVSRefCountFullforceMissDisable
> > > Implements WaDSRefCountFullforceMissDisable
> > > 
> > > v2: Rebased on the HSW patch (which fixed the bug from v1)
> > > commit 41c0b3a88c7bae96d8e2ee60c7ed91f57fd152d7
> > > Author: Ben Widawsky <ben@bwidawsk.net>
> > > Date:   Sat Jan 26 11:52:00 2013 -0800
> > > 
> > >     drm/i915: Implement WaVSRefCountFullforceMissDisable
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 1 +
> > >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> > >  2 files changed, 5 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 9929750..68b877d 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -990,6 +990,7 @@
> > >  
> > >  #define GEN7_FF_THREAD_MODE		0x20a0
> > >  #define   GEN7_FF_SCHED_MASK		0x0077070
> > > +#define   GEN7_FF_DS_REF_CNT_FFME	(1 << 19)
> > >  #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
> > >  #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
> > >  #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index abc51ea..81ec2c3 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5147,6 +5147,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> > >  	if (IS_HASWELL(dev_priv->dev))
> > >  		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
> > >  
> > > +	/* WaVSRefCountFullforceMissDisable|WaDSRefCountFullforceMissDisable */
> > > +	if (IS_GEN8(dev_priv->dev))
> > > +		reg &= ~(GEN7_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
> > > +
> > >  	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
> > >  }
> > 
> > gen7_setup_fixed_func_scheduler() isn't called for GEN8.
> 
> I've just looked at the history of the quilt tree and it's been like that
> ever since I've merged the patch apparently. Probably mis-wiggled while
> applying ... Ben, should I just move this to the gen8 clock gating?

I've dropped this one for now.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 51/62] drm/i915/bdw: Use HSW formula for ring freq scaling

[Daniel Vetter]

On Sat, Nov 02, 2013 at 09:07:49PM -0700, Ben Widawsky wrote:
> The current formula we use for HSW is not what is in current docs.
> However, changing to the HSW formula on my HSW does not improve power
> usage, and decreases performance by about 5% in limited xonotic testing.
> 
> For gen8, until we know otherwise, or run experiments, let's use
> the HSW formula - which should be the same used in the Windows driver
> (and thus help make an apples-applies comparison) on gen8.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6d14182..3dd30f7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,7 +3924,10 @@ void gen6_update_ring_freq(struct drm_device *dev)
>  		int diff = dev_priv->rps.max_delay - gpu_freq;
>  		unsigned int ia_freq = 0, ring_freq = 0;
>  
> -		if (IS_HASWELL(dev)) {
> +		if (INTEL_INFO(dev)->gen > 7) {

Our coding style is to use >= 8 or < 8 to be consistent with 0 based C
arrays and so hopefully avoiding off-by-ones. I.e. I've spent a bit of
time being stumped until I've noticed that this is gen8+ and actually
doesn't apply to ivb. Fixed while applying.
-Daniel

> +			/* max(2 * GT, DDR). NB: GT is 50MHz units */
> +			ring_freq = max(min_ring_freq, gpu_freq);
> +		} else if (IS_HASWELL(dev)) {
>  			ring_freq = mult_frac(gpu_freq, 5, 4);
>  			ring_freq = max(min_ring_freq, ring_freq);
>  			/* leave ia_freq as the default, chosen by cpufreq */
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 56/62] drm/i915/bdw: Implement edp PSR workarounds

[Daniel Vetter]

On Sat, Nov 02, 2013 at 09:07:54PM -0700, Ben Widawsky wrote:
> This implements a workaround for PSR dealing with some vblank issue.
> 
> WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD
> 
> v2: forgot to git add bogus whitespace fix
> 
> v3: Update with workaround names.
> Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)
> 
> Cc: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
>  drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
>  2 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f97836e..9608f96 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4092,8 +4092,14 @@
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
>  
>  #define CHICKEN_PAR1_1		0x42080
> +#define  DPA_MASK_VBLANK_SRD	(1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
>  
> +#define _CHICKEN_PIPESL_1_A	0x420b0
> +#define _CHICKEN_PIPESL_1_B	0x420b4
> +#define  DPRS_MASK_VBLANK_SRD	(1 << 0)
> +#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> +
>  #define DISP_ARB_CTL	0x45000
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0245985..63f6e59 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5288,6 +5288,23 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  
>  	/* WaSwitchSolVfFArbitrationPriority */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> +
> +	if (IS_BROADWELL(dev)) {

This check looks funny in a function which only runs on bdw. I've killed
it.
-Daniel

> +		enum pipe i;
> +
> +		/* WaPsrDPAMaskVBlankInSRD */
> +		I915_WRITE(CHICKEN_PAR1_1,
> +			   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> +
> +		/* WaPsrDPRSUnmaskVBlankInSRD */
> +		for_each_pipe(i) {
> +			I915_WRITE(CHICKEN_PIPESL_1(i),
> +				   I915_READ(CHICKEN_PIPESL_1(i) |
> +					     DPRS_MASK_VBLANK_SRD));
> +		}
> +	}
> +
> +
>  }
>  
>  static void haswell_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR

[Kumar, Kiran S]

Hi Ben,

Can you please let me know the reason for explicit about not setting min link entry time for BDW. During my PSR testing on BDW, I found perf counter not getting increment and SRD control is setting to 0x0 with the following check:
 	IS_BROADWELL(dev) ? 0 : link_entry_time

When I remove and used only "link_entry_time" without check for BDW, PSR worked fine. (perf counter started incrementing)

Thanks
Kiran

-----Original Message-----
From: intel-gfx-bounces@lists.freedesktop.org [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Ben Widawsky
Sent: Tuesday, November 05, 2013 12:15 PM
To: Intel GFX
Cc: Nikula, Jani; Ben Widawsky; Widawsky, Benjamin
Subject: [Intel-gfx] [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR

Broadwell PSR support is a superset of Haswell. With this simple register base calculation, everything that worked on HSW for eDP PSR should work on BDW.

Note that Broadwell provides additional PSR support. This is not addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

v5: Be explicit about not setting min link entry time for BDW. This should be no functional change over v4 (Jani)

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--  drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f222eb4..dc79a0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev))
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba1fe7e..3761c80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1959,8 +1959,8 @@
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)  #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
-/* HSW eDP PSR registers */
-#define EDP_PSR_BASE(dev)			0x64800
+/* HSW+ eDP PSR registers */
+#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
 #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   EDP_PSR_LINK_DISABLE			(0<<27)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7725f81..6e4246f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1603,6 +1603,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t max_sleep_time = 0x1f;
 	uint32_t idle_frames = 1;
 	uint32_t val = 0x0;
+	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_LINK_STANDBY;
@@ -1613,7 +1614,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_LINK_DISABLE;
 
 	I915_WRITE(EDP_PSR_CTL(dev), val |
-		   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
+		   IS_BROADWELL(dev) ? 0 : link_entry_time |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 		   EDP_PSR_ENABLE);
--
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR

[Ben Widawsky]

This is a bug. Someone needs to send me back to C-programmer school.

Bits 26:25 are reserved in the spec. Furthermore, there shouldn't be a
functional difference since link_entry_time =
EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0<<25). So you found the bug, but I
think the solution is actually:

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c512d78..2c0ceb4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1723,7 +1723,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
                val |= EDP_PSR_LINK_DISABLE;
 
        I915_WRITE(EDP_PSR_CTL(dev), val |
-                  IS_BROADWELL(dev) ? 0 : link_entry_time |
+                  (IS_BROADWELL(dev) ? 0 : link_entry_time) |
                   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
                   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
                   EDP_PSR_ENABLE);




On Tue, Mar 04, 2014 at 09:31:28AM +0000, Kumar, Kiran S wrote:
> Hi Ben,
> 
> Can you please let me know the reason for explicit about not setting min link entry time for BDW. During my PSR testing on BDW, I found perf counter not getting increment and SRD control is setting to 0x0 with the following check:
>  	IS_BROADWELL(dev) ? 0 : link_entry_time
> 
> When I remove and used only "link_entry_time" without check for BDW, PSR worked fine. (perf counter started incrementing)
> 
> Thanks
> Kiran
> 
> -----Original Message-----
> From: intel-gfx-bounces@lists.freedesktop.org [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Ben Widawsky
> Sent: Tuesday, November 05, 2013 12:15 PM
> To: Intel GFX
> Cc: Nikula, Jani; Ben Widawsky; Widawsky, Benjamin
> Subject: [Intel-gfx] [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR
> 
> Broadwell PSR support is a superset of Haswell. With this simple register base calculation, everything that worked on HSW for eDP PSR should work on BDW.
> 
> Note that Broadwell provides additional PSR support. This is not addressed at this time.
> 
> v2: Make the HAS_PSR include BDW
> 
> v3: Use the correct offset (I had incorrectly used one from my faulty
> brain) (Art!)
> 
> v4: It helps if you git add
> 
> v5: Be explicit about not setting min link entry time for BDW. This should be no functional change over v4 (Jani)
> 
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--  drivers/gpu/drm/i915/intel_dp.c | 3 ++-
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f222eb4..dc79a0f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)		(IS_HASWELL(dev))
> +#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba1fe7e..3761c80 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1959,8 +1959,8 @@
>  #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)  #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>  
> -/* HSW eDP PSR registers */
> -#define EDP_PSR_BASE(dev)			0x64800
> +/* HSW+ eDP PSR registers */
> +#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
>  #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   EDP_PSR_LINK_DISABLE			(0<<27)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7725f81..6e4246f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1603,6 +1603,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
>  	uint32_t max_sleep_time = 0x1f;
>  	uint32_t idle_frames = 1;
>  	uint32_t val = 0x0;
> +	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>  
>  	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>  		val |= EDP_PSR_LINK_STANDBY;
> @@ -1613,7 +1614,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
>  		val |= EDP_PSR_LINK_DISABLE;
>  
>  	I915_WRITE(EDP_PSR_CTL(dev), val |
> -		   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
> +		   IS_BROADWELL(dev) ? 0 : link_entry_time |
>  		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>  		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
>  		   EDP_PSR_ENABLE);
> --
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Ben Widawsky, Intel Open Source Technology Center