[U-Boot] [PATCH 1/5] ARM: armv7: Make indirect vector addresses globl

[U-Boot] [PATCH 1/5] ARM: armv7: Make indirect vector addresses globl

[Marek Vasut]

Make indirect vectors addresses global, so they can be replaced by
various code that needs to do so. For example the MX6 PCI express
driver needs to temporarily replace data abort handler when reading
the config space.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/start.S | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 6c9b11a..5aac773 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -38,12 +38,19 @@ _irq:			.word _irq
 _fiq:			.word _fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #else
+.globl _undefined_instruction
 _undefined_instruction: .word undefined_instruction
+.globl _software_interrupt
 _software_interrupt:	.word software_interrupt
+.globl _prefetch_abort
 _prefetch_abort:	.word prefetch_abort
+.globl _data_abort
 _data_abort:		.word data_abort
+.globl _not_used
 _not_used:		.word not_used
+.globl _irq
 _irq:			.word irq
+.globl _fiq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
-- 
1.8.4.rc3

[U-Boot] [PATCH 2/5] ARM: lib: Add cpu_clock_teardown() call

[Marek Vasut]

Add cpu_clock_teardown() call before the Linux kernel is started,
so the CPU code can stop clock that may hinder the Linux's boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7e..75f8a33 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -23,6 +23,7 @@
 #include <linux/compiler.h>
 
 void __weak cpu_cache_initialization(void){}
+void __weak cpu_clock_teardown(void) {}
 
 int cleanup_before_linux(void)
 {
@@ -66,5 +67,8 @@ int cleanup_before_linux(void)
 	 */
 	cpu_cache_initialization();
 
+	/* Let CPUs stop clock that might hinder Linux's boot. */
+	cpu_clock_teardown();
+
 	return 0;
 }
-- 
1.8.4.rc3

[U-Boot] [PATCH 3/5] ARM: mx6: Add PCI express clock configuration

[Marek Vasut]

Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx6/clock.c        | 84 ++++++++++++++++++++++++++++++-----
 arch/arm/include/asm/arch-mx6/clock.h |  1 +
 2 files changed, 75 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index df11678..3101cb9 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -376,17 +376,12 @@ u32 imx_get_fecclk(void)
 	return decode_pll(PLL_ENET, MXC_HCLK);
 }
 
-int enable_sata_clock(void)
+static int enable_enet_pll(uint32_t en)
 {
-	u32 reg = 0;
-	s32 timeout = 100000;
 	struct mxc_ccm_reg *const imx_ccm
 		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
-
-	/* Enable sata clock */
-	reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
-	reg |= MXC_CCM_CCGR5_SATA_MASK;
-	writel(reg, &imx_ccm->CCGR5);
+	s32 timeout = 100000;
+	u32 reg = 0;
 
 	/* Enable PLLs */
 	reg = readl(&imx_ccm->analog_pll_enet);
@@ -401,10 +396,79 @@ int enable_sata_clock(void)
 		return -EIO;
 	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 	writel(reg, &imx_ccm->analog_pll_enet);
-	reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+	reg |= en;
 	writel(reg, &imx_ccm->analog_pll_enet);
+	return 0;
+}
+
+static void ungate_sata_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *) CCM_BASE_ADDR;
+
+	/* Enable SATA clock. */
+	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+
+static void ungate_pcie_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *) CCM_BASE_ADDR;
+
+	/* Enable PCIe clock. */
+	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
+int enable_sata_clock(void)
+{
+	ungate_sata_clock();
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+int enable_pcie_clock(void)
+{
+	struct anatop_regs *anatop_regs =
+		(struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * Here be dragons!
+	 *
+	 * The register ANATOP_MISC1 is not documented in the Freescale
+	 * MX6RM. The register that is mapped in the ANATOP space and
+	 * marked as ANATOP_MISC1 is actually documented in the PMU section
+	 * of the datasheet as PMU_MISC1.
+	 *
+	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
+	 * enable clock OUTPUT. This is important for PCI express link that
+	 * is clocked from the i.MX6.
+	 */
+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
+#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+	clrsetbits_le32(&anatop_regs->ana_misc1,
+			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+
+	/* PCIe reference clock sourced from AXI. */
+	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
+	/* Party time! Ungate the clock to the PCIe. */
+	ungate_sata_clock();
+	ungate_pcie_clock();
+
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+}
+
+void cpu_clock_teardown(void)
+{
+	struct anatop_regs *anatop_regs =
+		(struct anatop_regs *)ANATOP_BASE_ADDR;
 
-	return 0 ;
+	/* Stop the PCIe/LVDS clock source before booting Linux. */
+	writel(0, &anatop_regs->ana_misc1);
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 93f29a7..95b1270 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -48,6 +48,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
+int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(void);
-- 
1.8.4.rc3

[U-Boot] [PATCH 4/5] ARM: mx6: Add PCI express driver

[Marek Vasut]

Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mx6/iomux.h |  30 ++
 drivers/pci/Makefile                  |   1 +
 drivers/pci/pcie_imx.c                | 560 ++++++++++++++++++++++++++++++++++
 3 files changed, 591 insertions(+)
 create mode 100644 drivers/pci/pcie_imx.c

diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index ff13a1e..bf727a9 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -10,6 +10,36 @@
 #define MX6_IOMUXC_GPR7		0x020e001c
 
 /*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET		0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK	(0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET	6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK		(0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET	12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK		(0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET		18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK		(0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET		25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+
+/*
  * IOMUXC_GPR13 bit fields
  */
 #define IOMUXC_GPR13_SDMA_STOP_REQ	(1<<30)
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index be26b60..46c5c9a 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 COBJS-$(CONFIG_PCI) += pci.o pci_auto.o
 COBJS-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
 COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+COBJS-$(CONFIG_PCIE_IMX) += pcie_imx.o
 COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
 COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
 COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
new file mode 100644
index 0000000..12e3546
--- /dev/null
+++ b/drivers/pci/pcie_imx.c
@@ -0,0 +1,560 @@
+/*
+ * Freescale i.MX6 PCI Express Root-Complex driver
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Based on upstream Linux kernel driver:
+ * pci-imx6.c:		Sean Cross <xobs@kosagi.com>
+ * pcie-designware.c:	Jingoo Han <jg1.han@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <errno.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define MX6_DBI_ADDR	0x01ffc000
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_ADDR	0x01000000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_ADDR	0x01100000
+#define MX6_MEM_SIZE	0xe00000
+#define MX6_ROOT_ADDR	0x01f00000
+#define MX6_ROOT_SIZE	0xfc000
+
+/* PCIe Port Logic registers (memory-mapped) */
+#define PL_OFFSET 0x700
+#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
+#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+
+#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
+#define PCIE_PHY_CTRL_DATA_LOC 0
+#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
+#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
+#define PCIE_PHY_CTRL_WR_LOC 18
+#define PCIE_PHY_CTRL_RD_LOC 19
+
+#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
+#define PCIE_PHY_STAT_DATA_LOC 0
+#define PCIE_PHY_STAT_ACK_LOC 16
+
+/* PHY registers (not memory-mapped) */
+#define PCIE_PHY_RX_ASIC_OUT 0x100D
+
+#define PHY_RX_OVRD_IN_LO 0x1005
+#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
+#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+
+/* iATU registers */
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
+/*
+ * PHY access functions
+ */
+static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
+{
+	u32 val;
+	u32 max_iterations = 10;
+	u32 wait_counter = 0;
+
+	do {
+		val = readl(dbi_base + PCIE_PHY_STAT);
+		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
+		wait_counter++;
+
+		if (val == exp_val)
+			return 0;
+
+		udelay(1);
+	} while (wait_counter < max_iterations);
+
+	return -ETIMEDOUT;
+}
+
+static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
+{
+	u32 val;
+	int ret;
+
+	val = addr << PCIE_PHY_CTRL_DATA_LOC;
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	val = addr << PCIE_PHY_CTRL_DATA_LOC;
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
+static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
+{
+	u32 val, phy_ctl;
+	int ret;
+
+	ret = pcie_phy_wait_ack(dbi_base, addr);
+	if (ret)
+		return ret;
+
+	/* assert Read signal */
+	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
+	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	val = readl(dbi_base + PCIE_PHY_STAT);
+	*data = val & 0xffff;
+
+	/* deassert Read signal */
+	writel(0x00, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
+{
+	u32 var;
+	int ret;
+
+	/* write addr */
+	/* cap addr */
+	ret = pcie_phy_wait_ack(dbi_base, addr);
+	if (ret)
+		return ret;
+
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* capture data */
+	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	/* deassert cap data */
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack de-assertion */
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	/* assert wr signal */
+	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack */
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	/* deassert wr signal */
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack de-assertion */
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	writel(0x0, dbi_base + PCIE_PHY_CTRL);
+
+	return 0;
+}
+
+static int imx6_pcie_link_up(void)
+{
+	u32 rc, ltssm;
+	int rx_valid, temp;
+
+	/* link is debug bit 36, debug register 1 starts@bit 32 */
+	rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
+	if (rc)
+		return -EAGAIN;
+
+	/*
+	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
+	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
+	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
+	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
+	 * to gen2 is stuck
+	 */
+	pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
+	ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
+
+	if (rx_valid & 0x01)
+		return 0;
+
+	if (ltssm != 0x0d)
+		return 0;
+
+	printf("transition to gen2 is stuck, reset PHY!\n");
+
+	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
+	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
+
+	udelay(3000);
+
+	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
+	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
+
+	return 0;
+}
+
+/*
+ * iATU region setup
+ */
+static int imx_pcie_regions_setup(void)
+{
+	/*
+	 * i.MX6 defines 16MB in the AXI address map for PCIe.
+	 *
+	 * That address space excepted the pcie registers is
+	 * split and defined into different regions by iATU,
+	 * with sizes and offsets as follows:
+	 *
+	 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
+	 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
+	 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
+	 */
+
+	/* CMD reg:I/O space, MEM space, and Bus Master Enable */
+	setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
+		     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+	setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
+		     PCI_CLASS_BRIDGE_PCI << 16);
+
+	/* Region #0 is used for Outbound CFG space access. */
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
+
+	writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
+	writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
+
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
+	writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
+	writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
+
+	return 0;
+}
+
+/*
+ * PCI Express accessors
+ */
+static uint32_t get_bus_address(pci_dev_t d, int where)
+{
+	uint32_t va_address;
+
+	/* Reconfigure Region #0 */
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
+
+	if (PCI_BUS(d) < 2)
+		writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
+	else
+		writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
+
+	if (PCI_BUS(d) == 0) {
+		va_address = MX6_DBI_ADDR;
+	} else {
+		writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
+		va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
+	}
+
+	va_address += (where & ~0x3);
+
+	return va_address;
+}
+
+static int imx_pcie_addr_valid(pci_dev_t d)
+{
+	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
+		return -EINVAL;
+	if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
+		return -EINVAL;
+	return 0;
+}
+
+/*
+ * Replace the original ARM DABT handler with a simple jump-back one.
+ *
+ * The problem here is that if we have a PCIe bridge attached to this PCIe
+ * controller, but no PCIe device is connected to the bridges' downstream
+ * port, the attempt to read/write from/to the config space will produce
+ * a DABT. This is a behavior of the controller and can not be disabled
+ * unfortuatelly.
+ *
+ * To work around the problem, we backup the current DABT handler address
+ * and replace it with our own DABT handler, which only bounces right back
+ * into the code.
+ */
+static void imx_pcie_fix_dabt_handler(bool set)
+{
+	extern uint32_t *_data_abort;
+	uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
+
+	static const uint32_t data_abort_bounce_handler = 0xe25ef004;
+	uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
+
+	static uint32_t data_abort_backup;
+
+	if (set) {
+		data_abort_backup = *data_abort_addr;
+		*data_abort_addr = data_abort_bounce_addr;
+	} else {
+		*data_abort_addr = data_abort_backup;
+	}
+}
+
+static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
+				int where, u32 *val)
+{
+	uint32_t va_address;
+	int ret;
+
+	ret = imx_pcie_addr_valid(d);
+	if (ret) {
+		*val = 0xffffffff;
+		return ret;
+	}
+
+	va_address = get_bus_address(d, where);
+
+	/*
+	 * Read the PCIe config space. We must replace the DABT handler
+	 * here in case we got data abort from the PCIe controller, see
+	 * imx_pcie_fix_dabt_handler() description. Note that writing the
+	 * "val" with valid value is also imperative here as in case we
+	 * did got DABT, the val would contain random value.
+	 */
+	imx_pcie_fix_dabt_handler(true);
+	writel(0xffffffff, val);
+	*val = readl(va_address);
+	imx_pcie_fix_dabt_handler(false);
+
+	return 0;
+}
+
+static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
+			int where, u32 val)
+{
+	uint32_t va_address = 0;
+	int ret;
+
+	ret = imx_pcie_addr_valid(d);
+	if (ret)
+		return ret;
+
+	va_address = get_bus_address(d, where);
+
+	/*
+	 * Write the PCIe config space. We must replace the DABT handler
+	 * here in case we got data abort from the PCIe controller, see
+	 * imx_pcie_fix_dabt_handler() description.
+	 */
+	imx_pcie_fix_dabt_handler(true);
+	writel(val, va_address);
+	imx_pcie_fix_dabt_handler(false);
+
+	return 0;
+}
+
+/*
+ * Initial bus setup
+ */
+static int imx6_pcie_assert_core_reset(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
+	/* FIXME: GPIO reset goes here */
+	mdelay(100);
+
+	return 0;
+}
+
+static int imx6_pcie_init_phy(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_DEVICE_TYPE_MASK,
+			IOMUXC_GPR12_DEVICE_TYPE_RC);
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_LOS_LEVEL_MASK,
+			IOMUXC_GPR12_LOS_LEVEL_9);
+
+	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
+	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
+	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
+	       (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
+	       (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
+	       &iomuxc_regs->gpr[8]);
+	
+	return 0;
+}
+
+static int imx6_pcie_deassert_core_reset(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* FIXME: Power-up GPIO goes here. */
+
+	/* Enable PCIe */
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
+	enable_pcie_clock();
+
+	/*
+	 * Wait for the clock to settle a bit, when the clock are sourced
+	 * from the CPU, we need about 30mS to settle.
+	 */
+	udelay(30000);
+
+	return 0;
+}
+
+static int imx_pcie_link_up(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	uint32_t tmp;
+	int count = 0;
+
+	imx6_pcie_assert_core_reset();
+	imx6_pcie_init_phy();
+	imx6_pcie_deassert_core_reset();
+
+	imx_pcie_regions_setup();
+
+	/*
+	 * FIXME: Force the PCIe RC to Gen1 operation
+	 * The RC must be forced into Gen1 mode before bringing the link
+	 * up, otherwise no downstream devices are detected. After the
+	 * link is up, a managed Gen1->Gen2 transition can be initiated.
+	 */
+	tmp = readl(MX6_DBI_ADDR + 0x7c);
+	tmp &= ~0xf;
+	tmp |= 0x1;
+	writel(tmp, MX6_DBI_ADDR + 0x7c);
+
+	/* LTSSM enable, starting link. */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+
+	while (!imx6_pcie_link_up()) {
+		udelay(1000);
+		count++;
+		if (count >= 2000) {
+			debug("phy link never came up\n");
+			debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
+			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
+			break;
+		}
+	}
+
+	return 0;
+}
+
+void imx_pcie_init(void)
+{
+	/* Static instance of the controller. */
+	static struct pci_controller	pcc;
+	struct pci_controller		*hose = &pcc;
+
+	memset(&pcc, 0, sizeof(pcc));
+
+	/* PCI I/O space */
+	pci_set_region(&hose->regions[0],
+		       MX6_IO_ADDR, MX6_IO_ADDR,
+		       MX6_IO_SIZE, PCI_REGION_IO);
+
+	/* PCI memory space */
+	pci_set_region(&hose->regions[1],
+		       MX6_MEM_ADDR, MX6_MEM_ADDR,
+		       MX6_MEM_SIZE, PCI_REGION_MEM);
+
+	/* System memory space */
+	pci_set_region(&hose->regions[2],
+		       MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
+		       0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 3;
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    imx_pcie_read_config,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    imx_pcie_write_config);
+
+	/* Start the controller. */
+	imx_pcie_link_up();
+
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+/* Probe function. */
+void pci_init_board(void)
+{
+	imx_pcie_init();
+}
-- 
1.8.4.rc3

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Enable PCI express on MX6 Sabrelite.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/boundary/nitrogen6x/nitrogen6x.c |  7 ++++++-
 include/configs/nitrogen6x.h           | 11 +++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 1712908..46be51e 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -369,7 +369,12 @@ int board_eth_init(bd_t *bis)
 		free(bus);
 	}
 #endif
-	return 0;
+
+#ifdef CONFIG_PCI
+	ret = pci_eth_init(bis);
+#endif
+
+	return ret;
 }
 
 static void setup_buttons(void)
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 3454b86..ccde896 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -355,4 +355,15 @@
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_CMD_FS_GENERIC
 
+/*
+ * PCI express
+ */
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
 #endif	       /* __CONFIG_H */
-- 
1.8.4.rc3

[U-Boot] [PATCH 1/5] ARM: armv7: Make indirect vector addresses globl

[Marek Vasut]

Hi

+Cc Sinan

> Make indirect vectors addresses global, so they can be replaced by
> various code that needs to do so. For example the MX6 PCI express
> driver needs to temporarily replace data abort handler when reading
> the config space.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  arch/arm/cpu/armv7/start.S | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 6c9b11a..5aac773 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -38,12 +38,19 @@ _irq:			.word _irq
>  _fiq:			.word _fiq
>  _pad:			.word 0x12345678 /* now 16*4=64 */
>  #else
> +.globl _undefined_instruction
>  _undefined_instruction: .word undefined_instruction
> +.globl _software_interrupt
>  _software_interrupt:	.word software_interrupt
> +.globl _prefetch_abort
>  _prefetch_abort:	.word prefetch_abort
> +.globl _data_abort
>  _data_abort:		.word data_abort
> +.globl _not_used
>  _not_used:		.word not_used
> +.globl _irq
>  _irq:			.word irq
> +.globl _fiq
>  _fiq:			.word fiq
>  _pad:			.word 0x12345678 /* now 16*4=64 */
>  #endif	/* CONFIG_SPL_BUILD */

Best regards,
Marek Vasut

[U-Boot] [PATCH 1/5] ARM: armv7: Make indirect vector addresses globl

[Stefano Babic]

On 11/11/2013 17:22, Marek Vasut wrote:
> Make indirect vectors addresses global, so they can be replaced by
> various code that needs to do so. For example the MX6 PCI express
> driver needs to temporarily replace data abort handler when reading
> the config space.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 2/5] ARM: lib: Add cpu_clock_teardown() call

[Stefano Babic]

On 11/11/2013 17:22, Marek Vasut wrote:
> Add cpu_clock_teardown() call before the Linux kernel is started,
> so the CPU code can stop clock that may hinder the Linux's boot.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 3/5] ARM: mx6: Add PCI express clock configuration

[Stefano Babic]

On 11/11/2013 17:22, Marek Vasut wrote:
> Split the SATA clock enabling function and add PCI express clock
> enabling function. The SATA clock enabling function starts up the
> 100MHz SATA reference PLL in ENET_PLL register, but the code can
> be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
> this code into separate function. Moreover, add the PCIe clock
> enabling code.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 4/5] ARM: mx6: Add PCI express driver

[Stefano Babic]

On 11/11/2013 17:22, Marek Vasut wrote:
> Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
> PCIe block in RC mode only, the EP mode is NOT supported. The driver is
> tested with the Intel e1000 NIC driver.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Stefano Babic]

On 11/11/2013 17:22, Marek Vasut wrote:
> Enable PCI express on MX6 Sabrelite.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 2/5] ARM: lib: Add cpu_clock_teardown() call

[Marek Vasut]

Hi,

> On 11/11/2013 17:22, Marek Vasut wrote:
> > Add cpu_clock_teardown() call before the Linux kernel is started,
> > so the CPU code can stop clock that may hinder the Linux's boot.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> 
> Applied to u-boot-imx, thanks.

Albert, you OK with this one ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Hi,

> On 11/11/2013 17:22, Marek Vasut wrote:
> > Enable PCI express on MX6 Sabrelite.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> > Cc: Fabio Estevam <fabio.estevam@freescale.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> 
> Applied to u-boot-imx, thanks.

Eric, is this one OK?

Best regards,
Marek Vasut

[U-Boot] [PATCH 2/5] ARM: lib: Add cpu_clock_teardown() call

[Stefano Babic]

Hi Marek,

On 27/11/2013 09:59, Marek Vasut wrote:
> Hi,
> 
>> On 11/11/2013 17:22, Marek Vasut wrote:
>>> Add cpu_clock_teardown() call before the Linux kernel is started,
>>> so the CPU code can stop clock that may hinder the Linux's boot.
>>>
>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> ---
>>
>> Applied to u-boot-imx, thanks.
> 
> Albert, you OK with this one ?
> 

I'll wait before pushing to the server.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Eric Nelson]

Hi Marek,

On 11/27/2013 01:59 AM, Marek Vasut wrote:
> Hi,
>
>> On 11/11/2013 17:22, Marek Vasut wrote:
>>> Enable PCI express on MX6 Sabrelite.
>>>
>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
>>> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
>>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> ---
>>
>> Applied to u-boot-imx, thanks.
>
> Eric, is this one OK?
>

It's okay by me in principle, though we haven't tested it
for any side effects.

I should be able to do that this morning, and pulling from
u-boot-imx will make that easier.

Regards,


Eric

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Hi Eric,

> Hi Marek,
> 
> On 11/27/2013 01:59 AM, Marek Vasut wrote:
> > Hi,
> > 
> >> On 11/11/2013 17:22, Marek Vasut wrote:
> >>> Enable PCI express on MX6 Sabrelite.
> >>> 
> >>> Signed-off-by: Marek Vasut <marex@denx.de>
> >>> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> >>> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> >>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> >>> Cc: Stefano Babic <sbabic@denx.de>
> >>> ---
> >> 
> >> Applied to u-boot-imx, thanks.
> > 
> > Eric, is this one OK?
> 
> It's okay by me in principle, though we haven't tested it
> for any side effects.
> 
> I should be able to do that this morning, and pulling from
> u-boot-imx will make that easier.

Cool, thanks :)

Best regards,
Marek Vasut

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Eric Nelson]

Thanks Marek,

On 11/11/2013 09:22 AM, Marek Vasut wrote:
> Enable PCI express on MX6 Sabrelite.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>   board/boundary/nitrogen6x/nitrogen6x.c |  7 ++++++-
>   include/configs/nitrogen6x.h           | 11 +++++++++++
>   2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
> index 1712908..46be51e 100644
> --- a/board/boundary/nitrogen6x/nitrogen6x.c
> +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> @@ -369,7 +369,12 @@ int board_eth_init(bd_t *bis)
>   		free(bus);
>   	}
>   #endif
> -	return 0;
> +

I think this bit needs a different configuration option
and should be disabled by default.

> +#ifdef CONFIG_PCI
> +	ret = pci_eth_init(bis);
> +#endif
> +

It seems to lock up the system if you don't have the proper
device connected.

Without this bit, I was able to confirm proper enumeration
of a PCIe bus with a USB 3.0 controller:

    00:01.0     - 16c3:abcd - Bridge device
    01:00.0    - 1b21:0612 - Mass storage controller

Unfortunately, in a quick test, the image fails to boot
without a PCIe device connected, or oddly, with a different
PCIe ethernet controller connected.

I think it's handy to have the placeholder here, but
I think you're the only person on the planet with the
right set of components to make it work at the moment.

Regards,


Eric

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Stefano Babic]

Hi Eric, Marek,

On 27/11/2013 17:19, Eric Nelson wrote:

> It seems to lock up the system if you don't have the proper
> device connected.
> 
> Without this bit, I was able to confirm proper enumeration
> of a PCIe bus with a USB 3.0 controller:
> 
>    00:01.0     - 16c3:abcd - Bridge device
>    01:00.0    - 1b21:0612 - Mass storage controller
> 
> Unfortunately, in a quick test, the image fails to boot
> without a PCIe device connected, or oddly, with a different
> PCIe ethernet controller connected.
> 
> I think it's handy to have the placeholder here, but
> I think you're the only person on the planet with the
> right set of components to make it work at the moment.

Waiting for someone from Mars is coming to help Marek, I'll put the
patchset in the -next for better testing.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Hi Eric,

> Thanks Marek,
> 
> On 11/11/2013 09:22 AM, Marek Vasut wrote:
> > Enable PCI express on MX6 Sabrelite.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Eric Nelson <eric.nelson@boundarydevices.com>
> > Cc: Fabio Estevam <fabio.estevam@freescale.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> > 
> >   board/boundary/nitrogen6x/nitrogen6x.c |  7 ++++++-
> >   include/configs/nitrogen6x.h           | 11 +++++++++++
> >   2 files changed, 17 insertions(+), 1 deletion(-)
> > 
> > diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
> > b/board/boundary/nitrogen6x/nitrogen6x.c index 1712908..46be51e 100644
> > --- a/board/boundary/nitrogen6x/nitrogen6x.c
> > +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> > @@ -369,7 +369,12 @@ int board_eth_init(bd_t *bis)
> > 
> >   		free(bus);
> >   	
> >   	}
> >   
> >   #endif
> > 
> > -	return 0;
> > +
> 
> I think this bit needs a different configuration option
> and should be disabled by default.

This activates all PCI/PCI-express ethernet cards, that's why CONFIG_PCI. I 
suppose testing CONFIG_CMD_NET would be a good idea here as well.

> > +#ifdef CONFIG_PCI
> > +	ret = pci_eth_init(bis);
> > +#endif
> > +
> 
> It seems to lock up the system if you don't have the proper
> device connected.

I am attaching you a patch, can you please try with the attached patch ? It 
should fix your enumeration issue.

btw. I noticed there's no PCIe reset connected on the sabrelite, that's a bit 
bad, we found out the PCIe reset should be connected, otherwise the PCIe will 
misbehave upon init sometimes.

> Without this bit, I was able to confirm proper enumeration
> of a PCIe bus with a USB 3.0 controller:
> 
>     00:01.0     - 16c3:abcd - Bridge device
>     01:00.0    - 1b21:0612 - Mass storage controller
> 
> Unfortunately, in a quick test, the image fails to boot
> without a PCIe device connected, or oddly, with a different
> PCIe ethernet controller connected.
> 
> I think it's handy to have the placeholder here, but
> I think you're the only person on the planet with the
> right set of components to make it work at the moment.

I'd usually be proud by hearing that, but ... I can't say I'm too happy about 
this ;-)

Best regards,
Marek Vasut
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[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Dear Stefano Babic,

> Hi Eric, Marek,
> 
> On 27/11/2013 17:19, Eric Nelson wrote:
> > It seems to lock up the system if you don't have the proper
> > device connected.
> > 
> > Without this bit, I was able to confirm proper enumeration
> > 
> > of a PCIe bus with a USB 3.0 controller:
> >    00:01.0     - 16c3:abcd - Bridge device
> >    01:00.0    - 1b21:0612 - Mass storage controller
> > 
> > Unfortunately, in a quick test, the image fails to boot
> > without a PCIe device connected, or oddly, with a different
> > PCIe ethernet controller connected.
> > 
> > I think it's handy to have the placeholder here, but
> > I think you're the only person on the planet with the
> > right set of components to make it work at the moment.
> 
> Waiting for someone from Mars is coming to help Marek, I'll put the
> patchset in the -next for better testing.

I got a hint from fourth dimension, let's see if the patch I produced in a 
higher level of consciousness helps ... let's hope I wasn't too high (pun 
intended, lol!)

Best regards,
Marek Vasut

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Eric Nelson]

Hi Marek,

On 11/29/2013 05:06 PM, Marek Vasut wrote:
> Dear Stefano Babic,
>
>> Hi Eric, Marek,
>>
>> On 27/11/2013 17:19, Eric Nelson wrote:
>>> It seems to lock up the system if you don't have the proper
>>> device connected.
>>>
>>> Without this bit, I was able to confirm proper enumeration
>>>
>>> of a PCIe bus with a USB 3.0 controller:
>>>     00:01.0     - 16c3:abcd - Bridge device
>>>     01:00.0    - 1b21:0612 - Mass storage controller
>>>
>>> Unfortunately, in a quick test, the image fails to boot
>>> without a PCIe device connected, or oddly, with a different
>>> PCIe ethernet controller connected.
>>>
>>> I think it's handy to have the placeholder here, but
>>> I think you're the only person on the planet with the
>>> right set of components to make it work at the moment.
>>
>> Waiting for someone from Mars is coming to help Marek, I'll put the
>> patchset in the -next for better testing.
>
> I got a hint from fourth dimension, let's see if the patch I produced in a
> higher level of consciousness helps ... let's hope I wasn't too high (pun
> intended, lol!)
>

Sorry for the delayed response. The holiday got in the way
of testing.

I think I already had this patch. I tested with these
patches against Stefano's master branch:

0001-ARM-mx6-Update-non-Freescale-boards-to-include-CPU-e.patch
0002-ARM-armv7-Make-indirect-vector-addresses-globl.patch
0003-ARM-lib-Add-cpu_clock_teardown-call.patch
0004-ARM-mx6-Add-PCI-express-clock-configuration.patch
0005-ARM-mx6-Add-PCI-express-driver.patch
0006-ARM-mx6-Enable-PCIe-on-Sabrelite.patch

I also apologize for some bad information the other day.

I saw (and reported) lock-ups during PCIE bus enumeration,
but I can't seem to reproduce them tonight.

I've tested against three different PCIe devices, and with
nothing connected, and everything boots.

As I mentioned, we don't have one of the ethernet
adapters you're using, but this patch set doesn't appear to
break anything.

I'll try on some other boards over the coming days and
let you know if I see any issues.

Regards,


Eric

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Stefano Babic]

Hi Eric,

On 03/12/2013 02:05, Eric Nelson wrote:

> 
> I think I already had this patch. I tested with these
> patches against Stefano's master branch:
> 
> 0001-ARM-mx6-Update-non-Freescale-boards-to-include-CPU-e.patch
> 0002-ARM-armv7-Make-indirect-vector-addresses-globl.patch
> 0003-ARM-lib-Add-cpu_clock_teardown-call.patch
> 0004-ARM-mx6-Add-PCI-express-clock-configuration.patch
> 0005-ARM-mx6-Add-PCI-express-driver.patch
> 0006-ARM-mx6-Enable-PCIe-on-Sabrelite.patch
> 
> I also apologize for some bad information the other day.
> 
> I saw (and reported) lock-ups during PCIE bus enumeration,
> but I can't seem to reproduce them tonight.
> 
> I've tested against three different PCIe devices, and with
> nothing connected, and everything boots.
> 
> As I mentioned, we don't have one of the ethernet
> adapters you're using, but this patch set doesn't appear to
> break anything.
> 
> I'll try on some other boards over the coming days and
> let you know if I see any issues.

Thanks for testing. I will let the patchset on -next until your
feedback. If boards can boot flawlessly, I will merge it into -master.

Best regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Hi Eric,

> Hi Marek,
> 
> On 11/29/2013 05:06 PM, Marek Vasut wrote:
> > Dear Stefano Babic,
> > 
> >> Hi Eric, Marek,
> >> 
> >> On 27/11/2013 17:19, Eric Nelson wrote:
> >>> It seems to lock up the system if you don't have the proper
> >>> device connected.
> >>> 
> >>> Without this bit, I was able to confirm proper enumeration
> >>> 
> >>> of a PCIe bus with a USB 3.0 controller:
> >>>     00:01.0     - 16c3:abcd - Bridge device
> >>>     01:00.0    - 1b21:0612 - Mass storage controller
> >>> 
> >>> Unfortunately, in a quick test, the image fails to boot
> >>> without a PCIe device connected, or oddly, with a different
> >>> PCIe ethernet controller connected.
> >>> 
> >>> I think it's handy to have the placeholder here, but
> >>> I think you're the only person on the planet with the
> >>> right set of components to make it work at the moment.
> >> 
> >> Waiting for someone from Mars is coming to help Marek, I'll put the
> >> patchset in the -next for better testing.
> > 
> > I got a hint from fourth dimension, let's see if the patch I produced in
> > a higher level of consciousness helps ... let's hope I wasn't too high
> > (pun intended, lol!)
> 
> Sorry for the delayed response. The holiday got in the way
> of testing.

No problem ;-)

> I think I already had this patch.

The one I attached is a new one. I suppose that one fixes your lockups and stuff 
:)

> I tested with these
> patches against Stefano's master branch:
> 
> 0001-ARM-mx6-Update-non-Freescale-boards-to-include-CPU-e.patch
> 0002-ARM-armv7-Make-indirect-vector-addresses-globl.patch
> 0003-ARM-lib-Add-cpu_clock_teardown-call.patch
> 0004-ARM-mx6-Add-PCI-express-clock-configuration.patch
> 0005-ARM-mx6-Add-PCI-express-driver.patch
> 0006-ARM-mx6-Enable-PCIe-on-Sabrelite.patch
> 
> I also apologize for some bad information the other day.
> 
> I saw (and reported) lock-ups during PCIE bus enumeration,
> but I can't seem to reproduce them tonight.
> 
> I've tested against three different PCIe devices, and with
> nothing connected, and everything boots.
> 
> As I mentioned, we don't have one of the ethernet
> adapters you're using, but this patch set doesn't appear to
> break anything.
> 
> I'll try on some other boards over the coming days and
> let you know if I see any issues.
> 
> Regards,
> 
> 
> Eric

Best regards,
Marek Vasut

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Dear Stefano Babic,

> Hi Eric,
> 
> On 03/12/2013 02:05, Eric Nelson wrote:
> > I think I already had this patch. I tested with these
> > patches against Stefano's master branch:
> > 
> > 0001-ARM-mx6-Update-non-Freescale-boards-to-include-CPU-e.patch
> > 0002-ARM-armv7-Make-indirect-vector-addresses-globl.patch
> > 0003-ARM-lib-Add-cpu_clock_teardown-call.patch
> > 0004-ARM-mx6-Add-PCI-express-clock-configuration.patch
> > 0005-ARM-mx6-Add-PCI-express-driver.patch
> > 0006-ARM-mx6-Enable-PCIe-on-Sabrelite.patch
> > 
> > I also apologize for some bad information the other day.
> > 
> > I saw (and reported) lock-ups during PCIE bus enumeration,
> > but I can't seem to reproduce them tonight.
> > 
> > I've tested against three different PCIe devices, and with
> > nothing connected, and everything boots.
> > 
> > As I mentioned, we don't have one of the ethernet
> > adapters you're using, but this patch set doesn't appear to
> > break anything.
> > 
> > I'll try on some other boards over the coming days and
> > let you know if I see any issues.
> 
> Thanks for testing. I will let the patchset on -next until your
> feedback. If boards can boot flawlessly, I will merge it into -master.

Will this still make it for 2014.01 please?

Best regards,
Marek Vasut

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Stefano Babic]

Hi Marek,

On 03/12/2013 10:12, Marek Vasut wrote:

>> Thanks for testing. I will let the patchset on -next until your
>> feedback. If boards can boot flawlessly, I will merge it into -master.
> 
> Will this still make it for 2014.01 please?

If boards can anyway boot, yes.

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 5/5] ARM: mx6: Enable PCIe on Sabrelite

[Marek Vasut]

Dear Stefano Babic,

> Hi Marek,
> 
> On 03/12/2013 10:12, Marek Vasut wrote:
> >> Thanks for testing. I will let the patchset on -next until your
> >> feedback. If boards can boot flawlessly, I will merge it into -master.
> > 
> > Will this still make it for 2014.01 please?
> 
> If boards can anyway boot, yes.

OK, thanks!

Best regards,
Marek Vasut