* [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
@ 2013-11-12 13:51 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:51 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
Greg Kroah-Hartman, Giuseppe Cavallaro, Grant Likely, devicetree,
linux-doc, stephen.gallimore, linux-kernel, kernel, linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
STi SOC series integrates dwmac IP from synopsis, however there is a hardware
glue on top of this standard IP, this glue needs to configured before the
actual dwmac can be used.
To add this a new driver dwmac-sti is introduced whose responsibility is to
configure dwmac glue and before dwmac driver, this is achieved by making dwmac
device node as child to ethernet glue node. Inspired by usb/dwc3.
Also the glue needs to come out of softreset which is why we have added a
softreset controller to driver which looked perfectly neat, rather then
driving the softreset bit from the glue driver.
Also as part of power management in glue driver, I found that there was no
function to determine if the child device is a wakeup source or not.
I have added a new api device_child_may_wakeup API which could be useful for
drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
this new API.
The reason for combining all these patches in a same series is because of
dependencies.
This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
SOC on ethernet 100/1000 Links.
Comments?
Thanks,
srini
Srinivas Kandagatla (6):
drivers: reset: stih415: add softreset controller
drivers: reset: stih416: add softreset controller
PM / wakeup : Introduce device_child_may_wakeup
net: stmmac:sti: Add STi SOC glue driver.
ARM: STi: Add STiH415 ethernet support.
ARM: STi: Add STiH416 ethernet support.
Stephen Gallimore (4):
drivers: reset: STi SoC system configuration reset controller support
drivers: reset: Reset controller driver for STiH415
drivers: reset: Reset controller driver for STiH416
ARM: STi: Add reset controller support to mach-sti Kconfig
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
arch/arm/boot/dts/stih415-clock.dtsi | 14 +
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
arch/arm/boot/dts/stih415.dtsi | 67 +++++
arch/arm/boot/dts/stih416-clock.dtsi | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
arch/arm/boot/dts/stih416.dtsi | 69 +++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
arch/arm/mach-sti/Kconfig | 3 +
drivers/base/power/wakeup.c | 23 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 15 +
drivers/reset/sti/Makefile | 4 +
drivers/reset/sti/reset-stih415.c | 99 +++++++
drivers/reset/sti/reset-stih416.c | 101 +++++++
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 +++++
.../dt-bindings/reset-controller/stih415-resets.h | 23 ++
.../dt-bindings/reset-controller/stih416-resets.h | 25 ++
include/linux/pm_wakeup.h | 1 +
26 files changed, 1402 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
--
1.7.6.5
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
@ 2013-11-12 13:51 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:51 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
Greg Kroah-Hartman, Giuseppe Cavallaro, Grant Likely, devicetree,
linux-doc, stephen.gallimore, linux-kernel, kernel, linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
STi SOC series integrates dwmac IP from synopsis, however there is a hardware
glue on top of this standard IP, this glue needs to configured before the
actual dwmac can be used.
To add this a new driver dwmac-sti is introduced whose responsibility is to
configure dwmac glue and before dwmac driver, this is achieved by making dwmac
device node as child to ethernet glue node. Inspired by usb/dwc3.
Also the glue needs to come out of softreset which is why we have added a
softreset controller to driver which looked perfectly neat, rather then
driving the softreset bit from the glue driver.
Also as part of power management in glue driver, I found that there was no
function to determine if the child device is a wakeup source or not.
I have added a new api device_child_may_wakeup API which could be useful for
drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
this new API.
The reason for combining all these patches in a same series is because of
dependencies.
This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
SOC on ethernet 100/1000 Links.
Comments?
Thanks,
srini
Srinivas Kandagatla (6):
drivers: reset: stih415: add softreset controller
drivers: reset: stih416: add softreset controller
PM / wakeup : Introduce device_child_may_wakeup
net: stmmac:sti: Add STi SOC glue driver.
ARM: STi: Add STiH415 ethernet support.
ARM: STi: Add STiH416 ethernet support.
Stephen Gallimore (4):
drivers: reset: STi SoC system configuration reset controller support
drivers: reset: Reset controller driver for STiH415
drivers: reset: Reset controller driver for STiH416
ARM: STi: Add reset controller support to mach-sti Kconfig
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
arch/arm/boot/dts/stih415-clock.dtsi | 14 +
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
arch/arm/boot/dts/stih415.dtsi | 67 +++++
arch/arm/boot/dts/stih416-clock.dtsi | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
arch/arm/boot/dts/stih416.dtsi | 69 +++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
arch/arm/mach-sti/Kconfig | 3 +
drivers/base/power/wakeup.c | 23 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 15 +
drivers/reset/sti/Makefile | 4 +
drivers/reset/sti/reset-stih415.c | 99 +++++++
drivers/reset/sti/reset-stih416.c | 101 +++++++
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 +++++
.../dt-bindings/reset-controller/stih415-resets.h | 23 ++
.../dt-bindings/reset-controller/stih416-resets.h | 25 ++
include/linux/pm_wakeup.h | 1 +
26 files changed, 1402 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
--
1.7.6.5
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
@ 2013-11-12 13:51 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:51 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
STi SOC series integrates dwmac IP from synopsis, however there is a hardware
glue on top of this standard IP, this glue needs to configured before the
actual dwmac can be used.
To add this a new driver dwmac-sti is introduced whose responsibility is to
configure dwmac glue and before dwmac driver, this is achieved by making dwmac
device node as child to ethernet glue node. Inspired by usb/dwc3.
Also the glue needs to come out of softreset which is why we have added a
softreset controller to driver which looked perfectly neat, rather then
driving the softreset bit from the glue driver.
Also as part of power management in glue driver, I found that there was no
function to determine if the child device is a wakeup source or not.
I have added a new api device_child_may_wakeup API which could be useful for
drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
this new API.
The reason for combining all these patches in a same series is because of
dependencies.
This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
SOC on ethernet 100/1000 Links.
Comments?
Thanks,
srini
Srinivas Kandagatla (6):
drivers: reset: stih415: add softreset controller
drivers: reset: stih416: add softreset controller
PM / wakeup : Introduce device_child_may_wakeup
net: stmmac:sti: Add STi SOC glue driver.
ARM: STi: Add STiH415 ethernet support.
ARM: STi: Add STiH416 ethernet support.
Stephen Gallimore (4):
drivers: reset: STi SoC system configuration reset controller support
drivers: reset: Reset controller driver for STiH415
drivers: reset: Reset controller driver for STiH416
ARM: STi: Add reset controller support to mach-sti Kconfig
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
arch/arm/boot/dts/stih415-clock.dtsi | 14 +
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
arch/arm/boot/dts/stih415.dtsi | 67 +++++
arch/arm/boot/dts/stih416-clock.dtsi | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
arch/arm/boot/dts/stih416.dtsi | 69 +++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
arch/arm/mach-sti/Kconfig | 3 +
drivers/base/power/wakeup.c | 23 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 15 +
drivers/reset/sti/Makefile | 4 +
drivers/reset/sti/reset-stih415.c | 99 +++++++
drivers/reset/sti/reset-stih416.c | 101 +++++++
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 +++++
.../dt-bindings/reset-controller/stih415-resets.h | 23 ++
.../dt-bindings/reset-controller/stih416-resets.h | 25 ++
include/linux/pm_wakeup.h | 1 +
26 files changed, 1402 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
--
1.7.6.5
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 01/10] drivers: reset: STi SoC system configuration reset controller support
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.
The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 7 ++
drivers/reset/sti/Makefile | 1 +
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++++++++++++++++++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 ++++++++++++++
6 files changed, 268 insertions(+), 0 deletions(-)
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..0615f50 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,5 @@ menuconfig RESET_CONTROLLER
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
+
+source "drivers/reset/sti/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f..2b2a57c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
+
+# SoC specific
+obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
new file mode 100644
index 0000000..ba13796
--- /dev/null
+++ b/drivers/reset/sti/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_STI
+
+config STI_RESET_SYSCFG
+ bool
+ select RESET_CONTROLLER
+
+endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
new file mode 100644
index 0000000..c4a51d9
--- /dev/null
+++ b/drivers/reset/sti/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
new file mode 100644
index 0000000..a145cc0
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * Inspired by mach-imx/src.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset-syscfg.h"
+
+/**
+ * Reset channel regmap configuration
+ *
+ * @reset: regmap field for the channel's reset bit.
+ * @ack: regmap field for the channel's ack bit (optional).
+ */
+struct syscfg_reset_channel {
+ struct regmap_field *reset;
+ struct regmap_field *ack;
+};
+
+/**
+ * A reset controller which groups together a set of related reset bits, which
+ * may be located in different system configuration registers.
+ *
+ * @rst: base reset controller structure.
+ * @active_low: are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @channels: An array of reset channels for this controller.
+ */
+struct syscfg_reset_controller {
+ struct reset_controller_dev rst;
+ bool active_low;
+ struct syscfg_reset_channel *channels;
+};
+
+#define to_syscfg_reset_controller(_rst) \
+ container_of(_rst, struct syscfg_reset_controller, rst)
+
+static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, int assert)
+{
+ struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
+ const struct syscfg_reset_channel *ch;
+ u32 ctrl_val = rst->active_low ? !assert : !!assert;
+ int err;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ ch = &rst->channels[idx];
+
+ err = regmap_field_write(ch->reset, ctrl_val);
+ if (err)
+ return err;
+
+ if (ch->ack) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+ u32 ack_val;
+
+ while (true) {
+ err = regmap_field_read(ch->ack, &ack_val);
+ if (err)
+ return err;
+
+ if (ack_val == ctrl_val)
+ break;
+
+ if (time_after(jiffies, timeout))
+ return -ETIME;
+
+ cpu_relax();
+ }
+ }
+
+ return 0;
+}
+
+static int syscfg_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, true);
+}
+
+static int syscfg_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, false);
+}
+
+static int syscfg_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err = syscfg_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return syscfg_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops syscfg_reset_ops = {
+ .reset = syscfg_reset_dev,
+ .assert = syscfg_reset_assert,
+ .deassert = syscfg_reset_deassert,
+};
+
+static int syscfg_reset_controller_register(struct device *dev,
+ const struct syscfg_reset_controller_data *data)
+{
+ struct syscfg_reset_controller *rc;
+ size_t size;
+ int i, err;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ size = sizeof(struct syscfg_reset_channel) * data->nr_channels;
+
+ rc->channels = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!rc->channels)
+ return -ENOMEM;
+
+ rc->rst.ops = &syscfg_reset_ops,
+ rc->rst.of_node = dev->of_node;
+ rc->rst.nr_resets = data->nr_channels;
+ rc->active_low = data->active_low;
+
+ for (i = 0; i < data->nr_channels; i++) {
+ struct regmap *map;
+ struct regmap_field *f;
+ const char *compatible = data->channels[i].compatible;
+
+ map = syscon_regmap_lookup_by_compatible(compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].reset = f;
+
+ if (!data->wait_for_ack)
+ continue;
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].ack = f;
+ }
+
+ err = reset_controller_register(&rc->rst);
+ if (!err)
+ dev_info(dev, "registered\n");
+
+ return err;
+}
+
+int syscfg_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev ? &pdev->dev : NULL;
+ const struct of_device_id *match;
+
+ if (!dev || !dev->driver)
+ return -ENODEV;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ return syscfg_reset_controller_register(dev, match->data);
+}
diff --git a/drivers/reset/sti/reset-syscfg.h b/drivers/reset/sti/reset-syscfg.h
new file mode 100644
index 0000000..2cc2283
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __STI_RESET_SYSCFG_H
+#define __STI_RESET_SYSCFG_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon regmap containing this
+ * channel's control and ack (status) bits.
+ * @reset: Regmap field description of the channel's reset bit.
+ * @ack: Regmap field description of the channel's acknowledge bit.
+ */
+struct syscfg_reset_channel_data {
+ const char *compatible;
+ struct reg_field reset;
+ struct reg_field ack;
+};
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), \
+ .ack = REG_FIELD(_ar, _ab, _ab), }
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), }
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ * be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+ bool wait_for_ack;
+ bool active_low;
+ int nr_channels;
+ const struct syscfg_reset_channel_data *channels;
+};
+
+/**
+ * syscfg_reset_probe(): platform device probe function used by syscfg
+ * reset controller drivers. This registers a reset
+ * controller configured by the OF match data for
+ * the compatible device which should be of type
+ * "struct syscfg_reset_controller_data".
+ *
+ * @pdev: platform device
+ */
+int syscfg_reset_probe(struct platform_device *pdev);
+
+#endif /* __STI_RESET_SYSCFG_H */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 01/10] drivers: reset: STi SoC system configuration reset controller support
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.
The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 7 ++
drivers/reset/sti/Makefile | 1 +
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++++++++++++++++++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 ++++++++++++++
6 files changed, 268 insertions(+), 0 deletions(-)
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..0615f50 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,5 @@ menuconfig RESET_CONTROLLER
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
+
+source "drivers/reset/sti/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f..2b2a57c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
+
+# SoC specific
+obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
new file mode 100644
index 0000000..ba13796
--- /dev/null
+++ b/drivers/reset/sti/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_STI
+
+config STI_RESET_SYSCFG
+ bool
+ select RESET_CONTROLLER
+
+endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
new file mode 100644
index 0000000..c4a51d9
--- /dev/null
+++ b/drivers/reset/sti/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
new file mode 100644
index 0000000..a145cc0
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * Inspired by mach-imx/src.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset-syscfg.h"
+
+/**
+ * Reset channel regmap configuration
+ *
+ * @reset: regmap field for the channel's reset bit.
+ * @ack: regmap field for the channel's ack bit (optional).
+ */
+struct syscfg_reset_channel {
+ struct regmap_field *reset;
+ struct regmap_field *ack;
+};
+
+/**
+ * A reset controller which groups together a set of related reset bits, which
+ * may be located in different system configuration registers.
+ *
+ * @rst: base reset controller structure.
+ * @active_low: are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @channels: An array of reset channels for this controller.
+ */
+struct syscfg_reset_controller {
+ struct reset_controller_dev rst;
+ bool active_low;
+ struct syscfg_reset_channel *channels;
+};
+
+#define to_syscfg_reset_controller(_rst) \
+ container_of(_rst, struct syscfg_reset_controller, rst)
+
+static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, int assert)
+{
+ struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
+ const struct syscfg_reset_channel *ch;
+ u32 ctrl_val = rst->active_low ? !assert : !!assert;
+ int err;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ ch = &rst->channels[idx];
+
+ err = regmap_field_write(ch->reset, ctrl_val);
+ if (err)
+ return err;
+
+ if (ch->ack) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+ u32 ack_val;
+
+ while (true) {
+ err = regmap_field_read(ch->ack, &ack_val);
+ if (err)
+ return err;
+
+ if (ack_val == ctrl_val)
+ break;
+
+ if (time_after(jiffies, timeout))
+ return -ETIME;
+
+ cpu_relax();
+ }
+ }
+
+ return 0;
+}
+
+static int syscfg_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, true);
+}
+
+static int syscfg_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, false);
+}
+
+static int syscfg_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err = syscfg_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return syscfg_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops syscfg_reset_ops = {
+ .reset = syscfg_reset_dev,
+ .assert = syscfg_reset_assert,
+ .deassert = syscfg_reset_deassert,
+};
+
+static int syscfg_reset_controller_register(struct device *dev,
+ const struct syscfg_reset_controller_data *data)
+{
+ struct syscfg_reset_controller *rc;
+ size_t size;
+ int i, err;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ size = sizeof(struct syscfg_reset_channel) * data->nr_channels;
+
+ rc->channels = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!rc->channels)
+ return -ENOMEM;
+
+ rc->rst.ops = &syscfg_reset_ops,
+ rc->rst.of_node = dev->of_node;
+ rc->rst.nr_resets = data->nr_channels;
+ rc->active_low = data->active_low;
+
+ for (i = 0; i < data->nr_channels; i++) {
+ struct regmap *map;
+ struct regmap_field *f;
+ const char *compatible = data->channels[i].compatible;
+
+ map = syscon_regmap_lookup_by_compatible(compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].reset = f;
+
+ if (!data->wait_for_ack)
+ continue;
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].ack = f;
+ }
+
+ err = reset_controller_register(&rc->rst);
+ if (!err)
+ dev_info(dev, "registered\n");
+
+ return err;
+}
+
+int syscfg_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev ? &pdev->dev : NULL;
+ const struct of_device_id *match;
+
+ if (!dev || !dev->driver)
+ return -ENODEV;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ return syscfg_reset_controller_register(dev, match->data);
+}
diff --git a/drivers/reset/sti/reset-syscfg.h b/drivers/reset/sti/reset-syscfg.h
new file mode 100644
index 0000000..2cc2283
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __STI_RESET_SYSCFG_H
+#define __STI_RESET_SYSCFG_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon regmap containing this
+ * channel's control and ack (status) bits.
+ * @reset: Regmap field description of the channel's reset bit.
+ * @ack: Regmap field description of the channel's acknowledge bit.
+ */
+struct syscfg_reset_channel_data {
+ const char *compatible;
+ struct reg_field reset;
+ struct reg_field ack;
+};
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), \
+ .ack = REG_FIELD(_ar, _ab, _ab), }
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), }
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ * be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+ bool wait_for_ack;
+ bool active_low;
+ int nr_channels;
+ const struct syscfg_reset_channel_data *channels;
+};
+
+/**
+ * syscfg_reset_probe(): platform device probe function used by syscfg
+ * reset controller drivers. This registers a reset
+ * controller configured by the OF match data for
+ * the compatible device which should be of type
+ * "struct syscfg_reset_controller_data".
+ *
+ * @pdev: platform device
+ */
+int syscfg_reset_probe(struct platform_device *pdev);
+
+#endif /* __STI_RESET_SYSCFG_H */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 01/10] drivers: reset: STi SoC system configuration reset controller support
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.
The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 3 +
drivers/reset/sti/Kconfig | 7 ++
drivers/reset/sti/Makefile | 1 +
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++++++++++++++++++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 ++++++++++++++
6 files changed, 268 insertions(+), 0 deletions(-)
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..0615f50 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,5 @@ menuconfig RESET_CONTROLLER
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
+
+source "drivers/reset/sti/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f..2b2a57c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
+
+# SoC specific
+obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
new file mode 100644
index 0000000..ba13796
--- /dev/null
+++ b/drivers/reset/sti/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_STI
+
+config STI_RESET_SYSCFG
+ bool
+ select RESET_CONTROLLER
+
+endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
new file mode 100644
index 0000000..c4a51d9
--- /dev/null
+++ b/drivers/reset/sti/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
new file mode 100644
index 0000000..a145cc0
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * Inspired by mach-imx/src.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset-syscfg.h"
+
+/**
+ * Reset channel regmap configuration
+ *
+ * @reset: regmap field for the channel's reset bit.
+ * @ack: regmap field for the channel's ack bit (optional).
+ */
+struct syscfg_reset_channel {
+ struct regmap_field *reset;
+ struct regmap_field *ack;
+};
+
+/**
+ * A reset controller which groups together a set of related reset bits, which
+ * may be located in different system configuration registers.
+ *
+ * @rst: base reset controller structure.
+ * @active_low: are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @channels: An array of reset channels for this controller.
+ */
+struct syscfg_reset_controller {
+ struct reset_controller_dev rst;
+ bool active_low;
+ struct syscfg_reset_channel *channels;
+};
+
+#define to_syscfg_reset_controller(_rst) \
+ container_of(_rst, struct syscfg_reset_controller, rst)
+
+static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, int assert)
+{
+ struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
+ const struct syscfg_reset_channel *ch;
+ u32 ctrl_val = rst->active_low ? !assert : !!assert;
+ int err;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ ch = &rst->channels[idx];
+
+ err = regmap_field_write(ch->reset, ctrl_val);
+ if (err)
+ return err;
+
+ if (ch->ack) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+ u32 ack_val;
+
+ while (true) {
+ err = regmap_field_read(ch->ack, &ack_val);
+ if (err)
+ return err;
+
+ if (ack_val == ctrl_val)
+ break;
+
+ if (time_after(jiffies, timeout))
+ return -ETIME;
+
+ cpu_relax();
+ }
+ }
+
+ return 0;
+}
+
+static int syscfg_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, true);
+}
+
+static int syscfg_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, false);
+}
+
+static int syscfg_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err = syscfg_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return syscfg_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops syscfg_reset_ops = {
+ .reset = syscfg_reset_dev,
+ .assert = syscfg_reset_assert,
+ .deassert = syscfg_reset_deassert,
+};
+
+static int syscfg_reset_controller_register(struct device *dev,
+ const struct syscfg_reset_controller_data *data)
+{
+ struct syscfg_reset_controller *rc;
+ size_t size;
+ int i, err;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ size = sizeof(struct syscfg_reset_channel) * data->nr_channels;
+
+ rc->channels = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!rc->channels)
+ return -ENOMEM;
+
+ rc->rst.ops = &syscfg_reset_ops,
+ rc->rst.of_node = dev->of_node;
+ rc->rst.nr_resets = data->nr_channels;
+ rc->active_low = data->active_low;
+
+ for (i = 0; i < data->nr_channels; i++) {
+ struct regmap *map;
+ struct regmap_field *f;
+ const char *compatible = data->channels[i].compatible;
+
+ map = syscon_regmap_lookup_by_compatible(compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].reset = f;
+
+ if (!data->wait_for_ack)
+ continue;
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].ack = f;
+ }
+
+ err = reset_controller_register(&rc->rst);
+ if (!err)
+ dev_info(dev, "registered\n");
+
+ return err;
+}
+
+int syscfg_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev ? &pdev->dev : NULL;
+ const struct of_device_id *match;
+
+ if (!dev || !dev->driver)
+ return -ENODEV;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ return syscfg_reset_controller_register(dev, match->data);
+}
diff --git a/drivers/reset/sti/reset-syscfg.h b/drivers/reset/sti/reset-syscfg.h
new file mode 100644
index 0000000..2cc2283
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __STI_RESET_SYSCFG_H
+#define __STI_RESET_SYSCFG_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon regmap containing this
+ * channel's control and ack (status) bits.
+ * @reset: Regmap field description of the channel's reset bit.
+ * @ack: Regmap field description of the channel's acknowledge bit.
+ */
+struct syscfg_reset_channel_data {
+ const char *compatible;
+ struct reg_field reset;
+ struct reg_field ack;
+};
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), \
+ .ack = REG_FIELD(_ar, _ab, _ab), }
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), }
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ * be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+ bool wait_for_ack;
+ bool active_low;
+ int nr_channels;
+ const struct syscfg_reset_channel_data *channels;
+};
+
+/**
+ * syscfg_reset_probe(): platform device probe function used by syscfg
+ * reset controller drivers. This registers a reset
+ * controller configured by the OF match data for
+ * the compatible device which should be of type
+ * "struct syscfg_reset_controller_data".
+ *
+ * @pdev: platform device
+ */
+int syscfg_reset_probe(struct platform_device *pdev);
+
+#endif /* __STI_RESET_SYSCFG_H */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 02/10] drivers: reset: Reset controller driver for STiH415
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH415
SoC. This initial version provides a compatible driver for the
"st,stih415-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 ++++++++++++
arch/arm/boot/dts/stih415.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 3 +
drivers/reset/sti/reset-stih415.c | 77 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 19 +++++
6 files changed, 155 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 0000000..23a808c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"powerdown" control bits found in the STi family SoC system configuration
+registers. These have been grouped together into a single reset controller
+device for convenience.
+
+The actual action taken when powerdown is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-powerdown"
+- #reset-cells: 1, see below
+
+example:
+
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
+
+Specifying powerdown control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the powerdown device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ usb1: usb@fe200000 {
+ resets = <&powerdown STIH41X_USB1_POWERDOWN>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8de..09379a6b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih415-resets.h>
/ {
L2: cache-controller {
@@ -27,6 +28,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
syscfg_sbc: sbc-syscfg@fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ba13796..ef6654a 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -4,4 +4,8 @@ config STI_RESET_SYSCFG
bool
select RESET_CONTROLLER
+config STIH415_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index c4a51d9..fce4433 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
+
+# SoC specific reset devices
+obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
new file mode 100644
index 0000000..56c2146
--- /dev/null
+++ b/drivers/reset/sti/reset-stih415.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih415-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH415 Peripheral powerdown definitions.
+ */
+static const char stih415_front[] = "st,stih415-front-syscfg";
+static const char stih415_rear[] = "st,stih415-rear-syscfg";
+static const char stih415_sbc[] = "st,stih415-sbc-syscfg";
+static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
+
+#define STIH415_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih415_front, SYSCFG_114, _bit, SYSSTAT_187, _bit)
+
+#define STIH415_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
+
+#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
+ [STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
+ [STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
+ [STIH415_KEYSCAN_POWERDOWN] = STIH415_PDN_FRONT(2),
+ [STIH415_USB0_POWERDOWN] = STIH415_PDN_REAR(0, 0),
+ [STIH415_USB1_POWERDOWN] = STIH415_PDN_REAR(1, 1),
+ [STIH415_USB2_POWERDOWN] = STIH415_PDN_REAR(2, 2),
+ [STIH415_SATA0_POWERDOWN] = STIH415_PDN_REAR(3, 3),
+ [STIH415_SATA1_POWERDOWN] = STIH415_PDN_REAR(4, 4),
+ [STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih415_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih415_powerdowns),
+ .channels = stih415_powerdowns,
+};
+
+static struct of_device_id stih415_reset_match[] = {
+ { .compatible = "st,stih415-powerdown",
+ .data = &stih415_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih415_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih415",
+ .owner = THIS_MODULE,
+ .of_match_table = stih415_reset_match,
+ },
+};
+
+static int __init stih415_reset_init(void)
+{
+ return platform_driver_register(&stih415_reset_driver);
+}
+arch_initcall(stih415_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
new file mode 100644
index 0000000..2d54e68
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
+
+#define STIH415_EMISS_POWERDOWN 0
+#define STIH415_NAND_POWERDOWN 1
+#define STIH415_KEYSCAN_POWERDOWN 2
+#define STIH415_USB0_POWERDOWN 3
+#define STIH415_USB1_POWERDOWN 4
+#define STIH415_USB2_POWERDOWN 5
+#define STIH415_SATA0_POWERDOWN 6
+#define STIH415_SATA1_POWERDOWN 7
+#define STIH415_PCIE_POWERDOWN 8
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 02/10] drivers: reset: Reset controller driver for STiH415
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH415
SoC. This initial version provides a compatible driver for the
"st,stih415-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 ++++++++++++
arch/arm/boot/dts/stih415.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 3 +
drivers/reset/sti/reset-stih415.c | 77 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 19 +++++
6 files changed, 155 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 0000000..23a808c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"powerdown" control bits found in the STi family SoC system configuration
+registers. These have been grouped together into a single reset controller
+device for convenience.
+
+The actual action taken when powerdown is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-powerdown"
+- #reset-cells: 1, see below
+
+example:
+
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
+
+Specifying powerdown control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the powerdown device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ usb1: usb@fe200000 {
+ resets = <&powerdown STIH41X_USB1_POWERDOWN>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8de..09379a6b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih415-resets.h>
/ {
L2: cache-controller {
@@ -27,6 +28,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
syscfg_sbc: sbc-syscfg@fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ba13796..ef6654a 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -4,4 +4,8 @@ config STI_RESET_SYSCFG
bool
select RESET_CONTROLLER
+config STIH415_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index c4a51d9..fce4433 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
+
+# SoC specific reset devices
+obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
new file mode 100644
index 0000000..56c2146
--- /dev/null
+++ b/drivers/reset/sti/reset-stih415.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih415-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH415 Peripheral powerdown definitions.
+ */
+static const char stih415_front[] = "st,stih415-front-syscfg";
+static const char stih415_rear[] = "st,stih415-rear-syscfg";
+static const char stih415_sbc[] = "st,stih415-sbc-syscfg";
+static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
+
+#define STIH415_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih415_front, SYSCFG_114, _bit, SYSSTAT_187, _bit)
+
+#define STIH415_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
+
+#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
+ [STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
+ [STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
+ [STIH415_KEYSCAN_POWERDOWN] = STIH415_PDN_FRONT(2),
+ [STIH415_USB0_POWERDOWN] = STIH415_PDN_REAR(0, 0),
+ [STIH415_USB1_POWERDOWN] = STIH415_PDN_REAR(1, 1),
+ [STIH415_USB2_POWERDOWN] = STIH415_PDN_REAR(2, 2),
+ [STIH415_SATA0_POWERDOWN] = STIH415_PDN_REAR(3, 3),
+ [STIH415_SATA1_POWERDOWN] = STIH415_PDN_REAR(4, 4),
+ [STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih415_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih415_powerdowns),
+ .channels = stih415_powerdowns,
+};
+
+static struct of_device_id stih415_reset_match[] = {
+ { .compatible = "st,stih415-powerdown",
+ .data = &stih415_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih415_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih415",
+ .owner = THIS_MODULE,
+ .of_match_table = stih415_reset_match,
+ },
+};
+
+static int __init stih415_reset_init(void)
+{
+ return platform_driver_register(&stih415_reset_driver);
+}
+arch_initcall(stih415_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
new file mode 100644
index 0000000..2d54e68
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
+
+#define STIH415_EMISS_POWERDOWN 0
+#define STIH415_NAND_POWERDOWN 1
+#define STIH415_KEYSCAN_POWERDOWN 2
+#define STIH415_USB0_POWERDOWN 3
+#define STIH415_USB1_POWERDOWN 4
+#define STIH415_USB2_POWERDOWN 5
+#define STIH415_SATA0_POWERDOWN 6
+#define STIH415_SATA1_POWERDOWN 7
+#define STIH415_PCIE_POWERDOWN 8
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 02/10] drivers: reset: Reset controller driver for STiH415
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH415
SoC. This initial version provides a compatible driver for the
"st,stih415-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
.../devicetree/bindings/reset/st,sti-powerdown.txt | 46 ++++++++++++
arch/arm/boot/dts/stih415.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 3 +
drivers/reset/sti/reset-stih415.c | 77 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 19 +++++
6 files changed, 155 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 0000000..23a808c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"powerdown" control bits found in the STi family SoC system configuration
+registers. These have been grouped together into a single reset controller
+device for convenience.
+
+The actual action taken when powerdown is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-powerdown"
+- #reset-cells: 1, see below
+
+example:
+
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
+
+Specifying powerdown control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the powerdown device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ usb1: usb at fe200000 {
+ resets = <&powerdown STIH41X_USB1_POWERDOWN>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8de..09379a6b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih415-resets.h>
/ {
L2: cache-controller {
@@ -27,6 +28,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
syscfg_sbc: sbc-syscfg at fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ba13796..ef6654a 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -4,4 +4,8 @@ config STI_RESET_SYSCFG
bool
select RESET_CONTROLLER
+config STIH415_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index c4a51d9..fce4433 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
+
+# SoC specific reset devices
+obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
new file mode 100644
index 0000000..56c2146
--- /dev/null
+++ b/drivers/reset/sti/reset-stih415.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih415-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH415 Peripheral powerdown definitions.
+ */
+static const char stih415_front[] = "st,stih415-front-syscfg";
+static const char stih415_rear[] = "st,stih415-rear-syscfg";
+static const char stih415_sbc[] = "st,stih415-sbc-syscfg";
+static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
+
+#define STIH415_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih415_front, SYSCFG_114, _bit, SYSSTAT_187, _bit)
+
+#define STIH415_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
+
+#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
+ [STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
+ [STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
+ [STIH415_KEYSCAN_POWERDOWN] = STIH415_PDN_FRONT(2),
+ [STIH415_USB0_POWERDOWN] = STIH415_PDN_REAR(0, 0),
+ [STIH415_USB1_POWERDOWN] = STIH415_PDN_REAR(1, 1),
+ [STIH415_USB2_POWERDOWN] = STIH415_PDN_REAR(2, 2),
+ [STIH415_SATA0_POWERDOWN] = STIH415_PDN_REAR(3, 3),
+ [STIH415_SATA1_POWERDOWN] = STIH415_PDN_REAR(4, 4),
+ [STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih415_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih415_powerdowns),
+ .channels = stih415_powerdowns,
+};
+
+static struct of_device_id stih415_reset_match[] = {
+ { .compatible = "st,stih415-powerdown",
+ .data = &stih415_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih415_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih415",
+ .owner = THIS_MODULE,
+ .of_match_table = stih415_reset_match,
+ },
+};
+
+static int __init stih415_reset_init(void)
+{
+ return platform_driver_register(&stih415_reset_driver);
+}
+arch_initcall(stih415_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
new file mode 100644
index 0000000..2d54e68
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
+
+#define STIH415_EMISS_POWERDOWN 0
+#define STIH415_NAND_POWERDOWN 1
+#define STIH415_KEYSCAN_POWERDOWN 2
+#define STIH415_USB0_POWERDOWN 3
+#define STIH415_USB1_POWERDOWN 4
+#define STIH415_USB2_POWERDOWN 5
+#define STIH415_SATA0_POWERDOWN 6
+#define STIH415_SATA1_POWERDOWN 7
+#define STIH415_PCIE_POWERDOWN 8
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 03/10] drivers: reset: Reset controller driver for STiH416
2013-11-12 13:51 ` srinivas.kandagatla
(?)
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH416
SoC. This initial version provides a compatible driver for the
"st,stih416-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 2 +-
drivers/reset/sti/reset-stih416.c | 79 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 21 +++++
5 files changed, 111 insertions(+), 1 deletions(-)
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326e..b8cabbb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -26,6 +27,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-powerdown";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ef6654a..88d2d03 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -8,4 +8,8 @@ config STIH415_RESET
bool
select STI_RESET_SYSCFG
+config STIH416_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index fce4433..be1c976 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-# SoC specific reset devices
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
+obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
new file mode 100644
index 0000000..0becfc5
--- /dev/null
+++ b/drivers/reset/sti/reset-stih416.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih416-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH416 Peripheral powerdown definitions.
+ */
+static const char stih416_front[] = "st,stih416-front-syscfg";
+static const char stih416_rear[] = "st,stih416-rear-syscfg";
+static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
+static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+
+#define STIH416_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
+
+#define STIH416_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
+
+#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
+ [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
+ [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
+ [STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
+ [STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
+ [STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
+ [STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
+ [STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
+ [STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
+ [STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
+ [STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
+ [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih416_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih416_powerdowns),
+ .channels = stih416_powerdowns,
+};
+
+static struct of_device_id stih416_reset_match[] = {
+ { .compatible = "st,stih416-powerdown",
+ .data = &stih416_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih416_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih416",
+ .owner = THIS_MODULE,
+ .of_match_table = stih416_reset_match,
+ },
+};
+
+static int __init stih416_reset_init(void)
+{
+ return platform_driver_register(&stih416_reset_driver);
+}
+arch_initcall(stih416_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 0000000..d7da55f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,21 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
+
+#define STIH416_EMISS_POWERDOWN 0
+#define STIH416_NAND_POWERDOWN 1
+#define STIH416_KEYSCAN_POWERDOWN 2
+#define STIH416_USB0_POWERDOWN 3
+#define STIH416_USB1_POWERDOWN 4
+#define STIH416_USB2_POWERDOWN 5
+#define STIH416_USB3_POWERDOWN 6
+#define STIH416_SATA0_POWERDOWN 7
+#define STIH416_SATA1_POWERDOWN 8
+#define STIH416_PCIE0_POWERDOWN 9
+#define STIH416_PCIE1_POWERDOWN 10
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 03/10] drivers: reset: Reset controller driver for STiH416
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH416
SoC. This initial version provides a compatible driver for the
"st,stih416-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 2 +-
drivers/reset/sti/reset-stih416.c | 79 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 21 +++++
5 files changed, 111 insertions(+), 1 deletions(-)
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326e..b8cabbb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -26,6 +27,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-powerdown";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ef6654a..88d2d03 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -8,4 +8,8 @@ config STIH415_RESET
bool
select STI_RESET_SYSCFG
+config STIH416_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index fce4433..be1c976 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-# SoC specific reset devices
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
+obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
new file mode 100644
index 0000000..0becfc5
--- /dev/null
+++ b/drivers/reset/sti/reset-stih416.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih416-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH416 Peripheral powerdown definitions.
+ */
+static const char stih416_front[] = "st,stih416-front-syscfg";
+static const char stih416_rear[] = "st,stih416-rear-syscfg";
+static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
+static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+
+#define STIH416_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
+
+#define STIH416_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
+
+#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
+ [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
+ [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
+ [STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
+ [STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
+ [STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
+ [STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
+ [STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
+ [STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
+ [STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
+ [STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
+ [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih416_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih416_powerdowns),
+ .channels = stih416_powerdowns,
+};
+
+static struct of_device_id stih416_reset_match[] = {
+ { .compatible = "st,stih416-powerdown",
+ .data = &stih416_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih416_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih416",
+ .owner = THIS_MODULE,
+ .of_match_table = stih416_reset_match,
+ },
+};
+
+static int __init stih416_reset_init(void)
+{
+ return platform_driver_register(&stih416_reset_driver);
+}
+arch_initcall(stih416_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 0000000..d7da55f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,21 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
+
+#define STIH416_EMISS_POWERDOWN 0
+#define STIH416_NAND_POWERDOWN 1
+#define STIH416_KEYSCAN_POWERDOWN 2
+#define STIH416_USB0_POWERDOWN 3
+#define STIH416_USB1_POWERDOWN 4
+#define STIH416_USB2_POWERDOWN 5
+#define STIH416_USB3_POWERDOWN 6
+#define STIH416_SATA0_POWERDOWN 7
+#define STIH416_SATA1_POWERDOWN 8
+#define STIH416_PCIE0_POWERDOWN 9
+#define STIH416_PCIE1_POWERDOWN 10
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 03/10] drivers: reset: Reset controller driver for STiH416
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH416
SoC. This initial version provides a compatible driver for the
"st,stih416-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 2 +-
drivers/reset/sti/reset-stih416.c | 79 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 21 +++++
5 files changed, 111 insertions(+), 1 deletions(-)
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326e..b8cabbb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -26,6 +27,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-powerdown";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ef6654a..88d2d03 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -8,4 +8,8 @@ config STIH415_RESET
bool
select STI_RESET_SYSCFG
+config STIH416_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index fce4433..be1c976 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-# SoC specific reset devices
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
+obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
new file mode 100644
index 0000000..0becfc5
--- /dev/null
+++ b/drivers/reset/sti/reset-stih416.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih416-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH416 Peripheral powerdown definitions.
+ */
+static const char stih416_front[] = "st,stih416-front-syscfg";
+static const char stih416_rear[] = "st,stih416-rear-syscfg";
+static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
+static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+
+#define STIH416_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
+
+#define STIH416_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
+
+#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
+ [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
+ [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
+ [STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
+ [STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
+ [STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
+ [STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
+ [STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
+ [STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
+ [STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
+ [STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
+ [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih416_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih416_powerdowns),
+ .channels = stih416_powerdowns,
+};
+
+static struct of_device_id stih416_reset_match[] = {
+ { .compatible = "st,stih416-powerdown",
+ .data = &stih416_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih416_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih416",
+ .owner = THIS_MODULE,
+ .of_match_table = stih416_reset_match,
+ },
+};
+
+static int __init stih416_reset_init(void)
+{
+ return platform_driver_register(&stih416_reset_driver);
+}
+arch_initcall(stih416_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 0000000..d7da55f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,21 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
+
+#define STIH416_EMISS_POWERDOWN 0
+#define STIH416_NAND_POWERDOWN 1
+#define STIH416_KEYSCAN_POWERDOWN 2
+#define STIH416_USB0_POWERDOWN 3
+#define STIH416_USB1_POWERDOWN 4
+#define STIH416_USB2_POWERDOWN 5
+#define STIH416_USB3_POWERDOWN 6
+#define STIH416_SATA0_POWERDOWN 7
+#define STIH416_SATA1_POWERDOWN 8
+#define STIH416_PCIE0_POWERDOWN 9
+#define STIH416_PCIE1_POWERDOWN 10
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 03/10] drivers: reset: Reset controller driver for STiH416
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH416
SoC. This initial version provides a compatible driver for the
"st,stih416-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 2 +-
drivers/reset/sti/reset-stih416.c | 79 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 21 +++++
5 files changed, 111 insertions(+), 1 deletions(-)
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326e..b8cabbb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -26,6 +27,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-powerdown";
+ };
+
syscfg_sbc:sbc-syscfg at fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ef6654a..88d2d03 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -8,4 +8,8 @@ config STIH415_RESET
bool
select STI_RESET_SYSCFG
+config STIH416_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index fce4433..be1c976 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-# SoC specific reset devices
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
+obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
new file mode 100644
index 0000000..0becfc5
--- /dev/null
+++ b/drivers/reset/sti/reset-stih416.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih416-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH416 Peripheral powerdown definitions.
+ */
+static const char stih416_front[] = "st,stih416-front-syscfg";
+static const char stih416_rear[] = "st,stih416-rear-syscfg";
+static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
+static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+
+#define STIH416_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
+
+#define STIH416_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
+
+#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
+ [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
+ [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
+ [STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
+ [STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
+ [STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
+ [STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
+ [STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
+ [STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
+ [STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
+ [STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
+ [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih416_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih416_powerdowns),
+ .channels = stih416_powerdowns,
+};
+
+static struct of_device_id stih416_reset_match[] = {
+ { .compatible = "st,stih416-powerdown",
+ .data = &stih416_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih416_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih416",
+ .owner = THIS_MODULE,
+ .of_match_table = stih416_reset_match,
+ },
+};
+
+static int __init stih416_reset_init(void)
+{
+ return platform_driver_register(&stih416_reset_driver);
+}
+arch_initcall(stih416_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 0000000..d7da55f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,21 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
+
+#define STIH416_EMISS_POWERDOWN 0
+#define STIH416_NAND_POWERDOWN 1
+#define STIH416_KEYSCAN_POWERDOWN 2
+#define STIH416_USB0_POWERDOWN 3
+#define STIH416_USB1_POWERDOWN 4
+#define STIH416_USB2_POWERDOWN 5
+#define STIH416_USB3_POWERDOWN 6
+#define STIH416_SATA0_POWERDOWN 7
+#define STIH416_SATA1_POWERDOWN 8
+#define STIH416_PCIE0_POWERDOWN 9
+#define STIH416_PCIE1_POWERDOWN 10
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 04/10] drivers: reset: stih415: add softreset controller
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH415 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih415-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 ++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 5 ++
drivers/reset/sti/reset-stih415.c | 22 ++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 4 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 0000000..b2df262
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,45 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-softreset"
+- #reset-cells: 1, see below
+
+example:
+
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ ethernet0{
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 09379a6b..0c0776e 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -33,6 +33,11 @@
compatible = "st,stih415-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
syscfg_sbc: sbc-syscfg@fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
index 56c2146..fce5153 100644
--- a/drivers/reset/sti/reset-stih415.c
+++ b/drivers/reset/sti/reset-stih415.c
@@ -37,6 +37,10 @@ static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_166 0x108 /* Softreset Ethernet 0 */
+#define SYSCFG_31 0x7c /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
[STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
@@ -49,15 +53,33 @@ static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih415_softresets[] = {
+ [STIH415_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_front,
+ SYSCFG_166, 0),
+ [STIH415_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_sbc,
+ SYSCFG_31, 0),
+ [STIH415_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih415_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih415_powerdowns),
.channels = stih415_powerdowns,
};
+static struct syscfg_reset_controller_data stih415_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih415_softresets),
+ .channels = stih415_softresets,
+};
+
static struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
+ { .compatible = "st,stih415-softreset",
+ .data = &stih415_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
index 2d54e68..825ed41 100644
--- a/include/dt-bindings/reset-controller/stih415-resets.h
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -16,4 +16,8 @@
#define STIH415_SATA1_POWERDOWN 7
#define STIH415_PCIE_POWERDOWN 8
+#define STIH415_ETH0_SOFTRESET 0
+#define STIH415_ETH1_SOFTRESET 1
+#define STIH415_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 04/10] drivers: reset: stih415: add softreset controller
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH415 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih415-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 ++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 5 ++
drivers/reset/sti/reset-stih415.c | 22 ++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 4 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 0000000..b2df262
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,45 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-softreset"
+- #reset-cells: 1, see below
+
+example:
+
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ ethernet0{
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 09379a6b..0c0776e 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -33,6 +33,11 @@
compatible = "st,stih415-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
syscfg_sbc: sbc-syscfg@fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
index 56c2146..fce5153 100644
--- a/drivers/reset/sti/reset-stih415.c
+++ b/drivers/reset/sti/reset-stih415.c
@@ -37,6 +37,10 @@ static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_166 0x108 /* Softreset Ethernet 0 */
+#define SYSCFG_31 0x7c /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
[STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
@@ -49,15 +53,33 @@ static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih415_softresets[] = {
+ [STIH415_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_front,
+ SYSCFG_166, 0),
+ [STIH415_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_sbc,
+ SYSCFG_31, 0),
+ [STIH415_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih415_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih415_powerdowns),
.channels = stih415_powerdowns,
};
+static struct syscfg_reset_controller_data stih415_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih415_softresets),
+ .channels = stih415_softresets,
+};
+
static struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
+ { .compatible = "st,stih415-softreset",
+ .data = &stih415_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
index 2d54e68..825ed41 100644
--- a/include/dt-bindings/reset-controller/stih415-resets.h
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -16,4 +16,8 @@
#define STIH415_SATA1_POWERDOWN 7
#define STIH415_PCIE_POWERDOWN 8
+#define STIH415_ETH0_SOFTRESET 0
+#define STIH415_ETH1_SOFTRESET 1
+#define STIH415_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 04/10] drivers: reset: stih415: add softreset controller
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH415 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih415-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/reset/st,sti-softreset.txt | 45 ++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 5 ++
drivers/reset/sti/reset-stih415.c | 22 ++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 4 ++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 0000000..b2df262
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,45 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-softreset"
+- #reset-cells: 1, see below
+
+example:
+
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ ethernet0{
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 09379a6b..0c0776e 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -33,6 +33,11 @@
compatible = "st,stih415-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
syscfg_sbc: sbc-syscfg at fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
index 56c2146..fce5153 100644
--- a/drivers/reset/sti/reset-stih415.c
+++ b/drivers/reset/sti/reset-stih415.c
@@ -37,6 +37,10 @@ static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_166 0x108 /* Softreset Ethernet 0 */
+#define SYSCFG_31 0x7c /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
[STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
@@ -49,15 +53,33 @@ static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih415_softresets[] = {
+ [STIH415_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_front,
+ SYSCFG_166, 0),
+ [STIH415_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_sbc,
+ SYSCFG_31, 0),
+ [STIH415_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih415_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih415_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih415_powerdowns),
.channels = stih415_powerdowns,
};
+static struct syscfg_reset_controller_data stih415_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih415_softresets),
+ .channels = stih415_softresets,
+};
+
static struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
+ { .compatible = "st,stih415-softreset",
+ .data = &stih415_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
index 2d54e68..825ed41 100644
--- a/include/dt-bindings/reset-controller/stih415-resets.h
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -16,4 +16,8 @@
#define STIH415_SATA1_POWERDOWN 7
#define STIH415_PCIE_POWERDOWN 8
+#define STIH415_ETH0_SOFTRESET 0
+#define STIH415_ETH1_SOFTRESET 1
+#define STIH415_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 05/10] drivers: reset: stih416: add softreset controller
2013-11-12 13:51 ` srinivas.kandagatla
(?)
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH416 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih416-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 5 ++++
drivers/reset/sti/reset-stih416.c | 22 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 4 +++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b8cabbb..a3831a3 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -32,6 +32,11 @@
compatible = "st,stih416-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-softreset";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
index 0becfc5..685fd3b 100644
--- a/drivers/reset/sti/reset-stih416.c
+++ b/drivers/reset/sti/reset-stih416.c
@@ -37,6 +37,10 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
+#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
@@ -51,15 +55,33 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih416_softresets[] = {
+ [STIH416_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_front,
+ SYSCFG_1539, 0),
+ [STIH416_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_sbc,
+ SYSCFG_510, 0),
+ [STIH416_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
+static struct syscfg_reset_controller_data stih416_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih416_softresets),
+ .channels = stih416_softresets,
+};
+
static struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
+ { .compatible = "st,stih416-softreset",
+ .data = &stih416_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
index d7da55f..ee8ccd0 100644
--- a/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -18,4 +18,8 @@
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
+#define STIH416_ETH0_SOFTRESET 0
+#define STIH416_ETH1_SOFTRESET 1
+#define STIH416_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 05/10] drivers: reset: stih416: add softreset controller
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH416 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih416-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 5 ++++
drivers/reset/sti/reset-stih416.c | 22 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 4 +++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b8cabbb..a3831a3 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -32,6 +32,11 @@
compatible = "st,stih416-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-softreset";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
index 0becfc5..685fd3b 100644
--- a/drivers/reset/sti/reset-stih416.c
+++ b/drivers/reset/sti/reset-stih416.c
@@ -37,6 +37,10 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
+#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
@@ -51,15 +55,33 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih416_softresets[] = {
+ [STIH416_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_front,
+ SYSCFG_1539, 0),
+ [STIH416_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_sbc,
+ SYSCFG_510, 0),
+ [STIH416_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
+static struct syscfg_reset_controller_data stih416_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih416_softresets),
+ .channels = stih416_softresets,
+};
+
static struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
+ { .compatible = "st,stih416-softreset",
+ .data = &stih416_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
index d7da55f..ee8ccd0 100644
--- a/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -18,4 +18,8 @@
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
+#define STIH416_ETH0_SOFTRESET 0
+#define STIH416_ETH1_SOFTRESET 1
+#define STIH416_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 05/10] drivers: reset: stih416: add softreset controller
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH416 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih416-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 5 ++++
drivers/reset/sti/reset-stih416.c | 22 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 4 +++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b8cabbb..a3831a3 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -32,6 +32,11 @@
compatible = "st,stih416-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-softreset";
+ };
+
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
index 0becfc5..685fd3b 100644
--- a/drivers/reset/sti/reset-stih416.c
+++ b/drivers/reset/sti/reset-stih416.c
@@ -37,6 +37,10 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
+#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
@@ -51,15 +55,33 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih416_softresets[] = {
+ [STIH416_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_front,
+ SYSCFG_1539, 0),
+ [STIH416_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_sbc,
+ SYSCFG_510, 0),
+ [STIH416_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
+static struct syscfg_reset_controller_data stih416_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih416_softresets),
+ .channels = stih416_softresets,
+};
+
static struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
+ { .compatible = "st,stih416-softreset",
+ .data = &stih416_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
index d7da55f..ee8ccd0 100644
--- a/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -18,4 +18,8 @@
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
+#define STIH416_ETH0_SOFTRESET 0
+#define STIH416_ETH1_SOFTRESET 1
+#define STIH416_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 05/10] drivers: reset: stih416: add softreset controller
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH416 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih416-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 5 ++++
drivers/reset/sti/reset-stih416.c | 22 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 4 +++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b8cabbb..a3831a3 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -32,6 +32,11 @@
compatible = "st,stih416-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-softreset";
+ };
+
syscfg_sbc:sbc-syscfg at fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
index 0becfc5..685fd3b 100644
--- a/drivers/reset/sti/reset-stih416.c
+++ b/drivers/reset/sti/reset-stih416.c
@@ -37,6 +37,10 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
+#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
@@ -51,15 +55,33 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih416_softresets[] = {
+ [STIH416_ETH0_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_front,
+ SYSCFG_1539, 0),
+ [STIH416_ETH1_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_sbc,
+ SYSCFG_510, 0),
+ [STIH416_IRB_SOFTRESET] = _SYSCFG_RST_CH_NO_ACK(stih416_lpm,
+ LPM_SYSCFG_1, 6),
+};
+
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
+static struct syscfg_reset_controller_data stih416_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih416_softresets),
+ .channels = stih416_softresets,
+};
+
static struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
+ { .compatible = "st,stih416-softreset",
+ .data = &stih416_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
index d7da55f..ee8ccd0 100644
--- a/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -18,4 +18,8 @@
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
+#define STIH416_ETH0_SOFTRESET 0
+#define STIH416_ETH1_SOFTRESET 1
+#define STIH416_IRB_SOFTRESET 2
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 06/10] ARM: STi: Add reset controller support to mach-sti Kconfig
2013-11-12 13:51 ` srinivas.kandagatla
(?)
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/mach-sti/Kconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 835833e..b7c527e 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
+ select ARCH_HAS_RESET_CONTROLLER
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SMP
select HAVE_ARM_SCU if SMP
@@ -28,6 +29,7 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
+ select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targetted at set-top-box
@@ -37,6 +39,7 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
+ select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targetted at set-top-box
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 06/10] ARM: STi: Add reset controller support to mach-sti Kconfig
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/mach-sti/Kconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 835833e..b7c527e 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
+ select ARCH_HAS_RESET_CONTROLLER
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SMP
select HAVE_ARM_SCU if SMP
@@ -28,6 +29,7 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
+ select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targetted at set-top-box
@@ -37,6 +39,7 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
+ select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targetted at set-top-box
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 06/10] ARM: STi: Add reset controller support to mach-sti Kconfig
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Mark Rutland, Len Brown, Russell King, Pavel Machek, Pawel Moll,
Ian Campbell, Srinivas Kandagatla, Greg Kroah-Hartman, linux-pm,
Stephen Warren, Rafael J. Wysocki, stephen.gallimore,
Rob Herring, linux-doc, Stuart Menefy, devicetree, Rob Landley,
Grant Likely, Giuseppe Cavallaro, linux-kernel, kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/mach-sti/Kconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 835833e..b7c527e 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
+ select ARCH_HAS_RESET_CONTROLLER
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SMP
select HAVE_ARM_SCU if SMP
@@ -28,6 +29,7 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
+ select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targetted at set-top-box
@@ -37,6 +39,7 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
+ select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targetted at set-top-box
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 06/10] ARM: STi: Add reset controller support to mach-sti Kconfig
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/mach-sti/Kconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 835833e..b7c527e 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
+ select ARCH_HAS_RESET_CONTROLLER
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SMP
select HAVE_ARM_SCU if SMP
@@ -28,6 +29,7 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
+ select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targetted at set-top-box
@@ -37,6 +39,7 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
+ select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targetted at set-top-box
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:52 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch introduces device_child_may_wakeup function, which will be
useful for wrapper or SoC level driver power management code.
Without this patch each driver has to write this same code to get the
functionality.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
drivers/base/power/wakeup.c | 23 +++++++++++++++++++++++
include/linux/pm_wakeup.h | 1 +
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
index 2d56f41..270f000 100644
--- a/drivers/base/power/wakeup.c
+++ b/drivers/base/power/wakeup.c
@@ -342,6 +342,29 @@ int device_set_wakeup_enable(struct device *dev, bool enable)
}
EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
+/* callback for device_child_may_wakeup */
+static int __device_child_may_wakeup(struct device *dev, void *c)
+{
+ return device_may_wakeup(dev);
+}
+
+/**
+ * device_child_may_wakeup - Check if any of the child devices are wakeup
+ * sources.
+ * @dev: parent device to handle.
+ *
+ * Function to check if any of the children of a given parent are wakeup
+ * sources.
+ *
+ * This function will return true if any one of the children of given parent
+ * are wakeup sources, else it returns false.
+ */
+bool device_child_may_wakeup(struct device *parent)
+{
+ return device_for_each_child(parent, NULL, __device_child_may_wakeup);
+}
+EXPORT_SYMBOL_GPL(device_child_may_wakeup);
+
/*
* The functions below use the observation that each wakeup event starts a
* period in which the system should not be suspended. The moment this period
diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
index a0f7080..b376584 100644
--- a/include/linux/pm_wakeup.h
+++ b/include/linux/pm_wakeup.h
@@ -93,6 +93,7 @@ extern int device_wakeup_disable(struct device *dev);
extern void device_set_wakeup_capable(struct device *dev, bool capable);
extern int device_init_wakeup(struct device *dev, bool val);
extern int device_set_wakeup_enable(struct device *dev, bool enable);
+bool device_child_may_wakeup(struct device *parent);
extern void __pm_stay_awake(struct wakeup_source *ws);
extern void pm_stay_awake(struct device *dev);
extern void __pm_relax(struct wakeup_source *ws);
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch introduces device_child_may_wakeup function, which will be
useful for wrapper or SoC level driver power management code.
Without this patch each driver has to write this same code to get the
functionality.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
drivers/base/power/wakeup.c | 23 +++++++++++++++++++++++
include/linux/pm_wakeup.h | 1 +
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
index 2d56f41..270f000 100644
--- a/drivers/base/power/wakeup.c
+++ b/drivers/base/power/wakeup.c
@@ -342,6 +342,29 @@ int device_set_wakeup_enable(struct device *dev, bool enable)
}
EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
+/* callback for device_child_may_wakeup */
+static int __device_child_may_wakeup(struct device *dev, void *c)
+{
+ return device_may_wakeup(dev);
+}
+
+/**
+ * device_child_may_wakeup - Check if any of the child devices are wakeup
+ * sources.
+ * @dev: parent device to handle.
+ *
+ * Function to check if any of the children of a given parent are wakeup
+ * sources.
+ *
+ * This function will return true if any one of the children of given parent
+ * are wakeup sources, else it returns false.
+ */
+bool device_child_may_wakeup(struct device *parent)
+{
+ return device_for_each_child(parent, NULL, __device_child_may_wakeup);
+}
+EXPORT_SYMBOL_GPL(device_child_may_wakeup);
+
/*
* The functions below use the observation that each wakeup event starts a
* period in which the system should not be suspended. The moment this period
diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
index a0f7080..b376584 100644
--- a/include/linux/pm_wakeup.h
+++ b/include/linux/pm_wakeup.h
@@ -93,6 +93,7 @@ extern int device_wakeup_disable(struct device *dev);
extern void device_set_wakeup_capable(struct device *dev, bool capable);
extern int device_init_wakeup(struct device *dev, bool val);
extern int device_set_wakeup_enable(struct device *dev, bool enable);
+bool device_child_may_wakeup(struct device *parent);
extern void __pm_stay_awake(struct wakeup_source *ws);
extern void pm_stay_awake(struct device *dev);
extern void __pm_relax(struct wakeup_source *ws);
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
@ 2013-11-12 13:52 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch introduces device_child_may_wakeup function, which will be
useful for wrapper or SoC level driver power management code.
Without this patch each driver has to write this same code to get the
functionality.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
drivers/base/power/wakeup.c | 23 +++++++++++++++++++++++
include/linux/pm_wakeup.h | 1 +
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
index 2d56f41..270f000 100644
--- a/drivers/base/power/wakeup.c
+++ b/drivers/base/power/wakeup.c
@@ -342,6 +342,29 @@ int device_set_wakeup_enable(struct device *dev, bool enable)
}
EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
+/* callback for device_child_may_wakeup */
+static int __device_child_may_wakeup(struct device *dev, void *c)
+{
+ return device_may_wakeup(dev);
+}
+
+/**
+ * device_child_may_wakeup - Check if any of the child devices are wakeup
+ * sources.
+ * @dev: parent device to handle.
+ *
+ * Function to check if any of the children of a given parent are wakeup
+ * sources.
+ *
+ * This function will return true if any one of the children of given parent
+ * are wakeup sources, else it returns false.
+ */
+bool device_child_may_wakeup(struct device *parent)
+{
+ return device_for_each_child(parent, NULL, __device_child_may_wakeup);
+}
+EXPORT_SYMBOL_GPL(device_child_may_wakeup);
+
/*
* The functions below use the observation that each wakeup event starts a
* period in which the system should not be suspended. The moment this period
diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
index a0f7080..b376584 100644
--- a/include/linux/pm_wakeup.h
+++ b/include/linux/pm_wakeup.h
@@ -93,6 +93,7 @@ extern int device_wakeup_disable(struct device *dev);
extern void device_set_wakeup_capable(struct device *dev, bool capable);
extern int device_init_wakeup(struct device *dev, bool val);
extern int device_set_wakeup_enable(struct device *dev, bool enable);
+bool device_child_may_wakeup(struct device *parent);
extern void __pm_stay_awake(struct wakeup_source *ws);
extern void pm_stay_awake(struct device *dev);
extern void __pm_relax(struct wakeup_source *ws);
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:53 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
STi series SOCs have a glue layer on top of the synopsis gmac IP, this
glue layer needs to be configured before the gmac driver starts using
the IP.
This patch adds a platform driver for the glue layer which configures
the IP before stmmac driver takes over.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
3 files changed, 340 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 0000000..5431d9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,45 @@
+STMicroelectronics SoC DWMAC controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+ "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
+ configuration regmap pointed by st,syscon property and size.
+ - st,syscon : Should be phandle to system configuration node which
+ encompases this glue registers.
+ - st,tx-retime-src: This specifies which clk is wired up to the mac for
+ retimeing tx lines. This is totally board dependent and can take one of the
+ posssible values from "txclk", "clk_125", "phyclk" or "clkgen".
+
+Optional properties:
+ - resets : phandle pointing to the system reset controller with correct
+ reset line index for ethernet reset.
+
+Sub-nodes:
+The dwmac core should be added as subnode to STMicroelectronics dwmac glue.
+- dwmac : The binding details of dwmac can be found in
+ Documentation/devicetree/bindings/net/stmmac.txt
+
+Example:
+
+ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ st,syscon = <&syscfg_rear>;
+ st,tx-retime-src = "clk_125";
+ ranges;
+
+ dwmac0:dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>;
+ interrupt-names = "macirq";
+ ...
+ };
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 356a9dd..32db223 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
+stmmac-$(CONFIG_ARCH_STI) += dwmac-sti.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 0000000..34cfa96
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,294 @@
+/**
+ * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
+ *
+ * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * Inspired by drivers/usb/dwc3/dwc3-exynos.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#define BITS_MASK(lsb, msb) ((BIT(msb - lsb + 1) - 1) << lsb)
+
+#define TX_RETIME_SRC_MASK BITS_MASK(6, 8)
+#define ETH_SEL_TX_RETIME_CLK BIT(8)
+#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
+#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
+
+#define ENMII_MASK BITS_MASK(5, 5)
+#define ENMII BIT(5)
+
+/**
+ * 3 bits [4:2]
+ * 000-GMII/MII
+ * 001-RGMII
+ * 010-SGMII
+ * 100-RMII
+*/
+#define MII_PHY_SEL_MASK BITS_MASK(2, 4)
+#define ETH_PHY_SEL_RMII BIT(4)
+#define ETH_PHY_SEL_SGMII BIT(3)
+#define ETH_PHY_SEL_RGMII BIT(2)
+#define ETH_PHY_SEL_GMII 0x0
+#define ETH_PHY_SEL_MII 0x0
+
+struct sti_dwmac {
+ int interface;
+ int tx_retime_src;
+ int reg;
+ struct device *dev;
+ struct regmap *regmap;
+ struct device_node *dwmac_np;
+ struct reset_control *rstc;
+};
+
+static u32 phy_intf_sels[] = {
+ [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
+ [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
+ [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
+ [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
+};
+
+enum {
+ TX_RETIME_SRC_NA,
+ TX_RETIME_SRC_TXCLK,
+ TX_RETIME_SRC_MII_CLK_125,
+ TX_RETIME_SRC_PHYCLK,
+ TX_RETIME_SRC_CLKGEN,
+};
+
+static const char * const tx_retime_srcs[] = {
+ [TX_RETIME_SRC_NA] = "",
+ [TX_RETIME_SRC_TXCLK] = "txclk",
+ [TX_RETIME_SRC_MII_CLK_125] = "clk_125",
+ [TX_RETIME_SRC_PHYCLK] = "phyclk",
+ [TX_RETIME_SRC_CLKGEN] = "clkgen",
+};
+
+/**
+ * TX lines are always retimed with a clk, which can vary depending
+ * on the board configuration. Below is the table of these bits
+ * in eth configuration register depending on source of retime clk.
+ *
+ *---------------------------------------------------------------
+ * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
+ *---------------------------------------------------------------
+ * txclk | 0 | n/a | 1 |
+ *---------------------------------------------------------------
+ * ck_125| 0 | n/a | 0 |
+ *---------------------------------------------------------------
+ * phyclk| 1 | 0 | n/a |
+ *---------------------------------------------------------------
+ * clkgen| 1 | 1 | n/a |
+ *---------------------------------------------------------------
+ */
+
+static u32 tx_retime_val[] = {
+ [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
+ [TX_RETIME_SRC_MII_CLK_125] = 0x0,
+ [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
+ [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
+ ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
+};
+
+static int sti_get_tx_retime_src(struct device_node *np)
+{
+ const char *rs;
+ int err, i;
+
+ err = of_property_read_string(np, "st,tx-retime-src", &rs);
+ if (err < 0)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(tx_retime_srcs); i++)
+ if (!strcasecmp(rs, tx_retime_srcs[i]))
+ return i;
+
+ return -EINVAL;
+}
+
+static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, struct device *dev)
+{
+ struct resource res;
+ struct device_node *np = dev->of_node;
+ struct device_node *stmmac_np;
+ struct regmap *regmap;
+ int tx_retime_src;
+
+ stmmac_np = of_get_next_available_child(np, NULL);
+ if (!stmmac_np) {
+ dev_info(dev, "No dwmac node found\n");
+ return -EINVAL;
+ }
+
+ if (!of_device_is_compatible(stmmac_np, "snps,dwmac")) {
+ dev_info(dev, "dwmac node isn't compatible with snps,dwmac\n");
+ return -EINVAL;
+ }
+
+ dwmac->interface = of_get_phy_mode(stmmac_np);
+ of_node_put(stmmac_np);
+
+ if (of_address_to_resource(np, 0, &res))
+ return -EINVAL;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ tx_retime_src = sti_get_tx_retime_src(np);
+ if (tx_retime_src <= 0)
+ return tx_retime_src;
+
+ dwmac->tx_retime_src = tx_retime_src;
+ dwmac->regmap = regmap;
+ dwmac->dwmac_np = stmmac_np;
+ dwmac->reg = res.start;
+ dwmac->dev = dev;
+ dwmac->rstc = reset_control_get(dev, NULL);
+
+ if (IS_ERR(dwmac->rstc))
+ dwmac->rstc = NULL;
+
+ return 0;
+}
+
+static int sti_dwmac_setup(struct sti_dwmac *dwmac)
+{
+ struct regmap *regmap = dwmac->regmap;
+ int tx_retime_src = dwmac->tx_retime_src;
+ int iface = dwmac->interface;
+ int reg = dwmac->reg;
+ u32 val;
+
+ regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK,
+ phy_intf_sels[iface]);
+
+ val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
+ regmap_update_bits(regmap, reg, ENMII_MASK, val);
+
+ regmap_update_bits(regmap, reg, TX_RETIME_SRC_MASK,
+ tx_retime_val[tx_retime_src]);
+
+ /* Enable the IP */
+ if (dwmac->rstc)
+ reset_control_deassert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ int ret = -ENOMEM;
+ struct sti_dwmac *dwmac;
+
+ dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
+
+ if (!dwmac)
+ return -ENOMEM;
+
+ ret = sti_dwmac_parse_data(dwmac, dev);
+ if (ret) {
+ dev_err(dev, "Unable to parse OF data\n");
+ return ret;
+ }
+
+ ret = sti_dwmac_setup(dwmac);
+ if (ret) {
+ dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
+ return ret;
+ }
+
+ if (node) {
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwmac core\n");
+ return ret;
+ }
+ } else {
+ dev_err(dev, "no device node, failed to add dwmac core\n");
+ return -ENODEV;
+ }
+
+ platform_set_drvdata(pdev, dwmac);
+
+ return 0;
+}
+
+static int sti_dwmac_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int sti_dwmac_suspend(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ reset_control_assert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_resume(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ sti_dwmac_setup(dwmac);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, sti_dwmac_resume);
+#endif
+
+static const struct of_device_id sti_dwmac_match[] = {
+ { .compatible = "st,stih415-dwmac" },
+ { .compatible = "st,stih416-dwmac" },
+ { .compatible = "st,stid127-dwmac" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sti_dwmac_match);
+
+static struct platform_driver sti_dwmac_driver = {
+ .probe = sti_dwmac_probe,
+ .remove = sti_dwmac_remove,
+ .driver = {
+ .name = "sti-dwmac",
+ .of_match_table = of_match_ptr(sti_dwmac_match),
+#ifdef CONFIG_PM
+ .pm = &sti_dwmac_pm_ops,
+#endif
+ },
+};
+
+module_platform_driver(sti_dwmac_driver);
+
+MODULE_ALIAS("platform:sti-dwmac");
+MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("STMicroelectronics DWMAC Glue Layer");
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
STi series SOCs have a glue layer on top of the synopsis gmac IP, this
glue layer needs to be configured before the gmac driver starts using
the IP.
This patch adds a platform driver for the glue layer which configures
the IP before stmmac driver takes over.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
3 files changed, 340 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 0000000..5431d9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,45 @@
+STMicroelectronics SoC DWMAC controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+ "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
+ configuration regmap pointed by st,syscon property and size.
+ - st,syscon : Should be phandle to system configuration node which
+ encompases this glue registers.
+ - st,tx-retime-src: This specifies which clk is wired up to the mac for
+ retimeing tx lines. This is totally board dependent and can take one of the
+ posssible values from "txclk", "clk_125", "phyclk" or "clkgen".
+
+Optional properties:
+ - resets : phandle pointing to the system reset controller with correct
+ reset line index for ethernet reset.
+
+Sub-nodes:
+The dwmac core should be added as subnode to STMicroelectronics dwmac glue.
+- dwmac : The binding details of dwmac can be found in
+ Documentation/devicetree/bindings/net/stmmac.txt
+
+Example:
+
+ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ st,syscon = <&syscfg_rear>;
+ st,tx-retime-src = "clk_125";
+ ranges;
+
+ dwmac0:dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>;
+ interrupt-names = "macirq";
+ ...
+ };
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 356a9dd..32db223 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
+stmmac-$(CONFIG_ARCH_STI) += dwmac-sti.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 0000000..34cfa96
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,294 @@
+/**
+ * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
+ *
+ * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * Inspired by drivers/usb/dwc3/dwc3-exynos.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#define BITS_MASK(lsb, msb) ((BIT(msb - lsb + 1) - 1) << lsb)
+
+#define TX_RETIME_SRC_MASK BITS_MASK(6, 8)
+#define ETH_SEL_TX_RETIME_CLK BIT(8)
+#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
+#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
+
+#define ENMII_MASK BITS_MASK(5, 5)
+#define ENMII BIT(5)
+
+/**
+ * 3 bits [4:2]
+ * 000-GMII/MII
+ * 001-RGMII
+ * 010-SGMII
+ * 100-RMII
+*/
+#define MII_PHY_SEL_MASK BITS_MASK(2, 4)
+#define ETH_PHY_SEL_RMII BIT(4)
+#define ETH_PHY_SEL_SGMII BIT(3)
+#define ETH_PHY_SEL_RGMII BIT(2)
+#define ETH_PHY_SEL_GMII 0x0
+#define ETH_PHY_SEL_MII 0x0
+
+struct sti_dwmac {
+ int interface;
+ int tx_retime_src;
+ int reg;
+ struct device *dev;
+ struct regmap *regmap;
+ struct device_node *dwmac_np;
+ struct reset_control *rstc;
+};
+
+static u32 phy_intf_sels[] = {
+ [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
+ [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
+ [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
+ [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
+};
+
+enum {
+ TX_RETIME_SRC_NA,
+ TX_RETIME_SRC_TXCLK,
+ TX_RETIME_SRC_MII_CLK_125,
+ TX_RETIME_SRC_PHYCLK,
+ TX_RETIME_SRC_CLKGEN,
+};
+
+static const char * const tx_retime_srcs[] = {
+ [TX_RETIME_SRC_NA] = "",
+ [TX_RETIME_SRC_TXCLK] = "txclk",
+ [TX_RETIME_SRC_MII_CLK_125] = "clk_125",
+ [TX_RETIME_SRC_PHYCLK] = "phyclk",
+ [TX_RETIME_SRC_CLKGEN] = "clkgen",
+};
+
+/**
+ * TX lines are always retimed with a clk, which can vary depending
+ * on the board configuration. Below is the table of these bits
+ * in eth configuration register depending on source of retime clk.
+ *
+ *---------------------------------------------------------------
+ * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
+ *---------------------------------------------------------------
+ * txclk | 0 | n/a | 1 |
+ *---------------------------------------------------------------
+ * ck_125| 0 | n/a | 0 |
+ *---------------------------------------------------------------
+ * phyclk| 1 | 0 | n/a |
+ *---------------------------------------------------------------
+ * clkgen| 1 | 1 | n/a |
+ *---------------------------------------------------------------
+ */
+
+static u32 tx_retime_val[] = {
+ [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
+ [TX_RETIME_SRC_MII_CLK_125] = 0x0,
+ [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
+ [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
+ ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
+};
+
+static int sti_get_tx_retime_src(struct device_node *np)
+{
+ const char *rs;
+ int err, i;
+
+ err = of_property_read_string(np, "st,tx-retime-src", &rs);
+ if (err < 0)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(tx_retime_srcs); i++)
+ if (!strcasecmp(rs, tx_retime_srcs[i]))
+ return i;
+
+ return -EINVAL;
+}
+
+static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, struct device *dev)
+{
+ struct resource res;
+ struct device_node *np = dev->of_node;
+ struct device_node *stmmac_np;
+ struct regmap *regmap;
+ int tx_retime_src;
+
+ stmmac_np = of_get_next_available_child(np, NULL);
+ if (!stmmac_np) {
+ dev_info(dev, "No dwmac node found\n");
+ return -EINVAL;
+ }
+
+ if (!of_device_is_compatible(stmmac_np, "snps,dwmac")) {
+ dev_info(dev, "dwmac node isn't compatible with snps,dwmac\n");
+ return -EINVAL;
+ }
+
+ dwmac->interface = of_get_phy_mode(stmmac_np);
+ of_node_put(stmmac_np);
+
+ if (of_address_to_resource(np, 0, &res))
+ return -EINVAL;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ tx_retime_src = sti_get_tx_retime_src(np);
+ if (tx_retime_src <= 0)
+ return tx_retime_src;
+
+ dwmac->tx_retime_src = tx_retime_src;
+ dwmac->regmap = regmap;
+ dwmac->dwmac_np = stmmac_np;
+ dwmac->reg = res.start;
+ dwmac->dev = dev;
+ dwmac->rstc = reset_control_get(dev, NULL);
+
+ if (IS_ERR(dwmac->rstc))
+ dwmac->rstc = NULL;
+
+ return 0;
+}
+
+static int sti_dwmac_setup(struct sti_dwmac *dwmac)
+{
+ struct regmap *regmap = dwmac->regmap;
+ int tx_retime_src = dwmac->tx_retime_src;
+ int iface = dwmac->interface;
+ int reg = dwmac->reg;
+ u32 val;
+
+ regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK,
+ phy_intf_sels[iface]);
+
+ val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
+ regmap_update_bits(regmap, reg, ENMII_MASK, val);
+
+ regmap_update_bits(regmap, reg, TX_RETIME_SRC_MASK,
+ tx_retime_val[tx_retime_src]);
+
+ /* Enable the IP */
+ if (dwmac->rstc)
+ reset_control_deassert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ int ret = -ENOMEM;
+ struct sti_dwmac *dwmac;
+
+ dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
+
+ if (!dwmac)
+ return -ENOMEM;
+
+ ret = sti_dwmac_parse_data(dwmac, dev);
+ if (ret) {
+ dev_err(dev, "Unable to parse OF data\n");
+ return ret;
+ }
+
+ ret = sti_dwmac_setup(dwmac);
+ if (ret) {
+ dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
+ return ret;
+ }
+
+ if (node) {
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwmac core\n");
+ return ret;
+ }
+ } else {
+ dev_err(dev, "no device node, failed to add dwmac core\n");
+ return -ENODEV;
+ }
+
+ platform_set_drvdata(pdev, dwmac);
+
+ return 0;
+}
+
+static int sti_dwmac_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int sti_dwmac_suspend(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ reset_control_assert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_resume(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ sti_dwmac_setup(dwmac);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, sti_dwmac_resume);
+#endif
+
+static const struct of_device_id sti_dwmac_match[] = {
+ { .compatible = "st,stih415-dwmac" },
+ { .compatible = "st,stih416-dwmac" },
+ { .compatible = "st,stid127-dwmac" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sti_dwmac_match);
+
+static struct platform_driver sti_dwmac_driver = {
+ .probe = sti_dwmac_probe,
+ .remove = sti_dwmac_remove,
+ .driver = {
+ .name = "sti-dwmac",
+ .of_match_table = of_match_ptr(sti_dwmac_match),
+#ifdef CONFIG_PM
+ .pm = &sti_dwmac_pm_ops,
+#endif
+ },
+};
+
+module_platform_driver(sti_dwmac_driver);
+
+MODULE_ALIAS("platform:sti-dwmac");
+MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("STMicroelectronics DWMAC Glue Layer");
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
STi series SOCs have a glue layer on top of the synopsis gmac IP, this
glue layer needs to be configured before the gmac driver starts using
the IP.
This patch adds a platform driver for the glue layer which configures
the IP before stmmac driver takes over.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/net/sti-dwmac.txt | 45 +++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
3 files changed, 340 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 0000000..5431d9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,45 @@
+STMicroelectronics SoC DWMAC controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+ "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
+ configuration regmap pointed by st,syscon property and size.
+ - st,syscon : Should be phandle to system configuration node which
+ encompases this glue registers.
+ - st,tx-retime-src: This specifies which clk is wired up to the mac for
+ retimeing tx lines. This is totally board dependent and can take one of the
+ posssible values from "txclk", "clk_125", "phyclk" or "clkgen".
+
+Optional properties:
+ - resets : phandle pointing to the system reset controller with correct
+ reset line index for ethernet reset.
+
+Sub-nodes:
+The dwmac core should be added as subnode to STMicroelectronics dwmac glue.
+- dwmac : The binding details of dwmac can be found in
+ Documentation/devicetree/bindings/net/stmmac.txt
+
+Example:
+
+ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ st,syscon = <&syscfg_rear>;
+ st,tx-retime-src = "clk_125";
+ ranges;
+
+ dwmac0:dwmac at fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>;
+ interrupt-names = "macirq";
+ ...
+ };
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 356a9dd..32db223 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
+stmmac-$(CONFIG_ARCH_STI) += dwmac-sti.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 0000000..34cfa96
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,294 @@
+/**
+ * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
+ *
+ * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * Inspired by drivers/usb/dwc3/dwc3-exynos.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#define BITS_MASK(lsb, msb) ((BIT(msb - lsb + 1) - 1) << lsb)
+
+#define TX_RETIME_SRC_MASK BITS_MASK(6, 8)
+#define ETH_SEL_TX_RETIME_CLK BIT(8)
+#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
+#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
+
+#define ENMII_MASK BITS_MASK(5, 5)
+#define ENMII BIT(5)
+
+/**
+ * 3 bits [4:2]
+ * 000-GMII/MII
+ * 001-RGMII
+ * 010-SGMII
+ * 100-RMII
+*/
+#define MII_PHY_SEL_MASK BITS_MASK(2, 4)
+#define ETH_PHY_SEL_RMII BIT(4)
+#define ETH_PHY_SEL_SGMII BIT(3)
+#define ETH_PHY_SEL_RGMII BIT(2)
+#define ETH_PHY_SEL_GMII 0x0
+#define ETH_PHY_SEL_MII 0x0
+
+struct sti_dwmac {
+ int interface;
+ int tx_retime_src;
+ int reg;
+ struct device *dev;
+ struct regmap *regmap;
+ struct device_node *dwmac_np;
+ struct reset_control *rstc;
+};
+
+static u32 phy_intf_sels[] = {
+ [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
+ [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
+ [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
+ [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
+};
+
+enum {
+ TX_RETIME_SRC_NA,
+ TX_RETIME_SRC_TXCLK,
+ TX_RETIME_SRC_MII_CLK_125,
+ TX_RETIME_SRC_PHYCLK,
+ TX_RETIME_SRC_CLKGEN,
+};
+
+static const char * const tx_retime_srcs[] = {
+ [TX_RETIME_SRC_NA] = "",
+ [TX_RETIME_SRC_TXCLK] = "txclk",
+ [TX_RETIME_SRC_MII_CLK_125] = "clk_125",
+ [TX_RETIME_SRC_PHYCLK] = "phyclk",
+ [TX_RETIME_SRC_CLKGEN] = "clkgen",
+};
+
+/**
+ * TX lines are always retimed with a clk, which can vary depending
+ * on the board configuration. Below is the table of these bits
+ * in eth configuration register depending on source of retime clk.
+ *
+ *---------------------------------------------------------------
+ * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
+ *---------------------------------------------------------------
+ * txclk | 0 | n/a | 1 |
+ *---------------------------------------------------------------
+ * ck_125| 0 | n/a | 0 |
+ *---------------------------------------------------------------
+ * phyclk| 1 | 0 | n/a |
+ *---------------------------------------------------------------
+ * clkgen| 1 | 1 | n/a |
+ *---------------------------------------------------------------
+ */
+
+static u32 tx_retime_val[] = {
+ [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
+ [TX_RETIME_SRC_MII_CLK_125] = 0x0,
+ [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
+ [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
+ ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
+};
+
+static int sti_get_tx_retime_src(struct device_node *np)
+{
+ const char *rs;
+ int err, i;
+
+ err = of_property_read_string(np, "st,tx-retime-src", &rs);
+ if (err < 0)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(tx_retime_srcs); i++)
+ if (!strcasecmp(rs, tx_retime_srcs[i]))
+ return i;
+
+ return -EINVAL;
+}
+
+static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, struct device *dev)
+{
+ struct resource res;
+ struct device_node *np = dev->of_node;
+ struct device_node *stmmac_np;
+ struct regmap *regmap;
+ int tx_retime_src;
+
+ stmmac_np = of_get_next_available_child(np, NULL);
+ if (!stmmac_np) {
+ dev_info(dev, "No dwmac node found\n");
+ return -EINVAL;
+ }
+
+ if (!of_device_is_compatible(stmmac_np, "snps,dwmac")) {
+ dev_info(dev, "dwmac node isn't compatible with snps,dwmac\n");
+ return -EINVAL;
+ }
+
+ dwmac->interface = of_get_phy_mode(stmmac_np);
+ of_node_put(stmmac_np);
+
+ if (of_address_to_resource(np, 0, &res))
+ return -EINVAL;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ tx_retime_src = sti_get_tx_retime_src(np);
+ if (tx_retime_src <= 0)
+ return tx_retime_src;
+
+ dwmac->tx_retime_src = tx_retime_src;
+ dwmac->regmap = regmap;
+ dwmac->dwmac_np = stmmac_np;
+ dwmac->reg = res.start;
+ dwmac->dev = dev;
+ dwmac->rstc = reset_control_get(dev, NULL);
+
+ if (IS_ERR(dwmac->rstc))
+ dwmac->rstc = NULL;
+
+ return 0;
+}
+
+static int sti_dwmac_setup(struct sti_dwmac *dwmac)
+{
+ struct regmap *regmap = dwmac->regmap;
+ int tx_retime_src = dwmac->tx_retime_src;
+ int iface = dwmac->interface;
+ int reg = dwmac->reg;
+ u32 val;
+
+ regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK,
+ phy_intf_sels[iface]);
+
+ val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
+ regmap_update_bits(regmap, reg, ENMII_MASK, val);
+
+ regmap_update_bits(regmap, reg, TX_RETIME_SRC_MASK,
+ tx_retime_val[tx_retime_src]);
+
+ /* Enable the IP */
+ if (dwmac->rstc)
+ reset_control_deassert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ int ret = -ENOMEM;
+ struct sti_dwmac *dwmac;
+
+ dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
+
+ if (!dwmac)
+ return -ENOMEM;
+
+ ret = sti_dwmac_parse_data(dwmac, dev);
+ if (ret) {
+ dev_err(dev, "Unable to parse OF data\n");
+ return ret;
+ }
+
+ ret = sti_dwmac_setup(dwmac);
+ if (ret) {
+ dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
+ return ret;
+ }
+
+ if (node) {
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwmac core\n");
+ return ret;
+ }
+ } else {
+ dev_err(dev, "no device node, failed to add dwmac core\n");
+ return -ENODEV;
+ }
+
+ platform_set_drvdata(pdev, dwmac);
+
+ return 0;
+}
+
+static int sti_dwmac_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int sti_dwmac_suspend(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ reset_control_assert(dwmac->rstc);
+
+ return 0;
+}
+
+static int sti_dwmac_resume(struct device *dev)
+{
+ struct sti_dwmac *dwmac = dev_get_drvdata(dev);
+
+ if (!device_child_may_wakeup(dev))
+ sti_dwmac_setup(dwmac);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, sti_dwmac_resume);
+#endif
+
+static const struct of_device_id sti_dwmac_match[] = {
+ { .compatible = "st,stih415-dwmac" },
+ { .compatible = "st,stih416-dwmac" },
+ { .compatible = "st,stid127-dwmac" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sti_dwmac_match);
+
+static struct platform_driver sti_dwmac_driver = {
+ .probe = sti_dwmac_probe,
+ .remove = sti_dwmac_remove,
+ .driver = {
+ .name = "sti-dwmac",
+ .of_match_table = of_match_ptr(sti_dwmac_match),
+#ifdef CONFIG_PM
+ .pm = &sti_dwmac_pm_ops,
+#endif
+ },
+};
+
+module_platform_driver(sti_dwmac_driver);
+
+MODULE_ALIAS("platform:sti-dwmac");
+MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("STMicroelectronics DWMAC Glue Layer");
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 09/10] ARM: STi: Add STiH415 ethernet support.
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:53 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 +++++
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 56 ++++++++++++++++++++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 ++++++++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++++++++++++
5 files changed, 217 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799..d047dbc 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
+
+ CLKS_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_GMAC0_PHY";
+ };
+
+ CLKS_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b2..c087af8 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,57 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
+ };
+ };
+
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -197,6 +248,37 @@
};
};
};
+
+ gmac0{
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
+
+ };
+ };
+ };
};
pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 0c0776e..c2b18c8 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -94,5 +94,61 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac0:dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x74 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH415_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac1: dwmac@fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_ETH1_PHY>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2..9ae9ca9 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
aliases {
ttyAS0 = &serial2;
+ ethernet0 = &dwmac0;
+ ethernet1 = &dwmac1;
};
soc {
@@ -37,5 +39,35 @@
};
};
+ ethernet0: ethernet0{
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac0:dwmac@fe810000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO106 2>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac1: dwmac@fef08000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO4 7>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e181..7ce1380 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
aliases {
ttyAS0 = &sbc_serial1;
+ ethernet1 = &dwmac1;
};
soc {
sbc_serial1: serial@fe531000 {
@@ -38,5 +39,37 @@
default-state = "off";
};
};
+
+ /**
+ * ethernet clk routing:
+ * for
+ * max-speed = <1000>;
+ * set
+ * st,tx-retime-src = "clk_125";
+ *
+ * for
+ * max-speed = <100>;
+ * set
+ * st,tx-retime-src = "clkgen";
+ */
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "clkgen";
+
+ dwmac1: dwmac@fef08000 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ max-speed = <100>;
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO3 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 09/10] ARM: STi: Add STiH415 ethernet support.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 +++++
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 56 ++++++++++++++++++++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 ++++++++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++++++++++++
5 files changed, 217 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799..d047dbc 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
+
+ CLKS_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_GMAC0_PHY";
+ };
+
+ CLKS_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b2..c087af8 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,57 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
+ };
+ };
+
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -197,6 +248,37 @@
};
};
};
+
+ gmac0{
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
+
+ };
+ };
+ };
};
pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 0c0776e..c2b18c8 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -94,5 +94,61 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac0:dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x74 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH415_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac1: dwmac@fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_ETH1_PHY>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2..9ae9ca9 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
aliases {
ttyAS0 = &serial2;
+ ethernet0 = &dwmac0;
+ ethernet1 = &dwmac1;
};
soc {
@@ -37,5 +39,35 @@
};
};
+ ethernet0: ethernet0{
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac0:dwmac@fe810000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO106 2>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac1: dwmac@fef08000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO4 7>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e181..7ce1380 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
aliases {
ttyAS0 = &sbc_serial1;
+ ethernet1 = &dwmac1;
};
soc {
sbc_serial1: serial@fe531000 {
@@ -38,5 +39,37 @@
default-state = "off";
};
};
+
+ /**
+ * ethernet clk routing:
+ * for
+ * max-speed = <1000>;
+ * set
+ * st,tx-retime-src = "clk_125";
+ *
+ * for
+ * max-speed = <100>;
+ * set
+ * st,tx-retime-src = "clkgen";
+ */
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "clkgen";
+
+ dwmac1: dwmac@fef08000 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ max-speed = <100>;
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO3 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 09/10] ARM: STi: Add STiH415 ethernet support.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 +++++
arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 56 ++++++++++++++++++++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 32 ++++++++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++++++++++++
5 files changed, 217 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799..d047dbc 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
+
+ CLKS_GMAC0_PHY: clockgenA1 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_GMAC0_PHY";
+ };
+
+ CLKS_ETH1_PHY: clockgenA0 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b2..c087af8 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,57 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
+ };
+ };
+
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -197,6 +248,37 @@
};
};
};
+
+ gmac0{
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
+
+ };
+ };
+ };
};
pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 0c0776e..c2b18c8 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -94,5 +94,61 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x148 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac0:dwmac at fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+ interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih415-dwmac";
+ reg = <0x74 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH415_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac1: dwmac at fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_ETH1_PHY>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2..9ae9ca9 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
aliases {
ttyAS0 = &serial2;
+ ethernet0 = &dwmac0;
+ ethernet1 = &dwmac1;
};
soc {
@@ -37,5 +39,35 @@
};
};
+ ethernet0: ethernet0{
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac0:dwmac at fe810000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO106 2>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "txclk";
+
+ dwmac1: dwmac at fef08000 {
+ status = "okay";
+ phy-mode = "mii";
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO4 7>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+ };
+
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e181..7ce1380 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
aliases {
ttyAS0 = &sbc_serial1;
+ ethernet1 = &dwmac1;
};
soc {
sbc_serial1: serial at fe531000 {
@@ -38,5 +39,37 @@
default-state = "off";
};
};
+
+ /**
+ * ethernet clk routing:
+ * for
+ * max-speed = <1000>;
+ * set
+ * st,tx-retime-src = "clk_125";
+ *
+ * for
+ * max-speed = <100>;
+ * set
+ * st,tx-retime-src = "clkgen";
+ */
+
+ ethernet1: ethernet1 {
+ status = "okay";
+ st,tx-retime-src = "clkgen";
+
+ dwmac1: dwmac at fef08000 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ max-speed = <100>;
+ snps,phy-addr = <0x1>;
+
+ snps,reset-gpio = <&PIO3 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 10/10] ARM: STi: Add STiH416 ethernet support.
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-12 13:53 ` srinivas.kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 58 +++++++++++++++++
3 files changed, 178 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c9..216754f 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,59 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -230,6 +283,59 @@
};
};
};
+
+ gmac0 {
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+ };
+ };
+
+ pinctrl_rgmii0: rgmii0 {
+ st,pins {
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+ rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
+ rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
+ rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
+ rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+ rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+ clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index a3831a3..bf052fb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -103,5 +103,63 @@
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&CLK_SYSIN>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x8bc 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x7f0 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH416_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac@fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_ETH1_PHY>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 10/10] ARM: STi: Add STiH416 ethernet support.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel, netdev
Cc: Rob Herring, Pawel Moll, Mark Rutland, Stephen Warren,
Ian Campbell, Rob Landley, Russell King, Srinivas Kandagatla,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 58 +++++++++++++++++
3 files changed, 178 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c9..216754f 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,59 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -230,6 +283,59 @@
};
};
};
+
+ gmac0 {
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+ };
+ };
+
+ pinctrl_rgmii0: rgmii0 {
+ st,pins {
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+ rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
+ rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
+ rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
+ rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+ rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+ clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index a3831a3..bf052fb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -103,5 +103,63 @@
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&CLK_SYSIN>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x8bc 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac@fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x7f0 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH416_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac@fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_ETH1_PHY>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH RFC 10/10] ARM: STi: Add STiH416 ethernet support.
@ 2013-11-12 13:53 ` srinivas.kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas.kandagatla at st.com @ 2013-11-12 13:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 58 +++++++++++++++++
3 files changed, 178 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c9..216754f 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,59 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
};
pin-controller-front {
@@ -230,6 +283,59 @@
};
};
};
+
+ gmac0 {
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+ };
+ };
+
+ pinctrl_rgmii0: rgmii0 {
+ st,pins {
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+ rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
+ rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
+ rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
+ rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+ rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+ clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index a3831a3..bf052fb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -103,5 +103,63 @@
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&CLK_SYSIN>;
};
+
+ ethernet0: ethernet0{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x8bc 0x4>;
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ ranges;
+
+ dwmac at fe810000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>;
+
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ };
+ };
+
+ ethernet1: ethernet1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "st,stih416-dwmac";
+ reg = <0x7f0 0x4>;
+ st,syscon = <&syscfg_sbc>;
+ resets = <&softreset STIH416_ETH1_SOFTRESET>;
+ ranges;
+
+ dwmac at fef08000 {
+ device_type = "network";
+ compatible = "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>;
+ interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_ETH1_PHY>;
+ };
+ };
+
};
};
--
1.7.6.5
^ permalink raw reply related [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
2013-11-12 14:20 ` Rafael J. Wysocki
(?)
@ 2013-11-12 14:09 ` srinivas kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-11-12 14:09 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Len Brown, stephen.gallimore,
Greg Kroah-Hartman, Giuseppe Cavallaro, Grant Likely, devicetree,
linux-doc, linux-kernel, kernel, linux-pm
On 12/11/13 14:20, Rafael J. Wysocki wrote:
>>
>> > +/* callback for device_child_may_wakeup */
>> > +static int __device_child_may_wakeup(struct device *dev, void *c)
>> > +{
>> > + return device_may_wakeup(dev);
>> > +}
> This doesn't have anything to do with children in principle, so please call
> it differently. Something like device_may_wakeup_cb() would work for me (and
> then you may not need the comment even).
Thanks Rafael, I will fix this in next version.
>
> Thanks!
>
>> > +
>> > +/**
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
@ 2013-11-12 14:09 ` srinivas kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-11-12 14:09 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Len Brown, stephen.gallimore,
Greg Kroah-Hartman, Giuseppe Cavallaro, Grant Likely, devicetree,
linux-doc, linux-kernel, kernel, linux-pm
On 12/11/13 14:20, Rafael J. Wysocki wrote:
>>
>> > +/* callback for device_child_may_wakeup */
>> > +static int __device_child_may_wakeup(struct device *dev, void *c)
>> > +{
>> > + return device_may_wakeup(dev);
>> > +}
> This doesn't have anything to do with children in principle, so please call
> it differently. Something like device_may_wakeup_cb() would work for me (and
> then you may not need the comment even).
Thanks Rafael, I will fix this in next version.
>
> Thanks!
>
>> > +
>> > +/**
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
@ 2013-11-12 14:09 ` srinivas kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-11-12 14:09 UTC (permalink / raw)
To: linux-arm-kernel
On 12/11/13 14:20, Rafael J. Wysocki wrote:
>>
>> > +/* callback for device_child_may_wakeup */
>> > +static int __device_child_may_wakeup(struct device *dev, void *c)
>> > +{
>> > + return device_may_wakeup(dev);
>> > +}
> This doesn't have anything to do with children in principle, so please call
> it differently. Something like device_may_wakeup_cb() would work for me (and
> then you may not need the comment even).
Thanks Rafael, I will fix this in next version.
>
> Thanks!
>
>> > +
>> > +/**
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
2013-11-12 13:52 ` srinivas.kandagatla
@ 2013-11-12 14:20 ` Rafael J. Wysocki
-1 siblings, 0 replies; 51+ messages in thread
From: Rafael J. Wysocki @ 2013-11-12 14:20 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Len Brown, stephen.gallimore,
Greg Kroah-Hartman, Giuseppe Cavallaro, Grant Likely, devicetree,
linux-doc, linux-kernel, kernel, linux-pm
On Tuesday, November 12, 2013 01:52:57 PM srinivas.kandagatla@st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> This patch introduces device_child_may_wakeup function, which will be
> useful for wrapper or SoC level driver power management code.
> Without this patch each driver has to write this same code to get the
> functionality.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> ---
> drivers/base/power/wakeup.c | 23 +++++++++++++++++++++++
> include/linux/pm_wakeup.h | 1 +
> 2 files changed, 24 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
> index 2d56f41..270f000 100644
> --- a/drivers/base/power/wakeup.c
> +++ b/drivers/base/power/wakeup.c
> @@ -342,6 +342,29 @@ int device_set_wakeup_enable(struct device *dev, bool enable)
> }
> EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
>
> +/* callback for device_child_may_wakeup */
> +static int __device_child_may_wakeup(struct device *dev, void *c)
> +{
> + return device_may_wakeup(dev);
> +}
This doesn't have anything to do with children in principle, so please call
it differently. Something like device_may_wakeup_cb() would work for me (and
then you may not need the comment even).
Thanks!
> +
> +/**
> + * device_child_may_wakeup - Check if any of the child devices are wakeup
> + * sources.
> + * @dev: parent device to handle.
> + *
> + * Function to check if any of the children of a given parent are wakeup
> + * sources.
> + *
> + * This function will return true if any one of the children of given parent
> + * are wakeup sources, else it returns false.
> + */
> +bool device_child_may_wakeup(struct device *parent)
> +{
> + return device_for_each_child(parent, NULL, __device_child_may_wakeup);
> +}
> +EXPORT_SYMBOL_GPL(device_child_may_wakeup);
> +
> /*
> * The functions below use the observation that each wakeup event starts a
> * period in which the system should not be suspended. The moment this period
> diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
> index a0f7080..b376584 100644
> --- a/include/linux/pm_wakeup.h
> +++ b/include/linux/pm_wakeup.h
> @@ -93,6 +93,7 @@ extern int device_wakeup_disable(struct device *dev);
> extern void device_set_wakeup_capable(struct device *dev, bool capable);
> extern int device_init_wakeup(struct device *dev, bool val);
> extern int device_set_wakeup_enable(struct device *dev, bool enable);
> +bool device_child_may_wakeup(struct device *parent);
> extern void __pm_stay_awake(struct wakeup_source *ws);
> extern void pm_stay_awake(struct device *dev);
> extern void __pm_relax(struct wakeup_source *ws);
>
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup
@ 2013-11-12 14:20 ` Rafael J. Wysocki
0 siblings, 0 replies; 51+ messages in thread
From: Rafael J. Wysocki @ 2013-11-12 14:20 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, November 12, 2013 01:52:57 PM srinivas.kandagatla at st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> This patch introduces device_child_may_wakeup function, which will be
> useful for wrapper or SoC level driver power management code.
> Without this patch each driver has to write this same code to get the
> functionality.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> ---
> drivers/base/power/wakeup.c | 23 +++++++++++++++++++++++
> include/linux/pm_wakeup.h | 1 +
> 2 files changed, 24 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
> index 2d56f41..270f000 100644
> --- a/drivers/base/power/wakeup.c
> +++ b/drivers/base/power/wakeup.c
> @@ -342,6 +342,29 @@ int device_set_wakeup_enable(struct device *dev, bool enable)
> }
> EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
>
> +/* callback for device_child_may_wakeup */
> +static int __device_child_may_wakeup(struct device *dev, void *c)
> +{
> + return device_may_wakeup(dev);
> +}
This doesn't have anything to do with children in principle, so please call
it differently. Something like device_may_wakeup_cb() would work for me (and
then you may not need the comment even).
Thanks!
> +
> +/**
> + * device_child_may_wakeup - Check if any of the child devices are wakeup
> + * sources.
> + * @dev: parent device to handle.
> + *
> + * Function to check if any of the children of a given parent are wakeup
> + * sources.
> + *
> + * This function will return true if any one of the children of given parent
> + * are wakeup sources, else it returns false.
> + */
> +bool device_child_may_wakeup(struct device *parent)
> +{
> + return device_for_each_child(parent, NULL, __device_child_may_wakeup);
> +}
> +EXPORT_SYMBOL_GPL(device_child_may_wakeup);
> +
> /*
> * The functions below use the observation that each wakeup event starts a
> * period in which the system should not be suspended. The moment this period
> diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h
> index a0f7080..b376584 100644
> --- a/include/linux/pm_wakeup.h
> +++ b/include/linux/pm_wakeup.h
> @@ -93,6 +93,7 @@ extern int device_wakeup_disable(struct device *dev);
> extern void device_set_wakeup_capable(struct device *dev, bool capable);
> extern int device_init_wakeup(struct device *dev, bool val);
> extern int device_set_wakeup_enable(struct device *dev, bool enable);
> +bool device_child_may_wakeup(struct device *parent);
> extern void __pm_stay_awake(struct wakeup_source *ws);
> extern void pm_stay_awake(struct device *dev);
> extern void __pm_relax(struct wakeup_source *ws);
>
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
2013-11-12 13:51 ` srinivas.kandagatla
(?)
@ 2013-11-19 5:28 ` Giuseppe CAVALLARO
-1 siblings, 0 replies; 51+ messages in thread
From: Giuseppe CAVALLARO @ 2013-11-19 5:28 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
Greg Kroah-Hartman, Grant Likely, devicetree, linux-doc,
stephen.gallimore, linux-kernel, kernel, linux-pm
On 11/12/2013 2:51 PM, srinivas.kandagatla@st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> Hi All,
>
> This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
> STi SOC series integrates dwmac IP from synopsis, however there is a hardware
> glue on top of this standard IP, this glue needs to configured before the
> actual dwmac can be used.
> To add this a new driver dwmac-sti is introduced whose responsibility is to
> configure dwmac glue and before dwmac driver, this is achieved by making dwmac
> device node as child to ethernet glue node. Inspired by usb/dwc3.
> Also the glue needs to come out of softreset which is why we have added a
> softreset controller to driver which looked perfectly neat, rather then
> driving the softreset bit from the glue driver.
>
> Also as part of power management in glue driver, I found that there was no
> function to determine if the child device is a wakeup source or not.
> I have added a new api device_child_may_wakeup API which could be useful for
> drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
> that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
> this new API.
>
> The reason for combining all these patches in a same series is because of
> dependencies.
>
> This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
> SOC on ethernet 100/1000 Links.
>
> Comments?
Hello Srini
ll these patches are ok for me and, as you know, I have already started
using them while porting other SoC. Glue logic is mandatory now!
Thanks
peppe
>
> Thanks,
> srini
>
> Srinivas Kandagatla (6):
> drivers: reset: stih415: add softreset controller
> drivers: reset: stih416: add softreset controller
> PM / wakeup : Introduce device_child_may_wakeup
> net: stmmac:sti: Add STi SOC glue driver.
> ARM: STi: Add STiH415 ethernet support.
> ARM: STi: Add STiH416 ethernet support.
>
> Stephen Gallimore (4):
> drivers: reset: STi SoC system configuration reset controller support
> drivers: reset: Reset controller driver for STiH415
> drivers: reset: Reset controller driver for STiH416
> ARM: STi: Add reset controller support to mach-sti Kconfig
>
> .../devicetree/bindings/net/sti-dwmac.txt | 45 +++
> .../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
> .../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
> arch/arm/boot/dts/stih415-clock.dtsi | 14 +
> arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
> arch/arm/boot/dts/stih415.dtsi | 67 +++++
> arch/arm/boot/dts/stih416-clock.dtsi | 14 +
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
> arch/arm/boot/dts/stih416.dtsi | 69 +++++
> arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
> arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
> arch/arm/mach-sti/Kconfig | 3 +
> drivers/base/power/wakeup.c | 23 ++
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
> drivers/reset/Kconfig | 2 +
> drivers/reset/Makefile | 3 +
> drivers/reset/sti/Kconfig | 15 +
> drivers/reset/sti/Makefile | 4 +
> drivers/reset/sti/reset-stih415.c | 99 +++++++
> drivers/reset/sti/reset-stih416.c | 101 +++++++
> drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
> drivers/reset/sti/reset-syscfg.h | 69 +++++
> .../dt-bindings/reset-controller/stih415-resets.h | 23 ++
> .../dt-bindings/reset-controller/stih416-resets.h | 25 ++
> include/linux/pm_wakeup.h | 1 +
> 26 files changed, 1402 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
> create mode 100644 drivers/reset/sti/Kconfig
> create mode 100644 drivers/reset/sti/Makefile
> create mode 100644 drivers/reset/sti/reset-stih415.c
> create mode 100644 drivers/reset/sti/reset-stih416.c
> create mode 100644 drivers/reset/sti/reset-syscfg.c
> create mode 100644 drivers/reset/sti/reset-syscfg.h
> create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
> create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
@ 2013-11-19 5:28 ` Giuseppe CAVALLARO
0 siblings, 0 replies; 51+ messages in thread
From: Giuseppe CAVALLARO @ 2013-11-19 5:28 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
Greg Kroah-Hartman, Grant Likely, devicetree, linux-doc,
stephen.gallimore, linux-kernel, kernel, linux-pm
On 11/12/2013 2:51 PM, srinivas.kandagatla@st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> Hi All,
>
> This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
> STi SOC series integrates dwmac IP from synopsis, however there is a hardware
> glue on top of this standard IP, this glue needs to configured before the
> actual dwmac can be used.
> To add this a new driver dwmac-sti is introduced whose responsibility is to
> configure dwmac glue and before dwmac driver, this is achieved by making dwmac
> device node as child to ethernet glue node. Inspired by usb/dwc3.
> Also the glue needs to come out of softreset which is why we have added a
> softreset controller to driver which looked perfectly neat, rather then
> driving the softreset bit from the glue driver.
>
> Also as part of power management in glue driver, I found that there was no
> function to determine if the child device is a wakeup source or not.
> I have added a new api device_child_may_wakeup API which could be useful for
> drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
> that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
> this new API.
>
> The reason for combining all these patches in a same series is because of
> dependencies.
>
> This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
> SOC on ethernet 100/1000 Links.
>
> Comments?
Hello Srini
ll these patches are ok for me and, as you know, I have already started
using them while porting other SoC. Glue logic is mandatory now!
Thanks
peppe
>
> Thanks,
> srini
>
> Srinivas Kandagatla (6):
> drivers: reset: stih415: add softreset controller
> drivers: reset: stih416: add softreset controller
> PM / wakeup : Introduce device_child_may_wakeup
> net: stmmac:sti: Add STi SOC glue driver.
> ARM: STi: Add STiH415 ethernet support.
> ARM: STi: Add STiH416 ethernet support.
>
> Stephen Gallimore (4):
> drivers: reset: STi SoC system configuration reset controller support
> drivers: reset: Reset controller driver for STiH415
> drivers: reset: Reset controller driver for STiH416
> ARM: STi: Add reset controller support to mach-sti Kconfig
>
> .../devicetree/bindings/net/sti-dwmac.txt | 45 +++
> .../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
> .../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
> arch/arm/boot/dts/stih415-clock.dtsi | 14 +
> arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
> arch/arm/boot/dts/stih415.dtsi | 67 +++++
> arch/arm/boot/dts/stih416-clock.dtsi | 14 +
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
> arch/arm/boot/dts/stih416.dtsi | 69 +++++
> arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
> arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
> arch/arm/mach-sti/Kconfig | 3 +
> drivers/base/power/wakeup.c | 23 ++
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
> drivers/reset/Kconfig | 2 +
> drivers/reset/Makefile | 3 +
> drivers/reset/sti/Kconfig | 15 +
> drivers/reset/sti/Makefile | 4 +
> drivers/reset/sti/reset-stih415.c | 99 +++++++
> drivers/reset/sti/reset-stih416.c | 101 +++++++
> drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
> drivers/reset/sti/reset-syscfg.h | 69 +++++
> .../dt-bindings/reset-controller/stih415-resets.h | 23 ++
> .../dt-bindings/reset-controller/stih416-resets.h | 25 ++
> include/linux/pm_wakeup.h | 1 +
> 26 files changed, 1402 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
> create mode 100644 drivers/reset/sti/Kconfig
> create mode 100644 drivers/reset/sti/Makefile
> create mode 100644 drivers/reset/sti/reset-stih415.c
> create mode 100644 drivers/reset/sti/reset-stih416.c
> create mode 100644 drivers/reset/sti/reset-syscfg.c
> create mode 100644 drivers/reset/sti/reset-syscfg.h
> create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
> create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller
@ 2013-11-19 5:28 ` Giuseppe CAVALLARO
0 siblings, 0 replies; 51+ messages in thread
From: Giuseppe CAVALLARO @ 2013-11-19 5:28 UTC (permalink / raw)
To: linux-arm-kernel
On 11/12/2013 2:51 PM, srinivas.kandagatla at st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> Hi All,
>
> This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
> STi SOC series integrates dwmac IP from synopsis, however there is a hardware
> glue on top of this standard IP, this glue needs to configured before the
> actual dwmac can be used.
> To add this a new driver dwmac-sti is introduced whose responsibility is to
> configure dwmac glue and before dwmac driver, this is achieved by making dwmac
> device node as child to ethernet glue node. Inspired by usb/dwc3.
> Also the glue needs to come out of softreset which is why we have added a
> softreset controller to driver which looked perfectly neat, rather then
> driving the softreset bit from the glue driver.
>
> Also as part of power management in glue driver, I found that there was no
> function to determine if the child device is a wakeup source or not.
> I have added a new api device_child_may_wakeup API which could be useful for
> drivers like this. "PM / wakeup : Introduce device_child_may_wakeup" patch has
> that new API and "net: stmmac:sti: Add STi SOC glue driver." glue driver uses
> this new API.
>
> The reason for combining all these patches in a same series is because of
> dependencies.
>
> This patch series is tested on B2000 and B2020 boards with STiH415, STiH416
> SOC on ethernet 100/1000 Links.
>
> Comments?
Hello Srini
ll these patches are ok for me and, as you know, I have already started
using them while porting other SoC. Glue logic is mandatory now!
Thanks
peppe
>
> Thanks,
> srini
>
> Srinivas Kandagatla (6):
> drivers: reset: stih415: add softreset controller
> drivers: reset: stih416: add softreset controller
> PM / wakeup : Introduce device_child_may_wakeup
> net: stmmac:sti: Add STi SOC glue driver.
> ARM: STi: Add STiH415 ethernet support.
> ARM: STi: Add STiH416 ethernet support.
>
> Stephen Gallimore (4):
> drivers: reset: STi SoC system configuration reset controller support
> drivers: reset: Reset controller driver for STiH415
> drivers: reset: Reset controller driver for STiH416
> ARM: STi: Add reset controller support to mach-sti Kconfig
>
> .../devicetree/bindings/net/sti-dwmac.txt | 45 +++
> .../devicetree/bindings/reset/st,sti-powerdown.txt | 46 +++
> .../devicetree/bindings/reset/st,sti-softreset.txt | 45 +++
> arch/arm/boot/dts/stih415-clock.dtsi | 14 +
> arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++
> arch/arm/boot/dts/stih415.dtsi | 67 +++++
> arch/arm/boot/dts/stih416-clock.dtsi | 14 +
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 106 +++++++
> arch/arm/boot/dts/stih416.dtsi | 69 +++++
> arch/arm/boot/dts/stih41x-b2000.dtsi | 32 +++
> arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++
> arch/arm/mach-sti/Kconfig | 3 +
> drivers/base/power/wakeup.c | 23 ++
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
> drivers/reset/Kconfig | 2 +
> drivers/reset/Makefile | 3 +
> drivers/reset/sti/Kconfig | 15 +
> drivers/reset/sti/Makefile | 4 +
> drivers/reset/sti/reset-stih415.c | 99 +++++++
> drivers/reset/sti/reset-stih416.c | 101 +++++++
> drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++
> drivers/reset/sti/reset-syscfg.h | 69 +++++
> .../dt-bindings/reset-controller/stih415-resets.h | 23 ++
> .../dt-bindings/reset-controller/stih416-resets.h | 25 ++
> include/linux/pm_wakeup.h | 1 +
> 26 files changed, 1402 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
> create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
> create mode 100644 drivers/reset/sti/Kconfig
> create mode 100644 drivers/reset/sti/Makefile
> create mode 100644 drivers/reset/sti/reset-stih415.c
> create mode 100644 drivers/reset/sti/reset-stih416.c
> create mode 100644 drivers/reset/sti/reset-syscfg.c
> create mode 100644 drivers/reset/sti/reset-syscfg.h
> create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
> create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
2013-11-12 13:53 ` srinivas.kandagatla
@ 2013-11-29 19:37 ` Maxime Ripard
-1 siblings, 0 replies; 51+ messages in thread
From: Maxime Ripard @ 2013-11-29 19:37 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
[-- Attachment #1: Type: text/plain, Size: 4005 bytes --]
Hi Srinivas,
On Tue, Nov 12, 2013 at 01:53:03PM +0000, srinivas.kandagatla@st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> STi series SOCs have a glue layer on top of the synopsis gmac IP, this
> glue layer needs to be configured before the gmac driver starts using
> the IP.
>
> This patch adds a platform driver for the glue layer which configures
> the IP before stmmac driver takes over.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> ---
> .../devicetree/bindings/net/sti-dwmac.txt | 45 +++
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
> 3 files changed, 340 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
>
> diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
> new file mode 100644
> index 0000000..5431d9d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
> @@ -0,0 +1,45 @@
> +STMicroelectronics SoC DWMAC controller
> +
> +The device node has following properties.
> +
> +Required properties:
> + - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
> + "st,stid127-dwmac".
> + - reg : Offset of the glue configuration register map in system
> + configuration regmap pointed by st,syscon property and size.
> + - st,syscon : Should be phandle to system configuration node which
> + encompases this glue registers.
> + - st,tx-retime-src: This specifies which clk is wired up to the mac for
> + retimeing tx lines. This is totally board dependent and can take one of the
> + posssible values from "txclk", "clk_125", "phyclk" or "clkgen".
> +
> +Optional properties:
> + - resets : phandle pointing to the system reset controller with correct
> + reset line index for ethernet reset.
> +
> +Sub-nodes:
> +The dwmac core should be added as subnode to STMicroelectronics dwmac glue.
> +- dwmac : The binding details of dwmac can be found in
> + Documentation/devicetree/bindings/net/stmmac.txt
> +
> +Example:
> +
> +ethernet0: ethernet0{
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,stih415-dwmac";
> + reg = <0x148 0x4>;
> + resets = <&softreset STIH415_ETH0_SOFTRESET>;
> + st,syscon = <&syscfg_rear>;
> + st,tx-retime-src = "clk_125";
> + ranges;
> +
> + dwmac0:dwmac@fe810000 {
> + device_type = "network";
> + compatible = "snps,dwmac", "snps,dwmac-3.610";
> + reg = <0xfe810000 0x8000>;
> + interrupts = <0 147 0>;
> + interrupt-names = "macirq";
> + ...
> + };
> +};
Sorry for stepping up so late, but I dont' think this is the right way
to do it.
DT is to describe how the hardware is laid out in a system agnostic
way, hence, it should not be impacted by the implementation details.
The fact that you use a glue to the dwmac driver *is* an
implementation detail.
I think you'd rather have something like:
dwmac0: ethernet@fe810000 {
compatible = "st,stih415-dwmac";
reg = <0xfe810000 0x8000 0x148 0x4>;
resets = <&softreset STIH415_ETH0_SOFTRESET>;
st,syscon = <&syscfg_rear>;
st,tx-retime-src = "clk_125";
interrupts = <0 147 0>;
interrupt-names = "macirq";
...
};
Then, the driver can have its init functions associated to the
compatible you're using, through the .data field of the of_device_id
structure, and you just call it in the generic driver at probe's time.
I don't really know what this syscon thing is either, but I think the
reg <0x148 0x4> is related to that.
Why don't you pass it directly in the st,syscon property, to have
something like <&syscfg_rear 0x148>?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-11-29 19:37 ` Maxime Ripard
0 siblings, 0 replies; 51+ messages in thread
From: Maxime Ripard @ 2013-11-29 19:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Srinivas,
On Tue, Nov 12, 2013 at 01:53:03PM +0000, srinivas.kandagatla at st.com wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> STi series SOCs have a glue layer on top of the synopsis gmac IP, this
> glue layer needs to be configured before the gmac driver starts using
> the IP.
>
> This patch adds a platform driver for the glue layer which configures
> the IP before stmmac driver takes over.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> ---
> .../devicetree/bindings/net/sti-dwmac.txt | 45 +++
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 294 ++++++++++++++++++++
> 3 files changed, 340 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
>
> diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
> new file mode 100644
> index 0000000..5431d9d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
> @@ -0,0 +1,45 @@
> +STMicroelectronics SoC DWMAC controller
> +
> +The device node has following properties.
> +
> +Required properties:
> + - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
> + "st,stid127-dwmac".
> + - reg : Offset of the glue configuration register map in system
> + configuration regmap pointed by st,syscon property and size.
> + - st,syscon : Should be phandle to system configuration node which
> + encompases this glue registers.
> + - st,tx-retime-src: This specifies which clk is wired up to the mac for
> + retimeing tx lines. This is totally board dependent and can take one of the
> + posssible values from "txclk", "clk_125", "phyclk" or "clkgen".
> +
> +Optional properties:
> + - resets : phandle pointing to the system reset controller with correct
> + reset line index for ethernet reset.
> +
> +Sub-nodes:
> +The dwmac core should be added as subnode to STMicroelectronics dwmac glue.
> +- dwmac : The binding details of dwmac can be found in
> + Documentation/devicetree/bindings/net/stmmac.txt
> +
> +Example:
> +
> +ethernet0: ethernet0{
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,stih415-dwmac";
> + reg = <0x148 0x4>;
> + resets = <&softreset STIH415_ETH0_SOFTRESET>;
> + st,syscon = <&syscfg_rear>;
> + st,tx-retime-src = "clk_125";
> + ranges;
> +
> + dwmac0:dwmac at fe810000 {
> + device_type = "network";
> + compatible = "snps,dwmac", "snps,dwmac-3.610";
> + reg = <0xfe810000 0x8000>;
> + interrupts = <0 147 0>;
> + interrupt-names = "macirq";
> + ...
> + };
> +};
Sorry for stepping up so late, but I dont' think this is the right way
to do it.
DT is to describe how the hardware is laid out in a system agnostic
way, hence, it should not be impacted by the implementation details.
The fact that you use a glue to the dwmac driver *is* an
implementation detail.
I think you'd rather have something like:
dwmac0: ethernet at fe810000 {
compatible = "st,stih415-dwmac";
reg = <0xfe810000 0x8000 0x148 0x4>;
resets = <&softreset STIH415_ETH0_SOFTRESET>;
st,syscon = <&syscfg_rear>;
st,tx-retime-src = "clk_125";
interrupts = <0 147 0>;
interrupt-names = "macirq";
...
};
Then, the driver can have its init functions associated to the
compatible you're using, through the .data field of the of_device_id
structure, and you just call it in the generic driver at probe's time.
I don't really know what this syscon thing is either, but I think the
reg <0x148 0x4> is related to that.
Why don't you pass it directly in the st,syscon property, to have
something like <&syscfg_rear 0x148>?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
-------------- next part --------------
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
2013-11-29 19:37 ` Maxime Ripard
(?)
@ 2013-12-02 12:48 ` srinivas kandagatla
-1 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-12-02 12:48 UTC (permalink / raw)
To: Maxime Ripard
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
Hi Maxime,
Thankyou for the comments.
On 29/11/13 19:37, Maxime Ripard wrote:
>> +
>> > +ethernet0: ethernet0{
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > + compatible = "st,stih415-dwmac";
>> > + reg = <0x148 0x4>;
>> > + resets = <&softreset STIH415_ETH0_SOFTRESET>;
>> > + st,syscon = <&syscfg_rear>;
>> > + st,tx-retime-src = "clk_125";
>> > + ranges;
>> > +
>> > + dwmac0:dwmac@fe810000 {
>> > + device_type = "network";
>> > + compatible = "snps,dwmac", "snps,dwmac-3.610";
>> > + reg = <0xfe810000 0x8000>;
>> > + interrupts = <0 147 0>;
>> > + interrupt-names = "macirq";
>> > + ...
>> > + };
>> > +};
> Sorry for stepping up so late, but I dont' think this is the right way
> to do it.
>
Not a issue.
> DT is to describe how the hardware is laid out in a system agnostic
> way, hence, it should not be impacted by the implementation details.
>
If "hardware is laid out" means at SoC level? Then I attempted to do
describe it in system agnostic way.
On ST SoCs "snps,dwmac" IP always has a hw glue layer on top of it.
> The fact that you use a glue to the dwmac driver *is* an
> implementation detail.
Glue layer described here is actually a hardware glue on ST SoCs.
>
> I think you'd rather have something like:
>
> dwmac0: ethernet@fe810000 {
> compatible = "st,stih415-dwmac";
> reg = <0xfe810000 0x8000 0x148 0x4>;
> resets = <&softreset STIH415_ETH0_SOFTRESET>;
> st,syscon = <&syscfg_rear>;
> st,tx-retime-src = "clk_125";
> interrupts = <0 147 0>;
> interrupt-names = "macirq";Am happy to go with
> ...
> };
>
> Then, the driver can have its init functions associated to the
> compatible you're using, through the .data field of the of_device_id
> structure, and you just call it in the generic driver at probe's time.
This is changing the device tree bindings for the generic driver.
Is this something Acceptable?
Peppe, are you Ok with such intrusive changes to the driver?
I did try few things before I sent this patch,
1> Doing it via AUXDATA which was discouraged by Arnd.
2> Doing it the way you suggested which did not fit in very neatly,
which looked like lot of SOC specific changes are added to generic driver.
3> Doing it as this patch, influenced by dwc3 code drivers/usb/dwc3/,
Which fitted in very neatly without touching the existing generic driver.
stmmac driver is a generic synopsis driver which ST has written the
driver, so I did not want to pollute this driver with ST specific glue
logic bindings.
Again, this could be irrelevant/confusing to other people who are using
this driver in there SoCs.
Only thing that bothers me with your suggestion is the changes to
generic driver.
>
> I don't really know what this syscon thing is either, but I think the
> reg <0x148 0x4> is related to that.
Yes, it is related to that.
>
> Why don't you pass it directly in the st,syscon property, to have
> something like <&syscfg_rear 0x148>?
This style was once discouraged by Arnd when I first sent pinctrl driver
for reasons that dt should not specify the offsets to registers.
>
> Maxime
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-12-02 12:48 ` srinivas kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-12-02 12:48 UTC (permalink / raw)
To: Maxime Ripard
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
Hi Maxime,
Thankyou for the comments.
On 29/11/13 19:37, Maxime Ripard wrote:
>> +
>> > +ethernet0: ethernet0{
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > + compatible = "st,stih415-dwmac";
>> > + reg = <0x148 0x4>;
>> > + resets = <&softreset STIH415_ETH0_SOFTRESET>;
>> > + st,syscon = <&syscfg_rear>;
>> > + st,tx-retime-src = "clk_125";
>> > + ranges;
>> > +
>> > + dwmac0:dwmac@fe810000 {
>> > + device_type = "network";
>> > + compatible = "snps,dwmac", "snps,dwmac-3.610";
>> > + reg = <0xfe810000 0x8000>;
>> > + interrupts = <0 147 0>;
>> > + interrupt-names = "macirq";
>> > + ...
>> > + };
>> > +};
> Sorry for stepping up so late, but I dont' think this is the right way
> to do it.
>
Not a issue.
> DT is to describe how the hardware is laid out in a system agnostic
> way, hence, it should not be impacted by the implementation details.
>
If "hardware is laid out" means at SoC level? Then I attempted to do
describe it in system agnostic way.
On ST SoCs "snps,dwmac" IP always has a hw glue layer on top of it.
> The fact that you use a glue to the dwmac driver *is* an
> implementation detail.
Glue layer described here is actually a hardware glue on ST SoCs.
>
> I think you'd rather have something like:
>
> dwmac0: ethernet@fe810000 {
> compatible = "st,stih415-dwmac";
> reg = <0xfe810000 0x8000 0x148 0x4>;
> resets = <&softreset STIH415_ETH0_SOFTRESET>;
> st,syscon = <&syscfg_rear>;
> st,tx-retime-src = "clk_125";
> interrupts = <0 147 0>;
> interrupt-names = "macirq";Am happy to go with
> ...
> };
>
> Then, the driver can have its init functions associated to the
> compatible you're using, through the .data field of the of_device_id
> structure, and you just call it in the generic driver at probe's time.
This is changing the device tree bindings for the generic driver.
Is this something Acceptable?
Peppe, are you Ok with such intrusive changes to the driver?
I did try few things before I sent this patch,
1> Doing it via AUXDATA which was discouraged by Arnd.
2> Doing it the way you suggested which did not fit in very neatly,
which looked like lot of SOC specific changes are added to generic driver.
3> Doing it as this patch, influenced by dwc3 code drivers/usb/dwc3/,
Which fitted in very neatly without touching the existing generic driver.
stmmac driver is a generic synopsis driver which ST has written the
driver, so I did not want to pollute this driver with ST specific glue
logic bindings.
Again, this could be irrelevant/confusing to other people who are using
this driver in there SoCs.
Only thing that bothers me with your suggestion is the changes to
generic driver.
>
> I don't really know what this syscon thing is either, but I think the
> reg <0x148 0x4> is related to that.
Yes, it is related to that.
>
> Why don't you pass it directly in the st,syscon property, to have
> something like <&syscfg_rear 0x148>?
This style was once discouraged by Arnd when I first sent pinctrl driver
for reasons that dt should not specify the offsets to registers.
>
> Maxime
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-12-02 12:48 ` srinivas kandagatla
0 siblings, 0 replies; 51+ messages in thread
From: srinivas kandagatla @ 2013-12-02 12:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
Thankyou for the comments.
On 29/11/13 19:37, Maxime Ripard wrote:
>> +
>> > +ethernet0: ethernet0{
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > + compatible = "st,stih415-dwmac";
>> > + reg = <0x148 0x4>;
>> > + resets = <&softreset STIH415_ETH0_SOFTRESET>;
>> > + st,syscon = <&syscfg_rear>;
>> > + st,tx-retime-src = "clk_125";
>> > + ranges;
>> > +
>> > + dwmac0:dwmac at fe810000 {
>> > + device_type = "network";
>> > + compatible = "snps,dwmac", "snps,dwmac-3.610";
>> > + reg = <0xfe810000 0x8000>;
>> > + interrupts = <0 147 0>;
>> > + interrupt-names = "macirq";
>> > + ...
>> > + };
>> > +};
> Sorry for stepping up so late, but I dont' think this is the right way
> to do it.
>
Not a issue.
> DT is to describe how the hardware is laid out in a system agnostic
> way, hence, it should not be impacted by the implementation details.
>
If "hardware is laid out" means at SoC level? Then I attempted to do
describe it in system agnostic way.
On ST SoCs "snps,dwmac" IP always has a hw glue layer on top of it.
> The fact that you use a glue to the dwmac driver *is* an
> implementation detail.
Glue layer described here is actually a hardware glue on ST SoCs.
>
> I think you'd rather have something like:
>
> dwmac0: ethernet at fe810000 {
> compatible = "st,stih415-dwmac";
> reg = <0xfe810000 0x8000 0x148 0x4>;
> resets = <&softreset STIH415_ETH0_SOFTRESET>;
> st,syscon = <&syscfg_rear>;
> st,tx-retime-src = "clk_125";
> interrupts = <0 147 0>;
> interrupt-names = "macirq";Am happy to go with
> ...
> };
>
> Then, the driver can have its init functions associated to the
> compatible you're using, through the .data field of the of_device_id
> structure, and you just call it in the generic driver at probe's time.
This is changing the device tree bindings for the generic driver.
Is this something Acceptable?
Peppe, are you Ok with such intrusive changes to the driver?
I did try few things before I sent this patch,
1> Doing it via AUXDATA which was discouraged by Arnd.
2> Doing it the way you suggested which did not fit in very neatly,
which looked like lot of SOC specific changes are added to generic driver.
3> Doing it as this patch, influenced by dwc3 code drivers/usb/dwc3/,
Which fitted in very neatly without touching the existing generic driver.
stmmac driver is a generic synopsis driver which ST has written the
driver, so I did not want to pollute this driver with ST specific glue
logic bindings.
Again, this could be irrelevant/confusing to other people who are using
this driver in there SoCs.
Only thing that bothers me with your suggestion is the changes to
generic driver.
>
> I don't really know what this syscon thing is either, but I think the
> reg <0x148 0x4> is related to that.
Yes, it is related to that.
>
> Why don't you pass it directly in the st,syscon property, to have
> something like <&syscfg_rear 0x148>?
This style was once discouraged by Arnd when I first sent pinctrl driver
for reasons that dt should not specify the offsets to registers.
>
> Maxime
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
2013-12-02 12:48 ` srinivas kandagatla
@ 2013-12-06 18:37 ` Maxime Ripard
-1 siblings, 0 replies; 51+ messages in thread
From: Maxime Ripard @ 2013-12-06 18:37 UTC (permalink / raw)
To: srinivas kandagatla
Cc: linux-arm-kernel, netdev, Rob Herring, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Rob Landley, Russell King,
Stuart Menefy, Pavel Machek, Rafael J. Wysocki, Len Brown,
stephen.gallimore, Greg Kroah-Hartman, Giuseppe Cavallaro,
Grant Likely, devicetree, linux-doc, linux-kernel, kernel,
linux-pm
[-- Attachment #1: Type: text/plain, Size: 3218 bytes --]
Hi Srinivas,
On Mon, Dec 02, 2013 at 12:48:24PM +0000, srinivas kandagatla wrote:
> Hi Maxime,
>
> Thankyou for the comments.
>
> On 29/11/13 19:37, Maxime Ripard wrote:
> >> +
> >> > +ethernet0: ethernet0{
> >> > + #address-cells = <1>;
> >> > + #size-cells = <1>;
> >> > + compatible = "st,stih415-dwmac";
> >> > + reg = <0x148 0x4>;
> >> > + resets = <&softreset STIH415_ETH0_SOFTRESET>;
> >> > + st,syscon = <&syscfg_rear>;
> >> > + st,tx-retime-src = "clk_125";
> >> > + ranges;
> >> > +
> >> > + dwmac0:dwmac@fe810000 {
> >> > + device_type = "network";
> >> > + compatible = "snps,dwmac", "snps,dwmac-3.610";
> >> > + reg = <0xfe810000 0x8000>;
> >> > + interrupts = <0 147 0>;
> >> > + interrupt-names = "macirq";
> >> > + ...
> >> > + };
> >> > +};
> > Sorry for stepping up so late, but I dont' think this is the right way
> > to do it.
> >
> Not a issue.
>
> > DT is to describe how the hardware is laid out in a system agnostic
> > way, hence, it should not be impacted by the implementation details.
> >
> If "hardware is laid out" means at SoC level? Then I attempted to do
> describe it in system agnostic way.
>
> On ST SoCs "snps,dwmac" IP always has a hw glue layer on top of it.
>
> > The fact that you use a glue to the dwmac driver *is* an
> > implementation detail.
>
> Glue layer described here is actually a hardware glue on ST SoCs.
Ho, ok, it makes sense then :)
Sorry for the noise.
> > I think you'd rather have something like:
> >
> > dwmac0: ethernet@fe810000 {
> > compatible = "st,stih415-dwmac";
> > reg = <0xfe810000 0x8000 0x148 0x4>;
> > resets = <&softreset STIH415_ETH0_SOFTRESET>;
> > st,syscon = <&syscfg_rear>;
> > st,tx-retime-src = "clk_125";
> > interrupts = <0 147 0>;
> > interrupt-names = "macirq";Am happy to go with
> > ...
> > };
> >
> > Then, the driver can have its init functions associated to the
> > compatible you're using, through the .data field of the of_device_id
> > structure, and you just call it in the generic driver at probe's time.
>
> This is changing the device tree bindings for the generic driver.
> Is this something Acceptable?
It really depends. As long as these are based on new compatibles, and
you require these new properties only for this new compatible, it's
fine most of the time.
> Peppe, are you Ok with such intrusive changes to the driver?
>
> I did try few things before I sent this patch,
>
> 1> Doing it via AUXDATA which was discouraged by Arnd.
>
> 2> Doing it the way you suggested which did not fit in very neatly,
> which looked like lot of SOC specific changes are added to generic driver.
>
> 3> Doing it as this patch, influenced by dwc3 code drivers/usb/dwc3/,
> Which fitted in very neatly without touching the existing generic driver.
>
> stmmac driver is a generic synopsis driver which ST has written the
> driver, so I did not want to pollute this driver with ST specific glue
> logic bindings.
Yeah, I didn't know that. My apologies.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver.
@ 2013-12-06 18:37 ` Maxime Ripard
0 siblings, 0 replies; 51+ messages in thread
From: Maxime Ripard @ 2013-12-06 18:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Srinivas,
On Mon, Dec 02, 2013 at 12:48:24PM +0000, srinivas kandagatla wrote:
> Hi Maxime,
>
> Thankyou for the comments.
>
> On 29/11/13 19:37, Maxime Ripard wrote:
> >> +
> >> > +ethernet0: ethernet0{
> >> > + #address-cells = <1>;
> >> > + #size-cells = <1>;
> >> > + compatible = "st,stih415-dwmac";
> >> > + reg = <0x148 0x4>;
> >> > + resets = <&softreset STIH415_ETH0_SOFTRESET>;
> >> > + st,syscon = <&syscfg_rear>;
> >> > + st,tx-retime-src = "clk_125";
> >> > + ranges;
> >> > +
> >> > + dwmac0:dwmac at fe810000 {
> >> > + device_type = "network";
> >> > + compatible = "snps,dwmac", "snps,dwmac-3.610";
> >> > + reg = <0xfe810000 0x8000>;
> >> > + interrupts = <0 147 0>;
> >> > + interrupt-names = "macirq";
> >> > + ...
> >> > + };
> >> > +};
> > Sorry for stepping up so late, but I dont' think this is the right way
> > to do it.
> >
> Not a issue.
>
> > DT is to describe how the hardware is laid out in a system agnostic
> > way, hence, it should not be impacted by the implementation details.
> >
> If "hardware is laid out" means at SoC level? Then I attempted to do
> describe it in system agnostic way.
>
> On ST SoCs "snps,dwmac" IP always has a hw glue layer on top of it.
>
> > The fact that you use a glue to the dwmac driver *is* an
> > implementation detail.
>
> Glue layer described here is actually a hardware glue on ST SoCs.
Ho, ok, it makes sense then :)
Sorry for the noise.
> > I think you'd rather have something like:
> >
> > dwmac0: ethernet at fe810000 {
> > compatible = "st,stih415-dwmac";
> > reg = <0xfe810000 0x8000 0x148 0x4>;
> > resets = <&softreset STIH415_ETH0_SOFTRESET>;
> > st,syscon = <&syscfg_rear>;
> > st,tx-retime-src = "clk_125";
> > interrupts = <0 147 0>;
> > interrupt-names = "macirq";Am happy to go with
> > ...
> > };
> >
> > Then, the driver can have its init functions associated to the
> > compatible you're using, through the .data field of the of_device_id
> > structure, and you just call it in the generic driver at probe's time.
>
> This is changing the device tree bindings for the generic driver.
> Is this something Acceptable?
It really depends. As long as these are based on new compatibles, and
you require these new properties only for this new compatible, it's
fine most of the time.
> Peppe, are you Ok with such intrusive changes to the driver?
>
> I did try few things before I sent this patch,
>
> 1> Doing it via AUXDATA which was discouraged by Arnd.
>
> 2> Doing it the way you suggested which did not fit in very neatly,
> which looked like lot of SOC specific changes are added to generic driver.
>
> 3> Doing it as this patch, influenced by dwc3 code drivers/usb/dwc3/,
> Which fitted in very neatly without touching the existing generic driver.
>
> stmmac driver is a generic synopsis driver which ST has written the
> driver, so I did not want to pollute this driver with ST specific glue
> logic bindings.
Yeah, I didn't know that. My apologies.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2013-12-07 10:05 UTC | newest]
Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-11-12 13:51 [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller srinivas.kandagatla
2013-11-12 13:51 ` srinivas.kandagatla at st.com
2013-11-12 13:51 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 01/10] drivers: reset: STi SoC system configuration reset controller support srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 02/10] drivers: reset: Reset controller driver for STiH415 srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 03/10] drivers: reset: Reset controller driver for STiH416 srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 04/10] drivers: reset: stih415: add softreset controller srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 05/10] drivers: reset: stih416: " srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 06/10] ARM: STi: Add reset controller support to mach-sti Kconfig srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 13:52 ` [PATCH RFC 07/10] PM / wakeup : Introduce device_child_may_wakeup srinivas.kandagatla
2013-11-12 13:52 ` srinivas.kandagatla at st.com
2013-11-12 13:52 ` srinivas.kandagatla
2013-11-12 14:20 ` Rafael J. Wysocki
2013-11-12 14:20 ` Rafael J. Wysocki
2013-11-12 14:09 ` srinivas kandagatla
2013-11-12 14:09 ` srinivas kandagatla
2013-11-12 14:09 ` srinivas kandagatla
2013-11-12 13:53 ` [PATCH RFC 08/10] net: stmmac:sti: Add STi SOC glue driver srinivas.kandagatla
2013-11-12 13:53 ` srinivas.kandagatla at st.com
2013-11-12 13:53 ` srinivas.kandagatla
2013-11-29 19:37 ` Maxime Ripard
2013-11-29 19:37 ` Maxime Ripard
2013-12-02 12:48 ` srinivas kandagatla
2013-12-02 12:48 ` srinivas kandagatla
2013-12-02 12:48 ` srinivas kandagatla
2013-12-06 18:37 ` Maxime Ripard
2013-12-06 18:37 ` Maxime Ripard
2013-11-12 13:53 ` [PATCH RFC 09/10] ARM: STi: Add STiH415 ethernet support srinivas.kandagatla
2013-11-12 13:53 ` srinivas.kandagatla at st.com
2013-11-12 13:53 ` srinivas.kandagatla
2013-11-12 13:53 ` [PATCH RFC 10/10] ARM: STi: Add STiH416 " srinivas.kandagatla
2013-11-12 13:53 ` srinivas.kandagatla at st.com
2013-11-12 13:53 ` srinivas.kandagatla
2013-11-19 5:28 ` [PATCH RFC 00/10] ARM: STi: Add dwmac glue and reset controller Giuseppe CAVALLARO
2013-11-19 5:28 ` Giuseppe CAVALLARO
2013-11-19 5:28 ` Giuseppe CAVALLARO
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