From: Tero Kristo <t-kristo@ti.com> To: linux-omap@vger.kernel.org, paul@pwsan.com, tony@atomide.com, nm@ti.com, rnayak@ti.com, bcousson@baylibre.com, mturquette@linaro.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCHv10 17/41] CLK: TI: add am33xx clock init file Date: Tue, 26 Nov 2013 10:05:58 +0200 [thread overview] Message-ID: <1385453182-24421-18-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1385453182-24421-1-git-send-email-t-kristo@ti.com> clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/clock.h | 1 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-33xx.c | 161 +++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 + 4 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clk-33xx.c diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b83fca6..1da9dc3 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -249,7 +249,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index f8ae4b5..7eb6f2b 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o dpll.o autoidle.o divider.o \ fixed-factor.o gate.o clockdomain.o \ composite.o mux.o apll.o +obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c new file mode 100644 index 0000000..776ee45 --- /dev/null +++ b/drivers/clk/ti/clk-33xx.c @@ -0,0 +1,161 @@ +/* + * AM33XX Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-provider.h> +#include <linux/clk/ti.h> + +static struct ti_dt_clk am33xx_clks[] = { + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK("cpu0", NULL, "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), + DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), + DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), + DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), + DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), + DT_CLK(NULL, "mmu_fck", "mmu_fck"), + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), + DT_CLK(NULL, "sha0_fck", "sha0_fck"), + DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), + DT_CLK(NULL, "timer3_fck", "timer3_fck"), + DT_CLK(NULL, "timer4_fck", "timer4_fck"), + DT_CLK(NULL, "timer5_fck", "timer5_fck"), + DT_CLK(NULL, "timer6_fck", "timer6_fck"), + DT_CLK(NULL, "timer7_fck", "timer7_fck"), + DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), + DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), + DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), + DT_CLK(NULL, "l3_gclk", "l3_gclk"), + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), + DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), + DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), + DT_CLK(NULL, "mmc_clk", "mmc_clk"), + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), + DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), + DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), + DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), + DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), + DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), + DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), + DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), + { .node_name = NULL }, +}; + +static const char *enable_init_clks[] = { + "dpll_ddr_m2_ck", + "dpll_mpu_m2_ck", + "l3_gclk", + "l4hs_gclk", + "l4fw_gclk", + "l4ls_gclk", + /* Required for external peripherals like, Audio codecs */ + "clkout2_ck", +}; + +int __init am33xx_dt_clk_init(void) +{ + struct clk *clk1, *clk2; + + ti_dt_clocks_register(am33xx_clks); + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ + + clk1 = clk_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_get_sys(NULL, "timer3_fck"); + clk_set_parent(clk2, clk1); + + clk2 = clk_get_sys(NULL, "timer6_fck"); + clk_set_parent(clk2, clk1); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk1 = clk_get_sys(NULL, "wdt1_fck"); + clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); + clk_set_parent(clk1, clk2); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 671c8af..f7287ef 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -226,6 +226,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -242,6 +243,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); int dra7xx_dt_clk_init(void); +int am33xx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: t-kristo@ti.com (Tero Kristo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv10 17/41] CLK: TI: add am33xx clock init file Date: Tue, 26 Nov 2013 10:05:58 +0200 [thread overview] Message-ID: <1385453182-24421-18-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1385453182-24421-1-git-send-email-t-kristo@ti.com> clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/clock.h | 1 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-33xx.c | 161 +++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 + 4 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clk-33xx.c diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b83fca6..1da9dc3 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -249,7 +249,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index f8ae4b5..7eb6f2b 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o dpll.o autoidle.o divider.o \ fixed-factor.o gate.o clockdomain.o \ composite.o mux.o apll.o +obj-$(CONFIG_SOC_AM33XX) += clk-33xx.o obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += clk-7xx.o diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c new file mode 100644 index 0000000..776ee45 --- /dev/null +++ b/drivers/clk/ti/clk-33xx.c @@ -0,0 +1,161 @@ +/* + * AM33XX Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc + * Tero Kristo (t-kristo at ti.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-provider.h> +#include <linux/clk/ti.h> + +static struct ti_dt_clk am33xx_clks[] = { + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK("cpu0", NULL, "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), + DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), + DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), + DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), + DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), + DT_CLK(NULL, "mmu_fck", "mmu_fck"), + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), + DT_CLK(NULL, "sha0_fck", "sha0_fck"), + DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), + DT_CLK(NULL, "timer3_fck", "timer3_fck"), + DT_CLK(NULL, "timer4_fck", "timer4_fck"), + DT_CLK(NULL, "timer5_fck", "timer5_fck"), + DT_CLK(NULL, "timer6_fck", "timer6_fck"), + DT_CLK(NULL, "timer7_fck", "timer7_fck"), + DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), + DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), + DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), + DT_CLK(NULL, "l3_gclk", "l3_gclk"), + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), + DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), + DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), + DT_CLK(NULL, "mmc_clk", "mmc_clk"), + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), + DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), + DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), + DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), + DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), + DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), + DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), + DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), + { .node_name = NULL }, +}; + +static const char *enable_init_clks[] = { + "dpll_ddr_m2_ck", + "dpll_mpu_m2_ck", + "l3_gclk", + "l4hs_gclk", + "l4fw_gclk", + "l4ls_gclk", + /* Required for external peripherals like, Audio codecs */ + "clkout2_ck", +}; + +int __init am33xx_dt_clk_init(void) +{ + struct clk *clk1, *clk2; + + ti_dt_clocks_register(am33xx_clks); + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ + + clk1 = clk_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_get_sys(NULL, "timer3_fck"); + clk_set_parent(clk2, clk1); + + clk2 = clk_get_sys(NULL, "timer6_fck"); + clk_set_parent(clk2, clk1); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk1 = clk_get_sys(NULL, "wdt1_fck"); + clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); + clk_set_parent(clk1, clk2); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 671c8af..f7287ef 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -226,6 +226,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -242,6 +243,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); int dra7xx_dt_clk_init(void); +int am33xx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- 1.7.9.5
next prev parent reply other threads:[~2013-11-26 8:05 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-11-26 8:05 [PATCHv10 00/41] ARM: TI SoC clock DT conversion Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 01/41] clk: add support for platform specific clock I/O wrapper functions Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-15 0:48 ` Mike Turquette 2013-12-15 0:48 ` Mike Turquette 2013-12-16 8:06 ` Tero Kristo 2013-12-16 8:06 ` Tero Kristo 2013-12-17 12:34 ` Paul Walmsley 2013-12-17 12:34 ` Paul Walmsley 2013-12-18 3:33 ` Paul Walmsley 2013-12-18 3:33 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 02/41] CLK: TI: add DT alias clock registration mechanism Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 03/41] CLK: ti: add init support for clock IP blocks Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 8:14 ` Paul Walmsley 2013-12-17 8:14 ` Paul Walmsley 2013-12-17 8:21 ` Tero Kristo 2013-12-17 8:21 ` Tero Kristo 2013-12-17 8:32 ` Paul Walmsley 2013-12-17 8:32 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 04/41] CLK: TI: Add DPLL clock support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 8:37 ` Paul Walmsley 2013-12-17 8:37 ` Paul Walmsley 2013-12-17 8:40 ` Paul Walmsley 2013-12-17 8:40 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 05/41] CLK: TI: add autoidle support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 06/41] clk: ti: add composite clock support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 07/41] CLK: ti: add support for ti divider-clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 08/41] clk: ti: add support for TI fixed factor clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 09/41] CLK: TI: add support for gate clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 11/41] clk: ti: add support for basic mux clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 12/41] CLK: TI: add omap4 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 9:30 ` Paul Walmsley 2013-12-17 9:30 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 14/41] CLK: TI: omap5: Initialize USB_DPLL at boot Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 15/41] CLK: TI: DRA7: Add APLL support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:51 ` Alexander Aring 2013-11-26 8:51 ` Alexander Aring 2013-11-29 19:00 ` Tero Kristo 2013-11-29 19:00 ` Tero Kristo 2013-11-29 20:52 ` Alexander Aring 2013-11-29 20:52 ` Alexander Aring 2013-11-26 8:05 ` [PATCHv10 16/41] CLK: TI: add dra7 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` Tero Kristo [this message] 2013-11-26 8:05 ` [PATCHv10 17/41] CLK: TI: add am33xx " Tero Kristo 2013-11-26 8:06 ` [PATCHv10 19/41] CLK: TI: add omap3 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 20/41] CLK: TI: add am43xx " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 21/41] ARM: dts: omap4 clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:44 ` Paul Walmsley 2013-12-17 9:44 ` Paul Walmsley 2013-12-17 9:57 ` Tero Kristo 2013-12-17 9:57 ` Tero Kristo 2013-12-20 11:15 ` Paul Walmsley 2013-12-20 11:15 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 23/41] ARM: dts: dra7 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:46 ` Paul Walmsley 2013-12-17 9:46 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 24/41] ARM: dts: clk: Add apll related clocks Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 26/41] ARM: dts: DRA7: Add PCIe related clock nodes Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 27/41] ARM: dts: am33xx clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:48 ` Paul Walmsley 2013-12-17 9:48 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 28/41] ARM: dts: omap3 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:50 ` Paul Walmsley 2013-12-17 9:50 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 29/41] ARM: dts: AM35xx: use DT " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 30/41] ARM: dts: am43xx " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:52 ` Paul Walmsley 2013-12-17 9:52 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 31/41] ARM: OMAP2+: clock: add support for regmap Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 17:40 ` Tony Lindgren 2013-11-26 17:40 ` Tony Lindgren 2013-11-27 9:08 ` Tero Kristo 2013-11-27 9:08 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 32/41] ARM: OMAP2+: clock: use driver API instead of direct memory read/write Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 33/41] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 34/41] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 35/41] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT Tero Kristo 2013-11-26 8:06 ` Tero Kristo [not found] ` <1385453182-24421-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org> 2013-11-26 8:05 ` [PATCHv10 10/41] CLK: TI: add support for clockdomain binding Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-15 4:23 ` Mike Turquette 2013-12-15 4:23 ` Mike Turquette 2013-12-16 8:13 ` Tero Kristo 2013-12-16 8:13 ` Tero Kristo 2013-12-18 3:07 ` Mike Turquette 2013-12-18 3:07 ` Mike Turquette 2013-11-26 8:05 ` [PATCHv10 13/41] CLK: TI: add omap5 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 18/41] CLK: TI: add interface clock support for OMAP3 Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 22/41] ARM: dts: omap5 clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-16 10:51 ` Paul Walmsley 2013-12-16 10:51 ` Paul Walmsley 2013-12-16 10:57 ` Tero Kristo 2013-12-16 10:57 ` Tero Kristo 2013-12-17 9:46 ` Paul Walmsley 2013-12-17 9:46 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 25/41] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 36/41] ARM: OMAP2+: io: use new clock init API Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-28 0:49 ` [PATCHv10 00/41] ARM: TI SoC clock DT conversion Nishanth Menon 2013-11-28 0:49 ` Nishanth Menon [not found] ` <52969313.6090207-l0cyMroinI0@public.gmane.org> 2013-11-28 18:58 ` Paul Walmsley 2013-11-28 18:58 ` Paul Walmsley 2013-11-29 17:12 ` Tony Lindgren 2013-11-29 17:12 ` Tony Lindgren 2013-11-29 18:59 ` Tero Kristo 2013-11-29 18:59 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 37/41] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 38/41] ARM: OMAP: DRA7: Enable clock init Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 39/41] ARM: AM43xx: " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 40/41] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 41/41] ARM: OMAP3: use DT clock init if DT data is available Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 17:44 ` Tony Lindgren 2013-11-26 17:44 ` Tony Lindgren 2013-11-27 9:06 ` Tero Kristo 2013-11-27 9:06 ` Tero Kristo 2013-11-26 17:57 ` [PATCHv10 00/41] ARM: TI SoC clock DT conversion Tony Lindgren 2013-11-26 17:57 ` Tony Lindgren 2013-12-15 0:51 ` Mike Turquette 2013-12-15 0:51 ` Mike Turquette 2013-12-15 4:35 ` Mike Turquette 2013-12-15 4:35 ` Mike Turquette 2013-12-16 8:12 ` Tero Kristo 2013-12-16 8:12 ` Tero Kristo 2013-12-20 16:10 ` Felipe Balbi 2013-12-20 16:10 ` Felipe Balbi
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