* [U-Boot] [PATCH] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
@ 2013-12-02 4:12 Po Liu
2013-12-05 6:18 ` [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
0 siblings, 1 reply; 34+ messages in thread
From: Po Liu @ 2013-12-02 4:12 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 4kB size tlb for minimal SPL image;
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C291PCIE_NAND/C292PCIE_NAND/C293PCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++--
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 73 ++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 22 +++++-
boards.cfg | 1 +
drivers/mtd/nand/fsl_ifc_spl.c | 29 +++++--
include/configs/C29XPCIE.h | 129 +++++++++++++++++++++++++++++++-
9 files changed, 330 insertions(+), 19 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..7bc8ce1
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,73 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+ puts("\nTertiary program loader running in sram...");
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..7e7726d
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..11f8a37 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +53,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +72,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
+ && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +83,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index e742746..b5f4750 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -784,6 +784,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9fa5ccb..5e58614 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
+#ifdef CONFIG_TPL_BUILD
+void nand_spl_load_image(uint32_t offs, int uboot_size, void *vdst)
+#else
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,9 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+#ifdef CONFIG_TPL_BUILD
+ char *dst = vdst;
+#endif
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -211,6 +218,15 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
}
/*
++ * Defines a static function nand_load_image() here, because non-static makes
++ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
++ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, dst) \
+ nand_load(offs, uboot_size, dst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index bb15745..d0a5010 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,48 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +73,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +178,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +235,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +267,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +299,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +339,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +385,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +475,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2013-12-02 4:12 [U-Boot] [PATCH] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2013-12-05 6:18 ` Po Liu
2013-12-05 6:19 ` [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2013-12-07 1:33 ` [U-Boot] [PATCH v2 " Scott Wood
0 siblings, 2 replies; 34+ messages in thread
From: Po Liu @ 2013-12-05 6:18 UTC (permalink / raw)
To: u-boot
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_IFC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
drivers/mtd/nand/fsl_ifc_spl.c | 29 +++++++++++++++++++++++------
spl/Makefile | 1 +
3 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..93303b4 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
+#ifdef CONFIG_TPL_BUILD
+void nand_spl_load_image(uint32_t offs, int uboot_size, void *vdst)
+#else
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,9 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+#ifdef CONFIG_TPL_BUILD
+ char *dst = vdst;
+#endif
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -211,6 +218,15 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
}
/*
++ * Defines a static function nand_load_image() here, because non-static makes
++ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
++ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, dst) \
+ nand_load(offs, uboot_size, dst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/spl/Makefile b/spl/Makefile
index 2a787af..908af35 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -79,6 +79,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_IFC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
--
1.8.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-05 6:18 ` [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
@ 2013-12-05 6:19 ` Po Liu
2013-12-07 1:21 ` Scott Wood
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-07 1:33 ` [U-Boot] [PATCH v2 " Scott Wood
1 sibling, 2 replies; 34+ messages in thread
From: Po Liu @ 2013-12-05 6:19 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 8kB size tlb for minimal SPL image;
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate the public code and c29xpcie board code;
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 73 ++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 22 +++++-
boards.cfg | 1 +
include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++-
7 files changed, 300 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..7bc8ce1
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,73 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+ puts("\nTertiary program loader running in sram...");
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..7e7726d
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..11f8a37 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +53,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +72,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
+ && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +83,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 114cc86..adcbbdf 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -784,6 +784,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..7d2b1a5 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_IFC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +74,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +179,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +236,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +340,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +386,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +476,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-05 6:19 ` [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2013-12-07 1:21 ` Scott Wood
2013-12-09 5:40 ` Prabhakar Kushwaha
` (2 more replies)
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
1 sibling, 3 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-07 1:21 UTC (permalink / raw)
To: u-boot
On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
> diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
> new file mode 100644
> index 0000000..7bc8ce1
> --- /dev/null
> +++ b/board/freescale/c29xpcie/spl.c
> @@ -0,0 +1,73 @@
> +/* Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <ns16550.h>
> +#include <malloc.h>
> +#include <mmc.h>
> +#include <nand.h>
> +#include <i2c.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +ulong get_effective_memsize(void)
> +{
> + return CONFIG_SYS_L2_SIZE;
> +}
> +
> +void board_init_f(ulong bootflag)
> +{
> + u32 plat_ratio;
> + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> +
> + console_init_f();
> +
> + /* initialize selected port with appropriate baud rate */
> + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
> + plat_ratio >>= 1;
> + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
> +
> + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
> + gd->bus_clk / 16 / CONFIG_BAUDRATE);
> +
> + /* copy code to RAM and jump to it - this should not return */
> + /* NOTE - code has to be copied out of NAND buffer before
> + * other blocks can be read.
> + */
> + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
> +}
> +
> +void board_init_r(gd_t *gd, ulong dest_addr)
> +{
> + /* Pointer is writable since we allocated a register for it */
> + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
> + bd_t *bd;
> +
> + memset(gd, 0, sizeof(gd_t));
> + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
> + memset(bd, 0, sizeof(bd_t));
> + gd->bd = bd;
> + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
> + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
> +
> + probecpu();
> + get_clocks();
> + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
> + CONFIG_SPL_RELOC_MALLOC_SIZE);
> +
> + /* relocate environment function pointers etc. */
> + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> + (uchar *)CONFIG_ENV_ADDR);
> + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
> + gd->env_valid = 1;
> +
> + i2c_init_all();
> +
> + gd->ram_size = initdram(0);
> +
> + puts("\nTertiary program loader running in sram...");
Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or was it
a copy/paste error that you added things to the board config file for
SD/SPI (after all, the subject line says it's a NAND patch)?
> +void board_init_r(gd_t *gd, ulong dest_addr)
> +{
> + puts("\nSecond program loader running in sram...");
I see that this isn't new to this patch, but we ought to be consistent
and either change this to "secondary", or change "tertiary" to "third".
It's also probably too verbose... Simply saying "SPL\n" or "TPL\n"
would suffice to indicate progress and verify that console output is
working (if nothing is printed, then that path doesn't get tested in the
absence of a load error).
> diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
> index 84844ee..11f8a37 100644
> --- a/board/freescale/c29xpcie/tlb.c
> +++ b/board/freescale/c29xpcie/tlb.c
> @@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
> 0, 0, BOOKE_PAGESZ_4K, 0),
>
> /* TLB 1 */
> +#ifdef CONFIG_SPL_NAND_MINIMAL
> + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 10, BOOKE_PAGESZ_4K, 1),
> + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + 0, 11, BOOKE_PAGESZ_4K, 1),
> +#endif
CONFIG_SPL_NAND_MINIMAL should not exist. It was introduced by accident
after a different approach was chosen in patch review (and even then,
this wasn't what it meant).
Prabhakar, why did you extend that to other uses? Why are both entries
ifdeffed here, but only the 0xffffe000 entry on existing boards?
If this needs to be ifdeffed (and it probably does, if only to avoid
possible speculative instruction fetches), use (and document)
CONFIG_SPL_NAND_BOOT.
> SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> 0, 5, BOOKE_PAGESZ_64K, 1),
No.
> SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
> @@ -61,7 +72,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
> MAS3_SX|MAS3_SW|MAS3_SR, 0,
> 0, 7, BOOKE_PAGESZ_256K, 1),
>
> -#ifdef CONFIG_SYS_RAMBOOT
> +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
> + && !defined(CONFIG_SPL_COMMON_INIT_DDR))
> SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> CONFIG_SYS_DDR_SDRAM_BASE,
> MAS3_SX|MAS3_SW|MAS3_SR, 0,
This will have the result of mapping DDR in the SPL where it's not used,
but not in the TPL where it is.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2013-12-05 6:18 ` [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-05 6:19 ` [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2013-12-07 1:33 ` Scott Wood
1 sibling, 0 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-07 1:33 UTC (permalink / raw)
To: u-boot
On Thu, 2013-12-05 at 14:18 +0800, Po Liu wrote:
> diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
> index 9de327b..93303b4 100644
> --- a/drivers/mtd/nand/fsl_ifc_spl.c
> +++ b/drivers/mtd/nand/fsl_ifc_spl.c
> @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
> return __raw_readw((u16 *)marker) != 0xffff;
> }
>
> +#ifdef CONFIG_TPL_BUILD
> +void nand_spl_load_image(uint32_t offs, int uboot_size, void *vdst)
> +#else
> static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
> +#endif
> {
> struct fsl_ifc *ifc = IFC_BASE_ADDR;
> uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
> @@ -105,6 +109,9 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
>
> int sram_addr;
> int pg_no;
> +#ifdef CONFIG_TPL_BUILD
> + char *dst = vdst;
> +#endif
Use uchar to be consistent.
> /* Get NAND Flash configuration */
> csor = CONFIG_SYS_NAND_CSOR;
> @@ -211,6 +218,15 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
> }
>
> /*
> ++ * Defines a static function nand_load_image() here, because non-static makes
> ++ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
> ++ */
> +#ifndef CONFIG_TPL_BUILD
Too many pluses -- did you copy and paste from a patch?
> diff --git a/spl/Makefile b/spl/Makefile
> index 2a787af..908af35 100644
> --- a/spl/Makefile
> +++ b/spl/Makefile
> @@ -79,6 +79,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
> LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
> drivers/power/pmic/
> LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
> +LIBS-$(CONFIG_SPL_IFC_SUPPORT) += drivers/misc/
Make a CONFIG_SPL_DRIVERS_MISC_SUPPORT instead.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-07 1:21 ` Scott Wood
@ 2013-12-09 5:40 ` Prabhakar Kushwaha
2013-12-09 17:51 ` Scott Wood
[not found] ` <c957f7e802e245488c0c0e0fc0f425ed@DM2PR03MB317.namprd03.prod.outlook.com>
[not found] ` <ce05f24a72e0474f82d7f99c215353e6@DM2PR03MB317.namprd03.prod.outlook.com>
2 siblings, 1 reply; 34+ messages in thread
From: Prabhakar Kushwaha @ 2013-12-09 5:40 UTC (permalink / raw)
To: u-boot
On 12/7/2013 6:51 AM, Scott Wood wrote:
> On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
>> diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
>> new file mode 100644
>> index 0000000..7bc8ce1
>> --- /dev/null
>> +++ b/board/freescale/c29xpcie/spl.c
>> @@ -0,0 +1,73 @@
>> +/* Copyright 2013 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <ns16550.h>
>> +#include <malloc.h>
>> +#include <mmc.h>
>> +#include <nand.h>
>> +#include <i2c.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +ulong get_effective_memsize(void)
>> +{
>> + return CONFIG_SYS_L2_SIZE;
>> +}
>> +
>> +void board_init_f(ulong bootflag)
>> +{
>> + u32 plat_ratio;
>> + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
>> +
>> + console_init_f();
>> +
>> + /* initialize selected port with appropriate baud rate */
>> + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
>> + plat_ratio >>= 1;
>> + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
>> +
>> + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
>> + gd->bus_clk / 16 / CONFIG_BAUDRATE);
>> +
>> + /* copy code to RAM and jump to it - this should not return */
>> + /* NOTE - code has to be copied out of NAND buffer before
>> + * other blocks can be read.
>> + */
>> + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
>> +}
>> +
>> +void board_init_r(gd_t *gd, ulong dest_addr)
>> +{
>> + /* Pointer is writable since we allocated a register for it */
>> + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
>> + bd_t *bd;
>> +
>> + memset(gd, 0, sizeof(gd_t));
>> + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
>> + memset(bd, 0, sizeof(bd_t));
>> + gd->bd = bd;
>> + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
>> + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
>> +
>> + probecpu();
>> + get_clocks();
>> + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
>> + CONFIG_SPL_RELOC_MALLOC_SIZE);
>> +
>> + /* relocate environment function pointers etc. */
>> + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
>> + (uchar *)CONFIG_ENV_ADDR);
>> + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
>> + gd->env_valid = 1;
>> +
>> + i2c_init_all();
>> +
>> + gd->ram_size = initdram(0);
>> +
>> + puts("\nTertiary program loader running in sram...");
> Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or was it
> a copy/paste error that you added things to the board config file for
> SD/SPI (after all, the subject line says it's a NAND patch)?
>
>> +void board_init_r(gd_t *gd, ulong dest_addr)
>> +{
>> + puts("\nSecond program loader running in sram...");
> I see that this isn't new to this patch, but we ought to be consistent
> and either change this to "secondary", or change "tertiary" to "third".
>
> It's also probably too verbose... Simply saying "SPL\n" or "TPL\n"
> would suffice to indicate progress and verify that console output is
> working (if nothing is printed, then that path doesn't get tested in the
> absence of a load error).
>
>> diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
>> index 84844ee..11f8a37 100644
>> --- a/board/freescale/c29xpcie/tlb.c
>> +++ b/board/freescale/c29xpcie/tlb.c
>> @@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
>> 0, 0, BOOKE_PAGESZ_4K, 0),
>>
>> /* TLB 1 */
>> +#ifdef CONFIG_SPL_NAND_MINIMAL
>> + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
>> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>> + 0, 10, BOOKE_PAGESZ_4K, 1),
>> + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
>> + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>> + 0, 11, BOOKE_PAGESZ_4K, 1),
>> +#endif
> CONFIG_SPL_NAND_MINIMAL should not exist. It was introduced by accident
> after a different approach was chosen in patch review (and even then,
> this wasn't what it meant).
I was not aware of this. My mistake :(
> Prabhakar, why did you extend that to other uses? Why are both entries
> ifdeffed here, but only the 0xffffe000 entry on existing boards?
both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
not have this.
i dont think NOR boot tested after this patch. NOR boot will not work
after applying this patch.
> If this needs to be ifdeffed (and it probably does, if only to avoid
> possible speculative instruction fetches), use (and document)
> CONFIG_SPL_NAND_BOOT.
Yes, I will suggest to have CONFIG_SPL_NAND_BOOT instead of
CONFIG_SPL_NAND_MINIMAL.
I will fix for p1010rdb, bsc9131rdb, bsc9132qds.
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-09 5:40 ` Prabhakar Kushwaha
@ 2013-12-09 17:51 ` Scott Wood
2013-12-10 6:07 ` Prabhakar Kushwaha
0 siblings, 1 reply; 34+ messages in thread
From: Scott Wood @ 2013-12-09 17:51 UTC (permalink / raw)
To: u-boot
On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
> On 12/7/2013 6:51 AM, Scott Wood wrote:
> > Prabhakar, why did you extend that to other uses? Why are both entries
> > ifdeffed here, but only the 0xffffe000 entry on existing boards?
>
> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
> not have this.
> i dont think NOR boot tested after this patch. NOR boot will not work
> after applying this patch.
So what happens if there's a speculative access to the non-ifdeffed
0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
SD/SPI...)?
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-09 17:51 ` Scott Wood
@ 2013-12-10 6:07 ` Prabhakar Kushwaha
2013-12-10 18:20 ` Scott Wood
0 siblings, 1 reply; 34+ messages in thread
From: Prabhakar Kushwaha @ 2013-12-10 6:07 UTC (permalink / raw)
To: u-boot
On 12/9/2013 11:21 PM, Scott Wood wrote:
> On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
>> On 12/7/2013 6:51 AM, Scott Wood wrote:
>>> Prabhakar, why did you extend that to other uses? Why are both entries
>>> ifdeffed here, but only the 0xffffe000 entry on existing boards?
>> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
>> not have this.
>> i dont think NOR boot tested after this patch. NOR boot will not work
>> after applying this patch.
> So what happens if there's a speculative access to the non-ifdeffed
> 0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
> SD/SPI...)?
>
>
If I understand the question correctly,
Ideally ramboot, SPL payload, SD/SPI should not make access to this
address. They assumed to be running from DDR whose TLB has already been
created by IBR, or First stage boot loader.
do you see any such requirement
Regards,
Pabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-10 6:07 ` Prabhakar Kushwaha
@ 2013-12-10 18:20 ` Scott Wood
[not found] ` <5d27987f1d694ae9977cba2e8a78d843@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 6:40 ` Prabhakar Kushwaha
0 siblings, 2 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-10 18:20 UTC (permalink / raw)
To: u-boot
On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
> On 12/9/2013 11:21 PM, Scott Wood wrote:
> > On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
> >> On 12/7/2013 6:51 AM, Scott Wood wrote:
> >>> Prabhakar, why did you extend that to other uses? Why are both entries
> >>> ifdeffed here, but only the 0xffffe000 entry on existing boards?
> >> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
> >> not have this.
> >> i dont think NOR boot tested after this patch. NOR boot will not work
> >> after applying this patch.
> > So what happens if there's a speculative access to the non-ifdeffed
> > 0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
> > SD/SPI...)?
> >
> >
> If I understand the question correctly,
> Ideally ramboot, SPL payload, SD/SPI should not make access to this
> address. They assumed to be running from DDR whose TLB has already been
> created by IBR, or First stage boot loader.
Speculative accesses don't come (directly) from software. They are
initiated by the hardware and are not predictable.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <c957f7e802e245488c0c0e0fc0f425ed@DM2PR03MB317.namprd03.prod.outlook.com>
@ 2013-12-11 2:46 ` Po.Liu at freescale.com
2013-12-13 21:22 ` Scott Wood
0 siblings, 1 reply; 34+ messages in thread
From: Po.Liu at freescale.com @ 2013-12-11 2:46 UTC (permalink / raw)
To: u-boot
Sorry for late reply since the email system crash.
> -----Original Message-----
> From: Scott Wood [mailto:scottwood at freescale.com]
> Sent: Saturday, December 07, 2013 9:22 AM
> To: Liu Po-B43644
> Cc: u-boot at lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579
> Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot
> support base on TPL/SPL
>
> On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
> > diff --git a/board/freescale/c29xpcie/spl.c
> > b/board/freescale/c29xpcie/spl.c new file mode 100644 index
> > 0000000..7bc8ce1
> > --- /dev/null
> > +++ b/board/freescale/c29xpcie/spl.c
> > @@ -0,0 +1,73 @@
> > +/* Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <ns16550.h>
> > +#include <malloc.h>
> > +#include <mmc.h>
> > +#include <nand.h>
> > +#include <i2c.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +ulong get_effective_memsize(void)
> > +{
> > + return CONFIG_SYS_L2_SIZE;
> > +}
> > +
> > +void board_init_f(ulong bootflag)
> > +{
> > + u32 plat_ratio;
> > + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> > +
> > + console_init_f();
> > +
> > + /* initialize selected port with appropriate baud rate */
> > + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
> > + plat_ratio >>= 1;
> > + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
> > +
> > + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
> > + gd->bus_clk / 16 / CONFIG_BAUDRATE);
> > +
> > + /* copy code to RAM and jump to it - this should not return */
> > + /* NOTE - code has to be copied out of NAND buffer before
> > + * other blocks can be read.
> > + */
> > + relocate_code(CONFIG_SPL_RELOC_STACK, 0,
> > +CONFIG_SPL_RELOC_TEXT_BASE); }
> > +
> > +void board_init_r(gd_t *gd, ulong dest_addr) {
> > + /* Pointer is writable since we allocated a register for it */
> > + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
> > + bd_t *bd;
> > +
> > + memset(gd, 0, sizeof(gd_t));
> > + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
> > + memset(bd, 0, sizeof(bd_t));
> > + gd->bd = bd;
> > + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
> > + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
> > +
> > + probecpu();
> > + get_clocks();
> > + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
> > + CONFIG_SPL_RELOC_MALLOC_SIZE);
> > +
> > + /* relocate environment function pointers etc. */
> > + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> > + (uchar *)CONFIG_ENV_ADDR);
> > + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
> > + gd->env_valid = 1;
> > +
> > + i2c_init_all();
> > +
> > + gd->ram_size = initdram(0);
> > +
> > + puts("\nTertiary program loader running in sram...");
>
> Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or was it
> a copy/paste error that you added things to the board config file for
> SD/SPI (after all, the subject line says it's a NAND patch)?
>
Yes, I assume this patch only for NAND boot for C29XPCIE.
> > +void board_init_r(gd_t *gd, ulong dest_addr) {
> > + puts("\nSecond program loader running in sram...");
>
> I see that this isn't new to this patch, but we ought to be consistent
> and either change this to "secondary", or change "tertiary" to "third".
>
> It's also probably too verbose... Simply saying "SPL\n" or "TPL\n"
> would suffice to indicate progress and verify that console output is
> working (if nothing is printed, then that path doesn't get tested in the
> absence of a load error).
>
> > diff --git a/board/freescale/c29xpcie/tlb.c
> > b/board/freescale/c29xpcie/tlb.c index 84844ee..11f8a37 100644
> > --- a/board/freescale/c29xpcie/tlb.c
> > +++ b/board/freescale/c29xpcie/tlb.c
> > @@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
> > 0, 0, BOOKE_PAGESZ_4K, 0),
> >
> > /* TLB 1 */
> > +#ifdef CONFIG_SPL_NAND_MINIMAL
> > + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > + 0, 10, BOOKE_PAGESZ_4K, 1),
> > + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
> > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > + 0, 11, BOOKE_PAGESZ_4K, 1),
> > +#endif
>
> CONFIG_SPL_NAND_MINIMAL should not exist. It was introduced by accident
> after a different approach was chosen in patch review (and even then,
> this wasn't what it meant).
>
> Prabhakar, why did you extend that to other uses? Why are both entries
> ifdeffed here, but only the 0xffffe000 entry on existing boards?
>
> If this needs to be ifdeffed (and it probably does, if only to avoid
> possible speculative instruction fetches), use (and document)
> CONFIG_SPL_NAND_BOOT.
I'll replace the CONFIG_SPL_NAND_MINIMAL with CONFIG_SPL_NAND_BOOT
>
> > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
> > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > 0, 5, BOOKE_PAGESZ_64K, 1),
>
> No.
>
> > SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@
> > struct fsl_e_tlb_entry tlb_table[] = {
> > MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > 0, 7, BOOKE_PAGESZ_256K, 1),
> >
> > -#ifdef CONFIG_SYS_RAMBOOT
> > +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
> > + && !defined(CONFIG_SPL_COMMON_INIT_DDR))
> > SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> > CONFIG_SYS_DDR_SDRAM_BASE,
> > MAS3_SX|MAS3_SW|MAS3_SR, 0,
>
> This will have the result of mapping DDR in the SPL where it's not used,
> but not in the TPL where it is.
Just define:
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) ?
I think code load image to SRAM from NAND for SPL and DDR do not need to be allocate.
>
> -Scott
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <5d27987f1d694ae9977cba2e8a78d843@DM2PR03MB317.namprd03.prod.outlook.com>
@ 2013-12-11 3:00 ` Po.Liu at freescale.com
2013-12-11 7:00 ` Prabhakar Kushwaha
1 sibling, 0 replies; 34+ messages in thread
From: Po.Liu at freescale.com @ 2013-12-11 3:00 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Scott Wood [mailto:scottwood at freescale.com]
> Sent: Wednesday, December 11, 2013 2:20 AM
> To: Kushwaha Prabhakar-B32579
> Cc: Liu Po-B43644; u-boot at lists.denx.de; Sun York-R58495
> Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot
> support base on TPL/SPL
>
> On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
> > On 12/9/2013 11:21 PM, Scott Wood wrote:
> > > On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
> > >> On 12/7/2013 6:51 AM, Scott Wood wrote:
> > >>> Prabhakar, why did you extend that to other uses? Why are both
> > >>> entries ifdeffed here, but only the 0xffffe000 entry on existing
> boards?
> > >> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds
> > >> does not have this.
> > >> i dont think NOR boot tested after this patch. NOR boot will not
> > >> work after applying this patch.
> > > So what happens if there's a speculative access to the non-ifdeffed
> > > 0xfffff000 when we're not booting from that (e.g. ramboot, SPL
> > > payload, SD/SPI...)?
> > >
> > >
> > If I understand the question correctly,
> > Ideally ramboot, SPL payload, SD/SPI should not make access to
> > this address. They assumed to be running from DDR whose TLB has
> > already been created by IBR, or First stage boot loader.
>
> Speculative accesses don't come (directly) from software. They are
> initiated by the hardware and are not predictable.
Remove the:
-#ifdef CONFIG_SPL_NAND_MINIMAL
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
Do not effect the NAND/NOR boot after I test on C29XPCIE.
>
> -Scott
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <ce05f24a72e0474f82d7f99c215353e6@DM2PR03MB317.namprd03.prod.outlook.com>
@ 2013-12-11 6:20 ` Po.Liu at freescale.com
2013-12-13 20:25 ` Scott Wood
1 sibling, 0 replies; 34+ messages in thread
From: Po.Liu at freescale.com @ 2013-12-11 6:20 UTC (permalink / raw)
To: u-boot
> > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
> > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > 0, 5, BOOKE_PAGESZ_64K, 1),
>
> No.
Without MAS3_SX, the board can't run in booting from NAND.
>
> > SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@
> > struct fsl_e_tlb_entry tlb_table[] = {
> > MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > 0, 7, BOOKE_PAGESZ_256K, 1),
> >
> > -#ifdef CONFIG_SYS_RAMBOOT
> > +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
> > + && !defined(CONFIG_SPL_COMMON_INIT_DDR))
> > SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> > CONFIG_SYS_DDR_SDRAM_BASE,
> > MAS3_SX|MAS3_SW|MAS3_SR, 0,
>
> This will have the result of mapping DDR in the SPL where it's not used,
> but not in the TPL where it is.
For the TPL the ddr initial by initdram(), so don't need to mapping ddr here.
I intend to change it to #if defined(CONFIG_SYS_RAMBOOT) || !defined(CONFIG_SPL_COMMON_INIT_DDR)
Is it more clear?
>
> -Scott
>
>
-Po Liu
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-10 18:20 ` Scott Wood
[not found] ` <5d27987f1d694ae9977cba2e8a78d843@DM2PR03MB317.namprd03.prod.outlook.com>
@ 2013-12-11 6:40 ` Prabhakar Kushwaha
2013-12-11 16:42 ` Scott Wood
1 sibling, 1 reply; 34+ messages in thread
From: Prabhakar Kushwaha @ 2013-12-11 6:40 UTC (permalink / raw)
To: u-boot
On 12/10/2013 11:50 PM, Scott Wood wrote:
> On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
>> On 12/9/2013 11:21 PM, Scott Wood wrote:
>>> On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
>>>> On 12/7/2013 6:51 AM, Scott Wood wrote:
>>>>> Prabhakar, why did you extend that to other uses? Why are both entries
>>>>> ifdeffed here, but only the 0xffffe000 entry on existing boards?
>>>> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
>>>> not have this.
>>>> i dont think NOR boot tested after this patch. NOR boot will not work
>>>> after applying this patch.
>>> So what happens if there's a speculative access to the non-ifdeffed
>>> 0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
>>> SD/SPI...)?
>>>
>>>
>> If I understand the question correctly,
>> Ideally ramboot, SPL payload, SD/SPI should not make access to this
>> address. They assumed to be running from DDR whose TLB has already been
>> created by IBR, or First stage boot loader.
> Speculative accesses don't come (directly) from software. They are
> initiated by the hardware and are not predictable.
>
>
Please help me in understanding this.
What are the scenario where it is possible? means how hardware can
initiate any access?
do hardware initiated transaction require TLB?
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <5d27987f1d694ae9977cba2e8a78d843@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 3:00 ` Po.Liu at freescale.com
@ 2013-12-11 7:00 ` Prabhakar Kushwaha
1 sibling, 0 replies; 34+ messages in thread
From: Prabhakar Kushwaha @ 2013-12-11 7:00 UTC (permalink / raw)
To: u-boot
On 12/11/2013 8:24 AM, Liu Po-B43644 wrote:
>> -----Original Message-----
>> From: Scott Wood [mailto:scottwood at freescale.com]
>> Sent: Wednesday, December 11, 2013 2:20 AM
>> To: Kushwaha Prabhakar-B32579
>> Cc: Liu Po-B43644; u-boot at lists.denx.de; Sun York-R58495
>> Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot
>> support base on TPL/SPL
>>
>> On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
>> > On 12/9/2013 11:21 PM, Scott Wood wrote:
>> > > On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
>> > >> On 12/7/2013 6:51 AM, Scott Wood wrote:
>> > >>> Prabhakar, why did you extend that to other uses? Why are both
>> > >>> entries ifdeffed here, but only the 0xffffe000 entry on existing
>> boards?
>> > >> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds
>> > >> does not have this.
>> > >> i dont think NOR boot tested after this patch. NOR boot will not
>> > >> work after applying this patch.
>> > > So what happens if there's a speculative access to the non-ifdeffed
>> > > 0xfffff000 when we're not booting from that (e.g. ramboot, SPL
>> > > payload, SD/SPI...)?
>> > >
>> > >
>> > If I understand the question correctly,
>> > Ideally ramboot, SPL payload, SD/SPI should not make access to
>> > this address. They assumed to be running from DDR whose TLB has
>> > already been created by IBR, or First stage boot loader.
>>
>> Speculative accesses don't come (directly) from software. They are
>> initiated by the hardware and are not predictable.
> Remove the:
> -#ifdef CONFIG_SPL_NAND_MINIMAL
> - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 10, BOOKE_PAGESZ_4K, 1),
> - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 11, BOOKE_PAGESZ_4K, 1),
> -#endif
> Do not effect the NAND/NOR boot after I test in C29XPCIE.
>
I just wonder how it is working without both TLBs. I can guess what is
happening
- NOR boot: After coming to AS1--> AS0, system is running with NOR
TLB entry
- NAND boot: after coming to AS1--> AS0, It is
usingCONFIG_SYS_INIT_L2_ADDR TLB entry
so, it can be removed for c293PCIe.
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-11 6:40 ` Prabhakar Kushwaha
@ 2013-12-11 16:42 ` Scott Wood
0 siblings, 0 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-11 16:42 UTC (permalink / raw)
To: u-boot
On Wed, 2013-12-11 at 12:10 +0530, Prabhakar Kushwaha wrote:
> On 12/10/2013 11:50 PM, Scott Wood wrote:
> > On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
> >> On 12/9/2013 11:21 PM, Scott Wood wrote:
> >>> On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
> >>>> On 12/7/2013 6:51 AM, Scott Wood wrote:
> >>>>> Prabhakar, why did you extend that to other uses? Why are both entries
> >>>>> ifdeffed here, but only the 0xffffe000 entry on existing boards?
> >>>> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
> >>>> not have this.
> >>>> i dont think NOR boot tested after this patch. NOR boot will not work
> >>>> after applying this patch.
> >>> So what happens if there's a speculative access to the non-ifdeffed
> >>> 0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
> >>> SD/SPI...)?
> >>>
> >>>
> >> If I understand the question correctly,
> >> Ideally ramboot, SPL payload, SD/SPI should not make access to this
> >> address. They assumed to be running from DDR whose TLB has already been
> >> created by IBR, or First stage boot loader.
> > Speculative accesses don't come (directly) from software. They are
> > initiated by the hardware and are not predictable.
> >
> >
>
> Please help me in understanding this.
> What are the scenario where it is possible? means how hardware can
> initiate any access?
> do hardware initiated transaction require TLB?
Any mapping that is in the TLB can be used for speculative reads (except
that the guarded bit or lack of read permission inhibits speculative
data reads, and the lack of execute permission inhibits speculative
instruction fetches). Any TLB where speculative reads aren't inhibited
as described must be backed by something memory-like.
The CPU will do this when it predicts that it will need data from that
address, though sometimes the predictions are wrong.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <ce05f24a72e0474f82d7f99c215353e6@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 6:20 ` Po.Liu at freescale.com
@ 2013-12-13 20:25 ` Scott Wood
[not found] ` <8cbfa2585cd04b348c5883a628e3a33c@DM2PR03MB317.namprd03.prod.outlook.com>
1 sibling, 1 reply; 34+ messages in thread
From: Scott Wood @ 2013-12-13 20:25 UTC (permalink / raw)
To: u-boot
On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote:
> > > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
> > > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > > 0, 5, BOOKE_PAGESZ_64K, 1),
> >
> > No.
> Without MAS3_SX, the board can't run in booting from NAND.
Explain why you're executing from this TLB entry. This should be for
accessing the NAND as I/O after you've relocated away from the boot
buffer. There should be a different mapping for the boot buffer early
on. None of the other NAND boot targets have needed this. Perhaps this
is related to the other TLB entry that you said you could work without.
> > > SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@
> > > struct fsl_e_tlb_entry tlb_table[] = {
> > > MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > > 0, 7, BOOKE_PAGESZ_256K, 1),
> > >
> > > -#ifdef CONFIG_SYS_RAMBOOT
> > > +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
> > > + && !defined(CONFIG_SPL_COMMON_INIT_DDR))
> > > SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> > > CONFIG_SYS_DDR_SDRAM_BASE,
> > > MAS3_SX|MAS3_SW|MAS3_SR, 0,
> >
> > This will have the result of mapping DDR in the SPL where it's not used,
> > but not in the TPL where it is.
> For the TPL the ddr initial by initdram(), so don't need to mapping ddr here.
> I intend to change it to #if defined(CONFIG_SYS_RAMBOOT) || !defined(CONFIG_SPL_COMMON_INIT_DDR)
> Is it more clear?
No, you'll still end up mapping it in the SPL (when DDR hasn't been set
up yet, so again there could be speculative accesses causing machine
checks), and that change would make the mapping happen in ordinary NOR
boot as well (where it would duplicate what initdram() does). We only
want this TLB entry in phases that are booting out of DDR.
How about:
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
...with the assumption that all SPLs for a given board will either put
the final U-boot in DDR or SRAM, and the board tlb.c knows the
difference.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-11 2:46 ` Po.Liu at freescale.com
@ 2013-12-13 21:22 ` Scott Wood
0 siblings, 0 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-13 21:22 UTC (permalink / raw)
To: u-boot
On Tue, 2013-12-10 at 20:46 -0600, Liu Po-B43644 wrote:
>
>
> Sorry for late reply since the email system crash.
>
> > -----Original Message-----
> > From: Scott Wood [mailto:scottwood at freescale.com]
> > Sent: Saturday, December 07, 2013 9:22 AM
> > To: Liu Po-B43644
> > Cc: u-boot at lists.denx.de; Sun York-R58495; Kushwaha
> Prabhakar-B32579
> > Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND
> boot
> > support base on TPL/SPL
> >
> > On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
> > > diff --git a/board/freescale/c29xpcie/spl.c
> > > b/board/freescale/c29xpcie/spl.c new file mode 100644 index
> > > 0000000..7bc8ce1
> > > --- /dev/null
> > > +++ b/board/freescale/c29xpcie/spl.c
> > > @@ -0,0 +1,73 @@
> > > +/* Copyright 2013 Freescale Semiconductor, Inc.
> > > + *
> > > + * SPDX-License-Identifier: GPL-2.0+
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <ns16550.h>
> > > +#include <malloc.h>
> > > +#include <mmc.h>
> > > +#include <nand.h>
> > > +#include <i2c.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +ulong get_effective_memsize(void)
> > > +{
> > > + return CONFIG_SYS_L2_SIZE;
> > > +}
> > > +
> > > +void board_init_f(ulong bootflag)
> > > +{
> > > + u32 plat_ratio;
> > > + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> > > +
> > > + console_init_f();
> > > +
> > > + /* initialize selected port with appropriate baud rate */
> > > + plat_ratio = in_be32(&gur->porpllsr) &
> MPC85xx_PORPLLSR_PLAT_RATIO;
> > > + plat_ratio >>= 1;
> > > + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
> > > +
> > > + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
> > > + gd->bus_clk / 16 / CONFIG_BAUDRATE);
> > > +
> > > + /* copy code to RAM and jump to it - this should not return */
> > > + /* NOTE - code has to be copied out of NAND buffer before
> > > + * other blocks can be read.
> > > + */
> > > + relocate_code(CONFIG_SPL_RELOC_STACK, 0,
> > > +CONFIG_SPL_RELOC_TEXT_BASE); }
> > > +
> > > +void board_init_r(gd_t *gd, ulong dest_addr) {
> > > + /* Pointer is writable since we allocated a register for it */
> > > + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
> > > + bd_t *bd;
> > > +
> > > + memset(gd, 0, sizeof(gd_t));
> > > + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
> > > + memset(bd, 0, sizeof(bd_t));
> > > + gd->bd = bd;
> > > + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
> > > + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
> > > +
> > > + probecpu();
> > > + get_clocks();
> > > + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
> > > + CONFIG_SPL_RELOC_MALLOC_SIZE);
> > > +
> > > + /* relocate environment function pointers etc. */
> > > + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
> > > + (uchar *)CONFIG_ENV_ADDR);
> > > + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
> > > + gd->env_valid = 1;
> > > +
> > > + i2c_init_all();
> > > +
> > > + gd->ram_size = initdram(0);
> > > +
> > > + puts("\nTertiary program loader running in sram...");
> >
> > Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or
> was it
> > a copy/paste error that you added things to the board config file
> for
> > SD/SPI (after all, the subject line says it's a NAND patch)?
> >
> Yes, I assume this patch only for NAND boot for C29XPCIE.
Then why did you add a "#if defined(CONFIG_SDCARD) ||
defined(CONFIG_SPIFLASH)" section in the board config file?
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2013-12-05 6:19 ` [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2013-12-07 1:21 ` Scott Wood
@ 2013-12-14 3:08 ` Po Liu
2013-12-14 3:08 ` [U-Boot] [PATCH v3 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
` (2 more replies)
1 sibling, 3 replies; 34+ messages in thread
From: Po Liu @ 2013-12-14 3:08 UTC (permalink / raw)
To: u-boot
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_IFC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
drivers/mtd/nand/fsl_ifc_spl.c | 29 +++++++++++++++++++++++------
spl/Makefile | 1 +
3 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..28656f2 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
+#ifdef CONFIG_TPL_BUILD
+void nand_spl_load_image(uint32_t offs, int uboot_size, void *vdst)
+#else
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,9 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+#ifdef CONFIG_TPL_BUILD
+ uchar *dst = vdst;
+#endif
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -211,6 +218,15 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, dst) \
+ nand_load(offs, uboot_size, dst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/spl/Makefile b/spl/Makefile
index 2a787af..7e2adf9 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -79,6 +79,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v3 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
@ 2013-12-14 3:08 ` Po Liu
2014-01-02 22:01 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-06 6:15 ` [U-Boot] [PATCH v4 " Po Liu
2 siblings, 0 replies; 34+ messages in thread
From: Po Liu @ 2013-12-14 3:08 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xffffe000 to 0xffffffff
- change the ddr tlb mapping condition
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 77 +++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 13 +++-
boards.cfg | 1 +
include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++-
7 files changed, 295 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..36fe06f
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..ba9b651
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..c5abed0 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +44,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 114cc86..adcbbdf 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -784,6 +784,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..8ec5cee 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +74,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +179,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +236,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +340,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +386,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +476,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
[not found] ` <8cbfa2585cd04b348c5883a628e3a33c@DM2PR03MB317.namprd03.prod.outlook.com>
@ 2013-12-14 3:21 ` Scott Wood
0 siblings, 0 replies; 34+ messages in thread
From: Scott Wood @ 2013-12-14 3:21 UTC (permalink / raw)
To: u-boot
On Fri, 2013-12-13 at 21:09 -0600, Liu Po-B43644 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Saturday, December 14, 2013 4:26 AM
> > To: Liu Po-B43644
> > Cc: u-boot at lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579
> > Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot
> > support base on TPL/SPL
> >
> > On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote:
> > > > > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,
> > CONFIG_SYS_NAND_BASE_PHYS,
> > > > > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > > > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > > > > 0, 5, BOOKE_PAGESZ_64K, 1),
> > > >
> > > > No.
> > > Without MAS3_SX, the board can't run in booting from NAND.
> >
> > Explain why you're executing from this TLB entry. This should be for
> > accessing the NAND as I/O after you've relocated away from the boot
> > buffer. There should be a different mapping for the boot buffer early on.
> > None of the other NAND boot targets have needed this. Perhaps this is
> > related to the other TLB entry that you said you could work without.
> This is because for SPL, the
> #define CONFIG_SPL_TEXT_BASE 0xff800000
> #define CONFIG_SYS_NAND_BASE 0xff800000
> Code space overlap the nand io space.
OK, I guess we move the NAND buffer before relocating out of it. And
for some reason I missed that existing targets do the same thing. Never
mind...
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-14 3:08 ` [U-Boot] [PATCH v3 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2014-01-02 22:01 ` Scott Wood
2014-01-06 6:15 ` [U-Boot] [PATCH v4 " Po Liu
2 siblings, 0 replies; 34+ messages in thread
From: Scott Wood @ 2014-01-02 22:01 UTC (permalink / raw)
To: u-boot
On Sat, 2013-12-14 at 11:08 +0800, Po Liu wrote:
> diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
> index 9de327b..28656f2 100644
> --- a/drivers/mtd/nand/fsl_ifc_spl.c
> +++ b/drivers/mtd/nand/fsl_ifc_spl.c
> @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
> return __raw_readw((u16 *)marker) != 0xffff;
> }
>
> +#ifdef CONFIG_TPL_BUILD
> +void nand_spl_load_image(uint32_t offs, int uboot_size, void *vdst)
> +#else
> static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
> +#endif
> {
> struct fsl_ifc *ifc = IFC_BASE_ADDR;
> uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
> @@ -105,6 +109,9 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
>
> int sram_addr;
> int pg_no;
> +#ifdef CONFIG_TPL_BUILD
> + uchar *dst = vdst;
> +#endif
Please change the static function signature to match, as fsl_elbc_spl.c
does.
> diff --git a/spl/Makefile b/spl/Makefile
> index 2a787af..7e2adf9 100644
> --- a/spl/Makefile
> +++ b/spl/Makefile
> @@ -79,6 +79,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
> LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
> drivers/power/pmic/
> LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
> +LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
> LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
> LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
> LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
Document this in README.
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v4 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-14 3:08 ` [U-Boot] [PATCH v3 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-02 22:01 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
@ 2014-01-06 6:15 ` Po Liu
2014-01-06 6:15 ` [U-Boot] [PATCH v4 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2 siblings, 1 reply; 34+ messages in thread
From: Po Liu @ 2014-01-06 6:15 UTC (permalink / raw)
To: u-boot
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes for v4:
- modify the nand_load function
- add comments in README.SPL
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
doc/README.SPL | 1 +
drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
spl/Makefile | 1 +
4 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/doc/README.SPL b/doc/README.SPL
index 312a6a6..20d53fb 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc/fsl_ifc.o)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..6b43496 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
+static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+ uchar *dst = vdst;
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -208,9 +213,20 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
offs += page_size;
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
}
+
+ return 0;
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load(offs, uboot_size, vdst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/spl/Makefile b/spl/Makefile
index 1e88d74..4a0442b 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -72,6 +72,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v4 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2014-01-06 6:15 ` [U-Boot] [PATCH v4 " Po Liu
@ 2014-01-06 6:15 ` Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
0 siblings, 1 reply; 34+ messages in thread
From: Po Liu @ 2014-01-06 6:15 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xffffe000 to 0xffffffff
- change the ddr tlb mapping condition
changes for v4:
- None.
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 77 +++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 13 +++-
boards.cfg | 1 +
include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++-
7 files changed, 295 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..36fe06f
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..ba9b651
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..c5abed0 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +44,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 93c3fd1..d26e041 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -791,6 +791,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..8ec5cee 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +74,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +179,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +236,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +340,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +386,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +476,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-06 6:15 ` [U-Boot] [PATCH v4 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2014-01-07 3:37 ` Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
` (2 more replies)
0 siblings, 3 replies; 34+ messages in thread
From: Po Liu @ 2014-01-07 3:37 UTC (permalink / raw)
To: u-boot
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes for v4:
- modify the nand_load function
- add comments in README.SPL
changes for v5:
-none
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
doc/README.SPL | 1 +
drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
spl/Makefile | 1 +
4 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/doc/README.SPL b/doc/README.SPL
index 312a6a6..20d53fb 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc/fsl_ifc.o)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..6b43496 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
+static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+ uchar *dst = vdst;
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -208,9 +213,20 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
offs += page_size;
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
}
+
+ return 0;
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load(offs, uboot_size, vdst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/spl/Makefile b/spl/Makefile
index 1e88d74..4a0442b 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -72,6 +72,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2014-01-07 3:37 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
@ 2014-01-07 3:37 ` Po Liu
2014-01-08 0:03 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
2 siblings, 0 replies; 34+ messages in thread
From: Po Liu @ 2014-01-07 3:37 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xffffe000 to 0xffffffff
- change the ddr tlb mapping condition
changes for v4:
- None.
changes for v5:
- code style change.
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 77 +++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 13 +++-
boards.cfg | 1 +
include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++-
7 files changed, 295 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..3cfdb72
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..8f96b67
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..c5abed0 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +44,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 93c3fd1..d26e041 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -791,6 +791,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..8ec5cee 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +74,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +179,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +236,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +340,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +386,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +476,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-07 3:37 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2014-01-08 0:03 ` Scott Wood
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
2 siblings, 0 replies; 34+ messages in thread
From: Scott Wood @ 2014-01-08 0:03 UTC (permalink / raw)
To: u-boot
On Tue, 2014-01-07 at 11:37 +0800, Po Liu wrote:
> diff --git a/doc/README.SPL b/doc/README.SPL
> index 312a6a6..20d53fb 100644
> --- a/doc/README.SPL
> +++ b/doc/README.SPL
> @@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
> CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
> CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
> CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc/fsl_ifc.o)
This symbol is not specifically for fsl_ifc.o, it's for the entire
drivers/misc directory (would have been drivers/misc/libmisc.o, but now
they're all drivers/<foo>/built-in.o).
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-07 3:37 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-08 0:03 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
@ 2014-01-10 2:10 ` Po Liu
2014-01-10 2:10 ` [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
` (2 more replies)
2 siblings, 3 replies; 34+ messages in thread
From: Po Liu @ 2014-01-10 2:10 UTC (permalink / raw)
To: u-boot
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate public code and c29xpcie board code
- add ifc support
changes for v3:
- remove the redundant plus
- ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
changes for v4:
- modify the nand_load function
- add comments in README.SPL
changes for v5:
-none
changes for v6:
- modify the readme file for the include lib file
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
doc/README.SPL | 1 +
drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
spl/Makefile | 1 +
4 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc13267..acaa093 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
@@ -69,12 +76,6 @@ SECTIONS
#else
#error unknown NAND controller
#endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg ADDR(.text) - 0x1000 :
- {
- KEEP(*(.bootpg))
- } :text = 0xffff
-#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
diff --git a/doc/README.SPL b/doc/README.SPL
index 312a6a6..b1bc3ca 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..6b43496 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
+static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
int sram_addr;
int pg_no;
+ uchar *dst = vdst;
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
@@ -208,9 +213,20 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
offs += page_size;
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
}
+
+ return 0;
}
/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+ nand_load(offs, uboot_size, vdst)
+#endif
+
+/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
@@ -221,16 +237,17 @@ void nand_boot(void)
/*
* Load U-Boot image from NAND into RAM
*/
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
- nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
diff --git a/spl/Makefile b/spl/Makefile
index 1e88d74..4a0442b 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -72,6 +72,7 @@ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
drivers/power/pmic/
LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
@ 2014-01-10 2:10 ` Po Liu
2014-01-21 22:54 ` York Sun
2014-01-10 19:03 ` [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-13 6:28 ` Prabhakar Kushwaha
2 siblings, 1 reply; 34+ messages in thread
From: Po Liu @ 2014-01-10 2:10 UTC (permalink / raw)
To: u-boot
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
- seperate the public code and c29xpcie board code;
changes for v3:
- booting log simple to "SPL" "TPL"
- remove the 8k TLB from 0xffffe000 to 0xffffffff
- change the ddr tlb mapping condition
changes for v4:
- None.
changes for v5:
- code style change.
changes for v6:
- none
board/freescale/c29xpcie/Makefile | 15 ++++
board/freescale/c29xpcie/cpld.c | 2 +
board/freescale/c29xpcie/spl.c | 77 +++++++++++++++++++
board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++
board/freescale/c29xpcie/tlb.c | 13 +++-
boards.cfg | 1 +
include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++-
7 files changed, 295 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/c29xpcie/spl.c
create mode 100644 board/freescale/c29xpcie/spl_minimal.c
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
}
#endif
+#ifndef CONFIG_SPL_BUILD
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..3cfdb72
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..8f96b67
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..c5abed0 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +44,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
+#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 18faf09..d19e43a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -790,6 +790,7 @@ Active powerpc mpc85xx - freescale bsc9132qds
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..8ec5cee 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
@@ -31,8 +74,14 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* High Level Configuration Options */
@@ -130,6 +179,10 @@
(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/*
* IFC Definitions
*/
@@ -183,7 +236,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -269,7 +340,44 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -278,6 +386,10 @@
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -364,6 +476,16 @@
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
--
1.8.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
2014-01-10 2:10 ` [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2014-01-10 19:03 ` Scott Wood
2014-01-21 22:54 ` York Sun
2014-01-13 6:28 ` Prabhakar Kushwaha
2 siblings, 1 reply; 34+ messages in thread
From: Scott Wood @ 2014-01-10 19:03 UTC (permalink / raw)
To: u-boot
On Fri, 2014-01-10 at 10:10 +0800, Po Liu wrote:
> Using the TPL method for nand boot by sram was already
> supported. Here add some code for mpc85xx ifc nand boot.
>
> - For ifc, elbc, esdhc, espi, all need the SPL without
> section .resetvec.
> - Use a clear function name for nand spl boot.
> - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
> in spl/Makefile;
>
> Signed-off-by: Po Liu <Po.Liu@freescale.com>
> ---
> changes for v2:
> - seperate public code and c29xpcie board code
> - add ifc support
> changes for v3:
> - remove the redundant plus
> - ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
> changes for v4:
> - modify the nand_load function
> - add comments in README.SPL
> changes for v5:
> -none
> changes for v6:
> - modify the readme file for the include lib file
>
> arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
> doc/README.SPL | 1 +
> drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
> spl/Makefile | 1 +
> 4 files changed, 34 insertions(+), 14 deletions(-)
Acked-by: Scott Wood <scottwood@freescale.com>
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
2014-01-10 2:10 ` [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-10 19:03 ` [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
@ 2014-01-13 6:28 ` Prabhakar Kushwaha
2014-01-14 1:09 ` Scott Wood
2 siblings, 1 reply; 34+ messages in thread
From: Prabhakar Kushwaha @ 2014-01-13 6:28 UTC (permalink / raw)
To: u-boot
On 1/10/2014 7:40 AM, Po Liu wrote:
> Using the TPL method for nand boot by sram was already
> supported. Here add some code for mpc85xx ifc nand boot.
>
> - For ifc, elbc, esdhc, espi, all need the SPL without
> section .resetvec.
> - Use a clear function name for nand spl boot.
> - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
> in spl/Makefile;
>
> Signed-off-by: Po Liu <Po.Liu@freescale.com>
> ---
> changes for v2:
> - seperate public code and c29xpcie board code
> - add ifc support
> changes for v3:
> - remove the redundant plus
> - ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
> changes for v4:
> - modify the nand_load function
> - add comments in README.SPL
> changes for v5:
> -none
> changes for v6:
> - modify the readme file for the include lib file
>
> arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
> doc/README.SPL | 1 +
> drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
> spl/Makefile | 1 +
> 4 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> index bc13267..acaa093 100644
> --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> @@ -57,7 +57,14 @@ SECTIONS
> . = ALIGN(8);
> __init_begin = .;
> __init_end = .;
> -/* FIXME for non-NAND SPL */
> +
> +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
> +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
> + .bootpg ADDR(.text) - 0x1000 :
> + {
> + KEEP(*(.bootpg))
> + } :text = 0xffff
> +#else
> #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
> .bootpg ADDR(.text) + 0x1000 :
> {
> @@ -69,12 +76,6 @@ SECTIONS
> #else
> #error unknown NAND controller
> #endif
> -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
> - .bootpg ADDR(.text) - 0x1000 :
> - {
> - KEEP(*(.bootpg))
> - } :text = 0xffff
> -#else
> .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
> KEEP(*(.resetvec))
> } = 0xffff
> diff --git a/doc/README.SPL b/doc/README.SPL
> index 312a6a6..b1bc3ca 100644
> --- a/doc/README.SPL
> +++ b/doc/README.SPL
> @@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
> CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
> CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
> CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc)
> CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
> CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
> CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
> diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
> index 9de327b..6b43496 100644
> --- a/drivers/mtd/nand/fsl_ifc_spl.c
> +++ b/drivers/mtd/nand/fsl_ifc_spl.c
> @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
> return __raw_readw((u16 *)marker) != 0xffff;
> }
>
> -static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
> +#ifdef CONFIG_TPL_BUILD
> +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
> +#else
> +static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
> +#endif
nand_load definition is
static void nand_load(unsigned int offs, int uboot_size, uchar *dst);
have you checked the compilation warning for non TPL framework?
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-13 6:28 ` Prabhakar Kushwaha
@ 2014-01-14 1:09 ` Scott Wood
2014-01-14 3:44 ` Prabhakar Kushwaha
0 siblings, 1 reply; 34+ messages in thread
From: Scott Wood @ 2014-01-14 1:09 UTC (permalink / raw)
To: u-boot
On Mon, 2014-01-13 at 11:58 +0530, Prabhakar Kushwaha wrote:
> On 1/10/2014 7:40 AM, Po Liu wrote:
> > diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
> > index 9de327b..6b43496 100644
> > --- a/drivers/mtd/nand/fsl_ifc_spl.c
> > +++ b/drivers/mtd/nand/fsl_ifc_spl.c
> > @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
> > return __raw_readw((u16 *)marker) != 0xffff;
> > }
> >
> > -static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
> > +#ifdef CONFIG_TPL_BUILD
> > +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
> > +#else
> > +static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
> > +#endif
>
> nand_load definition is
> static void nand_load(unsigned int offs, int uboot_size, uchar *dst);
Not anymore...
> have you checked the compilation warning for non TPL framework?
Are you seeing a warning?
-Scott
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-14 1:09 ` Scott Wood
@ 2014-01-14 3:44 ` Prabhakar Kushwaha
0 siblings, 0 replies; 34+ messages in thread
From: Prabhakar Kushwaha @ 2014-01-14 3:44 UTC (permalink / raw)
To: u-boot
On 1/14/2014 6:39 AM, Scott Wood wrote:
> On Mon, 2014-01-13 at 11:58 +0530, Prabhakar Kushwaha wrote:
>> On 1/10/2014 7:40 AM, Po Liu wrote:
>>> diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
>>> index 9de327b..6b43496 100644
>>> --- a/drivers/mtd/nand/fsl_ifc_spl.c
>>> +++ b/drivers/mtd/nand/fsl_ifc_spl.c
>>> @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
>>> return __raw_readw((u16 *)marker) != 0xffff;
>>> }
>>>
>>> -static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
>>> +#ifdef CONFIG_TPL_BUILD
>>> +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
>>> +#else
>>> +static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
>>> +#endif
>> nand_load definition is
>> static void nand_load(unsigned int offs, int uboot_size, uchar *dst);
> Not anymore...
Just confused with previous fsl_ifc_spl.c file. Actually this patch
is changing nand_load signature.
No warning. I checked for BSC9131RDB, P1010 NAND target.
Thanks,
Prabhakar
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
2014-01-10 19:03 ` [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
@ 2014-01-21 22:54 ` York Sun
0 siblings, 0 replies; 34+ messages in thread
From: York Sun @ 2014-01-21 22:54 UTC (permalink / raw)
To: u-boot
On 01/10/2014 11:03 AM, Scott Wood wrote:
> On Fri, 2014-01-10 at 10:10 +0800, Po Liu wrote:
>> Using the TPL method for nand boot by sram was already
>> supported. Here add some code for mpc85xx ifc nand boot.
>>
>> - For ifc, elbc, esdhc, espi, all need the SPL without
>> section .resetvec.
>> - Use a clear function name for nand spl boot.
>> - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
>> in spl/Makefile;
>>
>> Signed-off-by: Po Liu <Po.Liu@freescale.com>
>> ---
>> changes for v2:
>> - seperate public code and c29xpcie board code
>> - add ifc support
>> changes for v3:
>> - remove the redundant plus
>> - ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT
>> changes for v4:
>> - modify the nand_load function
>> - add comments in README.SPL
>> changes for v5:
>> -none
>> changes for v6:
>> - modify the readme file for the include lib file
>>
>> arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 ++++++++-------
>> doc/README.SPL | 1 +
>> drivers/mtd/nand/fsl_ifc_spl.c | 31 ++++++++++++++++++++++++-------
>> spl/Makefile | 1 +
>> 4 files changed, 34 insertions(+), 14 deletions(-)
>
> Acked-by: Scott Wood <scottwood@freescale.com>
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
2014-01-10 2:10 ` [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
@ 2014-01-21 22:54 ` York Sun
0 siblings, 0 replies; 34+ messages in thread
From: York Sun @ 2014-01-21 22:54 UTC (permalink / raw)
To: u-boot
On 01/09/2014 06:10 PM, Po Liu wrote:
> Using the TPL/SPL method to booting from 8k page NAND flash.
> - Add 256kB size SRAM tlb for second step booting;
> - Add spl.c for TPL image boot;
> - Add spl_minimal.c for minimal SPL image;
> - Add C29XPCIE_NAND configure;
> - Modify C29XPCIE.h for nand config and enviroment;
>
> Signed-off-by: Po Liu <Po.Liu@freescale.com>
> ---
> changes for v2:
> - seperate the public code and c29xpcie board code;
> changes for v3:
> - booting log simple to "SPL" "TPL"
> - remove the 8k TLB from 0xffffe000 to 0xffffffff
> - change the ddr tlb mapping condition
> changes for v4:
> - None.
> changes for v5:
> - code style change.
> changes for v6:
> - none
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2014-01-21 22:54 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-02 4:12 [U-Boot] [PATCH] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2013-12-05 6:18 ` [U-Boot] [PATCH v2 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-05 6:19 ` [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2013-12-07 1:21 ` Scott Wood
2013-12-09 5:40 ` Prabhakar Kushwaha
2013-12-09 17:51 ` Scott Wood
2013-12-10 6:07 ` Prabhakar Kushwaha
2013-12-10 18:20 ` Scott Wood
[not found] ` <5d27987f1d694ae9977cba2e8a78d843@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 3:00 ` Po.Liu at freescale.com
2013-12-11 7:00 ` Prabhakar Kushwaha
2013-12-11 6:40 ` Prabhakar Kushwaha
2013-12-11 16:42 ` Scott Wood
[not found] ` <c957f7e802e245488c0c0e0fc0f425ed@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 2:46 ` Po.Liu at freescale.com
2013-12-13 21:22 ` Scott Wood
[not found] ` <ce05f24a72e0474f82d7f99c215353e6@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-11 6:20 ` Po.Liu at freescale.com
2013-12-13 20:25 ` Scott Wood
[not found] ` <8cbfa2585cd04b348c5883a628e3a33c@DM2PR03MB317.namprd03.prod.outlook.com>
2013-12-14 3:21 ` Scott Wood
2013-12-14 3:08 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2013-12-14 3:08 ` [U-Boot] [PATCH v3 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-02 22:01 ` [U-Boot] [PATCH v3 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-06 6:15 ` [U-Boot] [PATCH v4 " Po Liu
2014-01-06 6:15 ` [U-Boot] [PATCH v4 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Po Liu
2014-01-07 3:37 ` [U-Boot] [PATCH v5 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-08 0:03 ` [U-Boot] [PATCH v5 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-10 2:10 ` [U-Boot] [PATCH v6 " Po Liu
2014-01-10 2:10 ` [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Po Liu
2014-01-21 22:54 ` York Sun
2014-01-10 19:03 ` [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL Scott Wood
2014-01-21 22:54 ` York Sun
2014-01-13 6:28 ` Prabhakar Kushwaha
2014-01-14 1:09 ` Scott Wood
2014-01-14 3:44 ` Prabhakar Kushwaha
2013-12-07 1:33 ` [U-Boot] [PATCH v2 " Scott Wood
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