From: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
To: <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
Cc: <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
<angus.clark-qxv4g6HH51o@public.gmane.org>,
<marex-ynQEQJNshbs@public.gmane.org>,
<lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
<pekon-l0cyMroinI0@public.gmane.org>,
<sourav.poddar-l0cyMroinI0@public.gmane.org>,
<broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
<linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Subject: [PATCH V2 1/4] mtd: spi-nor: copy the SPI NOR commands to a new header file
Date: Fri, 6 Dec 2013 16:32:41 +0800 [thread overview]
Message-ID: <1386318764-15882-2-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1386318764-15882-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie <b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
include/linux/mtd/spi-nor.h | 53 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
new file mode 100644
index 0000000..ab2ea1e
--- /dev/null
+++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,53 @@
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+
+/* Flash opcodes. */
+#define OPCODE_WREN 0x06 /* Write enable */
+#define OPCODE_RDSR 0x05 /* Read status register */
+#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
+#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ 0x6b /* Read data bytes */
+#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
+#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
+#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
+#define OPCODE_RDID 0x9f /* Read JEDEC ID */
+#define OPCODE_RDCR 0x35 /* Read configuration register */
+
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
+#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
+#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+
+/* Used for SST flashes only. */
+#define OPCODE_BP 0x02 /* Byte program */
+#define OPCODE_WRDI 0x04 /* Write disable */
+#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
+
+/* Used for Macronix and Winbond flashes. */
+#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
+#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
+
+/* Used for Spansion flashes only. */
+#define OPCODE_BRWR 0x17 /* Bank register write */
+
+/* Status Register bits. */
+#define SR_WIP 1 /* Write in progress */
+#define SR_WEL 2 /* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0 4 /* Block protect 0 */
+#define SR_BP1 8 /* Block protect 1 */
+#define SR_BP2 0x10 /* Block protect 2 */
+#define SR_SRWD 0x80 /* SR write protect */
+
+#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
+
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
+
+#endif
--
1.7.2.rc3
--
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WARNING: multiple messages have this Message-ID (diff)
From: Huang Shijie <b32955@freescale.com>
To: <dwmw2@infradead.org>
Cc: marex@denx.de, angus.clark@st.com, broonie@linaro.org,
linux-spi@vger.kernel.org, Huang Shijie <b32955@freescale.com>,
linux-mtd@lists.infradead.org, pekon@ti.com,
sourav.poddar@ti.com, computersforpeace@gmail.com,
lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 1/4] mtd: spi-nor: copy the SPI NOR commands to a new header file
Date: Fri, 6 Dec 2013 16:32:41 +0800 [thread overview]
Message-ID: <1386318764-15882-2-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1386318764-15882-1-git-send-email-b32955@freescale.com>
This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
include/linux/mtd/spi-nor.h | 53 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
new file mode 100644
index 0000000..ab2ea1e
--- /dev/null
+++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,53 @@
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+
+/* Flash opcodes. */
+#define OPCODE_WREN 0x06 /* Write enable */
+#define OPCODE_RDSR 0x05 /* Read status register */
+#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
+#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ 0x6b /* Read data bytes */
+#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
+#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
+#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
+#define OPCODE_RDID 0x9f /* Read JEDEC ID */
+#define OPCODE_RDCR 0x35 /* Read configuration register */
+
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
+#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
+#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+
+/* Used for SST flashes only. */
+#define OPCODE_BP 0x02 /* Byte program */
+#define OPCODE_WRDI 0x04 /* Write disable */
+#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
+
+/* Used for Macronix and Winbond flashes. */
+#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
+#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
+
+/* Used for Spansion flashes only. */
+#define OPCODE_BRWR 0x17 /* Bank register write */
+
+/* Status Register bits. */
+#define SR_WIP 1 /* Write in progress */
+#define SR_WEL 2 /* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0 4 /* Block protect 0 */
+#define SR_BP1 8 /* Block protect 1 */
+#define SR_BP2 0x10 /* Block protect 2 */
+#define SR_SRWD 0x80 /* SR write protect */
+
+#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
+
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
+
+#endif
--
1.7.2.rc3
WARNING: multiple messages have this Message-ID (diff)
From: b32955@freescale.com (Huang Shijie)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 1/4] mtd: spi-nor: copy the SPI NOR commands to a new header file
Date: Fri, 6 Dec 2013 16:32:41 +0800 [thread overview]
Message-ID: <1386318764-15882-2-git-send-email-b32955@freescale.com> (raw)
In-Reply-To: <1386318764-15882-1-git-send-email-b32955@freescale.com>
This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
include/linux/mtd/spi-nor.h | 53 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
new file mode 100644
index 0000000..ab2ea1e
--- /dev/null
+++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,53 @@
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+
+/* Flash opcodes. */
+#define OPCODE_WREN 0x06 /* Write enable */
+#define OPCODE_RDSR 0x05 /* Read status register */
+#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
+#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ 0x6b /* Read data bytes */
+#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
+#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
+#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
+#define OPCODE_RDID 0x9f /* Read JEDEC ID */
+#define OPCODE_RDCR 0x35 /* Read configuration register */
+
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
+#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
+#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
+#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+
+/* Used for SST flashes only. */
+#define OPCODE_BP 0x02 /* Byte program */
+#define OPCODE_WRDI 0x04 /* Write disable */
+#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
+
+/* Used for Macronix and Winbond flashes. */
+#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
+#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
+
+/* Used for Spansion flashes only. */
+#define OPCODE_BRWR 0x17 /* Bank register write */
+
+/* Status Register bits. */
+#define SR_WIP 1 /* Write in progress */
+#define SR_WEL 2 /* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0 4 /* Block protect 0 */
+#define SR_BP1 8 /* Block protect 1 */
+#define SR_BP2 0x10 /* Block protect 2 */
+#define SR_SRWD 0x80 /* SR write protect */
+
+#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
+
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
+
+#endif
--
1.7.2.rc3
next prev parent reply other threads:[~2013-12-06 8:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-06 8:32 [PATCH V2 0/4] mtd: spi-nor: add a new framework for SPI NOR Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` Huang Shijie
[not found] ` <1386318764-15882-1-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2013-12-06 8:32 ` Huang Shijie [this message]
2013-12-06 8:32 ` [PATCH V2 1/4] mtd: spi-nor: copy the SPI NOR commands to a new header file Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` [PATCH V2 2/4] mtd: spi-nor: add the basic data structures Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` Huang Shijie
[not found] ` <1386318764-15882-3-git-send-email-b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2013-12-10 13:07 ` Marek Vasut
2013-12-10 13:07 ` Marek Vasut
2013-12-10 13:07 ` Marek Vasut
[not found] ` <201312101407.59958.marex-ynQEQJNshbs@public.gmane.org>
2013-12-11 6:24 ` Huang Shijie
2013-12-11 6:24 ` Huang Shijie
2013-12-11 6:24 ` Huang Shijie
[not found] ` <20131211062428.GA25147-Fb7DQEYuewWctlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2013-12-11 10:02 ` Marek Vasut
2013-12-11 10:02 ` Marek Vasut
2013-12-11 10:02 ` Marek Vasut
[not found] ` <201312111102.18554.marex-ynQEQJNshbs@public.gmane.org>
2013-12-11 11:53 ` Lee Jones
2013-12-11 11:53 ` Lee Jones
2013-12-11 11:53 ` Lee Jones
2013-12-11 14:33 ` Huang Shijie
2013-12-11 14:33 ` Huang Shijie
2013-12-11 14:33 ` Huang Shijie
[not found] ` <20131211143356.GA1719-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-12-11 14:36 ` Marek Vasut
2013-12-11 14:36 ` Marek Vasut
2013-12-11 14:36 ` Marek Vasut
2013-12-06 8:32 ` [PATCH V2 3/4] mtd: spi-nor: add the framework for SPI NOR Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` [PATCH] mtd: m25p80: use the SPI nor framework Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-06 8:32 ` Huang Shijie
2013-12-11 15:16 ` [PATCH V2 0/4] mtd: spi-nor: add a new framework for SPI NOR Sourav Poddar
2013-12-11 15:16 ` Sourav Poddar
2013-12-11 15:16 ` Sourav Poddar
[not found] ` <52A881CF.4020001-l0cyMroinI0@public.gmane.org>
2013-12-12 4:14 ` Huang Shijie
2013-12-12 4:14 ` Huang Shijie
2013-12-12 4:14 ` Huang Shijie
2013-12-12 5:22 ` Sourav Poddar
2013-12-12 5:22 ` Sourav Poddar
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