Supporting fused display configurations v3

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* Supporting fused display configurations v3
@ 2013-12-12 14:36 Damien Lespiau
  2013-12-12 14:36 ` [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag Damien Lespiau
                   ` (8 more replies)
  0 siblings, 9 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

v3, following up a couple of review comments from Ville:
  http://lists.freedesktop.org/archives/intel-gfx/2013-December/037313.html

Changes:
  - Always use INTEL_INFO() after initialization to access dev_priv->info
    (well, except in the reg macros, where it's just too impractical),
  - Cast the device_info pointer returned by INTEL_INFO() to be const to cast
    potential writes by code using the macro,
  - Renamed num_plane to num_sprites as num_planes would imply we're counting
    the primary plane there, but we're not.

-- 
Damien

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-17  9:38   ` Daniel Vetter
  2013-12-12 14:36 ` [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure Damien Lespiau
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c01d08d..351065d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3584,9 +3584,11 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (dev_priv->info->is_valleyview)
+		if (IS_VALLEYVIEW(dev))
 			valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
@@ -3597,9 +3599,11 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_boost(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (dev_priv->info->is_valleyview)
+		if (IS_VALLEYVIEW(dev))
 			valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag
  2013-12-12 14:36 ` [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag Damien Lespiau
@ 2013-12-17  9:38   ` Daniel Vetter
  2013-12-17 11:17     ` Damien Lespiau
  0 siblings, 1 reply; 20+ messages in thread
From: Daniel Vetter @ 2013-12-17  9:38 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Thu, Dec 12, 2013 at 02:36:36PM +0000, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Merged this one here, not really sure what to do with the rest.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c01d08d..351065d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3584,9 +3584,11 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
>  
>  void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  {
> +	struct drm_device *dev = dev_priv->dev;
> +
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (dev_priv->rps.enabled) {
> -		if (dev_priv->info->is_valleyview)
> +		if (IS_VALLEYVIEW(dev))
>  			valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
>  		else
>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> @@ -3597,9 +3599,11 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  
>  void gen6_rps_boost(struct drm_i915_private *dev_priv)
>  {
> +	struct drm_device *dev = dev_priv->dev;
> +
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	if (dev_priv->rps.enabled) {
> -		if (dev_priv->info->is_valleyview)
> +		if (IS_VALLEYVIEW(dev))
>  			valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
>  		else
>  			gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag
  2013-12-17  9:38   ` Daniel Vetter
@ 2013-12-17 11:17     ` Damien Lespiau
  2013-12-17 12:18       ` Daniel Vetter
  0 siblings, 1 reply; 20+ messages in thread
From: Damien Lespiau @ 2013-12-17 11:17 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx

On Tue, Dec 17, 2013 at 10:38:48AM +0100, Daniel Vetter wrote:
> On Thu, Dec 12, 2013 at 02:36:36PM +0000, Damien Lespiau wrote:
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> Merged this one here, not really sure what to do with the rest.

So, apparently, there's some unhappiness with INTEL_INFO, which is
somewhat understandable, it doesn't provide much more convenience than
dev_priv->info.

I can resend the series getting rid of INTEL_INFO() if the sentiment is
shared. To provide the const safety, we can then declare the info struct
as const in the private structure and cast it as non const at
initialization time (as Ville suggests).

-- 
Damien

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag
  2013-12-17 11:17     ` Damien Lespiau
@ 2013-12-17 12:18       ` Daniel Vetter
  0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2013-12-17 12:18 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Tue, Dec 17, 2013 at 12:17 PM, Damien Lespiau
<damien.lespiau@intel.com> wrote:
> On Tue, Dec 17, 2013 at 10:38:48AM +0100, Daniel Vetter wrote:
>> On Thu, Dec 12, 2013 at 02:36:36PM +0000, Damien Lespiau wrote:
>> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>>
>> Merged this one here, not really sure what to do with the rest.
>
> So, apparently, there's some unhappiness with INTEL_INFO, which is
> somewhat understandable, it doesn't provide much more convenience than
> dev_priv->info.
>
> I can resend the series getting rid of INTEL_INFO() if the sentiment is
> shared. To provide the const safety, we can then declare the info struct
> as const in the private structure and cast it as non const at
> initialization time (as Ville suggests).

I'd be ok with that plan. Like I've said on irc, no opinions really on
this matter, as long as we can keep the const safety around - imo that
helps a lot with reviewing code. E.g. Chris just spotted that some of
Ben's semaphore changes aren't too safe since we can frob semaphores
at runtime.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
  2013-12-12 14:36 ` [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 16:58   ` Chris Wilson
  2013-12-12 14:36 ` [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable Damien Lespiau
                   ` (6 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

If we make sure that all the dev_priv->info usages are wrapped by
INTEL_INFO(), we can easily modify the ->info field to be structure and
not a pointer while keeping the const protection in the INTEL_INFO()
macro.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c      |  5 +++--
 drivers/gpu/drm/i915/i915_irq.c      |  4 ++--
 drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++------------
 drivers/gpu/drm/i915/intel_pm.c      | 13 +++++++++----
 4 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4ecfbf7..5fc0b83 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1014,7 +1014,8 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 			struct timespec *timeout,
 			struct drm_i915_file_private *file_priv)
 {
-	drm_i915_private_t *dev_priv = ring->dev->dev_private;
+	struct drm_device *dev = ring->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct timespec before, now;
 	DEFINE_WAIT(wait);
 	long timeout_jiffies;
@@ -1027,7 +1028,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 
 	timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1;
 
-	if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
+	if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
 		gen6_rps_boost(dev_priv);
 		if (file_priv)
 			mod_delayed_work(dev_priv->wq,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d44c79..8ed7edf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2209,7 +2209,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
 				     PIPE_VBLANK_INTERRUPT_ENABLE);
 
 	/* maintain vblank delivery even in deep C-states */
-	if (dev_priv->info->gen == 3)
+	if (INTEL_INFO(dev)->gen == 3)
 		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
@@ -2281,7 +2281,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
 	unsigned long irqflags;
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	if (dev_priv->info->gen == 3)
+	if (INTEL_INFO(dev)->gen == 3)
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
 
 	i915_disable_pipestat(dev_priv, pipe,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5c4c3ca..34dc0d6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1030,7 +1030,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	/* ILK FDI PLL is always enabled */
-	if (dev_priv->info->gen == 5)
+	if (INTEL_INFO(dev_priv->dev)->gen == 5)
 		return;
 
 	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -1433,7 +1433,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
-	BUG_ON(dev_priv->info->gen >= 5);
+	BUG_ON(INTEL_INFO(dev)->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev) && !IS_I830(dev))
@@ -1536,11 +1536,12 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  */
 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
-	BUG_ON(dev_priv->info->gen < 5);
+	BUG_ON(INTEL_INFO(dev)->gen < 5);
 	if (WARN_ON(pll == NULL))
 		return;
 
@@ -1565,11 +1566,12 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 
 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
 	/* PCH only available on ILK+ */
-	BUG_ON(dev_priv->info->gen < 5);
+	BUG_ON(INTEL_INFO(dev)->gen < 5);
 	if (WARN_ON(pll == NULL))
 	       return;
 
@@ -1604,7 +1606,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	uint32_t reg, val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
-	BUG_ON(dev_priv->info->gen < 5);
+	BUG_ON(INTEL_INFO(dev)->gen < 5);
 
 	/* Make sure PCH DPLL is enabled */
 	assert_shared_dpll_enabled(dev_priv,
@@ -1657,7 +1659,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	u32 val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
-	BUG_ON(dev_priv->info->gen < 5);
+	BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@@ -1838,7 +1840,8 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 			       enum plane plane)
 {
-	u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
+	struct drm_device *dev = dev_priv->dev;
+	u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
 
 	I915_WRITE(reg, I915_READ(reg));
 	POSTING_READ(reg);
@@ -7532,7 +7535,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!dev_priv->info->cursor_needs_physical) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical) {
 		unsigned alignment;
 
 		if (obj->tiling_mode) {
@@ -7580,7 +7583,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 
  finish:
 	if (intel_crtc->cursor_bo) {
-		if (dev_priv->info->cursor_needs_physical) {
+		if (INTEL_INFO(dev)->cursor_needs_physical) {
 			if (intel_crtc->cursor_bo != obj)
 				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
 		} else
@@ -8163,7 +8166,7 @@ void intel_mark_idle(struct drm_device *dev)
 		intel_decrease_pllclock(crtc);
 	}
 
-	if (dev_priv->info->gen >= 6)
+	if (INTEL_INFO(dev)->gen >= 6)
 		gen6_rps_idle(dev->dev_private);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 351065d..cc21796 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4370,9 +4370,10 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
 
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
 	unsigned long val;
 
-	if (dev_priv->info->gen != 5)
+	if (INTEL_INFO(dev)->gen != 5)
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
@@ -4401,6 +4402,7 @@ unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
 
 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
 {
+	struct drm_device *dev = dev_priv->dev;
 	static const struct v_table {
 		u16 vd; /* in .1 mil */
 		u16 vm; /* in .1 mil */
@@ -4534,7 +4536,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
 		{ 16000, 14875, },
 		{ 16125, 15000, },
 	};
-	if (dev_priv->info->is_mobile)
+	if (INTEL_INFO(dev)->is_mobile)
 		return v_table[pxvid].vm;
 	else
 		return v_table[pxvid].vd;
@@ -4577,7 +4579,9 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
 
 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
 {
-	if (dev_priv->info->gen != 5)
+	struct drm_device *dev = dev_priv->dev;
+
+	if (INTEL_INFO(dev)->gen != 5)
 		return;
 
 	spin_lock_irq(&mchdev_lock);
@@ -4626,9 +4630,10 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
 
 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
 	unsigned long val;
 
-	if (dev_priv->info->gen != 5)
+	if (INTEL_INFO(dev)->gen != 5)
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure
  2013-12-12 14:36 ` [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure Damien Lespiau
@ 2013-12-12 16:58   ` Chris Wilson
  2013-12-12 17:05     ` Damien Lespiau
  0 siblings, 1 reply; 20+ messages in thread
From: Chris Wilson @ 2013-12-12 16:58 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Thu, Dec 12, 2013 at 02:36:37PM +0000, Damien Lespiau wrote:
> If we make sure that all the dev_priv->info usages are wrapped by
> INTEL_INFO(), we can easily modify the ->info field to be structure and
> not a pointer while keeping the const protection in the INTEL_INFO()
> macro.

Yuck.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure
  2013-12-12 16:58   ` Chris Wilson
@ 2013-12-12 17:05     ` Damien Lespiau
  2013-12-12 17:23       ` Chris Wilson
  0 siblings, 1 reply; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 17:05 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

On Thu, Dec 12, 2013 at 04:58:21PM +0000, Chris Wilson wrote:
> On Thu, Dec 12, 2013 at 02:36:37PM +0000, Damien Lespiau wrote:
> > If we make sure that all the dev_priv->info usages are wrapped by
> > INTEL_INFO(), we can easily modify the ->info field to be structure and
> > not a pointer while keeping the const protection in the INTEL_INFO()
> > macro.
> 
> Yuck.

Would Jani's suggestion to transmogrify INTEL_INFO() into a function
make you happier? Or is it the back and forth from *dev_priv to *dev
to dev_priv->info that is of utmost disgust?

-- 
Damien

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure
  2013-12-12 17:05     ` Damien Lespiau
@ 2013-12-12 17:23       ` Chris Wilson
  2013-12-12 18:47         ` Ville Syrjälä
  0 siblings, 1 reply; 20+ messages in thread
From: Chris Wilson @ 2013-12-12 17:23 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Thu, Dec 12, 2013 at 05:05:18PM +0000, Damien Lespiau wrote:
> On Thu, Dec 12, 2013 at 04:58:21PM +0000, Chris Wilson wrote:
> > On Thu, Dec 12, 2013 at 02:36:37PM +0000, Damien Lespiau wrote:
> > > If we make sure that all the dev_priv->info usages are wrapped by
> > > INTEL_INFO(), we can easily modify the ->info field to be structure and
> > > not a pointer while keeping the const protection in the INTEL_INFO()
> > > macro.
> > 
> > Yuck.
> 
> Would Jani's suggestion to transmogrify INTEL_INFO() into a function
> make you happier? Or is it the back and forth from *dev_priv to *dev
> to dev_priv->info that is of utmost disgust?

Ultimately, I'd like to see the pointer dance die. But in the meantime,
I'd like to see the macro die, dev_priv->info is far less scary than
INTEL_INFO(dev_priv->dev)->info, even to_i915(dev)->info is more
pleasant to read.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure
  2013-12-12 17:23       ` Chris Wilson
@ 2013-12-12 18:47         ` Ville Syrjälä
  0 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjälä @ 2013-12-12 18:47 UTC (permalink / raw)
  To: Chris Wilson, Damien Lespiau, intel-gfx

On Thu, Dec 12, 2013 at 05:23:08PM +0000, Chris Wilson wrote:
> On Thu, Dec 12, 2013 at 05:05:18PM +0000, Damien Lespiau wrote:
> > On Thu, Dec 12, 2013 at 04:58:21PM +0000, Chris Wilson wrote:
> > > On Thu, Dec 12, 2013 at 02:36:37PM +0000, Damien Lespiau wrote:
> > > > If we make sure that all the dev_priv->info usages are wrapped by
> > > > INTEL_INFO(), we can easily modify the ->info field to be structure and
> > > > not a pointer while keeping the const protection in the INTEL_INFO()
> > > > macro.
> > > 
> > > Yuck.
> > 
> > Would Jani's suggestion to transmogrify INTEL_INFO() into a function
> > make you happier? Or is it the back and forth from *dev_priv to *dev
> > to dev_priv->info that is of utmost disgust?
> 
> Ultimately, I'd like to see the pointer dance die. But in the meantime,
> I'd like to see the macro die, dev_priv->info is far less scary than
> INTEL_INFO(dev_priv->dev)->info, even to_i915(dev)->info is more
> pleasant to read.

I guess another option would be to make keep the dev_priv.info as a
const struct, and just explicitly cast the const away when modifying
the struct.

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
  2013-12-12 14:36 ` [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag Damien Lespiau
  2013-12-12 14:36 ` [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 15:30   ` Jani Nikula
  2013-12-12 16:58   ` Ville Syrjälä
  2013-12-12 14:36 ` [PATCH 4/8] drm/i915: Move num_plane to the intel_device_info structure Damien Lespiau
                   ` (5 subsequent siblings)
  8 siblings, 2 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

Turns out it'd be nice to change some device information at run-time or
simply have some code to fill in the info struct instead of having to
declare the values in 30+ structures.

What prompted this change is handling fused out display/pipe and
tweaking num_pipes at run-time, but I'm quite sure we'll find other
flags/limits to stick into dev_priv->info.

Most of the changes were done with a sed:
sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch]

with a few tweaks to make it all work:
  - Change the field definition in struct drm_i915_private
  - adjust i915_dump_device_info()
  - adjust i915_driver_load()
  - adjust the INTEL_INFO() macro

v2: cast the info pointer returned by INTEL_INFO() to be const to catch
    uses that would modify the structure post-initialization.
    (Ville Syrjälä)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c |   4 +-
 drivers/gpu/drm/i915/i915_drv.h |   4 +-
 drivers/gpu/drm/i915/i915_reg.h | 228 ++++++++++++++++++++--------------------
 3 files changed, 118 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index bfbf9fc..332d5b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1442,7 +1442,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 
 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 {
-	const struct intel_device_info *info = dev_priv->info;
+	const struct intel_device_info *info = &dev_priv->info;
 
 #define PRINT_S(name) "%s"
 #define SEP_EMPTY
@@ -1492,7 +1492,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	dev->dev_private = (void *)dev_priv;
 	dev_priv->dev = dev;
-	dev_priv->info = info;
+	memcpy(&dev_priv->info, info, sizeof(*info));
 
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 46072b9..a66245a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1327,7 +1327,7 @@ typedef struct drm_i915_private {
 	struct drm_device *dev;
 	struct kmem_cache *slab;
 
-	const struct intel_device_info *info;
+	struct intel_device_info info;
 
 	int relative_constants_mode;
 
@@ -1751,7 +1751,7 @@ struct drm_i915_file_private {
 	atomic_t rps_wait_boost;
 };
 
-#define INTEL_INFO(dev)	(to_i915(dev)->info)
+#define INTEL_INFO(dev)	((const struct intel_device_info *)&to_i915(dev)->info)
 
 #define IS_I830(dev)		((dev)->pdev->device == 0x3577)
 #define IS_845G(dev)		((dev)->pdev->device == 0x2562)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8cc27c..67e9673 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1213,8 +1213,8 @@
 #define   VGA1_PD_P1_DIV_2	(1 << 13)
 #define   VGA1_PD_P1_SHIFT	8
 #define   VGA1_PD_P1_MASK	(0x1f << 8)
-#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
-#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
+#define _DPLL_A	(dev_priv->info.display_mmio_offset + 0x6014)
+#define _DPLL_B	(dev_priv->info.display_mmio_offset + 0x6018)
 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
 #define   DPLL_VCO_ENABLE		(1 << 31)
 #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
@@ -1277,7 +1277,7 @@
 #define   SDVO_MULTIPLIER_MASK			0x000000ff
 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
-#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
+#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) /* 965+ only */
 /*
  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  *
@@ -1314,7 +1314,7 @@
  */
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
-#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
+#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) /* 965+ only */
 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
 
 #define _FPA0	0x06040
@@ -1347,7 +1347,7 @@
 #define  DSTATE_PLL_D3_OFF			(1<<3)
 #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
 #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
-#define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
@@ -1472,8 +1472,8 @@
  * Palette regs
  */
 
-#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
-#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
+#define _PALETTE_A		(dev_priv->info.display_mmio_offset + 0xa000)
+#define _PALETTE_B		(dev_priv->info.display_mmio_offset + 0xa800)
 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
 
 /* MCH MMIO space */
@@ -1861,7 +1861,7 @@
  */
 
 /* Pipe A CRC regs */
-#define _PIPE_CRC_CTL_A		(dev_priv->info->display_mmio_offset + 0x60050)
+#define _PIPE_CRC_CTL_A		(dev_priv->info.display_mmio_offset + 0x60050)
 #define   PIPE_CRC_ENABLE		(1 << 31)
 /* ivb+ source selection */
 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
@@ -1901,11 +1901,11 @@
 #define _PIPE_CRC_RES_4_A_IVB		0x60070
 #define _PIPE_CRC_RES_5_A_IVB		0x60074
 
-#define _PIPE_CRC_RES_RED_A		(dev_priv->info->display_mmio_offset + 0x60060)
-#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info->display_mmio_offset + 0x60064)
-#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info->display_mmio_offset + 0x60068)
-#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info->display_mmio_offset + 0x6006c)
-#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info->display_mmio_offset + 0x60080)
+#define _PIPE_CRC_RES_RED_A		(dev_priv->info.display_mmio_offset + 0x60060)
+#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info.display_mmio_offset + 0x60064)
+#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info.display_mmio_offset + 0x60068)
+#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info.display_mmio_offset + 0x6006c)
+#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info.display_mmio_offset + 0x60080)
 
 /* Pipe B CRC regs */
 #define _PIPE_CRC_RES_1_B_IVB		0x61064
@@ -1938,26 +1938,26 @@
 	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
 
 /* Pipe A timing regs */
-#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
-#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
-#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
-#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
-#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
-#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
-#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
-#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
-#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
+#define _HTOTAL_A	(dev_priv->info.display_mmio_offset + 0x60000)
+#define _HBLANK_A	(dev_priv->info.display_mmio_offset + 0x60004)
+#define _HSYNC_A	(dev_priv->info.display_mmio_offset + 0x60008)
+#define _VTOTAL_A	(dev_priv->info.display_mmio_offset + 0x6000c)
+#define _VBLANK_A	(dev_priv->info.display_mmio_offset + 0x60010)
+#define _VSYNC_A	(dev_priv->info.display_mmio_offset + 0x60014)
+#define _PIPEASRC	(dev_priv->info.display_mmio_offset + 0x6001c)
+#define _BCLRPAT_A	(dev_priv->info.display_mmio_offset + 0x60020)
+#define _VSYNCSHIFT_A	(dev_priv->info.display_mmio_offset + 0x60028)
 
 /* Pipe B timing regs */
-#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
-#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
-#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
-#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
-#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
-#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
-#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
-#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
-#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
+#define _HTOTAL_B	(dev_priv->info.display_mmio_offset + 0x61000)
+#define _HBLANK_B	(dev_priv->info.display_mmio_offset + 0x61004)
+#define _HSYNC_B	(dev_priv->info.display_mmio_offset + 0x61008)
+#define _VTOTAL_B	(dev_priv->info.display_mmio_offset + 0x6100c)
+#define _VBLANK_B	(dev_priv->info.display_mmio_offset + 0x61010)
+#define _VSYNC_B	(dev_priv->info.display_mmio_offset + 0x61014)
+#define _PIPEBSRC	(dev_priv->info.display_mmio_offset + 0x6101c)
+#define _BCLRPAT_B	(dev_priv->info.display_mmio_offset + 0x61020)
+#define _VSYNCSHIFT_B	(dev_priv->info.display_mmio_offset + 0x61028)
 
 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
@@ -2083,7 +2083,7 @@
 
 
 /* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
@@ -2113,7 +2113,7 @@
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 
-#define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
 /*
  * HDMI/DP bits are gen4+
  *
@@ -2385,7 +2385,7 @@
 #define PP_DIVISOR	0x61210
 
 /* Panel fitting */
-#define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
+#define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
 #define   PFIT_ENABLE		(1 << 31)
 #define   PFIT_PIPE_MASK	(3 << 29)
 #define   PFIT_PIPE_SHIFT	29
@@ -2403,7 +2403,7 @@
 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
 #define   PFIT_SCALING_PILLAR	(2 << 26)
 #define   PFIT_SCALING_LETTER	(3 << 26)
-#define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
 /* Pre-965 */
 #define		PFIT_VERT_SCALE_SHIFT		20
 #define		PFIT_VERT_SCALE_MASK		0xfff00000
@@ -2415,25 +2415,25 @@
 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
 
-#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
 
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
 				     _VLV_BLC_PWM_CTL2_B)
 
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
 				    _VLV_BLC_PWM_CTL_B)
 
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
 				     _VLV_BLC_HIST_CTL_B)
 
 /* Backlight control */
-#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT		(1 << 29)
@@ -2456,7 +2456,7 @@
 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.
@@ -2478,7 +2478,7 @@
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -3172,10 +3172,10 @@
 /* Display & cursor control */
 
 /* Pipe A */
-#define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
+#define _PIPEADSL		(dev_priv->info.display_mmio_offset + 0x70000)
 #define   DSL_LINEMASK_GEN2	0x00000fff
 #define   DSL_LINEMASK_GEN3	0x00001fff
-#define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
+#define _PIPEACONF		(dev_priv->info.display_mmio_offset + 0x70008)
 #define   PIPECONF_ENABLE	(1<<31)
 #define   PIPECONF_DISABLE	0
 #define   PIPECONF_DOUBLE_WIDE	(1<<30)
@@ -3218,7 +3218,7 @@
 #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
 #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
-#define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
+#define _PIPEASTAT		(dev_priv->info.display_mmio_offset + 0x70024)
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
 #define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
@@ -3317,7 +3317,7 @@
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
-#define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
+#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT	23
 #define   DSPFW_SR_MASK		(0x1ff<<23)
 #define   DSPFW_CURSORB_SHIFT	16
@@ -3325,11 +3325,11 @@
 #define   DSPFW_PLANEB_SHIFT	8
 #define   DSPFW_PLANEB_MASK	(0x7f<<8)
 #define   DSPFW_PLANEA_MASK	(0x7f)
-#define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
+#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
 #define   DSPFW_CURSORA_MASK	0x00003f00
 #define   DSPFW_CURSORA_SHIFT	8
 #define   DSPFW_PLANEC_MASK	(0x7f)
-#define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
+#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
 #define   DSPFW_HPLL_SR_EN	(1<<31)
 #define   DSPFW_CURSOR_SR_SHIFT	24
 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
@@ -3337,8 +3337,8 @@
 #define   DSPFW_HPLL_CURSOR_SHIFT	16
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
-#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
-#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
+#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
+#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
@@ -3498,12 +3498,12 @@
 #define   PIPE_PIXEL_MASK         0x00ffffff
 #define   PIPE_PIXEL_SHIFT        0
 /* GM45+ just has to be different */
-#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70040)
-#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70044)
+#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70040)
+#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70044)
 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
 
 /* Cursor A & B regs */
-#define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
+#define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)
 /* Old style CUR*CNTR flags (desktop 8xx) */
 #define   CURSOR_ENABLE		0x80000000
 #define   CURSOR_GAMMA_ENABLE	0x40000000
@@ -3526,16 +3526,16 @@
 #define   MCURSOR_PIPE_B	(1 << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
 #define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
-#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
-#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
+#define _CURABASE		(dev_priv->info.display_mmio_offset + 0x70084)
+#define _CURAPOS		(dev_priv->info.display_mmio_offset + 0x70088)
 #define   CURSOR_POS_MASK       0x007FF
 #define   CURSOR_POS_SIGN       0x8000
 #define   CURSOR_X_SHIFT        0
 #define   CURSOR_Y_SHIFT        16
 #define CURSIZE			0x700a0
-#define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
-#define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
-#define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
+#define _CURBCNTR		(dev_priv->info.display_mmio_offset + 0x700c0)
+#define _CURBBASE		(dev_priv->info.display_mmio_offset + 0x700c4)
+#define _CURBPOS		(dev_priv->info.display_mmio_offset + 0x700c8)
 
 #define _CURBCNTR_IVB		0x71080
 #define _CURBBASE_IVB		0x71084
@@ -3550,7 +3550,7 @@
 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
 
 /* Display A control */
-#define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
+#define _DSPACNTR                (dev_priv->info.display_mmio_offset + 0x70180)
 #define   DISPLAY_PLANE_ENABLE			(1<<31)
 #define   DISPLAY_PLANE_DISABLE			0
 #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
@@ -3584,14 +3584,14 @@
 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
 #define   DISPPLANE_TILED			(1<<10)
-#define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
-#define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
-#define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
-#define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
-#define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
-#define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
-#define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
-#define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
+#define _DSPAADDR		(dev_priv->info.display_mmio_offset + 0x70184)
+#define _DSPASTRIDE		(dev_priv->info.display_mmio_offset + 0x70188)
+#define _DSPAPOS		(dev_priv->info.display_mmio_offset + 0x7018C) /* reserved */
+#define _DSPASIZE		(dev_priv->info.display_mmio_offset + 0x70190)
+#define _DSPASURF		(dev_priv->info.display_mmio_offset + 0x7019C) /* 965+ only */
+#define _DSPATILEOFF		(dev_priv->info.display_mmio_offset + 0x701A4) /* 965+ only */
+#define _DSPAOFFSET		(dev_priv->info.display_mmio_offset + 0x701A4) /* HSW */
+#define _DSPASURFLIVE		(dev_priv->info.display_mmio_offset + 0x701AC)
 
 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
@@ -3612,44 +3612,44 @@
 		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
 
 /* VBIOS flags */
-#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
-#define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
-#define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
-#define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
-#define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
-#define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
-#define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
-#define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
-#define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
-#define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
-#define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
-#define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
-#define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
+#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
+#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
+#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
+#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
+#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
+#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
+#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
+#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
+#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
+#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
+#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
+#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
+#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
 
 /* Pipe B */
-#define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
-#define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
-#define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
+#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
+#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
+#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
 
 
 /* Display B control */
-#define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
+#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
-#define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
-#define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
-#define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
-#define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
+#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
+#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
+#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
+#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
 
 /* Sprite A control */
 #define _DVSACNTR		0x72180
@@ -3898,39 +3898,39 @@
 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
 
 
-#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
+#define _PIPEA_DATA_M1           (dev_priv->info.display_mmio_offset + 0x60030)
 #define  PIPE_DATA_M1_OFFSET    0
-#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
+#define _PIPEA_DATA_N1           (dev_priv->info.display_mmio_offset + 0x60034)
 #define  PIPE_DATA_N1_OFFSET    0
 
-#define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
+#define _PIPEA_DATA_M2           (dev_priv->info.display_mmio_offset + 0x60038)
 #define  PIPE_DATA_M2_OFFSET    0
-#define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
+#define _PIPEA_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6003c)
 #define  PIPE_DATA_N2_OFFSET    0
 
-#define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
+#define _PIPEA_LINK_M1           (dev_priv->info.display_mmio_offset + 0x60040)
 #define  PIPE_LINK_M1_OFFSET    0
-#define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
+#define _PIPEA_LINK_N1           (dev_priv->info.display_mmio_offset + 0x60044)
 #define  PIPE_LINK_N1_OFFSET    0
 
-#define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
+#define _PIPEA_LINK_M2           (dev_priv->info.display_mmio_offset + 0x60048)
 #define  PIPE_LINK_M2_OFFSET    0
-#define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
+#define _PIPEA_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6004c)
 #define  PIPE_LINK_N2_OFFSET    0
 
 /* PIPEB timing regs are same start from 0x61000 */
 
-#define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
-#define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
+#define _PIPEB_DATA_M1           (dev_priv->info.display_mmio_offset + 0x61030)
+#define _PIPEB_DATA_N1           (dev_priv->info.display_mmio_offset + 0x61034)
 
-#define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
-#define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
+#define _PIPEB_DATA_M2           (dev_priv->info.display_mmio_offset + 0x61038)
+#define _PIPEB_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6103c)
 
-#define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
-#define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
+#define _PIPEB_LINK_M1           (dev_priv->info.display_mmio_offset + 0x61040)
+#define _PIPEB_LINK_N1           (dev_priv->info.display_mmio_offset + 0x61044)
 
-#define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
-#define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
+#define _PIPEB_LINK_M2           (dev_priv->info.display_mmio_offset + 0x61048)
+#define _PIPEB_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6104c)
 
 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
@@ -5041,7 +5041,7 @@
 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
 
-#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
 #define INTEL_AUDIO_DEVCL		0x808629FB
 #define INTEL_AUDIO_DEVBLC		0x80862801
 #define INTEL_AUDIO_DEVCTG		0x80862802
-- 
1.8.3.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable
  2013-12-12 14:36 ` [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable Damien Lespiau
@ 2013-12-12 15:30   ` Jani Nikula
  2013-12-12 15:38     ` Damien Lespiau
  2013-12-12 16:58   ` Ville Syrjälä
  1 sibling, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2013-12-12 15:30 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx

On Thu, 12 Dec 2013, Damien Lespiau <damien.lespiau@intel.com> wrote:
> Turns out it'd be nice to change some device information at run-time or
> simply have some code to fill in the info struct instead of having to
> declare the values in 30+ structures.
>
> What prompted this change is handling fused out display/pipe and
> tweaking num_pipes at run-time, but I'm quite sure we'll find other
> flags/limits to stick into dev_priv->info.
>
> Most of the changes were done with a sed:
> sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch]
>
> with a few tweaks to make it all work:
>   - Change the field definition in struct drm_i915_private
>   - adjust i915_dump_device_info()
>   - adjust i915_driver_load()
>   - adjust the INTEL_INFO() macro
>
> v2: cast the info pointer returned by INTEL_INFO() to be const to catch
>     uses that would modify the structure post-initialization.
>     (Ville Syrjälä)
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c |   4 +-
>  drivers/gpu/drm/i915/i915_drv.h |   4 +-
>  drivers/gpu/drm/i915/i915_reg.h | 228 ++++++++++++++++++++--------------------
>  3 files changed, 118 insertions(+), 118 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index bfbf9fc..332d5b6 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1442,7 +1442,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
>  
>  static void i915_dump_device_info(struct drm_i915_private *dev_priv)
>  {
> -	const struct intel_device_info *info = dev_priv->info;
> +	const struct intel_device_info *info = &dev_priv->info;
>  
>  #define PRINT_S(name) "%s"
>  #define SEP_EMPTY
> @@ -1492,7 +1492,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  
>  	dev->dev_private = (void *)dev_priv;
>  	dev_priv->dev = dev;
> -	dev_priv->info = info;
> +	memcpy(&dev_priv->info, info, sizeof(*info));
>  
>  	spin_lock_init(&dev_priv->irq_lock);
>  	spin_lock_init(&dev_priv->gpu_error.lock);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 46072b9..a66245a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1327,7 +1327,7 @@ typedef struct drm_i915_private {
>  	struct drm_device *dev;
>  	struct kmem_cache *slab;
>  
> -	const struct intel_device_info *info;
> +	struct intel_device_info info;
>  
>  	int relative_constants_mode;
>  
> @@ -1751,7 +1751,7 @@ struct drm_i915_file_private {
>  	atomic_t rps_wait_boost;
>  };
>  
> -#define INTEL_INFO(dev)	(to_i915(dev)->info)
> +#define INTEL_INFO(dev)	((const struct intel_device_info *)&to_i915(dev)->info)

If that were an inline function you wouldn't have to cast to add const:

static inline const struct intel_device_info *
intel_info(const struct drm_device *dev)
{
        return to_i915(dev)->info;
}

I'm not insisting on this bikeshed, though.


BR,
Jani.


>  
>  #define IS_I830(dev)		((dev)->pdev->device == 0x3577)
>  #define IS_845G(dev)		((dev)->pdev->device == 0x2562)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e8cc27c..67e9673 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1213,8 +1213,8 @@
>  #define   VGA1_PD_P1_DIV_2	(1 << 13)
>  #define   VGA1_PD_P1_SHIFT	8
>  #define   VGA1_PD_P1_MASK	(0x1f << 8)
> -#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
> -#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
> +#define _DPLL_A	(dev_priv->info.display_mmio_offset + 0x6014)
> +#define _DPLL_B	(dev_priv->info.display_mmio_offset + 0x6018)
>  #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
> @@ -1277,7 +1277,7 @@
>  #define   SDVO_MULTIPLIER_MASK			0x000000ff
>  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
>  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
> -#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
> +#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) /* 965+ only */
>  /*
>   * UDI pixel divider, controlling how many pixels are stuffed into a packet.
>   *
> @@ -1314,7 +1314,7 @@
>   */
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
> -#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
> +#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) /* 965+ only */
>  #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
>  
>  #define _FPA0	0x06040
> @@ -1347,7 +1347,7 @@
>  #define  DSTATE_PLL_D3_OFF			(1<<3)
>  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
>  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> -#define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)
> +#define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
>  # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
>  # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
>  # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> @@ -1472,8 +1472,8 @@
>   * Palette regs
>   */
>  
> -#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
> -#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
> +#define _PALETTE_A		(dev_priv->info.display_mmio_offset + 0xa000)
> +#define _PALETTE_B		(dev_priv->info.display_mmio_offset + 0xa800)
>  #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
>  
>  /* MCH MMIO space */
> @@ -1861,7 +1861,7 @@
>   */
>  
>  /* Pipe A CRC regs */
> -#define _PIPE_CRC_CTL_A		(dev_priv->info->display_mmio_offset + 0x60050)
> +#define _PIPE_CRC_CTL_A		(dev_priv->info.display_mmio_offset + 0x60050)
>  #define   PIPE_CRC_ENABLE		(1 << 31)
>  /* ivb+ source selection */
>  #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
> @@ -1901,11 +1901,11 @@
>  #define _PIPE_CRC_RES_4_A_IVB		0x60070
>  #define _PIPE_CRC_RES_5_A_IVB		0x60074
>  
> -#define _PIPE_CRC_RES_RED_A		(dev_priv->info->display_mmio_offset + 0x60060)
> -#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info->display_mmio_offset + 0x60064)
> -#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info->display_mmio_offset + 0x60068)
> -#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info->display_mmio_offset + 0x6006c)
> -#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info->display_mmio_offset + 0x60080)
> +#define _PIPE_CRC_RES_RED_A		(dev_priv->info.display_mmio_offset + 0x60060)
> +#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info.display_mmio_offset + 0x60064)
> +#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info.display_mmio_offset + 0x60068)
> +#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info.display_mmio_offset + 0x6006c)
> +#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info.display_mmio_offset + 0x60080)
>  
>  /* Pipe B CRC regs */
>  #define _PIPE_CRC_RES_1_B_IVB		0x61064
> @@ -1938,26 +1938,26 @@
>  	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
>  
>  /* Pipe A timing regs */
> -#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
> -#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
> -#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
> -#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
> -#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
> -#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
> -#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
> -#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
> -#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
> +#define _HTOTAL_A	(dev_priv->info.display_mmio_offset + 0x60000)
> +#define _HBLANK_A	(dev_priv->info.display_mmio_offset + 0x60004)
> +#define _HSYNC_A	(dev_priv->info.display_mmio_offset + 0x60008)
> +#define _VTOTAL_A	(dev_priv->info.display_mmio_offset + 0x6000c)
> +#define _VBLANK_A	(dev_priv->info.display_mmio_offset + 0x60010)
> +#define _VSYNC_A	(dev_priv->info.display_mmio_offset + 0x60014)
> +#define _PIPEASRC	(dev_priv->info.display_mmio_offset + 0x6001c)
> +#define _BCLRPAT_A	(dev_priv->info.display_mmio_offset + 0x60020)
> +#define _VSYNCSHIFT_A	(dev_priv->info.display_mmio_offset + 0x60028)
>  
>  /* Pipe B timing regs */
> -#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
> -#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
> -#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
> -#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
> -#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
> -#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
> -#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
> -#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
> -#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
> +#define _HTOTAL_B	(dev_priv->info.display_mmio_offset + 0x61000)
> +#define _HBLANK_B	(dev_priv->info.display_mmio_offset + 0x61004)
> +#define _HSYNC_B	(dev_priv->info.display_mmio_offset + 0x61008)
> +#define _VTOTAL_B	(dev_priv->info.display_mmio_offset + 0x6100c)
> +#define _VBLANK_B	(dev_priv->info.display_mmio_offset + 0x61010)
> +#define _VSYNC_B	(dev_priv->info.display_mmio_offset + 0x61014)
> +#define _PIPEBSRC	(dev_priv->info.display_mmio_offset + 0x6101c)
> +#define _BCLRPAT_B	(dev_priv->info.display_mmio_offset + 0x61020)
> +#define _VSYNCSHIFT_B	(dev_priv->info.display_mmio_offset + 0x61028)
>  
>  #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
>  #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> @@ -2083,7 +2083,7 @@
>  
>  
>  /* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
> +#define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
>  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
>  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
>  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
> @@ -2113,7 +2113,7 @@
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
>  
> -#define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
> +#define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
>  /*
>   * HDMI/DP bits are gen4+
>   *
> @@ -2385,7 +2385,7 @@
>  #define PP_DIVISOR	0x61210
>  
>  /* Panel fitting */
> -#define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
> +#define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
>  #define   PFIT_ENABLE		(1 << 31)
>  #define   PFIT_PIPE_MASK	(3 << 29)
>  #define   PFIT_PIPE_SHIFT	29
> @@ -2403,7 +2403,7 @@
>  #define   PFIT_SCALING_PROGRAMMED (1 << 26)
>  #define   PFIT_SCALING_PILLAR	(2 << 26)
>  #define   PFIT_SCALING_LETTER	(3 << 26)
> -#define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
> +#define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
>  /* Pre-965 */
>  #define		PFIT_VERT_SCALE_SHIFT		20
>  #define		PFIT_VERT_SCALE_MASK		0xfff00000
> @@ -2415,25 +2415,25 @@
>  #define		PFIT_HORIZ_SCALE_SHIFT_965	0
>  #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
>  
> -#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
> +#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
>  
> -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
> -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
> +#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
> +#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
>  #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
>  				     _VLV_BLC_PWM_CTL2_B)
>  
> -#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
> -#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
> +#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
> +#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
>  #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
>  				    _VLV_BLC_PWM_CTL_B)
>  
> -#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
> -#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
> +#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
> +#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
>  #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
>  				     _VLV_BLC_HIST_CTL_B)
>  
>  /* Backlight control */
> -#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
> +#define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
>  #define   BLM_PWM_ENABLE		(1 << 31)
>  #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
>  #define   BLM_PIPE_SELECT		(1 << 29)
> @@ -2456,7 +2456,7 @@
>  #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
>  #define   BLM_PHASE_IN_INCR_SHIFT	(0)
>  #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
> -#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
> +#define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
>  /*
>   * This is the most significant 15 bits of the number of backlight cycles in a
>   * complete cycle of the modulated backlight control.
> @@ -2478,7 +2478,7 @@
>  #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
>  #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
>  
> -#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
> +#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
>  
>  /* New registers for PCH-split platforms. Safe where new bits show up, the
>   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> @@ -3172,10 +3172,10 @@
>  /* Display & cursor control */
>  
>  /* Pipe A */
> -#define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
> +#define _PIPEADSL		(dev_priv->info.display_mmio_offset + 0x70000)
>  #define   DSL_LINEMASK_GEN2	0x00000fff
>  #define   DSL_LINEMASK_GEN3	0x00001fff
> -#define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
> +#define _PIPEACONF		(dev_priv->info.display_mmio_offset + 0x70008)
>  #define   PIPECONF_ENABLE	(1<<31)
>  #define   PIPECONF_DISABLE	0
>  #define   PIPECONF_DOUBLE_WIDE	(1<<30)
> @@ -3218,7 +3218,7 @@
>  #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
>  #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
>  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
> -#define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
> +#define _PIPEASTAT		(dev_priv->info.display_mmio_offset + 0x70024)
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
>  #define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
> @@ -3317,7 +3317,7 @@
>  #define   DSPARB_BEND_SHIFT	9 /* on 855 */
>  #define   DSPARB_AEND_SHIFT	0
>  
> -#define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
> +#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
>  #define   DSPFW_SR_SHIFT	23
>  #define   DSPFW_SR_MASK		(0x1ff<<23)
>  #define   DSPFW_CURSORB_SHIFT	16
> @@ -3325,11 +3325,11 @@
>  #define   DSPFW_PLANEB_SHIFT	8
>  #define   DSPFW_PLANEB_MASK	(0x7f<<8)
>  #define   DSPFW_PLANEA_MASK	(0x7f)
> -#define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
> +#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
>  #define   DSPFW_CURSORA_MASK	0x00003f00
>  #define   DSPFW_CURSORA_SHIFT	8
>  #define   DSPFW_PLANEC_MASK	(0x7f)
> -#define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
> +#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
>  #define   DSPFW_HPLL_SR_EN	(1<<31)
>  #define   DSPFW_CURSOR_SR_SHIFT	24
>  #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
> @@ -3337,8 +3337,8 @@
>  #define   DSPFW_HPLL_CURSOR_SHIFT	16
>  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
>  #define   DSPFW_HPLL_SR_MASK		(0x1ff)
> -#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
> -#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
> +#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
> +#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
>  
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32	32
> @@ -3498,12 +3498,12 @@
>  #define   PIPE_PIXEL_MASK         0x00ffffff
>  #define   PIPE_PIXEL_SHIFT        0
>  /* GM45+ just has to be different */
> -#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70040)
> -#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70044)
> +#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70040)
> +#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70044)
>  #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
>  
>  /* Cursor A & B regs */
> -#define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
> +#define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)
>  /* Old style CUR*CNTR flags (desktop 8xx) */
>  #define   CURSOR_ENABLE		0x80000000
>  #define   CURSOR_GAMMA_ENABLE	0x40000000
> @@ -3526,16 +3526,16 @@
>  #define   MCURSOR_PIPE_B	(1 << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
>  #define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
> -#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
> -#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
> +#define _CURABASE		(dev_priv->info.display_mmio_offset + 0x70084)
> +#define _CURAPOS		(dev_priv->info.display_mmio_offset + 0x70088)
>  #define   CURSOR_POS_MASK       0x007FF
>  #define   CURSOR_POS_SIGN       0x8000
>  #define   CURSOR_X_SHIFT        0
>  #define   CURSOR_Y_SHIFT        16
>  #define CURSIZE			0x700a0
> -#define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
> -#define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
> -#define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
> +#define _CURBCNTR		(dev_priv->info.display_mmio_offset + 0x700c0)
> +#define _CURBBASE		(dev_priv->info.display_mmio_offset + 0x700c4)
> +#define _CURBPOS		(dev_priv->info.display_mmio_offset + 0x700c8)
>  
>  #define _CURBCNTR_IVB		0x71080
>  #define _CURBBASE_IVB		0x71084
> @@ -3550,7 +3550,7 @@
>  #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
>  
>  /* Display A control */
> -#define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
> +#define _DSPACNTR                (dev_priv->info.display_mmio_offset + 0x70180)
>  #define   DISPLAY_PLANE_ENABLE			(1<<31)
>  #define   DISPLAY_PLANE_DISABLE			0
>  #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
> @@ -3584,14 +3584,14 @@
>  #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
>  #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
>  #define   DISPPLANE_TILED			(1<<10)
> -#define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
> -#define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
> -#define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
> -#define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
> -#define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
> -#define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
> -#define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
> -#define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
> +#define _DSPAADDR		(dev_priv->info.display_mmio_offset + 0x70184)
> +#define _DSPASTRIDE		(dev_priv->info.display_mmio_offset + 0x70188)
> +#define _DSPAPOS		(dev_priv->info.display_mmio_offset + 0x7018C) /* reserved */
> +#define _DSPASIZE		(dev_priv->info.display_mmio_offset + 0x70190)
> +#define _DSPASURF		(dev_priv->info.display_mmio_offset + 0x7019C) /* 965+ only */
> +#define _DSPATILEOFF		(dev_priv->info.display_mmio_offset + 0x701A4) /* 965+ only */
> +#define _DSPAOFFSET		(dev_priv->info.display_mmio_offset + 0x701A4) /* HSW */
> +#define _DSPASURFLIVE		(dev_priv->info.display_mmio_offset + 0x701AC)
>  
>  #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
>  #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
> @@ -3612,44 +3612,44 @@
>  		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
>  
>  /* VBIOS flags */
> -#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
> -#define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
> -#define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
> -#define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
> -#define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
> -#define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
> -#define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
> -#define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
> -#define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
> -#define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
> -#define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
> -#define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
> -#define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
> +#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
> +#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
> +#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
> +#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
> +#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
> +#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
> +#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
> +#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
> +#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
> +#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
> +#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
> +#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
> +#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
>  
>  /* Pipe B */
> -#define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
> -#define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
> -#define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
> +#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> +#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
> +#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
> -#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71040)
> -#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71044)
> +#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
> +#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
>  
>  
>  /* Display B control */
> -#define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
> +#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
>  #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
>  #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
>  #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
>  #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
> -#define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
> -#define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
> -#define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
> -#define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
> -#define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
> -#define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
> -#define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
> -#define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
> +#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
> +#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
> +#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
> +#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
> +#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
> +#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
> +#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
> +#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
>  
>  /* Sprite A control */
>  #define _DVSACNTR		0x72180
> @@ -3898,39 +3898,39 @@
>  #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
>  
>  
> -#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
> +#define _PIPEA_DATA_M1           (dev_priv->info.display_mmio_offset + 0x60030)
>  #define  PIPE_DATA_M1_OFFSET    0
> -#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
> +#define _PIPEA_DATA_N1           (dev_priv->info.display_mmio_offset + 0x60034)
>  #define  PIPE_DATA_N1_OFFSET    0
>  
> -#define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
> +#define _PIPEA_DATA_M2           (dev_priv->info.display_mmio_offset + 0x60038)
>  #define  PIPE_DATA_M2_OFFSET    0
> -#define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
> +#define _PIPEA_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6003c)
>  #define  PIPE_DATA_N2_OFFSET    0
>  
> -#define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
> +#define _PIPEA_LINK_M1           (dev_priv->info.display_mmio_offset + 0x60040)
>  #define  PIPE_LINK_M1_OFFSET    0
> -#define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
> +#define _PIPEA_LINK_N1           (dev_priv->info.display_mmio_offset + 0x60044)
>  #define  PIPE_LINK_N1_OFFSET    0
>  
> -#define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
> +#define _PIPEA_LINK_M2           (dev_priv->info.display_mmio_offset + 0x60048)
>  #define  PIPE_LINK_M2_OFFSET    0
> -#define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
> +#define _PIPEA_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6004c)
>  #define  PIPE_LINK_N2_OFFSET    0
>  
>  /* PIPEB timing regs are same start from 0x61000 */
>  
> -#define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
> -#define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
> +#define _PIPEB_DATA_M1           (dev_priv->info.display_mmio_offset + 0x61030)
> +#define _PIPEB_DATA_N1           (dev_priv->info.display_mmio_offset + 0x61034)
>  
> -#define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
> -#define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
> +#define _PIPEB_DATA_M2           (dev_priv->info.display_mmio_offset + 0x61038)
> +#define _PIPEB_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6103c)
>  
> -#define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
> -#define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
> +#define _PIPEB_LINK_M1           (dev_priv->info.display_mmio_offset + 0x61040)
> +#define _PIPEB_LINK_N1           (dev_priv->info.display_mmio_offset + 0x61044)
>  
> -#define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
> -#define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
> +#define _PIPEB_LINK_M2           (dev_priv->info.display_mmio_offset + 0x61048)
> +#define _PIPEB_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6104c)
>  
>  #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
>  #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> @@ -5041,7 +5041,7 @@
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>  
> -#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
> +#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801
>  #define INTEL_AUDIO_DEVCTG		0x80862802
> -- 
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable
  2013-12-12 15:30   ` Jani Nikula
@ 2013-12-12 15:38     ` Damien Lespiau
  0 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 15:38 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Thu, Dec 12, 2013 at 05:30:14PM +0200, Jani Nikula wrote:
> > -#define INTEL_INFO(dev)	(to_i915(dev)->info)
> > +#define INTEL_INFO(dev)	((const struct intel_device_info *)&to_i915(dev)->info)
> 
> If that were an inline function you wouldn't have to cast to add const:
> 
> static inline const struct intel_device_info *
> intel_info(const struct drm_device *dev)
> {
>         return to_i915(dev)->info;
> }
> 
> I'm not insisting on this bikeshed, though.

True, I'd happily review a follow-up patch once the series has landed :)

-- 
Damien

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable
  2013-12-12 14:36 ` [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable Damien Lespiau
  2013-12-12 15:30   ` Jani Nikula
@ 2013-12-12 16:58   ` Ville Syrjälä
  1 sibling, 0 replies; 20+ messages in thread
From: Ville Syrjälä @ 2013-12-12 16:58 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Thu, Dec 12, 2013 at 02:36:38PM +0000, Damien Lespiau wrote:
> Turns out it'd be nice to change some device information at run-time or
> simply have some code to fill in the info struct instead of having to
> declare the values in 30+ structures.
> 
> What prompted this change is handling fused out display/pipe and
> tweaking num_pipes at run-time, but I'm quite sure we'll find other
> flags/limits to stick into dev_priv->info.
> 
> Most of the changes were done with a sed:
> sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch]
> 
> with a few tweaks to make it all work:
>   - Change the field definition in struct drm_i915_private
>   - adjust i915_dump_device_info()
>   - adjust i915_driver_load()
>   - adjust the INTEL_INFO() macro
> 
> v2: cast the info pointer returned by INTEL_INFO() to be const to catch
>     uses that would modify the structure post-initialization.
>     (Ville Syrjälä)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c |   4 +-
>  drivers/gpu/drm/i915/i915_drv.h |   4 +-
>  drivers/gpu/drm/i915/i915_reg.h | 228 ++++++++++++++++++++--------------------
>  3 files changed, 118 insertions(+), 118 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index bfbf9fc..332d5b6 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1442,7 +1442,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
>  
>  static void i915_dump_device_info(struct drm_i915_private *dev_priv)
>  {
> -	const struct intel_device_info *info = dev_priv->info;
> +	const struct intel_device_info *info = &dev_priv->info;
>  
>  #define PRINT_S(name) "%s"
>  #define SEP_EMPTY
> @@ -1492,7 +1492,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  
>  	dev->dev_private = (void *)dev_priv;
>  	dev_priv->dev = dev;
> -	dev_priv->info = info;
> +	memcpy(&dev_priv->info, info, sizeof(*info));

This could be just an assigment. The benefit would be type checking
from the compiler.

Otherwise the series looks good to me:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	spin_lock_init(&dev_priv->irq_lock);
>  	spin_lock_init(&dev_priv->gpu_error.lock);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 46072b9..a66245a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1327,7 +1327,7 @@ typedef struct drm_i915_private {
>  	struct drm_device *dev;
>  	struct kmem_cache *slab;
>  
> -	const struct intel_device_info *info;
> +	struct intel_device_info info;
>  
>  	int relative_constants_mode;
>  
> @@ -1751,7 +1751,7 @@ struct drm_i915_file_private {
>  	atomic_t rps_wait_boost;
>  };
>  
> -#define INTEL_INFO(dev)	(to_i915(dev)->info)
> +#define INTEL_INFO(dev)	((const struct intel_device_info *)&to_i915(dev)->info)
>  
>  #define IS_I830(dev)		((dev)->pdev->device == 0x3577)
>  #define IS_845G(dev)		((dev)->pdev->device == 0x2562)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e8cc27c..67e9673 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1213,8 +1213,8 @@
>  #define   VGA1_PD_P1_DIV_2	(1 << 13)
>  #define   VGA1_PD_P1_SHIFT	8
>  #define   VGA1_PD_P1_MASK	(0x1f << 8)
> -#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
> -#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
> +#define _DPLL_A	(dev_priv->info.display_mmio_offset + 0x6014)
> +#define _DPLL_B	(dev_priv->info.display_mmio_offset + 0x6018)
>  #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
> @@ -1277,7 +1277,7 @@
>  #define   SDVO_MULTIPLIER_MASK			0x000000ff
>  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
>  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
> -#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
> +#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) /* 965+ only */
>  /*
>   * UDI pixel divider, controlling how many pixels are stuffed into a packet.
>   *
> @@ -1314,7 +1314,7 @@
>   */
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
> -#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
> +#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) /* 965+ only */
>  #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
>  
>  #define _FPA0	0x06040
> @@ -1347,7 +1347,7 @@
>  #define  DSTATE_PLL_D3_OFF			(1<<3)
>  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
>  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> -#define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)
> +#define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
>  # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
>  # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
>  # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> @@ -1472,8 +1472,8 @@
>   * Palette regs
>   */
>  
> -#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
> -#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
> +#define _PALETTE_A		(dev_priv->info.display_mmio_offset + 0xa000)
> +#define _PALETTE_B		(dev_priv->info.display_mmio_offset + 0xa800)
>  #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
>  
>  /* MCH MMIO space */
> @@ -1861,7 +1861,7 @@
>   */
>  
>  /* Pipe A CRC regs */
> -#define _PIPE_CRC_CTL_A		(dev_priv->info->display_mmio_offset + 0x60050)
> +#define _PIPE_CRC_CTL_A		(dev_priv->info.display_mmio_offset + 0x60050)
>  #define   PIPE_CRC_ENABLE		(1 << 31)
>  /* ivb+ source selection */
>  #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
> @@ -1901,11 +1901,11 @@
>  #define _PIPE_CRC_RES_4_A_IVB		0x60070
>  #define _PIPE_CRC_RES_5_A_IVB		0x60074
>  
> -#define _PIPE_CRC_RES_RED_A		(dev_priv->info->display_mmio_offset + 0x60060)
> -#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info->display_mmio_offset + 0x60064)
> -#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info->display_mmio_offset + 0x60068)
> -#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info->display_mmio_offset + 0x6006c)
> -#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info->display_mmio_offset + 0x60080)
> +#define _PIPE_CRC_RES_RED_A		(dev_priv->info.display_mmio_offset + 0x60060)
> +#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info.display_mmio_offset + 0x60064)
> +#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info.display_mmio_offset + 0x60068)
> +#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info.display_mmio_offset + 0x6006c)
> +#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info.display_mmio_offset + 0x60080)
>  
>  /* Pipe B CRC regs */
>  #define _PIPE_CRC_RES_1_B_IVB		0x61064
> @@ -1938,26 +1938,26 @@
>  	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
>  
>  /* Pipe A timing regs */
> -#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
> -#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
> -#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
> -#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
> -#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
> -#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
> -#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
> -#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
> -#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
> +#define _HTOTAL_A	(dev_priv->info.display_mmio_offset + 0x60000)
> +#define _HBLANK_A	(dev_priv->info.display_mmio_offset + 0x60004)
> +#define _HSYNC_A	(dev_priv->info.display_mmio_offset + 0x60008)
> +#define _VTOTAL_A	(dev_priv->info.display_mmio_offset + 0x6000c)
> +#define _VBLANK_A	(dev_priv->info.display_mmio_offset + 0x60010)
> +#define _VSYNC_A	(dev_priv->info.display_mmio_offset + 0x60014)
> +#define _PIPEASRC	(dev_priv->info.display_mmio_offset + 0x6001c)
> +#define _BCLRPAT_A	(dev_priv->info.display_mmio_offset + 0x60020)
> +#define _VSYNCSHIFT_A	(dev_priv->info.display_mmio_offset + 0x60028)
>  
>  /* Pipe B timing regs */
> -#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
> -#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
> -#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
> -#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
> -#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
> -#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
> -#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
> -#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
> -#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
> +#define _HTOTAL_B	(dev_priv->info.display_mmio_offset + 0x61000)
> +#define _HBLANK_B	(dev_priv->info.display_mmio_offset + 0x61004)
> +#define _HSYNC_B	(dev_priv->info.display_mmio_offset + 0x61008)
> +#define _VTOTAL_B	(dev_priv->info.display_mmio_offset + 0x6100c)
> +#define _VBLANK_B	(dev_priv->info.display_mmio_offset + 0x61010)
> +#define _VSYNC_B	(dev_priv->info.display_mmio_offset + 0x61014)
> +#define _PIPEBSRC	(dev_priv->info.display_mmio_offset + 0x6101c)
> +#define _BCLRPAT_B	(dev_priv->info.display_mmio_offset + 0x61020)
> +#define _VSYNCSHIFT_B	(dev_priv->info.display_mmio_offset + 0x61028)
>  
>  #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
>  #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> @@ -2083,7 +2083,7 @@
>  
>  
>  /* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
> +#define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
>  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
>  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
>  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
> @@ -2113,7 +2113,7 @@
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
>  
> -#define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
> +#define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
>  /*
>   * HDMI/DP bits are gen4+
>   *
> @@ -2385,7 +2385,7 @@
>  #define PP_DIVISOR	0x61210
>  
>  /* Panel fitting */
> -#define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
> +#define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
>  #define   PFIT_ENABLE		(1 << 31)
>  #define   PFIT_PIPE_MASK	(3 << 29)
>  #define   PFIT_PIPE_SHIFT	29
> @@ -2403,7 +2403,7 @@
>  #define   PFIT_SCALING_PROGRAMMED (1 << 26)
>  #define   PFIT_SCALING_PILLAR	(2 << 26)
>  #define   PFIT_SCALING_LETTER	(3 << 26)
> -#define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
> +#define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
>  /* Pre-965 */
>  #define		PFIT_VERT_SCALE_SHIFT		20
>  #define		PFIT_VERT_SCALE_MASK		0xfff00000
> @@ -2415,25 +2415,25 @@
>  #define		PFIT_HORIZ_SCALE_SHIFT_965	0
>  #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
>  
> -#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
> +#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
>  
> -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
> -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
> +#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
> +#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
>  #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
>  				     _VLV_BLC_PWM_CTL2_B)
>  
> -#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
> -#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
> +#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
> +#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
>  #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
>  				    _VLV_BLC_PWM_CTL_B)
>  
> -#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
> -#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
> +#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
> +#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
>  #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
>  				     _VLV_BLC_HIST_CTL_B)
>  
>  /* Backlight control */
> -#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
> +#define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
>  #define   BLM_PWM_ENABLE		(1 << 31)
>  #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
>  #define   BLM_PIPE_SELECT		(1 << 29)
> @@ -2456,7 +2456,7 @@
>  #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
>  #define   BLM_PHASE_IN_INCR_SHIFT	(0)
>  #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
> -#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
> +#define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
>  /*
>   * This is the most significant 15 bits of the number of backlight cycles in a
>   * complete cycle of the modulated backlight control.
> @@ -2478,7 +2478,7 @@
>  #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
>  #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
>  
> -#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
> +#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
>  
>  /* New registers for PCH-split platforms. Safe where new bits show up, the
>   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> @@ -3172,10 +3172,10 @@
>  /* Display & cursor control */
>  
>  /* Pipe A */
> -#define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
> +#define _PIPEADSL		(dev_priv->info.display_mmio_offset + 0x70000)
>  #define   DSL_LINEMASK_GEN2	0x00000fff
>  #define   DSL_LINEMASK_GEN3	0x00001fff
> -#define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
> +#define _PIPEACONF		(dev_priv->info.display_mmio_offset + 0x70008)
>  #define   PIPECONF_ENABLE	(1<<31)
>  #define   PIPECONF_DISABLE	0
>  #define   PIPECONF_DOUBLE_WIDE	(1<<30)
> @@ -3218,7 +3218,7 @@
>  #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
>  #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
>  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
> -#define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
> +#define _PIPEASTAT		(dev_priv->info.display_mmio_offset + 0x70024)
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
>  #define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
> @@ -3317,7 +3317,7 @@
>  #define   DSPARB_BEND_SHIFT	9 /* on 855 */
>  #define   DSPARB_AEND_SHIFT	0
>  
> -#define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
> +#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
>  #define   DSPFW_SR_SHIFT	23
>  #define   DSPFW_SR_MASK		(0x1ff<<23)
>  #define   DSPFW_CURSORB_SHIFT	16
> @@ -3325,11 +3325,11 @@
>  #define   DSPFW_PLANEB_SHIFT	8
>  #define   DSPFW_PLANEB_MASK	(0x7f<<8)
>  #define   DSPFW_PLANEA_MASK	(0x7f)
> -#define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
> +#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
>  #define   DSPFW_CURSORA_MASK	0x00003f00
>  #define   DSPFW_CURSORA_SHIFT	8
>  #define   DSPFW_PLANEC_MASK	(0x7f)
> -#define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
> +#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
>  #define   DSPFW_HPLL_SR_EN	(1<<31)
>  #define   DSPFW_CURSOR_SR_SHIFT	24
>  #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
> @@ -3337,8 +3337,8 @@
>  #define   DSPFW_HPLL_CURSOR_SHIFT	16
>  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
>  #define   DSPFW_HPLL_SR_MASK		(0x1ff)
> -#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
> -#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
> +#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
> +#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
>  
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32	32
> @@ -3498,12 +3498,12 @@
>  #define   PIPE_PIXEL_MASK         0x00ffffff
>  #define   PIPE_PIXEL_SHIFT        0
>  /* GM45+ just has to be different */
> -#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70040)
> -#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x70044)
> +#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70040)
> +#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70044)
>  #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
>  
>  /* Cursor A & B regs */
> -#define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
> +#define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)
>  /* Old style CUR*CNTR flags (desktop 8xx) */
>  #define   CURSOR_ENABLE		0x80000000
>  #define   CURSOR_GAMMA_ENABLE	0x40000000
> @@ -3526,16 +3526,16 @@
>  #define   MCURSOR_PIPE_B	(1 << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
>  #define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
> -#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
> -#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
> +#define _CURABASE		(dev_priv->info.display_mmio_offset + 0x70084)
> +#define _CURAPOS		(dev_priv->info.display_mmio_offset + 0x70088)
>  #define   CURSOR_POS_MASK       0x007FF
>  #define   CURSOR_POS_SIGN       0x8000
>  #define   CURSOR_X_SHIFT        0
>  #define   CURSOR_Y_SHIFT        16
>  #define CURSIZE			0x700a0
> -#define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
> -#define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
> -#define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
> +#define _CURBCNTR		(dev_priv->info.display_mmio_offset + 0x700c0)
> +#define _CURBBASE		(dev_priv->info.display_mmio_offset + 0x700c4)
> +#define _CURBPOS		(dev_priv->info.display_mmio_offset + 0x700c8)
>  
>  #define _CURBCNTR_IVB		0x71080
>  #define _CURBBASE_IVB		0x71084
> @@ -3550,7 +3550,7 @@
>  #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
>  
>  /* Display A control */
> -#define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
> +#define _DSPACNTR                (dev_priv->info.display_mmio_offset + 0x70180)
>  #define   DISPLAY_PLANE_ENABLE			(1<<31)
>  #define   DISPLAY_PLANE_DISABLE			0
>  #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
> @@ -3584,14 +3584,14 @@
>  #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
>  #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
>  #define   DISPPLANE_TILED			(1<<10)
> -#define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
> -#define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
> -#define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
> -#define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
> -#define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
> -#define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
> -#define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
> -#define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
> +#define _DSPAADDR		(dev_priv->info.display_mmio_offset + 0x70184)
> +#define _DSPASTRIDE		(dev_priv->info.display_mmio_offset + 0x70188)
> +#define _DSPAPOS		(dev_priv->info.display_mmio_offset + 0x7018C) /* reserved */
> +#define _DSPASIZE		(dev_priv->info.display_mmio_offset + 0x70190)
> +#define _DSPASURF		(dev_priv->info.display_mmio_offset + 0x7019C) /* 965+ only */
> +#define _DSPATILEOFF		(dev_priv->info.display_mmio_offset + 0x701A4) /* 965+ only */
> +#define _DSPAOFFSET		(dev_priv->info.display_mmio_offset + 0x701A4) /* HSW */
> +#define _DSPASURFLIVE		(dev_priv->info.display_mmio_offset + 0x701AC)
>  
>  #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
>  #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
> @@ -3612,44 +3612,44 @@
>  		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
>  
>  /* VBIOS flags */
> -#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
> -#define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
> -#define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
> -#define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
> -#define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
> -#define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
> -#define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
> -#define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
> -#define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
> -#define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
> -#define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
> -#define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
> -#define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
> +#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
> +#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
> +#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
> +#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
> +#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
> +#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
> +#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
> +#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
> +#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
> +#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
> +#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
> +#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
> +#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
>  
>  /* Pipe B */
> -#define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
> -#define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
> -#define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
> +#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> +#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
> +#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
> -#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71040)
> -#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info->display_mmio_offset + 0x71044)
> +#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
> +#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
>  
>  
>  /* Display B control */
> -#define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
> +#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
>  #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
>  #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
>  #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
>  #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
> -#define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
> -#define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
> -#define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
> -#define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
> -#define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
> -#define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
> -#define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
> -#define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
> +#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
> +#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
> +#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
> +#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
> +#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
> +#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
> +#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
> +#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
>  
>  /* Sprite A control */
>  #define _DVSACNTR		0x72180
> @@ -3898,39 +3898,39 @@
>  #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
>  
>  
> -#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
> +#define _PIPEA_DATA_M1           (dev_priv->info.display_mmio_offset + 0x60030)
>  #define  PIPE_DATA_M1_OFFSET    0
> -#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
> +#define _PIPEA_DATA_N1           (dev_priv->info.display_mmio_offset + 0x60034)
>  #define  PIPE_DATA_N1_OFFSET    0
>  
> -#define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
> +#define _PIPEA_DATA_M2           (dev_priv->info.display_mmio_offset + 0x60038)
>  #define  PIPE_DATA_M2_OFFSET    0
> -#define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
> +#define _PIPEA_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6003c)
>  #define  PIPE_DATA_N2_OFFSET    0
>  
> -#define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
> +#define _PIPEA_LINK_M1           (dev_priv->info.display_mmio_offset + 0x60040)
>  #define  PIPE_LINK_M1_OFFSET    0
> -#define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
> +#define _PIPEA_LINK_N1           (dev_priv->info.display_mmio_offset + 0x60044)
>  #define  PIPE_LINK_N1_OFFSET    0
>  
> -#define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
> +#define _PIPEA_LINK_M2           (dev_priv->info.display_mmio_offset + 0x60048)
>  #define  PIPE_LINK_M2_OFFSET    0
> -#define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
> +#define _PIPEA_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6004c)
>  #define  PIPE_LINK_N2_OFFSET    0
>  
>  /* PIPEB timing regs are same start from 0x61000 */
>  
> -#define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
> -#define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
> +#define _PIPEB_DATA_M1           (dev_priv->info.display_mmio_offset + 0x61030)
> +#define _PIPEB_DATA_N1           (dev_priv->info.display_mmio_offset + 0x61034)
>  
> -#define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
> -#define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
> +#define _PIPEB_DATA_M2           (dev_priv->info.display_mmio_offset + 0x61038)
> +#define _PIPEB_DATA_N2           (dev_priv->info.display_mmio_offset + 0x6103c)
>  
> -#define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
> -#define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
> +#define _PIPEB_LINK_M1           (dev_priv->info.display_mmio_offset + 0x61040)
> +#define _PIPEB_LINK_N1           (dev_priv->info.display_mmio_offset + 0x61044)
>  
> -#define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
> -#define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
> +#define _PIPEB_LINK_M2           (dev_priv->info.display_mmio_offset + 0x61048)
> +#define _PIPEB_LINK_N2           (dev_priv->info.display_mmio_offset + 0x6104c)
>  
>  #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
>  #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> @@ -5041,7 +5041,7 @@
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>  
> -#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
> +#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801
>  #define INTEL_AUDIO_DEVCTG		0x80862802
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 4/8] drm/i915: Move num_plane to the intel_device_info structure
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (2 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 14:36 ` [PATCH 5/8] drm/i915: Consolidate FUSE_STRAP in one set of defines Damien Lespiau
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

And rename it to num_sprites as this value doesn't count the primary
plane.

This limit lives with num_pipes really, and now that dev_priv->info is
writable we can put it there instead.

While at it, introduce a intel_device_info_runtime_init() where we'll be
able to gather the device info fields at run-time.

v2: rename num_plane to num_sprites (Ville Syrjälä)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c      | 21 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_drv.h      |  5 ++---
 drivers/gpu/drm/i915/intel_display.c |  4 ++--
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 332d5b6..28a1142 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1459,6 +1459,23 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 #undef SEP_COMMA
 }
 
+/*
+ * Determine various intel_device_info fields at runtime.
+ *
+ * Use it when either:
+ *   - it's judged too laborious to fill n static structures with the limit
+ *     when a simple if statement does the job,
+ *   - run-time checks (eg read fuse/strap registers) are needed.
+ */
+static void intel_device_info_runtime_init(struct drm_device *dev)
+{
+	struct intel_device_info *info = &to_i915(dev)->info;
+
+	info->num_sprites = 1;
+	if (IS_VALLEYVIEW(dev))
+		info->num_sprites = 2;
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
@@ -1631,9 +1648,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (!IS_I945G(dev) && !IS_I945GM(dev))
 		pci_enable_msi(dev->pdev);
 
-	dev_priv->num_plane = 1;
-	if (IS_VALLEYVIEW(dev))
-		dev_priv->num_plane = 2;
+	intel_device_info_runtime_init(dev);
 
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a66245a..c3e170f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -77,7 +77,7 @@ enum plane {
 };
 #define plane_name(p) ((p) + 'A')
 
-#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
+#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites + (s) + 'A')
 
 enum port {
 	PORT_A = 0,
@@ -503,6 +503,7 @@ struct intel_uncore {
 struct intel_device_info {
 	u32 display_mmio_offset;
 	u8 num_pipes:3;
+	u8 num_sprites:2;
 	u8 gen;
 	u8 ring_mask; /* Rings supported by the HW */
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
@@ -1389,8 +1390,6 @@ typedef struct drm_i915_private {
 	u32 hpd_event_bits;
 	struct timer_list hotplug_reenable_timer;
 
-	int num_plane;
-
 	struct i915_fbc fbc;
 	struct intel_opregion opregion;
 	struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 34dc0d6..46e0688 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1189,7 +1189,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	if (IS_VALLEYVIEW(dev)) {
-		for (i = 0; i < dev_priv->num_plane; i++) {
+		for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) {
 			reg = SPCNTR(pipe, i);
 			val = I915_READ(reg);
 			WARN((val & SP_ENABLE),
@@ -10865,7 +10865,7 @@ void intel_modeset_init(struct drm_device *dev)
 
 	for_each_pipe(i) {
 		intel_crtc_init(dev, i);
-		for (j = 0; j < dev_priv->num_plane; j++) {
+		for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) {
 			ret = intel_plane_init(dev, i, j);
 			if (ret)
 				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 5/8] drm/i915: Consolidate FUSE_STRAP in one set of defines
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (3 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 4/8] drm/i915: Move num_plane to the intel_device_info structure Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 14:36 ` [PATCH 6/8] drm/i915: Disable display when fused off Damien Lespiau
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

We had 2 set of defines for the same register, so make it one.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 18 ++++++++----------
 drivers/gpu/drm/i915/intel_ddi.c     |  2 +-
 drivers/gpu/drm/i915/intel_display.c |  3 +--
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67e9673..c6d9ba5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4116,13 +4116,14 @@
 #define  ILK_ELPIN_409_SELECT	(1 << 25)
 #define  ILK_DPARB_GATE	(1<<22)
 #define  ILK_VSDPFD_FULL	(1<<21)
-#define ILK_DISPLAY_CHICKEN_FUSES	0x42014
-#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
-#define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
-#define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
-#define  ILK_HDCP_DISABLE		(1<<25)
-#define  ILK_eDP_A_DISABLE		(1<<24)
-#define  ILK_DESKTOP			(1<<23)
+#define FUSE_STRAP			0x42014
+#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
+#define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
+#define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
+#define  ILK_HDCP_DISABLE		(1 << 25)
+#define  ILK_eDP_A_DISABLE		(1 << 24)
+#define  HSW_CDCLK_LIMIT		(1 << 24)
+#define  ILK_DESKTOP			(1 << 23)
 
 #define ILK_DSPCLK_GATE_D			0x42020
 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
@@ -4174,9 +4175,6 @@
 #define HSW_SCRATCH1				0xb038
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
 
-#define HSW_FUSE_STRAP		0x42014
-#define  HSW_CDCLK_LIMIT	(1 << 24)
-
 /* PCH */
 
 /* south display engine interrupt: IBX */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3a14d99..24f49b6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1246,7 +1246,7 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 
 	if (lcpll & LCPLL_CD_SOURCE_FCLK) {
 		return 800000;
-	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
+	} else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
 		return 450000;
 	} else if (freq == LCPLL_CLK_FREQ_450) {
 		return 450000;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 46e0688..561b95e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10235,8 +10235,7 @@ static bool has_edp_a(struct drm_device *dev)
 	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
 		return false;
 
-	if (IS_GEN5(dev) &&
-	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
+	if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
 		return false;
 
 	return true;
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 6/8] drm/i915: Disable display when fused off
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (4 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 5/8] drm/i915: Consolidate FUSE_STRAP in one set of defines Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 14:36 ` [PATCH 7/8] drm/i915: Remove the Quanta special case Damien Lespiau
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

FUSE_STRAP has a bit to inform us that the display has been fused off.
Use it to setup the definitive number of pipes at run-time.

v2: actually tweak num_pipes, not num_planes
v3: also tests SFUSE_STRAP bit 7

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 18 +++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 28a1142..8810097 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1466,14 +1466,30 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
  *   - it's judged too laborious to fill n static structures with the limit
  *     when a simple if statement does the job,
  *   - run-time checks (eg read fuse/strap registers) are needed.
+ *
+ * This function needs to be called after the MMIO has been setup as we are
+ * reading registers, and before the first usage of the fields it can tweak.
  */
 static void intel_device_info_runtime_init(struct drm_device *dev)
 {
-	struct intel_device_info *info = &to_i915(dev)->info;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_device_info *info = &dev_priv->info;
 
 	info->num_sprites = 1;
 	if (IS_VALLEYVIEW(dev))
 		info->num_sprites = 2;
+
+	if ((INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
+	    !IS_VALLEYVIEW(dev)) {
+		u32 fuse_strap = I915_READ(FUSE_STRAP);
+		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
+
+		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
+		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED) {
+			DRM_DEBUG_DRIVER("Display fused off, disabling\n");
+			info->num_pipes = 0;
+		}
+	}
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6d9ba5..85e53ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5411,6 +5411,7 @@
 
 /* SFUSE_STRAP */
 #define SFUSE_STRAP			0xc2014
+#define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 7/8] drm/i915: Remove the Quanta special case
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (5 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 6/8] drm/i915: Disable display when fused off Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-12 14:36 ` [PATCH 8/8] drm/i915: Use I915_MAX_PIPES in the pipe/plane_to_crtc_mapping definitions Damien Lespiau
  2013-12-13  8:51 ` Supporting fused display configurations v3 Mika Kuoppala
  8 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ben Widawsky

We now read out the FUSE_STRAP and SFUSE_STRAP registers, looking for
configurations with display fused off. Let's remove the Quanta special
case and rely on the programmed fuses to set num_pipes to 0.

This patch is untested and needs a good soul with such a device to give
it a go.

Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 13 -------------
 include/drm/i915_pciids.h       |  9 ---------
 2 files changed, 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a13b8ed..7717030 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -295,12 +295,6 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.is_mobile = 1,
 };
 
-static const struct intel_device_info intel_ivybridge_q_info = {
-	GEN7_FEATURES,
-	.is_ivybridge = 1,
-	.num_pipes = 0, /* legal, last one wins */
-};
-
 static const struct intel_device_info intel_valleyview_m_info = {
 	GEN7_FEATURES,
 	.is_mobile = 1,
@@ -355,12 +349,6 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	.has_ddi = 1,
 };
 
-/*
- * Make sure any device matches here are from most specific to most
- * general.  For example, since the Quanta match is based on the subsystem
- * and subvendor IDs, we need it to come before the more general IVB
- * PCI ID matches, otherwise we'll use the wrong info struct above.
- */
 #define INTEL_PCI_IDS \
 	INTEL_I830_IDS(&intel_i830_info),	\
 	INTEL_I845G_IDS(&intel_845g_info),	\
@@ -380,7 +368,6 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\
 	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\
 	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\
-	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\
 	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\
 	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4..02ebb67 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -41,12 +41,6 @@
 	0x030000, 0xff0000,			\
 	(unsigned long) info }
 
-#define INTEL_QUANTA_VGA_DEVICE(info) {		\
-	0x8086,	0x16a,				\
-	0x152d,	0x8990,				\
-	0x030000, 0xff0000,			\
-	(unsigned long) info }
-
 #define INTEL_I830_IDS(info)				\
 	INTEL_VGA_DEVICE(0x3577, info)
 
@@ -131,9 +125,6 @@
 	INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
 	INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
 
-#define INTEL_IVB_Q_IDS(info) \
-	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
-
 #define INTEL_HSW_D_IDS(info) \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 8/8] drm/i915: Use I915_MAX_PIPES in the pipe/plane_to_crtc_mapping definitions
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (6 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 7/8] drm/i915: Remove the Quanta special case Damien Lespiau
@ 2013-12-12 14:36 ` Damien Lespiau
  2013-12-13  8:51 ` Supporting fused display configurations v3 Mika Kuoppala
  8 siblings, 0 replies; 20+ messages in thread
From: Damien Lespiau @ 2013-12-12 14:36 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c3e170f..ea6b578 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1440,8 +1440,8 @@ typedef struct drm_i915_private {
 
 	struct sdvo_device_mapping sdvo_mappings[2];
 
-	struct drm_crtc *plane_to_crtc_mapping[3];
-	struct drm_crtc *pipe_to_crtc_mapping[3];
+	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
+	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 	wait_queue_head_t pending_flip_queue;
 
 #ifdef CONFIG_DEBUG_FS
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: Supporting fused display configurations v3
  2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
                   ` (7 preceding siblings ...)
  2013-12-12 14:36 ` [PATCH 8/8] drm/i915: Use I915_MAX_PIPES in the pipe/plane_to_crtc_mapping definitions Damien Lespiau
@ 2013-12-13  8:51 ` Mika Kuoppala
  8 siblings, 0 replies; 20+ messages in thread
From: Mika Kuoppala @ 2013-12-13  8:51 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx

Damien Lespiau <damien.lespiau@intel.com> writes:

> v3, following up a couple of review comments from Ville:
>   http://lists.freedesktop.org/archives/intel-gfx/2013-December/037313.html
>
> Changes:
>   - Always use INTEL_INFO() after initialization to access dev_priv->info
>     (well, except in the reg macros, where it's just too impractical),
>   - Cast the device_info pointer returned by INTEL_INFO() to be const to cast
>     potential writes by code using the macro,
>   - Renamed num_plane to num_sprites as num_planes would imply we're counting
>     the primary plane there, but we're not.
>
> -- 
> Damien

Series:
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2013-12-17 12:18 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-12 14:36 Supporting fused display configurations v3 Damien Lespiau
2013-12-12 14:36 ` [PATCH 1/8] drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flag Damien Lespiau
2013-12-17  9:38   ` Daniel Vetter
2013-12-17 11:17     ` Damien Lespiau
2013-12-17 12:18       ` Daniel Vetter
2013-12-12 14:36 ` [PATCH 2/8] drm/i915: Always use INTEL_INFO() to access the device_info structure Damien Lespiau
2013-12-12 16:58   ` Chris Wilson
2013-12-12 17:05     ` Damien Lespiau
2013-12-12 17:23       ` Chris Wilson
2013-12-12 18:47         ` Ville Syrjälä
2013-12-12 14:36 ` [PATCH 3/8] drm/i915: Make the intel_device_info structure kept in dev_priv writable Damien Lespiau
2013-12-12 15:30   ` Jani Nikula
2013-12-12 15:38     ` Damien Lespiau
2013-12-12 16:58   ` Ville Syrjälä
2013-12-12 14:36 ` [PATCH 4/8] drm/i915: Move num_plane to the intel_device_info structure Damien Lespiau
2013-12-12 14:36 ` [PATCH 5/8] drm/i915: Consolidate FUSE_STRAP in one set of defines Damien Lespiau
2013-12-12 14:36 ` [PATCH 6/8] drm/i915: Disable display when fused off Damien Lespiau
2013-12-12 14:36 ` [PATCH 7/8] drm/i915: Remove the Quanta special case Damien Lespiau
2013-12-12 14:36 ` [PATCH 8/8] drm/i915: Use I915_MAX_PIPES in the pipe/plane_to_crtc_mapping definitions Damien Lespiau
2013-12-13  8:51 ` Supporting fused display configurations v3 Mika Kuoppala

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