* [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces
@ 2013-12-16 8:05 edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS edgar.iglesias
` (21 more replies)
0 siblings, 22 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Hi,
I'm looking at modeling systems where multiple CPUs co-exist with
different views of their attached buses/devs.
With this series I'm trying to take some steps towards having
an address-space per CPU. It's not complete but good enough for
making it possible to model (to some extent) CPU local memories
for MicroBlaze systems in emulation mode (tcg). I'm updating the
petalogix-ml605 here and will follow-up later with the petalogix-s3adsp.
There is lots of future work needed, for example to transform more of
the cpu_* bus accessing functions. To add more usage of AddressSpace
properties to pass on address spaces to DMA models. Qtest mechanisms
to target specific address spaces, etc...
Cheers,
Edgar
Edgar E. Iglesias (22):
exec: Make tb_invalidate_phys_addr input an AS
exec: Make iotlb_to_region input an AS
exec: Always initialize MemorySection address spaces
exec: Make memory_region_section_get_iotlb use section AS
memory: Add MemoryListener to typedefs.h
memory: Add address_space_find_by_name()
qdev: Add qdev property type for AddressSpaces
cpu: Add per-cpu address space
target-microblaze: Add address-space property
exec: On AS changes, only flush affected CPU TLBs
exec: Make ldl_*_phys input an AddressSpace
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make lduw_*_phys input an AddressSpace
exec: Make stq_*_phys input an AddressSpace
exec: Make stl_*_phys input an AddressSpace
exec: Make stl_phys_notdirty input an AddressSpace
exec: Make stw_*_phys input an AddressSpace
exec: Make stb_phys input an AddressSpace
exec: Make cpu_physical_memory_write_rom input an AS
exec: Make cpu_memory_rw_debug use the CPUs AS
petalogix-ml605: Create the CPU with object_new()
petalogix-ml605: Make the LMB visible only to the CPU
cpu-exec.c | 5 +-
cputlb.c | 4 +-
exec.c | 176 ++++++++++++---------
hw/alpha/dp264.c | 5 +-
hw/alpha/typhoon.c | 2 +-
hw/arm/boot.c | 9 +-
hw/arm/highbank.c | 6 +-
hw/core/loader.c | 3 +-
hw/core/qdev-properties-system.c | 46 ++++++
hw/display/sm501.c | 1 +
hw/display/sm501_template.h | 2 +-
hw/dma/pl080.c | 9 +-
hw/dma/sun4m_iommu.c | 3 +-
hw/intc/apic.c | 3 +-
hw/microblaze/petalogix_ml605_mmu.c | 28 +++-
hw/net/vmware_utils.h | 16 +-
hw/pci/msi.c | 2 +-
hw/pci/msix.c | 2 +-
hw/ppc/ppc405_uc.c | 44 +++---
hw/ppc/spapr_hcall.c | 42 ++---
hw/s390x/css.c | 11 +-
hw/s390x/s390-virtio-bus.c | 36 +++--
hw/s390x/s390-virtio.c | 2 +-
hw/s390x/virtio-ccw.c | 40 +++--
hw/scsi/megasas.c | 22 ++-
hw/scsi/vmw_pvscsi.c | 6 +-
hw/sh4/r2d.c | 4 +-
hw/sparc/sun4m.c | 3 +-
hw/timer/hpet.c | 3 +-
hw/virtio/virtio.c | 31 ++--
include/exec/cpu-common.h | 44 +++---
include/exec/cpu-defs.h | 3 +
include/exec/exec-all.h | 5 +-
include/exec/memory.h | 10 +-
include/exec/softmmu_template.h | 5 +-
include/hw/ppc/spapr.h | 4 +-
include/hw/qdev-properties.h | 5 +
include/qemu/typedefs.h | 1 +
include/qom/cpu.h | 2 +
memory.c | 12 ++
monitor.c | 2 +-
target-alpha/helper.c | 6 +-
target-alpha/helper.h | 8 +-
target-alpha/mem_helper.c | 28 ++--
target-alpha/translate.c | 8 +-
target-arm/helper.c | 16 +-
target-i386/arch_memory_mapping.c | 46 +++---
target-i386/helper.c | 47 +++---
target-i386/seg_helper.c | 12 +-
target-i386/smm_helper.c | 298 ++++++++++++++++++-----------------
target-i386/svm_helper.c | 291 ++++++++++++++++++++--------------
target-microblaze/cpu.c | 14 ++
target-ppc/excp_helper.c | 2 +-
target-ppc/mmu-hash32.h | 8 +-
target-ppc/mmu-hash64.h | 10 +-
target-s390x/cpu.c | 2 +-
target-s390x/helper.c | 8 +-
target-s390x/mem_helper.c | 6 +-
target-sparc/ldst_helper.c | 68 ++++----
target-sparc/mmu_helper.c | 20 +--
target-unicore32/softmmu.c | 4 +-
target-xtensa/helper.c | 2 +-
target-xtensa/op_helper.c | 3 +-
translate-all.c | 4 +-
64 files changed, 906 insertions(+), 664 deletions(-)
--
1.7.10.4
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 02/22] exec: Make iotlb_to_region " edgar.iglesias
` (20 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 3 ++-
include/exec/exec-all.h | 2 +-
target-xtensa/op_helper.c | 3 ++-
translate-all.c | 4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 00526d1..7ed34e2 100644
--- a/exec.c
+++ b/exec.c
@@ -484,7 +484,8 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
- tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK));
+ tb_invalidate_phys_addr(&address_space_memory,
+ phys | (pc & ~TARGET_PAGE_MASK));
}
}
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ea90b64..b4dfc07 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -101,7 +101,7 @@ void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..89a72b5 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -29,6 +29,7 @@
#include "helper.h"
#include "qemu/host-utils.h"
#include "exec/softmmu_exec.h"
+#include "exec/address-spaces.h"
static void do_unaligned_access(CPUXtensaState *env,
target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
@@ -90,7 +91,7 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
- tb_invalidate_phys_addr(paddr);
+ tb_invalidate_phys_addr(&address_space_memory, paddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index 1c63d78..2ff8781 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1356,13 +1356,13 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
hwaddr l = 1;
- mr = address_space_translate(&address_space_memory, addr, &addr, &l, false);
+ mr = address_space_translate(as, addr, &addr, &l, false);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
return;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 02/22] exec: Make iotlb_to_region input an AS
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 03/22] exec: Always initialize MemorySection address spaces edgar.iglesias
` (19 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cputlb.c | 2 +-
exec.c | 5 ++---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index fff0afb..0399172 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
- mr = iotlb_to_region(pd);
+ mr = iotlb_to_region(&address_space_memory, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 7ed34e2..c34f642 100644
--- a/exec.c
+++ b/exec.c
@@ -1726,10 +1726,9 @@ static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
return phys_section_add(map, §ion);
}
-MemoryRegion *iotlb_to_region(hwaddr index)
+MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
{
- return address_space_memory.dispatch->map.sections[
- index & ~TARGET_PAGE_MASK].mr;
+ return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
}
static void io_mem_init(void)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b4dfc07..6129365 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -324,7 +324,7 @@ extern uintptr_t tci_tb_ptr;
void phys_mem_set_alloc(void *(*alloc)(size_t));
-struct MemoryRegion *iotlb_to_region(hwaddr index);
+struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
uint64_t *pvalue, unsigned size);
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c6a5440..69d856a 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -22,6 +22,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/timer.h"
+#include "exec/address-spaces.h"
#include "exec/memory.h"
#define DATA_SIZE (1 << SHIFT)
@@ -118,7 +119,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
uintptr_t retaddr)
{
uint64_t val;
- MemoryRegion *mr = iotlb_to_region(physaddr);
+ MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = retaddr;
@@ -324,7 +325,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
- MemoryRegion *mr = iotlb_to_region(physaddr);
+ MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 03/22] exec: Always initialize MemorySection address spaces
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 02/22] exec: Make iotlb_to_region " edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 04/22] exec: Make memory_region_section_get_iotlb use section AS edgar.iglesias
` (18 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index c34f642..6d88931 100644
--- a/exec.c
+++ b/exec.c
@@ -878,6 +878,7 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
if (!(existing->mr->subpage)) {
subpage = subpage_init(d->as, base);
+ subsection.address_space = d->as;
subsection.mr = &subpage->iomem;
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
phys_section_add(&d->map, &subsection));
@@ -1717,6 +1718,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
{
MemoryRegionSection section = {
+ .address_space = &address_space_memory,
.mr = mr,
.offset_within_address_space = 0,
.offset_within_region = 0,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 04/22] exec: Make memory_region_section_get_iotlb use section AS
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (2 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 03/22] exec: Always initialize MemorySection address spaces edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 05/22] memory: Add MemoryListener to typedefs.h edgar.iglesias
` (17 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 6d88931..803bbde 100644
--- a/exec.c
+++ b/exec.c
@@ -782,7 +782,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
iotlb |= PHYS_SECTION_ROM;
}
} else {
- iotlb = section - address_space_memory.dispatch->map.sections;
+ iotlb = section - section->address_space->dispatch->map.sections;
iotlb += xlat;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 05/22] memory: Add MemoryListener to typedefs.h
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (3 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 04/22] exec: Make memory_region_section_get_iotlb use section AS edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 06/22] memory: Add address_space_find_by_name() edgar.iglesias
` (16 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/exec/memory.h | 2 --
include/qemu/typedefs.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 480dfbf..2d0b614 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -165,8 +165,6 @@ struct MemoryRegion {
NotifierList iommu_notify;
};
-typedef struct MemoryListener MemoryListener;
-
/**
* MemoryListener: callbacks structure for updates to the physical memory map
*
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index a4c1b84..425ca1a 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -24,6 +24,7 @@ typedef struct BusClass BusClass;
typedef struct AddressSpace AddressSpace;
typedef struct MemoryRegion MemoryRegion;
typedef struct MemoryRegionSection MemoryRegionSection;
+typedef struct MemoryListener MemoryListener;
typedef struct MemoryMappingList MemoryMappingList;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 06/22] memory: Add address_space_find_by_name()
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (4 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 05/22] memory: Add MemoryListener to typedefs.h edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 07/22] qdev: Add qdev property type for AddressSpaces edgar.iglesias
` (15 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/exec/memory.h | 8 ++++++++
memory.c | 12 ++++++++++++
2 files changed, 20 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 2d0b614..02f4012 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -941,6 +941,14 @@ void mtree_info(fprintf_function mon_printf, void *f);
*/
void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name);
+/**
+ * address_space_find_by_name: Find an AddressSpace * by name
+ *
+ * Returns an AddressSpace * if found.
+ *
+ * @name: name of an address space too look for.
+ */
+AddressSpace *address_space_find_by_name(const char *name);
/**
* address_space_destroy: destroy an address space
diff --git a/memory.c b/memory.c
index 7764314..4695879 100644
--- a/memory.c
+++ b/memory.c
@@ -1725,6 +1725,18 @@ void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
memory_region_transaction_commit();
}
+AddressSpace *address_space_find_by_name(const char *name)
+{
+ AddressSpace *as;
+
+ QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
+ if (strcmp(as->name, name) == 0) {
+ return as;
+ }
+ }
+ return NULL;
+}
+
void address_space_destroy(AddressSpace *as)
{
/* Flush out anything from MemoryListeners listening in on this */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 07/22] qdev: Add qdev property type for AddressSpaces
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (5 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 06/22] memory: Add address_space_find_by_name() edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space edgar.iglesias
` (14 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/core/qdev-properties-system.c | 46 ++++++++++++++++++++++++++++++++++++++
include/hw/qdev-properties.h | 5 +++++
2 files changed, 51 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 729efa8..f78bd50 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -170,6 +170,42 @@ PropertyInfo qdev_prop_chr = {
.release = release_chr,
};
+/* --- AddressSpace --- */
+
+static int parse_address_space(DeviceState *dev, const char *name, void **ptr)
+{
+ AddressSpace *as = address_space_find_by_name(name);
+ if (as == NULL) {
+ return -ENOENT;
+ }
+ *ptr = as;
+ return 0;
+}
+
+static const char *print_address_space(void *ptr)
+{
+ AddressSpace *as = ptr;
+ return as->name;
+}
+
+static void get_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ get_pointer(obj, v, opaque, print_address_space, name, errp);
+}
+
+static void set_address_space(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ set_pointer(obj, v, opaque, parse_address_space, name, errp);
+}
+
+PropertyInfo qdev_prop_address_space = {
+ .name = "address_space",
+ .get = get_address_space,
+ .set = set_address_space,
+};
+
/* --- netdev device --- */
static int parse_netdev(DeviceState *dev, const char *str, void **ptr)
@@ -369,6 +405,16 @@ void qdev_prop_set_netdev(DeviceState *dev, const char *name,
assert_no_error(errp);
}
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value)
+{
+ Error *errp = NULL;
+ assert(!value || value->name);
+ object_property_set_str(OBJECT(dev),
+ value ? value->name : "", name, &errp);
+ assert_no_error(errp);
+}
+
void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
{
qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 692f82e..0e1076d 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -19,6 +19,7 @@ extern PropertyInfo qdev_prop_size;
extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
+extern PropertyInfo qdev_prop_address_space;
extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
@@ -124,6 +125,8 @@ extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
+#define DEFINE_PROP_ADDRESS_SPACE(_n, _s, _f) \
+ DEFINE_PROP(_n, _s, _f, qdev_prop_address_space, AddressSpace*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@@ -160,6 +163,8 @@ void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value);
void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value);
void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value);
void qdev_prop_set_string(DeviceState *dev, const char *name, const char *value);
+void qdev_prop_set_address_space(DeviceState *dev, const char *name,
+ AddressSpace *value);
void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState *value);
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState *value);
int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState *value) QEMU_WARN_UNUSED_RESULT;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (6 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 07/22] qdev: Add qdev property type for AddressSpaces edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 12:11 ` Andreas Färber
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 09/22] target-microblaze: Add address-space property edgar.iglesias
` (13 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cputlb.c | 4 ++--
exec.c | 31 +++++++++++++++++++++++--------
include/exec/cpu-defs.h | 3 +++
include/exec/exec-all.h | 1 +
include/exec/softmmu_template.h | 4 ++--
include/qom/cpu.h | 2 ++
6 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 0399172..a2264a3 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -254,7 +254,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
sz = size;
- section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+ section = address_space_translate_for_iotlb(env->as, paddr,
&xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
@@ -327,7 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
cpu_ldub_code(env1, addr);
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
- mr = iotlb_to_region(&address_space_memory, pd);
+ mr = iotlb_to_region(env1->as, pd);
if (memory_region_is_unassigned(mr)) {
CPUState *cpu = ENV_GET_CPU(env1);
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/exec.c b/exec.c
index 803bbde..edb6a43 100644
--- a/exec.c
+++ b/exec.c
@@ -136,6 +136,7 @@ typedef struct subpage_t {
static void io_mem_init(void);
static void memory_map_init(void);
+static void tcg_commit(MemoryListener *listener);
static MemoryRegion io_mem_watch;
#endif
@@ -434,6 +435,25 @@ CPUState *qemu_get_cpu(int index)
return NULL;
}
+#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
+{
+ CPUArchState *env = cpu->env_ptr;
+
+ if (tcg_enabled()) {
+ if (cpu->tcg_as_listener) {
+ memory_listener_unregister(cpu->tcg_as_listener);
+ } else {
+ cpu->tcg_as_listener = g_new0(MemoryListener, 1);
+ }
+ cpu->tcg_as_listener->commit = tcg_commit;
+ memory_listener_register(cpu->tcg_as_listener, as);
+ }
+
+ env->as = as;
+}
+#endif
+
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
@@ -453,6 +473,7 @@ void cpu_exec_init(CPUArchState *env)
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
+ cpu_address_space_init(cpu, &address_space_memory);
cpu->thread_id = qemu_get_thread_id();
#endif
QTAILQ_INSERT_TAIL(&cpus, cpu, node);
@@ -482,9 +503,10 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
#else
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
+ CPUArchState *env = cpu->env_ptr;
hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
if (phys != -1) {
- tb_invalidate_phys_addr(&address_space_memory,
+ tb_invalidate_phys_addr(env->as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -1810,10 +1832,6 @@ static MemoryListener core_memory_listener = {
.priority = 1,
};
-static MemoryListener tcg_memory_listener = {
- .commit = tcg_commit,
-};
-
void address_space_init_dispatch(AddressSpace *as)
{
as->dispatch = NULL;
@@ -1849,9 +1867,6 @@ static void memory_map_init(void)
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);
- if (tcg_enabled()) {
- memory_listener_register(&tcg_memory_listener, &address_space_memory);
- }
}
MemoryRegion *get_system_memory(void)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 01cd8c7..406b36c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -176,6 +176,9 @@ typedef struct CPUWatchpoint {
sigjmp_buf jmp_env; \
int exception_index; \
\
+ /* Per CPU address-space. */ \
+ AddressSpace *as; \
+ \
/* user data */ \
void *opaque; \
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6129365..61770ee 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,6 +95,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
+void cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 69d856a..1dacb4d 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -119,7 +119,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
uintptr_t retaddr)
{
uint64_t val;
- MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
+ MemoryRegion *mr = iotlb_to_region(env->as, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = retaddr;
@@ -325,7 +325,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
- MemoryRegion *mr = iotlb_to_region(&address_space_memory, physaddr);
+ MemoryRegion *mr = iotlb_to_region(env->as, physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7739e00..c1febae 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -186,6 +186,8 @@ struct CPUState {
uint32_t interrupt_request;
int singlestep_enabled;
+ MemoryListener *tcg_as_listener;
+
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
struct GDBRegisterState *gdb_regs;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 09/22] target-microblaze: Add address-space property
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (7 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs edgar.iglesias
` (12 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-microblaze/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0ef9aa4..ada9556 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -88,11 +88,22 @@ static void mb_cpu_reset(CPUState *s)
#endif
}
+static void mb_cpu_setup_as(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
+ cpu_address_space_init(cs, env->as);
+#endif
+}
+
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+ mb_cpu_setup_as(cs);
cpu_reset(cs);
qemu_init_vcpu(cs);
@@ -123,6 +134,9 @@ static const VMStateDescription vmstate_mb_cpu = {
};
static Property mb_properties[] = {
+#ifndef CONFIG_USER_ONLY
+ DEFINE_PROP_ADDRESS_SPACE("address-space", MicroBlazeCPU, env.as),
+#endif
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (8 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 09/22] target-microblaze: Add address-space property edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 12:54 ` Andreas Färber
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 11/22] exec: Make ldl_*_phys input an AddressSpace edgar.iglesias
` (11 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index edb6a43..203c8e4 100644
--- a/exec.c
+++ b/exec.c
@@ -1810,6 +1810,11 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
+ /* FIXME: Disentangle the cpu.h circular files deps so we can
+ directly get the right CPU from listener. */
+ if (cpu->tcg_as_listener != listener) {
+ continue;
+ }
CPUArchState *env = cpu->env_ptr;
tlb_flush(env, 1);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 11/22] exec: Make ldl_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (9 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs edgar.iglesias
@ 2013-12-16 8:05 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 12/22] exec: Make ldq/ldub_*_phys " edgar.iglesias
` (10 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cpu-exec.c | 5 +-
exec.c | 19 ++++---
hw/dma/pl080.c | 9 ++--
hw/dma/sun4m_iommu.c | 3 +-
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 8 +--
hw/s390x/css.c | 3 +-
hw/s390x/s390-virtio-bus.c | 2 +-
hw/s390x/virtio-ccw.c | 5 +-
hw/scsi/megasas.c | 4 +-
hw/scsi/vmw_pvscsi.c | 3 +-
hw/virtio/virtio.c | 3 +-
include/exec/cpu-common.h | 6 +--
include/hw/ppc/spapr.h | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 8 +--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 12 ++---
target-i386/arch_memory_mapping.c | 36 ++++++-------
target-i386/helper.c | 8 +--
target-i386/seg_helper.c | 4 +-
target-i386/smm_helper.c | 102 +++++++++++++++++++------------------
target-i386/svm_helper.c | 26 +++++-----
target-ppc/excp_helper.c | 2 +-
target-ppc/mmu-hash32.h | 4 +-
target-s390x/cpu.c | 2 +-
target-sparc/ldst_helper.c | 6 +--
target-sparc/mmu_helper.c | 18 +++----
target-unicore32/softmmu.c | 4 +-
target-xtensa/helper.c | 2 +-
30 files changed, 163 insertions(+), 149 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..8f6766b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -374,7 +374,10 @@ int cpu_exec(CPUArchState *env)
/* FIXME: this should respect TPR */
cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
0);
- intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
+ intno = ldl_phys(env->as,
+ env->vm_vmcb
+ + offsetof(struct vmcb,
+ control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
diff --git a/exec.c b/exec.c
index 203c8e4..0e898bb 100644
--- a/exec.c
+++ b/exec.c
@@ -1598,7 +1598,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
switch (size) {
case 1: return ldub_phys(addr);
case 2: return lduw_phys(addr);
- case 4: return ldl_phys(addr);
+ case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
}
@@ -2310,7 +2310,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(hwaddr addr,
+static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2319,8 +2319,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- false);
+ mr = address_space_translate(as, addr, &addr1, &l, false);
if (l < 4 || !memory_access_is_direct(mr, false)) {
/* I/O case */
io_mem_read(mr, addr1, &val, 4);
@@ -2353,19 +2352,19 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
return val;
}
-uint32_t ldl_phys(hwaddr addr)
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(hwaddr addr)
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(hwaddr addr)
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
{
- return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 35b9015..58556f3 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -8,6 +8,7 @@
*/
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
@@ -204,10 +205,10 @@ again:
if (size == 0) {
/* Transfer complete. */
if (ch->lli) {
- ch->src = ldl_le_phys(ch->lli);
- ch->dest = ldl_le_phys(ch->lli + 4);
- ch->ctrl = ldl_le_phys(ch->lli + 12);
- ch->lli = ldl_le_phys(ch->lli + 8);
+ ch->src = ldl_le_phys(&address_space_memory, ch->lli);
+ ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
+ ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
+ ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
} else {
ch->conf &= ~PL080_CCONF_E;
}
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4m_iommu.c
index a04409a..723f66d 100644
--- a/hw/dma/sun4m_iommu.c
+++ b/hw/dma/sun4m_iommu.c
@@ -24,6 +24,7 @@
#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
#include "trace.h"
/*
@@ -262,7 +263,7 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
- ret = ldl_be_phys(iopte);
+ ret = ldl_be_phys(&address_space_memory, iopte);
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
return ret;
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 5307e2c..b465eb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -95,7 +95,7 @@ vmw_shmem_st16(hwaddr addr, uint16_t value)
static inline uint32_t
vmw_shmem_ld32(hwaddr addr)
{
- uint32_t res = ldl_le_phys(addr);
+ uint32_t res = ldl_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f755a53..8ba2c3f 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -397,7 +397,7 @@ static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(env->as, addr + 0x4);
if (size < 0x8) {
return H_PARAMETER;
}
@@ -432,7 +432,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
return H_HARDWARE;
}
- size = ldl_be_phys(addr + 0x4);
+ size = ldl_be_phys(env->as, addr + 0x4);
if (size < 48) {
return H_PARAMETER;
@@ -543,7 +543,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = lduw_phys(addr);
return H_SUCCESS;
case 4:
- args[0] = ldl_phys(addr);
+ args[0] = ldl_phys(cpu->env.as, addr);
return H_SUCCESS;
case 8:
args[0] = ldq_phys(addr);
@@ -611,7 +611,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = lduw_phys(src);
break;
case 2:
- tmp = ldl_phys(src);
+ tmp = ldl_phys(cpu->env.as, src);
break;
case 3:
tmp = ldq_phys(src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 101da63..41b1903 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -11,6 +11,7 @@
#include <hw/qdev.h>
#include "qemu/bitops.h"
+#include "exec/address-spaces.h"
#include "cpu.h"
#include "ioinst.h"
#include "css.h"
@@ -667,7 +668,7 @@ static void css_update_chnmon(SubchDev *sch)
/* Format 1, per-subchannel area. */
uint32_t count;
- count = ldl_phys(sch->curr_status.mba);
+ count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
stl_phys(sch->curr_status.mba, count);
} else {
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 6a83111..7c28fd7 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -409,7 +409,7 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
/* Update guest supported feature bitmap */
- features = bswap32(ldl_be_phys(dev->feat_offs));
+ features = bswap32(ldl_be_phys(&address_space_memory, dev->feat_offs));
virtio_set_features(vdev, features);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index ecc80ec..fb2f8f9 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -266,7 +266,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
info.queue = ldq_phys(ccw.cda);
- info.align = ldl_phys(ccw.cda + sizeof(info.queue));
+ info.align = ldl_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
info.num = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -323,7 +324,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EFAULT;
} else {
features.index = ldub_phys(ccw.cda + sizeof(features.features));
- features.features = ldl_le_phys(ccw.cda);
+ features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
vdev->guest_features = features.features;
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 7c5a1a2..a655980 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -602,8 +602,8 @@ static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
pa_lo = le32_to_cpu(initq->pi_addr_lo);
pa_hi = le32_to_cpu(initq->pi_addr_hi);
s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
- s->reply_queue_head = ldl_le_phys(s->producer_pa);
- s->reply_queue_tail = ldl_le_phys(s->consumer_pa);
+ s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
+ s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
flags = le32_to_cpu(initq->flags);
if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
s->flags |= MEGASAS_MASK_USE_QUEUE64;
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 94b328f..6cc6c1b 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -43,7 +43,8 @@
(sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
#define RS_GET_FIELD(rs_pa, field) \
- (ldl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field)))
+ (ldl_le_phys(&address_space_memory, \
+ rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
(stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 144b9ca..267af80 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -14,6 +14,7 @@
#include <inttypes.h>
#include "trace.h"
+#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/virtio/virtio.h"
#include "qemu/atomic.h"
@@ -111,7 +112,7 @@ static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
- return ldl_phys(pa);
+ return ldl_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index e4996e1..2f5626a 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -86,8 +86,8 @@ void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
-uint32_t ldl_le_phys(hwaddr addr);
-uint32_t ldl_be_phys(hwaddr addr);
+uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
+uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(hwaddr addr);
uint64_t ldq_be_phys(hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
@@ -100,7 +100,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
-uint32_t ldl_phys(hwaddr addr);
+uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index fdaab2d..aec756e 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -339,7 +339,7 @@ static inline uint64_t ppc64_phys_to_real(uint64_t addr)
static inline uint32_t rtas_ld(target_ulong phys, int n)
{
- return ldl_be_phys(ppc64_phys_to_real(phys + 4*n));
+ return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
}
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 5a0e78c..3977702 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -101,7 +101,7 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
-DEF_HELPER_1(ldl_phys, i64, i64)
+DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_1(ldq_phys, i64, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 7160a1c..5887052 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -24,9 +24,9 @@
/* Softmmu support */
#ifndef CONFIG_USER_ONLY
-uint64_t helper_ldl_phys(uint64_t p)
+uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
{
- return (int32_t)ldl_phys(p);
+ return (int32_t)ldl_phys(env->as, p);
}
uint64_t helper_ldq_phys(uint64_t p)
@@ -37,7 +37,7 @@ uint64_t helper_ldq_phys(uint64_t p)
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
{
env->lock_addr = p;
- return env->lock_value = (int32_t)ldl_phys(p);
+ return env->lock_value = (int32_t)ldl_phys(env->as, p);
}
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
@@ -61,7 +61,7 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
uint64_t ret = 0;
if (p == env->lock_addr) {
- int32_t old = ldl_phys(p);
+ int32_t old = ldl_phys(env->as, p);
if (old == (int32_t)env->lock_value) {
stl_phys(p, v);
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1155e86..802c49a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2912,7 +2912,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- gen_helper_ldl_phys(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5e5e5aa..6bb33dc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2232,7 +2232,7 @@ static void v7m_push(CPUARMState *env, uint32_t val)
static uint32_t v7m_pop(CPUARMState *env)
{
uint32_t val;
- val = ldl_phys(env->regs[13]);
+ val = ldl_phys(env->as, env->regs[13]);
env->regs[13] += 4;
return val;
}
@@ -2387,7 +2387,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
- addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
+ addr = ldl_phys(env->as, env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
@@ -2604,7 +2604,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
@@ -2635,7 +2635,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -2701,7 +2701,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
/* Pagetable walk. */
/* Lookup l1 descriptor. */
table = get_level1_table_address(env, address);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -2743,7 +2743,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
}
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c
index 462f984..132be93 100644
--- a/target-i386/arch_memory_mapping.c
+++ b/target-i386/arch_memory_mapping.c
@@ -16,7 +16,8 @@
#include "sysemu/memory_mapping.h"
/* PAE Paging or IA-32e Paging */
-static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
+static void walk_pte(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pte_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pte_addr, start_paddr;
@@ -45,7 +46,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
}
/* 32-bit Paging */
-static void walk_pte2(MemoryMappingList *list,
+static void walk_pte2(MemoryMappingList *list, AddressSpace *as,
hwaddr pte_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -56,7 +57,7 @@ static void walk_pte2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pte_addr = (pte_start_addr + i * 4) & a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -77,7 +78,8 @@ static void walk_pte2(MemoryMappingList *list,
/* PAE Paging or IA-32e Paging */
#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */
-static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
+static void walk_pde(MemoryMappingList *list, AddressSpace *as,
+ hwaddr pde_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
hwaddr pde_addr, pte_start_addr, start_paddr;
@@ -108,12 +110,12 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
}
pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
- walk_pte(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* 32-bit Paging */
-static void walk_pde2(MemoryMappingList *list,
+static void walk_pde2(MemoryMappingList *list, AddressSpace *as,
hwaddr pde_start_addr, int32_t a20_mask,
bool pse)
{
@@ -124,7 +126,7 @@ static void walk_pde2(MemoryMappingList *list,
for (i = 0; i < 1024; i++) {
pde_addr = (pde_start_addr + i * 4) & a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -150,12 +152,12 @@ static void walk_pde2(MemoryMappingList *list,
}
pte_start_addr = (pde & ~0xfff) & a20_mask;
- walk_pte2(list, pte_start_addr, a20_mask, line_addr);
+ walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
}
}
/* PAE Paging */
-static void walk_pdpe2(MemoryMappingList *list,
+static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask)
{
hwaddr pdpe_addr, pde_start_addr;
@@ -173,13 +175,13 @@ static void walk_pdpe2(MemoryMappingList *list,
line_addr = (((unsigned int)i & 0x3) << 30);
pde_start_addr = (pdpe & ~0xfff) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
#ifdef TARGET_X86_64
/* IA-32e Paging */
-static void walk_pdpe(MemoryMappingList *list,
+static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
hwaddr pdpe_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
@@ -211,12 +213,12 @@ static void walk_pdpe(MemoryMappingList *list,
}
pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
- walk_pde(list, pde_start_addr, a20_mask, line_addr);
+ walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
}
}
/* IA-32e Paging */
-static void walk_pml4e(MemoryMappingList *list,
+static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
hwaddr pml4e_start_addr, int32_t a20_mask)
{
hwaddr pml4e_addr, pdpe_start_addr;
@@ -234,7 +236,7 @@ static void walk_pml4e(MemoryMappingList *list,
line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
- walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
+ walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
}
}
#endif
@@ -256,14 +258,14 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
hwaddr pml4e_addr;
pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
- walk_pml4e(list, pml4e_addr, env->a20_mask);
+ walk_pml4e(list, env->as, pml4e_addr, env->a20_mask);
} else
#endif
{
hwaddr pdpe_addr;
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
- walk_pdpe2(list, pdpe_addr, env->a20_mask);
+ walk_pdpe2(list, env->as, pdpe_addr, env->a20_mask);
}
} else {
hwaddr pde_addr;
@@ -271,7 +273,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
pse = !!(env->cr[4] & CR4_PSE_MASK);
- walk_pde2(list, pde_addr, env->a20_mask, pse);
+ walk_pde2(list, env->as, pde_addr, env->a20_mask, pse);
}
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 7c196ff..c802d34 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -728,7 +728,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -786,7 +786,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(env->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -957,7 +957,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
- pde = ldl_phys(pde_addr);
+ pde = ldl_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK))
return -1;
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -966,7 +966,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
} else {
/* page directory entry */
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
- pte = ldl_phys(pte_addr);
+ pte = ldl_phys(env->as, pte_addr);
if (!(pte & PG_PRESENT_MASK))
return -1;
page_size = 4096;
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index e789102..0c7216f 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1131,7 +1131,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
static void handle_even_inj(CPUX86State *env, int intno, int is_int,
int error_code, int is_hw, int rm)
{
- uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ uint32_t event_inj = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (!(event_inj & SVM_EVTINJ_VALID)) {
@@ -1225,7 +1225,7 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & HF_SVMI_MASK) {
- uint32_t event_inj = ldl_phys(env->vm_vmcb +
+ uint32_t event_inj = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj));
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 6cb4551..4c2edc2 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -194,25 +194,25 @@ void helper_rsm(CPUX86State *env)
cpu_x86_load_seg_cache(env, i,
lduw_phys(sm_state + offset),
ldq_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
+ ldl_phys(env->as, sm_state + offset + 4),
(lduw_phys(sm_state + offset + 2) &
0xf0ff) << 8);
}
env->gdt.base = ldq_phys(sm_state + 0x7e68);
- env->gdt.limit = ldl_phys(sm_state + 0x7e64);
+ env->gdt.limit = ldl_phys(env->as, sm_state + 0x7e64);
env->ldt.selector = lduw_phys(sm_state + 0x7e70);
env->ldt.base = ldq_phys(sm_state + 0x7e78);
- env->ldt.limit = ldl_phys(sm_state + 0x7e74);
+ env->ldt.limit = ldl_phys(env->as, sm_state + 0x7e74);
env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
env->idt.base = ldq_phys(sm_state + 0x7e88);
- env->idt.limit = ldl_phys(sm_state + 0x7e84);
+ env->idt.limit = ldl_phys(env->as, sm_state + 0x7e84);
env->tr.selector = lduw_phys(sm_state + 0x7e90);
env->tr.base = ldq_phys(sm_state + 0x7e98);
- env->tr.limit = ldl_phys(sm_state + 0x7e94);
+ env->tr.limit = ldl_phys(env->as, sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
@@ -227,51 +227,51 @@ void helper_rsm(CPUX86State *env)
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
}
env->eip = ldq_phys(sm_state + 0x7f78);
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
+ cpu_load_eflags(env, ldl_phys(env->as, sm_state + 0x7f70),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->dr[6] = ldl_phys(sm_state + 0x7f68);
- env->dr[7] = ldl_phys(sm_state + 0x7f60);
+ env->dr[6] = ldl_phys(env->as, sm_state + 0x7f68);
+ env->dr[7] = ldl_phys(env->as, sm_state + 0x7f60);
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
+ cpu_x86_update_cr4(env, ldl_phys(env->as, sm_state + 0x7f48));
+ cpu_x86_update_cr3(env, ldl_phys(env->as, sm_state + 0x7f50));
+ cpu_x86_update_cr0(env, ldl_phys(env->as, sm_state + 0x7f58));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(env->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
+ env->smbase = ldl_phys(env->as, sm_state + 0x7f00) & ~0x7fff;
}
#else
- cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
- cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
- cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
+ cpu_x86_update_cr0(env, ldl_phys(env->as, sm_state + 0x7ffc));
+ cpu_x86_update_cr3(env, ldl_phys(env->as, sm_state + 0x7ff8));
+ cpu_load_eflags(env, ldl_phys(env->as, sm_state + 0x7ff4),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
- env->eip = ldl_phys(sm_state + 0x7ff0);
- env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec);
- env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
- env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
- env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
- env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
- env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
- env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
- env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
- env->dr[6] = ldl_phys(sm_state + 0x7fcc);
- env->dr[7] = ldl_phys(sm_state + 0x7fc8);
-
- env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
- env->tr.base = ldl_phys(sm_state + 0x7f64);
- env->tr.limit = ldl_phys(sm_state + 0x7f60);
- env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
-
- env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
- env->ldt.base = ldl_phys(sm_state + 0x7f80);
- env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
- env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
-
- env->gdt.base = ldl_phys(sm_state + 0x7f74);
- env->gdt.limit = ldl_phys(sm_state + 0x7f70);
-
- env->idt.base = ldl_phys(sm_state + 0x7f58);
- env->idt.limit = ldl_phys(sm_state + 0x7f54);
+ env->eip = ldl_phys(env->as, sm_state + 0x7ff0);
+ env->regs[R_EDI] = ldl_phys(env->as, sm_state + 0x7fec);
+ env->regs[R_ESI] = ldl_phys(env->as, sm_state + 0x7fe8);
+ env->regs[R_EBP] = ldl_phys(env->as, sm_state + 0x7fe4);
+ env->regs[R_ESP] = ldl_phys(env->as, sm_state + 0x7fe0);
+ env->regs[R_EBX] = ldl_phys(env->as, sm_state + 0x7fdc);
+ env->regs[R_EDX] = ldl_phys(env->as, sm_state + 0x7fd8);
+ env->regs[R_ECX] = ldl_phys(env->as, sm_state + 0x7fd4);
+ env->regs[R_EAX] = ldl_phys(env->as, sm_state + 0x7fd0);
+ env->dr[6] = ldl_phys(env->as, sm_state + 0x7fcc);
+ env->dr[7] = ldl_phys(env->as, sm_state + 0x7fc8);
+
+ env->tr.selector = ldl_phys(env->as, sm_state + 0x7fc4) & 0xffff;
+ env->tr.base = ldl_phys(env->as, sm_state + 0x7f64);
+ env->tr.limit = ldl_phys(env->as, sm_state + 0x7f60);
+ env->tr.flags = (ldl_phys(env->as, sm_state + 0x7f5c) & 0xf0ff) << 8;
+
+ env->ldt.selector = ldl_phys(env->as, sm_state + 0x7fc0) & 0xffff;
+ env->ldt.base = ldl_phys(env->as, sm_state + 0x7f80);
+ env->ldt.limit = ldl_phys(env->as, sm_state + 0x7f7c);
+ env->ldt.flags = (ldl_phys(env->as, sm_state + 0x7f78) & 0xf0ff) << 8;
+
+ env->gdt.base = ldl_phys(env->as, sm_state + 0x7f74);
+ env->gdt.limit = ldl_phys(env->as, sm_state + 0x7f70);
+
+ env->idt.base = ldl_phys(env->as, sm_state + 0x7f58);
+ env->idt.limit = ldl_phys(env->as, sm_state + 0x7f54);
for (i = 0; i < 6; i++) {
if (i < 3) {
@@ -280,16 +280,18 @@ void helper_rsm(CPUX86State *env)
offset = 0x7f2c + (i - 3) * 12;
}
cpu_x86_load_seg_cache(env, i,
- ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
- ldl_phys(sm_state + offset + 8),
- ldl_phys(sm_state + offset + 4),
- (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
+ ldl_phys(env->as,
+ sm_state + 0x7fa8 + i * 4) & 0xffff,
+ ldl_phys(env->as, sm_state + offset + 8),
+ ldl_phys(env->as, sm_state + offset + 4),
+ (ldl_phys(env->as,
+ sm_state + offset) & 0xf0ff) << 8);
}
- cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
+ cpu_x86_update_cr4(env, ldl_phys(env->as, sm_state + 0x7f14));
- val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+ val = ldl_phys(env->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
+ env->smbase = ldl_phys(env->as, sm_state + 0x7ef8) & ~0x7fff;
}
#endif
CC_OP = CC_OP_EFLAGS;
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4a7de42..2700232 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -105,7 +105,7 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
- sc->limit = ldl_phys(addr + offsetof(struct vmcb_seg, limit));
+ sc->limit = ldl_phys(env->as, addr + offsetof(struct vmcb_seg, limit));
flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
@@ -190,7 +190,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->intercept_dr_write = lduw_phys(env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_write));
- env->intercept_exceptions = ldl_phys(env->vm_vmcb +
+ env->intercept_exceptions = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_exceptions
));
@@ -203,12 +203,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.limit));
/* clear exit_info_2 so we behave like the real hardware */
@@ -221,7 +221,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
save.cr3)));
env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
if (int_ctl & V_INTR_MASKING_MASK) {
env->v_tpr = int_ctl & V_TPR_MASK;
@@ -277,12 +278,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
}
/* maybe we need to inject an event */
- event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ event_inj = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
if (event_inj & SVM_EVTINJ_VALID) {
uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK;
uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR;
- uint32_t event_inj_err = ldl_phys(env->vm_vmcb +
+ uint32_t event_inj_err = ldl_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.event_inj_err));
@@ -594,7 +595,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
- int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ int_ctl = ldl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK);
int_ctl |= env->v_tpr & V_TPR_MASK;
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
@@ -623,12 +625,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.gdtr.base));
- env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->gdt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.limit));
env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.idtr.base));
- env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->idt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.limit));
cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
@@ -674,10 +676,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
exit_info_1);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
- ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err)));
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index c959460..bb1e206 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -185,7 +185,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
if (env->mpic_proxy) {
/* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(env->mpic_iack);
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(env->as, env->mpic_iack);
}
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b..d102bff 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -69,14 +69,14 @@ static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
hwaddr pte_offset)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset);
+ return ldl_phys(env->as, env->htab_base + pte_offset);
}
static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
hwaddr pte_offset)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+ return ldl_phys(env->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
}
static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 3c89f8a..b2d6716 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -70,7 +70,7 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
static void s390_cpu_load_normal(CPUState *s)
{
S390CPU *cpu = S390_CPU(s);
- cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR;
+ cpu->env.psw.addr = ldl_phys(cpu->env.as, 4) & PSW_MASK_ESA_ADDR;
cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
s390_add_running_cpu(cpu);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2936b58..d5400e2 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -615,7 +615,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(env->as, addr);
break;
case 8:
ret = ldq_phys(addr);
@@ -634,7 +634,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 4:
- ret = ldl_phys((hwaddr)addr
+ ret = ldl_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
@@ -1438,7 +1438,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = lduw_phys(addr);
break;
case 4:
- ret = ldl_phys(addr);
+ ret = ldl_phys(env->as, addr);
break;
default:
case 8:
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ef12a0a..8c5986e 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -108,7 +108,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
/* Ctx pde */
switch (pde & PTE_ENTRYTYPE_MASK) {
@@ -120,7 +120,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return 4 << 2;
case 1: /* L0 PDE */
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -130,7 +130,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (1 << 8) | (4 << 2);
case 1: /* L1 PDE */
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -140,7 +140,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
return (2 << 8) | (4 << 2);
case 1: /* L2 PDE */
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -250,7 +250,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
/* Context base + context number */
pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -263,7 +263,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -277,7 +277,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -291,7 +291,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
switch (pde & PTE_ENTRYTYPE_MASK) {
default:
@@ -317,7 +317,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = ldl_phys(pde_ptr);
+ pde = ldl_phys(env->as, pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 1e13a85..9045fcf 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -130,7 +130,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
/* Lookup l1 descriptor. */
table = env->cp0.c2_base & 0xfffff000;
table |= (address >> 20) & 0xffc;
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
code = 0;
switch (PAGETABLE_TYPE(desc)) {
case 3:
@@ -152,7 +152,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
goto do_fault;
}
table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
- desc = ldl_phys(table);
+ desc = ldl_phys(env->as, table);
/* 4k page. */
if (is_user) {
DPRINTF("PTE address %x, desc %x\n", table, desc);
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index a0f9993..6977726 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -564,7 +564,7 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
vaddr, ret ? ~0 : paddr);
if (ret == 0) {
- *pte = ldl_phys(paddr);
+ *pte = ldl_phys(env->as, paddr);
}
return ret;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 12/22] exec: Make ldq/ldub_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (10 preceding siblings ...)
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 11/22] exec: Make ldl_*_phys input an AddressSpace edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 13/22] exec: Make lduw_*_phys " edgar.iglesias
` (9 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 22 ++++----
hw/alpha/typhoon.c | 2 +-
hw/display/sm501.c | 1 +
hw/display/sm501_template.h | 2 +-
hw/net/vmware_utils.h | 4 +-
hw/ppc/spapr_hcall.c | 10 ++--
hw/s390x/s390-virtio-bus.c | 5 +-
hw/s390x/virtio-ccw.c | 18 +++---
hw/scsi/megasas.c | 3 +-
hw/virtio/virtio.c | 2 +-
include/exec/cpu-common.h | 8 +--
monitor.c | 2 +-
target-alpha/helper.c | 6 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 8 +--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 2 +-
target-i386/arch_memory_mapping.c | 10 ++--
target-i386/helper.c | 20 +++----
target-i386/smm_helper.c | 32 +++++------
target-i386/svm_helper.c | 112 ++++++++++++++++++++++---------------
target-ppc/mmu-hash64.h | 5 +-
target-s390x/helper.c | 2 +-
target-s390x/mem_helper.c | 2 +-
target-sparc/ldst_helper.c | 24 ++++----
25 files changed, 169 insertions(+), 137 deletions(-)
diff --git a/exec.c b/exec.c
index 0e898bb..db64e13 100644
--- a/exec.c
+++ b/exec.c
@@ -1596,7 +1596,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
- case 1: return ldub_phys(addr);
+ case 1: return ldub_phys(&address_space_memory, addr);
case 2: return lduw_phys(addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
@@ -2368,7 +2368,7 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(hwaddr addr,
+static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2377,7 +2377,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
hwaddr l = 8;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 8 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2411,26 +2411,26 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
return val;
}
-uint64_t ldq_phys(hwaddr addr)
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(hwaddr addr)
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(hwaddr addr)
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
{
- return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(hwaddr addr)
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
{
uint8_t val;
- cpu_physical_memory_read(addr, &val, 1);
+ address_space_rw(as, addr, &val, 1, 0);
return val;
}
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 59e1bb8..d07cfe5 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -613,7 +613,7 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret)
translation, given the address of the PTE. */
static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
{
- uint64_t pte = ldq_phys(pte_addr);
+ uint64_t pte = ldq_phys(&address_space_memory, pte_addr);
/* Check valid bit. */
if ((pte & 1) == 0) {
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c75d6ac..0b5f993 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
+#include "exec/address-spaces.h"
/*
* Status: 2010/05/07
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 2d4a3d8..d4cea9e 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -120,7 +120,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
/* get pixel value */
if (i % 4 == 0) {
- bitset = ldub_phys(cursor_addr);
+ bitset = ldub_phys(&address_space_memory, cursor_addr);
cursor_addr++;
}
v = bitset & 3;
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index b465eb6..eb98d2a 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -65,7 +65,7 @@ vmw_shmem_set(hwaddr addr, uint8 val, int len)
static inline uint32_t
vmw_shmem_ld8(hwaddr addr)
{
- uint8_t res = ldub_phys(addr);
+ uint8_t res = ldub_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
@@ -110,7 +110,7 @@ vmw_shmem_st32(hwaddr addr, uint32_t value)
static inline uint64_t
vmw_shmem_ld64(hwaddr addr)
{
- uint64_t res = ldq_le_phys(addr);
+ uint64_t res = ldq_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 8ba2c3f..942751b 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -367,7 +367,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
env->vpa_addr = vpa;
- tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET);
+ tmp = ldub_phys(env->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
@@ -537,7 +537,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
switch (size) {
case 1:
- args[0] = ldub_phys(addr);
+ args[0] = ldub_phys(cpu->env.as, addr);
return H_SUCCESS;
case 2:
args[0] = lduw_phys(addr);
@@ -546,7 +546,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = ldl_phys(cpu->env.as, addr);
return H_SUCCESS;
case 8:
- args[0] = ldq_phys(addr);
+ args[0] = ldq_phys(cpu->env.as, addr);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -605,7 +605,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
while (count--) {
switch (esize) {
case 0:
- tmp = ldub_phys(src);
+ tmp = ldub_phys(cpu->env.as, src);
break;
case 1:
tmp = lduw_phys(src);
@@ -614,7 +614,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = ldl_phys(cpu->env.as, src);
break;
case 3:
- tmp = ldq_phys(src);
+ tmp = ldq_phys(cpu->env.as, src);
break;
default:
return H_PARAMETER;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 7c28fd7..e8e6e10 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -324,7 +324,7 @@ static uint64_t s390_virtio_device_vq_token(VirtIOS390Device *dev, int vq)
(vq * VIRTIO_VQCONFIG_LEN) +
VIRTIO_VQCONFIG_OFFS_TOKEN;
- return ldq_be_phys(token_off);
+ return ldq_be_phys(&address_space_memory, token_off);
}
static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev)
@@ -405,7 +405,8 @@ void s390_virtio_device_update_status(VirtIOS390Device *dev)
VirtIODevice *vdev = dev->vdev;
uint32_t features;
- virtio_set_status(vdev, ldub_phys(dev->dev_offs + VIRTIO_DEV_OFFS_STATUS));
+ virtio_set_status(vdev, ldub_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_STATUS));
/* Update guest supported feature bitmap */
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index fb2f8f9..b86d94e 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -265,7 +265,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- info.queue = ldq_phys(ccw.cda);
+ info.queue = ldq_phys(&address_space_memory, ccw.cda);
info.align = ldl_phys(&address_space_memory,
ccw.cda + sizeof(info.queue));
info.index = lduw_phys(ccw.cda + sizeof(info.queue)
@@ -297,7 +297,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- features.index = ldub_phys(ccw.cda + sizeof(features.features));
+ features.index = ldub_phys(&address_space_memory,
+ ccw.cda + sizeof(features.features));
if (features.index < ARRAY_SIZE(dev->host_features)) {
features.features = dev->host_features[features.index];
} else {
@@ -323,7 +324,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- features.index = ldub_phys(ccw.cda + sizeof(features.features));
+ features.index = ldub_phys(&address_space_memory,
+ ccw.cda + sizeof(features.features));
features.features = ldl_le_phys(&address_space_memory, ccw.cda);
if (features.index < ARRAY_SIZE(dev->host_features)) {
virtio_bus_set_vdev_features(&dev->bus, features.features);
@@ -401,7 +403,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- status = ldub_phys(ccw.cda);
+ status = ldub_phys(&address_space_memory, ccw.cda);
if (!(status & VIRTIO_CONFIG_S_DRIVER_OK)) {
virtio_ccw_stop_ioeventfd(dev);
}
@@ -430,7 +432,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- indicators = ldq_phys(ccw.cda);
+ indicators = ldq_phys(&address_space_memory, ccw.cda);
dev->indicators = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
@@ -450,7 +452,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- indicators = ldq_phys(ccw.cda);
+ indicators = ldq_phys(&address_space_memory, ccw.cda);
dev->indicators2 = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
@@ -870,7 +872,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
if (!dev->indicators) {
return;
}
- indicators = ldq_phys(dev->indicators);
+ indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
stq_phys(dev->indicators, indicators);
} else {
@@ -878,7 +880,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
return;
}
vector = 0;
- indicators = ldq_phys(dev->indicators2);
+ indicators = ldq_phys(&address_space_memory, dev->indicators2);
indicators |= 1ULL << vector;
stq_phys(dev->indicators2, indicators);
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index a655980..33bcb97 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -158,7 +158,8 @@ static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
*/
static uint64_t megasas_frame_get_context(unsigned long frame)
{
- return ldq_le_phys(frame + offsetof(struct mfi_frame_header, context));
+ return ldq_le_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, context));
}
static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 267af80..e5bd115 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -105,7 +105,7 @@ static inline uint64_t vring_desc_addr(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr);
- return ldq_phys(pa);
+ return ldq_phys(&address_space_memory, pa);
}
static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 2f5626a..086ae97 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -83,13 +83,13 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr);
*/
void qemu_flush_coalesced_mmio_buffer(void);
-uint32_t ldub_phys(hwaddr addr);
+uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
uint32_t lduw_le_phys(hwaddr addr);
uint32_t lduw_be_phys(hwaddr addr);
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
-uint64_t ldq_le_phys(hwaddr addr);
-uint64_t ldq_be_phys(hwaddr addr);
+uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
+uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
@@ -101,7 +101,7 @@ void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
-uint64_t ldq_phys(hwaddr addr);
+uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
diff --git a/monitor.c b/monitor.c
index 845f608..9a5d745 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1445,7 +1445,7 @@ static void do_sum(Monitor *mon, const QDict *qdict)
sum = 0;
for(addr = start; addr < (start + size); addr++) {
- uint8_t val = ldub_phys(addr);
+ uint8_t val = ldub_phys(&address_space_memory, addr);
/* BSD sum algorithm ('sum' Unix command) */
sum = (sum >> 1) | (sum << 15);
sum += val;
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index fc61bb0..1e3d330 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -251,7 +251,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L1 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
- L1pte = ldq_phys(pt + index*8);
+ L1pte = ldq_phys(env->as, pt + index*8);
if (unlikely((L1pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -264,7 +264,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L2 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
- L2pte = ldq_phys(pt + index*8);
+ L2pte = ldq_phys(env->as, pt + index*8);
if (unlikely((L2pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -277,7 +277,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L3 page table read. */
index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
- L3pte = ldq_phys(pt + index*8);
+ L3pte = ldq_phys(env->as, pt + index*8);
phys = L3pte >> 32 << TARGET_PAGE_BITS;
if (unlikely((L3pte & PTE_VALID) == 0)) {
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 3977702..74dbd07 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -102,7 +102,7 @@ DEF_HELPER_2(hw_ret, void, env, i64)
DEF_HELPER_3(call_pal, void, env, i64, i64)
DEF_HELPER_2(ldl_phys, i64, env, i64)
-DEF_HELPER_1(ldq_phys, i64, i64)
+DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
DEF_HELPER_2(stl_phys, void, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 5887052..513dbed 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -29,9 +29,9 @@ uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p)
return (int32_t)ldl_phys(env->as, p);
}
-uint64_t helper_ldq_phys(uint64_t p)
+uint64_t helper_ldq_phys(CPUAlphaState *env, uint64_t p)
{
- return ldq_phys(p);
+ return ldq_phys(env->as, p);
}
uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
@@ -43,7 +43,7 @@ uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
{
env->lock_addr = p;
- return env->lock_value = ldq_phys(p);
+ return env->lock_value = ldq_phys(env->as, p);
}
void helper_stl_phys(uint64_t p, uint64_t v)
@@ -77,7 +77,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
uint64_t ret = 0;
if (p == env->lock_addr) {
- uint64_t old = ldq_phys(p);
+ uint64_t old = ldq_phys(env->as, p);
if (old == env->lock_value) {
stq_phys(p, v);
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 802c49a..f60ee35 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2916,7 +2916,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
- gen_helper_ldq_phys(cpu_ir[ra], addr);
+ gen_helper_ldq_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6bb33dc..09e58f0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2897,7 +2897,7 @@ static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
uint64_t descriptor;
descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
- descriptor = ldq_phys(descaddr);
+ descriptor = ldq_phys(env->as, descaddr);
if (!(descriptor & 1) ||
(!(descriptor & 2) && (level == 3))) {
/* Invalid, or the Reserved level 3 encoding */
diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c
index 132be93..ad3fb43 100644
--- a/target-i386/arch_memory_mapping.c
+++ b/target-i386/arch_memory_mapping.c
@@ -27,7 +27,7 @@ static void walk_pte(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pte_addr = (pte_start_addr + i * 8) & a20_mask;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -89,7 +89,7 @@ static void walk_pde(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pde_addr = (pde_start_addr + i * 8) & a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -167,7 +167,7 @@ static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 4; i++) {
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -192,7 +192,7 @@ static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
/* not present */
continue;
@@ -228,7 +228,7 @@ static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
for (i = 0; i < 512; i++) {
pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
/* not present */
continue;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index c802d34..028fa03 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -556,7 +556,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
env->a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(env->as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -572,7 +572,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(env->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -592,7 +592,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* XXX: load them when cr3 is loaded ? */
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(env->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -602,7 +602,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
env->a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -667,7 +667,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
}
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
env->a20_mask;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(env->as, pte_addr);
if (!(pte & PG_PRESENT_MASK)) {
error_code = 0;
goto do_fault;
@@ -913,13 +913,13 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
env->a20_mask;
- pml4e = ldq_phys(pml4e_addr);
+ pml4e = ldq_phys(env->as, pml4e_addr);
if (!(pml4e & PG_PRESENT_MASK))
return -1;
pdpe_addr = ((pml4e & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 30) & 0x1ff) << 3)) & env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(env->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK))
return -1;
} else
@@ -927,14 +927,14 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
env->a20_mask;
- pdpe = ldq_phys(pdpe_addr);
+ pdpe = ldq_phys(env->as, pdpe_addr);
if (!(pdpe & PG_PRESENT_MASK))
return -1;
}
pde_addr = ((pdpe & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 21) & 0x1ff) << 3)) & env->a20_mask;
- pde = ldq_phys(pde_addr);
+ pde = ldq_phys(env->as, pde_addr);
if (!(pde & PG_PRESENT_MASK)) {
return -1;
}
@@ -947,7 +947,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
pte_addr = ((pde & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
(((addr >> 12) & 0x1ff) << 3)) & env->a20_mask;
page_size = 4096;
- pte = ldq_phys(pte_addr);
+ pte = ldq_phys(env->as, pte_addr);
}
pte &= ~(PG_NX_MASK | PG_HI_USER_MASK);
if (!(pte & PG_PRESENT_MASK))
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 4c2edc2..e591f83 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -187,46 +187,46 @@ void helper_rsm(CPUX86State *env)
sm_state = env->smbase + 0x8000;
#ifdef TARGET_X86_64
- cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
+ cpu_load_efer(env, ldq_phys(env->as, sm_state + 0x7ed0));
for (i = 0; i < 6; i++) {
offset = 0x7e00 + i * 16;
cpu_x86_load_seg_cache(env, i,
lduw_phys(sm_state + offset),
- ldq_phys(sm_state + offset + 8),
+ ldq_phys(env->as, sm_state + offset + 8),
ldl_phys(env->as, sm_state + offset + 4),
(lduw_phys(sm_state + offset + 2) &
0xf0ff) << 8);
}
- env->gdt.base = ldq_phys(sm_state + 0x7e68);
+ env->gdt.base = ldq_phys(env->as, sm_state + 0x7e68);
env->gdt.limit = ldl_phys(env->as, sm_state + 0x7e64);
env->ldt.selector = lduw_phys(sm_state + 0x7e70);
- env->ldt.base = ldq_phys(sm_state + 0x7e78);
+ env->ldt.base = ldq_phys(env->as, sm_state + 0x7e78);
env->ldt.limit = ldl_phys(env->as, sm_state + 0x7e74);
env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
- env->idt.base = ldq_phys(sm_state + 0x7e88);
+ env->idt.base = ldq_phys(env->as, sm_state + 0x7e88);
env->idt.limit = ldl_phys(env->as, sm_state + 0x7e84);
env->tr.selector = lduw_phys(sm_state + 0x7e90);
- env->tr.base = ldq_phys(sm_state + 0x7e98);
+ env->tr.base = ldq_phys(env->as, sm_state + 0x7e98);
env->tr.limit = ldl_phys(env->as, sm_state + 0x7e94);
env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
- env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
- env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
- env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
- env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
- env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
- env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
- env->regs[R_ESI] = ldq_phys(sm_state + 0x7fc8);
- env->regs[R_EDI] = ldq_phys(sm_state + 0x7fc0);
+ env->regs[R_EAX] = ldq_phys(env->as, sm_state + 0x7ff8);
+ env->regs[R_ECX] = ldq_phys(env->as, sm_state + 0x7ff0);
+ env->regs[R_EDX] = ldq_phys(env->as, sm_state + 0x7fe8);
+ env->regs[R_EBX] = ldq_phys(env->as, sm_state + 0x7fe0);
+ env->regs[R_ESP] = ldq_phys(env->as, sm_state + 0x7fd8);
+ env->regs[R_EBP] = ldq_phys(env->as, sm_state + 0x7fd0);
+ env->regs[R_ESI] = ldq_phys(env->as, sm_state + 0x7fc8);
+ env->regs[R_EDI] = ldq_phys(env->as, sm_state + 0x7fc0);
for (i = 8; i < 16; i++) {
- env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
+ env->regs[i] = ldq_phys(env->as, sm_state + 0x7ff8 - i * 8);
}
- env->eip = ldq_phys(sm_state + 0x7f78);
+ env->eip = ldq_phys(env->as, sm_state + 0x7f78);
cpu_load_eflags(env, ldl_phys(env->as, sm_state + 0x7f70),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
env->dr[6] = ldl_phys(env->as, sm_state + 0x7f68);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 2700232..2c61be2 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -104,7 +104,7 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
unsigned int flags;
sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
- sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
+ sc->base = ldq_phys(env->as, addr + offsetof(struct vmcb_seg, base));
sc->limit = ldl_phys(env->as, addr + offsetof(struct vmcb_seg, limit));
flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
@@ -176,7 +176,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* load the interception bitmaps so we do not need to access the
vmcb in svm mode */
- env->intercept = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->intercept = ldq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.intercept));
env->intercept_cr_read = lduw_phys(env->vm_vmcb +
offsetof(struct vmcb,
@@ -198,15 +198,15 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* enable intercepts */
env->hflags |= HF_SVMI_MASK;
- env->tsc_offset = ldq_phys(env->vm_vmcb +
+ env->tsc_offset = ldq_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb, control.tsc_offset));
- env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->gdt.base = ldq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.base));
env->gdt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.gdtr.limit));
- env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->idt.base = ldq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.base));
env->idt.limit = ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
save.idtr.limit));
@@ -214,13 +214,17 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* clear exit_info_2 so we behave like the real hardware */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
- cpu_x86_update_cr0(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr0(env, ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr0)));
- cpu_x86_update_cr4(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr4(env, ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr4)));
- cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_x86_update_cr3(env, ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cr3)));
- env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
+ env->cr[2] = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr2));
int_ctl = ldl_phys(env->as,
env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
@@ -233,9 +237,11 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
}
cpu_load_efer(env,
- ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer)));
+ ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.efer)));
env->eflags = 0;
- cpu_load_eflags(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ cpu_load_eflags(env, ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.rflags)),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
CC_OP = CC_OP_EFLAGS;
@@ -249,18 +255,25 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
R_DS);
- env->eip = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
-
- env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
- env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
- env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
- env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
- cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb,
+ env->eip = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rip));
+
+ env->regs[R_ESP] = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rsp));
+ env->regs[R_EAX] = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rax));
+ env->dr[7] = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr7));
+ env->dr[6] = ldq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr6));
+ cpu_x86_set_cpl(env, ldub_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb,
save.cpl)));
/* FIXME: guest state consistency checks */
- switch (ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
+ switch (ldub_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
case TLB_CONTROL_DO_NOTHING:
break;
case TLB_CONTROL_FLUSH_ALL_ASID:
@@ -349,7 +362,7 @@ void helper_vmload(CPUX86State *env, int aflag)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
- addr, ldq_phys(addr + offsetof(struct vmcb,
+ addr, ldq_phys(env->as, addr + offsetof(struct vmcb,
save.fs.base)),
env->segs[R_FS].base);
@@ -359,17 +372,18 @@ void helper_vmload(CPUX86State *env, int aflag)
svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
#ifdef TARGET_X86_64
- env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb,
+ env->kernelgsbase = ldq_phys(env->as, addr + offsetof(struct vmcb,
save.kernel_gs_base));
- env->lstar = ldq_phys(addr + offsetof(struct vmcb, save.lstar));
- env->cstar = ldq_phys(addr + offsetof(struct vmcb, save.cstar));
- env->fmask = ldq_phys(addr + offsetof(struct vmcb, save.sfmask));
+ env->lstar = ldq_phys(env->as, addr + offsetof(struct vmcb, save.lstar));
+ env->cstar = ldq_phys(env->as, addr + offsetof(struct vmcb, save.cstar));
+ env->fmask = ldq_phys(env->as, addr + offsetof(struct vmcb, save.sfmask));
#endif
- env->star = ldq_phys(addr + offsetof(struct vmcb, save.star));
- env->sysenter_cs = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_cs));
- env->sysenter_esp = ldq_phys(addr + offsetof(struct vmcb,
+ env->star = ldq_phys(env->as, addr + offsetof(struct vmcb, save.star));
+ env->sysenter_cs = ldq_phys(env->as,
+ addr + offsetof(struct vmcb, save.sysenter_cs));
+ env->sysenter_esp = ldq_phys(env->as, addr + offsetof(struct vmcb,
save.sysenter_esp));
- env->sysenter_eip = ldq_phys(addr + offsetof(struct vmcb,
+ env->sysenter_eip = ldq_phys(env->as, addr + offsetof(struct vmcb,
save.sysenter_eip));
}
@@ -387,7 +401,8 @@ void helper_vmsave(CPUX86State *env, int aflag)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
- addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
+ addr, ldq_phys(env->as,
+ addr + offsetof(struct vmcb, save.fs.base)),
env->segs[R_FS].base);
svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
@@ -485,7 +500,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
case SVM_EXIT_MSR:
if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
- uint64_t addr = ldq_phys(env->vm_vmcb +
+ uint64_t addr = ldq_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.msrpm_base_pa));
uint32_t t0, t1;
@@ -511,7 +526,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
t1 = 0;
break;
}
- if (ldub_phys(addr + t1) & ((1 << param) << t0)) {
+ if (ldub_phys(env->as, addr + t1) & ((1 << param) << t0)) {
helper_vmexit(env, type, param);
}
}
@@ -535,7 +550,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
{
if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
- uint64_t addr = ldq_phys(env->vm_vmcb +
+ uint64_t addr = ldq_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb, control.iopm_base_pa));
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
@@ -557,7 +572,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
PRIx64 ", " TARGET_FMT_lx ")!\n",
exit_code, exit_info_1,
- ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
+ ldq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.exit_info_2)),
env->eip);
@@ -623,29 +638,33 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
env->tsc_offset = 0;
- env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->gdt.base = ldq_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.base));
env->gdt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.gdtr.limit));
- env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ env->idt.base = ldq_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.base));
env->idt.limit = ldl_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.idtr.limit));
- cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr0(env, ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr0)) |
CR0_PE_MASK);
- cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr4(env, ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr4)));
- cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_x86_update_cr3(env, ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.cr3)));
/* we need to set the efer after the crs so the hidden flags get
set properly */
- cpu_load_efer(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_load_efer(env, ldq_phys(env->as, env->vm_hsave + offsetof(struct vmcb,
save.efer)));
env->eflags = 0;
- cpu_load_eflags(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
+ cpu_load_eflags(env, ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb,
save.rflags)),
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
CC_OP = CC_OP_EFLAGS;
@@ -659,14 +678,17 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
R_DS);
- env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
- env->regs[R_ESP] = ldq_phys(env->vm_hsave +
+ env->eip = ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rip));
+ env->regs[R_ESP] = ldq_phys(env->as, env->vm_hsave +
offsetof(struct vmcb, save.rsp));
- env->regs[R_EAX] = ldq_phys(env->vm_hsave +
+ env->regs[R_EAX] = ldq_phys(env->as, env->vm_hsave +
offsetof(struct vmcb, save.rax));
- env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
- env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
+ env->dr[6] = ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr6));
+ env->dr[7] = ldq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr7));
/* other setups */
cpu_x86_set_cpl(env, 0);
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 55f5a23..16f71a3 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -81,7 +81,7 @@ static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
if (env->external_htab) {
return ldq_p(env->external_htab + pte_offset);
} else {
- return ldq_phys(env->htab_base + pte_offset);
+ return ldq_phys(env->as, env->htab_base + pte_offset);
}
}
@@ -91,7 +91,8 @@ static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
if (env->external_htab) {
return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
} else {
- return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
+ return ldq_phys(env->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
}
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index da33b38..12338a0 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -218,7 +218,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
/* XXX region protection flags */
/* *flags &= ~PAGE_WRITE */
- new_asce = ldq_phys(origin + offs);
+ new_asce = ldq_phys(env->as, origin + offs);
PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
__func__, origin, offs, new_asce);
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 1422ae9..55e889b 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -984,7 +984,7 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
mvc_asc(env, l - i, a1 + i, mode1, a2 + i, mode2);
break;
}
- stb_phys(dest + i, ldub_phys(src + i));
+ stb_phys(dest + i, ldub_phys(env->as, src + i));
}
return cc;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index d5400e2..e26c763 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -608,7 +608,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
case 0x1c: /* LEON MMU passthrough */
switch (size) {
case 1:
- ret = ldub_phys(addr);
+ ret = ldub_phys(env->as, addr);
break;
case 2:
ret = lduw_phys(addr);
@@ -618,14 +618,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldl_phys(env->as, addr);
break;
case 8:
- ret = ldq_phys(addr);
+ ret = ldq_phys(env->as, addr);
break;
}
break;
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
switch (size) {
case 1:
- ret = ldub_phys((hwaddr)addr
+ ret = ldub_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
case 2:
@@ -638,7 +638,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
| ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
- ret = ldq_phys((hwaddr)addr
+ ret = ldq_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
}
@@ -771,13 +771,17 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
"%08x: unimplemented access size: %d\n", addr,
size);
}
- env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[0] = ldq_phys(env->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
0);
- env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[1] = ldq_phys(env->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
8);
- env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[2] = ldq_phys(env->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
16);
- env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
+ env->mxccdata[3] = ldq_phys(env->as,
+ (env->mxccregs[0] & 0xffffffffULL) +
24);
break;
case 0x01c00200: /* MXCC stream destination */
@@ -1432,7 +1436,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
{
switch (size) {
case 1:
- ret = ldub_phys(addr);
+ ret = ldub_phys(env->as, addr);
break;
case 2:
ret = lduw_phys(addr);
@@ -1442,7 +1446,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
break;
default:
case 8:
- ret = ldq_phys(addr);
+ ret = ldq_phys(env->as, addr);
break;
}
break;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 13/22] exec: Make lduw_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (11 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 12/22] exec: Make ldq/ldub_*_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 14/22] exec: Make stq_*_phys " edgar.iglesias
` (8 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 18 +++++++++---------
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 6 +++---
hw/s390x/css.c | 3 ++-
hw/s390x/virtio-ccw.c | 8 +++++---
hw/virtio/virtio.c | 16 ++++++++--------
include/exec/cpu-common.h | 6 +++---
target-i386/smm_helper.c | 12 ++++++------
target-i386/svm_helper.c | 15 ++++++++-------
target-sparc/ldst_helper.c | 6 +++---
10 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index db64e13..7ab6153 100644
--- a/exec.c
+++ b/exec.c
@@ -1597,7 +1597,7 @@ static uint64_t watch_mem_read(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
switch (size) {
case 1: return ldub_phys(&address_space_memory, addr);
- case 2: return lduw_phys(addr);
+ case 2: return lduw_phys(&address_space_memory, addr);
case 4: return ldl_phys(&address_space_memory, addr);
default: abort();
}
@@ -2435,7 +2435,7 @@ uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(hwaddr addr,
+static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2444,7 +2444,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
hwaddr l = 2;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
false);
if (l < 2 || !memory_access_is_direct(mr, false)) {
/* I/O case */
@@ -2478,19 +2478,19 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
return val;
}
-uint32_t lduw_phys(hwaddr addr)
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(hwaddr addr)
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(hwaddr addr)
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
{
- return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
+ return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index eb98d2a..7877cb6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -80,7 +80,7 @@ vmw_shmem_st8(hwaddr addr, uint8_t value)
static inline uint32_t
vmw_shmem_ld16(hwaddr addr)
{
- uint16_t res = lduw_le_phys(addr);
+ uint16_t res = lduw_le_phys(&address_space_memory, addr);
VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
return res;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 942751b..b1d5b91 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -354,7 +354,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
}
/* FIXME: bounds check the address */
- size = lduw_be_phys(vpa + 0x4);
+ size = lduw_be_phys(env->as, vpa + 0x4);
if (size < VPA_MIN_SIZE) {
return H_PARAMETER;
@@ -540,7 +540,7 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
args[0] = ldub_phys(cpu->env.as, addr);
return H_SUCCESS;
case 2:
- args[0] = lduw_phys(addr);
+ args[0] = lduw_phys(cpu->env.as, addr);
return H_SUCCESS;
case 4:
args[0] = ldl_phys(cpu->env.as, addr);
@@ -608,7 +608,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
tmp = ldub_phys(cpu->env.as, src);
break;
case 1:
- tmp = lduw_phys(src);
+ tmp = lduw_phys(cpu->env.as, src);
break;
case 2:
tmp = ldl_phys(cpu->env.as, src);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index 41b1903..d42d7ec 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -677,7 +677,8 @@ static void css_update_chnmon(SubchDev *sch)
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
- count = lduw_phys(channel_subsys->chnmon_area + offset);
+ count = lduw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset);
count++;
stw_phys(channel_subsys->chnmon_area + offset, count);
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index b86d94e..a92cbde 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -268,9 +268,11 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
info.queue = ldq_phys(&address_space_memory, ccw.cda);
info.align = ldl_phys(&address_space_memory,
ccw.cda + sizeof(info.queue));
- info.index = lduw_phys(ccw.cda + sizeof(info.queue)
+ info.index = lduw_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue)
+ sizeof(info.align));
- info.num = lduw_phys(ccw.cda + sizeof(info.queue)
+ info.num = lduw_phys(&address_space_memory,
+ ccw.cda + sizeof(info.queue)
+ sizeof(info.align)
+ sizeof(info.index));
ret = virtio_ccw_set_vqs(sch, info.queue, info.align, info.index,
@@ -472,7 +474,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
if (!ccw.cda) {
ret = -EFAULT;
} else {
- vq_config.index = lduw_phys(ccw.cda);
+ vq_config.index = lduw_phys(&address_space_memory, ccw.cda);
vq_config.num_max = virtio_queue_get_num(vdev,
vq_config.index);
stw_phys(ccw.cda + sizeof(vq_config.index), vq_config.num_max);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index e5bd115..492022c 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -119,35 +119,35 @@ static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_desc_next(hwaddr desc_pa, int i)
{
hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_flags(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, flags);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_idx(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, idx);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_avail_ring(VirtQueue *vq, int i)
{
hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, ring[i]);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline uint16_t vring_used_event(VirtQueue *vq)
@@ -173,7 +173,7 @@ static uint16_t vring_used_idx(VirtQueue *vq)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
- return lduw_phys(pa);
+ return lduw_phys(&address_space_memory, pa);
}
static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
@@ -187,14 +187,14 @@ static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(pa) | mask);
+ stw_phys(pa, lduw_phys(&address_space_memory, pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(pa) & ~mask);
+ stw_phys(pa, lduw_phys(&address_space_memory, pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 086ae97..0a8f836 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -84,8 +84,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr);
void qemu_flush_coalesced_mmio_buffer(void);
uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
-uint32_t lduw_le_phys(hwaddr addr);
-uint32_t lduw_be_phys(hwaddr addr);
+uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
+uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
@@ -99,7 +99,7 @@ void stq_le_phys(hwaddr addr, uint64_t val);
void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
-uint32_t lduw_phys(hwaddr addr);
+uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index e591f83..7a9bfa1 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -192,28 +192,28 @@ void helper_rsm(CPUX86State *env)
for (i = 0; i < 6; i++) {
offset = 0x7e00 + i * 16;
cpu_x86_load_seg_cache(env, i,
- lduw_phys(sm_state + offset),
+ lduw_phys(env->as, sm_state + offset),
ldq_phys(env->as, sm_state + offset + 8),
ldl_phys(env->as, sm_state + offset + 4),
- (lduw_phys(sm_state + offset + 2) &
+ (lduw_phys(env->as, sm_state + offset + 2) &
0xf0ff) << 8);
}
env->gdt.base = ldq_phys(env->as, sm_state + 0x7e68);
env->gdt.limit = ldl_phys(env->as, sm_state + 0x7e64);
- env->ldt.selector = lduw_phys(sm_state + 0x7e70);
+ env->ldt.selector = lduw_phys(env->as, sm_state + 0x7e70);
env->ldt.base = ldq_phys(env->as, sm_state + 0x7e78);
env->ldt.limit = ldl_phys(env->as, sm_state + 0x7e74);
- env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
+ env->ldt.flags = (lduw_phys(env->as, sm_state + 0x7e72) & 0xf0ff) << 8;
env->idt.base = ldq_phys(env->as, sm_state + 0x7e88);
env->idt.limit = ldl_phys(env->as, sm_state + 0x7e84);
- env->tr.selector = lduw_phys(sm_state + 0x7e90);
+ env->tr.selector = lduw_phys(env->as, sm_state + 0x7e90);
env->tr.base = ldq_phys(env->as, sm_state + 0x7e98);
env->tr.limit = ldl_phys(env->as, sm_state + 0x7e94);
- env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
+ env->tr.flags = (lduw_phys(env->as, sm_state + 0x7e92) & 0xf0ff) << 8;
env->regs[R_EAX] = ldq_phys(env->as, sm_state + 0x7ff8);
env->regs[R_ECX] = ldq_phys(env->as, sm_state + 0x7ff0);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 2c61be2..72d92df 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -103,10 +103,11 @@ static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
{
unsigned int flags;
- sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
+ sc->selector = lduw_phys(env->as,
+ addr + offsetof(struct vmcb_seg, selector));
sc->base = ldq_phys(env->as, addr + offsetof(struct vmcb_seg, base));
sc->limit = ldl_phys(env->as, addr + offsetof(struct vmcb_seg, limit));
- flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
+ flags = lduw_phys(env->as, addr + offsetof(struct vmcb_seg, attrib));
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
@@ -178,16 +179,16 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
vmcb in svm mode */
env->intercept = ldq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.intercept));
- env->intercept_cr_read = lduw_phys(env->vm_vmcb +
+ env->intercept_cr_read = lduw_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_cr_read));
- env->intercept_cr_write = lduw_phys(env->vm_vmcb +
+ env->intercept_cr_write = lduw_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_cr_write));
- env->intercept_dr_read = lduw_phys(env->vm_vmcb +
+ env->intercept_dr_read = lduw_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_read));
- env->intercept_dr_write = lduw_phys(env->vm_vmcb +
+ env->intercept_dr_write = lduw_phys(env->as, env->vm_vmcb +
offsetof(struct vmcb,
control.intercept_dr_write));
env->intercept_exceptions = ldl_phys(env->as, env->vm_vmcb +
@@ -554,7 +555,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
offsetof(struct vmcb, control.iopm_base_pa));
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
- if (lduw_phys(addr + port / 8) & (mask << (port & 7))) {
+ if (lduw_phys(env->as, addr + port / 8) & (mask << (port & 7))) {
/* next env->eip */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
env->eip + next_eip_addend);
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index e26c763..03afa86 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -611,7 +611,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldub_phys(env->as, addr);
break;
case 2:
- ret = lduw_phys(addr);
+ ret = lduw_phys(env->as, addr);
break;
default:
case 4:
@@ -629,7 +629,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
| ((hwaddr)(asi & 0xf) << 32));
break;
case 2:
- ret = lduw_phys((hwaddr)addr
+ ret = lduw_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32));
break;
default:
@@ -1439,7 +1439,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
ret = ldub_phys(env->as, addr);
break;
case 2:
- ret = lduw_phys(addr);
+ ret = lduw_phys(env->as, addr);
break;
case 4:
ret = ldl_phys(env->as, addr);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 14/22] exec: Make stq_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (12 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 13/22] exec: Make lduw_*_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 15/22] exec: Make stl_*_phys " edgar.iglesias
` (7 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 12 +++---
hw/alpha/dp264.c | 5 ++-
hw/net/vmware_utils.h | 2 +-
hw/ppc/spapr_hcall.c | 4 +-
hw/s390x/s390-virtio-bus.c | 3 +-
hw/s390x/virtio-ccw.c | 4 +-
hw/scsi/megasas.c | 3 +-
include/exec/cpu-common.h | 6 +--
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 6 +--
target-alpha/translate.c | 2 +-
target-i386/helper.c | 3 +-
target-i386/smm_helper.c | 32 +++++++-------
target-i386/svm_helper.c | 102 +++++++++++++++++++++++++++-----------------
target-ppc/mmu-hash64.h | 5 ++-
target-s390x/helper.c | 6 ++-
target-s390x/mem_helper.c | 2 +-
target-sparc/ldst_helper.c | 14 +++---
18 files changed, 121 insertions(+), 92 deletions(-)
diff --git a/exec.c b/exec.c
index 7ab6153..57aebd1 100644
--- a/exec.c
+++ b/exec.c
@@ -2644,22 +2644,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stq_phys(hwaddr addr, uint64_t val)
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_le_phys(hwaddr addr, uint64_t val)
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
-void stq_be_phys(hwaddr addr, uint64_t val)
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
- cpu_physical_memory_write(addr, &val, 8);
+ address_space_rw(as, addr, (void *) &val, 8, 1);
}
/* virtual memory access for debug (includes writing to ROM) */
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 20795ac..1351ba5 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
- stq_phys(param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
- stq_phys(param_offset + 0x108, initrd_size);
+ stq_phys(&address_space_memory,
+ param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
+ stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 7877cb6..4cf0e79 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
- stq_le_phys(addr, value);
+ stq_le_phys(&address_space_memory, addr, value);
}
/* Macros for simplification of operations on array-style registers */
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index b1d5b91..5becf91 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
- stq_phys(addr, val);
+ stq_phys(cpu->env.as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
@@ -633,7 +633,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
- stq_phys(dst, tmp);
+ stq_phys(cpu->env.as, dst, tmp);
break;
}
dst = dst + step;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index e8e6e10..5da28d7 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
- stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
+ stq_be_phys(&address_space_memory,
+ vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
}
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index a92cbde..0bb98ae 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -876,7 +876,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
}
indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
- stq_phys(dev->indicators, indicators);
+ stq_phys(&address_space_memory, dev->indicators, indicators);
} else {
if (!dev->indicators2) {
return;
@@ -884,7 +884,7 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
vector = 0;
indicators = ldq_phys(&address_space_memory, dev->indicators2);
indicators |= 1ULL << vector;
- stq_phys(dev->indicators2, indicators);
+ stq_phys(&address_space_memory, dev->indicators2, indicators);
}
css_conditional_io_interrupt(sch);
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 33bcb97..673cb61 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -517,7 +517,8 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
tail = s->reply_queue_head;
if (megasas_use_queue64(s)) {
queue_offset = tail * sizeof(uint64_t);
- stq_le_phys(s->reply_queue_pa + queue_offset, context);
+ stq_le_phys(&address_space_memory,
+ s->reply_queue_pa + queue_offset, context);
} else {
queue_offset = tail * sizeof(uint32_t);
stl_le_phys(s->reply_queue_pa + queue_offset, context);
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 0a8f836..e37a0b6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -95,8 +95,8 @@ void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
void stl_le_phys(hwaddr addr, uint32_t val);
void stl_be_phys(hwaddr addr, uint32_t val);
-void stq_le_phys(hwaddr addr, uint64_t val);
-void stq_be_phys(hwaddr addr, uint64_t val);
+void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
+void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
@@ -105,7 +105,7 @@ uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
-void stq_phys(hwaddr addr, uint64_t val);
+void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
void cpu_physical_memory_write_rom(hwaddr addr,
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 74dbd07..c67266b 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -106,7 +106,7 @@ DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
DEF_HELPER_2(stl_phys, void, i64, i64)
-DEF_HELPER_2(stq_phys, void, i64, i64)
+DEF_HELPER_3(stq_phys, void, env, i64, i64)
DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 513dbed..8d3abaf 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -51,9 +51,9 @@ void helper_stl_phys(uint64_t p, uint64_t v)
stl_phys(p, v);
}
-void helper_stq_phys(uint64_t p, uint64_t v)
+void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
- stq_phys(p, v);
+ stq_phys(env->as, p, v);
}
uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
@@ -79,7 +79,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
if (p == env->lock_addr) {
uint64_t old = ldq_phys(env->as, p);
if (old == env->lock_value) {
- stq_phys(p, v);
+ stq_phys(env->as, p, v);
ret = 1;
}
}
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index f60ee35..69e2334 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3229,7 +3229,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1:
/* Quadword physical access */
- gen_helper_stq_phys(addr, val);
+ gen_helper_stq_phys(cpu_env, addr, val);
break;
case 0x2:
/* Longword physical access with lock */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 028fa03..27461f1 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -874,7 +874,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
error_code |= PG_ERROR_I_D_MASK;
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
/* cr2 is not modified in case of exceptions */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
addr);
} else {
env->cr[2] = addr;
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 7a9bfa1..49a4324 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -62,39 +62,39 @@ void do_smm_enter(X86CPU *cpu)
stw_phys(sm_state + offset, dt->selector);
stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
stl_phys(sm_state + offset + 4, dt->limit);
- stq_phys(sm_state + offset + 8, dt->base);
+ stq_phys(env->as, sm_state + offset + 8, dt->base);
}
- stq_phys(sm_state + 0x7e68, env->gdt.base);
+ stq_phys(env->as, sm_state + 0x7e68, env->gdt.base);
stl_phys(sm_state + 0x7e64, env->gdt.limit);
stw_phys(sm_state + 0x7e70, env->ldt.selector);
- stq_phys(sm_state + 0x7e78, env->ldt.base);
+ stq_phys(env->as, sm_state + 0x7e78, env->ldt.base);
stl_phys(sm_state + 0x7e74, env->ldt.limit);
stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
- stq_phys(sm_state + 0x7e88, env->idt.base);
+ stq_phys(env->as, sm_state + 0x7e88, env->idt.base);
stl_phys(sm_state + 0x7e84, env->idt.limit);
stw_phys(sm_state + 0x7e90, env->tr.selector);
- stq_phys(sm_state + 0x7e98, env->tr.base);
+ stq_phys(env->as, sm_state + 0x7e98, env->tr.base);
stl_phys(sm_state + 0x7e94, env->tr.limit);
stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
- stq_phys(sm_state + 0x7ed0, env->efer);
+ stq_phys(env->as, sm_state + 0x7ed0, env->efer);
- stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
- stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
- stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
- stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
- stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
- stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
- stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
- stq_phys(sm_state + 0x7fc0, env->regs[R_EDI]);
+ stq_phys(env->as, sm_state + 0x7ff8, env->regs[R_EAX]);
+ stq_phys(env->as, sm_state + 0x7ff0, env->regs[R_ECX]);
+ stq_phys(env->as, sm_state + 0x7fe8, env->regs[R_EDX]);
+ stq_phys(env->as, sm_state + 0x7fe0, env->regs[R_EBX]);
+ stq_phys(env->as, sm_state + 0x7fd8, env->regs[R_ESP]);
+ stq_phys(env->as, sm_state + 0x7fd0, env->regs[R_EBP]);
+ stq_phys(env->as, sm_state + 0x7fc8, env->regs[R_ESI]);
+ stq_phys(env->as, sm_state + 0x7fc0, env->regs[R_EDI]);
for (i = 8; i < 16; i++) {
- stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
+ stq_phys(env->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
- stq_phys(sm_state + 0x7f78, env->eip);
+ stq_phys(env->as, sm_state + 0x7f78, env->eip);
stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
stl_phys(sm_state + 0x7f68, env->dr[6]);
stl_phys(sm_state + 0x7f60, env->dr[7]);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 72d92df..4dd2056 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -90,7 +90,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
{
stw_phys(addr + offsetof(struct vmcb_seg, selector),
sc->selector);
- stq_phys(addr + offsetof(struct vmcb_seg, base),
+ stq_phys(env->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
stl_phys(addr + offsetof(struct vmcb_seg, limit),
sc->limit);
@@ -140,25 +140,33 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->vm_vmcb = addr;
/* save the current CPU state in the hsave page */
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
+ stq_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
+ stq_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
-
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags),
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
+
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es),
@@ -170,10 +178,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
&env->segs[R_DS]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
+ stq_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.rip),
env->eip + next_eip_addend);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
- stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
+ stq_phys(env->as,
+ env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
/* load the interception bitmaps so we do not need to access the
vmcb in svm mode */
@@ -213,7 +223,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
save.idtr.limit));
/* clear exit_info_2 so we behave like the real hardware */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
cpu_x86_update_cr0(env, ldq_phys(env->as,
env->vm_vmcb + offsetof(struct vmcb,
@@ -416,17 +427,18 @@ void helper_vmsave(CPUX86State *env, int aflag)
&env->ldt);
#ifdef TARGET_X86_64
- stq_phys(addr + offsetof(struct vmcb, save.kernel_gs_base),
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.kernel_gs_base),
env->kernelgsbase);
- stq_phys(addr + offsetof(struct vmcb, save.lstar), env->lstar);
- stq_phys(addr + offsetof(struct vmcb, save.cstar), env->cstar);
- stq_phys(addr + offsetof(struct vmcb, save.sfmask), env->fmask);
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.lstar), env->lstar);
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.cstar), env->cstar);
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.sfmask), env->fmask);
#endif
- stq_phys(addr + offsetof(struct vmcb, save.star), env->star);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_esp),
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.star), env->star);
+ stq_phys(env->as,
+ addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.sysenter_esp),
env->sysenter_esp);
- stq_phys(addr + offsetof(struct vmcb, save.sysenter_eip),
+ stq_phys(env->as, addr + offsetof(struct vmcb, save.sysenter_eip),
env->sysenter_eip);
}
@@ -557,7 +569,8 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
if (lduw_phys(env->as, addr + port / 8) & (mask << (port & 7))) {
/* next env->eip */
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
env->eip + next_eip_addend);
helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16));
}
@@ -595,21 +608,26 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
&env->segs[R_DS]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
int_ctl = ldl_phys(env->as,
env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
@@ -620,14 +638,18 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
}
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.rip),
env->eip);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
+ stq_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
env->hflags & HF_CPL_MASK);
@@ -693,9 +715,9 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
/* other setups */
cpu_x86_set_cpl(env, 0);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_code),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_code),
exit_code);
- stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
+ stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
exit_info_1);
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 16f71a3..7b10348 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -102,7 +102,7 @@ static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
if (env->external_htab) {
stq_p(env->external_htab + pte_offset, pte0);
} else {
- stq_phys(env->htab_base + pte_offset, pte0);
+ stq_phys(env->as, env->htab_base + pte_offset, pte0);
}
}
@@ -112,7 +112,8 @@ static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
if (env->external_htab) {
stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
} else {
- stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+ stq_phys(env->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
}
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 12338a0..3043600 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -143,7 +143,8 @@ static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ stq_phys(env->as,
+ env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, PGM_PROTECTION, ilen);
}
@@ -160,7 +161,8 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ stq_phys(env->as,
+ env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, type, ilen);
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 55e889b..fb7650a 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1018,7 +1018,7 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
According to spec we'd have to find it out ourselves */
/* XXX Linux is fine with overwriting the pte, the spec requires
us to only set the invalid bit */
- stq_phys(pte_addr, pte | _PAGE_INVALID);
+ stq_phys(env->as, pte_addr, pte | _PAGE_INVALID);
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 03afa86..8e7f7b8 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -792,13 +792,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
"%08x: unimplemented access size: %d\n", addr,
size);
}
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
+ stq_phys(env->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
env->mxccdata[0]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
+ stq_phys(env->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
env->mxccdata[1]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
+ stq_phys(env->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
env->mxccdata[2]);
- stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
+ stq_phys(env->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
env->mxccdata[3]);
break;
case 0x01c00a00: /* MXCC control register */
@@ -1020,7 +1020,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
stl_phys(addr, val);
break;
case 8:
- stq_phys(addr, val);
+ stq_phys(env->as, addr, val);
break;
}
}
@@ -1042,7 +1042,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 8:
- stq_phys((hwaddr)addr
+ stq_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
}
@@ -1817,7 +1817,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
break;
case 8:
default:
- stq_phys(addr, val);
+ stq_phys(env->as, addr, val);
break;
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 15/22] exec: Make stl_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (13 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 14/22] exec: Make stq_*_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 16/22] exec: Make stl_phys_notdirty " edgar.iglesias
` (6 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 19 +++++----
hw/net/vmware_utils.h | 2 +-
hw/pci/msi.c | 2 +-
hw/pci/msix.c | 2 +-
hw/ppc/ppc405_uc.c | 32 +++++++-------
hw/ppc/spapr_hcall.c | 4 +-
hw/s390x/css.c | 2 +-
hw/s390x/s390-virtio-bus.c | 2 +-
hw/s390x/virtio-ccw.c | 2 +-
hw/scsi/megasas.c | 6 ++-
hw/scsi/vmw_pvscsi.c | 3 +-
hw/sh4/r2d.c | 2 +-
hw/timer/hpet.c | 3 +-
hw/virtio/virtio.c | 4 +-
include/exec/cpu-common.h | 6 +--
include/hw/ppc/spapr.h | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/mem_helper.c | 6 +--
target-alpha/translate.c | 2 +-
target-arm/helper.c | 2 +-
target-i386/seg_helper.c | 8 ++--
target-i386/smm_helper.c | 100 ++++++++++++++++++++++----------------------
target-i386/svm_helper.c | 28 ++++++++-----
target-ppc/mmu-hash32.h | 4 +-
target-sparc/ldst_helper.c | 6 +--
25 files changed, 132 insertions(+), 119 deletions(-)
diff --git a/exec.c b/exec.c
index 57aebd1..1dfdc3c 100644
--- a/exec.c
+++ b/exec.c
@@ -1615,7 +1615,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stw_phys(addr, val);
break;
case 4:
- stl_phys(addr, val);
+ stl_phys(&address_space_memory, addr, val);
break;
default: abort();
}
@@ -2525,7 +2525,8 @@ void stl_phys_notdirty(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(hwaddr addr, uint32_t val,
+static inline void stl_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2533,7 +2534,7 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
@@ -2565,19 +2566,19 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
}
}
-void stl_phys(hwaddr addr, uint32_t val)
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(hwaddr addr, uint32_t val)
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(hwaddr addr, uint32_t val)
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+ stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 4cf0e79..2ed73af 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -104,7 +104,7 @@ static inline void
vmw_shmem_st32(hwaddr addr, uint32_t value)
{
VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
- stl_le_phys(addr, value);
+ stl_le_phys(&address_space_memory, addr, value);
}
static inline uint64_t
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
index 2a04d18..a4a3040 100644
--- a/hw/pci/msi.c
+++ b/hw/pci/msi.c
@@ -291,7 +291,7 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
"notify vector 0x%x"
" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
vector, msg.address, msg.data);
- stl_le_phys(msg.address, msg.data);
+ stl_le_phys(&address_space_memory, msg.address, msg.data);
}
/* Normally called by pci_default_write_config(). */
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 3430770..5c49bfc 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -439,7 +439,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
msg = msix_get_message(dev, vector);
- stl_le_phys(msg.address, msg.data);
+ stl_le_phys(&address_space_memory, msg.address, msg.data);
}
void msix_reset(PCIDevice *dev)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8109f92..09a23ce 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -52,30 +52,30 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
else
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
- stl_be_phys(bdloc + 0x00, bd->bi_memstart);
- stl_be_phys(bdloc + 0x04, bd->bi_memsize);
- stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
- stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
- stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
- stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
- stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
- stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
- stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
+ stl_be_phys(env->as, bdloc + 0x00, bd->bi_memstart);
+ stl_be_phys(env->as, bdloc + 0x04, bd->bi_memsize);
+ stl_be_phys(env->as, bdloc + 0x08, bd->bi_flashstart);
+ stl_be_phys(env->as, bdloc + 0x0C, bd->bi_flashsize);
+ stl_be_phys(env->as, bdloc + 0x10, bd->bi_flashoffset);
+ stl_be_phys(env->as, bdloc + 0x14, bd->bi_sramstart);
+ stl_be_phys(env->as, bdloc + 0x18, bd->bi_sramsize);
+ stl_be_phys(env->as, bdloc + 0x1C, bd->bi_bootflags);
+ stl_be_phys(env->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
- stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
- stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
- stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
+ stl_be_phys(env->as, bdloc + 0x2C, bd->bi_intfreq);
+ stl_be_phys(env->as, bdloc + 0x30, bd->bi_busfreq);
+ stl_be_phys(env->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
}
- stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
- stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
+ stl_be_phys(env->as, bdloc + 0x5C, bd->bi_plb_busfreq);
+ stl_be_phys(env->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
@@ -84,10 +84,10 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++)
stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
- stl_be_phys(bdloc + n, bd->bi_opbfreq);
+ stl_be_phys(env->as, bdloc + n, bd->bi_opbfreq);
n += 4;
for (i = 0; i < 2; i++) {
- stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
+ stl_be_phys(env->as, bdloc + n, bd->bi_iic_fast[i]);
n += 4;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 5becf91..8f5a242 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -567,7 +567,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stw_phys(addr, val);
return H_SUCCESS;
case 4:
- stl_phys(addr, val);
+ stl_phys(cpu->env.as, addr, val);
return H_SUCCESS;
case 8:
stq_phys(cpu->env.as, addr, val);
@@ -630,7 +630,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stw_phys(dst, tmp);
break;
case 2:
- stl_phys(dst, tmp);
+ stl_phys(cpu->env.as, dst, tmp);
break;
case 3:
stq_phys(cpu->env.as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index d42d7ec..cfa8a9b 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -670,7 +670,7 @@ static void css_update_chnmon(SubchDev *sch)
count = ldl_phys(&address_space_memory, sch->curr_status.mba);
count++;
- stl_phys(sch->curr_status.mba, count);
+ stl_phys(&address_space_memory, sch->curr_status.mba, count);
} else {
/* Format 0, global area. */
uint32_t offset;
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index 5da28d7..f8d51b3 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -388,7 +388,7 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
cur_offs += num_vq * VIRTIO_VQCONFIG_LEN;
/* Sync feature bitmap */
- stl_le_phys(cur_offs, dev->host_features);
+ stl_le_phys(&address_space_memory, cur_offs, dev->host_features);
dev->feat_offs = cur_offs + dev->feat_len;
cur_offs += dev->feat_len * 2;
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 0bb98ae..c74d00b 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -307,7 +307,7 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
/* Return zeroes if the guest supports more feature bits. */
features.features = 0;
}
- stl_le_phys(ccw.cda, features.features);
+ stl_le_phys(&address_space_memory, ccw.cda, features.features);
sch->curr_status.scsw.count = ccw.count - sizeof(features);
ret = 0;
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 673cb61..e12f80c 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -521,7 +521,8 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
s->reply_queue_pa + queue_offset, context);
} else {
queue_offset = tail * sizeof(uint32_t);
- stl_le_phys(s->reply_queue_pa + queue_offset, context);
+ stl_le_phys(&address_space_memory,
+ s->reply_queue_pa + queue_offset, context);
}
s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
trace_megasas_qf_complete(context, tail, queue_offset,
@@ -1951,7 +1952,8 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
if (s->producer_pa && megasas_intr_enabled(s)) {
/* Update reply queue pointer */
trace_megasas_qf_update(s->reply_queue_head, s->busy);
- stl_le_phys(s->producer_pa, s->reply_queue_head);
+ stl_le_phys(&address_space_memory,
+ s->producer_pa, s->reply_queue_head);
if (!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 6cc6c1b..7d344b9 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -46,7 +46,8 @@
(ldl_le_phys(&address_space_memory, \
rs_pa + offsetof(struct PVSCSIRingsState, field)))
#define RS_SET_FIELD(rs_pa, field, val) \
- (stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val))
+ (stl_le_phys(&address_space_memory, \
+ rs_pa + offsetof(struct PVSCSIRingsState, field), val))
#define TYPE_PVSCSI "pvscsi"
#define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 7b1de85..76ef869 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -318,7 +318,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
}
/* initialization which should be done by firmware */
- stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
+ stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
}
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index bb3bf98..5f2ed69 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -206,7 +206,8 @@ static void update_irq(struct HPETTimer *timer, int set)
}
}
} else if (timer_fsb_route(timer)) {
- stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
+ stl_le_phys(&address_space_memory,
+ timer->fsb >> 32, timer->fsb & 0xffffffff);
} else if (timer->config & HPET_TN_TYPE_LEVEL) {
s->isr |= mask;
/* fold the ICH PIRQ# pin's internal inversion logic into hpet */
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 492022c..3a00020 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -159,14 +159,14 @@ static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].id);
- stl_phys(pa, val);
+ stl_phys(&address_space_memory, pa, val);
}
static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].len);
- stl_phys(pa, val);
+ stl_phys(&address_space_memory, pa, val);
}
static uint16_t vring_used_idx(VirtQueue *vq)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index e37a0b6..b29065d 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -93,8 +93,8 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
-void stl_le_phys(hwaddr addr, uint32_t val);
-void stl_be_phys(hwaddr addr, uint32_t val);
+void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
+void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
@@ -104,7 +104,7 @@ uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
-void stl_phys(hwaddr addr, uint32_t val);
+void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index aec756e..1a998c3 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -344,7 +344,7 @@ static inline uint32_t rtas_ld(target_ulong phys, int n)
static inline void rtas_st(target_ulong phys, int n, uint32_t val)
{
- stl_be_phys(ppc64_phys_to_real(phys + 4*n), val);
+ stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
}
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index c67266b..4f127c4 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -105,7 +105,7 @@ DEF_HELPER_2(ldl_phys, i64, env, i64)
DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
-DEF_HELPER_2(stl_phys, void, i64, i64)
+DEF_HELPER_3(stl_phys, void, env, i64, i64)
DEF_HELPER_3(stq_phys, void, env, i64, i64)
DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 8d3abaf..515442d 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -46,9 +46,9 @@ uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
return env->lock_value = ldq_phys(env->as, p);
}
-void helper_stl_phys(uint64_t p, uint64_t v)
+void helper_stl_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
- stl_phys(p, v);
+ stl_phys(env->as, p, v);
}
void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
@@ -63,7 +63,7 @@ uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
if (p == env->lock_addr) {
int32_t old = ldl_phys(env->as, p);
if (old == (int32_t)env->lock_value) {
- stl_phys(p, v);
+ stl_phys(env->as, p, v);
ret = 1;
}
}
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 69e2334..4c94bed 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3225,7 +3225,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access */
- gen_helper_stl_phys(addr, val);
+ gen_helper_stl_phys(cpu_env, addr, val);
break;
case 0x1:
/* Quadword physical access */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 09e58f0..1b6fef5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2226,7 +2226,7 @@ void switch_mode(CPUARMState *env, int mode)
static void v7m_push(CPUARMState *env, uint32_t val)
{
env->regs[13] -= 4;
- stl_phys(env->regs[13], val);
+ stl_phys(env->as, env->regs[13], val);
}
static uint32_t v7m_pop(CPUARMState *env)
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 0c7216f..c0f165e 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1145,11 +1145,12 @@ static void handle_even_inj(CPUX86State *env, int intno, int is_int,
event_inj = intno | type | SVM_EVTINJ_VALID;
if (!rm && exception_has_error_code(intno)) {
event_inj |= SVM_EVTINJ_VALID_ERR;
- stl_phys(env->vm_vmcb + offsetof(struct vmcb,
+ stl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err),
error_code);
}
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
event_inj);
}
}
@@ -1229,7 +1230,8 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
offsetof(struct vmcb,
control.event_inj));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
event_inj & ~SVM_EVTINJ_VALID);
}
#endif
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 49a4324..d68aee7 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -61,24 +61,24 @@ void do_smm_enter(X86CPU *cpu)
offset = 0x7e00 + i * 16;
stw_phys(sm_state + offset, dt->selector);
stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
- stl_phys(sm_state + offset + 4, dt->limit);
+ stl_phys(env->as, sm_state + offset + 4, dt->limit);
stq_phys(env->as, sm_state + offset + 8, dt->base);
}
stq_phys(env->as, sm_state + 0x7e68, env->gdt.base);
- stl_phys(sm_state + 0x7e64, env->gdt.limit);
+ stl_phys(env->as, sm_state + 0x7e64, env->gdt.limit);
stw_phys(sm_state + 0x7e70, env->ldt.selector);
stq_phys(env->as, sm_state + 0x7e78, env->ldt.base);
- stl_phys(sm_state + 0x7e74, env->ldt.limit);
+ stl_phys(env->as, sm_state + 0x7e74, env->ldt.limit);
stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
stq_phys(env->as, sm_state + 0x7e88, env->idt.base);
- stl_phys(sm_state + 0x7e84, env->idt.limit);
+ stl_phys(env->as, sm_state + 0x7e84, env->idt.limit);
stw_phys(sm_state + 0x7e90, env->tr.selector);
stq_phys(env->as, sm_state + 0x7e98, env->tr.base);
- stl_phys(sm_state + 0x7e94, env->tr.limit);
+ stl_phys(env->as, sm_state + 0x7e94, env->tr.limit);
stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
stq_phys(env->as, sm_state + 0x7ed0, env->efer);
@@ -95,47 +95,47 @@ void do_smm_enter(X86CPU *cpu)
stq_phys(env->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
stq_phys(env->as, sm_state + 0x7f78, env->eip);
- stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
- stl_phys(sm_state + 0x7f68, env->dr[6]);
- stl_phys(sm_state + 0x7f60, env->dr[7]);
+ stl_phys(env->as, sm_state + 0x7f70, cpu_compute_eflags(env));
+ stl_phys(env->as, sm_state + 0x7f68, env->dr[6]);
+ stl_phys(env->as, sm_state + 0x7f60, env->dr[7]);
- stl_phys(sm_state + 0x7f48, env->cr[4]);
- stl_phys(sm_state + 0x7f50, env->cr[3]);
- stl_phys(sm_state + 0x7f58, env->cr[0]);
+ stl_phys(env->as, sm_state + 0x7f48, env->cr[4]);
+ stl_phys(env->as, sm_state + 0x7f50, env->cr[3]);
+ stl_phys(env->as, sm_state + 0x7f58, env->cr[0]);
- stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
- stl_phys(sm_state + 0x7f00, env->smbase);
+ stl_phys(env->as, sm_state + 0x7efc, SMM_REVISION_ID);
+ stl_phys(env->as, sm_state + 0x7f00, env->smbase);
#else
- stl_phys(sm_state + 0x7ffc, env->cr[0]);
- stl_phys(sm_state + 0x7ff8, env->cr[3]);
- stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
- stl_phys(sm_state + 0x7ff0, env->eip);
- stl_phys(sm_state + 0x7fec, env->regs[R_EDI]);
- stl_phys(sm_state + 0x7fe8, env->regs[R_ESI]);
- stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
- stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
- stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
- stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
- stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
- stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
- stl_phys(sm_state + 0x7fcc, env->dr[6]);
- stl_phys(sm_state + 0x7fc8, env->dr[7]);
-
- stl_phys(sm_state + 0x7fc4, env->tr.selector);
- stl_phys(sm_state + 0x7f64, env->tr.base);
- stl_phys(sm_state + 0x7f60, env->tr.limit);
- stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
-
- stl_phys(sm_state + 0x7fc0, env->ldt.selector);
- stl_phys(sm_state + 0x7f80, env->ldt.base);
- stl_phys(sm_state + 0x7f7c, env->ldt.limit);
- stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
-
- stl_phys(sm_state + 0x7f74, env->gdt.base);
- stl_phys(sm_state + 0x7f70, env->gdt.limit);
-
- stl_phys(sm_state + 0x7f58, env->idt.base);
- stl_phys(sm_state + 0x7f54, env->idt.limit);
+ stl_phys(env->as, sm_state + 0x7ffc, env->cr[0]);
+ stl_phys(env->as, sm_state + 0x7ff8, env->cr[3]);
+ stl_phys(env->as, sm_state + 0x7ff4, cpu_compute_eflags(env));
+ stl_phys(env->as, sm_state + 0x7ff0, env->eip);
+ stl_phys(env->as, sm_state + 0x7fec, env->regs[R_EDI]);
+ stl_phys(env->as, sm_state + 0x7fe8, env->regs[R_ESI]);
+ stl_phys(env->as, sm_state + 0x7fe4, env->regs[R_EBP]);
+ stl_phys(env->as, sm_state + 0x7fe0, env->regs[R_ESP]);
+ stl_phys(env->as, sm_state + 0x7fdc, env->regs[R_EBX]);
+ stl_phys(env->as, sm_state + 0x7fd8, env->regs[R_EDX]);
+ stl_phys(env->as, sm_state + 0x7fd4, env->regs[R_ECX]);
+ stl_phys(env->as, sm_state + 0x7fd0, env->regs[R_EAX]);
+ stl_phys(env->as, sm_state + 0x7fcc, env->dr[6]);
+ stl_phys(env->as, sm_state + 0x7fc8, env->dr[7]);
+
+ stl_phys(env->as, sm_state + 0x7fc4, env->tr.selector);
+ stl_phys(env->as, sm_state + 0x7f64, env->tr.base);
+ stl_phys(env->as, sm_state + 0x7f60, env->tr.limit);
+ stl_phys(env->as, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
+
+ stl_phys(env->as, sm_state + 0x7fc0, env->ldt.selector);
+ stl_phys(env->as, sm_state + 0x7f80, env->ldt.base);
+ stl_phys(env->as, sm_state + 0x7f7c, env->ldt.limit);
+ stl_phys(env->as, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
+
+ stl_phys(env->as, sm_state + 0x7f74, env->gdt.base);
+ stl_phys(env->as, sm_state + 0x7f70, env->gdt.limit);
+
+ stl_phys(env->as, sm_state + 0x7f58, env->idt.base);
+ stl_phys(env->as, sm_state + 0x7f54, env->idt.limit);
for (i = 0; i < 6; i++) {
dt = &env->segs[i];
@@ -144,15 +144,15 @@ void do_smm_enter(X86CPU *cpu)
} else {
offset = 0x7f2c + (i - 3) * 12;
}
- stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
- stl_phys(sm_state + offset + 8, dt->base);
- stl_phys(sm_state + offset + 4, dt->limit);
- stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
+ stl_phys(env->as, sm_state + 0x7fa8 + i * 4, dt->selector);
+ stl_phys(env->as, sm_state + offset + 8, dt->base);
+ stl_phys(env->as, sm_state + offset + 4, dt->limit);
+ stl_phys(env->as, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
}
- stl_phys(sm_state + 0x7f14, env->cr[4]);
+ stl_phys(env->as, sm_state + 0x7f14, env->cr[4]);
- stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
- stl_phys(sm_state + 0x7ef8, env->smbase);
+ stl_phys(env->as, sm_state + 0x7efc, SMM_REVISION_ID);
+ stl_phys(env->as, sm_state + 0x7ef8, env->smbase);
#endif
/* init SMM cpu state */
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4dd2056..4bedb3a 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -92,7 +92,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
sc->selector);
stq_phys(env->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
- stl_phys(addr + offsetof(struct vmcb_seg, limit),
+ stl_phys(env->as, addr + offsetof(struct vmcb_seg, limit),
sc->limit);
stw_phys(addr + offsetof(struct vmcb_seg, attrib),
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
@@ -142,12 +142,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* save the current CPU state in the hsave page */
stq_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
- stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
+ stl_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
stq_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
- stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
+ stl_phys(env->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
stq_phys(env->as,
@@ -591,11 +591,13 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->eip);
if (env->hflags & HF_INHIBIT_IRQ_MASK) {
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state),
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_state),
SVM_INTERRUPT_SHADOW_MASK);
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
} else {
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
}
/* Save the VM state in the vmcb */
@@ -610,12 +612,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
env->gdt.base);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
+ stl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
env->gdt.limit);
stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
env->idt.base);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
+ stl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
env->idt.limit);
stq_phys(env->as,
@@ -636,7 +638,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
int_ctl |= V_IRQ_MASK;
}
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.rflags),
cpu_compute_eflags(env));
@@ -720,13 +723,16 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
stq_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
exit_info_1);
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj)));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
ldl_phys(env->as, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj_err)));
- stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
+ stl_phys(env->as,
+ env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
env->hflags2 &= ~HF2_GIF_MASK;
/* FIXME: Resets the current ASID register to zero (host ASID). */
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index d102bff..ddaaff1 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -83,14 +83,14 @@ static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte0)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(env->htab_base + pte_offset, pte0);
+ stl_phys(env->as, env->htab_base + pte_offset, pte0);
}
static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
hwaddr pte_offset, target_ulong pte1)
{
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
+ stl_phys(env->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
}
typedef struct {
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 8e7f7b8..e4e74ae 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1017,7 +1017,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
break;
case 4:
default:
- stl_phys(addr, val);
+ stl_phys(env->as, addr, val);
break;
case 8:
stq_phys(env->as, addr, val);
@@ -1038,7 +1038,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
break;
case 4:
default:
- stl_phys((hwaddr)addr
+ stl_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 8:
@@ -1813,7 +1813,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
stw_phys(addr, val);
break;
case 4:
- stl_phys(addr, val);
+ stl_phys(env->as, addr, val);
break;
case 8:
default:
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 16/22] exec: Make stl_phys_notdirty input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (14 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 15/22] exec: Make stl_*_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 17/22] exec: Make stw_*_phys " edgar.iglesias
` (5 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 4 ++--
hw/arm/boot.c | 9 +++++----
hw/arm/highbank.c | 6 +++---
include/exec/cpu-common.h | 2 +-
target-i386/helper.c | 16 ++++++++--------
target-sparc/mmu_helper.c | 2 +-
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/exec.c b/exec.c
index 1dfdc3c..0b92ec1 100644
--- a/exec.c
+++ b/exec.c
@@ -2496,14 +2496,14 @@ uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(hwaddr addr, uint32_t val)
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegion *mr;
hwaddr l = 4;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
+ mr = address_space_translate(as, addr, &addr1, &l,
true);
if (l < 4 || !memory_access_is_direct(mr, true)) {
io_mem_write(mr, addr1, val, 4);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 55d552f..b04d386 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -16,6 +16,7 @@
#include "elf.h"
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#include "exec/address-spaces.h"
#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x00010000
@@ -88,13 +89,13 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
- stl_phys_notdirty(info->smp_bootreg_addr, 0);
+ stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
-#define WRITE_WORD(p, value) do { \
- stl_phys_notdirty(p, value); \
- p += 4; \
+#define WRITE_WORD(p, value) do { \
+ stl_phys_notdirty(&address_space_memory, p, value); \
+ p += 4; \
} while (0)
static void set_kernel_args(const struct arm_boot_info *info)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index fe98ef1..2e95967 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -68,11 +68,11 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
switch (info->nb_cpus) {
case 4:
- stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
case 3:
- stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
case 2:
- stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
+ stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
env->regs[15] = SMP_BOOT_ADDR;
break;
default:
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b29065d..dd5feab 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,7 +102,7 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
-void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 27461f1..114acb7 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -567,7 +567,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
}
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pml4e_addr, pml4e);
+ stl_phys_notdirty(env->as, pml4e_addr, pml4e);
}
ptep = pml4e ^ PG_NX_MASK;
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
@@ -584,7 +584,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pdpe_addr, pdpe);
+ stl_phys_notdirty(env->as, pdpe_addr, pdpe);
}
} else
#endif
@@ -654,7 +654,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(env->as, pde_addr, pde);
}
/* align to page_size */
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
@@ -663,7 +663,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
/* 4 KB page */
if (!(pde & PG_ACCESSED_MASK)) {
pde |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(env->as, pde_addr, pde);
}
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
env->a20_mask;
@@ -716,7 +716,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pte |= PG_ACCESSED_MASK;
if (is_dirty)
pte |= PG_DIRTY_MASK;
- stl_phys_notdirty(pte_addr, pte);
+ stl_phys_notdirty(env->as, pte_addr, pte);
}
page_size = 4096;
virt_addr = addr & ~0xfff;
@@ -771,7 +771,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(env->as, pde_addr, pde);
}
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
@@ -780,7 +780,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
} else {
if (!(pde & PG_ACCESSED_MASK)) {
pde |= PG_ACCESSED_MASK;
- stl_phys_notdirty(pde_addr, pde);
+ stl_phys_notdirty(env->as, pde_addr, pde);
}
/* page directory entry */
@@ -828,7 +828,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
pte |= PG_ACCESSED_MASK;
if (is_dirty)
pte |= PG_DIRTY_MASK;
- stl_phys_notdirty(pte_addr, pte);
+ stl_phys_notdirty(env->as, pte_addr, pte);
}
page_size = 4096;
virt_addr = addr & ~0xfff;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 8c5986e..d82410f 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -179,7 +179,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
if (is_dirty) {
pde |= PG_MODIFIED_MASK;
}
- stl_phys_notdirty(pde_ptr, pde);
+ stl_phys_notdirty(env->as, pde_ptr, pde);
}
/* the page can be put in the TLB */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 17/22] exec: Make stw_*_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (15 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 16/22] exec: Make stl_phys_notdirty " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 18/22] exec: Make stb_phys " edgar.iglesias
` (4 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 20 ++++++++++----------
hw/net/vmware_utils.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/spapr_hcall.c | 4 ++--
hw/s390x/css.c | 3 ++-
hw/s390x/s390-virtio-bus.c | 8 +++++---
hw/s390x/virtio-ccw.c | 3 ++-
hw/sh4/r2d.c | 2 +-
hw/virtio/virtio.c | 10 ++++++----
include/exec/cpu-common.h | 6 +++---
target-i386/smm_helper.c | 12 ++++++------
target-i386/svm_helper.c | 4 ++--
target-s390x/mem_helper.c | 2 +-
target-sparc/ldst_helper.c | 6 +++---
14 files changed, 45 insertions(+), 39 deletions(-)
diff --git a/exec.c b/exec.c
index 0b92ec1..cf35cd4 100644
--- a/exec.c
+++ b/exec.c
@@ -1612,7 +1612,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(&address_space_memory, addr, val);
break;
case 4:
stl_phys(&address_space_memory, addr, val);
@@ -2589,7 +2589,8 @@ void stb_phys(hwaddr addr, uint32_t val)
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(hwaddr addr, uint32_t val,
+static inline void stw_phys_internal(AddressSpace *as,
+ hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
@@ -2597,8 +2598,7 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
hwaddr l = 2;
hwaddr addr1;
- mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
- true);
+ mr = address_space_translate(as, addr, &addr1, &l, true);
if (l < 2 || !memory_access_is_direct(mr, true)) {
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
@@ -2629,19 +2629,19 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
}
}
-void stw_phys(hwaddr addr, uint32_t val)
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(hwaddr addr, uint32_t val)
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(hwaddr addr, uint32_t val)
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
- stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
+ stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index 2ed73af..d8f734f 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -89,7 +89,7 @@ static inline void
vmw_shmem_st16(hwaddr addr, uint16_t value)
{
VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
- stw_le_phys(addr, value);
+ stw_le_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 09a23ce..4d22048 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -64,7 +64,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
- stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+ stw_be_phys(env->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(env->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(env->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(env->as, bdloc + 0x34, bd->bi_baudrate);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 8f5a242..520ffd5 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -564,7 +564,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stb_phys(addr, val);
return H_SUCCESS;
case 2:
- stw_phys(addr, val);
+ stw_phys(cpu->env.as, addr, val);
return H_SUCCESS;
case 4:
stl_phys(cpu->env.as, addr, val);
@@ -627,7 +627,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stb_phys(dst, tmp);
break;
case 1:
- stw_phys(dst, tmp);
+ stw_phys(cpu->env.as, dst, tmp);
break;
case 2:
stl_phys(cpu->env.as, dst, tmp);
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index cfa8a9b..75b04b4 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
count = lduw_phys(&address_space_memory,
channel_subsys->chnmon_area + offset);
count++;
- stw_phys(channel_subsys->chnmon_area + offset, count);
+ stw_phys(&address_space_memory,
+ channel_subsys->chnmon_area + offset, count);
}
}
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index f8d51b3..f05ca70 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -77,10 +77,10 @@ void s390_virtio_reset_idx(VirtIOS390Device *dev)
for (i = 0; i < num_vq; i++) {
idx_addr = virtio_queue_get_avail_addr(dev->vdev, i) +
VIRTIO_VRING_AVAIL_IDX_OFFS;
- stw_phys(idx_addr, 0);
+ stw_phys(&address_space_memory, idx_addr, 0);
idx_addr = virtio_queue_get_used_addr(dev->vdev, i) +
VIRTIO_VRING_USED_IDX_OFFS;
- stw_phys(idx_addr, 0);
+ stw_phys(&address_space_memory, idx_addr, 0);
}
}
@@ -380,7 +380,9 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_queue_set_vector(dev->vdev, i, i);
stq_be_phys(&address_space_memory,
vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
- stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
+ stw_be_phys(&address_space_memory,
+ vq + VIRTIO_VQCONFIG_OFFS_NUM,
+ virtio_queue_get_num(dev->vdev, i));
}
cur_offs = dev->dev_offs;
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index c74d00b..1817c79 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -477,7 +477,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
vq_config.index = lduw_phys(&address_space_memory, ccw.cda);
vq_config.num_max = virtio_queue_get_num(vdev,
vq_config.index);
- stw_phys(ccw.cda + sizeof(vq_config.index), vq_config.num_max);
+ stw_phys(&address_space_memory,
+ ccw.cda + sizeof(vq_config.index), vq_config.num_max);
sch->curr_status.scsw.count = ccw.count - sizeof(vq_config);
ret = 0;
}
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 76ef869..eaeb7ed 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -319,7 +319,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
/* initialization which should be done by firmware */
stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
- stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
+ stw_phys(&address_space_memory, SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
}
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 3a00020..21072f0 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -180,21 +180,23 @@ static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
- stw_phys(pa, val);
+ stw_phys(&address_space_memory, pa, val);
}
static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(&address_space_memory, pa) | mask);
+ stw_phys(&address_space_memory,
+ pa, lduw_phys(&address_space_memory, pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
- stw_phys(pa, lduw_phys(&address_space_memory, pa) & ~mask);
+ stw_phys(&address_space_memory,
+ pa, lduw_phys(&address_space_memory, pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
@@ -204,7 +206,7 @@ static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
return;
}
pa = vq->vring.used + offsetof(VRingUsed, ring[vq->vring.num]);
- stw_phys(pa, val);
+ stw_phys(&address_space_memory, pa, val);
}
void virtio_queue_set_notification(VirtQueue *vq, int enable)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index dd5feab..a02cc3b 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -91,8 +91,8 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
void stb_phys(hwaddr addr, uint32_t val);
-void stw_le_phys(hwaddr addr, uint32_t val);
-void stw_be_phys(hwaddr addr, uint32_t val);
+void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
+void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
@@ -103,7 +103,7 @@ uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
-void stw_phys(hwaddr addr, uint32_t val);
+void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index d68aee7..2ffa26c 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -59,8 +59,8 @@ void do_smm_enter(X86CPU *cpu)
for (i = 0; i < 6; i++) {
dt = &env->segs[i];
offset = 0x7e00 + i * 16;
- stw_phys(sm_state + offset, dt->selector);
- stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
+ stw_phys(env->as, sm_state + offset, dt->selector);
+ stw_phys(env->as, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
stl_phys(env->as, sm_state + offset + 4, dt->limit);
stq_phys(env->as, sm_state + offset + 8, dt->base);
}
@@ -68,18 +68,18 @@ void do_smm_enter(X86CPU *cpu)
stq_phys(env->as, sm_state + 0x7e68, env->gdt.base);
stl_phys(env->as, sm_state + 0x7e64, env->gdt.limit);
- stw_phys(sm_state + 0x7e70, env->ldt.selector);
+ stw_phys(env->as, sm_state + 0x7e70, env->ldt.selector);
stq_phys(env->as, sm_state + 0x7e78, env->ldt.base);
stl_phys(env->as, sm_state + 0x7e74, env->ldt.limit);
- stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
+ stw_phys(env->as, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
stq_phys(env->as, sm_state + 0x7e88, env->idt.base);
stl_phys(env->as, sm_state + 0x7e84, env->idt.limit);
- stw_phys(sm_state + 0x7e90, env->tr.selector);
+ stw_phys(env->as, sm_state + 0x7e90, env->tr.selector);
stq_phys(env->as, sm_state + 0x7e98, env->tr.base);
stl_phys(env->as, sm_state + 0x7e94, env->tr.limit);
- stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
+ stw_phys(env->as, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
stq_phys(env->as, sm_state + 0x7ed0, env->efer);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4bedb3a..2475e4f 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -88,13 +88,13 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
const SegmentCache *sc)
{
- stw_phys(addr + offsetof(struct vmcb_seg, selector),
+ stw_phys(env->as, addr + offsetof(struct vmcb_seg, selector),
sc->selector);
stq_phys(env->as, addr + offsetof(struct vmcb_seg, base),
sc->base);
stl_phys(env->as, addr + offsetof(struct vmcb_seg, limit),
sc->limit);
- stw_phys(addr + offsetof(struct vmcb_seg, attrib),
+ stw_phys(env->as, addr + offsetof(struct vmcb_seg, attrib),
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index fb7650a..50cdba6 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1041,7 +1041,7 @@ void HELPER(ptlb)(CPUS390XState *env)
/* store using real address */
void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1)
{
- stw_phys(get_address(env, 0, 0, addr), (uint32_t)v1);
+ stw_phys(env->as, get_address(env, 0, 0, addr), (uint32_t)v1);
}
/* load real address */
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index e4e74ae..c814460 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1013,7 +1013,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(env->as, addr, val);
break;
case 4:
default:
@@ -1033,7 +1033,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 2:
- stw_phys((hwaddr)addr
+ stw_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 4:
@@ -1810,7 +1810,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
stb_phys(addr, val);
break;
case 2:
- stw_phys(addr, val);
+ stw_phys(env->as, addr, val);
break;
case 4:
stl_phys(env->as, addr, val);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 18/22] exec: Make stb_phys input an AddressSpace
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (16 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 17/22] exec: Make stw_*_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 19/22] exec: Make cpu_physical_memory_write_rom input an AS edgar.iglesias
` (3 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 6 +++---
hw/net/vmware_utils.h | 2 +-
hw/ppc/ppc405_uc.c | 10 +++++-----
hw/ppc/spapr_hcall.c | 6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++++++++++-----
hw/s390x/s390-virtio.c | 2 +-
hw/scsi/megasas.c | 6 ++++--
include/exec/cpu-common.h | 2 +-
target-i386/svm_helper.c | 2 +-
target-s390x/mem_helper.c | 2 +-
target-sparc/ldst_helper.c | 6 +++---
11 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/exec.c b/exec.c
index cf35cd4..f027091 100644
--- a/exec.c
+++ b/exec.c
@@ -1609,7 +1609,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(&address_space_memory, addr, val);
break;
case 2:
stw_phys(&address_space_memory, addr, val);
@@ -2582,10 +2582,10 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
}
/* XXX: optimize */
-void stb_phys(hwaddr addr, uint32_t val)
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
{
uint8_t v = val;
- cpu_physical_memory_write(addr, &v, 1);
+ address_space_rw(as, addr, &v, 1, 1);
}
/* warning: addr must be aligned */
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h
index d8f734f..1099df6 100644
--- a/hw/net/vmware_utils.h
+++ b/hw/net/vmware_utils.h
@@ -74,7 +74,7 @@ static inline void
vmw_shmem_st8(hwaddr addr, uint8_t value)
{
VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
- stb_phys(addr, value);
+ stb_phys(&address_space_memory, addr, value);
}
static inline uint32_t
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 4d22048..36a394b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -62,27 +62,27 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
stl_be_phys(env->as, bdloc + 0x1C, bd->bi_bootflags);
stl_be_phys(env->as, bdloc + 0x20, bd->bi_ipaddr);
for (i = 0; i < 6; i++) {
- stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+ stb_phys(env->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
}
stw_be_phys(env->as, bdloc + 0x2A, bd->bi_ethspeed);
stl_be_phys(env->as, bdloc + 0x2C, bd->bi_intfreq);
stl_be_phys(env->as, bdloc + 0x30, bd->bi_busfreq);
stl_be_phys(env->as, bdloc + 0x34, bd->bi_baudrate);
for (i = 0; i < 4; i++) {
- stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
+ stb_phys(env->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
}
for (i = 0; i < 32; i++) {
- stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+ stb_phys(env->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
stl_be_phys(env->as, bdloc + 0x5C, bd->bi_plb_busfreq);
stl_be_phys(env->as, bdloc + 0x60, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
- stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+ stb_phys(env->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
if (flags & 0x00000001) {
for (i = 0; i < 6; i++)
- stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
+ stb_phys(env->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(env->as, bdloc + n, bd->bi_opbfreq);
n += 4;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 520ffd5..5c0df80 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -369,7 +369,7 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
tmp = ldub_phys(env->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
tmp |= VPA_SHARED_PROC_VAL;
- stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
+ stb_phys(env->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
return H_SUCCESS;
}
@@ -561,7 +561,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(cpu->env.as, addr, val);
return H_SUCCESS;
case 2:
stw_phys(cpu->env.as, addr, val);
@@ -624,7 +624,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
}
switch (esize) {
case 0:
- stb_phys(dst, tmp);
+ stb_phys(cpu->env.as, dst, tmp);
break;
case 1:
stw_phys(cpu->env.as, dst, tmp);
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index f05ca70..170d851 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -359,15 +359,21 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
virtio_reset(dev->vdev);
/* Sync dev space */
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_TYPE, dev->vdev->device_id);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, s390_virtio_device_num_vq(dev));
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_FEATURE_LEN, dev->feat_len);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ,
+ s390_virtio_device_num_vq(dev));
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_FEATURE_LEN, dev->feat_len);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_CONFIG_LEN, dev->vdev->config_len);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_CONFIG_LEN, dev->vdev->config_len);
num_vq = s390_virtio_device_num_vq(dev);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, num_vq);
+ stb_phys(&address_space_memory,
+ dev->dev_offs + VIRTIO_DEV_OFFS_NUM_VQ, num_vq);
/* Sync virtqueues */
for (i = 0; i < num_vq; i++) {
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 7adf92a..9eeda97 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -91,7 +91,7 @@ static int s390_virtio_hcall_reset(const uint64_t *args)
return -EINVAL;
}
virtio_reset(dev->vdev);
- stb_phys(dev->dev_offs + VIRTIO_DEV_OFFS_STATUS, 0);
+ stb_phys(&address_space_memory, dev->dev_offs + VIRTIO_DEV_OFFS_STATUS, 0);
s390_virtio_device_sync(dev);
s390_virtio_reset_idx(dev);
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index e12f80c..59570e2 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -144,12 +144,14 @@ static bool megasas_is_jbod(MegasasState *s)
static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
{
- stb_phys(frame + offsetof(struct mfi_frame_header, cmd_status), v);
+ stb_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, cmd_status), v);
}
static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
{
- stb_phys(frame + offsetof(struct mfi_frame_header, scsi_status), v);
+ stb_phys(&address_space_memory,
+ frame + offsetof(struct mfi_frame_header, scsi_status), v);
}
/*
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index a02cc3b..20d3518 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -90,7 +90,7 @@ uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
-void stb_phys(hwaddr addr, uint32_t val);
+void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 2475e4f..bb9cd3d 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -653,7 +653,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
stq_phys(env->as,
env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
- stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
+ stb_phys(env->as, env->vm_vmcb + offsetof(struct vmcb, save.cpl),
env->hflags & HF_CPL_MASK);
/* Reload the host state from vm_hsave */
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 50cdba6..f147dec 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -984,7 +984,7 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
mvc_asc(env, l - i, a1 + i, mode1, a2 + i, mode2);
break;
}
- stb_phys(dest + i, ldub_phys(env->as, src + i));
+ stb_phys(env->as, dest + i, ldub_phys(env->as, src + i));
}
return cc;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index c814460..25f73b1 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1010,7 +1010,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
{
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(env->as, addr, val);
break;
case 2:
stw_phys(env->as, addr, val);
@@ -1029,7 +1029,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
{
switch (size) {
case 1:
- stb_phys((hwaddr)addr
+ stb_phys(env->as, (hwaddr)addr
| ((hwaddr)(asi & 0xf) << 32), val);
break;
case 2:
@@ -1807,7 +1807,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
{
switch (size) {
case 1:
- stb_phys(addr, val);
+ stb_phys(env->as, addr, val);
break;
case 2:
stw_phys(env->as, addr, val);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 19/22] exec: Make cpu_physical_memory_write_rom input an AS
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (17 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 18/22] exec: Make stb_phys " edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS edgar.iglesias
` (2 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 8 ++++----
hw/core/loader.c | 3 ++-
hw/intc/apic.c | 3 ++-
hw/sparc/sun4m.c | 3 ++-
include/exec/cpu-common.h | 2 +-
5 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/exec.c b/exec.c
index f027091..686f0d1 100644
--- a/exec.c
+++ b/exec.c
@@ -2093,7 +2093,7 @@ void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
hwaddr l;
@@ -2103,8 +2103,7 @@ void cpu_physical_memory_write_rom(hwaddr addr,
while (len > 0) {
l = len;
- mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+ mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2682,7 +2681,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
- cpu_physical_memory_write_rom(phys_addr, buf, l);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 60d2ebd..5598b30 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
- cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index a913186..b48b5ef 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
}
vapic_state.irr = vector & 0xff;
- cpu_physical_memory_write_rom(s->vapic_paddr + start,
+ cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..2957d90 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
- cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+ cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 20d3518..1710c51 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_rom;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (18 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 19/22] exec: Make cpu_physical_memory_write_rom input an AS edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 12:48 ` Andreas Färber
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new() edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU edgar.iglesias
21 siblings, 1 reply; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index 686f0d1..e672824 100644
--- a/exec.c
+++ b/exec.c
@@ -2669,6 +2669,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
int l;
hwaddr phys_addr;
target_ulong page;
+ CPUArchState *env = cpu->env_ptr;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -2681,10 +2682,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
- cpu_physical_memory_write_rom(&address_space_memory,
- phys_addr, buf, l);
+ cpu_physical_memory_write_rom(env->as, phys_addr, buf, l);
else
- cpu_physical_memory_rw(phys_addr, buf, l, is_write);
+ address_space_rw(env->as, phys_addr, buf, l, 0);
len -= l;
buf += l;
addr += l;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new()
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (19 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 12:14 ` Andreas Färber
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU edgar.iglesias
21 siblings, 1 reply; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
This is to allow future patches to set properties before cpu::realize().
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/microblaze/petalogix_ml605_mmu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 10970e0..4009ff5 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -76,7 +76,7 @@ static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
- const char *cpu_model = args->cpu_model;
+ Error *err = NULL;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
@@ -91,10 +91,13 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
- if (cpu_model == NULL) {
- cpu_model = "microblaze";
+ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+ if (err) {
+ error_report("%s", error_get_pretty(err));
+ exit(EXIT_FAILURE);
}
- cpu = cpu_mb_init(cpu_model);
+
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
` (20 preceding siblings ...)
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new() edgar.iglesias
@ 2013-12-16 8:06 ` edgar.iglesias
2013-12-16 12:46 ` Andreas Färber
21 siblings, 1 reply; 41+ messages in thread
From: edgar.iglesias @ 2013-12-16 8:06 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, afaerber,
aurelien, rth
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/microblaze/petalogix_ml605_mmu.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 4009ff5..0a13b0e 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
+ AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
qemu_irq irq[32], *cpu_irq;
+ /* Setup the CPU specific address-space. */
+ memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
+ address_space_init(as_cpu, mr_cpu_root, "as/cpu");
+
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err) {
error_report("%s", error_get_pretty(err));
@@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
env = &cpu->env;
+ /* Populate the CPU AS with the LMB only visible to the CPU. */
+ memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
+ address_space_mem, 0,
+ memory_region_size(address_space_mem));
+ memory_region_add_subregion(mr_cpu_root, 0x00000000, sysmem_alias);
+
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
- memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
+ memory_region_add_subregion_overlap(mr_cpu_root, 0x00000000,
+ phys_lmb_bram, 2);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space edgar.iglesias
@ 2013-12-16 12:11 ` Andreas Färber
2013-12-17 0:34 ` Edgar E. Iglesias
0 siblings, 1 reply; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 12:11 UTC (permalink / raw)
To: edgar.iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Am 16.12.2013 09:05, schrieb edgar.iglesias@gmail.com:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> cputlb.c | 4 ++--
> exec.c | 31 +++++++++++++++++++++++--------
> include/exec/cpu-defs.h | 3 +++
> include/exec/exec-all.h | 1 +
> include/exec/softmmu_template.h | 4 ++--
> include/qom/cpu.h | 2 ++
> 6 files changed, 33 insertions(+), 12 deletions(-)
[...]
> diff --git a/exec.c b/exec.c
> index 803bbde..edb6a43 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -136,6 +136,7 @@ typedef struct subpage_t {
>
> static void io_mem_init(void);
> static void memory_map_init(void);
> +static void tcg_commit(MemoryListener *listener);
>
> static MemoryRegion io_mem_watch;
> #endif
> @@ -434,6 +435,25 @@ CPUState *qemu_get_cpu(int index)
> return NULL;
> }
>
> +#if !defined(CONFIG_USER_ONLY)
> +void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
> +{
> + CPUArchState *env = cpu->env_ptr;
> +
> + if (tcg_enabled()) {
> + if (cpu->tcg_as_listener) {
> + memory_listener_unregister(cpu->tcg_as_listener);
> + } else {
> + cpu->tcg_as_listener = g_new0(MemoryListener, 1);
> + }
> + cpu->tcg_as_listener->commit = tcg_commit;
> + memory_listener_register(cpu->tcg_as_listener, as);
> + }
> +
> + env->as = as;
> +}
> +#endif
> +
> void cpu_exec_init(CPUArchState *env)
> {
> CPUState *cpu = ENV_GET_CPU(env);
> @@ -453,6 +473,7 @@ void cpu_exec_init(CPUArchState *env)
> QTAILQ_INIT(&env->breakpoints);
> QTAILQ_INIT(&env->watchpoints);
> #ifndef CONFIG_USER_ONLY
> + cpu_address_space_init(cpu, &address_space_memory);
> cpu->thread_id = qemu_get_thread_id();
> #endif
> QTAILQ_INSERT_TAIL(&cpus, cpu, node);
> @@ -482,9 +503,10 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> #else
> static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> {
> + CPUArchState *env = cpu->env_ptr;
> hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
> if (phys != -1) {
> - tb_invalidate_phys_addr(&address_space_memory,
> + tb_invalidate_phys_addr(env->as,
> phys | (pc & ~TARGET_PAGE_MASK));
> }
> }
[...]
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 01cd8c7..406b36c 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -176,6 +176,9 @@ typedef struct CPUWatchpoint {
> sigjmp_buf jmp_env; \
> int exception_index; \
> \
> + /* Per CPU address-space. */ \
> + AddressSpace *as; \
Why are you adding this field here rather than in CPUState alongside the
other field? This being a pointer I can't imagine problems for
non-softmmu, and I had posted patches a while ago to move the
surrounding fields there. Having it in CPUState would avoid some of the
env_ptr accesses above, which were supposed to be an interim solution only.
Regards,
Andreas
> + \
> /* user data */ \
> void *opaque; \
>
[...]
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 7739e00..c1febae 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -186,6 +186,8 @@ struct CPUState {
> uint32_t interrupt_request;
> int singlestep_enabled;
>
> + MemoryListener *tcg_as_listener;
> +
> void *env_ptr; /* CPUArchState */
> struct TranslationBlock *current_tb;
> struct GDBRegisterState *gdb_regs;
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new()
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new() edgar.iglesias
@ 2013-12-16 12:14 ` Andreas Färber
0 siblings, 0 replies; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 12:14 UTC (permalink / raw)
To: edgar.iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Am 16.12.2013 09:06, schrieb edgar.iglesias@gmail.com:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> This is to allow future patches to set properties before cpu::realize().
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
/-F
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU edgar.iglesias
@ 2013-12-16 12:46 ` Andreas Färber
2013-12-16 13:29 ` Peter Maydell
2013-12-17 1:36 ` Edgar E. Iglesias
0 siblings, 2 replies; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 12:46 UTC (permalink / raw)
To: edgar.iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Hi Edgar,
Am 16.12.2013 09:06, schrieb edgar.iglesias@gmail.com:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> hw/microblaze/petalogix_ml605_mmu.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> index 4009ff5..0a13b0e 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
> hwaddr ddr_base = MEMORY_BASEADDR;
> MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
> MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
> + MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
> + AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
> qemu_irq irq[32], *cpu_irq;
>
> + /* Setup the CPU specific address-space. */
> + memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
> + address_space_init(as_cpu, mr_cpu_root, "as/cpu");
> +
> /* init CPUs */
> cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
> + qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
> object_property_set_bool(OBJECT(cpu), true, "realized", &err);
> if (err) {
> error_report("%s", error_get_pretty(err));
> @@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
>
> env = &cpu->env;
>
> + /* Populate the CPU AS with the LMB only visible to the CPU. */
> + memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
> + address_space_mem, 0,
> + memory_region_size(address_space_mem));
> + memory_region_add_subregion(mr_cpu_root, 0x00000000, sysmem_alias);
> +
Thanks for this series. I've been on vacation so couldn't review the
previous RFC yet... I'm not entirely happy with the way this is pushing
work to the machines here and wonder if we can simplify that some more:
For one, I don't like the allocation of AddressSpace and MemoryRegion at
machine level. Would it be possible to enforce allocating a per-CPU
AddressSpace and MemoryRegion at cpu.c level, ideally as embedded value
rather than pointer field? Otherwise CPU hot-add is going to get rather
complicated and error-prone.
TCG loads/saves should always have a CPU[Arch]State associated. Would it
work to always alias the system MemoryRegion again at cpu.c level with
lowest priority for range [0,UINT64_MAX] and let derived CPUs do per-CPU
MemoryRegions by adding MemoryRegions with higher priority?
I guess QTest is going to be a culprit for this approach as you
mentioned in the cover letter?
That would limit machine changes to adding to the new CPU MemoryRegion
instead of the global system one where appropriate.
Always allocating AddressSpace/MemoryRegion per CPU would at the same
time avoid the need for these new qdev'y address space properties. If we
do need the user to fiddle with this, then I would prefer making address
spaces QOM objects and using a standard link<> property. An API to set
it conveniently from code would of course still be fine then.
Regards,
Andreas
> /* Attach emulated BRAM through the LMB. */
> memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
> LMB_BRAM_SIZE);
> vmstate_register_ram_global(phys_lmb_bram);
> - memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
> + memory_region_add_subregion_overlap(mr_cpu_root, 0x00000000,
> + phys_lmb_bram, 2);
>
> memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
> vmstate_register_ram_global(phys_ram);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS edgar.iglesias
@ 2013-12-16 12:48 ` Andreas Färber
2013-12-17 0:52 ` Edgar E. Iglesias
0 siblings, 1 reply; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 12:48 UTC (permalink / raw)
To: edgar.iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Am 16.12.2013 09:06, schrieb edgar.iglesias@gmail.com:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> exec.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index 686f0d1..e672824 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -2669,6 +2669,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
> int l;
> hwaddr phys_addr;
> target_ulong page;
> + CPUArchState *env = cpu->env_ptr;
>
> while (len > 0) {
> page = addr & TARGET_PAGE_MASK;
> @@ -2681,10 +2682,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
> l = len;
> phys_addr += (addr & ~TARGET_PAGE_MASK);
> if (is_write)
> - cpu_physical_memory_write_rom(&address_space_memory,
> - phys_addr, buf, l);
> + cpu_physical_memory_write_rom(env->as, phys_addr, buf, l);
> else
> - cpu_physical_memory_rw(phys_addr, buf, l, is_write);
> + address_space_rw(env->as, phys_addr, buf, l, 0);
Add braces for if and else while at it? :)
Andreas
> len -= l;
> buf += l;
> addr += l;
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs edgar.iglesias
@ 2013-12-16 12:54 ` Andreas Färber
2013-12-17 0:57 ` Edgar E. Iglesias
0 siblings, 1 reply; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 12:54 UTC (permalink / raw)
To: edgar.iglesias, qemu-devel
Cc: peter.maydell, blauwirbel, aliguori, pcrost, pbonzini, aurelien, rth
Am 16.12.2013 09:05, schrieb edgar.iglesias@gmail.com:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> exec.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/exec.c b/exec.c
> index edb6a43..203c8e4 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1810,6 +1810,11 @@ static void tcg_commit(MemoryListener *listener)
> reset the modified entries */
> /* XXX: slow ! */
> CPU_FOREACH(cpu) {
> + /* FIXME: Disentangle the cpu.h circular files deps so we can
> + directly get the right CPU from listener. */
Was this circular dependency explained somewhere?
> + if (cpu->tcg_as_listener != listener) {
> + continue;
> + }
If this is to be committed (rather than fixed in a v2), please move to
below variables as usual.
Regards,
Andreas
> CPUArchState *env = cpu->env_ptr;
>
> tlb_flush(env, 1);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 12:46 ` Andreas Färber
@ 2013-12-16 13:29 ` Peter Maydell
2013-12-16 13:44 ` Andreas Färber
` (2 more replies)
2013-12-17 1:36 ` Edgar E. Iglesias
1 sibling, 3 replies; 41+ messages in thread
From: Peter Maydell @ 2013-12-16 13:29 UTC (permalink / raw)
To: Andreas Färber
Cc: pcrost, QEMU Developers, Blue Swirl, Anthony Liguori,
Paolo Bonzini, Edgar E. Iglesias, Aurelien Jarno,
Richard Henderson
On 16 December 2013 12:46, Andreas Färber <afaerber@suse.de> wrote:
> Thanks for this series. I've been on vacation so couldn't review the
> previous RFC yet... I'm not entirely happy with the way this is pushing
> work to the machines here and wonder if we can simplify that some more:
>
> For one, I don't like the allocation of AddressSpace and MemoryRegion at
> machine level. Would it be possible to enforce allocating a per-CPU
> AddressSpace and MemoryRegion at cpu.c level, ideally as embedded value
> rather than pointer field? Otherwise CPU hot-add is going to get rather
> complicated and error-prone.
This seems like a good place to stick my oar in about how I
think this should work in the long term...
My view is that AddressSpace and/or MemoryRegion pointers
(links?) should be how we wire up the addressing on machine
models, in an analogous manner to the way we wire up IRQs.
So to take A9MPCore as an example:
* each individual ARMCPU has an AddressSpace * property
* the 'a9mpcore' device should create those ARMCPU objects,
and also the AddressSpaces to pass to them
* the AddressSpace for each core is different, because it
has the private peripherals for that CPU only (this
allows us to get rid of all the shim memory regions which
look up the CPU via current_cpu->cpu_index)
* each core's AddressSpace has as a 'background region'
the single AddressSpace which the board and/or SoC model
has passed to the a9mpcore device
* if there's a separate SoC device object from the board
model, then again the AddressSpace the SoC device passes
to a9mpcore is the result of the SoC mapping the various
SoC-internal devices into an AddressSpace it got passed
by the board
* if the SoC has a DMA engine of some kind then the DMA
engine should also be passed an appropriate AddressSpace
[and we thus automatically correctly model the way the
hardware DMA engine can't see the per-CPU peripherals]
You'll notice that this essentially gets rid of the "system
memory" idea...
I don't have a strong opinion about the exact details of who
is allocating what at what level, but I do think we need to
move towards an idea of handing the consumer of an address
space be passed an appropriate AS/MR which is constructed
by the same thing that creates that consumer.
I'm also not entirely clear on which points in this API
should be dealing with MemoryRegions and which with
AddressSpaces. Perhaps the CPU object should create its
AddressSpace internally and the thing it's passed as a
property should be a MemoryRegion * ?
> TCG loads/saves should always have a CPU[Arch]State associated. Would it
> work to always alias the system MemoryRegion again at cpu.c level with
> lowest priority for range [0,UINT64_MAX] and let derived CPUs do per-CPU
> MemoryRegions by adding MemoryRegions with higher priority?
I think that we should definitely not have individual CPUs
looking at the system memory region directly.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 13:29 ` Peter Maydell
@ 2013-12-16 13:44 ` Andreas Färber
2013-12-16 13:51 ` Peter Maydell
2013-12-16 14:03 ` Andreas Färber
2013-12-17 1:24 ` Edgar E. Iglesias
2 siblings, 1 reply; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 13:44 UTC (permalink / raw)
To: Peter Maydell
Cc: Eduardo Habkost, Igor Mammedov, pcrost, QEMU Developers,
Blue Swirl, Anthony Liguori, Paolo Bonzini, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
Am 16.12.2013 14:29, schrieb Peter Maydell:
> On 16 December 2013 12:46, Andreas Färber <afaerber@suse.de> wrote:
>> TCG loads/saves should always have a CPU[Arch]State associated. Would it
>> work to always alias the system MemoryRegion again at cpu.c level with
>> lowest priority for range [0,UINT64_MAX] and let derived CPUs do per-CPU
>> MemoryRegions by adding MemoryRegions with higher priority?
>
> I think that we should definitely not have individual CPUs
> looking at the system memory region directly.
Well, overall the whole MemoryRegion API is an abstraction, and the
system MemoryRegion is where SysBus maps its devices, so we can't get
rid of it tomorrow just yet. I had compatibility with today's code in
mind, Edgar apparently even more so, and I think we do need some
container for memory accessible to all CPUs to not force adding all
devices per CPU. The PC is still the most widely used machine in QEMU
and per-CPU devices would probably be APICs whereas I imagine "all the
rest" still in the big bucket whatever we name it.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 13:44 ` Andreas Färber
@ 2013-12-16 13:51 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2013-12-16 13:51 UTC (permalink / raw)
To: Andreas Färber
Cc: Eduardo Habkost, Igor Mammedov, pcrost, QEMU Developers,
Blue Swirl, Anthony Liguori, Paolo Bonzini, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
On 16 December 2013 13:44, Andreas Färber <afaerber@suse.de> wrote:
> Am 16.12.2013 14:29, schrieb Peter Maydell:
>> I think that we should definitely not have individual CPUs
>> looking at the system memory region directly.
>
> Well, overall the whole MemoryRegion API is an abstraction, and the
> system MemoryRegion is where SysBus maps its devices, so we can't get
> rid of it tomorrow just yet.
Certainly -- I just thought it might be worth outlining where
I hope we might end up someday, in the interests of not moving
in the opposite direction by accident.
Off the top of my head, a possible way to introduce per-CPU
AddressSpaces without requiring full reworking of every board:
add the AddressSpace* (or MemoryRegion?) property to the CPU
object, but if it is not set then make the realize function
default it to "create an AS from the system memory region".
Similarly you could just pass the a9mpcore object the system
memory region rather than creating one entirely from scratch.
That would let us mostly continue to use sysbus devices
as we do at the moment, and we could update those bits of
the system which we care about (new SoC models, for instance)
as required.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 13:29 ` Peter Maydell
2013-12-16 13:44 ` Andreas Färber
@ 2013-12-16 14:03 ` Andreas Färber
2013-12-16 15:09 ` Peter Maydell
2013-12-17 1:24 ` Edgar E. Iglesias
2 siblings, 1 reply; 41+ messages in thread
From: Andreas Färber @ 2013-12-16 14:03 UTC (permalink / raw)
To: Peter Maydell
Cc: Igor Mammedov, pcrost, QEMU Developers, Blue Swirl,
Anthony Liguori, Paolo Bonzini, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
Am 16.12.2013 14:29, schrieb Peter Maydell:
> On 16 December 2013 12:46, Andreas Färber <afaerber@suse.de> wrote:
>> Thanks for this series. I've been on vacation so couldn't review the
>> previous RFC yet... I'm not entirely happy with the way this is pushing
>> work to the machines here and wonder if we can simplify that some more:
>>
>> For one, I don't like the allocation of AddressSpace and MemoryRegion at
>> machine level. Would it be possible to enforce allocating a per-CPU
>> AddressSpace and MemoryRegion at cpu.c level, ideally as embedded value
>> rather than pointer field? Otherwise CPU hot-add is going to get rather
>> complicated and error-prone.
>
> This seems like a good place to stick my oar in about how I
> think this should work in the long term...
>
> My view is that AddressSpace and/or MemoryRegion pointers
> (links?) should be how we wire up the addressing on machine
> models, in an analogous manner to the way we wire up IRQs.
> So to take A9MPCore as an example:
>
> * each individual ARMCPU has an AddressSpace * property
> * the 'a9mpcore' device should create those ARMCPU objects,
> and also the AddressSpaces to pass to them
> * the AddressSpace for each core is different, because it
> has the private peripherals for that CPU only (this
> allows us to get rid of all the shim memory regions which
> look up the CPU via current_cpu->cpu_index)
> * each core's AddressSpace has as a 'background region'
> the single AddressSpace which the board and/or SoC model
> has passed to the a9mpcore device
> * if there's a separate SoC device object from the board
> model, then again the AddressSpace the SoC device passes
> to a9mpcore is the result of the SoC mapping the various
> SoC-internal devices into an AddressSpace it got passed
> by the board
> * if the SoC has a DMA engine of some kind then the DMA
> engine should also be passed an appropriate AddressSpace
> [and we thus automatically correctly model the way the
> hardware DMA engine can't see the per-CPU peripherals]
>
> You'll notice that this essentially gets rid of the "system
> memory" idea...
If you leave aside the per-CPU aspect, you could start preparing such
code today, just no one so far did. ;)
Seriously, SysBus maps to system memory region, but you can access the
to-be-mapped region via SysBus API and map it to some private, e.g.
per-SoC, manually and map that to system MR for the time being.
> I don't have a strong opinion about the exact details of who
> is allocating what at what level, but I do think we need to
> move towards an idea of handing the consumer of an address
> space be passed an appropriate AS/MR which is constructed
> by the same thing that creates that consumer.
While I concur with the possibility of a "cascaded" setup of container
MemoryRegions, let's not forget that apart from SoC/MPCore parent
realization one important thing that creates devices is device_add
(user), so we are in need of a mechanism that is generic enough to not
require per-board and per-bus implementations in order to keep today's
generic functionality working. Therefore my request for some more
self-containment while remaining accessible for advanced tweaking. For a
PCIDevice we can have the PHB take care of handling mapping the bars,
whereas the CPUState seems to grow a root memory space, so if not the
CPU, who becomes the owner of that root memory then wrt dynamic creation
or destruction? The ICC bus seems little suited to me and maintaining
15(?) implementations doesn't sound so thrilling to me. HTE.
> I'm also not entirely clear on which points in this API
> should be dealing with MemoryRegions and which with
> AddressSpaces. Perhaps the CPU object should create its
> AddressSpace internally and the thing it's passed as a
> property should be a MemoryRegion * ?
And yes, I'm not aware of the exact differences between AddressSpace and
MemoryRegion, so take my terminology with a grain of salt. :)
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 14:03 ` Andreas Färber
@ 2013-12-16 15:09 ` Peter Maydell
0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2013-12-16 15:09 UTC (permalink / raw)
To: Andreas Färber
Cc: Igor Mammedov, pcrost, QEMU Developers, Blue Swirl,
Anthony Liguori, Paolo Bonzini, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
On 16 December 2013 14:03, Andreas Färber <afaerber@suse.de> wrote:
> Am 16.12.2013 14:29, schrieb Peter Maydell:
> If you leave aside the per-CPU aspect, you could start preparing such
> code today, just no one so far did. ;)
> Seriously, SysBus maps to system memory region, but you can access the
> to-be-mapped region via SysBus API and map it to some private, e.g.
> per-SoC, manually and map that to system MR for the time being.
Yes, definitely. There's just been not much point to it
so far while CPUs all use a single address space.
>> I don't have a strong opinion about the exact details of who
>> is allocating what at what level, but I do think we need to
>> move towards an idea of handing the consumer of an address
>> space be passed an appropriate AS/MR which is constructed
>> by the same thing that creates that consumer.
>
> While I concur with the possibility of a "cascaded" setup of container
> MemoryRegions, let's not forget that apart from SoC/MPCore parent
> realization one important thing that creates devices is device_add
> (user), so we are in need of a mechanism that is generic enough to not
> require per-board and per-bus implementations in order to keep today's
> generic functionality working. Therefore my request for some more
> self-containment while remaining accessible for advanced tweaking. For a
> PCIDevice we can have the PHB take care of handling mapping the bars,
> whereas the CPUState seems to grow a root memory space, so if not the
> CPU, who becomes the owner of that root memory then wrt dynamic creation
> or destruction? The ICC bus seems little suited to me and maintaining
> 15(?) implementations doesn't sound so thrilling to me. HTE.
I would suggest that where we have hot pluggable CPUs this needs
to happen via some kind of bus that encapsulates all the
address regions and interrupt lines that the CPU has that
need connecting to the system. I'm not sure how it works
at the moment but presumably something has to wire the interrupts
up already...
Similarly I think device_add should generally be reserved for
genuinely pluggable interfaces, in which case the interface
should include whatever the MemoryRegion*/AddressSpace* wiring
is, in the same way that it has to include interrupt line wiring
for that sort of bus.
Wiring up a MemoryRegion* should ideally be no harder than
wiring up a qemu_irq; but in general I wouldn't expect command
line access to doing either at a raw low level.
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-16 12:11 ` Andreas Färber
@ 2013-12-17 0:34 ` Edgar E. Iglesias
2013-12-17 0:54 ` Peter Maydell
0 siblings, 1 reply; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 0:34 UTC (permalink / raw)
To: Andreas Färber
Cc: peter.maydell, qemu-devel, blauwirbel, aliguori, pcrost,
pbonzini, aurelien, rth
On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:05, schrieb edgar.iglesias@gmail.com:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > cputlb.c | 4 ++--
> > exec.c | 31 +++++++++++++++++++++++--------
> > include/exec/cpu-defs.h | 3 +++
> > include/exec/exec-all.h | 1 +
> > include/exec/softmmu_template.h | 4 ++--
> > include/qom/cpu.h | 2 ++
> > 6 files changed, 33 insertions(+), 12 deletions(-)
> [...]
> > diff --git a/exec.c b/exec.c
> > index 803bbde..edb6a43 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -136,6 +136,7 @@ typedef struct subpage_t {
> >
> > static void io_mem_init(void);
> > static void memory_map_init(void);
> > +static void tcg_commit(MemoryListener *listener);
> >
> > static MemoryRegion io_mem_watch;
> > #endif
> > @@ -434,6 +435,25 @@ CPUState *qemu_get_cpu(int index)
> > return NULL;
> > }
> >
> > +#if !defined(CONFIG_USER_ONLY)
> > +void cpu_address_space_init(CPUState *cpu, AddressSpace *as)
> > +{
> > + CPUArchState *env = cpu->env_ptr;
> > +
> > + if (tcg_enabled()) {
> > + if (cpu->tcg_as_listener) {
> > + memory_listener_unregister(cpu->tcg_as_listener);
> > + } else {
> > + cpu->tcg_as_listener = g_new0(MemoryListener, 1);
> > + }
> > + cpu->tcg_as_listener->commit = tcg_commit;
> > + memory_listener_register(cpu->tcg_as_listener, as);
> > + }
> > +
> > + env->as = as;
> > +}
> > +#endif
> > +
> > void cpu_exec_init(CPUArchState *env)
> > {
> > CPUState *cpu = ENV_GET_CPU(env);
> > @@ -453,6 +473,7 @@ void cpu_exec_init(CPUArchState *env)
> > QTAILQ_INIT(&env->breakpoints);
> > QTAILQ_INIT(&env->watchpoints);
> > #ifndef CONFIG_USER_ONLY
> > + cpu_address_space_init(cpu, &address_space_memory);
> > cpu->thread_id = qemu_get_thread_id();
> > #endif
> > QTAILQ_INSERT_TAIL(&cpus, cpu, node);
> > @@ -482,9 +503,10 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> > #else
> > static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> > {
> > + CPUArchState *env = cpu->env_ptr;
> > hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
> > if (phys != -1) {
> > - tb_invalidate_phys_addr(&address_space_memory,
> > + tb_invalidate_phys_addr(env->as,
> > phys | (pc & ~TARGET_PAGE_MASK));
> > }
> > }
> [...]
> > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> > index 01cd8c7..406b36c 100644
> > --- a/include/exec/cpu-defs.h
> > +++ b/include/exec/cpu-defs.h
> > @@ -176,6 +176,9 @@ typedef struct CPUWatchpoint {
> > sigjmp_buf jmp_env; \
> > int exception_index; \
> > \
> > + /* Per CPU address-space. */ \
> > + AddressSpace *as; \
>
> Why are you adding this field here rather than in CPUState alongside the
> other field? This being a pointer I can't imagine problems for
> non-softmmu, and I had posted patches a while ago to move the
> surrounding fields there. Having it in CPUState would avoid some of the
> env_ptr accesses above, which were supposed to be an interim solution only.
Hi,
This was discussed when I posted the RFC. My first try had this member in
CPUState but some of the hot paths for mmio accesses needed to do
ENV_GET_CPU() to get hold of the CS and AS. ENV_GET_CPU does a runtime type
check that would slow things down. That's the reason I moved it to env.
I'm not against moving the field back if it doesnt cost too much. Maybe we
should consider removing the CPU() around ENV_GET_CPU()?
See:
http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg02889.html
Cheers,
Edgar
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS
2013-12-16 12:48 ` Andreas Färber
@ 2013-12-17 0:52 ` Edgar E. Iglesias
0 siblings, 0 replies; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 0:52 UTC (permalink / raw)
To: Andreas Färber
Cc: peter.maydell, qemu-devel, blauwirbel, aliguori, pcrost,
pbonzini, aurelien, rth
On Mon, Dec 16, 2013 at 01:48:10PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:06, schrieb edgar.iglesias@gmail.com:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > exec.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/exec.c b/exec.c
> > index 686f0d1..e672824 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -2669,6 +2669,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
> > int l;
> > hwaddr phys_addr;
> > target_ulong page;
> > + CPUArchState *env = cpu->env_ptr;
> >
> > while (len > 0) {
> > page = addr & TARGET_PAGE_MASK;
> > @@ -2681,10 +2682,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
> > l = len;
> > phys_addr += (addr & ~TARGET_PAGE_MASK);
> > if (is_write)
> > - cpu_physical_memory_write_rom(&address_space_memory,
> > - phys_addr, buf, l);
> > + cpu_physical_memory_write_rom(env->as, phys_addr, buf, l);
> > else
> > - cpu_physical_memory_rw(phys_addr, buf, l, is_write);
> > + address_space_rw(env->as, phys_addr, buf, l, 0);
>
> Add braces for if and else while at it? :)
Fixed, thanks.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-17 0:34 ` Edgar E. Iglesias
@ 2013-12-17 0:54 ` Peter Maydell
2013-12-17 0:57 ` Peter Crosthwaite
2013-12-17 1:01 ` Edgar E. Iglesias
0 siblings, 2 replies; 41+ messages in thread
From: Peter Maydell @ 2013-12-17 0:54 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On 17 December 2013 00:34, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
>> Why are you adding this field here rather than in CPUState alongside the
>> other field? This being a pointer I can't imagine problems for
>> non-softmmu, and I had posted patches a while ago to move the
>> surrounding fields there. Having it in CPUState would avoid some of the
>> env_ptr accesses above, which were supposed to be an interim solution only.
> This was discussed when I posted the RFC. My first try had this member in
> CPUState but some of the hot paths for mmio accesses needed to do
> ENV_GET_CPU() to get hold of the CS and AS. ENV_GET_CPU does a runtime type
> check that would slow things down. That's the reason I moved it to env.
>
> I'm not against moving the field back if it doesnt cost too much. Maybe we
> should consider removing the CPU() around ENV_GET_CPU()?
>
> See:
> http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg02889.html
I think that's the wrong way round. We should put the field in the right
place in the code, which is CPUState. To the extent that that means we
discover that our dynamic cast macros are not fast enough for hot
paths we should make the actual error checking be debug builds
only. (There's been pushback on dynamic-casts in fastpaths before
and the preferred approach so far has been "optimise the cast".
I think we should take "...and do it only in debug builds" over "do
the wrong thing because a purely-debug-purposes type check
isn't as fast as we'd like".)
thanks
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs
2013-12-16 12:54 ` Andreas Färber
@ 2013-12-17 0:57 ` Edgar E. Iglesias
0 siblings, 0 replies; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 0:57 UTC (permalink / raw)
To: Andreas Färber
Cc: peter.maydell, qemu-devel, blauwirbel, aliguori, pcrost,
pbonzini, aurelien, rth
On Mon, Dec 16, 2013 at 01:54:11PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:05, schrieb edgar.iglesias@gmail.com:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > exec.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/exec.c b/exec.c
> > index edb6a43..203c8e4 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -1810,6 +1810,11 @@ static void tcg_commit(MemoryListener *listener)
> > reset the modified entries */
> > /* XXX: slow ! */
> > CPU_FOREACH(cpu) {
> > + /* FIXME: Disentangle the cpu.h circular files deps so we can
> > + directly get the right CPU from listener. */
>
> Was this circular dependency explained somewhere?
Not really, I dont remember the exact details of which files it involves
but basically MemoryListeners storage size is not known at the time
CPUState is declared. I've got a patch that fixes it but it involves
changing lots of files so I opted to leave it out if the first round
as this patch already is fairly intrusive...
Ill post that change later as a follow-up.
>
> > + if (cpu->tcg_as_listener != listener) {
> > + continue;
> > + }
>
> If this is to be committed (rather than fixed in a v2), please move to
> below variables as usual.
Fixed, thanks.
>
> Regards,
> Andreas
>
> > CPUArchState *env = cpu->env_ptr;
> >
> > tlb_flush(env, 1);
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-17 0:54 ` Peter Maydell
@ 2013-12-17 0:57 ` Peter Crosthwaite
2013-12-17 1:01 ` Edgar E. Iglesias
1 sibling, 0 replies; 41+ messages in thread
From: Peter Crosthwaite @ 2013-12-17 0:57 UTC (permalink / raw)
To: Peter Maydell
Cc: Peter Crosthwaite, QEMU Developers, Blue Swirl, Anthony Liguori,
Paolo Bonzini, Edgar E. Iglesias, Andreas Färber,
Aurelien Jarno, Richard Henderson
On Tue, Dec 17, 2013 at 10:54 AM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 17 December 2013 00:34, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
>> On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
>>> Why are you adding this field here rather than in CPUState alongside the
>>> other field? This being a pointer I can't imagine problems for
>>> non-softmmu, and I had posted patches a while ago to move the
>>> surrounding fields there. Having it in CPUState would avoid some of the
>>> env_ptr accesses above, which were supposed to be an interim solution only.
>
>> This was discussed when I posted the RFC. My first try had this member in
>> CPUState but some of the hot paths for mmio accesses needed to do
>> ENV_GET_CPU() to get hold of the CS and AS. ENV_GET_CPU does a runtime type
>> check that would slow things down. That's the reason I moved it to env.
>>
>> I'm not against moving the field back if it doesnt cost too much. Maybe we
>> should consider removing the CPU() around ENV_GET_CPU()?
>>
>> See:
>> http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg02889.html
>
> I think that's the wrong way round. We should put the field in the right
> place in the code, which is CPUState. To the extent that that means we
> discover that our dynamic cast macros are not fast enough for hot
> paths we should make the actual error checking be debug builds
> only. (There's been pushback on dynamic-casts in fastpaths before
> and the preferred approach so far has been "optimise the cast".
> I think we should take "...and do it only in debug builds" over "do
> the wrong thing because a purely-debug-purposes type check
> isn't as fast as we'd like".)
>
A levelled approach to debugging can help here too rather than having
all-or-none with the QoM casts.
Regards,
Peter
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space
2013-12-17 0:54 ` Peter Maydell
2013-12-17 0:57 ` Peter Crosthwaite
@ 2013-12-17 1:01 ` Edgar E. Iglesias
1 sibling, 0 replies; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 1:01 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On Tue, Dec 17, 2013 at 12:54:19AM +0000, Peter Maydell wrote:
> On 17 December 2013 00:34, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
> >> Why are you adding this field here rather than in CPUState alongside the
> >> other field? This being a pointer I can't imagine problems for
> >> non-softmmu, and I had posted patches a while ago to move the
> >> surrounding fields there. Having it in CPUState would avoid some of the
> >> env_ptr accesses above, which were supposed to be an interim solution only.
>
> > This was discussed when I posted the RFC. My first try had this member in
> > CPUState but some of the hot paths for mmio accesses needed to do
> > ENV_GET_CPU() to get hold of the CS and AS. ENV_GET_CPU does a runtime type
> > check that would slow things down. That's the reason I moved it to env.
> >
> > I'm not against moving the field back if it doesnt cost too much. Maybe we
> > should consider removing the CPU() around ENV_GET_CPU()?
> >
> > See:
> > http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg02889.html
>
> I think that's the wrong way round. We should put the field in the right
> place in the code, which is CPUState. To the extent that that means we
> discover that our dynamic cast macros are not fast enough for hot
> paths we should make the actual error checking be debug builds
> only. (There's been pushback on dynamic-casts in fastpaths before
> and the preferred approach so far has been "optimise the cast".
> I think we should take "...and do it only in debug builds" over "do
> the wrong thing because a purely-debug-purposes type check
> isn't as fast as we'd like".)
Sounds reasonable to me, I'll move the AS back into CPUState for v2.
Thanks,
Edgar
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 13:29 ` Peter Maydell
2013-12-16 13:44 ` Andreas Färber
2013-12-16 14:03 ` Andreas Färber
@ 2013-12-17 1:24 ` Edgar E. Iglesias
2 siblings, 0 replies; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 1:24 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Blue Swirl, Anthony Liguori, pcrost,
Paolo Bonzini, Andreas Färber, Aurelien Jarno,
Richard Henderson
On Mon, Dec 16, 2013 at 01:29:47PM +0000, Peter Maydell wrote:
> On 16 December 2013 12:46, Andreas Färber <afaerber@suse.de> wrote:
> > Thanks for this series. I've been on vacation so couldn't review the
> > previous RFC yet... I'm not entirely happy with the way this is pushing
> > work to the machines here and wonder if we can simplify that some more:
> >
> > For one, I don't like the allocation of AddressSpace and MemoryRegion at
> > machine level. Would it be possible to enforce allocating a per-CPU
> > AddressSpace and MemoryRegion at cpu.c level, ideally as embedded value
> > rather than pointer field? Otherwise CPU hot-add is going to get rather
> > complicated and error-prone.
>
> This seems like a good place to stick my oar in about how I
> think this should work in the long term...
>
> My view is that AddressSpace and/or MemoryRegion pointers
> (links?) should be how we wire up the addressing on machine
> models, in an analogous manner to the way we wire up IRQs.
> So to take A9MPCore as an example:
>
> * each individual ARMCPU has an AddressSpace * property
> * the 'a9mpcore' device should create those ARMCPU objects,
> and also the AddressSpaces to pass to them
> * the AddressSpace for each core is different, because it
> has the private peripherals for that CPU only (this
> allows us to get rid of all the shim memory regions which
> look up the CPU via current_cpu->cpu_index)
> * each core's AddressSpace has as a 'background region'
> the single AddressSpace which the board and/or SoC model
> has passed to the a9mpcore device
> * if there's a separate SoC device object from the board
> model, then again the AddressSpace the SoC device passes
> to a9mpcore is the result of the SoC mapping the various
> SoC-internal devices into an AddressSpace it got passed
> by the board
> * if the SoC has a DMA engine of some kind then the DMA
> engine should also be passed an appropriate AddressSpace
> [and we thus automatically correctly model the way the
> hardware DMA engine can't see the per-CPU peripherals]
>
> You'll notice that this essentially gets rid of the "system
> memory" idea...
>
> I don't have a strong opinion about the exact details of who
> is allocating what at what level, but I do think we need to
> move towards an idea of handing the consumer of an address
> space be passed an appropriate AS/MR which is constructed
> by the same thing that creates that consumer.
AFAICT, this pretty much matches what I'm looking for.
>
> I'm also not entirely clear on which points in this API
> should be dealing with MemoryRegions and which with
> AddressSpaces. Perhaps the CPU object should create its
> AddressSpace internally and the thing it's passed as a
> property should be a MemoryRegion * ?
Maybe yes, It would maybe simplify the API a bit, but Im not sure.
AddressSpaces are not very lightweight, so for systems that can have many
masters which can share AS, it might help to pass/reuse AS refs and
avoid creating the full-blown AS structures for every master port.
> > TCG loads/saves should always have a CPU[Arch]State associated. Would it
> > work to always alias the system MemoryRegion again at cpu.c level with
> > lowest priority for range [0,UINT64_MAX] and let derived CPUs do per-CPU
> > MemoryRegions by adding MemoryRegions with higher priority?
>
> I think that we should definitely not have individual CPUs
> looking at the system memory region directly.
Agreed. This series doesnt reach that far (there is still lots of
address_space_memory usage) because its a big effort to transform
everything. Im taking an incremental path.
Cheers,
Edgar
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU
2013-12-16 12:46 ` Andreas Färber
2013-12-16 13:29 ` Peter Maydell
@ 2013-12-17 1:36 ` Edgar E. Iglesias
1 sibling, 0 replies; 41+ messages in thread
From: Edgar E. Iglesias @ 2013-12-17 1:36 UTC (permalink / raw)
To: Andreas Färber
Cc: peter.maydell, qemu-devel, blauwirbel, aliguori, pcrost,
pbonzini, aurelien, rth
On Mon, Dec 16, 2013 at 01:46:57PM +0100, Andreas Färber wrote:
> Hi Edgar,
>
> Am 16.12.2013 09:06, schrieb edgar.iglesias@gmail.com:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > hw/microblaze/petalogix_ml605_mmu.c | 17 ++++++++++++++++-
> > 1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
> > index 4009ff5..0a13b0e 100644
> > --- a/hw/microblaze/petalogix_ml605_mmu.c
> > +++ b/hw/microblaze/petalogix_ml605_mmu.c
> > @@ -88,10 +88,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
> > hwaddr ddr_base = MEMORY_BASEADDR;
> > MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
> > MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
> > + MemoryRegion *sysmem_alias = g_new(MemoryRegion, 1);
> > + MemoryRegion *mr_cpu_root = g_new(MemoryRegion, 1);
> > + AddressSpace *as_cpu = g_malloc0(sizeof(*as_cpu));
> > qemu_irq irq[32], *cpu_irq;
> >
> > + /* Setup the CPU specific address-space. */
> > + memory_region_init(mr_cpu_root, NULL, "as-cpu-root", INT64_MAX);
> > + address_space_init(as_cpu, mr_cpu_root, "as/cpu");
> > +
> > /* init CPUs */
> > cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
> > + qdev_prop_set_address_space(DEVICE(cpu), "address-space", as_cpu);
> > object_property_set_bool(OBJECT(cpu), true, "realized", &err);
> > if (err) {
> > error_report("%s", error_get_pretty(err));
> > @@ -100,11 +108,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
> >
> > env = &cpu->env;
> >
> > + /* Populate the CPU AS with the LMB only visible to the CPU. */
> > + memory_region_init_alias(sysmem_alias, NULL, "sysmem_alias",
> > + address_space_mem, 0,
> > + memory_region_size(address_space_mem));
> > + memory_region_add_subregion(mr_cpu_root, 0x00000000, sysmem_alias);
> > +
>
>
> Thanks for this series. I've been on vacation so couldn't review the
> previous RFC yet... I'm not entirely happy with the way this is pushing
> work to the machines here and wonder if we can simplify that some more:
>
> For one, I don't like the allocation of AddressSpace and MemoryRegion at
> machine level. Would it be possible to enforce allocating a per-CPU
> AddressSpace and MemoryRegion at cpu.c level, ideally as embedded value
> rather than pointer field? Otherwise CPU hot-add is going to get rather
> complicated and error-prone.
It depends how you see it. The CPU is the user of an AS, but not necessarily
the owner/creator of the AS/port. I think the AS should be created and owned
by the container/board that creates the CPU. PMM elaborates more on this
in his reply.
> TCG loads/saves should always have a CPU[Arch]State associated. Would it
> work to always alias the system MemoryRegion again at cpu.c level with
> lowest priority for range [0,UINT64_MAX] and let derived CPUs do per-CPU
> MemoryRegions by adding MemoryRegions with higher priority?
> I guess QTest is going to be a culprit for this approach as you
> mentioned in the cover letter?
> That would limit machine changes to adding to the new CPU MemoryRegion
> instead of the global system one where appropriate.
>
> Always allocating AddressSpace/MemoryRegion per CPU would at the same
> time avoid the need for these new qdev'y address space properties. If we
> do need the user to fiddle with this, then I would prefer making address
> spaces QOM objects and using a standard link<> property. An API to set
> it conveniently from code would of course still be fine then.
The reason why qdev props are nice for the CPU is that it makes the
interface to set the AS the same for all masters (DMA, CPUs etc).
For DMA capable devs, the device could even have multiple AS it operates
on which can be set by names. A CPU could in theory also need multiple AS,
but currently we have structural limitations that only allow support for one.
Cheers,
Edgar
>
> Regards,
> Andreas
>
> > /* Attach emulated BRAM through the LMB. */
> > memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
> > LMB_BRAM_SIZE);
> > vmstate_register_ram_global(phys_lmb_bram);
> > - memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
> > + memory_region_add_subregion_overlap(mr_cpu_root, 0x00000000,
> > + phys_lmb_bram, 2);
> >
> > memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
> > vmstate_register_ram_global(phys_ram);
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2013-12-17 1:36 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-16 8:05 [Qemu-devel] [PATCH v1 00/22] Steps towards per CPU address-spaces edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 01/22] exec: Make tb_invalidate_phys_addr input an AS edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 02/22] exec: Make iotlb_to_region " edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 03/22] exec: Always initialize MemorySection address spaces edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 04/22] exec: Make memory_region_section_get_iotlb use section AS edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 05/22] memory: Add MemoryListener to typedefs.h edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 06/22] memory: Add address_space_find_by_name() edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 07/22] qdev: Add qdev property type for AddressSpaces edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 08/22] cpu: Add per-cpu address space edgar.iglesias
2013-12-16 12:11 ` Andreas Färber
2013-12-17 0:34 ` Edgar E. Iglesias
2013-12-17 0:54 ` Peter Maydell
2013-12-17 0:57 ` Peter Crosthwaite
2013-12-17 1:01 ` Edgar E. Iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 09/22] target-microblaze: Add address-space property edgar.iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 10/22] exec: On AS changes, only flush affected CPU TLBs edgar.iglesias
2013-12-16 12:54 ` Andreas Färber
2013-12-17 0:57 ` Edgar E. Iglesias
2013-12-16 8:05 ` [Qemu-devel] [PATCH v1 11/22] exec: Make ldl_*_phys input an AddressSpace edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 12/22] exec: Make ldq/ldub_*_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 13/22] exec: Make lduw_*_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 14/22] exec: Make stq_*_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 15/22] exec: Make stl_*_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 16/22] exec: Make stl_phys_notdirty " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 17/22] exec: Make stw_*_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 18/22] exec: Make stb_phys " edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 19/22] exec: Make cpu_physical_memory_write_rom input an AS edgar.iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 20/22] exec: Make cpu_memory_rw_debug use the CPUs AS edgar.iglesias
2013-12-16 12:48 ` Andreas Färber
2013-12-17 0:52 ` Edgar E. Iglesias
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 21/22] petalogix-ml605: Create the CPU with object_new() edgar.iglesias
2013-12-16 12:14 ` Andreas Färber
2013-12-16 8:06 ` [Qemu-devel] [PATCH v1 22/22] petalogix-ml605: Make the LMB visible only to the CPU edgar.iglesias
2013-12-16 12:46 ` Andreas Färber
2013-12-16 13:29 ` Peter Maydell
2013-12-16 13:44 ` Andreas Färber
2013-12-16 13:51 ` Peter Maydell
2013-12-16 14:03 ` Andreas Färber
2013-12-16 15:09 ` Peter Maydell
2013-12-17 1:24 ` Edgar E. Iglesias
2013-12-17 1:36 ` Edgar E. Iglesias
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