[PATCH V1 0/7] Fix imx6 fec interrupts

[PATCH V1 0/7] Fix imx6 fec interrupts

[Troy Kisky]

This patch series works around a hardware
wake up on FEC interrupt bug.


Note: The last 2 patches need testing from
someone who has the boards.

Troy Kisky (7):
  ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ
  ARM: dts: imx6qdl: add pingroups for enet with GPIO6 interrupt
  ARM: dts: imx6qdl-sabrelite: use MX6QDL_ENET_PINGRP_RGMII_MD
  ARM: dts: imx6qdl: use interrupts-extended for fec
  ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.
  ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.
  ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.

 arch/arm/boot/dts/imx6dl-pinfunc.h        |  1 +
 arch/arm/boot/dts/imx6q-arm2.dts          |  4 +-
 arch/arm/boot/dts/imx6q-pinfunc.h         |  1 +
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 19 ++------
 arch/arm/boot/dts/imx6qdl-pingrp.h        | 77 +++++++++++++------------------
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi  |  4 +-
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi  | 19 ++------
 arch/arm/boot/dts/imx6qdl.dtsi            |  5 +-
 8 files changed, 52 insertions(+), 78 deletions(-)

-- 
1.8.1.2

[PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

[Troy Kisky]

Quoting from Ranjani Vaidyanathan

All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.

Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
workaround this problem.

The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
The mux reg value is 0x11, so that the observable mux is routed to
this pin and to the gpio controller(sion bit).

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: ra5478 at freescale.com
---
 arch/arm/boot/dts/imx6dl-pinfunc.h | 1 +
 arch/arm/boot/dts/imx6q-pinfunc.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index 7499eee..0ead323 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -755,6 +755,7 @@
 #define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x234 0x604 0x03c 0x11 0xff000609
 #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
 #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index e5834b2..9fc6120 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -673,6 +673,7 @@
 #define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
 #define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x230 0x600 0x03c 0x11 0xff000609
 #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
 #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
-- 
1.8.1.2

[PATCH V1 2/7] ARM: dts: imx6qdl: add pingroups for enet with GPIO6 interrupt

[Troy Kisky]

Most boards will want this hardware work-around so
add new pingroups.

Also, add MX6QDL_ENET_PINGRP_RGMII macro so that other
pingroups can use this.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 arch/arm/boot/dts/imx6qdl-pingrp.h | 77 ++++++++++++++++----------------------
 1 file changed, 33 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-pingrp.h b/arch/arm/boot/dts/imx6qdl-pingrp.h
index c9dd44c..082f0df 100644
--- a/arch/arm/boot/dts/imx6qdl-pingrp.h
+++ b/arch/arm/boot/dts/imx6qdl-pingrp.h
@@ -53,57 +53,37 @@
 	MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI		0x100b1 \
 	MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK		0x100b1
 
+#define MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
+	MX6QDL_PAD_RGMII_RXC__RGMII_RXC			rx_pad \
+	MX6QDL_PAD_RGMII_RD0__RGMII_RD0			rx_pad \
+	MX6QDL_PAD_RGMII_RD1__RGMII_RD1			rx_pad \
+	MX6QDL_PAD_RGMII_RD2__RGMII_RD2			rx_pad \
+	MX6QDL_PAD_RGMII_RD3__RGMII_RD3			rx_pad \
+	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		rx_pad \
+	MX6QDL_PAD_RGMII_TXC__RGMII_TXC			tx_pad \
+	MX6QDL_PAD_RGMII_TD0__RGMII_TD0			tx_pad \
+	MX6QDL_PAD_RGMII_TD1__RGMII_TD1			tx_pad \
+	MX6QDL_PAD_RGMII_TD2__RGMII_TD2			tx_pad \
+	MX6QDL_PAD_RGMII_TD3__RGMII_TD3			tx_pad \
+	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		tx_pad \
+	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		tx_pad
+
+#define MX6QDL_ENET_PINGRP_RGMII_MD(rx_pad, tx_pad)	\
+	MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad)	\
+	MX6QDL_PAD_ENET_MDIO__ENET_MDIO			tx_pad \
+	MX6QDL_PAD_ENET_MDC__ENET_MDC			tx_pad
+
 #define MX6QDL_ENET_PINGRP1 \
-	MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x1b0b0 \
-	MX6QDL_PAD_ENET_MDC__ENET_MDC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x1b0b0 \
-	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x1b0b0 \
-	MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b0b0 \
+	MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0)	\
 	MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x4001b0a8
 
 #define MX6QDL_ENET_PINGRP2 \
+	MX6QDL_ENET_PINGRP_RGMII(0x1b0b0, 0x1b0b0)		\
 	MX6QDL_PAD_KEY_COL1__ENET_MDIO			0x1b0b0 \
-	MX6QDL_PAD_KEY_COL2__ENET_MDC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x1b0b0 \
-	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x1b0b0 \
-	MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b0b0
+	MX6QDL_PAD_KEY_COL2__ENET_MDC			0x1b0b0
 
 #define MX6QDL_ENET_PINGRP3 \
-	MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x1b0b0 \
-	MX6QDL_PAD_ENET_MDC__ENET_MDC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x1b0b0 \
-	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x1b0b0 \
-	MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b0b0 \
-	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b0b0 \
+	MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0)	\
 	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x1b0b0
 
 #define MX6QDL_ENET_PINGRP4 \
@@ -117,6 +97,15 @@
 	MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x1b0b0	\
 	MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x1b0b0
 
+#define MX6QDL_ENET_PINGRP1_GPIO6	MX6QDL_ENET_PINGRP1 \
+	MX6QDL_PAD_GPIO_6__ENET_IRQ	0x000b1
+
+#define MX6QDL_ENET_PINGRP2_GPIO6	MX6QDL_ENET_PINGRP2 \
+	MX6QDL_PAD_GPIO_6__ENET_IRQ	0x000b1
+
+#define MX6QDL_ENET_PINGRP3_GPIO6	MX6QDL_ENET_PINGRP3 \
+	MX6QDL_PAD_GPIO_6__ENET_IRQ	0x000b1
+
 #define MX6QDL_ESAI_PINGRP1 \
 	MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK		0x1b030 \
 	MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK		0x1b030 \
-- 
1.8.1.2

[PATCH V1 3/7] ARM: dts: imx6qdl-sabrelite: use MX6QDL_ENET_PINGRP_RGMII_MD

[Troy Kisky]

This saves some lines, but should not be a functional change.
Also, apply same change to imx6qdl-nitrogen6x.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 16 +---------------
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi  | 16 +---------------
 2 files changed, 2 insertions(+), 30 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 78fe8b0..ef5ce885 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -207,21 +207,7 @@
 
 		pinctrl_enet: enetgrp {
 			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+				MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
 				/* Phy reset */
 				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x000b0
 			>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index d28f501..db06e40 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -206,21 +206,7 @@
 
 		pinctrl_enet: enetgrp {
 			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+				MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
 				/* Phy reset */
 				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x000b0
 			>;
-- 
1.8.1.2

[PATCH V1 4/7] ARM: dts: imx6qdl: use interrupts-extended for fec

[Troy Kisky]

We need to be able to override interrupts in board file to
workaround a hardware bug for ethernet interrupts
waking the processor by using interrupts-extended.
So, use interrupts-extended here as well.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 858ecd7..584dbe9a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -737,8 +737,9 @@
 			fec: ethernet at 02188000 {
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
-				interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
-					     <0 119 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts-extended =
+					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
+					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 				clock-names = "ipg", "ahb", "ptp";
 				status = "disabled";
-- 
1.8.1.2

[PATCH V1 5/7] ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.

[Troy Kisky]

This works around a hardware bug.
Quoting from Ranjani Vaidyanathan:

All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.

Before this patch, ping times of a Sabre Lite board are quite
random:
ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=15.7 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=14.4 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=13.4 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=12.4 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=11.4 ms

--- 192.168.0.13 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 2004ms
rtt min/avg/max/mdev = 11.431/13.501/15.746/1.508 ms
____________________________________________________
After this patch:

ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=0.120 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=0.175 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=0.169 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=0.168 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=0.172 ms

--- 192.168.0.13 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 1999ms
rtt min/avg/max/mdev = 0.120/0.160/0.175/0.026 ms
____________________________________________________

Also, apply same change to imx6qdl-nitrogen6x.

This change may not be appropriate for all boards.
Sabre Lite uses GPIO6 as a power down output for a ov5642
camera. As this expansion board does not yet work with mainline,
this is not yet a conflict. It would be nice to have an alternative
fix for boards where this is a problem.

For example Sabre SD uses GPIO6 for I2C3_SDA. It also
has long ping times currently. But cannot use this fix
without giving up a touchscreen.

Its ping times are also random.

ping 192.168.0.19 -i.5 -c5
PING 192.168.0.19 (192.168.0.19) 56(84) bytes of data.
64 bytes from 192.168.0.19: icmp_req=1 ttl=64 time=16.0 ms
64 bytes from 192.168.0.19: icmp_req=2 ttl=64 time=15.4 ms
64 bytes from 192.168.0.19: icmp_req=3 ttl=64 time=14.4 ms
64 bytes from 192.168.0.19: icmp_req=4 ttl=64 time=13.4 ms
64 bytes from 192.168.0.19: icmp_req=5 ttl=64 time=12.4 ms

--- 192.168.0.19 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 2003ms
rtt min/avg/max/mdev = 12.451/14.369/16.057/1.316 ms

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: ra5478 at freescale.com
---
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 3 +++
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi  | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index ef5ce885..9909c36 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -164,6 +164,8 @@
 	txd1-skew-ps = <0>;
 	txd2-skew-ps = <0>;
 	txd3-skew-ps = <0>;
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
 };
 
@@ -210,6 +212,7 @@
 				MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
 				/* Phy reset */
 				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x000b0
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 			>;
 		};
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index db06e40..8b620b5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -163,6 +163,8 @@
 	txd1-skew-ps = <0>;
 	txd2-skew-ps = <0>;
 	txd3-skew-ps = <0>;
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
 };
 
@@ -209,6 +211,7 @@
 				MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
 				/* Phy reset */
 				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x000b0
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 			>;
 		};
 
-- 
1.8.1.2

[PATCH V1 6/7] ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.

[Troy Kisky]

This works around a hardware bug.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

---
This has not been tested.
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 26fa0e5..088b0d2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -44,6 +44,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
 };
 
@@ -77,7 +79,7 @@
 		};
 
 		pinctrl_enet: enetgrp {
-			fsl,pins = <MX6QDL_ENET_PINGRP2>;
+			fsl,pins = <MX6QDL_ENET_PINGRP2_GPIO6>;
 		};
 
 		pinctrl_gpmi_nand: gpminandgrp {
-- 
1.8.1.2

[PATCH V1 7/7] ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.

[Troy Kisky]

This works around a hardware bug.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

---
This has not been tested
---
 arch/arm/boot/dts/imx6q-arm2.dts | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 9c00b73..631a426 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -75,7 +75,7 @@
 		};
 
 		pinctrl_enet: enetgrp {
-			fsl,pins = <MX6QDL_ENET_PINGRP2>;
+			fsl,pins = <MX6QDL_ENET_PINGRP2_GPIO6>;
 		};
 
 		pinctrl_gpmi_nand: gpminandgrp {
@@ -115,6 +115,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
+	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
 };
 
-- 
1.8.1.2

[PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

[Shawn Guo]

On Wed, Dec 18, 2013 at 03:41:31PM -0700, Troy Kisky wrote:
> Quoting from Ranjani Vaidyanathan
> 
> All of the interrupts from the ENET block are not routed to
> the GPC block. Hence ENET interrupts are not able to wake
> up the SOC when the system is in WAIT mode. And the ENET
> interrupt gets serviced only when another interrupt causes
> the SOC to exit WAIT mode. This impacts the ENET performance.

We should probably also quote the IMX6Q errata document below.

 http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fpsp=1

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.

> 
> Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
> workaround this problem.
> 
> The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.

It seems this is an undocumented register?  Is the info available
somewhere?

> The mux reg value is 0x11, so that the observable mux is routed to
> this pin and to the gpio controller(sion bit).
> 
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> CC: ra5478 at freescale.com

When having people in the tag, please put their name in there as well,
so Ranjani Vaidyanathan <ra5478@freescale.com> please.

Shawn

> ---
>  arch/arm/boot/dts/imx6dl-pinfunc.h | 1 +
>  arch/arm/boot/dts/imx6q-pinfunc.h  | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
> index 7499eee..0ead323 100644
> --- a/arch/arm/boot/dts/imx6dl-pinfunc.h
> +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
> @@ -755,6 +755,7 @@
>  #define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
>  #define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
>  #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
> +#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x234 0x604 0x03c 0x11 0xff000609
>  #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
>  #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
>  #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
> diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
> index e5834b2..9fc6120 100644
> --- a/arch/arm/boot/dts/imx6q-pinfunc.h
> +++ b/arch/arm/boot/dts/imx6q-pinfunc.h
> @@ -673,6 +673,7 @@
>  #define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
>  #define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
>  #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
> +#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x230 0x600 0x03c 0x11 0xff000609
>  #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
>  #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
>  #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
> -- 
> 1.8.1.2
> 

[PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

[Troy Kisky]

On 12/18/2013 10:04 PM, Shawn Guo wrote:
> On Wed, Dec 18, 2013 at 03:41:31PM -0700, Troy Kisky wrote:
>> Quoting from Ranjani Vaidyanathan
>>
>> All of the interrupts from the ENET block are not routed to
>> the GPC block. Hence ENET interrupts are not able to wake
>> up the SOC when the system is in WAIT mode. And the ENET
>> interrupt gets serviced only when another interrupt causes
>> the SOC to exit WAIT mode. This impacts the ENET performance.
> We should probably also quote the IMX6Q errata document below.
>
>   http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fpsp=1
>
> ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
> system from Wait mode.

Thanks for the link, I didn't know about rev 3. But since they say 
pretty much the same
things, should I only quote the manual ?

>> Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
>> workaround this problem.
>>
>> The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
> It seems this is an undocumented register?  Is the info available
> somewhere?

I'm the wrong person to ask. The only reference I've seen are patches.
Mode 1 for GPIO_6 isn't documented either.

>
>> The mux reg value is 0x11, so that the observable mux is routed to
>> this pin and to the gpio controller(sion bit).
>>
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> CC: ra5478 at freescale.com
> When having people in the tag, please put their name in there as well,
> so Ranjani Vaidyanathan <ra5478@freescale.com> please.
>
> Shawn
>
Will do,

Thanks
Troy

[PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

[Shawn Guo]

On Thu, Dec 19, 2013 at 11:52:41AM -0700, Troy Kisky wrote:
> On 12/18/2013 10:04 PM, Shawn Guo wrote:
> >On Wed, Dec 18, 2013 at 03:41:31PM -0700, Troy Kisky wrote:
> >>Quoting from Ranjani Vaidyanathan
> >>
> >>All of the interrupts from the ENET block are not routed to
> >>the GPC block. Hence ENET interrupts are not able to wake
> >>up the SOC when the system is in WAIT mode. And the ENET
> >>interrupt gets serviced only when another interrupt causes
> >>the SOC to exit WAIT mode. This impacts the ENET performance.
> >We should probably also quote the IMX6Q errata document below.
> >
> >  http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fpsp=1
> >
> >ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
> >system from Wait mode.
> 
> Thanks for the link, I didn't know about rev 3. But since they say
> pretty much the same
> things, should I only quote the manual ?

Sounds good.

> 
> >>Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
> >>workaround this problem.
> >>
> >>The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
> >It seems this is an undocumented register?  Is the info available
> >somewhere?
> 
> I'm the wrong person to ask. The only reference I've seen are patches.
> Mode 1 for GPIO_6 isn't documented either.

Ok.  Just make sure I do not miss any public document.

Shawn

[PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

[Ranjani.Vaidyanathan at freescale.com]

Hi Shawn,

Unfortunately the obsrv_mux registers are currently not documented in the RM, it was part of the original MX6Q userguide. We would need to request the doc team to put the info in.

Thanks,
Ranjani

-----Original Message-----
From: Shawn Guo [mailto:shawn.guo at linaro.org] 
Sent: Wednesday, December 18, 2013 11:05 PM
To: Troy Kisky
Cc: festevam at gmail.com; eric.nelson at boundarydevices.com; marex at denx.de; linux-arm-kernel at lists.infradead.org; Vaidyanathan Ranjani-RA5478
Subject: Re: [PATCH V1 1/7] ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ

On Wed, Dec 18, 2013 at 03:41:31PM -0700, Troy Kisky wrote:
> Quoting from Ranjani Vaidyanathan
> 
> All of the interrupts from the ENET block are not routed to the GPC 
> block. Hence ENET interrupts are not able to wake up the SOC when the 
> system is in WAIT mode. And the ENET interrupt gets serviced only when 
> another interrupt causes the SOC to exit WAIT mode. This impacts the 
> ENET performance.

We should probably also quote the IMX6Q errata document below.

 http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fpsp=1

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode.

> 
> Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to workaround this 
> problem.
> 
> The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.

It seems this is an undocumented register?  Is the info available somewhere?

> The mux reg value is 0x11, so that the observable mux is routed to 
> this pin and to the gpio controller(sion bit).
> 
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> CC: ra5478 at freescale.com

When having people in the tag, please put their name in there as well, so Ranjani Vaidyanathan <ra5478@freescale.com> please.

Shawn

> ---
>  arch/arm/boot/dts/imx6dl-pinfunc.h | 1 +  
> arch/arm/boot/dts/imx6q-pinfunc.h  | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h 
> b/arch/arm/boot/dts/imx6dl-pinfunc.h
> index 7499eee..0ead323 100644
> --- a/arch/arm/boot/dts/imx6dl-pinfunc.h
> +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
> @@ -755,6 +755,7 @@
>  #define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
>  #define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
>  #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
> +#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x234 0x604 0x03c 0x11 0xff000609
>  #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
>  #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
>  #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
> diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h 
> b/arch/arm/boot/dts/imx6q-pinfunc.h
> index e5834b2..9fc6120 100644
> --- a/arch/arm/boot/dts/imx6q-pinfunc.h
> +++ b/arch/arm/boot/dts/imx6q-pinfunc.h
> @@ -673,6 +673,7 @@
>  #define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
>  #define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
>  #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
> +#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x230 0x600 0x03c 0x11 0xff000609
>  #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
>  #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
>  #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
> --
> 1.8.1.2
>