[U-Boot] [PATCH v2 1/6] mx6: soc: Staticize set_vddsoc()

[U-Boot] [PATCH v2 1/6] mx6: soc: Staticize set_vddsoc()

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c              | 2 +-
 arch/arm/include/asm/arch-mx6/sys_proto.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a390296..6cbade7 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -101,7 +101,7 @@ void init_aips(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-void set_vddsoc(u32 mv)
+static void set_vddsoc(u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 val, reg = readl(&anatop->reg_core);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 8c21364..17125a6 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -29,8 +29,6 @@ u32 get_cpu_rev(void);
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 
-void set_vddsoc(u32 mv);
-
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
-- 
1.8.1.2

[U-Boot] [PATCH v2 2/6] mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 6cbade7..13b9e36 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -93,6 +93,20 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr4);
 }
 
+static void clear_ldo_ramp(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	/* ROM may modify LDO ramp up time according to fuse setting, so in
+	 * order to be in the safe side we neeed to reset these settings to
+	 * match the reset value: 0'b00
+	 */
+	reg = readl(&anatop->ana_misc2);
+	reg &= ~(0x3f << 24);
+	writel(reg, &anatop->ana_misc2);
+}
+
 /*
  * Set the VDDSOC
  *
@@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv)
 	else
 		val = (mv - 700) / 25;
 
+	clear_ldo_ramp();
+
 	/*
 	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 	 * and set them to the calculated value (0.7V + val * 0.25V)
-- 
1.8.1.2

[U-Boot] [PATCH v2 3/6] mx6: soc: Set the VDDSOC at 1.175 V

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 13b9e36..0136eb0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -151,7 +151,7 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
+	set_vddsoc(1175);	/* Set VDDSOC to 1.175V */
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
-- 
1.8.1.2

[U-Boot] [PATCH v2 4/6] mx6: soc: Introduce set_ldo_voltage()

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0136eb0..ee888ce 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -19,6 +19,12 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+enum ldo_reg {
+	LDO_ARM,
+	LDO_SOC,
+	LDO_PU,
+};
+
 struct scu_regs {
 	u32	ctrl;
 	u32	config;
@@ -115,10 +121,11 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static void set_vddsoc(u32 mv)
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 val, reg = readl(&anatop->reg_core);
+	u8 shift;
 
 	if (mv < 725)
 		val = 0x00;	/* Power gated off */
@@ -129,12 +136,24 @@ static void set_vddsoc(u32 mv)
 
 	clear_ldo_ramp();
 
-	/*
-	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
-	 * and set them to the calculated value (0.7V + val * 0.25V)
-	 */
-	reg = (reg & ~(0x1F << 18)) | (val << 18);
+	switch (ldo) {
+	case LDO_SOC:
+		shift = 18;
+		break;
+	case LDO_PU:
+		shift = 9;
+		break;
+	case LDO_ARM:
+		shift = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	reg = (reg & ~(0x1F << shift)) | (val << shift);
 	writel(reg, &anatop->reg_core);
+
+	return 0;
 }
 
 static void imx_set_wdog_powerdown(bool enable)
@@ -151,7 +170,7 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_vddsoc(1175);	/* Set VDDSOC to 1.175V */
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
-- 
1.8.1.2

[U-Boot] [PATCH v2 5/6] mx6: soc: Add the required LDO ramp up delay

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- None

 arch/arm/cpu/armv7/mx6/soc.c | 22 +++++++++++++++++++---
 include/configs/mx6_common.h |  1 +
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ee888ce..3aa3bb0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -124,7 +124,7 @@ static void clear_ldo_ramp(void)
 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 val, reg = readl(&anatop->reg_core);
+	u32 val, step, old, reg = readl(&anatop->reg_core);
 	u8 shift;
 
 	if (mv < 725)
@@ -150,9 +150,20 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 		return -EINVAL;
 	}
 
+	old = (reg & (0x1F << shift)) >> shift;
+	step = abs(val - old);
+	if (step == 0)
+		return 0;
+
 	reg = (reg & ~(0x1F << shift)) | (val << shift);
 	writel(reg, &anatop->reg_core);
 
+	/*
+	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+	 * step
+	 */
+	udelay(3 * step);
+
 	return 0;
 }
 
@@ -170,8 +181,6 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
-
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA
@@ -182,6 +191,13 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+int board_postclk_init(void)
+{
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 674bcd3..514d634 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -20,5 +20,6 @@
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_BOARD_POSTCLK_INIT
 
 #endif
-- 
1.8.1.2

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Disable vddpu the same way as in kernel

 arch/arm/cpu/armv7/mx6/soc.c             | 41 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/crm_regs.h |  1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h | 23 ++++++++++++++++++
 3 files changed, 65 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..b944edd 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -19,6 +19,8 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+#define VDDPU_MASK	(0x1f << 9)
+
 enum ldo_reg {
 	LDO_ARM,
 	LDO_SOC,
@@ -177,11 +179,50 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void imx_set_vddpu_power_down(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
+
+	u32 reg;
+
+	/*
+	 * Disable the brown out detection since we are going to be
+	 * disabling the LDO.
+	 */
+	reg = readl(&anatop->ana_misc2);
+	reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
+	writel(reg, &anatop->ana_misc2);
+
+	/* need to power down xPU in GPC before turning off PU LDO */
+	reg = readl(&gpc->gpu_ctrl);
+	writel(reg | 0x1, &gpc->gpu_ctrl);
+
+	reg = readl(&gpc->ctrl);
+	writel(reg | 0x1, &gpc->ctrl);
+	while (readl(&gpc->ctrl) & 0x1)
+		;
+
+	/* Mask the ANATOP brown out interrupt in the GPC. */
+	reg = readl(&gpc->imr4);
+	reg |= 0x80000000;
+	writel(reg, &gpc->imr4);
+
+	/* disable VDDPU */
+	writel(VDDPU_MASK, &anatop->reg_core_clr);
+
+	/* Clear the BO interrupt in the ANATOP. */
+	reg = readl(&anatop->ana_misc1);
+	reg |= 0x80000000;
+	writel(reg, &anatop->ana_misc1);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+	imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 7202073..aede126 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -890,4 +890,5 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
 	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define ANADIG_ANA_MISC2_REG1_BO_EN	(1 << 13)
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7ef7152..fb0c4c7 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -659,5 +659,28 @@ struct wdog_regs {
 	u16	wmcr;	/* Miscellaneous Control */
 };
 
+struct gpc_regs {
+	u32	ctrl;		/* 0x000 */
+	u32	pgr;		/* 0x004 */
+	u32	imr1;		/* 0x008 */
+	u32	imr2;		/* 0x00c */
+	u32	imr3;		/* 0x010 */
+	u32	imr4;		/* 0x014 */
+	u32	isr1;		/* 0x018 */
+	u32	isr2;		/* 0x01c */
+	u32	isr3;		/* 0x020 */
+	u32	isr4;		/* 0x024 */
+	u32	reserved1[0x86];
+	u32	gpu_ctrl;	/* 0x260 */
+	u32	gpu_pupscr;	/* 0x264 */
+	u32	gpu_pdnscr;	/* 0x268 */
+	u32	gpu_sr;		/* 0x26c */
+	u32	reserved2[0xc];
+	u32	cpu_ctrl;	/* 0x2a0 */
+	u32	cpu_pupscr;	/* 0x2a4 */
+	u32	cpu_pdnscr;	/* 0x2a8 */
+	u32	cpu_sr;		/* 0x2ac */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
-- 
1.8.1.2

[U-Boot] [PATCH v2 2/6] mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages

[Stefano Babic]

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Since ROM may modify the LDO ramp up time according to fuse setting,
> it is safer to reset the ramp up field to its default value of 00:
> 
> 00: 64 cycles of 24MHz clock;
> 01: 128 cycles of 24MHz clock;
> 02: 256 cycles of 24MHz clock;
> 03: 512 cycles of 24MHz clock;
> 
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Jason Liu <r64343@freescale.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - None
> 
>  arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 6cbade7..13b9e36 100644

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 3/6] mx6: soc: Set the VDDSOC at 1.175 V

[Stefano Babic]

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
> Add a 25 mV margin and set it to 1.175V.
> 
> This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
> http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 4/6] mx6: soc: Introduce set_ldo_voltage()

[Stefano Babic]

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 5/6] mx6: soc: Add the required LDO ramp up delay

[Stefano Babic]

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> When changing LDO voltages we need to wait for the required amount of time
> for the voltage to settle.
> 
> Also, as the timer is still not available when arch_cpu_init() is called, we
> need to call it later at board_postclk_init() phase.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Stefano Babic]

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
> in order to save power.
> 
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Jason Liu <r64343@freescale.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 1/6] mx6: soc: Staticize set_vddsoc()

[Stefano Babic]

Hi Fabio,

On 26/12/2013 17:51, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> set_vddsoc() is not used anywhere else, so make it static.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Otavio Salvador]

Hello,

On Thu, Dec 26, 2013 at 2:51 PM, Fabio Estevam <festevam@gmail.com> wrote:

> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
> in order to save power.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Jason Liu <r64343@freescale.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>

It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
reverting this makes this to work again. It freezes when loading Vivante
module.

Can someone reproduce this freeze?

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

On Thu, Jan 9, 2014 at 3:50 PM, Otavio Salvador <otavio@ossystems.com.br> wrote:

> It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
> reverting this makes this to work again. It freezes when loading Vivante
> module.

VDDPU is needed for using the GPU, so the kernel should turn on the
VDDPU regulator.

Looks like you are getting a kernel bug.

Regards,

Fabio Estevam

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Otavio Salvador]

On Thu, Jan 9, 2014 at 5:06 PM, Fabio Estevam <festevam@gmail.com> wrote:

> On Thu, Jan 9, 2014 at 3:50 PM, Otavio Salvador <otavio@ossystems.com.br>
> wrote:
>
> > It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
> > reverting this makes this to work again. It freezes when loading Vivante
> > module.
>
> VDDPU is needed for using the GPU, so the kernel should turn on the
> VDDPU regulator.
>
> Looks like you are getting a kernel bug.
>

It might be but shouldn't we delay this patch for now?

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

On Thu, Jan 9, 2014 at 5:11 PM, Otavio Salvador <otavio@ossystems.com.br> wrote:

> It might be but shouldn't we delay this patch for now?

I don't think so.

Please post your dts file. Most likely you are using

pu-supply = <&pu_dummy>;

where you should be using the internal vddpu instead.

Also, please post your kernel log and make sure vddpu is being turned on.

Regards,

Fabio Estevam

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

On Thu, Jan 9, 2014 at 5:13 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Jan 9, 2014 at 5:11 PM, Otavio Salvador <otavio@ossystems.com.br> wrote:
>
>> It might be but shouldn't we delay this patch for now?
>
> I don't think so.
>
> Please post your dts file. Most likely you are using
>
> pu-supply = <&pu_dummy>;
>
> where you should be using the internal vddpu instead.
>
> Also, please post your kernel log and make sure vddpu is being turned on.

Please try this on your dts file:
pu-supply = <&reg_pu>;

Regards,

Fabio Estevam

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Otavio Salvador]

On Thu, Jan 9, 2014 at 5:30 PM, Fabio Estevam <festevam@gmail.com> wrote:

> On Thu, Jan 9, 2014 at 5:13 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Thu, Jan 9, 2014 at 5:11 PM, Otavio Salvador <otavio@ossystems.com.br>
> wrote:
> >
> >> It might be but shouldn't we delay this patch for now?
> >
> > I don't think so.
> >
> > Please post your dts file. Most likely you are using
> >
> > pu-supply = <&pu_dummy>;
> >
> > where you should be using the internal vddpu instead.
> >
> > Also, please post your kernel log and make sure vddpu is being turned on.
>
> Please try this on your dts file:
> pu-supply = <&reg_pu>;
>

Mine dts has:


&gpu {
pu-supply = <&reg_pu>;
};

The bootlog is at:

http://privatepaste.com/download/104a504b26

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

On Thu, Jan 9, 2014 at 5:39 PM, Otavio Salvador <otavio@ossystems.com.br> wrote:

> Mine dts has:
>
>
> &gpu {
> pu-supply = <&reg_pu>;
> };
>
> The bootlog is at:
>
> http://privatepaste.com/download/104a504b26

According to your log:

vdd1p1: 800 <--> 1375 mV at 1125 mV
vdd3p0: 2800 <--> 3150 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2425 mV
cpu: 725 <--> 1450 mV at 1100 mV
vddpu: 725 <--> 1450 mV

cpu regulator is at 1.1V, which is below the spec for 800MHz, so this
is an issue.

vddpu is still turned off.

Hard to tell where the problem is without looking at your dts file.

Anyway, we are getting off topic on the U-boot list now :-)

Regards,

Fabio Estevam

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Stefano Babic]

Hi Otavio,

On 09/01/2014 20:11, Otavio Salvador wrote:
>
>
>
> On Thu, Jan 9, 2014 at 5:06 PM, Fabio Estevam <festevam@gmail.com
> <mailto:festevam@gmail.com>> wrote:
>
>     On Thu, Jan 9, 2014 at 3:50 PM, Otavio Salvador
>     <otavio at ossystems.com.br <mailto:otavio@ossystems.com.br>> wrote:
>
>      > It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer
>     board;
>      > reverting this makes this to work again. It freezes when loading
>     Vivante
>      > module.
>
>     VDDPU is needed for using the GPU, so the kernel should turn on the
>     VDDPU regulator.
>
>     Looks like you are getting a kernel bug.
>
>
> It might be but shouldn't we delay this patch for now?

Now or later it does not change. The correct behavior is done with the 
patch, and the kernel must turn power on. If it does not, the patch is 
needed for the kernel, not here.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Otavio Salvador]

Hello,

On Thu, Jan 9, 2014 at 7:31 PM, Stefano Babic <sbabic@denx.de> wrote:
>
> On 09/01/2014 20:11, Otavio Salvador wrote:
>
>> On Thu, Jan 9, 2014 at 5:06 PM, Fabio Estevam <festevam@gmail.com
>> <mailto:festevam@gmail.com>> wrote:
>>
>>     On Thu, Jan 9, 2014 at 3:50 PM, Otavio Salvador
>>     <otavio at ossystems.com.br <mailto:otavio@ossystems.com.br>> wrote:
>>
>>      > It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer
>>     board;
>>      > reverting this makes this to work again. It freezes when loading
>>     Vivante
>>      > module.
>>
>>     VDDPU is needed for using the GPU, so the kernel should turn on the
>>     VDDPU regulator.
>>
>>     Looks like you are getting a kernel bug.
>>
>> It might be but shouldn't we delay this patch for now?
>>
>
> Now or later it does not change. The correct behavior is done with the
> patch, and the kernel must turn power on. If it does not, the patch is
> needed for the kernel, not here.


I've been debugging to make 3.10 to work with this patch, but without
success...

I think this patch should be reverted and be added back to 2014.04 release
so we have more time to debug this.

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Stefano Babic]

Hi Otavio, hi Fabio,

On 15/01/2014 18:12, Otavio Salvador wrote:

> 
> I've been debugging to make 3.10 to work with this patch, but without
> success...
> 
> I think this patch should be reverted and be added back to 2014.04
> release so we have more time to debug this. 
> 

Generally, I disagree to fix an issue in U-Boot when it is clear that
this should be fixed in another component (in our case, the FSL-3.10
kernel). A patch should be revert if it is buggy - but this patch does
the work and generally U-Boot should not activate what it does not need.

I understand Otavio's reasons to avoid that users by taking the official
releases for U-Boot and FSL-3.10 will get a not working system. But
anyway, IMHO the fix should flow into FSL-3.10 and not here.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Pierre Aubert]

=Hello,


Otavio Salvador wrote
> 
> It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
> reverting this makes this to work again. It freezes when loading Vivante
> module.
> 
> Can someone reproduce this freeze?

The kernel 3.0.35 freezes also on the SabreSD platform with this commit. 

Best regards




--
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[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Fabio Estevam]

Hi Pierre,

On Thu, Jan 16, 2014 at 6:40 AM, Pierre Aubert <p.aubert@staubli.com> wrote:
> =Hello,
>
>
> Otavio Salvador wrote
>>
>> It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
>> reverting this makes this to work again. It freezes when loading Vivante
>> module.
>>
>> Can someone reproduce this freeze?
>
> The kernel 3.0.35 freezes also on the SabreSD platform with this commit.

What is the output of "md.l 0x20C8140 1' on your board?

What is the mx6 variant (solo, dl, q) and silicon version?

Regards,

Fabio Estevam

[U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator

[Pierre AUBERT]

Hi Fabio,


Le 16/01/2014 12:19, Fabio Estevam a ?crit :
> Hi Pierre,
>
> On Thu, Jan 16, 2014 at 6:40 AM, Pierre Aubert <p.aubert@staubli.com> wrote:
>> =Hello,
>>
>>
>> Otavio Salvador wrote
>>> It seems this patch makes 3.10.17-1.0.0-beta freeze in a customer board;
>>> reverting this makes this to work again. It freezes when loading Vivante
>>> module.
>>>
>>> Can someone reproduce this freeze?
>> The kernel 3.0.35 freezes also on the SabreSD platform with this commit.
> What is the output of "md.l 0x20C8140 1' on your board?
=> md.l 0x20C8140 1
020c8140: 004c0010
>
> What is the mx6 variant (solo, dl, q) and silicon version?
I'm using a SabreSDP with a iMX6DL :

U-Boot 2014.01-rc3-00077-g751be3b (Jan 16 2014 - 08:27:51)

CPU:   Freescale i.MX6DL rev1.1 at 792 MHz
Reset cause: POR
Board: MX6-SabreSD
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

>
> Regards,
>
> Fabio Estevam
Best regards