From: Paul Mackerras <paulus@samba.org> To: Alexander Graf <agraf@suse.de> Cc: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org Subject: [PATCH 06/18] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8 Date: Wed, 8 Jan 2014 21:25:24 +1100 [thread overview] Message-ID: <1389176736-26821-7-git-send-email-paulus@samba.org> (raw) In-Reply-To: <1389176736-26821-1-git-send-email-paulus@samba.org> This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7) compatibility modes on a POWER8 processor. (Note that transactional memory is disabled for usermode if either or both of the PCR_TM_DIS and PCR_ARCH_206 bits are set.) Signed-off-by: Paul Mackerras <paulus@samba.org> --- arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/kvm/book3s_hv.c | 16 +++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 2f41e64..5a99831 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -329,6 +329,8 @@ #define SPRN_PCR 0x152 /* Processor compatibility register */ #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ +#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ +#define PCR_ARCH_206 0x4 /* Architecture 2.06 */ #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index b89701a..e804ede 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -182,14 +182,28 @@ int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat) switch (arch_compat) { case PVR_ARCH_205: - pcr = PCR_ARCH_205; + /* + * If an arch bit is set in PCR, all the defined + * higher-order arch bits also have to be set. + */ + pcr = PCR_ARCH_206 | PCR_ARCH_205; break; case PVR_ARCH_206: case PVR_ARCH_206p: + pcr = PCR_ARCH_206; + break; + case PVR_ARCH_207: break; default: return -EINVAL; } + + if (!cpu_has_feature(CPU_FTR_ARCH_207S)) { + /* POWER7 can't emulate POWER8 */ + if (!(pcr & PCR_ARCH_206)) + return -EINVAL; + pcr &= ~PCR_ARCH_206; + } } spin_lock(&vc->lock); -- 1.8.5.2
WARNING: multiple messages have this Message-ID (diff)
From: Paul Mackerras <paulus@samba.org> To: Alexander Graf <agraf@suse.de> Cc: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org Subject: [PATCH 06/18] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8 Date: Wed, 08 Jan 2014 10:25:24 +0000 [thread overview] Message-ID: <1389176736-26821-7-git-send-email-paulus@samba.org> (raw) In-Reply-To: <1389176736-26821-1-git-send-email-paulus@samba.org> This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7) compatibility modes on a POWER8 processor. (Note that transactional memory is disabled for usermode if either or both of the PCR_TM_DIS and PCR_ARCH_206 bits are set.) Signed-off-by: Paul Mackerras <paulus@samba.org> --- arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/kvm/book3s_hv.c | 16 +++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 2f41e64..5a99831 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -329,6 +329,8 @@ #define SPRN_PCR 0x152 /* Processor compatibility register */ #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ +#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ +#define PCR_ARCH_206 0x4 /* Architecture 2.06 */ #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index b89701a..e804ede 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -182,14 +182,28 @@ int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat) switch (arch_compat) { case PVR_ARCH_205: - pcr = PCR_ARCH_205; + /* + * If an arch bit is set in PCR, all the defined + * higher-order arch bits also have to be set. + */ + pcr = PCR_ARCH_206 | PCR_ARCH_205; break; case PVR_ARCH_206: case PVR_ARCH_206p: + pcr = PCR_ARCH_206; + break; + case PVR_ARCH_207: break; default: return -EINVAL; } + + if (!cpu_has_feature(CPU_FTR_ARCH_207S)) { + /* POWER7 can't emulate POWER8 */ + if (!(pcr & PCR_ARCH_206)) + return -EINVAL; + pcr &= ~PCR_ARCH_206; + } } spin_lock(&vc->lock); -- 1.8.5.2
next prev parent reply other threads:[~2014-01-08 10:26 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-01-08 10:25 [PATCH 00/18] KVM: PPC: Book3S HV: POWER8 support Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 01/18] KVM: PPC: Book3S HV: Don't set DABR on POWER8 Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 02/18] KVM: PPC: Book3S HV: Align physical and virtual CPU thread numbers Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 03/18] KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 04/18] KVM: PPC: Book3S HV: Flush the correct number of TLB sets on POWER8 Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 05/18] KVM: PPC: Book3S HV: Add handler for HV facility unavailable Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras [this message] 2014-01-08 10:25 ` [PATCH 06/18] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8 Paul Mackerras 2014-01-08 10:25 ` [PATCH 07/18] KVM: PPC: Book3S HV: Consolidate code that checks reason for wake from nap Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-27 11:16 ` Alexander Graf 2014-01-27 11:16 ` Alexander Graf 2014-01-08 10:25 ` [PATCH 08/18] KVM: PPC: Book3S HV: Handle guest using doorbells for IPIs Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 09/18] KVM: PPC: Book3S HV: Handle new LPCR bits on POWER8 Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 10/18] KVM: PPC: Book3S HV: Prepare for host using hypervisor doorbells Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 11/18] KVM: PPC: Book3S HV: Add support for DABRX register on POWER7 Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 12/18] KVM: PPC: Book3S HV: Basic little-endian guest support Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 13/18] powerpc/Kconfig: Make TM select VSX and VMX Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 14/18] KVM: PPC: Book3S HV: Add new state for transactional memory Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-27 12:23 ` Alexander Graf 2014-01-27 12:23 ` Alexander Graf 2014-01-08 10:25 ` [PATCH 15/18] KVM: PPC: Book3S HV: Add software abort codes " Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 16/18] KVM: PPC: Book3S HV: Add transactional memory support Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-27 12:47 ` Alexander Graf 2014-01-27 12:47 ` Alexander Graf 2014-03-24 1:18 ` Paul Mackerras 2014-03-24 1:18 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 17/18] KVM: PPC: Book3S HV: Add get/set_one_reg for new TM state Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-08 10:25 ` [PATCH 18/18] KVM: PPC: Book3S PR: Cope with doorbell interrupts Paul Mackerras 2014-01-08 10:25 ` Paul Mackerras 2014-01-27 12:50 ` [PATCH 00/18] KVM: PPC: Book3S HV: POWER8 support Alexander Graf 2014-01-27 12:50 ` Alexander Graf
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