[PATCHv9 0/4] socfpga: Enable SD/MMC support

[PATCHv9 0/4] socfpga: Enable SD/MMC support

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Hi,

This is v9 of that patch series to enable SD/MMC on the SOCFPGA platform.

V9 differences from v8:

* Update the Makefile to remove the SOCFPGA DW platform specific build.

Thanks,
Dinh

Dinh Nguyen (4):
  clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc
  ARM: socfpga_defconfig: enable SD/MMC support

 .../devicetree/bindings/clock/altr_socfpga.txt     |    5 +
 arch/arm/boot/dts/socfpga.dtsi                     |   14 +-
 arch/arm/boot/dts/socfpga_arria5.dtsi              |   11 ++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi            |   11 ++
 arch/arm/boot/dts/socfpga_vt.dts                   |   11 ++
 arch/arm/configs/socfpga_defconfig                 |    2 +
 drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++
 drivers/mmc/host/Kconfig                           |    8 --
 drivers/mmc/host/Makefile                          |    1 -
 drivers/mmc/host/dw_mmc-socfpga.c                  |  138 --------------------
 10 files changed, 121 insertions(+), 148 deletions(-)
 delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

-- 
1.7.9.5

[PATCHv9 0/4] socfpga: Enable SD/MMC support

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Hi,

This is v9 of that patch series to enable SD/MMC on the SOCFPGA platform.

V9 differences from v8:

* Update the Makefile to remove the SOCFPGA DW platform specific build.

Thanks,
Dinh

Dinh Nguyen (4):
  clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc
  ARM: socfpga_defconfig: enable SD/MMC support

 .../devicetree/bindings/clock/altr_socfpga.txt     |    5 +
 arch/arm/boot/dts/socfpga.dtsi                     |   14 +-
 arch/arm/boot/dts/socfpga_arria5.dtsi              |   11 ++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi            |   11 ++
 arch/arm/boot/dts/socfpga_vt.dts                   |   11 ++
 arch/arm/configs/socfpga_defconfig                 |    2 +
 drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++
 drivers/mmc/host/Kconfig                           |    8 --
 drivers/mmc/host/Makefile                          |    1 -
 drivers/mmc/host/dw_mmc-socfpga.c                  |  138 --------------------
 10 files changed, 121 insertions(+), 148 deletions(-)
 delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

-- 
1.7.9.5

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[dinguyen-EIB2kfCEclfQT0dZR+AlfA]

From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>

The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.

Signed-off-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
Acked-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
 arch/arm/boot/dts/socfpga.dtsi                     |    1 +
 drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
 3 files changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433..5dfd145 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
         and the bit index.
 - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
         and width.
+- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
+	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
+	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
+	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
+	can be 0-315 degrees, in 45 degree increments.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f936476..e776512 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -413,6 +413,7 @@
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 						clk-gate = <0xa0 8>;
+						clk-phase = <0 135>;
 					};
 
 					nand_x_clk: nand_x_clk {
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 4efcf4e..501d513 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -19,7 +19,9 @@
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
+#include <linux/regmap.h>
 
 #include "clk.h"
 
@@ -35,6 +37,11 @@
 
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
 	u32 l4_src;
@@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+	struct regmap *sys_mgr_base_addr;
+	int i;
+	u32 hs_timing;
+	u32 clk_phase[2];
+
+	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+		if (IS_ERR(sys_mgr_base_addr)) {
+			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
+			return -EINVAL;
+		}
+
+		for (i = 0; i < 2; i++) {
+			switch (socfpgaclk->clk_phase[i]) {
+			case 0:
+				clk_phase[i] = 0;
+				break;
+			case 45:
+				clk_phase[i] = 1;
+				break;
+			case 90:
+				clk_phase[i] = 2;
+				break;
+			case 135:
+				clk_phase[i] = 3;
+				break;
+			case 180:
+				clk_phase[i] = 4;
+				break;
+			case 225:
+				clk_phase[i] = 5;
+				break;
+			case 270:
+				clk_phase[i] = 6;
+				break;
+			case 315:
+				clk_phase[i] = 7;
+				break;
+			default:
+				clk_phase[i] = 0;
+				break;
+			}
+		}
+		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
+			hs_timing);
+	}
+	return 0;
+}
+
 static struct clk_ops gateclk_ops = {
+	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_clk_recalc_rate,
 	.get_parent = socfpga_clk_get_parent,
 	.set_parent = socfpga_clk_set_parent,
@@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
+	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk *clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
 		socfpga_clk->div_reg = 0;
 	}
 
+	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
+	if (!rc) {
+		socfpga_clk->clk_phase[0] = clk_phase[0];
+		socfpga_clk->clk_phase[1] = clk_phase[1];
+	}
+
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
-- 
1.7.9.5


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[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver
---
 .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
 arch/arm/boot/dts/socfpga.dtsi                     |    1 +
 drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
 3 files changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433..5dfd145 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
         and the bit index.
 - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
         and width.
+- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
+	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
+	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
+	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
+	can be 0-315 degrees, in 45 degree increments.
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f936476..e776512 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -413,6 +413,7 @@
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 						clk-gate = <0xa0 8>;
+						clk-phase = <0 135>;
 					};
 
 					nand_x_clk: nand_x_clk {
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 4efcf4e..501d513 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -19,7 +19,9 @@
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
+#include <linux/regmap.h>
 
 #include "clk.h"
 
@@ -35,6 +37,11 @@
 
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
 	u32 l4_src;
@@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+	struct regmap *sys_mgr_base_addr;
+	int i;
+	u32 hs_timing;
+	u32 clk_phase[2];
+
+	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+		if (IS_ERR(sys_mgr_base_addr)) {
+			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
+			return -EINVAL;
+		}
+
+		for (i = 0; i < 2; i++) {
+			switch (socfpgaclk->clk_phase[i]) {
+			case 0:
+				clk_phase[i] = 0;
+				break;
+			case 45:
+				clk_phase[i] = 1;
+				break;
+			case 90:
+				clk_phase[i] = 2;
+				break;
+			case 135:
+				clk_phase[i] = 3;
+				break;
+			case 180:
+				clk_phase[i] = 4;
+				break;
+			case 225:
+				clk_phase[i] = 5;
+				break;
+			case 270:
+				clk_phase[i] = 6;
+				break;
+			case 315:
+				clk_phase[i] = 7;
+				break;
+			default:
+				clk_phase[i] = 0;
+				break;
+			}
+		}
+		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
+			hs_timing);
+	}
+	return 0;
+}
+
 static struct clk_ops gateclk_ops = {
+	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_clk_recalc_rate,
 	.get_parent = socfpga_clk_get_parent,
 	.set_parent = socfpga_clk_set_parent,
@@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
+	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk *clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
 		socfpga_clk->div_reg = 0;
 	}
 
+	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
+	if (!rc) {
+		socfpga_clk->clk_phase[0] = clk_phase[0];
+		socfpga_clk->clk_phase[1] = clk_phase[1];
+	}
+
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
-- 
1.7.9.5

[PATCHv9 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Use the "snps,dw-mshc" binding to enable the dw_mmc driver.
Add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: none
v8: none
v7: Use the standard "snps,dw-mshc" binding. Remove "altr,socfpga-sdmmc-sdr-clk".
v6: Add documentation for "altr,socfpga-sdmmc-sdr-clk". Add "syscon" to the
sysmgr binding.
v5: Use the "snps,dw-mshc" binding
v4: Re-use "rockchip,rk2928-dw-mshc" binding
v3: none
v2: none
---
 arch/arm/boot/dts/socfpga.dtsi          |   13 ++++++++++++-
 arch/arm/boot/dts/socfpga_arria5.dtsi   |   11 +++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |   11 +++++++++++
 arch/arm/boot/dts/socfpga_vt.dts        |   11 +++++++++++
 4 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index e776512..433bfbc 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -470,6 +470,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0@ff704000 {
+			compatible = "snps,dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer@fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
@@ -524,7 +535,7 @@
 		};
 
 		sysmgr@ffd08000 {
-				compatible = "altr,sys-mgr";
+				compatible = "altr,sys-mgr", "syscon";
 				reg = <0xffd08000 0x4000>;
 			};
 	};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b404..6c87b70 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
 			};
 		};
 
+		dwmmc0@ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot@0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		serial0@ffc02000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a8716f6..ca41b0e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,17 @@
 			};
 		};
 
+		dwmmc0@ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot@0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		ethernet@ff702000 {
 			phy-mode = "rgmii";
 			phy-addr = <0xffffffff>; /* probe for phy addr */
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0ca..222313f 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,17 @@
 			};
 		};
 
+		dwmmc0@ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot@0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		ethernet@ff700000 {
 			phy-mode = "gmii";
 			status = "okay";
-- 
1.7.9.5

[PATCHv9 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Use the "snps,dw-mshc" binding to enable the dw_mmc driver.
Add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: none
v8: none
v7: Use the standard "snps,dw-mshc" binding. Remove "altr,socfpga-sdmmc-sdr-clk".
v6: Add documentation for "altr,socfpga-sdmmc-sdr-clk". Add "syscon" to the
sysmgr binding.
v5: Use the "snps,dw-mshc" binding
v4: Re-use "rockchip,rk2928-dw-mshc" binding
v3: none
v2: none
---
 arch/arm/boot/dts/socfpga.dtsi          |   13 ++++++++++++-
 arch/arm/boot/dts/socfpga_arria5.dtsi   |   11 +++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dtsi |   11 +++++++++++
 arch/arm/boot/dts/socfpga_vt.dts        |   11 +++++++++++
 4 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index e776512..433bfbc 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -470,6 +470,17 @@
 			cache-level = <2>;
 		};
 
+		mmc: dwmmc0 at ff704000 {
+			compatible = "snps,dw-mshc";
+			reg = <0xff704000 0x1000>;
+			interrupts = <0 139 4>;
+			fifo-depth = <0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+			clock-names = "biu", "ciu";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
@@ -524,7 +535,7 @@
 		};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
+				compatible = "altr,sys-mgr", "syscon";
 				reg = <0xffd08000 0x4000>;
 			};
 	};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b404..6c87b70 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
 			};
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		serial0 at ffc02000 {
 			clock-frequency = <100000000>;
 		};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a8716f6..ca41b0e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,17 @@
 			};
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		ethernet at ff702000 {
 			phy-mode = "rgmii";
 			phy-addr = <0xffffffff>; /* probe for phy addr */
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0ca..222313f 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,17 @@
 			};
 		};
 
+		dwmmc0 at ff704000 {
+			num-slots = <1>;
+			supports-highspeed;
+			broken-cd;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+			};
+		};
+
 		ethernet at ff700000 {
 			phy-mode = "gmii";
 			status = "okay";
-- 
1.7.9.5

[PATCHv9 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

It turns now that the only really platform specific code that is needed for
SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
Since the Rockchip already has this functionality, re-use the code that is
already in dw_mmc-pltfm.c.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: Updated Makefile to also remove dw-mmc-socfpga
v8: none
v7: none
v6: none
v5: none
v4: Remove dw_mmc-socfpga platform specific code
v3: none
v2: none
---
 drivers/mmc/host/Kconfig          |    8 ---
 drivers/mmc/host/Makefile         |    1 -
 drivers/mmc/host/dw_mmc-socfpga.c |  138 -------------------------------------
 3 files changed, 147 deletions(-)
 delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 7fc5099..6737a4f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -567,14 +567,6 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
-config MMC_DW_SOCFPGA
-	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
-	depends on MMC_DW && MFD_SYSCON
-	select MMC_DW_PLTFM
-	help
-	  This selects support for Altera SoCFPGA specific extensions to the
-	  Synopsys DesignWare Memory Card Interface driver.
-
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c41d0c3..8779c4b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
-obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
deleted file mode 100644
index 3e8e53a..0000000
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface
- * driver
- *
- *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
- *  Copyright (C) 2013 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Taken from dw_mmc-exynos.c
- */
-#include <linux/clk.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/dw_mmc.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "dw_mmc.h"
-#include "dw_mmc-pltfm.h"
-
-#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
-#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
-	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
-
-/* SOCFPGA implementation specific driver private data */
-struct dw_mci_socfpga_priv_data {
-	u8	ciu_div; /* card interface unit divisor */
-	u32	hs_timing; /* bitmask for CIU clock phase shift */
-	struct regmap   *sysreg; /* regmap for system manager register */
-};
-
-static int dw_mci_socfpga_priv_init(struct dw_mci *host)
-{
-	return 0;
-}
-
-static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
-{
-	struct dw_mci_socfpga_priv_data *priv = host->priv;
-
-	clk_disable_unprepare(host->ciu_clk);
-	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
-		priv->hs_timing);
-	clk_prepare_enable(host->ciu_clk);
-
-	host->bus_hz /= (priv->ciu_div + 1);
-	return 0;
-}
-
-static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
-{
-	struct dw_mci_socfpga_priv_data *priv = host->priv;
-
-	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
-		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
-}
-
-static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
-{
-	struct dw_mci_socfpga_priv_data *priv;
-	struct device_node *np = host->dev->of_node;
-	u32 timing[2];
-	u32 div = 0;
-	int ret;
-
-	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv) {
-		dev_err(host->dev, "mem alloc failed for private data\n");
-		return -ENOMEM;
-	}
-
-	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-	if (IS_ERR(priv->sysreg)) {
-		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-		return PTR_ERR(priv->sysreg);
-	}
-
-	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
-	if (ret)
-		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
-	priv->ciu_div = div;
-
-	ret = of_property_read_u32_array(np,
-			"altr,dw-mshc-sdr-timing", timing, 2);
-	if (ret)
-		return ret;
-
-	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
-	host->priv = priv;
-	return 0;
-}
-
-static const struct dw_mci_drv_data socfpga_drv_data = {
-	.init			= dw_mci_socfpga_priv_init,
-	.setup_clock		= dw_mci_socfpga_setup_clock,
-	.prepare_command	= dw_mci_socfpga_prepare_command,
-	.parse_dt		= dw_mci_socfpga_parse_dt,
-};
-
-static const struct of_device_id dw_mci_socfpga_match[] = {
-	{ .compatible = "altr,socfpga-dw-mshc",
-			.data = &socfpga_drv_data, },
-	{},
-};
-MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
-
-static int dw_mci_socfpga_probe(struct platform_device *pdev)
-{
-	const struct dw_mci_drv_data *drv_data;
-	const struct of_device_id *match;
-
-	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
-	drv_data = match->data;
-	return dw_mci_pltfm_register(pdev, drv_data);
-}
-
-static struct platform_driver dw_mci_socfpga_pltfm_driver = {
-	.probe		= dw_mci_socfpga_probe,
-	.remove		= __exit_p(dw_mci_pltfm_remove),
-	.driver		= {
-		.name		= "dwmmc_socfpga",
-		.of_match_table	= dw_mci_socfpga_match,
-		.pm		= &dw_mci_pltfm_pmops,
-	},
-};
-
-module_platform_driver(dw_mci_socfpga_pltfm_driver);
-
-MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:dwmmc-socfpga");
-- 
1.7.9.5

[PATCHv9 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

It turns now that the only really platform specific code that is needed for
SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
Since the Rockchip already has this functionality, re-use the code that is
already in dw_mmc-pltfm.c.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: Updated Makefile to also remove dw-mmc-socfpga
v8: none
v7: none
v6: none
v5: none
v4: Remove dw_mmc-socfpga platform specific code
v3: none
v2: none
---
 drivers/mmc/host/Kconfig          |    8 ---
 drivers/mmc/host/Makefile         |    1 -
 drivers/mmc/host/dw_mmc-socfpga.c |  138 -------------------------------------
 3 files changed, 147 deletions(-)
 delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 7fc5099..6737a4f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -567,14 +567,6 @@ config MMC_DW_EXYNOS
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
 	  for platforms based on Exynos4 and Exynos5 SoC's.
 
-config MMC_DW_SOCFPGA
-	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
-	depends on MMC_DW && MFD_SYSCON
-	select MMC_DW_PLTFM
-	help
-	  This selects support for Altera SoCFPGA specific extensions to the
-	  Synopsys DesignWare Memory Card Interface driver.
-
 config MMC_DW_PCI
 	tristate "Synopsys Designware MCI support on PCI bus"
 	depends on MMC_DW && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c41d0c3..8779c4b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
 obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
 obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
 obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
-obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
 obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
 obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
deleted file mode 100644
index 3e8e53a..0000000
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface
- * driver
- *
- *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
- *  Copyright (C) 2013 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Taken from dw_mmc-exynos.c
- */
-#include <linux/clk.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/dw_mmc.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "dw_mmc.h"
-#include "dw_mmc-pltfm.h"
-
-#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
-#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
-	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
-
-/* SOCFPGA implementation specific driver private data */
-struct dw_mci_socfpga_priv_data {
-	u8	ciu_div; /* card interface unit divisor */
-	u32	hs_timing; /* bitmask for CIU clock phase shift */
-	struct regmap   *sysreg; /* regmap for system manager register */
-};
-
-static int dw_mci_socfpga_priv_init(struct dw_mci *host)
-{
-	return 0;
-}
-
-static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
-{
-	struct dw_mci_socfpga_priv_data *priv = host->priv;
-
-	clk_disable_unprepare(host->ciu_clk);
-	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
-		priv->hs_timing);
-	clk_prepare_enable(host->ciu_clk);
-
-	host->bus_hz /= (priv->ciu_div + 1);
-	return 0;
-}
-
-static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
-{
-	struct dw_mci_socfpga_priv_data *priv = host->priv;
-
-	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
-		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
-}
-
-static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
-{
-	struct dw_mci_socfpga_priv_data *priv;
-	struct device_node *np = host->dev->of_node;
-	u32 timing[2];
-	u32 div = 0;
-	int ret;
-
-	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv) {
-		dev_err(host->dev, "mem alloc failed for private data\n");
-		return -ENOMEM;
-	}
-
-	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-	if (IS_ERR(priv->sysreg)) {
-		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-		return PTR_ERR(priv->sysreg);
-	}
-
-	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
-	if (ret)
-		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
-	priv->ciu_div = div;
-
-	ret = of_property_read_u32_array(np,
-			"altr,dw-mshc-sdr-timing", timing, 2);
-	if (ret)
-		return ret;
-
-	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
-	host->priv = priv;
-	return 0;
-}
-
-static const struct dw_mci_drv_data socfpga_drv_data = {
-	.init			= dw_mci_socfpga_priv_init,
-	.setup_clock		= dw_mci_socfpga_setup_clock,
-	.prepare_command	= dw_mci_socfpga_prepare_command,
-	.parse_dt		= dw_mci_socfpga_parse_dt,
-};
-
-static const struct of_device_id dw_mci_socfpga_match[] = {
-	{ .compatible = "altr,socfpga-dw-mshc",
-			.data = &socfpga_drv_data, },
-	{},
-};
-MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
-
-static int dw_mci_socfpga_probe(struct platform_device *pdev)
-{
-	const struct dw_mci_drv_data *drv_data;
-	const struct of_device_id *match;
-
-	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
-	drv_data = match->data;
-	return dw_mci_pltfm_register(pdev, drv_data);
-}
-
-static struct platform_driver dw_mci_socfpga_pltfm_driver = {
-	.probe		= dw_mci_socfpga_probe,
-	.remove		= __exit_p(dw_mci_pltfm_remove),
-	.driver		= {
-		.name		= "dwmmc_socfpga",
-		.of_match_table	= dw_mci_socfpga_match,
-		.pm		= &dw_mci_pltfm_pmops,
-	},
-};
-
-module_platform_driver(dw_mci_socfpga_pltfm_driver);
-
-MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:dwmmc-socfpga");
-- 
1.7.9.5

[PATCHv9 4/4] ARM: socfpga_defconfig: enable SD/MMC support

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Enables the dw_mmc driver for SOCFPGA.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: none
v8: none
v7: none
v6: none
v5: Add dw_mmc driver into socfpga_defconfig
v4: none
v3: none
v2: none
---
 arch/arm/configs/socfpga_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce21..8fff96ba 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -82,3 +82,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_ENABLE_DEFAULT_TRACERS=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
-- 
1.7.9.5

[PATCHv9 4/4] ARM: socfpga_defconfig: enable SD/MMC support

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Enables the dw_mmc driver for SOCFPGA.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v9: none
v8: none
v7: none
v6: none
v5: Add dw_mmc driver into socfpga_defconfig
v4: none
v3: none
v2: none
---
 arch/arm/configs/socfpga_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce21..8fff96ba 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -82,3 +82,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_ENABLE_DEFAULT_TRACERS=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
-- 
1.7.9.5

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> The clk-phase property is used to represent the 2 clock phase values that is
> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> use the syscon driver to set sdmmc_clk's phase shift that is located in the
> system manager.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
> v9: none
> v8: Use degrees in the clk-phase binding property
> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>     prepare function to the gate clk that will toggle clock phase setting.
>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>     set the phase shift settings.
> v5: Use the "snps,dw-mshc" binding
> v4: Use the sdmmc_clk prepare function to set the phase shift settings
> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>     loaded after the clock driver.
> v2: Use the syscon driver
> ---
>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>  3 files changed, 74 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> index 0045433..5dfd145 100644
> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> @@ -23,3 +23,8 @@ Optional properties:
>          and the bit index.
>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>          and width.
> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> +	can be 0-315 degrees, in 45 degree increments.
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f936476..e776512 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -413,6 +413,7 @@
>  						compatible = "altr,socfpga-gate-clk";
>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
>  						clk-gate = <0xa0 8>;
> +						clk-phase = <0 135>;
>  					};
>  
>  					nand_x_clk: nand_x_clk {
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 4efcf4e..501d513 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -19,7 +19,9 @@
>  #include <linux/clkdev.h>
>  #include <linux/clk-provider.h>
>  #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/of.h>
> +#include <linux/regmap.h>
>  
>  #include "clk.h"
>  
> @@ -35,6 +37,11 @@
>  
>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
>  
> +/* SDMMC Group for System Manager defines */
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> +
>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>  {
>  	u32 l4_src;
> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  	return parent_rate / div;
>  }
>  
> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	struct regmap *sys_mgr_base_addr;
> +	int i;
> +	u32 hs_timing;
> +	u32 clk_phase[2];
> +
> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +		if (IS_ERR(sys_mgr_base_addr)) {
> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> +			return -EINVAL;
> +		}
> +
> +		for (i = 0; i < 2; i++) {
> +			switch (socfpgaclk->clk_phase[i]) {
> +			case 0:
> +				clk_phase[i] = 0;
> +				break;
> +			case 45:
> +				clk_phase[i] = 1;
> +				break;
> +			case 90:
> +				clk_phase[i] = 2;
> +				break;
> +			case 135:
> +				clk_phase[i] = 3;
> +				break;
> +			case 180:
> +				clk_phase[i] = 4;
> +				break;
> +			case 225:
> +				clk_phase[i] = 5;
> +				break;
> +			case 270:
> +				clk_phase[i] = 6;
> +				break;
> +			case 315:
> +				clk_phase[i] = 7;
> +				break;
> +			default:
> +				clk_phase[i] = 0;
> +				break;
> +			}
> +		}
> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> +			hs_timing);
> +	}
> +	return 0;
> +}
> +
>  static struct clk_ops gateclk_ops = {
> +	.prepare = socfpga_clk_prepare,
>  	.recalc_rate = socfpga_clk_recalc_rate,
>  	.get_parent = socfpga_clk_get_parent,
>  	.set_parent = socfpga_clk_set_parent,
> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  {
>  	u32 clk_gate[2];
>  	u32 div_reg[3];
> +	u32 clk_phase[2];
>  	u32 fixed_div;
>  	struct clk *clk;
>  	struct socfpga_gate_clk *socfpga_clk;
> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  		socfpga_clk->div_reg = 0;
>  	}
>  
> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> +	if (!rc) {
> +		socfpga_clk->clk_phase[0] = clk_phase[0];
> +		socfpga_clk->clk_phase[1] = clk_phase[1];
> +	}
> +
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  
>  	init.name = clk_name;
> 

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> The clk-phase property is used to represent the 2 clock phase values that is
> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> use the syscon driver to set sdmmc_clk's phase shift that is located in the
> system manager.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
> v9: none
> v8: Use degrees in the clk-phase binding property
> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>     prepare function to the gate clk that will toggle clock phase setting.
>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>     set the phase shift settings.
> v5: Use the "snps,dw-mshc" binding
> v4: Use the sdmmc_clk prepare function to set the phase shift settings
> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>     loaded after the clock driver.
> v2: Use the syscon driver
> ---
>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>  3 files changed, 74 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> index 0045433..5dfd145 100644
> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> @@ -23,3 +23,8 @@ Optional properties:
>          and the bit index.
>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>          and width.
> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> +	can be 0-315 degrees, in 45 degree increments.
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f936476..e776512 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -413,6 +413,7 @@
>  						compatible = "altr,socfpga-gate-clk";
>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
>  						clk-gate = <0xa0 8>;
> +						clk-phase = <0 135>;
>  					};
>  
>  					nand_x_clk: nand_x_clk {
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 4efcf4e..501d513 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -19,7 +19,9 @@
>  #include <linux/clkdev.h>
>  #include <linux/clk-provider.h>
>  #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/of.h>
> +#include <linux/regmap.h>
>  
>  #include "clk.h"
>  
> @@ -35,6 +37,11 @@
>  
>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
>  
> +/* SDMMC Group for System Manager defines */
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> +
>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>  {
>  	u32 l4_src;
> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  	return parent_rate / div;
>  }
>  
> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	struct regmap *sys_mgr_base_addr;
> +	int i;
> +	u32 hs_timing;
> +	u32 clk_phase[2];
> +
> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +		if (IS_ERR(sys_mgr_base_addr)) {
> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> +			return -EINVAL;
> +		}
> +
> +		for (i = 0; i < 2; i++) {
> +			switch (socfpgaclk->clk_phase[i]) {
> +			case 0:
> +				clk_phase[i] = 0;
> +				break;
> +			case 45:
> +				clk_phase[i] = 1;
> +				break;
> +			case 90:
> +				clk_phase[i] = 2;
> +				break;
> +			case 135:
> +				clk_phase[i] = 3;
> +				break;
> +			case 180:
> +				clk_phase[i] = 4;
> +				break;
> +			case 225:
> +				clk_phase[i] = 5;
> +				break;
> +			case 270:
> +				clk_phase[i] = 6;
> +				break;
> +			case 315:
> +				clk_phase[i] = 7;
> +				break;
> +			default:
> +				clk_phase[i] = 0;
> +				break;
> +			}
> +		}
> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> +			hs_timing);
> +	}
> +	return 0;
> +}
> +
>  static struct clk_ops gateclk_ops = {
> +	.prepare = socfpga_clk_prepare,
>  	.recalc_rate = socfpga_clk_recalc_rate,
>  	.get_parent = socfpga_clk_get_parent,
>  	.set_parent = socfpga_clk_set_parent,
> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  {
>  	u32 clk_gate[2];
>  	u32 div_reg[3];
> +	u32 clk_phase[2];
>  	u32 fixed_div;
>  	struct clk *clk;
>  	struct socfpga_gate_clk *socfpga_clk;
> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  		socfpga_clk->div_reg = 0;
>  	}
>  
> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> +	if (!rc) {
> +		socfpga_clk->clk_phase[0] = clk_phase[0];
> +		socfpga_clk->clk_phase[1] = clk_phase[1];
> +	}
> +
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  
>  	init.name = clk_name;
> 

Re: [PATCHv9 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Use the "snps,dw-mshc" binding to enable the dw_mmc driver.
> Add the "syscon" binding to the "altr,sys-mgr" node. The clock
> driver can use the syscon driver to toggle the register for the SD/MMC
> clock phase shift settings.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: none
> v8: none
> v7: Use the standard "snps,dw-mshc" binding. Remove "altr,socfpga-sdmmc-sdr-clk".
> v6: Add documentation for "altr,socfpga-sdmmc-sdr-clk". Add "syscon" to the
> sysmgr binding.
> v5: Use the "snps,dw-mshc" binding
> v4: Re-use "rockchip,rk2928-dw-mshc" binding
> v3: none
> v2: none
> ---
>  arch/arm/boot/dts/socfpga.dtsi          |   13 ++++++++++++-
>  arch/arm/boot/dts/socfpga_arria5.dtsi   |   11 +++++++++++
>  arch/arm/boot/dts/socfpga_cyclone5.dtsi |   11 +++++++++++
>  arch/arm/boot/dts/socfpga_vt.dts        |   11 +++++++++++
>  4 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index e776512..433bfbc 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -470,6 +470,17 @@
>  			cache-level = <2>;
>  		};
>  
> +		mmc: dwmmc0@ff704000 {
> +			compatible = "snps,dw-mshc";
> +			reg = <0xff704000 0x1000>;
> +			interrupts = <0 139 4>;
> +			fifo-depth = <0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
> +			clock-names = "biu", "ciu";
> +		};
> +
>  		/* Local timer */
>  		timer@fffec600 {
>  			compatible = "arm,cortex-a9-twd-timer";
> @@ -524,7 +535,7 @@
>  		};
>  
>  		sysmgr@ffd08000 {
> -				compatible = "altr,sys-mgr";
> +				compatible = "altr,sys-mgr", "syscon";
>  				reg = <0xffd08000 0x4000>;
>  			};
>  	};
> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
> index a85b404..6c87b70 100644
> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
> @@ -27,6 +27,17 @@
>  			};
>  		};
>  
> +		dwmmc0@ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot@0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		serial0@ffc02000 {
>  			clock-frequency = <100000000>;
>  		};
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index a8716f6..ca41b0e 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -28,6 +28,17 @@
>  			};
>  		};
>  
> +		dwmmc0@ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot@0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		ethernet@ff702000 {
>  			phy-mode = "rgmii";
>  			phy-addr = <0xffffffff>; /* probe for phy addr */
> diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> index d1ec0ca..222313f 100644
> --- a/arch/arm/boot/dts/socfpga_vt.dts
> +++ b/arch/arm/boot/dts/socfpga_vt.dts
> @@ -41,6 +41,17 @@
>  			};
>  		};
>  
> +		dwmmc0@ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot@0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		ethernet@ff700000 {
>  			phy-mode = "gmii";
>  			status = "okay";
> 

[PATCHv9 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Use the "snps,dw-mshc" binding to enable the dw_mmc driver.
> Add the "syscon" binding to the "altr,sys-mgr" node. The clock
> driver can use the syscon driver to toggle the register for the SD/MMC
> clock phase shift settings.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: none
> v8: none
> v7: Use the standard "snps,dw-mshc" binding. Remove "altr,socfpga-sdmmc-sdr-clk".
> v6: Add documentation for "altr,socfpga-sdmmc-sdr-clk". Add "syscon" to the
> sysmgr binding.
> v5: Use the "snps,dw-mshc" binding
> v4: Re-use "rockchip,rk2928-dw-mshc" binding
> v3: none
> v2: none
> ---
>  arch/arm/boot/dts/socfpga.dtsi          |   13 ++++++++++++-
>  arch/arm/boot/dts/socfpga_arria5.dtsi   |   11 +++++++++++
>  arch/arm/boot/dts/socfpga_cyclone5.dtsi |   11 +++++++++++
>  arch/arm/boot/dts/socfpga_vt.dts        |   11 +++++++++++
>  4 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index e776512..433bfbc 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -470,6 +470,17 @@
>  			cache-level = <2>;
>  		};
>  
> +		mmc: dwmmc0 at ff704000 {
> +			compatible = "snps,dw-mshc";
> +			reg = <0xff704000 0x1000>;
> +			interrupts = <0 139 4>;
> +			fifo-depth = <0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
> +			clock-names = "biu", "ciu";
> +		};
> +
>  		/* Local timer */
>  		timer at fffec600 {
>  			compatible = "arm,cortex-a9-twd-timer";
> @@ -524,7 +535,7 @@
>  		};
>  
>  		sysmgr at ffd08000 {
> -				compatible = "altr,sys-mgr";
> +				compatible = "altr,sys-mgr", "syscon";
>  				reg = <0xffd08000 0x4000>;
>  			};
>  	};
> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
> index a85b404..6c87b70 100644
> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
> @@ -27,6 +27,17 @@
>  			};
>  		};
>  
> +		dwmmc0 at ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot at 0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		serial0 at ffc02000 {
>  			clock-frequency = <100000000>;
>  		};
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index a8716f6..ca41b0e 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -28,6 +28,17 @@
>  			};
>  		};
>  
> +		dwmmc0 at ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot at 0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		ethernet at ff702000 {
>  			phy-mode = "rgmii";
>  			phy-addr = <0xffffffff>; /* probe for phy addr */
> diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> index d1ec0ca..222313f 100644
> --- a/arch/arm/boot/dts/socfpga_vt.dts
> +++ b/arch/arm/boot/dts/socfpga_vt.dts
> @@ -41,6 +41,17 @@
>  			};
>  		};
>  
> +		dwmmc0 at ff704000 {
> +			num-slots = <1>;
> +			supports-highspeed;
> +			broken-cd;
> +
> +			slot at 0 {
> +				reg = <0>;
> +				bus-width = <4>;
> +			};
> +		};
> +
>  		ethernet at ff700000 {
>  			phy-mode = "gmii";
>  			status = "okay";
> 

Re: [PATCHv9 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> It turns now that the only really platform specific code that is needed for
> SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
> Since the Rockchip already has this functionality, re-use the code that is
> already in dw_mmc-pltfm.c.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: Updated Makefile to also remove dw-mmc-socfpga
> v8: none
> v7: none
> v6: none
> v5: none
> v4: Remove dw_mmc-socfpga platform specific code
> v3: none
> v2: none
> ---
>  drivers/mmc/host/Kconfig          |    8 ---
>  drivers/mmc/host/Makefile         |    1 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  138 -------------------------------------
>  3 files changed, 147 deletions(-)
>  delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 7fc5099..6737a4f 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -567,14 +567,6 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>  
> -config MMC_DW_SOCFPGA
> -	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> -	depends on MMC_DW && MFD_SYSCON
> -	select MMC_DW_PLTFM
> -	help
> -	  This selects support for Altera SoCFPGA specific extensions to the
> -	  Synopsys DesignWare Memory Card Interface driver.
> -
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index c41d0c3..8779c4b 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,7 +42,6 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> -obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> deleted file mode 100644
> index 3e8e53a..0000000
> --- a/drivers/mmc/host/dw_mmc-socfpga.c
> +++ /dev/null
> @@ -1,138 +0,0 @@
> -/*
> - * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface
> - * driver
> - *
> - *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> - *  Copyright (C) 2013 Altera Corporation
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * Taken from dw_mmc-exynos.c
> - */
> -#include <linux/clk.h>
> -#include <linux/mfd/syscon.h>
> -#include <linux/mmc/host.h>
> -#include <linux/mmc/dw_mmc.h>
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/platform_device.h>
> -#include <linux/regmap.h>
> -
> -#include "dw_mmc.h"
> -#include "dw_mmc-pltfm.h"
> -
> -#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> -#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
> -	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> -
> -/* SOCFPGA implementation specific driver private data */
> -struct dw_mci_socfpga_priv_data {
> -	u8	ciu_div; /* card interface unit divisor */
> -	u32	hs_timing; /* bitmask for CIU clock phase shift */
> -	struct regmap   *sysreg; /* regmap for system manager register */
> -};
> -
> -static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> -{
> -	return 0;
> -}
> -
> -static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> -{
> -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> -
> -	clk_disable_unprepare(host->ciu_clk);
> -	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> -		priv->hs_timing);
> -	clk_prepare_enable(host->ciu_clk);
> -
> -	host->bus_hz /= (priv->ciu_div + 1);
> -	return 0;
> -}
> -
> -static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> -{
> -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> -
> -	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> -		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> -}
> -
> -static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> -{
> -	struct dw_mci_socfpga_priv_data *priv;
> -	struct device_node *np = host->dev->of_node;
> -	u32 timing[2];
> -	u32 div = 0;
> -	int ret;
> -
> -	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> -	if (!priv) {
> -		dev_err(host->dev, "mem alloc failed for private data\n");
> -		return -ENOMEM;
> -	}
> -
> -	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> -	if (IS_ERR(priv->sysreg)) {
> -		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> -		return PTR_ERR(priv->sysreg);
> -	}
> -
> -	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> -	if (ret)
> -		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> -	priv->ciu_div = div;
> -
> -	ret = of_property_read_u32_array(np,
> -			"altr,dw-mshc-sdr-timing", timing, 2);
> -	if (ret)
> -		return ret;
> -
> -	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> -	host->priv = priv;
> -	return 0;
> -}
> -
> -static const struct dw_mci_drv_data socfpga_drv_data = {
> -	.init			= dw_mci_socfpga_priv_init,
> -	.setup_clock		= dw_mci_socfpga_setup_clock,
> -	.prepare_command	= dw_mci_socfpga_prepare_command,
> -	.parse_dt		= dw_mci_socfpga_parse_dt,
> -};
> -
> -static const struct of_device_id dw_mci_socfpga_match[] = {
> -	{ .compatible = "altr,socfpga-dw-mshc",
> -			.data = &socfpga_drv_data, },
> -	{},
> -};
> -MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> -
> -static int dw_mci_socfpga_probe(struct platform_device *pdev)
> -{
> -	const struct dw_mci_drv_data *drv_data;
> -	const struct of_device_id *match;
> -
> -	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> -	drv_data = match->data;
> -	return dw_mci_pltfm_register(pdev, drv_data);
> -}
> -
> -static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> -	.probe		= dw_mci_socfpga_probe,
> -	.remove		= __exit_p(dw_mci_pltfm_remove),
> -	.driver		= {
> -		.name		= "dwmmc_socfpga",
> -		.of_match_table	= dw_mci_socfpga_match,
> -		.pm		= &dw_mci_pltfm_pmops,
> -	},
> -};
> -
> -module_platform_driver(dw_mci_socfpga_pltfm_driver);
> -
> -MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> -MODULE_LICENSE("GPL v2");
> -MODULE_ALIAS("platform:dwmmc-socfpga");
> 

[PATCHv9 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> It turns now that the only really platform specific code that is needed for
> SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
> Since the Rockchip already has this functionality, re-use the code that is
> already in dw_mmc-pltfm.c.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: Updated Makefile to also remove dw-mmc-socfpga
> v8: none
> v7: none
> v6: none
> v5: none
> v4: Remove dw_mmc-socfpga platform specific code
> v3: none
> v2: none
> ---
>  drivers/mmc/host/Kconfig          |    8 ---
>  drivers/mmc/host/Makefile         |    1 -
>  drivers/mmc/host/dw_mmc-socfpga.c |  138 -------------------------------------
>  3 files changed, 147 deletions(-)
>  delete mode 100644 drivers/mmc/host/dw_mmc-socfpga.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 7fc5099..6737a4f 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -567,14 +567,6 @@ config MMC_DW_EXYNOS
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
>  	  for platforms based on Exynos4 and Exynos5 SoC's.
>  
> -config MMC_DW_SOCFPGA
> -	tristate "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
> -	depends on MMC_DW && MFD_SYSCON
> -	select MMC_DW_PLTFM
> -	help
> -	  This selects support for Altera SoCFPGA specific extensions to the
> -	  Synopsys DesignWare Memory Card Interface driver.
> -
>  config MMC_DW_PCI
>  	tristate "Synopsys Designware MCI support on PCI bus"
>  	depends on MMC_DW && PCI
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index c41d0c3..8779c4b 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -42,7 +42,6 @@ obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
>  obj-$(CONFIG_MMC_DW)		+= dw_mmc.o
>  obj-$(CONFIG_MMC_DW_PLTFM)	+= dw_mmc-pltfm.o
>  obj-$(CONFIG_MMC_DW_EXYNOS)	+= dw_mmc-exynos.o
> -obj-$(CONFIG_MMC_DW_SOCFPGA)	+= dw_mmc-socfpga.o
>  obj-$(CONFIG_MMC_DW_PCI)	+= dw_mmc-pci.o
>  obj-$(CONFIG_MMC_SH_MMCIF)	+= sh_mmcif.o
>  obj-$(CONFIG_MMC_JZ4740)	+= jz4740_mmc.o
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> deleted file mode 100644
> index 3e8e53a..0000000
> --- a/drivers/mmc/host/dw_mmc-socfpga.c
> +++ /dev/null
> @@ -1,138 +0,0 @@
> -/*
> - * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface
> - * driver
> - *
> - *  Copyright (C) 2012, Samsung Electronics Co., Ltd.
> - *  Copyright (C) 2013 Altera Corporation
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * Taken from dw_mmc-exynos.c
> - */
> -#include <linux/clk.h>
> -#include <linux/mfd/syscon.h>
> -#include <linux/mmc/host.h>
> -#include <linux/mmc/dw_mmc.h>
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/platform_device.h>
> -#include <linux/regmap.h>
> -
> -#include "dw_mmc.h"
> -#include "dw_mmc-pltfm.h"
> -
> -#define SYSMGR_SDMMCGRP_CTRL_OFFSET		0x108
> -#define DRV_CLK_PHASE_SHIFT_SEL_MASK	0x7
> -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)          \
> -	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> -
> -/* SOCFPGA implementation specific driver private data */
> -struct dw_mci_socfpga_priv_data {
> -	u8	ciu_div; /* card interface unit divisor */
> -	u32	hs_timing; /* bitmask for CIU clock phase shift */
> -	struct regmap   *sysreg; /* regmap for system manager register */
> -};
> -
> -static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> -{
> -	return 0;
> -}
> -
> -static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> -{
> -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> -
> -	clk_disable_unprepare(host->ciu_clk);
> -	regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> -		priv->hs_timing);
> -	clk_prepare_enable(host->ciu_clk);
> -
> -	host->bus_hz /= (priv->ciu_div + 1);
> -	return 0;
> -}
> -
> -static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> -{
> -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> -
> -	if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
> -		*cmdr |= SDMMC_CMD_USE_HOLD_REG;
> -}
> -
> -static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> -{
> -	struct dw_mci_socfpga_priv_data *priv;
> -	struct device_node *np = host->dev->of_node;
> -	u32 timing[2];
> -	u32 div = 0;
> -	int ret;
> -
> -	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> -	if (!priv) {
> -		dev_err(host->dev, "mem alloc failed for private data\n");
> -		return -ENOMEM;
> -	}
> -
> -	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> -	if (IS_ERR(priv->sysreg)) {
> -		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> -		return PTR_ERR(priv->sysreg);
> -	}
> -
> -	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> -	if (ret)
> -		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> -	priv->ciu_div = div;
> -
> -	ret = of_property_read_u32_array(np,
> -			"altr,dw-mshc-sdr-timing", timing, 2);
> -	if (ret)
> -		return ret;
> -
> -	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> -	host->priv = priv;
> -	return 0;
> -}
> -
> -static const struct dw_mci_drv_data socfpga_drv_data = {
> -	.init			= dw_mci_socfpga_priv_init,
> -	.setup_clock		= dw_mci_socfpga_setup_clock,
> -	.prepare_command	= dw_mci_socfpga_prepare_command,
> -	.parse_dt		= dw_mci_socfpga_parse_dt,
> -};
> -
> -static const struct of_device_id dw_mci_socfpga_match[] = {
> -	{ .compatible = "altr,socfpga-dw-mshc",
> -			.data = &socfpga_drv_data, },
> -	{},
> -};
> -MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
> -
> -static int dw_mci_socfpga_probe(struct platform_device *pdev)
> -{
> -	const struct dw_mci_drv_data *drv_data;
> -	const struct of_device_id *match;
> -
> -	match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
> -	drv_data = match->data;
> -	return dw_mci_pltfm_register(pdev, drv_data);
> -}
> -
> -static struct platform_driver dw_mci_socfpga_pltfm_driver = {
> -	.probe		= dw_mci_socfpga_probe,
> -	.remove		= __exit_p(dw_mci_pltfm_remove),
> -	.driver		= {
> -		.name		= "dwmmc_socfpga",
> -		.of_match_table	= dw_mci_socfpga_match,
> -		.pm		= &dw_mci_pltfm_pmops,
> -	},
> -};
> -
> -module_platform_driver(dw_mci_socfpga_pltfm_driver);
> -
> -MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
> -MODULE_LICENSE("GPL v2");
> -MODULE_ALIAS("platform:dwmmc-socfpga");
> 

Re: [PATCHv9 4/4] ARM: socfpga_defconfig: enable SD/MMC support

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Enables the dw_mmc driver for SOCFPGA.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: none
> v8: none
> v7: none
> v6: none
> v5: Add dw_mmc driver into socfpga_defconfig
> v4: none
> v3: none
> v2: none
> ---
>  arch/arm/configs/socfpga_defconfig |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
> index 4e1ce21..8fff96ba 100644
> --- a/arch/arm/configs/socfpga_defconfig
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -82,3 +82,5 @@ CONFIG_DEBUG_INFO=y
>  CONFIG_ENABLE_DEFAULT_TRACERS=y
>  CONFIG_DEBUG_USER=y
>  CONFIG_XZ_DEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_DW=y
> 

[PATCHv9 4/4] ARM: socfpga_defconfig: enable SD/MMC support

[Jaehoon Chung]

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 01/10/2014 06:31 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Enables the dw_mmc driver for SOCFPGA.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> v9: none
> v8: none
> v7: none
> v6: none
> v5: Add dw_mmc driver into socfpga_defconfig
> v4: none
> v3: none
> v2: none
> ---
>  arch/arm/configs/socfpga_defconfig |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
> index 4e1ce21..8fff96ba 100644
> --- a/arch/arm/configs/socfpga_defconfig
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -82,3 +82,5 @@ CONFIG_DEBUG_INFO=y
>  CONFIG_ENABLE_DEFAULT_TRACERS=y
>  CONFIG_DEBUG_USER=y
>  CONFIG_XZ_DEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_DW=y
> 

RE: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[Seungwon Jeon]

Hi Dinh,

On Fri, January 10, 2014, Dinh Nguyen wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> The clk-phase property is used to represent the 2 clock phase values that is
> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> use the syscon driver to set sdmmc_clk's phase shift that is located in the
> system manager.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
> v9: none
> v8: Use degrees in the clk-phase binding property
> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>     prepare function to the gate clk that will toggle clock phase setting.
>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>     set the phase shift settings.
> v5: Use the "snps,dw-mshc" binding
> v4: Use the sdmmc_clk prepare function to set the phase shift settings
> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>     loaded after the clock driver.
> v2: Use the syscon driver
> ---
>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>  3 files changed, 74 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> index 0045433..5dfd145 100644
> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> @@ -23,3 +23,8 @@ Optional properties:
>          and the bit index.
>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>          and width.
> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> +	can be 0-315 degrees, in 45 degree increments.
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f936476..e776512 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -413,6 +413,7 @@
>  						compatible = "altr,socfpga-gate-clk";
>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> <&per_nand_mmc_clk>;
>  						clk-gate = <0xa0 8>;
> +						clk-phase = <0 135>;

Can clk-phase be applicable commonly for various board?
Isn't specific timing values?

Thanks,
Seungwon Jeon
>  					};
> 
>  					nand_x_clk: nand_x_clk {
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 4efcf4e..501d513 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -19,7 +19,9 @@
>  #include <linux/clkdev.h>
>  #include <linux/clk-provider.h>
>  #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/of.h>
> +#include <linux/regmap.h>
> 
>  #include "clk.h"
> 
> @@ -35,6 +37,11 @@
> 
>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
> 
> +/* SDMMC Group for System Manager defines */
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> +
>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>  {
>  	u32 l4_src;
> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  	return parent_rate / div;
>  }
> 
> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	struct regmap *sys_mgr_base_addr;
> +	int i;
> +	u32 hs_timing;
> +	u32 clk_phase[2];
> +
> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +		if (IS_ERR(sys_mgr_base_addr)) {
> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> +			return -EINVAL;
> +		}
> +
> +		for (i = 0; i < 2; i++) {
> +			switch (socfpgaclk->clk_phase[i]) {
> +			case 0:
> +				clk_phase[i] = 0;
> +				break;
> +			case 45:
> +				clk_phase[i] = 1;
> +				break;
> +			case 90:
> +				clk_phase[i] = 2;
> +				break;
> +			case 135:
> +				clk_phase[i] = 3;
> +				break;
> +			case 180:
> +				clk_phase[i] = 4;
> +				break;
> +			case 225:
> +				clk_phase[i] = 5;
> +				break;
> +			case 270:
> +				clk_phase[i] = 6;
> +				break;
> +			case 315:
> +				clk_phase[i] = 7;
> +				break;
> +			default:
> +				clk_phase[i] = 0;
> +				break;
> +			}
> +		}
> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> +			hs_timing);
> +	}
> +	return 0;
> +}
> +
>  static struct clk_ops gateclk_ops = {
> +	.prepare = socfpga_clk_prepare,
>  	.recalc_rate = socfpga_clk_recalc_rate,
>  	.get_parent = socfpga_clk_get_parent,
>  	.set_parent = socfpga_clk_set_parent,
> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  {
>  	u32 clk_gate[2];
>  	u32 div_reg[3];
> +	u32 clk_phase[2];
>  	u32 fixed_div;
>  	struct clk *clk;
>  	struct socfpga_gate_clk *socfpga_clk;
> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  		socfpga_clk->div_reg = 0;
>  	}
> 
> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> +	if (!rc) {
> +		socfpga_clk->clk_phase[0] = clk_phase[0];
> +		socfpga_clk->clk_phase[1] = clk_phase[1];
> +	}
> +
>  	of_property_read_string(node, "clock-output-names", &clk_name);
> 
>  	init.name = clk_name;
> --
> 1.7.9.5
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[Seungwon Jeon]

Hi Dinh,

On Fri, January 10, 2014, Dinh Nguyen wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> The clk-phase property is used to represent the 2 clock phase values that is
> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> use the syscon driver to set sdmmc_clk's phase shift that is located in the
> system manager.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
> v9: none
> v8: Use degrees in the clk-phase binding property
> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>     prepare function to the gate clk that will toggle clock phase setting.
>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>     set the phase shift settings.
> v5: Use the "snps,dw-mshc" binding
> v4: Use the sdmmc_clk prepare function to set the phase shift settings
> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>     loaded after the clock driver.
> v2: Use the syscon driver
> ---
>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>  3 files changed, 74 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> index 0045433..5dfd145 100644
> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> @@ -23,3 +23,8 @@ Optional properties:
>          and the bit index.
>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>          and width.
> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> +	can be 0-315 degrees, in 45 degree increments.
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f936476..e776512 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -413,6 +413,7 @@
>  						compatible = "altr,socfpga-gate-clk";
>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> <&per_nand_mmc_clk>;
>  						clk-gate = <0xa0 8>;
> +						clk-phase = <0 135>;

Can clk-phase be applicable commonly for various board?
Isn't specific timing values?

Thanks,
Seungwon Jeon
>  					};
> 
>  					nand_x_clk: nand_x_clk {
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 4efcf4e..501d513 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -19,7 +19,9 @@
>  #include <linux/clkdev.h>
>  #include <linux/clk-provider.h>
>  #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/of.h>
> +#include <linux/regmap.h>
> 
>  #include "clk.h"
> 
> @@ -35,6 +37,11 @@
> 
>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
> 
> +/* SDMMC Group for System Manager defines */
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> +
>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>  {
>  	u32 l4_src;
> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  	return parent_rate / div;
>  }
> 
> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	struct regmap *sys_mgr_base_addr;
> +	int i;
> +	u32 hs_timing;
> +	u32 clk_phase[2];
> +
> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +		if (IS_ERR(sys_mgr_base_addr)) {
> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> +			return -EINVAL;
> +		}
> +
> +		for (i = 0; i < 2; i++) {
> +			switch (socfpgaclk->clk_phase[i]) {
> +			case 0:
> +				clk_phase[i] = 0;
> +				break;
> +			case 45:
> +				clk_phase[i] = 1;
> +				break;
> +			case 90:
> +				clk_phase[i] = 2;
> +				break;
> +			case 135:
> +				clk_phase[i] = 3;
> +				break;
> +			case 180:
> +				clk_phase[i] = 4;
> +				break;
> +			case 225:
> +				clk_phase[i] = 5;
> +				break;
> +			case 270:
> +				clk_phase[i] = 6;
> +				break;
> +			case 315:
> +				clk_phase[i] = 7;
> +				break;
> +			default:
> +				clk_phase[i] = 0;
> +				break;
> +			}
> +		}
> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> +			hs_timing);
> +	}
> +	return 0;
> +}
> +
>  static struct clk_ops gateclk_ops = {
> +	.prepare = socfpga_clk_prepare,
>  	.recalc_rate = socfpga_clk_recalc_rate,
>  	.get_parent = socfpga_clk_get_parent,
>  	.set_parent = socfpga_clk_set_parent,
> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  {
>  	u32 clk_gate[2];
>  	u32 div_reg[3];
> +	u32 clk_phase[2];
>  	u32 fixed_div;
>  	struct clk *clk;
>  	struct socfpga_gate_clk *socfpga_clk;
> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  		socfpga_clk->div_reg = 0;
>  	}
> 
> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> +	if (!rc) {
> +		socfpga_clk->clk_phase[0] = clk_phase[0];
> +		socfpga_clk->clk_phase[1] = clk_phase[1];
> +	}
> +
>  	of_property_read_string(node, "clock-output-names", &clk_name);
> 
>  	init.name = clk_name;
> --
> 1.7.9.5
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[Dinh Nguyen]

Hi Seungwong,

On Fri, 2014-01-10 at 22:19 +0900, Seungwon Jeon wrote:
> Hi Dinh,
> 
> On Fri, January 10, 2014, Dinh Nguyen wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > The clk-phase property is used to represent the 2 clock phase values that is
> > needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> > use the syscon driver to set sdmmc_clk's phase shift that is located in the
> > system manager.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> > ---
> > v9: none
> > v8: Use degrees in the clk-phase binding property
> > v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
> >     prepare function to the gate clk that will toggle clock phase setting.
> >     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> > v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
> >     set the phase shift settings.
> > v5: Use the "snps,dw-mshc" binding
> > v4: Use the sdmmc_clk prepare function to set the phase shift settings
> > v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
> >     loaded after the clock driver.
> > v2: Use the syscon driver
> > ---
> >  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
> >  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
> >  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
> >  3 files changed, 74 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > index 0045433..5dfd145 100644
> > --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > @@ -23,3 +23,8 @@ Optional properties:
> >          and the bit index.
> >  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
> >          and width.
> > +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> > +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> > +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> > +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> > +	can be 0-315 degrees, in 45 degree increments.
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f936476..e776512 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -413,6 +413,7 @@
> >  						compatible = "altr,socfpga-gate-clk";
> >  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > <&per_nand_mmc_clk>;
> >  						clk-gate = <0xa0 8>;
> > +						clk-phase = <0 135>;
> 
> Can clk-phase be applicable commonly for various board?
> Isn't specific timing values?

No, the clock-phase does not change for various board. It is a
SoC-specific property.

Thanks,
Dinh
> 
> Thanks,
> Seungwon Jeon
> >  					};
> > 
> >  					nand_x_clk: nand_x_clk {
> > diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> > index 4efcf4e..501d513 100644
> > --- a/drivers/clk/socfpga/clk-gate.c
> > +++ b/drivers/clk/socfpga/clk-gate.c
> > @@ -19,7 +19,9 @@
> >  #include <linux/clkdev.h>
> >  #include <linux/clk-provider.h>
> >  #include <linux/io.h>
> > +#include <linux/mfd/syscon.h>
> >  #include <linux/of.h>
> > +#include <linux/regmap.h>
> > 
> >  #include "clk.h"
> > 
> > @@ -35,6 +37,11 @@
> > 
> >  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
> > 
> > +/* SDMMC Group for System Manager defines */
> > +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> > +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> > +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> > +
> >  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
> >  {
> >  	u32 l4_src;
> > @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> >  	return parent_rate / div;
> >  }
> > 
> > +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> > +{
> > +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> > +	struct regmap *sys_mgr_base_addr;
> > +	int i;
> > +	u32 hs_timing;
> > +	u32 clk_phase[2];
> > +
> > +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> > +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> > +		if (IS_ERR(sys_mgr_base_addr)) {
> > +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> > +			return -EINVAL;
> > +		}
> > +
> > +		for (i = 0; i < 2; i++) {
> > +			switch (socfpgaclk->clk_phase[i]) {
> > +			case 0:
> > +				clk_phase[i] = 0;
> > +				break;
> > +			case 45:
> > +				clk_phase[i] = 1;
> > +				break;
> > +			case 90:
> > +				clk_phase[i] = 2;
> > +				break;
> > +			case 135:
> > +				clk_phase[i] = 3;
> > +				break;
> > +			case 180:
> > +				clk_phase[i] = 4;
> > +				break;
> > +			case 225:
> > +				clk_phase[i] = 5;
> > +				break;
> > +			case 270:
> > +				clk_phase[i] = 6;
> > +				break;
> > +			case 315:
> > +				clk_phase[i] = 7;
> > +				break;
> > +			default:
> > +				clk_phase[i] = 0;
> > +				break;
> > +			}
> > +		}
> > +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> > +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> > +			hs_timing);
> > +	}
> > +	return 0;
> > +}
> > +
> >  static struct clk_ops gateclk_ops = {
> > +	.prepare = socfpga_clk_prepare,
> >  	.recalc_rate = socfpga_clk_recalc_rate,
> >  	.get_parent = socfpga_clk_get_parent,
> >  	.set_parent = socfpga_clk_set_parent,
> > @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
> >  {
> >  	u32 clk_gate[2];
> >  	u32 div_reg[3];
> > +	u32 clk_phase[2];
> >  	u32 fixed_div;
> >  	struct clk *clk;
> >  	struct socfpga_gate_clk *socfpga_clk;
> > @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
> >  		socfpga_clk->div_reg = 0;
> >  	}
> > 
> > +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> > +	if (!rc) {
> > +		socfpga_clk->clk_phase[0] = clk_phase[0];
> > +		socfpga_clk->clk_phase[1] = clk_phase[1];
> > +	}
> > +
> >  	of_property_read_string(node, "clock-output-names", &clk_name);
> > 
> >  	init.name = clk_name;
> > --
> > 1.7.9.5
> > 
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[Dinh Nguyen]

Hi Seungwong,

On Fri, 2014-01-10 at 22:19 +0900, Seungwon Jeon wrote:
> Hi Dinh,
> 
> On Fri, January 10, 2014, Dinh Nguyen wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > The clk-phase property is used to represent the 2 clock phase values that is
> > needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> > use the syscon driver to set sdmmc_clk's phase shift that is located in the
> > system manager.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> > ---
> > v9: none
> > v8: Use degrees in the clk-phase binding property
> > v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
> >     prepare function to the gate clk that will toggle clock phase setting.
> >     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
> > v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
> >     set the phase shift settings.
> > v5: Use the "snps,dw-mshc" binding
> > v4: Use the sdmmc_clk prepare function to set the phase shift settings
> > v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
> >     loaded after the clock driver.
> > v2: Use the syscon driver
> > ---
> >  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
> >  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
> >  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
> >  3 files changed, 74 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > index 0045433..5dfd145 100644
> > --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
> > @@ -23,3 +23,8 @@ Optional properties:
> >          and the bit index.
> >  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
> >          and width.
> > +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
> > +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
> > +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
> > +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
> > +	can be 0-315 degrees, in 45 degree increments.
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f936476..e776512 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -413,6 +413,7 @@
> >  						compatible = "altr,socfpga-gate-clk";
> >  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > <&per_nand_mmc_clk>;
> >  						clk-gate = <0xa0 8>;
> > +						clk-phase = <0 135>;
> 
> Can clk-phase be applicable commonly for various board?
> Isn't specific timing values?

No, the clock-phase does not change for various board. It is a
SoC-specific property.

Thanks,
Dinh
> 
> Thanks,
> Seungwon Jeon
> >  					};
> > 
> >  					nand_x_clk: nand_x_clk {
> > diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> > index 4efcf4e..501d513 100644
> > --- a/drivers/clk/socfpga/clk-gate.c
> > +++ b/drivers/clk/socfpga/clk-gate.c
> > @@ -19,7 +19,9 @@
> >  #include <linux/clkdev.h>
> >  #include <linux/clk-provider.h>
> >  #include <linux/io.h>
> > +#include <linux/mfd/syscon.h>
> >  #include <linux/of.h>
> > +#include <linux/regmap.h>
> > 
> >  #include "clk.h"
> > 
> > @@ -35,6 +37,11 @@
> > 
> >  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
> > 
> > +/* SDMMC Group for System Manager defines */
> > +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
> > +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> > +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
> > +
> >  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
> >  {
> >  	u32 l4_src;
> > @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> >  	return parent_rate / div;
> >  }
> > 
> > +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> > +{
> > +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> > +	struct regmap *sys_mgr_base_addr;
> > +	int i;
> > +	u32 hs_timing;
> > +	u32 clk_phase[2];
> > +
> > +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> > +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> > +		if (IS_ERR(sys_mgr_base_addr)) {
> > +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> > +			return -EINVAL;
> > +		}
> > +
> > +		for (i = 0; i < 2; i++) {
> > +			switch (socfpgaclk->clk_phase[i]) {
> > +			case 0:
> > +				clk_phase[i] = 0;
> > +				break;
> > +			case 45:
> > +				clk_phase[i] = 1;
> > +				break;
> > +			case 90:
> > +				clk_phase[i] = 2;
> > +				break;
> > +			case 135:
> > +				clk_phase[i] = 3;
> > +				break;
> > +			case 180:
> > +				clk_phase[i] = 4;
> > +				break;
> > +			case 225:
> > +				clk_phase[i] = 5;
> > +				break;
> > +			case 270:
> > +				clk_phase[i] = 6;
> > +				break;
> > +			case 315:
> > +				clk_phase[i] = 7;
> > +				break;
> > +			default:
> > +				clk_phase[i] = 0;
> > +				break;
> > +			}
> > +		}
> > +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> > +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> > +			hs_timing);
> > +	}
> > +	return 0;
> > +}
> > +
> >  static struct clk_ops gateclk_ops = {
> > +	.prepare = socfpga_clk_prepare,
> >  	.recalc_rate = socfpga_clk_recalc_rate,
> >  	.get_parent = socfpga_clk_get_parent,
> >  	.set_parent = socfpga_clk_set_parent,
> > @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
> >  {
> >  	u32 clk_gate[2];
> >  	u32 div_reg[3];
> > +	u32 clk_phase[2];
> >  	u32 fixed_div;
> >  	struct clk *clk;
> >  	struct socfpga_gate_clk *socfpga_clk;
> > @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
> >  		socfpga_clk->div_reg = 0;
> >  	}
> > 
> > +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> > +	if (!rc) {
> > +		socfpga_clk->clk_phase[0] = clk_phase[0];
> > +		socfpga_clk->clk_phase[1] = clk_phase[1];
> > +	}
> > +
> >  	of_property_read_string(node, "clock-output-names", &clk_name);
> > 
> >  	init.name = clk_name;
> > --
> > 1.7.9.5
> > 
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Arnd Bergmann]

On Friday 10 January 2014, Dinh Nguyen wrote:
> > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > > index f936476..e776512 100644
> > > --- a/arch/arm/boot/dts/socfpga.dtsi
> > > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > > @@ -413,6 +413,7 @@
> > >                                             compatible = "altr,socfpga-gate-clk";
> > >                                             clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > > <&per_nand_mmc_clk>;
> > >                                             clk-gate = <0xa0 8>;
> > > +                                           clk-phase = <0 135>;
> > 
> > Can clk-phase be applicable commonly for various board?
> > Isn't specific timing values?
> 
> No, the clock-phase does not change for various board. It is a
> SoC-specific property.

I'm curious about this: If the setting is fixed per soc, why is it even
configurable, rather than hardwired to the correct setting, or set up
by the boot loader?

	Arnd

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Arnd Bergmann]

On Friday 10 January 2014, Dinh Nguyen wrote:
> > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > > index f936476..e776512 100644
> > > --- a/arch/arm/boot/dts/socfpga.dtsi
> > > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > > @@ -413,6 +413,7 @@
> > >                                             compatible = "altr,socfpga-gate-clk";
> > >                                             clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
> > > <&per_nand_mmc_clk>;
> > >                                             clk-gate = <0xa0 8>;
> > > +                                           clk-phase = <0 135>;
> > 
> > Can clk-phase be applicable commonly for various board?
> > Isn't specific timing values?
> 
> No, the clock-phase does not change for various board. It is a
> SoC-specific property.

I'm curious about this: If the setting is fixed per soc, why is it even
configurable, rather than hardwired to the correct setting, or set up
by the boot loader?

	Arnd

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

[Dinh Nguyen]

Hi Arnd,

On 1/10/14 1:00 PM, Arnd Bergmann wrote:
> On Friday 10 January 2014, Dinh Nguyen wrote:
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>>> index f936476..e776512 100644
>>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>> @@ -413,6 +413,7 @@
>>>>                                             compatible = "altr,socfpga-gate-clk";
>>>>                                             clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
>>>> <&per_nand_mmc_clk>;
>>>>                                             clk-gate = <0xa0 8>;
>>>> +                                           clk-phase = <0 135>;
>>> Can clk-phase be applicable commonly for various board?
>>> Isn't specific timing values?
>> No, the clock-phase does not change for various board. It is a
>> SoC-specific property.
> I'm curious about this: If the setting is fixed per soc, why is it even
> configurable, rather than hardwired to the correct setting, or set up
> by the boot loader?
Yes, I guess it can be hardwired, but currently it is not and the values
all default
to 0. The bootloader does set it up, but only when the system is booting
from
the SD/MMC source. When booting from other flash medium(i.e. NAND,
QSPI), these SD/MMC settings are not set, so they must be set by the OS
if SD/MMC is to work correctly.

Dinh
>
> 	Arnd

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Dinh Nguyen]

Hi Arnd,

On 1/10/14 1:00 PM, Arnd Bergmann wrote:
> On Friday 10 January 2014, Dinh Nguyen wrote:
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>>> index f936476..e776512 100644
>>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>> @@ -413,6 +413,7 @@
>>>>                                             compatible = "altr,socfpga-gate-clk";
>>>>                                             clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,
>>>> <&per_nand_mmc_clk>;
>>>>                                             clk-gate = <0xa0 8>;
>>>> +                                           clk-phase = <0 135>;
>>> Can clk-phase be applicable commonly for various board?
>>> Isn't specific timing values?
>> No, the clock-phase does not change for various board. It is a
>> SoC-specific property.
> I'm curious about this: If the setting is fixed per soc, why is it even
> configurable, rather than hardwired to the correct setting, or set up
> by the boot loader?
Yes, I guess it can be hardwired, but currently it is not and the values
all default
to 0. The bootloader does set it up, but only when the system is booting
from
the SD/MMC source. When booting from other flash medium(i.e. NAND,
QSPI), these SD/MMC settings are not set, so they must be set by the OS
if SD/MMC is to work correctly.

Dinh
>
> 	Arnd

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Dinh Nguyen]

Hi Mike,

On 1/9/14 9:47 PM, Jaehoon Chung wrote:
> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
>
> On 01/10/2014 06:31 AM, dinguyen@altera.com wrote:
>> From: Dinh Nguyen <dinguyen@altera.com>
>>
>> The clk-phase property is used to represent the 2 clock phase values that is
>> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
>> use the syscon driver to set sdmmc_clk's phase shift that is located in the
>> system manager.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
>> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
>> ---
>> v9: none
>> v8: Use degrees in the clk-phase binding property
>> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>>     prepare function to the gate clk that will toggle clock phase setting.
>>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
>> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>>     set the phase shift settings.
>> v5: Use the "snps,dw-mshc" binding
>> v4: Use the sdmmc_clk prepare function to set the phase shift settings
>> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>>     loaded after the clock driver.
>> v2: Use the syscon driver
>> ---
>>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>>  3 files changed, 74 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> index 0045433..5dfd145 100644
>> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> @@ -23,3 +23,8 @@ Optional properties:
>>          and the bit index.
>>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>>          and width.
>> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
>> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
>> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
>> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
>> +	can be 0-315 degrees, in 45 degree increments.
>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>> index f936476..e776512 100644
>> --- a/arch/arm/boot/dts/socfpga.dtsi
>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>> @@ -413,6 +413,7 @@
>>  						compatible = "altr,socfpga-gate-clk";
>>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
>>  						clk-gate = <0xa0 8>;
>> +						clk-phase = <0 135>;
>>  					};
>>  
>>  					nand_x_clk: nand_x_clk {
>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
>> index 4efcf4e..501d513 100644
>> --- a/drivers/clk/socfpga/clk-gate.c
>> +++ b/drivers/clk/socfpga/clk-gate.c
>> @@ -19,7 +19,9 @@
>>  #include <linux/clkdev.h>
>>  #include <linux/clk-provider.h>
>>  #include <linux/io.h>
>> +#include <linux/mfd/syscon.h>
>>  #include <linux/of.h>
>> +#include <linux/regmap.h>
>>  
>>  #include "clk.h"
>>  
>> @@ -35,6 +37,11 @@
>>  
>>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
>>  
>> +/* SDMMC Group for System Manager defines */
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
>> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
>> +
>>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>>  {
>>  	u32 l4_src;
>> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>>  	return parent_rate / div;
>>  }
>>  
>> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
>> +{
>> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
>> +	struct regmap *sys_mgr_base_addr;
>> +	int i;
>> +	u32 hs_timing;
>> +	u32 clk_phase[2];
>> +
>> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
>> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> +		if (IS_ERR(sys_mgr_base_addr)) {
>> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
>> +			return -EINVAL;
>> +		}
>> +
>> +		for (i = 0; i < 2; i++) {
>> +			switch (socfpgaclk->clk_phase[i]) {
>> +			case 0:
>> +				clk_phase[i] = 0;
>> +				break;
>> +			case 45:
>> +				clk_phase[i] = 1;
>> +				break;
>> +			case 90:
>> +				clk_phase[i] = 2;
>> +				break;
>> +			case 135:
>> +				clk_phase[i] = 3;
>> +				break;
>> +			case 180:
>> +				clk_phase[i] = 4;
>> +				break;
>> +			case 225:
>> +				clk_phase[i] = 5;
>> +				break;
>> +			case 270:
>> +				clk_phase[i] = 6;
>> +				break;
>> +			case 315:
>> +				clk_phase[i] = 7;
>> +				break;
>> +			default:
>> +				clk_phase[i] = 0;
>> +				break;
>> +			}
>> +		}
>> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
>> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
>> +			hs_timing);
>> +	}
>> +	return 0;
>> +}
>> +
>>  static struct clk_ops gateclk_ops = {
>> +	.prepare = socfpga_clk_prepare,
>>  	.recalc_rate = socfpga_clk_recalc_rate,
>>  	.get_parent = socfpga_clk_get_parent,
>>  	.set_parent = socfpga_clk_set_parent,
>> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>>  {
>>  	u32 clk_gate[2];
>>  	u32 div_reg[3];
>> +	u32 clk_phase[2];
>>  	u32 fixed_div;
>>  	struct clk *clk;
>>  	struct socfpga_gate_clk *socfpga_clk;
>> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>>  		socfpga_clk->div_reg = 0;
>>  	}
>>  
>> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
>> +	if (!rc) {
>> +		socfpga_clk->clk_phase[0] = clk_phase[0];
>> +		socfpga_clk->clk_phase[1] = clk_phase[1];
>> +	}
>> +
>>  	of_property_read_string(node, "clock-output-names", &clk_name);
>>  
>>  	init.name = clk_name;
>>
Can you apply this to your clk tree?

Thanks,
Dinh

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Dinh Nguyen]

Hi Mike,

On 1/9/14 9:47 PM, Jaehoon Chung wrote:
> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
>
> On 01/10/2014 06:31 AM, dinguyen at altera.com wrote:
>> From: Dinh Nguyen <dinguyen@altera.com>
>>
>> The clk-phase property is used to represent the 2 clock phase values that is
>> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
>> use the syscon driver to set sdmmc_clk's phase shift that is located in the
>> system manager.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
>> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
>> ---
>> v9: none
>> v8: Use degrees in the clk-phase binding property
>> v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
>>     prepare function to the gate clk that will toggle clock phase setting.
>>     Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
>> v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
>>     set the phase shift settings.
>> v5: Use the "snps,dw-mshc" binding
>> v4: Use the sdmmc_clk prepare function to set the phase shift settings
>> v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
>>     loaded after the clock driver.
>> v2: Use the syscon driver
>> ---
>>  .../devicetree/bindings/clock/altr_socfpga.txt     |    5 ++
>>  arch/arm/boot/dts/socfpga.dtsi                     |    1 +
>>  drivers/clk/socfpga/clk-gate.c                     |   68 ++++++++++++++++++++
>>  3 files changed, 74 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> index 0045433..5dfd145 100644
>> --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
>> @@ -23,3 +23,8 @@ Optional properties:
>>          and the bit index.
>>  - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
>>          and width.
>> +- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
>> +	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
>> +	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
>> +	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
>> +	can be 0-315 degrees, in 45 degree increments.
>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>> index f936476..e776512 100644
>> --- a/arch/arm/boot/dts/socfpga.dtsi
>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>> @@ -413,6 +413,7 @@
>>  						compatible = "altr,socfpga-gate-clk";
>>  						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
>>  						clk-gate = <0xa0 8>;
>> +						clk-phase = <0 135>;
>>  					};
>>  
>>  					nand_x_clk: nand_x_clk {
>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
>> index 4efcf4e..501d513 100644
>> --- a/drivers/clk/socfpga/clk-gate.c
>> +++ b/drivers/clk/socfpga/clk-gate.c
>> @@ -19,7 +19,9 @@
>>  #include <linux/clkdev.h>
>>  #include <linux/clk-provider.h>
>>  #include <linux/io.h>
>> +#include <linux/mfd/syscon.h>
>>  #include <linux/of.h>
>> +#include <linux/regmap.h>
>>  
>>  #include "clk.h"
>>  
>> @@ -35,6 +37,11 @@
>>  
>>  #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
>>  
>> +/* SDMMC Group for System Manager defines */
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
>> +	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
>> +
>>  static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
>>  {
>>  	u32 l4_src;
>> @@ -115,7 +122,61 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>>  	return parent_rate / div;
>>  }
>>  
>> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
>> +{
>> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
>> +	struct regmap *sys_mgr_base_addr;
>> +	int i;
>> +	u32 hs_timing;
>> +	u32 clk_phase[2];
>> +
>> +	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
>> +		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> +		if (IS_ERR(sys_mgr_base_addr)) {
>> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
>> +			return -EINVAL;
>> +		}
>> +
>> +		for (i = 0; i < 2; i++) {
>> +			switch (socfpgaclk->clk_phase[i]) {
>> +			case 0:
>> +				clk_phase[i] = 0;
>> +				break;
>> +			case 45:
>> +				clk_phase[i] = 1;
>> +				break;
>> +			case 90:
>> +				clk_phase[i] = 2;
>> +				break;
>> +			case 135:
>> +				clk_phase[i] = 3;
>> +				break;
>> +			case 180:
>> +				clk_phase[i] = 4;
>> +				break;
>> +			case 225:
>> +				clk_phase[i] = 5;
>> +				break;
>> +			case 270:
>> +				clk_phase[i] = 6;
>> +				break;
>> +			case 315:
>> +				clk_phase[i] = 7;
>> +				break;
>> +			default:
>> +				clk_phase[i] = 0;
>> +				break;
>> +			}
>> +		}
>> +		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
>> +		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
>> +			hs_timing);
>> +	}
>> +	return 0;
>> +}
>> +
>>  static struct clk_ops gateclk_ops = {
>> +	.prepare = socfpga_clk_prepare,
>>  	.recalc_rate = socfpga_clk_recalc_rate,
>>  	.get_parent = socfpga_clk_get_parent,
>>  	.set_parent = socfpga_clk_set_parent,
>> @@ -126,6 +187,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
>>  {
>>  	u32 clk_gate[2];
>>  	u32 div_reg[3];
>> +	u32 clk_phase[2];
>>  	u32 fixed_div;
>>  	struct clk *clk;
>>  	struct socfpga_gate_clk *socfpga_clk;
>> @@ -166,6 +228,12 @@ static void __init __socfpga_gate_init(struct device_node *node,
>>  		socfpga_clk->div_reg = 0;
>>  	}
>>  
>> +	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
>> +	if (!rc) {
>> +		socfpga_clk->clk_phase[0] = clk_phase[0];
>> +		socfpga_clk->clk_phase[1] = clk_phase[1];
>> +	}
>> +
>>  	of_property_read_string(node, "clock-output-names", &clk_name);
>>  
>>  	init.name = clk_name;
>>
Can you apply this to your clk tree?

Thanks,
Dinh

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Mike Turquette]

Quoting Dinh Nguyen (2014-01-15 04:36:52)
> Hi Mike,
> 
> Can you apply this to your clk tree?

The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
3.14-rc1?

Thanks,
Mike

> 
> Thanks,
> Dinh
> 

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Mike Turquette]

Quoting Dinh Nguyen (2014-01-15 04:36:52)
> Hi Mike,
> 
> Can you apply this to your clk tree?

The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
3.14-rc1?

Thanks,
Mike

> 
> Thanks,
> Dinh
> 

Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Dinh Nguyen]

On Wed, 2014-02-05 at 08:03 -0800, Mike Turquette wrote:
> Quoting Dinh Nguyen (2014-01-15 04:36:52)
> > Hi Mike,
> > 
> > Can you apply this to your clk tree?
> 
> The patch looks good to me, but I think it depends on your pending pull
> request. Can you add this to that pull request and rebase it to
> 3.14-rc1?

Yes, I will send an updated pull request shortly.

Thanks,
Dinh
> 
> Thanks,
> Mike
> 
> > 
> > Thanks,
> > Dinh
> > 
> 

[PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"

[Dinh Nguyen]

On Wed, 2014-02-05 at 08:03 -0800, Mike Turquette wrote:
> Quoting Dinh Nguyen (2014-01-15 04:36:52)
> > Hi Mike,
> > 
> > Can you apply this to your clk tree?
> 
> The patch looks good to me, but I think it depends on your pending pull
> request. Can you add this to that pull request and rebase it to
> 3.14-rc1?

Yes, I will send an updated pull request shortly.

Thanks,
Dinh
> 
> Thanks,
> Mike
> 
> > 
> > Thanks,
> > Dinh
> > 
>