* [PATCH v9 0/4] ata: Add APM X-Gene SoC SATA host controller support
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
This patch adds support for the APM X-Gene SoC SATA host controller. In
order for the host controller to work, the corresponding PHY driver
musts also be available.
v9:
* Remove ACPI/EFI include files
* Remove the IO flush support, interrupt routine, and DTS resources
* Remove function xgene_rd, xgene_wr, and xgene_wr_flush
* Remove PMP support (function xgene_ahci_qc_issue, xgene_ahci_qc_prep,
xgene_ahci_qc_fill_rtf, xgene_ahci_softreset, and xgene_ahci_do_softreset)
* Rename function xgene_ahci_enable_phy to xgene_ahci_force_phy_rdy
* Clean up hardreset functions
* Require v7 of the PHY driver
v8:
* Remove _ADDR from defines
* Remove define MSTAWAUX_COHERENT_BYPASS_SET and
STARAUX_COHERENT_BYPASS_SET and use direct coding
* Remove the un-necessary check for DTS boot with built in ACPI table
* Switch to use dma_set_mask_and_coherent for setting DMA mask
* Remove ACPI table matching code
* Update clock-names for sata01clk, sata23clk, and sata45clk
v7:
* Update the clock code by toggle the clock
* Update the DTS clock mask values due to the clock spilt between host and
v5 of the PHY drivers
v6:
* Update binding documentation
* Change select PHY_XGENE_SATA to PHY_XGENE
* Add ULL to constants
* Change indentation and comments
* Clean up the probe functions a bit more
* Remove xgene_ahci_remove function
* Add the flush register to DTS
* Remove the interrupt-parent from DTS
v5:
* Sync up to v3 of the PHY driver
* Remove MSLIM wrapper functions
* Change the memory shutdown loop to use usleep_range
* Use devm_ioremap_resource instead devm_ioremap
* Remove suspend/resume functions as not needed
v4:
* Remove the ID property in DT
* Remove the temporary PHY direct function call and use PHY function
* Change printk to pr_debug
* Move the IOB flush addresses into the DT
* Remove the parameters retrieval function as no longer needed
* Remove the header file as no longer needed
* Require v2 patch of the SATA PHY driver. Require slightly modification
in the Kconfig as it is moved to folder driver/phy and use Kconfig
PHY_XGENE_SATA instead SATA_XGENE_PHY.
v3:
* Move out the SATA PHY to another driver
* Remove the clock-cells entry from DTS
* Remove debug wrapper
* Remove delay functions wrapper
* Clean up resource and IRQ query
* Remove query clock name
* Switch to use dma_set_mask/dma_coherent_mask
* Remove un-necessary devm_kfree
* Update GPL license header to v2
* Spilt up function xgene_ahci_hardreset
* Spilt up function xgene_ahci_probe
* Remove all reference of CONFIG_ARCH_MSLIM
* Clean up chip revision code
v2:
* Clean up file sata_xgene.c with Lindent and etc
* Clean up file sata_xgene_serdes.c with Lindent and etc
* Add description to each patch
v1:
* inital version
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Loc Ho (4):
ata: Export required functions by APM X-Gene SATA driver
Documentation: Add documentation for APM X-Gene SoC SATA host
controller DTS binding
ata: Add APM X-Gene SoC SATA host controller driver
arm64: Add APM X-Gene SoC SATA host controller DTS entries
.../devicetree/bindings/ata/apm-xgene.txt | 68 +++
arch/arm64/boot/dts/apm-storm.dtsi | 75 +++
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.h | 9 +
drivers/ata/libahci.c | 16 +-
drivers/ata/sata_xgene.c | 630 ++++++++++++++++++++
7 files changed, 801 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
create mode 100644 drivers/ata/sata_xgene.c
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 0/4] ata: Add APM X-Gene SoC SATA host controller support
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for the APM X-Gene SoC SATA host controller. In
order for the host controller to work, the corresponding PHY driver
musts also be available.
v9:
* Remove ACPI/EFI include files
* Remove the IO flush support, interrupt routine, and DTS resources
* Remove function xgene_rd, xgene_wr, and xgene_wr_flush
* Remove PMP support (function xgene_ahci_qc_issue, xgene_ahci_qc_prep,
xgene_ahci_qc_fill_rtf, xgene_ahci_softreset, and xgene_ahci_do_softreset)
* Rename function xgene_ahci_enable_phy to xgene_ahci_force_phy_rdy
* Clean up hardreset functions
* Require v7 of the PHY driver
v8:
* Remove _ADDR from defines
* Remove define MSTAWAUX_COHERENT_BYPASS_SET and
STARAUX_COHERENT_BYPASS_SET and use direct coding
* Remove the un-necessary check for DTS boot with built in ACPI table
* Switch to use dma_set_mask_and_coherent for setting DMA mask
* Remove ACPI table matching code
* Update clock-names for sata01clk, sata23clk, and sata45clk
v7:
* Update the clock code by toggle the clock
* Update the DTS clock mask values due to the clock spilt between host and
v5 of the PHY drivers
v6:
* Update binding documentation
* Change select PHY_XGENE_SATA to PHY_XGENE
* Add ULL to constants
* Change indentation and comments
* Clean up the probe functions a bit more
* Remove xgene_ahci_remove function
* Add the flush register to DTS
* Remove the interrupt-parent from DTS
v5:
* Sync up to v3 of the PHY driver
* Remove MSLIM wrapper functions
* Change the memory shutdown loop to use usleep_range
* Use devm_ioremap_resource instead devm_ioremap
* Remove suspend/resume functions as not needed
v4:
* Remove the ID property in DT
* Remove the temporary PHY direct function call and use PHY function
* Change printk to pr_debug
* Move the IOB flush addresses into the DT
* Remove the parameters retrieval function as no longer needed
* Remove the header file as no longer needed
* Require v2 patch of the SATA PHY driver. Require slightly modification
in the Kconfig as it is moved to folder driver/phy and use Kconfig
PHY_XGENE_SATA instead SATA_XGENE_PHY.
v3:
* Move out the SATA PHY to another driver
* Remove the clock-cells entry from DTS
* Remove debug wrapper
* Remove delay functions wrapper
* Clean up resource and IRQ query
* Remove query clock name
* Switch to use dma_set_mask/dma_coherent_mask
* Remove un-necessary devm_kfree
* Update GPL license header to v2
* Spilt up function xgene_ahci_hardreset
* Spilt up function xgene_ahci_probe
* Remove all reference of CONFIG_ARCH_MSLIM
* Clean up chip revision code
v2:
* Clean up file sata_xgene.c with Lindent and etc
* Clean up file sata_xgene_serdes.c with Lindent and etc
* Add description to each patch
v1:
* inital version
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Loc Ho (4):
ata: Export required functions by APM X-Gene SATA driver
Documentation: Add documentation for APM X-Gene SoC SATA host
controller DTS binding
ata: Add APM X-Gene SoC SATA host controller driver
arm64: Add APM X-Gene SoC SATA host controller DTS entries
.../devicetree/bindings/ata/apm-xgene.txt | 68 +++
arch/arm64/boot/dts/apm-storm.dtsi | 75 +++
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.h | 9 +
drivers/ata/libahci.c | 16 +-
drivers/ata/sata_xgene.c | 630 ++++++++++++++++++++
7 files changed, 801 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
create mode 100644 drivers/ata/sata_xgene.c
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 1/4] ata: Export required functions by APM X-Gene SATA driver
2014-01-15 7:11 ` Loc Ho
@ 2014-01-15 7:11 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
This patch exports functions required by APM X-Gene SoC SATA host
controller driver to avoid duplication of code.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
drivers/ata/ahci.h | 9 +++++++++
drivers/ata/libahci.c | 16 ++++++++++------
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 2289efd..8163b59 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -370,6 +370,15 @@ irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
void ahci_print_info(struct ata_host *host, const char *scc_s);
int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
void ahci_error_handler(struct ata_port *ap);
+void ahci_sw_activity(struct ata_link *link);
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat);
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+ struct ata_taskfile *tf, int is_cmd, u16 flags,
+ unsigned long timeout_msec);
+void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+ u32 opts);
+unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
static inline void __iomem *__ahci_port_base(struct ata_host *host,
unsigned int port_no)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index c482f8c..1d24bf5 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -68,7 +68,6 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
static int ahci_port_start(struct ata_port *ap);
@@ -553,7 +552,7 @@ static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
return -EINVAL;
}
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
void __iomem *port_mmio = ahci_port_base(link->ap);
int offset = ahci_scr_offset(link->ap, sc_reg);
@@ -564,6 +563,7 @@ static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
}
return -EINVAL;
}
+EXPORT_SYMBOL_GPL(ahci_scr_write);
void ahci_start_engine(struct ata_port *ap)
{
@@ -869,7 +869,7 @@ int ahci_reset_controller(struct ata_host *host)
}
EXPORT_SYMBOL_GPL(ahci_reset_controller);
-static void ahci_sw_activity(struct ata_link *link)
+void ahci_sw_activity(struct ata_link *link)
{
struct ata_port *ap = link->ap;
struct ahci_port_priv *pp = ap->private_data;
@@ -882,6 +882,7 @@ static void ahci_sw_activity(struct ata_link *link)
if (!timer_pending(&emp->timer))
mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
}
+EXPORT_SYMBOL_GPL(ahci_sw_activity);
static void ahci_sw_activity_blink(unsigned long arg)
{
@@ -1239,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
}
EXPORT_SYMBOL_GPL(ahci_kick_engine);
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
struct ata_taskfile *tf, int is_cmd, u16 flags,
unsigned long timeout_msec)
{
@@ -1268,6 +1269,7 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
return 0;
}
+EXPORT_SYMBOL_GPL(ahci_exec_polled_cmd);
int ahci_do_softreset(struct ata_link *link, unsigned int *class,
int pmp, unsigned long deadline,
@@ -1472,7 +1474,7 @@ static void ahci_postreset(struct ata_link *link, unsigned int *class)
}
}
-static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
+unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
{
struct scatterlist *sg;
struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
@@ -1494,6 +1496,7 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
return si;
}
+EXPORT_SYMBOL_GPL(ahci_fill_sg);
static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
{
@@ -1568,7 +1571,7 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
dev_err(ap->host->dev, "failed to clear device error\n");
}
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
{
struct ahci_host_priv *hpriv = ap->host->private_data;
struct ahci_port_priv *pp = ap->private_data;
@@ -1678,6 +1681,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
} else
ata_port_abort(ap);
}
+EXPORT_SYMBOL_GPL(ahci_error_intr);
static void ahci_handle_port_interrupt(struct ata_port *ap,
void __iomem *port_mmio, u32 status)
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 1/4] ata: Export required functions by APM X-Gene SATA driver
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch exports functions required by APM X-Gene SoC SATA host
controller driver to avoid duplication of code.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
drivers/ata/ahci.h | 9 +++++++++
drivers/ata/libahci.c | 16 ++++++++++------
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 2289efd..8163b59 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -370,6 +370,15 @@ irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
void ahci_print_info(struct ata_host *host, const char *scc_s);
int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
void ahci_error_handler(struct ata_port *ap);
+void ahci_sw_activity(struct ata_link *link);
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat);
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+ struct ata_taskfile *tf, int is_cmd, u16 flags,
+ unsigned long timeout_msec);
+void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+ u32 opts);
+unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
static inline void __iomem *__ahci_port_base(struct ata_host *host,
unsigned int port_no)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index c482f8c..1d24bf5 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -68,7 +68,6 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
static int ahci_port_start(struct ata_port *ap);
@@ -553,7 +552,7 @@ static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
return -EINVAL;
}
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
void __iomem *port_mmio = ahci_port_base(link->ap);
int offset = ahci_scr_offset(link->ap, sc_reg);
@@ -564,6 +563,7 @@ static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
}
return -EINVAL;
}
+EXPORT_SYMBOL_GPL(ahci_scr_write);
void ahci_start_engine(struct ata_port *ap)
{
@@ -869,7 +869,7 @@ int ahci_reset_controller(struct ata_host *host)
}
EXPORT_SYMBOL_GPL(ahci_reset_controller);
-static void ahci_sw_activity(struct ata_link *link)
+void ahci_sw_activity(struct ata_link *link)
{
struct ata_port *ap = link->ap;
struct ahci_port_priv *pp = ap->private_data;
@@ -882,6 +882,7 @@ static void ahci_sw_activity(struct ata_link *link)
if (!timer_pending(&emp->timer))
mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
}
+EXPORT_SYMBOL_GPL(ahci_sw_activity);
static void ahci_sw_activity_blink(unsigned long arg)
{
@@ -1239,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
}
EXPORT_SYMBOL_GPL(ahci_kick_engine);
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
struct ata_taskfile *tf, int is_cmd, u16 flags,
unsigned long timeout_msec)
{
@@ -1268,6 +1269,7 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
return 0;
}
+EXPORT_SYMBOL_GPL(ahci_exec_polled_cmd);
int ahci_do_softreset(struct ata_link *link, unsigned int *class,
int pmp, unsigned long deadline,
@@ -1472,7 +1474,7 @@ static void ahci_postreset(struct ata_link *link, unsigned int *class)
}
}
-static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
+unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
{
struct scatterlist *sg;
struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
@@ -1494,6 +1496,7 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
return si;
}
+EXPORT_SYMBOL_GPL(ahci_fill_sg);
static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
{
@@ -1568,7 +1571,7 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
dev_err(ap->host->dev, "failed to clear device error\n");
}
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
{
struct ahci_host_priv *hpriv = ap->host->private_data;
struct ahci_port_priv *pp = ap->private_data;
@@ -1678,6 +1681,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
} else
ata_port_abort(ap);
}
+EXPORT_SYMBOL_GPL(ahci_error_intr);
static void ahci_handle_port_interrupt(struct ata_port *ap,
void __iomem *port_mmio, u32 status)
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 7:11 ` Loc Ho
@ 2014-01-15 7:11 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
.../devicetree/bindings/ata/apm-xgene.txt | 68 ++++++++++++++++++++
1 files changed, 68 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644
index 0000000..3d1421a
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,68 @@
+* APM X-Gene 6.0 Gb/s SATA host controller nodes
+
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible : Shall be "apm,xgene-ahci-sgmii" if mux'ed with SGMII
+ or "apm,xgene-ahci-pcie" if mux'ed with PCIe.
+- reg : First memory resource shall be the AHCI memory
+ resource.
+ Second memory resource shall be the host controller
+ memory resource.
+- interrupts : Interrupt mapping for SATA host controller IRQ.
+- clocks : Reference to the clock entry.
+- phys : PHY reference with parameter 0.
+- phy-names : Name of the PHY. Shall be "sata-6g".
+
+Optional properties:
+- status : Shall be "ok" if enabled or "disabled" if disabled.
+ Default is "ok".
+- interrupt-parent : Interrupt controller.
+
+Example:
+ sataclk: sataclk {
+ compatible = "fixed-clock";
+ #clock-cells = <1>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sataclk";
+ };
+
+ phy2: phy@1f22a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f22a000 0x0 0x100>,
+ <0x0 0x1f22c000 0x0 0x100>;
+ #phy-cells = <1>;
+ };
+
+ phy3: phy@1f23a000 {
+ compatible = "apm,xgene-phy-ext";
+ reg = <0x0 0x1f23a000 0x0 0x100>,
+ <0x0 0x1f23c000 0x0 0x100>,
+ <0x0 0x1f2d0000 0x0 0x100>;
+ #phy-cells = <1>;
+ };
+
+ sata2: sata@1a400000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a400000 0x0 0x1000>,
+ <0x0 0x1f220000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0x0 0x87 0x4>;
+ status = "ok";
+ clocks = <&sataclk 0>;
+ phys = <&phy2 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata3: sata@1a800000 {
+ compatible = "apm,xgene-ahci-pcie";
+ reg = <0x0 0x1a800000 0x0 0x1000>,
+ <0x0 0x1f230000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0x0 0x88 0x4>;
+ status = "ok";
+ clocks = <&sataclk 0>;
+ phys = <&phy3 0>;
+ phy-names = "sata-6g";
+ };
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
.../devicetree/bindings/ata/apm-xgene.txt | 68 ++++++++++++++++++++
1 files changed, 68 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644
index 0000000..3d1421a
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,68 @@
+* APM X-Gene 6.0 Gb/s SATA host controller nodes
+
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible : Shall be "apm,xgene-ahci-sgmii" if mux'ed with SGMII
+ or "apm,xgene-ahci-pcie" if mux'ed with PCIe.
+- reg : First memory resource shall be the AHCI memory
+ resource.
+ Second memory resource shall be the host controller
+ memory resource.
+- interrupts : Interrupt mapping for SATA host controller IRQ.
+- clocks : Reference to the clock entry.
+- phys : PHY reference with parameter 0.
+- phy-names : Name of the PHY. Shall be "sata-6g".
+
+Optional properties:
+- status : Shall be "ok" if enabled or "disabled" if disabled.
+ Default is "ok".
+- interrupt-parent : Interrupt controller.
+
+Example:
+ sataclk: sataclk {
+ compatible = "fixed-clock";
+ #clock-cells = <1>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sataclk";
+ };
+
+ phy2: phy at 1f22a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f22a000 0x0 0x100>,
+ <0x0 0x1f22c000 0x0 0x100>;
+ #phy-cells = <1>;
+ };
+
+ phy3: phy at 1f23a000 {
+ compatible = "apm,xgene-phy-ext";
+ reg = <0x0 0x1f23a000 0x0 0x100>,
+ <0x0 0x1f23c000 0x0 0x100>,
+ <0x0 0x1f2d0000 0x0 0x100>;
+ #phy-cells = <1>;
+ };
+
+ sata2: sata at 1a400000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a400000 0x0 0x1000>,
+ <0x0 0x1f220000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0x0 0x87 0x4>;
+ status = "ok";
+ clocks = <&sataclk 0>;
+ phys = <&phy2 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata3: sata at 1a800000 {
+ compatible = "apm,xgene-ahci-pcie";
+ reg = <0x0 0x1a800000 0x0 0x1000>,
+ <0x0 0x1f230000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0x0 0x88 0x4>;
+ status = "ok";
+ clocks = <&sataclk 0>;
+ phys = <&phy3 0>;
+ phy-names = "sata-6g";
+ };
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 3/4] ata: Add APM X-Gene SoC SATA host controller driver
2014-01-15 7:11 ` Loc Ho
@ 2014-01-15 7:11 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
This patch adds support for the APM X-Gene SoC SATA host controller driver.
It requires the corresponding APM X-Gene SoC PHY driver.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/sata_xgene.c | 630 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 639 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_xgene.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4e73772..cd1bc3c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -106,6 +106,14 @@ config AHCI_IMX
If unsure, say N.
+config SATA_XGENE
+ tristate "APM X-Gene 6.0Gbps SATA host controller support"
+ depends on ARM64 || COMPILE_TEST
+ select SATA_AHCI_PLATFORM
+ select PHY_XGENE
+ help
+ This option enables support for APM X-Gene SoC SATA host controller.
+
config SATA_FSL
tristate "Freescale 3.0Gbps SATA support"
depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 46518c6..1c0fabe 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
+obj-$(CONFIG_SATA_XGENE) += sata_xgene.o
# SFF w/ custom DMA
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
diff --git a/drivers/ata/sata_xgene.c b/drivers/ata/sata_xgene.c
new file mode 100644
index 0000000..2e9da35
--- /dev/null
+++ b/drivers/ata/sata_xgene.c
@@ -0,0 +1,630 @@
+/*
+ * AppliedMicro X-Gene SoC SATA Host Controller Driver
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho <lho@apm.com>
+ * Tuan Phan <tphan@apm.com>
+ * Suman Tripathi <stripathi@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/phy/phy.h>
+#include "ahci.h"
+
+/* Controller who PHY shared with SGMII Ethernet PHY */
+#define XGENE_AHCI_SGMII_DTS "apm,xgene-ahci-sgmii"
+
+/* Controller who PHY (internal reference clock macro) shared with PCIe */
+#define XGENE_AHCI_PCIE_DTS "apm,xgene-ahci-pcie"
+
+/* Max # of disk per a controller */
+#define MAX_AHCI_CHN_PERCTR 2
+
+#define SATA_ENET_MUX_OFFSET 0x00007000
+#define SATA_DIAG_OFFSET 0x0000D000
+#define SATA_GLB_OFFSET 0x0000D850
+#define SATA_SHIM_OFFSET 0x0000E000
+#define SATA_MASTER_OFFSET 0x0000F000
+#define SATA_PORT0_OFFSET 0x00000100
+#define SATA_PORT1_OFFSET 0x00000180
+
+/* MUX CSR */
+#define SATA_ENET_CONFIG_REG 0x00000000
+#define CFG_SATA_ENET_SELECT_MASK 0x00000001
+
+/* SATA host controller CSR */
+#define SLVRDERRATTRIBUTES 0x00000000
+#define SLVWRERRATTRIBUTES 0x00000004
+#define MSTRDERRATTRIBUTES 0x00000008
+#define MSTWRERRATTRIBUTES 0x0000000c
+#define BUSCTLREG 0x00000014
+#define IOFMSTRWAUX 0x00000018
+#define INTSTATUSMASK 0x0000002c
+#define ERRINTSTATUS 0x00000030
+#define ERRINTSTATUSMASK 0x00000034
+
+/* SATA host AHCI CSR */
+#define PORTCFG 0x000000a4
+#define PORTADDR_SET(dst, src) \
+ (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
+#define PORTPHY1CFG 0x000000a8
+#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
+ (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
+#define PORTPHY2CFG 0x000000ac
+#define PORTPHY3CFG 0x000000b0
+#define PORTPHY4CFG 0x000000b4
+#define PORTPHY5CFG 0x000000b8
+#define SCTL0 0x0000012C
+#define PORTPHY5CFG_RTCHG_SET(dst, src) \
+ (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
+#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
+ (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
+#define PORTAXICFG 0x000000bc
+#define PORTAXICFG_OUTTRANS_SET(dst, src) \
+ (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
+
+/* SATA host controller slave CSR */
+#define INT_SLV_TMOMASK 0x00000010
+
+/* SATA global diagnostic CSR */
+#define CFG_MEM_RAM_SHUTDOWN 0x00000070
+#define BLOCK_MEM_RDY 0x00000074
+
+struct xgene_ahci_context {
+ struct ahci_host_priv hpriv;
+ struct device *dev;
+ int irq;
+ void __iomem *csr_base; /* CSR base address of IP */
+ void __iomem *mmio_base; /* AHCI I/O base address */
+
+ struct phy *phy;
+};
+
+static int xgene_ahci_get_channel(struct ata_host *host, struct ata_port *port)
+{
+ int i;
+ for (i = 0; i < host->n_ports; i++)
+ if (host->ports[i] == port)
+ return i;
+ return -1;
+}
+
+static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
+{
+ void __iomem *diagcsr = ctx->csr_base + SATA_DIAG_OFFSET;
+ int try;
+ u32 val;
+
+ val = readl(diagcsr + CFG_MEM_RAM_SHUTDOWN);
+ if (val == 0) {
+ dev_dbg(ctx->dev, "memory already released from shutdown\n");
+ return 0;
+ }
+ dev_dbg(ctx->dev, "Release memory from shutdown\n");
+ /* SATA controller memory in shutdown. Remove from shutdown. */
+ writel(0x0, diagcsr + CFG_MEM_RAM_SHUTDOWN);
+ readl(diagcsr + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
+
+ /* Check for at least ~1ms */
+ try = 1000;
+ do {
+ val = readl(diagcsr + BLOCK_MEM_RDY);
+ if (val != 0xFFFFFFFF)
+ usleep_range(1, 100);
+ } while (val != 0xFFFFFFFF && try-- > 0);
+ if (try <= 0) {
+ dev_err(ctx->dev, "failed to release memory from shutdown\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+/*
+ * Custom Query ID command
+ *
+ * Due to HW errata, we must stop and re-start the port state machine after
+ * read ID command.
+ */
+static unsigned int xgene_ahci_read_id(struct ata_device *dev,
+ struct ata_taskfile *tf, u16 *id)
+{
+ u32 err_mask;
+ void __iomem *port_mmio = ahci_port_base(dev->link->ap);
+
+ err_mask = ata_do_dev_read_id(dev, tf, id);
+ if (err_mask)
+ return err_mask;
+
+ /* Mask reserved area. Bit78 spec of Link Power Management
+ * bit15-8: reserved
+ * bit7: NCQ autosence
+ * bit6: Software settings preservation supported
+ * bit5: reserved
+ * bit4: In-order sata delivery supported
+ * bit3: DIPM requests supported
+ * bit2: DMA Setup FIS Auto-Activate optimization supported
+ * bit1: DMA Setup FIX non-Zero buffer offsets supported
+ * bit0: Reserved
+ *
+ * Clear reserved bit (DEVSLP bit) as we don't support DEVSLP
+ */
+ id[78] &= 0x00FF;
+
+ /* Restart the port if requred due to HW errata */
+ if (!readl(port_mmio + PORT_CMD_ISSUE)) {
+ writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
+ readl(port_mmio + PORT_CMD); /* Force a barrier */
+ writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
+ readl(port_mmio + PORT_CMD); /* Force a barrier */
+ }
+ return 0;
+}
+
+static void xgene_ahci_force_phy_rdy(struct xgene_ahci_context *ctx,
+ int channel, int force)
+{
+ void __iomem *mmio = ctx->mmio_base;
+ u32 val;
+
+ val = readl(mmio + PORTCFG);
+ val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
+ writel(val, mmio + PORTCFG);
+ readl(mmio + PORTCFG); /* Force a barrier */
+ val = readl(mmio + PORTPHY1CFG);
+ val = PORTPHY1CFG_FRCPHYRDY_SET(val, force);
+ writel(val, mmio + PORTPHY1CFG);
+}
+
+static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
+{
+ void __iomem *mmio = ctx->mmio_base;
+ u32 val;
+
+ dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
+ mmio, channel);
+ val = readl(mmio + PORTCFG);
+ val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
+ writel(val, mmio + PORTCFG);
+ readl(mmio + PORTCFG); /* Force a barrier */
+ /* Disable fix rate */
+ writel(0x0001fffe, mmio + PORTPHY1CFG);
+ readl(mmio + PORTPHY1CFG); /* Force a barrier */
+ writel(0x5018461c, mmio + PORTPHY2CFG);
+ readl(mmio + PORTPHY2CFG); /* Force a barrier */
+ writel(0x1c081907, mmio + PORTPHY3CFG);
+ readl(mmio + PORTPHY3CFG); /* Force a barrier */
+ writel(0x1c080815, mmio + PORTPHY4CFG);
+ readl(mmio + PORTPHY4CFG); /* Force a barrier */
+ /* Set window negotiation */
+ val = readl(mmio + PORTPHY5CFG);
+ val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
+ writel(val, mmio + PORTPHY5CFG);
+ readl(mmio + PORTPHY5CFG); /* Force a barrier */
+ val = readl(mmio + PORTAXICFG);
+ val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
+ val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
+ writel(val, mmio + PORTAXICFG);
+ readl(mmio + PORTAXICFG); /* Force a barrier */
+}
+
+static int xgene_ahci_phy_restart(struct ata_link *link)
+{
+ struct ata_port *port = link->ap;
+ struct ata_host *host = port->host;
+ struct xgene_ahci_context *ctx = host->private_data;
+ int channel;
+
+ channel = xgene_ahci_get_channel(host, port);
+ if (channel < 0 || channel >= MAX_AHCI_CHN_PERCTR)
+ return -EINVAL;
+ xgene_ahci_force_phy_rdy(ctx, channel, 1);
+ xgene_ahci_force_phy_rdy(ctx, channel, 0);
+ return 0;
+}
+
+static int xgene_ahci_do_hardreset(struct ata_link *link,
+ unsigned long deadline, bool *online)
+{
+ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+ struct ata_port *ap = link->ap;
+ struct xgene_ahci_context *ctx = ap->host->private_data;
+ struct ahci_port_priv *pp = ap->private_data;
+ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ struct ata_taskfile tf;
+ int first_time = 1;
+ int rc;
+ u32 val;
+ int chan;
+ int i;
+
+ chan = xgene_ahci_get_channel(ap->host, ap);
+
+hardreset_retry:
+ /* clear D2H reception area to properly wait for D2H FIS */
+ ata_tf_init(link->device, &tf);
+ tf.command = 0x80;
+ ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+ rc = sata_link_hardreset(link, timing, deadline, online,
+ ahci_check_ready);
+
+ if (*online) {
+ /* Check to ensure that the disk comes up in matching speed */
+ if (first_time) {
+ u32 gen_speed;
+
+ first_time = 0;
+ sata_scr_read(link, SCR_STATUS, &gen_speed);
+ gen_speed = (gen_speed >> 4) & 0xf;
+ if (gen_speed == 1 || gen_speed == 2) {
+ /* For Gen2/1 and first time, let's check again
+ * with Gen2/1 PHY to ensure actual Gen2/1 disk.
+ */
+ phy_set_speed(ctx->phy, chan,
+ gen_speed == 2 ? 3000000000ULL :
+ 1500000000ULL);
+ xgene_ahci_phy_restart(link);
+ goto hardreset_retry;
+ }
+ }
+
+ /* Clear SER_DISPARITY/SER_10B_8B_ERR if set due to errata */
+ for (i = 0; i < 5; i++) {
+ /* Check if error bit set */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ if (!(val & (SERR_DISPARITY | SERR_10B_8B_ERR)))
+ break;
+ /* Clear any error due to errata */
+ xgene_ahci_force_phy_rdy(ctx, chan, 1);
+ /* Reset the PHY Rx path */
+ phy_set_speed(ctx->phy, chan, 0);
+ xgene_ahci_force_phy_rdy(ctx, chan, 0);
+ /* Clear all errors */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ writel(val, port_mmio + PORT_SCR_ERR);
+ }
+ }
+
+ /* clear all errors if any pending */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ writel(val, port_mmio + PORT_SCR_ERR);
+
+ return rc;
+}
+
+static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline)
+{
+ struct ata_port *ap = link->ap;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ bool online;
+ int rc;
+ int portcmd_saved;
+ u32 portclb_saved;
+ u32 portclbhi_saved;
+ u32 portrxfis_saved;
+ u32 portrxfishi_saved;
+
+ /* As hardreset reset these CSR, let save it to restore later */
+ portcmd_saved = readl(port_mmio + PORT_CMD);
+ portclb_saved = readl(port_mmio + PORT_LST_ADDR);
+ portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
+ portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
+ portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
+
+ ahci_stop_engine(ap);
+
+ rc = xgene_ahci_do_hardreset(link, deadline, &online);
+
+ /* As controller hardreset clear them, let restore them */
+ writel(portcmd_saved, port_mmio + PORT_CMD);
+ writel(portclb_saved, port_mmio + PORT_LST_ADDR);
+ writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
+ writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
+ writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
+
+ ahci_start_engine(ap);
+
+ if (online)
+ *class = ahci_dev_classify(ap);
+
+ return rc;
+}
+
+static struct ata_port_operations xgene_ahci_ops = {
+ .inherits = &ahci_ops,
+ .hardreset = xgene_ahci_hardreset,
+ .read_id = xgene_ahci_read_id,
+};
+
+static const struct ata_port_info xgene_ahci_port_info[] = {
+ {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &xgene_ahci_ops,
+ },
+};
+
+static struct scsi_host_template xgene_ahci_sht = {
+ AHCI_SHT("XGene-ahci"),
+};
+
+static int xgene_ahci_hw_init(struct xgene_ahci_context *hpriv)
+{
+ int i;
+ int rc;
+ u32 val;
+
+ /* Remove IP RAM out of shutdown */
+ rc = xgene_ahci_init_memram(hpriv);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
+ xgene_ahci_set_phy_cfg(hpriv, i);
+
+ /* AXI disable Mask */
+ writel(0xffffffff, hpriv->mmio_base + HOST_IRQ_STAT);
+ readl(hpriv->mmio_base + HOST_IRQ_STAT); /* Force a barrier */
+ writel(0, hpriv->csr_base + INTSTATUSMASK);
+ readl(hpriv->csr_base + INTSTATUSMASK); /* Force a barrier */
+ dev_dbg(hpriv->dev, "top level interrupt mask 0x%X value 0x%08X\n",
+ INTSTATUSMASK, val);
+
+ writel(0x0, hpriv->csr_base + ERRINTSTATUSMASK);
+ readl(hpriv->csr_base + ERRINTSTATUSMASK); /* Force a barrier */
+ writel(0x0, hpriv->csr_base + SATA_SHIM_OFFSET + INT_SLV_TMOMASK);
+ readl(hpriv->csr_base + SATA_SHIM_OFFSET + INT_SLV_TMOMASK);
+
+ /* Enable AXI Interrupt */
+ writel(0xffffffff, hpriv->csr_base + SLVRDERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + SLVWRERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + MSTRDERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + MSTWRERRATTRIBUTES);
+
+ /* Enable coherency */
+ val = readl(hpriv->csr_base + BUSCTLREG);
+ val &= ~0x00000002; /* Enable write coherency */
+ val &= ~0x00000001; /* Enable read coherency */
+ writel(val, hpriv->csr_base + BUSCTLREG);
+
+ val = readl(hpriv->csr_base + IOFMSTRWAUX);
+ val |= (1 << 3); /* Enable read coherency */
+ val |= (1 << 9); /* Enable write coherency */
+ writel(val, hpriv->csr_base + IOFMSTRWAUX);
+ val = readl(hpriv->csr_base + IOFMSTRWAUX);
+ dev_dbg(hpriv->dev, "coherency 0x%X value 0x%08X\n",
+ IOFMSTRWAUX, val);
+
+ return rc;
+}
+
+static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
+{
+ void *mux_csr = ctx->csr_base + SATA_ENET_MUX_OFFSET;
+ u32 val;
+
+ dev_dbg(ctx->dev, "switch the MUX to SATA\n");
+ val = readl(mux_csr + SATA_ENET_CONFIG_REG);
+ val &= ~CFG_SATA_ENET_SELECT_MASK;
+ writel(val, mux_csr + SATA_ENET_CONFIG_REG);
+ val = readl(mux_csr + SATA_ENET_CONFIG_REG);
+ return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
+}
+
+static int xgene_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct xgene_ahci_context *hpriv;
+ struct ata_port_info pi = xgene_ahci_port_info[0];
+ const struct ata_port_info *ppi[] = { &pi, NULL };
+ struct ata_host *host;
+ struct resource *res;
+ int n_ports;
+ int rc = 0;
+ int i;
+
+ hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+ if (!hpriv) {
+ dev_err(dev, "can't allocate host context\n");
+ return -ENOMEM;
+ }
+
+ hpriv->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "no MMIO space\n");
+ return -EINVAL;
+ }
+
+ hpriv->mmio_base = devm_ioremap_resource(dev, res);
+ if (!hpriv->mmio_base) {
+ dev_err(dev, "can't map %pR\n", res);
+ return -ENOMEM;
+ }
+
+ hpriv->hpriv.mmio = hpriv->mmio_base;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res) {
+ dev_err(dev, "no csr space\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Can't use devm_ioremap_resource due to overlapping region.
+ * 0xYYYY.0000 - host core
+ * 0xYYYY.7000 - Mux (if applicable)
+ * 0xYYYY.A000 - PHY indirect access
+ * 0xYYYY.C000 - Clock
+ * 0xYYYY.D000 - RAM shutdown removal
+ * As we map the entire region as one, it overlaps with the PHY driver.
+ */
+ hpriv->csr_base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!hpriv->csr_base) {
+ dev_err(dev, "can't map %pR\n", res);
+ return -ENOMEM;
+ }
+
+ dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n",
+ hpriv->csr_base, hpriv->mmio_base);
+
+ hpriv->irq = platform_get_irq(pdev, 0);
+ if (hpriv->irq <= 0) {
+ dev_err(dev, "no IRQ\n");
+ return -EINVAL;
+ }
+
+ /* Select ATA */
+ if (of_device_is_compatible(pdev->dev.of_node,
+ XGENE_AHCI_SGMII_DTS)) {
+ if (xgene_ahci_mux_select(hpriv)) {
+ dev_err(dev, "SATA mux selection failed\n");
+ return -ENODEV;
+ }
+ }
+
+ hpriv->hpriv.clk = clk_get(dev, NULL);
+ if (IS_ERR(hpriv->hpriv.clk)) {
+ dev_err(dev, "no clock\n");
+ } else {
+ /* HW requires toggle of the clock */
+ clk_prepare_enable(hpriv->hpriv.clk);
+ clk_disable_unprepare(hpriv->hpriv.clk);
+ rc = clk_prepare_enable(hpriv->hpriv.clk);
+ if (rc) {
+ dev_err(dev, "clock prepare enable failed\n");
+ goto error;
+ }
+ }
+
+ /* Configure the PHY */
+ hpriv->phy = devm_phy_get(dev, "sata-6g");
+ if (!hpriv->phy) {
+ dev_err(dev, "no PHY available\n");
+ rc = -ENODEV;
+ goto error;
+ }
+
+ rc = phy_init(hpriv->phy);
+ if (rc) {
+ dev_err(dev, "PHY initialize failed %d\n", rc);
+ goto error;
+ }
+
+ /* Configure the host controller */
+ xgene_ahci_hw_init(hpriv);
+
+ /* Setup AHCI host priv structure */
+ ahci_save_initial_config(dev, &hpriv->hpriv, 0, 0);
+
+ /* prepare host */
+ if (hpriv->hpriv.cap & HOST_CAP_NCQ)
+ pi.flags |= ATA_FLAG_NCQ;
+
+ ahci_set_em_messages(&hpriv->hpriv, &pi);
+
+ /*
+ * CAP.NP sometimes indicate the index of the last enabled
+ * port, at other times, that of the last possible port, so
+ * determining the maximum port number requires looking at
+ * both CAP.NP and port_map.
+ */
+ n_ports = max(ahci_nr_ports(hpriv->hpriv.cap),
+ fls(hpriv->hpriv.port_map));
+
+ host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+ if (!host) {
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ host->private_data = hpriv;
+
+ if (!(hpriv->hpriv.cap & HOST_CAP_SSS) || ahci_ignore_sss)
+ host->flags |= ATA_HOST_PARALLEL_SCAN;
+ else
+ dev_warn(dev, "ahci: SSS flag set, parallel bus scan disabled\n");
+
+ if (pi.flags & ATA_FLAG_EM)
+ ahci_reset_em(host);
+
+ for (i = 0; i < host->n_ports; i++) {
+ struct ata_port *ap = host->ports[i];
+
+ ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+ /* set enclosure management message type */
+ if (ap->flags & ATA_FLAG_EM)
+ ap->em_message_type = hpriv->hpriv.em_msg_type;
+
+ /* disabled/not-implemented port */
+ if (!(hpriv->hpriv.port_map & (1 << i)))
+ ap->ops = &ata_dummy_port_ops;
+ }
+
+ rc = ahci_reset_controller(host);
+ if (rc)
+ goto error;
+
+ ahci_init_controller(host);
+
+ /* Setup DMA mask */
+ rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (rc) {
+ dev_err(dev, "Unable to set dma mask\n");
+ goto error;
+ }
+
+ rc = ata_host_activate(host, hpriv->irq, ahci_interrupt,
+ IRQF_SHARED, &xgene_ahci_sht);
+ if (rc)
+ goto error;
+
+ dev_dbg(dev, "X-Gene SATA host controller initialized\n");
+ return 0;
+
+error:
+ return rc;
+}
+
+static const struct of_device_id xgene_ahci_of_match[] = {
+ {.compatible = XGENE_AHCI_SGMII_DTS,},
+ {.compatible = XGENE_AHCI_PCIE_DTS,},
+ {},
+};
+MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
+
+static struct platform_driver xgene_ahci_driver = {
+ .driver = {
+ .name = "xgene-ahci",
+ .owner = THIS_MODULE,
+ .of_match_table = xgene_ahci_of_match,
+ },
+ .probe = xgene_ahci_probe,
+};
+
+module_platform_driver(xgene_ahci_driver);
+
+MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
+MODULE_AUTHOR("Loc Ho <lho@apm.com>");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("0.4");
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 3/4] ata: Add APM X-Gene SoC SATA host controller driver
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for the APM X-Gene SoC SATA host controller driver.
It requires the corresponding APM X-Gene SoC PHY driver.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/sata_xgene.c | 630 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 639 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_xgene.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4e73772..cd1bc3c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -106,6 +106,14 @@ config AHCI_IMX
If unsure, say N.
+config SATA_XGENE
+ tristate "APM X-Gene 6.0Gbps SATA host controller support"
+ depends on ARM64 || COMPILE_TEST
+ select SATA_AHCI_PLATFORM
+ select PHY_XGENE
+ help
+ This option enables support for APM X-Gene SoC SATA host controller.
+
config SATA_FSL
tristate "Freescale 3.0Gbps SATA support"
depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 46518c6..1c0fabe 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
+obj-$(CONFIG_SATA_XGENE) += sata_xgene.o
# SFF w/ custom DMA
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
diff --git a/drivers/ata/sata_xgene.c b/drivers/ata/sata_xgene.c
new file mode 100644
index 0000000..2e9da35
--- /dev/null
+++ b/drivers/ata/sata_xgene.c
@@ -0,0 +1,630 @@
+/*
+ * AppliedMicro X-Gene SoC SATA Host Controller Driver
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho <lho@apm.com>
+ * Tuan Phan <tphan@apm.com>
+ * Suman Tripathi <stripathi@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/phy/phy.h>
+#include "ahci.h"
+
+/* Controller who PHY shared with SGMII Ethernet PHY */
+#define XGENE_AHCI_SGMII_DTS "apm,xgene-ahci-sgmii"
+
+/* Controller who PHY (internal reference clock macro) shared with PCIe */
+#define XGENE_AHCI_PCIE_DTS "apm,xgene-ahci-pcie"
+
+/* Max # of disk per a controller */
+#define MAX_AHCI_CHN_PERCTR 2
+
+#define SATA_ENET_MUX_OFFSET 0x00007000
+#define SATA_DIAG_OFFSET 0x0000D000
+#define SATA_GLB_OFFSET 0x0000D850
+#define SATA_SHIM_OFFSET 0x0000E000
+#define SATA_MASTER_OFFSET 0x0000F000
+#define SATA_PORT0_OFFSET 0x00000100
+#define SATA_PORT1_OFFSET 0x00000180
+
+/* MUX CSR */
+#define SATA_ENET_CONFIG_REG 0x00000000
+#define CFG_SATA_ENET_SELECT_MASK 0x00000001
+
+/* SATA host controller CSR */
+#define SLVRDERRATTRIBUTES 0x00000000
+#define SLVWRERRATTRIBUTES 0x00000004
+#define MSTRDERRATTRIBUTES 0x00000008
+#define MSTWRERRATTRIBUTES 0x0000000c
+#define BUSCTLREG 0x00000014
+#define IOFMSTRWAUX 0x00000018
+#define INTSTATUSMASK 0x0000002c
+#define ERRINTSTATUS 0x00000030
+#define ERRINTSTATUSMASK 0x00000034
+
+/* SATA host AHCI CSR */
+#define PORTCFG 0x000000a4
+#define PORTADDR_SET(dst, src) \
+ (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
+#define PORTPHY1CFG 0x000000a8
+#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
+ (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
+#define PORTPHY2CFG 0x000000ac
+#define PORTPHY3CFG 0x000000b0
+#define PORTPHY4CFG 0x000000b4
+#define PORTPHY5CFG 0x000000b8
+#define SCTL0 0x0000012C
+#define PORTPHY5CFG_RTCHG_SET(dst, src) \
+ (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
+#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
+ (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
+#define PORTAXICFG 0x000000bc
+#define PORTAXICFG_OUTTRANS_SET(dst, src) \
+ (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
+
+/* SATA host controller slave CSR */
+#define INT_SLV_TMOMASK 0x00000010
+
+/* SATA global diagnostic CSR */
+#define CFG_MEM_RAM_SHUTDOWN 0x00000070
+#define BLOCK_MEM_RDY 0x00000074
+
+struct xgene_ahci_context {
+ struct ahci_host_priv hpriv;
+ struct device *dev;
+ int irq;
+ void __iomem *csr_base; /* CSR base address of IP */
+ void __iomem *mmio_base; /* AHCI I/O base address */
+
+ struct phy *phy;
+};
+
+static int xgene_ahci_get_channel(struct ata_host *host, struct ata_port *port)
+{
+ int i;
+ for (i = 0; i < host->n_ports; i++)
+ if (host->ports[i] == port)
+ return i;
+ return -1;
+}
+
+static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
+{
+ void __iomem *diagcsr = ctx->csr_base + SATA_DIAG_OFFSET;
+ int try;
+ u32 val;
+
+ val = readl(diagcsr + CFG_MEM_RAM_SHUTDOWN);
+ if (val == 0) {
+ dev_dbg(ctx->dev, "memory already released from shutdown\n");
+ return 0;
+ }
+ dev_dbg(ctx->dev, "Release memory from shutdown\n");
+ /* SATA controller memory in shutdown. Remove from shutdown. */
+ writel(0x0, diagcsr + CFG_MEM_RAM_SHUTDOWN);
+ readl(diagcsr + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
+
+ /* Check for at least ~1ms */
+ try = 1000;
+ do {
+ val = readl(diagcsr + BLOCK_MEM_RDY);
+ if (val != 0xFFFFFFFF)
+ usleep_range(1, 100);
+ } while (val != 0xFFFFFFFF && try-- > 0);
+ if (try <= 0) {
+ dev_err(ctx->dev, "failed to release memory from shutdown\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+/*
+ * Custom Query ID command
+ *
+ * Due to HW errata, we must stop and re-start the port state machine after
+ * read ID command.
+ */
+static unsigned int xgene_ahci_read_id(struct ata_device *dev,
+ struct ata_taskfile *tf, u16 *id)
+{
+ u32 err_mask;
+ void __iomem *port_mmio = ahci_port_base(dev->link->ap);
+
+ err_mask = ata_do_dev_read_id(dev, tf, id);
+ if (err_mask)
+ return err_mask;
+
+ /* Mask reserved area. Bit78 spec of Link Power Management
+ * bit15-8: reserved
+ * bit7: NCQ autosence
+ * bit6: Software settings preservation supported
+ * bit5: reserved
+ * bit4: In-order sata delivery supported
+ * bit3: DIPM requests supported
+ * bit2: DMA Setup FIS Auto-Activate optimization supported
+ * bit1: DMA Setup FIX non-Zero buffer offsets supported
+ * bit0: Reserved
+ *
+ * Clear reserved bit (DEVSLP bit) as we don't support DEVSLP
+ */
+ id[78] &= 0x00FF;
+
+ /* Restart the port if requred due to HW errata */
+ if (!readl(port_mmio + PORT_CMD_ISSUE)) {
+ writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
+ readl(port_mmio + PORT_CMD); /* Force a barrier */
+ writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
+ readl(port_mmio + PORT_CMD); /* Force a barrier */
+ }
+ return 0;
+}
+
+static void xgene_ahci_force_phy_rdy(struct xgene_ahci_context *ctx,
+ int channel, int force)
+{
+ void __iomem *mmio = ctx->mmio_base;
+ u32 val;
+
+ val = readl(mmio + PORTCFG);
+ val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
+ writel(val, mmio + PORTCFG);
+ readl(mmio + PORTCFG); /* Force a barrier */
+ val = readl(mmio + PORTPHY1CFG);
+ val = PORTPHY1CFG_FRCPHYRDY_SET(val, force);
+ writel(val, mmio + PORTPHY1CFG);
+}
+
+static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
+{
+ void __iomem *mmio = ctx->mmio_base;
+ u32 val;
+
+ dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
+ mmio, channel);
+ val = readl(mmio + PORTCFG);
+ val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
+ writel(val, mmio + PORTCFG);
+ readl(mmio + PORTCFG); /* Force a barrier */
+ /* Disable fix rate */
+ writel(0x0001fffe, mmio + PORTPHY1CFG);
+ readl(mmio + PORTPHY1CFG); /* Force a barrier */
+ writel(0x5018461c, mmio + PORTPHY2CFG);
+ readl(mmio + PORTPHY2CFG); /* Force a barrier */
+ writel(0x1c081907, mmio + PORTPHY3CFG);
+ readl(mmio + PORTPHY3CFG); /* Force a barrier */
+ writel(0x1c080815, mmio + PORTPHY4CFG);
+ readl(mmio + PORTPHY4CFG); /* Force a barrier */
+ /* Set window negotiation */
+ val = readl(mmio + PORTPHY5CFG);
+ val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
+ writel(val, mmio + PORTPHY5CFG);
+ readl(mmio + PORTPHY5CFG); /* Force a barrier */
+ val = readl(mmio + PORTAXICFG);
+ val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
+ val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
+ writel(val, mmio + PORTAXICFG);
+ readl(mmio + PORTAXICFG); /* Force a barrier */
+}
+
+static int xgene_ahci_phy_restart(struct ata_link *link)
+{
+ struct ata_port *port = link->ap;
+ struct ata_host *host = port->host;
+ struct xgene_ahci_context *ctx = host->private_data;
+ int channel;
+
+ channel = xgene_ahci_get_channel(host, port);
+ if (channel < 0 || channel >= MAX_AHCI_CHN_PERCTR)
+ return -EINVAL;
+ xgene_ahci_force_phy_rdy(ctx, channel, 1);
+ xgene_ahci_force_phy_rdy(ctx, channel, 0);
+ return 0;
+}
+
+static int xgene_ahci_do_hardreset(struct ata_link *link,
+ unsigned long deadline, bool *online)
+{
+ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+ struct ata_port *ap = link->ap;
+ struct xgene_ahci_context *ctx = ap->host->private_data;
+ struct ahci_port_priv *pp = ap->private_data;
+ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ struct ata_taskfile tf;
+ int first_time = 1;
+ int rc;
+ u32 val;
+ int chan;
+ int i;
+
+ chan = xgene_ahci_get_channel(ap->host, ap);
+
+hardreset_retry:
+ /* clear D2H reception area to properly wait for D2H FIS */
+ ata_tf_init(link->device, &tf);
+ tf.command = 0x80;
+ ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+ rc = sata_link_hardreset(link, timing, deadline, online,
+ ahci_check_ready);
+
+ if (*online) {
+ /* Check to ensure that the disk comes up in matching speed */
+ if (first_time) {
+ u32 gen_speed;
+
+ first_time = 0;
+ sata_scr_read(link, SCR_STATUS, &gen_speed);
+ gen_speed = (gen_speed >> 4) & 0xf;
+ if (gen_speed == 1 || gen_speed == 2) {
+ /* For Gen2/1 and first time, let's check again
+ * with Gen2/1 PHY to ensure actual Gen2/1 disk.
+ */
+ phy_set_speed(ctx->phy, chan,
+ gen_speed == 2 ? 3000000000ULL :
+ 1500000000ULL);
+ xgene_ahci_phy_restart(link);
+ goto hardreset_retry;
+ }
+ }
+
+ /* Clear SER_DISPARITY/SER_10B_8B_ERR if set due to errata */
+ for (i = 0; i < 5; i++) {
+ /* Check if error bit set */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ if (!(val & (SERR_DISPARITY | SERR_10B_8B_ERR)))
+ break;
+ /* Clear any error due to errata */
+ xgene_ahci_force_phy_rdy(ctx, chan, 1);
+ /* Reset the PHY Rx path */
+ phy_set_speed(ctx->phy, chan, 0);
+ xgene_ahci_force_phy_rdy(ctx, chan, 0);
+ /* Clear all errors */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ writel(val, port_mmio + PORT_SCR_ERR);
+ }
+ }
+
+ /* clear all errors if any pending */
+ val = readl(port_mmio + PORT_SCR_ERR);
+ writel(val, port_mmio + PORT_SCR_ERR);
+
+ return rc;
+}
+
+static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline)
+{
+ struct ata_port *ap = link->ap;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ bool online;
+ int rc;
+ int portcmd_saved;
+ u32 portclb_saved;
+ u32 portclbhi_saved;
+ u32 portrxfis_saved;
+ u32 portrxfishi_saved;
+
+ /* As hardreset reset these CSR, let save it to restore later */
+ portcmd_saved = readl(port_mmio + PORT_CMD);
+ portclb_saved = readl(port_mmio + PORT_LST_ADDR);
+ portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
+ portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
+ portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
+
+ ahci_stop_engine(ap);
+
+ rc = xgene_ahci_do_hardreset(link, deadline, &online);
+
+ /* As controller hardreset clear them, let restore them */
+ writel(portcmd_saved, port_mmio + PORT_CMD);
+ writel(portclb_saved, port_mmio + PORT_LST_ADDR);
+ writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
+ writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
+ writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
+
+ ahci_start_engine(ap);
+
+ if (online)
+ *class = ahci_dev_classify(ap);
+
+ return rc;
+}
+
+static struct ata_port_operations xgene_ahci_ops = {
+ .inherits = &ahci_ops,
+ .hardreset = xgene_ahci_hardreset,
+ .read_id = xgene_ahci_read_id,
+};
+
+static const struct ata_port_info xgene_ahci_port_info[] = {
+ {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &xgene_ahci_ops,
+ },
+};
+
+static struct scsi_host_template xgene_ahci_sht = {
+ AHCI_SHT("XGene-ahci"),
+};
+
+static int xgene_ahci_hw_init(struct xgene_ahci_context *hpriv)
+{
+ int i;
+ int rc;
+ u32 val;
+
+ /* Remove IP RAM out of shutdown */
+ rc = xgene_ahci_init_memram(hpriv);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
+ xgene_ahci_set_phy_cfg(hpriv, i);
+
+ /* AXI disable Mask */
+ writel(0xffffffff, hpriv->mmio_base + HOST_IRQ_STAT);
+ readl(hpriv->mmio_base + HOST_IRQ_STAT); /* Force a barrier */
+ writel(0, hpriv->csr_base + INTSTATUSMASK);
+ readl(hpriv->csr_base + INTSTATUSMASK); /* Force a barrier */
+ dev_dbg(hpriv->dev, "top level interrupt mask 0x%X value 0x%08X\n",
+ INTSTATUSMASK, val);
+
+ writel(0x0, hpriv->csr_base + ERRINTSTATUSMASK);
+ readl(hpriv->csr_base + ERRINTSTATUSMASK); /* Force a barrier */
+ writel(0x0, hpriv->csr_base + SATA_SHIM_OFFSET + INT_SLV_TMOMASK);
+ readl(hpriv->csr_base + SATA_SHIM_OFFSET + INT_SLV_TMOMASK);
+
+ /* Enable AXI Interrupt */
+ writel(0xffffffff, hpriv->csr_base + SLVRDERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + SLVWRERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + MSTRDERRATTRIBUTES);
+ writel(0xffffffff, hpriv->csr_base + MSTWRERRATTRIBUTES);
+
+ /* Enable coherency */
+ val = readl(hpriv->csr_base + BUSCTLREG);
+ val &= ~0x00000002; /* Enable write coherency */
+ val &= ~0x00000001; /* Enable read coherency */
+ writel(val, hpriv->csr_base + BUSCTLREG);
+
+ val = readl(hpriv->csr_base + IOFMSTRWAUX);
+ val |= (1 << 3); /* Enable read coherency */
+ val |= (1 << 9); /* Enable write coherency */
+ writel(val, hpriv->csr_base + IOFMSTRWAUX);
+ val = readl(hpriv->csr_base + IOFMSTRWAUX);
+ dev_dbg(hpriv->dev, "coherency 0x%X value 0x%08X\n",
+ IOFMSTRWAUX, val);
+
+ return rc;
+}
+
+static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
+{
+ void *mux_csr = ctx->csr_base + SATA_ENET_MUX_OFFSET;
+ u32 val;
+
+ dev_dbg(ctx->dev, "switch the MUX to SATA\n");
+ val = readl(mux_csr + SATA_ENET_CONFIG_REG);
+ val &= ~CFG_SATA_ENET_SELECT_MASK;
+ writel(val, mux_csr + SATA_ENET_CONFIG_REG);
+ val = readl(mux_csr + SATA_ENET_CONFIG_REG);
+ return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
+}
+
+static int xgene_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct xgene_ahci_context *hpriv;
+ struct ata_port_info pi = xgene_ahci_port_info[0];
+ const struct ata_port_info *ppi[] = { &pi, NULL };
+ struct ata_host *host;
+ struct resource *res;
+ int n_ports;
+ int rc = 0;
+ int i;
+
+ hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+ if (!hpriv) {
+ dev_err(dev, "can't allocate host context\n");
+ return -ENOMEM;
+ }
+
+ hpriv->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "no MMIO space\n");
+ return -EINVAL;
+ }
+
+ hpriv->mmio_base = devm_ioremap_resource(dev, res);
+ if (!hpriv->mmio_base) {
+ dev_err(dev, "can't map %pR\n", res);
+ return -ENOMEM;
+ }
+
+ hpriv->hpriv.mmio = hpriv->mmio_base;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res) {
+ dev_err(dev, "no csr space\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Can't use devm_ioremap_resource due to overlapping region.
+ * 0xYYYY.0000 - host core
+ * 0xYYYY.7000 - Mux (if applicable)
+ * 0xYYYY.A000 - PHY indirect access
+ * 0xYYYY.C000 - Clock
+ * 0xYYYY.D000 - RAM shutdown removal
+ * As we map the entire region as one, it overlaps with the PHY driver.
+ */
+ hpriv->csr_base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!hpriv->csr_base) {
+ dev_err(dev, "can't map %pR\n", res);
+ return -ENOMEM;
+ }
+
+ dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n",
+ hpriv->csr_base, hpriv->mmio_base);
+
+ hpriv->irq = platform_get_irq(pdev, 0);
+ if (hpriv->irq <= 0) {
+ dev_err(dev, "no IRQ\n");
+ return -EINVAL;
+ }
+
+ /* Select ATA */
+ if (of_device_is_compatible(pdev->dev.of_node,
+ XGENE_AHCI_SGMII_DTS)) {
+ if (xgene_ahci_mux_select(hpriv)) {
+ dev_err(dev, "SATA mux selection failed\n");
+ return -ENODEV;
+ }
+ }
+
+ hpriv->hpriv.clk = clk_get(dev, NULL);
+ if (IS_ERR(hpriv->hpriv.clk)) {
+ dev_err(dev, "no clock\n");
+ } else {
+ /* HW requires toggle of the clock */
+ clk_prepare_enable(hpriv->hpriv.clk);
+ clk_disable_unprepare(hpriv->hpriv.clk);
+ rc = clk_prepare_enable(hpriv->hpriv.clk);
+ if (rc) {
+ dev_err(dev, "clock prepare enable failed\n");
+ goto error;
+ }
+ }
+
+ /* Configure the PHY */
+ hpriv->phy = devm_phy_get(dev, "sata-6g");
+ if (!hpriv->phy) {
+ dev_err(dev, "no PHY available\n");
+ rc = -ENODEV;
+ goto error;
+ }
+
+ rc = phy_init(hpriv->phy);
+ if (rc) {
+ dev_err(dev, "PHY initialize failed %d\n", rc);
+ goto error;
+ }
+
+ /* Configure the host controller */
+ xgene_ahci_hw_init(hpriv);
+
+ /* Setup AHCI host priv structure */
+ ahci_save_initial_config(dev, &hpriv->hpriv, 0, 0);
+
+ /* prepare host */
+ if (hpriv->hpriv.cap & HOST_CAP_NCQ)
+ pi.flags |= ATA_FLAG_NCQ;
+
+ ahci_set_em_messages(&hpriv->hpriv, &pi);
+
+ /*
+ * CAP.NP sometimes indicate the index of the last enabled
+ * port, at other times, that of the last possible port, so
+ * determining the maximum port number requires looking at
+ * both CAP.NP and port_map.
+ */
+ n_ports = max(ahci_nr_ports(hpriv->hpriv.cap),
+ fls(hpriv->hpriv.port_map));
+
+ host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+ if (!host) {
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ host->private_data = hpriv;
+
+ if (!(hpriv->hpriv.cap & HOST_CAP_SSS) || ahci_ignore_sss)
+ host->flags |= ATA_HOST_PARALLEL_SCAN;
+ else
+ dev_warn(dev, "ahci: SSS flag set, parallel bus scan disabled\n");
+
+ if (pi.flags & ATA_FLAG_EM)
+ ahci_reset_em(host);
+
+ for (i = 0; i < host->n_ports; i++) {
+ struct ata_port *ap = host->ports[i];
+
+ ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+ /* set enclosure management message type */
+ if (ap->flags & ATA_FLAG_EM)
+ ap->em_message_type = hpriv->hpriv.em_msg_type;
+
+ /* disabled/not-implemented port */
+ if (!(hpriv->hpriv.port_map & (1 << i)))
+ ap->ops = &ata_dummy_port_ops;
+ }
+
+ rc = ahci_reset_controller(host);
+ if (rc)
+ goto error;
+
+ ahci_init_controller(host);
+
+ /* Setup DMA mask */
+ rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (rc) {
+ dev_err(dev, "Unable to set dma mask\n");
+ goto error;
+ }
+
+ rc = ata_host_activate(host, hpriv->irq, ahci_interrupt,
+ IRQF_SHARED, &xgene_ahci_sht);
+ if (rc)
+ goto error;
+
+ dev_dbg(dev, "X-Gene SATA host controller initialized\n");
+ return 0;
+
+error:
+ return rc;
+}
+
+static const struct of_device_id xgene_ahci_of_match[] = {
+ {.compatible = XGENE_AHCI_SGMII_DTS,},
+ {.compatible = XGENE_AHCI_PCIE_DTS,},
+ {},
+};
+MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
+
+static struct platform_driver xgene_ahci_driver = {
+ .driver = {
+ .name = "xgene-ahci",
+ .owner = THIS_MODULE,
+ .of_match_table = xgene_ahci_of_match,
+ },
+ .probe = xgene_ahci_probe,
+};
+
+module_platform_driver(xgene_ahci_driver);
+
+MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
+MODULE_AUTHOR("Loc Ho <lho@apm.com>");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("0.4");
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 4/4] arm64: Add APM X-Gene SoC SATA host controller DTS entries
2014-01-15 7:11 ` Loc Ho
@ 2014-01-15 7:11 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
arch/arm64/boot/dts/apm-storm.dtsi | 75 ++++++++++++++++++++++++++++++++++++
1 files changed, 75 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index a1f475d..34900d2 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -221,6 +221,48 @@
enable-offset = <0x0>;
enable-mask = <0x06>;
};
+
+ sata01clk: sata01clk@1f21c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f21c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata01clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata23clk: sata23clk@1f22c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f22c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata23clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata45clk: sata45clk@1f23c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f23c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata45clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
};
serial0: serial@1c020000 {
@@ -269,5 +311,38 @@
apm,tx-boost-gain = <31 31 31 31 31 31>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
};
+
+ sata1: sata@1a000000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a000000 0x0 0x1000>,
+ <0x0 0x1f210000 0x0 0x10000>;
+ interrupts = <0x0 0x86 0x4>;
+ status = "disabled";
+ clocks = <&sata01clk 0>;
+ phys = <&phy1 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata2: sata@1a400000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a400000 0x0 0x1000>,
+ <0x0 0x1f220000 0x0 0x10000>;
+ interrupts = <0x0 0x87 0x4>;
+ status = "ok";
+ clocks = <&sata23clk 0>;
+ phys = <&phy2 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata3: sata@1a800000 {
+ compatible = "apm,xgene-ahci-pcie";
+ reg = <0x0 0x1a800000 0x0 0x1000>,
+ <0x0 0x1f230000 0x0 0x10000>;
+ interrupts = <0x0 0x88 0x4>;
+ status = "ok";
+ clocks = <&sata45clk 0>;
+ phys = <&phy3 0>;
+ phy-names = "sata-6g";
+ };
};
};
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v9 4/4] arm64: Add APM X-Gene SoC SATA host controller DTS entries
@ 2014-01-15 7:11 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 7:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
arch/arm64/boot/dts/apm-storm.dtsi | 75 ++++++++++++++++++++++++++++++++++++
1 files changed, 75 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index a1f475d..34900d2 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -221,6 +221,48 @@
enable-offset = <0x0>;
enable-mask = <0x06>;
};
+
+ sata01clk: sata01clk at 1f21c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f21c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata01clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata23clk: sata23clk at 1f22c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f22c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata23clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata45clk: sata45clk at 1f23c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ clock-names = "socplldiv2";
+ reg = <0x0 0x1f23c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata45clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
};
serial0: serial at 1c020000 {
@@ -269,5 +311,38 @@
apm,tx-boost-gain = <31 31 31 31 31 31>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
};
+
+ sata1: sata at 1a000000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a000000 0x0 0x1000>,
+ <0x0 0x1f210000 0x0 0x10000>;
+ interrupts = <0x0 0x86 0x4>;
+ status = "disabled";
+ clocks = <&sata01clk 0>;
+ phys = <&phy1 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata2: sata at 1a400000 {
+ compatible = "apm,xgene-ahci-sgmii";
+ reg = <0x0 0x1a400000 0x0 0x1000>,
+ <0x0 0x1f220000 0x0 0x10000>;
+ interrupts = <0x0 0x87 0x4>;
+ status = "ok";
+ clocks = <&sata23clk 0>;
+ phys = <&phy2 0>;
+ phy-names = "sata-6g";
+ };
+
+ sata3: sata at 1a800000 {
+ compatible = "apm,xgene-ahci-pcie";
+ reg = <0x0 0x1a800000 0x0 0x1000>,
+ <0x0 0x1f230000 0x0 0x10000>;
+ interrupts = <0x0 0x88 0x4>;
+ status = "ok";
+ clocks = <&sata45clk 0>;
+ phys = <&phy3 0>;
+ phy-names = "sata-6g";
+ };
};
};
--
1.5.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 7:11 ` Loc Ho
@ 2014-01-15 11:18 ` Mark Rutland
-1 siblings, 0 replies; 26+ messages in thread
From: Mark Rutland @ 2014-01-15 11:18 UTC (permalink / raw)
To: Loc Ho
Cc: devicetree, Suman Tripathi, arnd, linux-scsi, linux-ide, jcm,
patches, tj, dmilburn, olof, Tuan Phan, linux-arm-kernel
On Wed, Jan 15, 2014 at 07:11:48AM +0000, Loc Ho wrote:
> Signed-off-by: Loc Ho <lho@apm.com>
> Signed-off-by: Tuan Phan <tphan@apm.com>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
> ---
> .../devicetree/bindings/ata/apm-xgene.txt | 68 ++++++++++++++++++++
> 1 files changed, 68 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
> new file mode 100644
> index 0000000..3d1421a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
> @@ -0,0 +1,68 @@
> +* APM X-Gene 6.0 Gb/s SATA host controller nodes
> +
> +SATA host controller nodes are defined to describe on-chip Serial ATA
> +controllers. Each SATA controller (pair of ports) have its own node.
> +
> +Required properties:
> +- compatible : Shall be "apm,xgene-ahci-sgmii" if mux'ed with SGMII
> + or "apm,xgene-ahci-pcie" if mux'ed with PCIe.
> +- reg : First memory resource shall be the AHCI memory
> + resource.
> + Second memory resource shall be the host controller
> + memory resource.
> +- interrupts : Interrupt mapping for SATA host controller IRQ.
s/Interrupt-mapping/interrupt-specifier/
> +- clocks : Reference to the clock entry.
> +- phys : PHY reference with parameter 0.
The specific value of the phy-specifier shouldn't matter to this
binding. What should matter is what it logically corresponds to.
> +- phy-names : Name of the PHY. Shall be "sata-6g".
Could you define phys in terms of phy-names please? It makes the
relationship clearer:
- phys: a list of phandles + phy-sciefiers, one for each entry in
phy-names
- phy-names: Should contain:
* "sata-6g" for the SATA PHY <notes about requirements go here>
Cheers,
Mark.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 11:18 ` Mark Rutland
0 siblings, 0 replies; 26+ messages in thread
From: Mark Rutland @ 2014-01-15 11:18 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 15, 2014 at 07:11:48AM +0000, Loc Ho wrote:
> Signed-off-by: Loc Ho <lho@apm.com>
> Signed-off-by: Tuan Phan <tphan@apm.com>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
> ---
> .../devicetree/bindings/ata/apm-xgene.txt | 68 ++++++++++++++++++++
> 1 files changed, 68 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
> new file mode 100644
> index 0000000..3d1421a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
> @@ -0,0 +1,68 @@
> +* APM X-Gene 6.0 Gb/s SATA host controller nodes
> +
> +SATA host controller nodes are defined to describe on-chip Serial ATA
> +controllers. Each SATA controller (pair of ports) have its own node.
> +
> +Required properties:
> +- compatible : Shall be "apm,xgene-ahci-sgmii" if mux'ed with SGMII
> + or "apm,xgene-ahci-pcie" if mux'ed with PCIe.
> +- reg : First memory resource shall be the AHCI memory
> + resource.
> + Second memory resource shall be the host controller
> + memory resource.
> +- interrupts : Interrupt mapping for SATA host controller IRQ.
s/Interrupt-mapping/interrupt-specifier/
> +- clocks : Reference to the clock entry.
> +- phys : PHY reference with parameter 0.
The specific value of the phy-specifier shouldn't matter to this
binding. What should matter is what it logically corresponds to.
> +- phy-names : Name of the PHY. Shall be "sata-6g".
Could you define phys in terms of phy-names please? It makes the
relationship clearer:
- phys: a list of phandles + phy-sciefiers, one for each entry in
phy-names
- phy-names: Should contain:
* "sata-6g" for the SATA PHY <notes about requirements go here>
Cheers,
Mark.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 11:18 ` Mark Rutland
@ 2014-01-15 20:04 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 20:04 UTC (permalink / raw)
To: Mark Rutland
Cc: olof, tj, arnd, linux-scsi, linux-ide, devicetree,
linux-arm-kernel, dmilburn, jcm, patches, Tuan Phan,
Suman Tripathi
Hi,
>> +- clocks : Reference to the clock entry.
>> +- phys : PHY reference with parameter 0.
>
> The specific value of the phy-specifier shouldn't matter to this
> binding. What should matter is what it logically corresponds to.
I not quite following this. Are you suggest that I drop the value 0.
In the binding, one needs to specify the mode of operation - 0 is for
SATA. Can you explain more?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 20:04 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 20:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
>> +- clocks : Reference to the clock entry.
>> +- phys : PHY reference with parameter 0.
>
> The specific value of the phy-specifier shouldn't matter to this
> binding. What should matter is what it logically corresponds to.
I not quite following this. Are you suggest that I drop the value 0.
In the binding, one needs to specify the mode of operation - 0 is for
SATA. Can you explain more?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 20:04 ` Loc Ho
@ 2014-01-15 20:10 ` Arnd Bergmann
-1 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-15 20:10 UTC (permalink / raw)
To: Loc Ho
Cc: Mark Rutland, olof, tj, linux-scsi, linux-ide, devicetree,
linux-arm-kernel, dmilburn, jcm, patches, Tuan Phan,
Suman Tripathi
On Wednesday 15 January 2014 12:04:02 Loc Ho wrote:
>
> >> +- clocks : Reference to the clock entry.
> >> +- phys : PHY reference with parameter 0.
> >
> > The specific value of the phy-specifier shouldn't matter to this
> > binding. What should matter is what it logically corresponds to.
>
> I not quite following this. Are you suggest that I drop the value 0.
> In the binding, one needs to specify the mode of operation - 0 is for
> SATA. Can you explain more?
The SATA device should not care what the argument for the PHY
device is. You could connect the same device to another PHY
that has a different set of arguments, which is the whole point
of abstracting it.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 20:10 ` Arnd Bergmann
0 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-15 20:10 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 15 January 2014 12:04:02 Loc Ho wrote:
>
> >> +- clocks : Reference to the clock entry.
> >> +- phys : PHY reference with parameter 0.
> >
> > The specific value of the phy-specifier shouldn't matter to this
> > binding. What should matter is what it logically corresponds to.
>
> I not quite following this. Are you suggest that I drop the value 0.
> In the binding, one needs to specify the mode of operation - 0 is for
> SATA. Can you explain more?
The SATA device should not care what the argument for the PHY
device is. You could connect the same device to another PHY
that has a different set of arguments, which is the whole point
of abstracting it.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 20:10 ` Arnd Bergmann
@ 2014-01-15 21:08 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 21:08 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, olof, tj, linux-scsi, linux-ide, devicetree,
linux-arm-kernel, dmilburn, jcm, patches, Tuan Phan,
Suman Tripathi
Hi,
>>
>> >> +- clocks : Reference to the clock entry.
>> >> +- phys : PHY reference with parameter 0.
>> >
>> > The specific value of the phy-specifier shouldn't matter to this
>> > binding. What should matter is what it logically corresponds to.
>>
>> I not quite following this. Are you suggest that I drop the value 0.
>> In the binding, one needs to specify the mode of operation - 0 is for
>> SATA. Can you explain more?
>
> The SATA device should not care what the argument for the PHY
> device is. You could connect the same device to another PHY
> that has a different set of arguments, which is the whole point
> of abstracting it.
>
I understand what you wrote here. We should not have an argument from
the host controller. Then my question is how should the PHY node
indicates that it needs to be configured itself as an SATA PHY?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 21:08 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 21:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
>>
>> >> +- clocks : Reference to the clock entry.
>> >> +- phys : PHY reference with parameter 0.
>> >
>> > The specific value of the phy-specifier shouldn't matter to this
>> > binding. What should matter is what it logically corresponds to.
>>
>> I not quite following this. Are you suggest that I drop the value 0.
>> In the binding, one needs to specify the mode of operation - 0 is for
>> SATA. Can you explain more?
>
> The SATA device should not care what the argument for the PHY
> device is. You could connect the same device to another PHY
> that has a different set of arguments, which is the whole point
> of abstracting it.
>
I understand what you wrote here. We should not have an argument from
the host controller. Then my question is how should the PHY node
indicates that it needs to be configured itself as an SATA PHY?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 21:08 ` Loc Ho
@ 2014-01-15 21:12 ` Arnd Bergmann
-1 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-15 21:12 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Loc Ho, Mark Rutland, devicetree, Suman Tripathi, linux-scsi,
linux-ide, jcm, patches, tj, dmilburn, olof, Tuan Phan
On Wednesday 15 January 2014 13:08:47 Loc Ho wrote:
> >> >> +- clocks : Reference to the clock entry.
> >> >> +- phys : PHY reference with parameter 0.
> >> >
> >> > The specific value of the phy-specifier shouldn't matter to this
> >> > binding. What should matter is what it logically corresponds to.
> >>
> >> I not quite following this. Are you suggest that I drop the value 0.
> >> In the binding, one needs to specify the mode of operation - 0 is for
> >> SATA. Can you explain more?
> >
> > The SATA device should not care what the argument for the PHY
> > device is. You could connect the same device to another PHY
> > that has a different set of arguments, which is the whole point
> > of abstracting it.
> >
>
> I understand what you wrote here. We should not have an argument from
> the host controller. Then my question is how should the PHY node
> indicates that it needs to be configured itself as an SATA PHY?
The "phys" property should specify whatever the configuration of
the phy device is supposed to be. It's just not the business of
the sata driver or the sata binding to know what that configuration
is.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 21:12 ` Arnd Bergmann
0 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-15 21:12 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 15 January 2014 13:08:47 Loc Ho wrote:
> >> >> +- clocks : Reference to the clock entry.
> >> >> +- phys : PHY reference with parameter 0.
> >> >
> >> > The specific value of the phy-specifier shouldn't matter to this
> >> > binding. What should matter is what it logically corresponds to.
> >>
> >> I not quite following this. Are you suggest that I drop the value 0.
> >> In the binding, one needs to specify the mode of operation - 0 is for
> >> SATA. Can you explain more?
> >
> > The SATA device should not care what the argument for the PHY
> > device is. You could connect the same device to another PHY
> > that has a different set of arguments, which is the whole point
> > of abstracting it.
> >
>
> I understand what you wrote here. We should not have an argument from
> the host controller. Then my question is how should the PHY node
> indicates that it needs to be configured itself as an SATA PHY?
The "phys" property should specify whatever the configuration of
the phy device is supposed to be. It's just not the business of
the sata driver or the sata binding to know what that configuration
is.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 21:12 ` Arnd Bergmann
@ 2014-01-15 22:07 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 22:07 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, Mark Rutland, devicetree, Suman Tripathi,
linux-scsi, linux-ide, jcm, patches, tj, dmilburn, olof,
Tuan Phan
Hi,
>> >> >> +- clocks : Reference to the clock entry.
>> >> >> +- phys : PHY reference with parameter 0.
>> >> >
>> >> > The specific value of the phy-specifier shouldn't matter to this
>> >> > binding. What should matter is what it logically corresponds to.
>> >>
>> >> I not quite following this. Are you suggest that I drop the value 0.
>> >> In the binding, one needs to specify the mode of operation - 0 is for
>> >> SATA. Can you explain more?
>> >
>> > The SATA device should not care what the argument for the PHY
>> > device is. You could connect the same device to another PHY
>> > that has a different set of arguments, which is the whole point
>> > of abstracting it.
>> >
>>
>> I understand what you wrote here. We should not have an argument from
>> the host controller. Then my question is how should the PHY node
>> indicates that it needs to be configured itself as an SATA PHY?
>
> The "phys" property should specify whatever the configuration of
> the phy device is supposed to be. It's just not the business of
> the sata driver or the sata binding to know what that configuration
> is.
>
Here is what I have and I am trying to piece this together:
phy1 {
#phy-cells = <0>; /* No parameter as suggest by Mark */
};
sata1 {
:::
phys = <&phy1>;
};
What I don't get is how does one specify the mode
(SATA/USB/SGMII/etc)? As another parameter in the phy1 node?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 22:07 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 22:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
>> >> >> +- clocks : Reference to the clock entry.
>> >> >> +- phys : PHY reference with parameter 0.
>> >> >
>> >> > The specific value of the phy-specifier shouldn't matter to this
>> >> > binding. What should matter is what it logically corresponds to.
>> >>
>> >> I not quite following this. Are you suggest that I drop the value 0.
>> >> In the binding, one needs to specify the mode of operation - 0 is for
>> >> SATA. Can you explain more?
>> >
>> > The SATA device should not care what the argument for the PHY
>> > device is. You could connect the same device to another PHY
>> > that has a different set of arguments, which is the whole point
>> > of abstracting it.
>> >
>>
>> I understand what you wrote here. We should not have an argument from
>> the host controller. Then my question is how should the PHY node
>> indicates that it needs to be configured itself as an SATA PHY?
>
> The "phys" property should specify whatever the configuration of
> the phy device is supposed to be. It's just not the business of
> the sata driver or the sata binding to know what that configuration
> is.
>
Here is what I have and I am trying to piece this together:
phy1 {
#phy-cells = <0>; /* No parameter as suggest by Mark */
};
sata1 {
:::
phys = <&phy1>;
};
What I don't get is how does one specify the mode
(SATA/USB/SGMII/etc)? As another parameter in the phy1 node?
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 22:07 ` Loc Ho
@ 2014-01-15 23:59 ` Loc Ho
-1 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 23:59 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, Mark Rutland, devicetree, Suman Tripathi,
linux-scsi, linux-ide, jcm, patches, tj, dmilburn, olof,
Tuan Phan
Hi,
>>> >> >> +- clocks : Reference to the clock entry.
>>> >> >> +- phys : PHY reference with parameter 0.
>>> >> >
>>> >> > The specific value of the phy-specifier shouldn't matter to this
>>> >> > binding. What should matter is what it logically corresponds to.
>>> >>
>>> >> I not quite following this. Are you suggest that I drop the value 0.
>>> >> In the binding, one needs to specify the mode of operation - 0 is for
>>> >> SATA. Can you explain more?
>>> >
>>> > The SATA device should not care what the argument for the PHY
>>> > device is. You could connect the same device to another PHY
>>> > that has a different set of arguments, which is the whole point
>>> > of abstracting it.
>>> >
>>>
>>> I understand what you wrote here. We should not have an argument from
>>> the host controller. Then my question is how should the PHY node
>>> indicates that it needs to be configured itself as an SATA PHY?
>>
>> The "phys" property should specify whatever the configuration of
>> the phy device is supposed to be. It's just not the business of
>> the sata driver or the sata binding to know what that configuration
>> is.
>>
>
> Here is what I have and I am trying to piece this together:
>
> phy1 {
> #phy-cells = <0>; /* No parameter as suggest by Mark */
> };
>
> sata1 {
> :::
> phys = <&phy1>;
> };
>
> What I don't get is how does one specify the mode
> (SATA/USB/SGMII/etc)? As another parameter in the phy1 node?
>
May be I misread what Mark mentioned. The binding documentation should
not specify the requirement of 0. And the binding of the dts should be
as is:
phy1 {
#phy-cells = <1>;
};
sata1 {
:::
phys = <&phy1 0>; where 0 indicates the mode of operation?
};
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-15 23:59 ` Loc Ho
0 siblings, 0 replies; 26+ messages in thread
From: Loc Ho @ 2014-01-15 23:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
>>> >> >> +- clocks : Reference to the clock entry.
>>> >> >> +- phys : PHY reference with parameter 0.
>>> >> >
>>> >> > The specific value of the phy-specifier shouldn't matter to this
>>> >> > binding. What should matter is what it logically corresponds to.
>>> >>
>>> >> I not quite following this. Are you suggest that I drop the value 0.
>>> >> In the binding, one needs to specify the mode of operation - 0 is for
>>> >> SATA. Can you explain more?
>>> >
>>> > The SATA device should not care what the argument for the PHY
>>> > device is. You could connect the same device to another PHY
>>> > that has a different set of arguments, which is the whole point
>>> > of abstracting it.
>>> >
>>>
>>> I understand what you wrote here. We should not have an argument from
>>> the host controller. Then my question is how should the PHY node
>>> indicates that it needs to be configured itself as an SATA PHY?
>>
>> The "phys" property should specify whatever the configuration of
>> the phy device is supposed to be. It's just not the business of
>> the sata driver or the sata binding to know what that configuration
>> is.
>>
>
> Here is what I have and I am trying to piece this together:
>
> phy1 {
> #phy-cells = <0>; /* No parameter as suggest by Mark */
> };
>
> sata1 {
> :::
> phys = <&phy1>;
> };
>
> What I don't get is how does one specify the mode
> (SATA/USB/SGMII/etc)? As another parameter in the phy1 node?
>
May be I misread what Mark mentioned. The binding documentation should
not specify the requirement of 0. And the binding of the dts should be
as is:
phy1 {
#phy-cells = <1>;
};
sata1 {
:::
phys = <&phy1 0>; where 0 indicates the mode of operation?
};
-Loc
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
2014-01-15 23:59 ` Loc Ho
@ 2014-01-16 10:38 ` Arnd Bergmann
-1 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-16 10:38 UTC (permalink / raw)
To: Loc Ho
Cc: Mark Rutland, devicetree, Suman Tripathi, linux-scsi, dmilburn,
jcm, olof, patches, linux-ide, tj, Tuan Phan, linux-arm-kernel
On Wednesday 15 January 2014 15:59:27 Loc Ho wrote:
>
> May be I misread what Mark mentioned. The binding documentation should
> not specify the requirement of 0. And the binding of the dts should be
> as is:
>
> phy1 {
> #phy-cells = <1>;
> };
>
> sata1 {
> :::
> phys = <&phy1 0>; where 0 indicates the mode of operation?
> };
>
>
Yes, that is right. You can keep the zero in the example, but the
binding text must not require a specific phy to be used.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding
@ 2014-01-16 10:38 ` Arnd Bergmann
0 siblings, 0 replies; 26+ messages in thread
From: Arnd Bergmann @ 2014-01-16 10:38 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 15 January 2014 15:59:27 Loc Ho wrote:
>
> May be I misread what Mark mentioned. The binding documentation should
> not specify the requirement of 0. And the binding of the dts should be
> as is:
>
> phy1 {
> #phy-cells = <1>;
> };
>
> sata1 {
> :::
> phys = <&phy1 0>; where 0 indicates the mode of operation?
> };
>
>
Yes, that is right. You can keep the zero in the example, but the
binding text must not require a specific phy to be used.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2014-01-16 10:38 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-01-15 7:11 [PATCH v9 0/4] ata: Add APM X-Gene SoC SATA host controller support Loc Ho
2014-01-15 7:11 ` Loc Ho
2014-01-15 7:11 ` [PATCH v9 1/4] ata: Export required functions by APM X-Gene SATA driver Loc Ho
2014-01-15 7:11 ` Loc Ho
2014-01-15 7:11 ` [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding Loc Ho
2014-01-15 7:11 ` Loc Ho
2014-01-15 7:11 ` [PATCH v9 3/4] ata: Add APM X-Gene SoC SATA host controller driver Loc Ho
2014-01-15 7:11 ` Loc Ho
2014-01-15 7:11 ` [PATCH v9 4/4] arm64: Add APM X-Gene SoC SATA host controller DTS entries Loc Ho
2014-01-15 7:11 ` Loc Ho
2014-01-15 11:18 ` [PATCH v9 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding Mark Rutland
2014-01-15 11:18 ` Mark Rutland
2014-01-15 20:04 ` Loc Ho
2014-01-15 20:04 ` Loc Ho
2014-01-15 20:10 ` Arnd Bergmann
2014-01-15 20:10 ` Arnd Bergmann
2014-01-15 21:08 ` Loc Ho
2014-01-15 21:08 ` Loc Ho
2014-01-15 21:12 ` Arnd Bergmann
2014-01-15 21:12 ` Arnd Bergmann
2014-01-15 22:07 ` Loc Ho
2014-01-15 22:07 ` Loc Ho
2014-01-15 23:59 ` Loc Ho
2014-01-15 23:59 ` Loc Ho
2014-01-16 10:38 ` Arnd Bergmann
2014-01-16 10:38 ` Arnd Bergmann
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