[U-Boot] [Patch v2] spi: mxc-spi: fixes for ECSPI

[U-Boot] [Patch v2] spi: mxc-spi: fixes for ECSPI

[Markus Niebel]

This series improver the original one:

- split first patch into two patches
- add only the register fields that are needed for clk control
- better comments

[PATCH 1/3] spi: spi-mxc: add defines for clk inactive state for
[PATCH 2/3] spi: spi-mxc: implement clk control for ECSPI to fix
[PATCH 3/3] spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller

[U-Boot] [PATCH v2 1/3] spi: spi-mxc: add defines for clk inactive state for ECSPI

[Markus Niebel]

From: Markus Niebel <Markus.Niebel@tq-group.de>

Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
---
changes for v2:
- split first patch into header changes (defines) and driver changes
- define only register flags that are used in pathches of this series
---
 arch/arm/include/asm/arch-mx5/imx-regs.h |    7 ++++---
 arch/arm/include/asm/arch-mx6/imx-regs.h |    7 ++++---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4955ccf..054c680 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -230,9 +230,10 @@
 #define MXC_CSPICTRL_CHAN	18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #define MXC_SPI_BASE_ADDRESSES \
 	CSPI1_BASE_ADDR, \
 	CSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f2ad6e9..3c58c01 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -405,9 +405,10 @@ struct cspi_regs {
 #define MXC_CSPICTRL_CHAN	18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #ifdef CONFIG_MX6SL
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
-- 
1.7.9.5

[U-Boot] [PATCH v2 2/3] spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3

[Markus Niebel]

From: Markus Niebel <Markus.Niebel@tqs.de>

SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
---
changes for v2:
- split original patch into two 
- improve commit message
---
 drivers/spi/mxc_spi.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 95dd03f..f3f029d 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -115,7 +115,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 {
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 	s32 reg_ctrl, reg_config;
-	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
+	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
+	u32 pre_div = 0, post_div = 0;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 
 	if (max_hz == 0) {
@@ -164,8 +165,10 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ss_pol = 1;
 
-	if (mode & SPI_CPOL)
+	if (mode & SPI_CPOL) {
 		sclkpol = 1;
+		sclkctl = 1;
+	}
 
 	if (mode & SPI_CPHA)
 		sclkpha = 1;
@@ -180,6 +183,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		(ss_pol << (cs + MXC_CSPICON_SSPOL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
 		(sclkpol << (cs + MXC_CSPICON_POL));
+	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
+		(sclkctl << (cs + MXC_CSPICON_CTL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
 		(sclkpha << (cs + MXC_CSPICON_PHA));
 
-- 
1.7.9.5

[U-Boot] [PATCH v2 3/3] spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller

[Markus Niebel]

From: Markus Niebel <Markus.Niebel@tqs.de>

The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
---
changes for v2:
no changes
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3c58c01..26f2a88 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -409,7 +409,7 @@ struct cspi_regs {
 #define MXC_CSPICON_POL		4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
-#ifdef CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
-- 
1.7.9.5

[U-Boot] [Patch v2] spi: mxc-spi: fixes for ECSPI

[Jagan Teki]

On Mon, Feb 17, 2014 at 6:42 PM, Markus Niebel <list-09_u-boot@tqsc.de> wrote:
> This series improver the original one:
>
> - split first patch into two patches
> - add only the register fields that are needed for clk control
> - better comments
>
> [PATCH 1/3] spi: spi-mxc: add defines for clk inactive state for
> [PATCH 2/3] spi: spi-mxc: implement clk control for ECSPI to fix
> [PATCH 3/3] spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller

Seems like you manually edited this - please use --cover-letter (while
in git format-patch)

thanks!
-- 
Jagan.