[U-Boot] [PATCH v3 0/6] PPC 85xx: Add support for QEMU's ppce500 PV machine

[U-Boot] [PATCH v3 0/6] PPC 85xx: Add support for QEMU's ppce500 PV machine

[Alexander Graf]

In QEMU we implement a PV machine type called "ppce500". That board is able
to run any e500+ FSL cores (e500v2, e500mc, e5500, e6500).

It is heavily inspired by the MPC8544DS SoC and board combination, but
implements only the bare minimum to make Linux happy enough to drive a
virtual machine.

This patch set implements support for this PV machine type in U-Boot, enabling
users to run their virtual machines with netboot, u-boot payload binaries or
other fun things they come up with.

---

v1 -> v2:

  - Write device tree offset directly into global variable
  - use r4 rather than r2 for that
  - access fdt directly from in-memory copy
  - remove unneeded header includes
  - clean up pci enumeration
  - coding style fixes
  - populate and only use fdt_addr_r
  - remove unused exported functions
  - remove unused TLB0 entries
  - make TLB1 I/O maps non-executable
  - remove unused defines in board header
  - make -kernel boot variables more clear
  - remove TLB0 invalidation
  - use tlb1.14 for temporary as=1 map
  - use CONFIG_SYS_MPC85XX_NO_RESETVEC
  - store fdt pointer in gd through cpu_init_early_f()
  - replace fixup_tlb1() with dynamic TLB creation hook
  - find CCSRBAR from device tree
  - find PCI controllers from device tree
  - find CPU speed from device tree

v2 -> v3:

  - new patch: fdt_support: split fdt_getprop_u32_default
  - new patch: fdt_support: Add helper function to read "ranges" property
  - new patch: PPC: 85xx: Remove IVOR reset
  - removed patch: PPC 85xx: Detect e500v2 / e500mc during runtime
  - merge dt patches into machine patch
  - Document and rename CONFIG_SYS_USE_DYNAMIC_TLBS
  - remove CONFIG_DDR_SPD
  - Reduce PCI message to only base address
  - Map AS=1 fdt behind CCSRBAR
  - Use CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  - remove unnecessary ccsr map
  - s/cell size/cell count/
  - add temporary map define
  - use fdt_get_base_address() to find region
  - use new APIs
  - remove myfdt helpers

Alexander Graf (6):
  fdt_support: split fdt_getprop_u32_default
  fdt_support: Add helper function to read "ranges" property
  PPC: 85xx: Remove IVOR reset
  PPC: 85xx: Generalize DDR TLB mapping function
  PPC 85xx: Add ELF entry point
  PPC 85xx: Add qemu-ppce500 machine

 README                                       |    5 +
 arch/powerpc/cpu/mpc85xx/Makefile            |    2 +
 arch/powerpc/cpu/mpc85xx/cpu.c               |    3 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c          |    4 -
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c    |   10 +-
 arch/powerpc/cpu/mpc85xx/fixed_ivor.S        |   63 -----
 arch/powerpc/cpu/mpc85xx/release.S           |    3 -
 arch/powerpc/cpu/mpc85xx/start.S             |   19 +-
 arch/powerpc/cpu/mpc85xx/tlb.c               |   52 ++--
 arch/powerpc/cpu/mpc85xx/u-boot.lds          |    1 +
 arch/powerpc/include/asm/config_mpc85xx.h    |    4 +
 arch/powerpc/include/asm/mmu.h               |    3 +
 board/freescale/qemu-ppce500/Makefile        |   10 +
 board/freescale/qemu-ppce500/qemu-ppce500.c  |  334 ++++++++++++++++++++++++++
 board/freescale/qemu-ppce500/tlb.c           |   16 ++
 boards.cfg                                   |    1 +
 common/fdt_support.c                         |  132 +++++++++-
 include/configs/qemu-ppce500.h               |  206 ++++++++++++++++
 include/fdt_support.h                        |    4 +
 nand_spl/board/freescale/mpc8536ds/Makefile  |    4 -
 nand_spl/board/freescale/mpc8569mds/Makefile |    4 -
 nand_spl/board/freescale/mpc8572ds/Makefile  |    4 -
 nand_spl/board/freescale/p1023rds/Makefile   |    4 -
 nand_spl/board/freescale/p1_p2_rdb/Makefile  |    4 -
 24 files changed, 771 insertions(+), 121 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/fixed_ivor.S
 create mode 100644 board/freescale/qemu-ppce500/Makefile
 create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c
 create mode 100644 board/freescale/qemu-ppce500/tlb.c
 create mode 100644 include/configs/qemu-ppce500.h

-- 
1.7.10.4

[U-Boot] [PATCH v3 1/6] fdt_support: split fdt_getprop_u32_default

[Alexander Graf]

We already have a nice helper to give us a property cell value with default
fall back from a path. Split that into two helpers - one for the old path
based lookup and one to give us a value based on a node offset.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 common/fdt_support.c  |   38 ++++++++++++++++++++++++++++++++------
 include/fdt_support.h |    2 ++
 2 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index b9dce99..65c68f9 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -50,6 +50,37 @@ static void write_cell(u8 *addr, u64 val, int size)
 }
 
 /**
+ * fdt_getprop_u32_default_node - Return a node's property or a default
+ *
+ * @fdt: ptr to device tree
+ * @off: offset of node
+ * @cell: cell offset in property
+ * @prop: property name
+ * @dflt: default value if the property isn't found
+ *
+ * Convenience function to return a node's property or a default value if
+ * the property doesn't exist.
+ */
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt)
+{
+	const fdt32_t *val;
+	int len;
+
+	val = fdt_getprop(fdt, off, prop, &len);
+
+	/* Check if property exists */
+	if (!val)
+		return dflt;
+
+	/* Check if property is long enough */
+	if (len < ((cell + 1) * sizeof(uint32_t)))
+		return dflt;
+
+	return fdt32_to_cpu(*val);
+}
+
+/**
  * fdt_getprop_u32_default - Find a node and return it's property or a default
  *
  * @fdt: ptr to device tree
@@ -63,18 +94,13 @@ static void write_cell(u8 *addr, u64 val, int size)
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt)
 {
-	const fdt32_t *val;
 	int off;
 
 	off = fdt_path_offset(fdt, path);
 	if (off < 0)
 		return dflt;
 
-	val = fdt_getprop(fdt, off, prop, NULL);
-	if (val)
-		return fdt32_to_cpu(*val);
-	else
-		return dflt;
+	return fdt_getprop_u32_default_node(fdt, off, 0, prop, dflt);
 }
 
 /**
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 9871e2f..3e1be57 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -12,6 +12,8 @@
 
 #include <libfdt.h>
 
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt);
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt);
 int fdt_chosen(void *fdt, int force);
-- 
1.7.10.4

[U-Boot] [PATCH v3 2/6] fdt_support: Add helper function to read "ranges" property

[Alexander Graf]

This patch adds a helper function that can be used to interpret most
"ranges" properties in the device tree.

It reads the n'th range out of a "ranges" array and returns the node's
virtual address of the range, the physical address that range starts at
and the size of the range.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 common/fdt_support.c  |   94 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/fdt_support.h |    2 ++
 2 files changed, 96 insertions(+)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 65c68f9..17fa852 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1435,3 +1435,97 @@ u64 fdt_get_base_address(void *fdt, int node)
 
 	return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
 }
+
+/*
+ * Read a property of size <prop_len>. Currently only supports 1 or 2 cells.
+ */
+static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off,
+			 uint64_t *val, int cells)
+{
+	const fdt32_t *prop32 = &prop[cell_off];
+	const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off];
+
+	if ((cell_off + cells) > prop_len)
+		return -FDT_ERR_NOSPACE;
+
+	switch (cells) {
+	case 1:
+		*val = fdt32_to_cpu(*prop32);
+		break;
+	case 2:
+		*val = fdt64_to_cpu(*prop64);
+		break;
+	default:
+		return -FDT_ERR_NOSPACE;
+	}
+
+	return 0;
+}
+
+/**
+ * fdt_read_range - Read a node's n'th range property
+ *
+ * @fdt: ptr to device tree
+ * @node: offset of node
+ * @n: range index
+ * @child_addr: pointer to storage for the "child address" field
+ * @addr: pointer to storage for the CPU view translated physical start
+ * @len: pointer to storage for the range length
+ *
+ * Convenience function that reads and interprets a specific range out of
+ * a number of the "ranges" property array.
+ */
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len)
+{
+	int pnode = fdt_parent_offset(fdt, node);
+	const fdt32_t *ranges;
+	int pacells;
+	int acells;
+	int scells;
+	int ranges_len;
+	int cell = 0;
+	int r = 0;
+
+	/*
+	 * The "ranges" property is an array of
+	 * { <child address> <parent address> <size in child address space> }
+	 *
+	 * All 3 elements can span a diffent number of cells. Fetch their size.
+	 */
+	pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1);
+	acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1);
+	scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1);
+
+	/* Now try to get the ranges property */
+	ranges = fdt_getprop(fdt, node, "ranges", &ranges_len);
+	if (!ranges)
+		return -FDT_ERR_NOTFOUND;
+	ranges_len /= sizeof(uint32_t);
+
+	/* Jump to the n'th entry */
+	cell = n * (pacells + acells + scells);
+
+	/* Read <child address> */
+	if (child_addr) {
+		r = fdt_read_prop(ranges, ranges_len, cell, child_addr,
+				  acells);
+		if (r)
+			return r;
+	}
+	cell += acells;
+
+	/* Read <parent address> */
+	if (addr)
+		*addr = fdt_translate_address(fdt, node, ranges + cell);
+	cell += pacells;
+
+	/* Read <size in child address space> */
+	if (len) {
+		r = fdt_read_prop(ranges, ranges_len, cell, len, scells);
+		if (r)
+			return r;
+	}
+
+	return 0;
+}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 3e1be57..b28fae6 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -87,6 +87,8 @@ int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
 int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
 			      u64 addr);
 u64 fdt_get_base_address(void *fdt, int node);
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len);
 
 enum fdt_status {
 	FDT_STATUS_OKAY,
-- 
1.7.10.4

[U-Boot] [PATCH v3 3/6] PPC: 85xx: Remove IVOR reset

[Alexander Graf]

There is no need to set IVORs to anything but their default values,
so let's leave them where they are.

Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c          |    4 --
 arch/powerpc/cpu/mpc85xx/fixed_ivor.S        |   63 --------------------------
 arch/powerpc/cpu/mpc85xx/release.S           |    3 --
 arch/powerpc/cpu/mpc85xx/start.S             |    6 ---
 nand_spl/board/freescale/mpc8536ds/Makefile  |    4 --
 nand_spl/board/freescale/mpc8569mds/Makefile |    4 --
 nand_spl/board/freescale/mpc8572ds/Makefile  |    4 --
 nand_spl/board/freescale/p1023rds/Makefile   |    4 --
 nand_spl/board/freescale/p1_p2_rdb/Makefile  |    4 --
 9 files changed, 96 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/fixed_ivor.S

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..a49f8dd 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -705,8 +705,6 @@ skip_l2:
 	return 0;
 }
 
-extern void setup_ivors(void);
-
 void arch_preboot_os(void)
 {
 	u32 msr;
@@ -719,8 +717,6 @@ void arch_preboot_os(void)
 	msr = mfmsr();
 	msr &= ~(MSR_ME|MSR_CE);
 	mtmsr(msr);
-
-	setup_ivors();
 }
 
 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
deleted file mode 100644
index ebbb8c0..0000000
--- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Kumar Gala <kumar.gala@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* This file is intended to be included by other asm code since
- * we will want to execute this on both the primary core when
- * it does a bootm and the secondary core's that get released
- * out of the spin table */
-
-#define SET_IVOR(vector_number, vector_offset)	\
-	li	r3,vector_offset at l; 		\
-	mtspr	SPRN_IVOR##vector_number,r3;
-
-#define SET_GIVOR(vector_number, vector_offset)	\
-	li	r3,vector_offset at l; 		\
-	mtspr	SPRN_GIVOR##vector_number,r3;
-
-	SET_IVOR(0, 0x020) /* Critical Input */
-	SET_IVOR(1, 0x000) /* Machine Check */
-	SET_IVOR(2, 0x060) /* Data Storage */
-	SET_IVOR(3, 0x080) /* Instruction Storage */
-	SET_IVOR(4, 0x0a0) /* External Input */
-	SET_IVOR(5, 0x0c0) /* Alignment */
-	SET_IVOR(6, 0x0e0) /* Program */
-	SET_IVOR(7, 0x100) /* FP Unavailable */
-	SET_IVOR(8, 0x120) /* System Call */
-	SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
-	SET_IVOR(10, 0x160) /* Decrementer */
-	SET_IVOR(11, 0x180) /* Fixed Interval Timer */
-	SET_IVOR(12, 0x1a0) /* Watchdog Timer */
-	SET_IVOR(13, 0x1c0) /* Data TLB Error */
-	SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
-	SET_IVOR(15, 0x040) /* Debug */
-
-/* e500v1 & e500v2 only */
-#ifndef CONFIG_E500MC
-	SET_IVOR(32, 0x200) /* SPE Unavailable */
-	SET_IVOR(33, 0x220) /* Embedded FP Data */
-	SET_IVOR(34, 0x240) /* Embedded FP Round */
-#endif
-
-	SET_IVOR(35, 0x260) /* Performance monitor */
-
-/* e500mc only */
-#ifdef CONFIG_E500MC
-	SET_IVOR(36, 0x280) /* Processor doorbell */
-	SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
-	SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
-	SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
-	SET_IVOR(40, 0x300) /* Hypervisor system call */
-	SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
-
-	SET_GIVOR(2, 0x060) /* Guest Data Storage */
-	SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
-	SET_GIVOR(4, 0x0a0) /* Guest External Input */
-	SET_GIVOR(8, 0x120) /* Guest System Call */
-	SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
-	SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
-#endif
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c15e83b..a37c7af 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -407,9 +407,6 @@ __second_half_boot_page:
 	bne	3b
 	isync
 
-	/* setup IVORs to match fixed offsets */
-#include "fixed_ivor.S"
-
 	/* get the upper bits of the addr */
 	lwz	r11,ENTRY_ADDR_UPPER(r10)
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..bb0025c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1967,10 +1967,4 @@ flush_dcache:
 	isync
 
 	blr
-
-.globl setup_ivors
-setup_ivors:
-
-#include "fixed_ivor.S"
-	blr
 #endif /* !MINIMAL_SPL */
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
index 6233081..becf644 100644
--- a/nand_spl/board/freescale/mpc8536ds/Makefile
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -80,10 +80,6 @@ $(obj)resetvec.S:
 	@rm -f $@
 	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $@
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
 $(obj)start.S: $(obj)fixed_ivor.S
 	@rm -f $@
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
index 6233081..becf644 100644
--- a/nand_spl/board/freescale/mpc8569mds/Makefile
+++ b/nand_spl/board/freescale/mpc8569mds/Makefile
@@ -80,10 +80,6 @@ $(obj)resetvec.S:
 	@rm -f $@
 	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $@
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
 $(obj)start.S: $(obj)fixed_ivor.S
 	@rm -f $@
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile
index 6233081..becf644 100644
--- a/nand_spl/board/freescale/mpc8572ds/Makefile
+++ b/nand_spl/board/freescale/mpc8572ds/Makefile
@@ -80,10 +80,6 @@ $(obj)resetvec.S:
 	@rm -f $@
 	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $@
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
 $(obj)start.S: $(obj)fixed_ivor.S
 	@rm -f $@
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index dbdfa19..98a6988 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -75,10 +75,6 @@ $(obj)resetvec.S:
 	@rm -f $@
 	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $@
-	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@
-
 $(obj)start.S: $(obj)fixed_ivor.S
 	@rm -f $@
 	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
index 6233081..becf644 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile
@@ -80,10 +80,6 @@ $(obj)resetvec.S:
 	@rm -f $@
 	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $@
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
 $(obj)start.S: $(obj)fixed_ivor.S
 	@rm -f $@
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
-- 
1.7.10.4

[U-Boot] [PATCH v3 4/6] PPC: 85xx: Generalize DDR TLB mapping function

[Alexander Graf]

The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/cpu/mpc85xx/tlb.c |   48 ++++++++++++++++++++++++++--------------
 arch/powerpc/include/asm/mmu.h |    3 +++
 2 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 8748ecd..2011fb8 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -236,20 +236,26 @@ void init_addr_map(void)
 }
 #endif
 
-unsigned int
-setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+void
+tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, bool is_ram)
 {
 	int i;
 	unsigned int tlb_size;
-	unsigned int wimge = MAS2_M;
-	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	unsigned int wimge;
+	unsigned int perm;
 	unsigned int max_cam, tsize_mask;
-	u64 size, memsize = (u64)memsize_in_meg << 20;
 
+	if (is_ram) {
+		perm = MAS3_SX|MAS3_SW|MAS3_SR;
+		wimge = MAS2_M;
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
-	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
+		wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
-	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+	} else {
+		perm = MAS3_SW|MAS3_SR;
+		wimge = MAS2_I|MAS2_G;
+	}
+
 	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 		/* Convert (4^max) kB to (2^max) bytes */
 		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
@@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	}
 
 	for (i = 0; size && i < 8; i++) {
-		int ram_tlb_index = find_free_tlbcam();
+		int tlb_index = find_free_tlbcam();
 		u32 camsize = __ilog2_u64(size) & tsize_mask;
-		u32 align = __ilog2(ram_tlb_address) & tsize_mask;
+		u32 align = __ilog2(v_addr) & tsize_mask;
 
-		if (ram_tlb_index == -1)
+		if (tlb_index == -1)
 			break;
 
 		if (align == -2) align = max_cam;
@@ -277,18 +283,26 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 
 		tlb_size = camsize - 10;
 
-		set_tlb(1, ram_tlb_address, p_addr,
-			MAS3_SX|MAS3_SW|MAS3_SR, wimge,
-			0, ram_tlb_index, tlb_size, 1);
+		set_tlb(1, v_addr, p_addr, perm, wimge,
+			0, tlb_index, tlb_size, 1);
 
 		size -= 1ULL << camsize;
-		memsize -= 1ULL << camsize;
-		ram_tlb_address += 1UL << camsize;
+		v_addr += 1UL << camsize;
 		p_addr += 1UL << camsize;
 	}
 
-	if (memsize)
-		print_size(memsize, " left unmapped\n");
+	if (size)
+		print_size(size, " left unmapped\n");
+}
+
+unsigned int
+setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+{
+	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	u64 memsize = (u64)memsize_in_meg << 20;
+
+	memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+	tlb_map_range(ram_tlb_address, p_addr, memsize, true);
 	return memsize_in_meg;
 }
 
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index cadaeef..5493c51 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -509,6 +509,9 @@ extern void print_tlbcam(void);
 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
 
+extern void tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+			  bool is_ram);
+
 extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
-- 
1.7.10.4

[U-Boot] [PATCH v3 5/6] PPC 85xx: Add ELF entry point

[Alexander Graf]

We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.

To know where we have to start executing this ELF binary  we have to
tell the linker where our entry point is.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/cpu/mpc85xx/u-boot.lds |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 2af4c80..b34d212 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -13,6 +13,7 @@
 #endif
 
 OUTPUT_ARCH(powerpc)
+ENTRY(_start_e500)
 
 PHDRS
 {
-- 
1.7.10.4

[U-Boot] [PATCH v3 6/6] PPC 85xx: Add qemu-ppce500 machine

[Alexander Graf]

For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v1 -> v2:

  - Write device tree offset directly into global variable
  - use r4 rather than r2 for that
  - access fdt directly from in-memory copy
  - remove unneeded header includes
  - clean up pci enumeration
  - coding style fixes
  - populate and only use fdt_addr_r
  - remove unused exported functions
  - remove unused TLB0 entries
  - make TLB1 I/O maps non-executable
  - remove unused defines in board header
  - make -kernel boot variables more clear
  - remove TLB0 invalidation
  - use tlb1.14 for temporary as=1 map
  - use CONFIG_SYS_MPC85XX_NO_RESETVEC
  - store fdt pointer in gd through cpu_init_early_f()
  - replace fixup_tlb1() with dynamic TLB creation hook

v2 -> v3:

  - merge dt patches into this one
  - Document and rename CONFIG_SYS_USE_DYNAMIC_TLBS
  - remove CONFIG_DDR_SPD
  - Reduce PCI message to only base address
  - Map AS=1 fdt behind CCSRBAR
  - Use CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  - remove unnecessary ccsr map
  - s/cell size/cell count/
  - add temporary map define
  - use fdt_get_base_address() to find region
  - use new APIs
  - remove myfdt helpers
---
 README                                      |    5 +
 arch/powerpc/cpu/mpc85xx/Makefile           |    2 +
 arch/powerpc/cpu/mpc85xx/cpu.c              |    3 +-
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c   |   10 +-
 arch/powerpc/cpu/mpc85xx/start.S            |   13 ++
 arch/powerpc/cpu/mpc85xx/tlb.c              |    4 +
 arch/powerpc/include/asm/config_mpc85xx.h   |    4 +
 board/freescale/qemu-ppce500/Makefile       |   10 +
 board/freescale/qemu-ppce500/qemu-ppce500.c |  334 +++++++++++++++++++++++++++
 board/freescale/qemu-ppce500/tlb.c          |   16 ++
 boards.cfg                                  |    1 +
 include/configs/qemu-ppce500.h              |  206 +++++++++++++++++
 12 files changed, 606 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/qemu-ppce500/Makefile
 create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c
 create mode 100644 board/freescale/qemu-ppce500/tlb.c
 create mode 100644 include/configs/qemu-ppce500.h

diff --git a/README b/README
index aea82be..5ae0514 100644
--- a/README
+++ b/README
@@ -379,6 +379,11 @@ The following options need to be configured:
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 
+		CONFIG_SYS_USE_DYNAMIC_TLBS
+
+		Create dynamic TLB entries in early CPU bringup. If you enable
+		this, make sure to implement void init_tlbs_dynamic(void).
+
 		CONFIG_SYS_FSL_ERRATUM_A004510
 
 		Enables a workaround for erratum A004510.  If set,
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index ef7637a..4094785 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -102,7 +102,9 @@ obj-y	+= cpu.o
 obj-y	+= cpu_init.o
 obj-y	+= cpu_init_early.o
 obj-y	+= interrupts.o
+ifneq ($(CONFIG_QEMU_E500),y)
 obj-y	+= speed.o
+endif
 obj-y	+= tlb.o
 obj-y	+= traps.o
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3e99b07..f1f366c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -338,7 +338,8 @@ void mpc85xx_reginfo(void)
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
+	defined(CONFIG_QEMU_E500)
 	return fsl_ddr_sdram_size();
 #else
 	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 993b8b8..b0ec9ea 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -79,7 +79,7 @@ void setup_ifc(void)
 #endif
 
 /* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
+void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 	int i;
@@ -102,6 +102,14 @@ void cpu_init_early_f(void)
 	for (i = 0; i < sizeof(gd_t); i++)
 		((char *)gd)[i] = 0;
 
+#ifdef CONFIG_QEMU_E500
+	/*
+	 * CONFIG_SYS_CCSRBAR_PHYS below will use gd->fdt_blob, so we need to
+	 * populate it before it accesses it.
+	 */
+	gd->fdt_blob = fdt;
+#endif
+
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index bb0025c..8982c78 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,6 +80,11 @@ _start_e500:
 	li	r1,MSR_DE
 	mtmsr 	r1
 
+#ifdef CONFIG_QEMU_E500
+	/* Save our ePAPR device tree pointer before we clobber it */
+	mr	r24, r3
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	mfspr	r3,SPRN_SVR
 	rlwinm	r3,r3,0,0xff
@@ -514,6 +519,7 @@ nexti:	mflr	r1		/* R1 = our PC */
  * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  * long-term TLBs, so we use TLB0 here.
  */
+#if !defined(CONFIG_DYNAMIC_CCSRBAR)
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 
 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
@@ -698,6 +704,7 @@ delete_temp_tlbs:
 	delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
 
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#endif /* #if !defined(CONFIG_DYNAMIC_CCSRBAR) */
 
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 create_ccsr_l2_tlb:
@@ -1144,6 +1151,12 @@ _start_cont:
 	mr	r1,r3		/* Transfer to SP(r1) */
 
 	GET_GOT
+
+#ifdef CONFIG_QEMU_E500
+	/* Pass the ePAPR device tree pointer to cpu_init_early_f */
+	mr	r3, r24
+#endif
+
 	bl	cpu_init_early_f
 
 	/* switch back to AS = 0 */
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 2011fb8..0e0b483 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -36,6 +36,10 @@ void init_tlbs(void)
 			  tlb_table[i].mas7);
 	}
 
+#ifdef CONFIG_SYS_USE_DYNAMIC_TLBS
+	init_tlbs_dynamic();
+#endif
+
 	return ;
 }
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..a0ab453 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -776,6 +776,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xe0000000
+
 #else
 #error Processor type not defined for this platform
 #endif
diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile
new file mode 100644
index 0000000..193b160
--- /dev/null
+++ b/board/freescale/qemu-ppce500/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= qemu-ppce500.o
+obj-y	+= tlb.o
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
new file mode 100644
index 0000000..fc546b9
--- /dev/null
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void *get_fdt(void)
+{
+	return (void *)gd->fdt_blob;
+}
+
+uint64_t get_phys_ccsrbar_addr_early(void)
+{
+	u32 mas0, mas1, mas2, mas3, mas7;
+	ulong fdt = (ulong)get_fdt();
+	uint64_t r;
+
+	/*
+	 * To be able to read the FDT we need to create a temporary TLB
+	 * map for it.
+	 */
+
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(10);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(fdt, 0);
+	mas3 = FSL_BOOKE_MAS3(fdt, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(fdt);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+	r = fdt_get_base_address(get_fdt(), fdt_path_offset(get_fdt(), "/soc"));
+
+	disable_tlb(10);
+
+	return r;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	return 0;
+}
+
+static int pci_map_region(void *fdt, int pci_node, int range_id,
+			  phys_size_t *ppaddr, pci_addr_t *pvaddr,
+			  pci_size_t *psize, ulong *pmap_addr)
+{
+	uint64_t addr;
+	uint64_t size;
+	ulong map_addr;
+	int r;
+
+	r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+	if (r)
+		return r;
+
+	if (ppaddr)
+		*ppaddr = addr;
+	if (psize)
+		*psize = size;
+
+	if (!pmap_addr)
+		return 0;
+
+	map_addr = *pmap_addr;
+
+	/* Align map_addr */
+	map_addr += size - 1;
+	map_addr &= ~(size - 1);
+
+	/* Map virtual memory for range */
+	tlb_map_range(map_addr, addr, size, false);
+	*pmap_addr = map_addr + size;
+
+	if (pvaddr)
+		*pvaddr = map_addr;
+
+	return 0;
+}
+
+void pci_init_board(void)
+{
+	struct pci_controller *pci_hoses;
+	void *fdt = get_fdt();
+	int pci_node;
+	int pci_num = 0;
+	int pci_count = 0;
+	const char *compat = "fsl,mpc8540-pci";
+	ulong map_addr;
+
+	puts("\n");
+
+	/* Start MMIO and PIO range maps above RAM */
+	map_addr = CONFIG_MAX_MEM_MAPPED;
+
+	/* Count and allocate PCI buses */
+	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
+	while (pci_node != -FDT_ERR_NOTFOUND) {
+		pci_node = fdt_node_offset_by_compatible(fdt, pci_node, compat);
+		pci_count++;
+	}
+
+	if (pci_count) {
+		pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
+	} else {
+		printf("PCI: disabled\n\n");
+		return;
+	}
+
+	/* Spawn PCI buses based on device tree */
+	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
+	while (pci_node != -FDT_ERR_NOTFOUND) {
+		struct fsl_pci_info pci_info = { };
+		const fdt32_t *reg;
+		int r;
+
+		reg = fdt_getprop(fdt, pci_node, "reg", NULL);
+		pci_info.regs = fdt_translate_address((void *)fdt, pci_node, reg);
+
+		/* Map MMIO range */
+		r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
+				   &pci_info.mem_size, &map_addr);
+		if (r)
+			break;
+
+		/* Map PIO range */
+		r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
+				   &pci_info.io_size, &map_addr);
+		if (r)
+			break;
+
+		/*
+		 * The PCI framework finds virtual addresses for the buses
+		 * through our address map, so tell it the physical addresses.
+		 */
+		pci_info.mem_bus = pci_info.mem_phys;
+		pci_info.io_bus = pci_info.io_phys;
+
+		/* Instantiate */
+		pci_info.pci_num = pci_num + 1;
+
+		fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
+		printf("PCI: base address %lx\n", pci_info.regs);
+
+		fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
+
+		/* Jump to next PCI node */
+		pci_node = fdt_node_offset_by_compatible(fdt, pci_node, compat);
+		pci_num++;
+	}
+
+	puts("\n");
+}
+
+int last_stage_init(void)
+{
+	void *fdt = get_fdt();
+	int len = 0;
+	const uint64_t *prop;
+	int chosen;
+
+	chosen = fdt_path_offset(fdt, "/chosen");
+	if (chosen < 0) {
+		printf("Couldn't find /chosen node in fdt\n");
+		return -EIO;
+	}
+
+	/* -kernel boot */
+	prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
+	if (prop && (len >= 8))
+		setenv_hex("qemu_kernel_addr", *prop);
+
+	/* Give the user a variable for the host fdt */
+	setenv_hex("fdt_addr_r", (ulong)fdt);
+
+	return 0;
+}
+
+static uint64_t get_linear_ram_size(void)
+{
+	void *fdt = get_fdt();
+	const void *prop;
+	int memory;
+	int len;
+
+	memory = fdt_path_offset(fdt, "/memory");
+	prop = fdt_getprop(fdt, memory, "reg", &len);
+
+	if (prop && len >= 16)
+		return *(uint64_t *)(prop+8);
+
+	panic("Couldn't determine RAM size");
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
+#endif
+
+void print_laws(void)
+{
+	/* We don't emulate LAWs yet */
+}
+
+phys_size_t fixed_sdram(void)
+{
+	return get_linear_ram_size();
+}
+
+phys_size_t fsl_ddr_sdram_size(void)
+{
+	return get_linear_ram_size();
+}
+
+void init_tlbs_dynamic(void)
+{
+	unsigned long fdt_phys = (unsigned long)get_fdt();
+	unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
+	unsigned long fdt_virt_tlb = CONFIG_SYS_TMPVIRT;
+	unsigned long fdt_virt = fdt_virt_tlb + (fdt_phys & 0xffffful);
+	u32 mas0, mas1, mas2, mas3, mas7;
+	phys_size_t ram_size;
+
+	/*
+	 * Create a temporary AS=1 map for the fdt
+	 *
+	 * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
+	 * which was only 4k big. This way we don't have to clear any other maps.
+	 */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
+	mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+	gd->fdt_blob = (void *)fdt_virt;
+
+	/* Fetch RAM size from the fdt */
+	ram_size = fixed_sdram();
+
+	/* And remove our fdt map again */
+	gd->fdt_blob = (void *)fdt_phys;
+	disable_tlb(0);
+
+	/* Create a dynamic AS=0 CCSRBAR mapping */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+	/* Create a RAM map that spans all accessible RAM */
+	init_used_tlb_cams();
+	setup_ddr_tlbs(ram_size >> 20);
+}
+
+void init_laws(void)
+{
+	/* We don't emulate LAWs yet */
+}
+
+static uint32_t get_cpu_freq(void)
+{
+	void *fdt = get_fdt();
+	int cpus_node = fdt_path_offset(fdt, "/cpus");
+	int cpu_node = fdt_first_subnode(fdt, cpus_node);
+	const char *prop = "clock-frequency";
+	return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+	int freq = get_cpu_freq();
+
+	memset(sys_info, 0, sizeof(sys_info_t));
+	sys_info->freq_systembus = freq;
+	sys_info->freq_ddrbus = freq;
+	sys_info->freq_processor[0] = freq;
+}
+
+int get_clocks (void)
+{
+	sys_info_t sys_info;
+
+	get_sys_info(&sys_info);
+
+	gd->cpu_clk = sys_info.freq_processor[0];
+	gd->bus_clk = sys_info.freq_systembus;
+	gd->mem_clk = sys_info.freq_ddrbus;
+	gd->arch.lbc_clk = sys_info.freq_ddrbus;
+
+	return 0;
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+	sys_info_t sys_info;
+	get_sys_info(&sys_info);
+	return sys_info.freq_systembus;
+}
diff --git a/board/freescale/qemu-ppce500/tlb.c b/board/freescale/qemu-ppce500/tlb.c
new file mode 100644
index 0000000..cf51d0e
--- /dev/null
+++ b/board/freescale/qemu-ppce500/tlb.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index d177f82..ab50982 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -986,6 +986,7 @@ Active  powerpc     mpc85xx        -           freescale       t2080qds
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SPIFLASH     T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_NAND         T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SRIO_PCIE_BOOT  T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+Active  powerpc     mpc85xx        -           freescale       qemu-ppce500        qemu-ppce500                         -                                                                                                                                 Alexander Graf <agraf@suse.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD          controlcenterd:36BIT,SDCARD                                                                                                       Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD_DEVELOP  controlcenterd:36BIT,SDCARD,DEVELOP                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER           controlcenterd:TRAILBLAZER,SPIFLASH                                                                                               Dirk Eibach <eibach@gdsys.de>
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
new file mode 100644
index 0000000..1918a50
--- /dev/null
+++ b/include/configs/qemu-ppce500.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __QEMU_PPCE500_H
+#define __QEMU_PPCE500_H
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
+#define CONFIG_QEMU_E500
+
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
+
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+
+#define CONFIG_SYS_RAMBOOT
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_USE_DYNAMIC_TLBS
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/* Needed to fill the ccsrbar pointer */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Virtual address to CCSRBAR */
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+/* Physical address should be a function call */
+#ifndef __ASSEMBLY__
+extern unsigned long long get_phys_ccsrbar_addr_early(void);
+#endif
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_DYNAMIC_CCSRBAR
+
+/* Virtual address to a temporary map if we need it (max 128MB) */
+#define CONFIG_SYS_TMPVIRT		0xe8000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	0
+
+#define CONFIG_SYS_CLK_FREQ        33000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+#define CONFIG_LBA48
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_BOOTDELAY        1
+#define CONFIG_BOOTCOMMAND		\
+	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
+
+#endif	/* __QEMU_PPCE500_H */
-- 
1.7.10.4

[U-Boot] [PATCH v3 4/6] PPC: 85xx: Generalize DDR TLB mapping function

[Scott Wood]

On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
> -	if (memsize)
> -		print_size(memsize, " left unmapped\n");
> +	if (size)
> +		print_size(size, " left unmapped\n");
> +}

The print_size should move to the caller, with some way to pass back the
amout left unmapped.  Non-RAM callers would treat a non-zero unmapped
value as an error.

> +unsigned int
> +setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
> +{
> +	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
> +	u64 memsize = (u64)memsize_in_meg << 20;
> +
> +	memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
> +	tlb_map_range(ram_tlb_address, p_addr, memsize, true);
>  	return memsize_in_meg;
>  }

Here you seem to be hiding the message for RAM.

York, are you OK with just removing the message altogether, and having
tlb_map_range return a normal error code if it can't map everything
(with DDR size reduced in advance as above)?

> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index cadaeef..5493c51 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -509,6 +509,9 @@ extern void print_tlbcam(void);
>  extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
>  extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
>  
> +extern void tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
> +			  bool is_ram);

bool arguments tend to be hard to read at call sites -- flags (or enum)
with something like MAP_RAM/MAP_IO would be nicer (I'm not insisting,
though).

-Scott

[U-Boot] [PATCH v3 6/6] PPC 85xx: Add qemu-ppce500 machine

[Scott Wood]

On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
> diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
> index bb0025c..8982c78 100644
> --- a/arch/powerpc/cpu/mpc85xx/start.S
> +++ b/arch/powerpc/cpu/mpc85xx/start.S
> @@ -80,6 +80,11 @@ _start_e500:
>  	li	r1,MSR_DE
>  	mtmsr 	r1
>  
> +#ifdef CONFIG_QEMU_E500
> +	/* Save our ePAPR device tree pointer before we clobber it */
> +	mr	r24, r3
> +#endif

FWIW, it should be harmless to do this unconditionally (though in that
case I'd insert "(if we have one)" in the comment.

>  #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
>  	mfspr	r3,SPRN_SVR
>  	rlwinm	r3,r3,0,0xff
> @@ -514,6 +519,7 @@ nexti:	mflr	r1		/* R1 = our PC */
>   * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
>   * long-term TLBs, so we use TLB0 here.
>   */
> +#if !defined(CONFIG_DYNAMIC_CCSRBAR)
>  #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)

This shouldn't be necessary, if you have
CONFIG_SYS_CCSR_DO_NOT_RELOCATE.

> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
> index 2011fb8..0e0b483 100644
> --- a/arch/powerpc/cpu/mpc85xx/tlb.c
> +++ b/arch/powerpc/cpu/mpc85xx/tlb.c
> @@ -36,6 +36,10 @@ void init_tlbs(void)
>  			  tlb_table[i].mas7);
>  	}
>  
> +#ifdef CONFIG_SYS_USE_DYNAMIC_TLBS
> +	init_tlbs_dynamic();
> +#endif

You could avoid the ifdef by moving a stub implementation into the
header -- or possibly better, avoid the config symbol entirely by using
a weak symbol.

Better still, make init_tlbs() weak.  Then you don't need a config
symbol, a new function name, or a dummy tlb_table[] -- you just redefine
init_tlbs() in board code.

> diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
> new file mode 100644
> index 0000000..fc546b9
> --- /dev/null
> +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
> @@ -0,0 +1,334 @@
> +/*
> + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <pci.h>
> +#include <asm/processor.h>
> +#include <asm/mmu.h>
> +#include <asm/fsl_pci.h>
> +#include <asm/io.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +#include <netdev.h>
> +#include <fdtdec.h>
> +#include <errno.h>
> +#include <malloc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void *get_fdt(void)
> +{
> +	return (void *)gd->fdt_blob;
> +}

Does this return virtual or physical?

> +
> +uint64_t get_phys_ccsrbar_addr_early(void)
> +{
> +	u32 mas0, mas1, mas2, mas3, mas7;
> +	ulong fdt = (ulong)get_fdt();
> +	uint64_t r;
> +
> +	/*
> +	 * To be able to read the FDT we need to create a temporary TLB
> +	 * map for it.
> +	 */
> +
> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(10);
> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
> +	mas2 = FSL_BOOKE_MAS2(fdt, 0);
> +	mas3 = FSL_BOOKE_MAS3(fdt, 0, MAS3_SW|MAS3_SR);
> +	mas7 = FSL_BOOKE_MAS7(fdt);

Don't use the physical address as a virtual address.  Use a known-good
virtual address.  Using unknown physical addresses as virtual addresses
is generally a bad idea (it's different for stuff whose physical address
is hardcoded in U-Boot), but it's particularly bad here because you'll
create an overlapping TLB entry if the fdt happens to live within your
initial memory mapping.

OK, I see you use CONFIG_SYS_TMPVIRT for this elsewhere, but I guess
forgot to use it here (why is fdt mapping code duplicated?).

> +void pci_init_board(void)
> +{
> +	struct pci_controller *pci_hoses;
> +	void *fdt = get_fdt();
> +	int pci_node;
> +	int pci_num = 0;
> +	int pci_count = 0;
> +	const char *compat = "fsl,mpc8540-pci";
> +	ulong map_addr;

May want to look for arbitrary PCI host controllers (device_type would
be simplest), in case the QEMU machine ever gets an upgrade to PCIe.

> +
> +	puts("\n");
> +
> +	/* Start MMIO and PIO range maps above RAM */
> +	map_addr = CONFIG_MAX_MEM_MAPPED;

It'd be better to hardcode virtual addresses for this (as other boards
do), and limit the size you map to the smaller of the hardcoded size or
the device tree size.

> +	/* Count and allocate PCI buses */
> +	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
> +	while (pci_node != -FDT_ERR_NOTFOUND) {
> +		pci_node = fdt_node_offset_by_compatible(fdt, pci_node, compat);
> +		pci_count++;
> +	}
> +
> +	if (pci_count) {
> +		pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
> +	} else {
> +		printf("PCI: disabled\n\n");
> +		return;
> +	}
> +
> +	/* Spawn PCI buses based on device tree */
> +	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
> +	while (pci_node != -FDT_ERR_NOTFOUND) {
> +		struct fsl_pci_info pci_info = { };
> +		const fdt32_t *reg;
> +		int r;
> +
> +		reg = fdt_getprop(fdt, pci_node, "reg", NULL);
> +		pci_info.regs = fdt_translate_address((void *)fdt, pci_node, reg);

Unnecessary cast.

> +void init_tlbs_dynamic(void)
> +{
> +	unsigned long fdt_phys = (unsigned long)get_fdt();
> +	unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
> +	unsigned long fdt_virt_tlb = CONFIG_SYS_TMPVIRT;
> +	unsigned long fdt_virt = fdt_virt_tlb + (fdt_phys & 0xffffful);
> +	u32 mas0, mas1, mas2, mas3, mas7;
> +	phys_size_t ram_size;
> +
> +	/*
> +	 * Create a temporary AS=1 map for the fdt
> +	 *
> +	 * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
> +	 * which was only 4k big. This way we don't have to clear any other maps.
> +	 */

I don't think it's generally safe to assume that this entry is ESEL 0 --
though I'm wondering if the current TLB code is assuming that (or at
least, assuming that whatever entry is used gets overwritten by the TLB
table).

> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
> +	mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
> +	mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
> +	mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);

What if the fdt straddles a 1M boundary?

> +	write_tlb(mas0, mas1, mas2, mas3, mas7);
> +	gd->fdt_blob = (void *)fdt_virt;
> +
> +	/* Fetch RAM size from the fdt */
> +	ram_size = fixed_sdram();

Why not just call get_linear_ram_size() directly?

> +	/* And remove our fdt map again */
> +	gd->fdt_blob = (void *)fdt_phys;
> +	disable_tlb(0);
> +
> +	/* Create a dynamic AS=0 CCSRBAR mapping */
> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TSIZE(BOOKE_PAGESZ_1M);
> +	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
> +	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
> +	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
> +
> +	write_tlb(mas0, mas1, mas2, mas3, mas7);

Why is this not done via tlb_map_range (after calling
init_used_tlb_cams, of course)?

> +
> +	/* Create a RAM map that spans all accessible RAM */
> +	init_used_tlb_cams();
> +	setup_ddr_tlbs(ram_size >> 20);
> +}
> +
> +void init_laws(void)
> +{
> +	/* We don't emulate LAWs yet */
> +}
> +
> +static uint32_t get_cpu_freq(void)
> +{
> +	void *fdt = get_fdt();
> +	int cpus_node = fdt_path_offset(fdt, "/cpus");
> +	int cpu_node = fdt_first_subnode(fdt, cpus_node);
> +	const char *prop = "clock-frequency";
> +	return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
> +}
> +
> +void get_sys_info(sys_info_t *sys_info)
> +{
> +	int freq = get_cpu_freq();
> +
> +	memset(sys_info, 0, sizeof(sys_info_t));
> +	sys_info->freq_systembus = freq;
> +	sys_info->freq_ddrbus = freq;
> +	sys_info->freq_processor[0] = freq;
> +}
> +

Again, if you're doing this you really should override get_tbclk()
instead of letting it use the much faster cpufreq/8.

> +int get_clocks (void)
> +{
> +	sys_info_t sys_info;
> +
> +	get_sys_info(&sys_info);
> +
> +	gd->cpu_clk = sys_info.freq_processor[0];
> +	gd->bus_clk = sys_info.freq_systembus;
> +	gd->mem_clk = sys_info.freq_ddrbus;
> +	gd->arch.lbc_clk = sys_info.freq_ddrbus;

I wonder if with higher frequencies we'll trigger overflows in some
drivers. :-)

> +/* Physical address should be a function call */
> +#ifndef __ASSEMBLY__
> +extern unsigned long long get_phys_ccsrbar_addr_early(void);
> +#endif

Where does this get called?

-Scott

[U-Boot] [PATCH v3 4/6] PPC: 85xx: Generalize DDR TLB mapping function

[Alexander Graf]

On 19.02.2014, at 00:21, Scott Wood <scottwood@freescale.com> wrote:

> On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
>> -	if (memsize)
>> -		print_size(memsize, " left unmapped\n");
>> +	if (size)
>> +		print_size(size, " left unmapped\n");
>> +}
> 
> The print_size should move to the caller, with some way to pass back the
> amout left unmapped.  Non-RAM callers would treat a non-zero unmapped
> value as an error.
> 
>> +unsigned int
>> +setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
>> +{
>> +	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
>> +	u64 memsize = (u64)memsize_in_meg << 20;
>> +
>> +	memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
>> +	tlb_map_range(ram_tlb_address, p_addr, memsize, true);
>> 	return memsize_in_meg;
>> }
> 
> Here you seem to be hiding the message for RAM.

It could still fail if we're running out of TLB entries, no?

> York, are you OK with just removing the message altogether, and having
> tlb_map_range return a normal error code if it can't map everything
> (with DDR size reduced in advance as above)?

How about we just change the return value of tlb_map_range to uint64_t and return size? That way we can 1:1 move the print code out of the function into the RAM map code and IO callers can just call assert(r != 0).

> 
>> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
>> index cadaeef..5493c51 100644
>> --- a/arch/powerpc/include/asm/mmu.h
>> +++ b/arch/powerpc/include/asm/mmu.h
>> @@ -509,6 +509,9 @@ extern void print_tlbcam(void);
>> extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
>> extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
>> 
>> +extern void tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
>> +			  bool is_ram);
> 
> bool arguments tend to be hard to read at call sites -- flags (or enum)
> with something like MAP_RAM/MAP_IO would be nicer (I'm not insisting,
> though).

Good point.


Alex

[U-Boot] [PATCH v3 6/6] PPC 85xx: Add qemu-ppce500 machine

[Alexander Graf]

On 19.02.2014, at 01:03, Scott Wood <scottwood@freescale.com> wrote:

> On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
>> diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
>> index bb0025c..8982c78 100644
>> --- a/arch/powerpc/cpu/mpc85xx/start.S
>> +++ b/arch/powerpc/cpu/mpc85xx/start.S
>> @@ -80,6 +80,11 @@ _start_e500:
>> 	li	r1,MSR_DE
>> 	mtmsr 	r1
>> 
>> +#ifdef CONFIG_QEMU_E500
>> +	/* Save our ePAPR device tree pointer before we clobber it */
>> +	mr	r24, r3
>> +#endif
> 
> FWIW, it should be harmless to do this unconditionally (though in that
> case I'd insert "(if we have one)" in the comment.

Sure.

> 
>> #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
>> 	mfspr	r3,SPRN_SVR
>> 	rlwinm	r3,r3,0,0xff
>> @@ -514,6 +519,7 @@ nexti:	mflr	r1		/* R1 = our PC */
>>  * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
>>  * long-term TLBs, so we use TLB0 here.
>>  */
>> +#if !defined(CONFIG_DYNAMIC_CCSRBAR)
>> #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
> 
> This shouldn't be necessary, if you have
> CONFIG_SYS_CCSR_DO_NOT_RELOCATE.

You're right :).

> 
>> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
>> index 2011fb8..0e0b483 100644
>> --- a/arch/powerpc/cpu/mpc85xx/tlb.c
>> +++ b/arch/powerpc/cpu/mpc85xx/tlb.c
>> @@ -36,6 +36,10 @@ void init_tlbs(void)
>> 			  tlb_table[i].mas7);
>> 	}
>> 
>> +#ifdef CONFIG_SYS_USE_DYNAMIC_TLBS
>> +	init_tlbs_dynamic();
>> +#endif
> 
> You could avoid the ifdef by moving a stub implementation into the
> header -- or possibly better, avoid the config symbol entirely by using
> a weak symbol.
> 
> Better still, make init_tlbs() weak.  Then you don't need a config
> symbol, a new function name, or a dummy tlb_table[] -- you just redefine
> init_tlbs() in board code.

Nice idea. That radically simplifies the code.

> 
>> diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
>> new file mode 100644
>> index 0000000..fc546b9
>> --- /dev/null
>> +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
>> @@ -0,0 +1,334 @@
>> +/*
>> + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:	GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <command.h>
>> +#include <pci.h>
>> +#include <asm/processor.h>
>> +#include <asm/mmu.h>
>> +#include <asm/fsl_pci.h>
>> +#include <asm/io.h>
>> +#include <libfdt.h>
>> +#include <fdt_support.h>
>> +#include <netdev.h>
>> +#include <fdtdec.h>
>> +#include <errno.h>
>> +#include <malloc.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static void *get_fdt(void)
>> +{
>> +	return (void *)gd->fdt_blob;
>> +}
> 
> Does this return virtual or physical?

I've split this into a get_fdt_virt() and get_fdt_phys() function to make this more explicit.

> 
>> +
>> +uint64_t get_phys_ccsrbar_addr_early(void)
>> +{
>> +	u32 mas0, mas1, mas2, mas3, mas7;
>> +	ulong fdt = (ulong)get_fdt();
>> +	uint64_t r;
>> +
>> +	/*
>> +	 * To be able to read the FDT we need to create a temporary TLB
>> +	 * map for it.
>> +	 */
>> +
>> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(10);
>> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
>> +	mas2 = FSL_BOOKE_MAS2(fdt, 0);
>> +	mas3 = FSL_BOOKE_MAS3(fdt, 0, MAS3_SW|MAS3_SR);
>> +	mas7 = FSL_BOOKE_MAS7(fdt);
> 
> Don't use the physical address as a virtual address.  Use a known-good
> virtual address.  Using unknown physical addresses as virtual addresses
> is generally a bad idea (it's different for stuff whose physical address
> is hardcoded in U-Boot), but it's particularly bad here because you'll
> create an overlapping TLB entry if the fdt happens to live within your
> initial memory mapping.

Ok.

> 
> OK, I see you use CONFIG_SYS_TMPVIRT for this elsewhere, but I guess
> forgot to use it here (why is fdt mapping code duplicated?).

I've folded the AS=1 mapping functions into a single function and used tlb_map_range for the AS=0 one.

> 
>> +void pci_init_board(void)
>> +{
>> +	struct pci_controller *pci_hoses;
>> +	void *fdt = get_fdt();
>> +	int pci_node;
>> +	int pci_num = 0;
>> +	int pci_count = 0;
>> +	const char *compat = "fsl,mpc8540-pci";
>> +	ulong map_addr;
> 
> May want to look for arbitrary PCI host controllers (device_type would
> be simplest), in case the QEMU machine ever gets an upgrade to PCIe.

Ok.

> 
>> +
>> +	puts("\n");
>> +
>> +	/* Start MMIO and PIO range maps above RAM */
>> +	map_addr = CONFIG_MAX_MEM_MAPPED;
> 
> It'd be better to hardcode virtual addresses for this (as other boards
> do), and limit the size you map to the smaller of the hardcoded size or
> the device tree size.

I don't understand this comment. CONFIG_MAX_MEM_MAPPED is basically the first address available to IO maps, so with this it is properly hardcoded and ensured to always map IO to the same physical address regardless of memory passed in.

> 
>> +	/* Count and allocate PCI buses */
>> +	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
>> +	while (pci_node != -FDT_ERR_NOTFOUND) {
>> +		pci_node = fdt_node_offset_by_compatible(fdt, pci_node, compat);
>> +		pci_count++;
>> +	}
>> +
>> +	if (pci_count) {
>> +		pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
>> +	} else {
>> +		printf("PCI: disabled\n\n");
>> +		return;
>> +	}
>> +
>> +	/* Spawn PCI buses based on device tree */
>> +	pci_node = fdt_node_offset_by_compatible(fdt, -1, compat);
>> +	while (pci_node != -FDT_ERR_NOTFOUND) {
>> +		struct fsl_pci_info pci_info = { };
>> +		const fdt32_t *reg;
>> +		int r;
>> +
>> +		reg = fdt_getprop(fdt, pci_node, "reg", NULL);
>> +		pci_info.regs = fdt_translate_address((void *)fdt, pci_node, reg);
> 
> Unnecessary cast.

Removed.

> 
>> +void init_tlbs_dynamic(void)
>> +{
>> +	unsigned long fdt_phys = (unsigned long)get_fdt();
>> +	unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
>> +	unsigned long fdt_virt_tlb = CONFIG_SYS_TMPVIRT;
>> +	unsigned long fdt_virt = fdt_virt_tlb + (fdt_phys & 0xffffful);
>> +	u32 mas0, mas1, mas2, mas3, mas7;
>> +	phys_size_t ram_size;
>> +
>> +	/*
>> +	 * Create a temporary AS=1 map for the fdt
>> +	 *
>> +	 * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
>> +	 * which was only 4k big. This way we don't have to clear any other maps.
>> +	 */
> 
> I don't think it's generally safe to assume that this entry is ESEL 0 --
> though I'm wondering if the current TLB code is assuming that (or at
> least, assuming that whatever entry is used gets overwritten by the TLB
> table).

That's at least the way I understand the current code :). There's definitely no code anywhere that removes the 4k map:

  0x0000000000f00000 0x0000000000f00000   4K 0     0  SRWXURWX ----- U----

> 
>> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
>> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
>> +	mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
>> +	mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
>> +	mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
> 
> What if the fdt straddles a 1M boundary?

Then we fix the hypervisor ;). Even the 1MB is only an approximation. We don't know the size of the fdt. But I think we can expect the hypervisor to align it on 1MB. The masks here really are just to be nice to a hypervisor if it's broken (or knows exactly what it's doing).

> 
>> +	write_tlb(mas0, mas1, mas2, mas3, mas7);
>> +	gd->fdt_blob = (void *)fdt_virt;
>> +
>> +	/* Fetch RAM size from the fdt */
>> +	ram_size = fixed_sdram();
> 
> Why not just call get_linear_ram_size() directly?

*shrug*. Fixed :).

> 
>> +	/* And remove our fdt map again */
>> +	gd->fdt_blob = (void *)fdt_phys;
>> +	disable_tlb(0);
>> +
>> +	/* Create a dynamic AS=0 CCSRBAR mapping */
>> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
>> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TSIZE(BOOKE_PAGESZ_1M);
>> +	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
>> +	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
>> +	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
>> +
>> +	write_tlb(mas0, mas1, mas2, mas3, mas7);
> 
> Why is this not done via tlb_map_range (after calling
> init_used_tlb_cams, of course)?

Only because this code predates the generic tlb_map_range function. I've fixed it.

> 
>> +
>> +	/* Create a RAM map that spans all accessible RAM */
>> +	init_used_tlb_cams();
>> +	setup_ddr_tlbs(ram_size >> 20);
>> +}
>> +
>> +void init_laws(void)
>> +{
>> +	/* We don't emulate LAWs yet */
>> +}
>> +
>> +static uint32_t get_cpu_freq(void)
>> +{
>> +	void *fdt = get_fdt();
>> +	int cpus_node = fdt_path_offset(fdt, "/cpus");
>> +	int cpu_node = fdt_first_subnode(fdt, cpus_node);
>> +	const char *prop = "clock-frequency";
>> +	return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
>> +}
>> +
>> +void get_sys_info(sys_info_t *sys_info)
>> +{
>> +	int freq = get_cpu_freq();
>> +
>> +	memset(sys_info, 0, sizeof(sys_info_t));
>> +	sys_info->freq_systembus = freq;
>> +	sys_info->freq_ddrbus = freq;
>> +	sys_info->freq_processor[0] = freq;
>> +}
>> +
> 
> Again, if you're doing this you really should override get_tbclk()
> instead of letting it use the much faster cpufreq/8.

Ok, I've made get_tbclk weak and override it with a function that reads timebase-frequency from the first cpu node in dt.

> 
>> +int get_clocks (void)
>> +{
>> +	sys_info_t sys_info;
>> +
>> +	get_sys_info(&sys_info);
>> +
>> +	gd->cpu_clk = sys_info.freq_processor[0];
>> +	gd->bus_clk = sys_info.freq_systembus;
>> +	gd->mem_clk = sys_info.freq_ddrbus;
>> +	gd->arch.lbc_clk = sys_info.freq_ddrbus;
> 
> I wonder if with higher frequencies we'll trigger overflows in some
> drivers. :-)
> 
>> +/* Physical address should be a function call */
>> +#ifndef __ASSEMBLY__
>> +extern unsigned long long get_phys_ccsrbar_addr_early(void);
>> +#endif
> 
> Where does this get called?

CONFIG_SYS_CCSRBAR_PHYS is defined to this which gets used in cpu_init_early_f().


Alex

[U-Boot] [PATCH v3 6/6] PPC 85xx: Add qemu-ppce500 machine

[Scott Wood]

On Thu, 2014-02-20 at 13:34 +0100, Alexander Graf wrote:
> On 19.02.2014, at 01:03, Scott Wood <scottwood@freescale.com> wrote:
> 
> > On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
> >> +	puts("\n");
> >> +
> >> +	/* Start MMIO and PIO range maps above RAM */
> >> +	map_addr = CONFIG_MAX_MEM_MAPPED;
> > 
> > It'd be better to hardcode virtual addresses for this (as other boards
> > do), and limit the size you map to the smaller of the hardcoded size or
> > the device tree size.
> 
> I don't understand this comment. CONFIG_MAX_MEM_MAPPED is basically the
> first address available to IO maps, so with this it is properly
> hardcoded and ensured to always map IO to the same physical address
> regardless of memory passed in.

I mean an explicit address in the board config file, rather than hiding
it here.  It helps to have the full address map in one place.  Consider
what would happen if some other part of the code tried the same trick
with CONFIG_MAX_MEM_MAPPED. :-)
 
> >> +	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
> >> +	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
> >> +	mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
> >> +	mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
> >> +	mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
> > 
> > What if the fdt straddles a 1M boundary?
> 
> Then we fix the hypervisor ;). Even the 1MB is only an approximation.
> We don't know the size of the fdt. But I think we can expect the
> hypervisor to align it on 1MB. The masks here really are just to be
> nice to a hypervisor if it's broken (or knows exactly what it's doing).

What's special about 1 MiB?  If you want to rely on DTC_PAD_MASK not
changing to simplify this code, since it's QEMU-specific, fine -- but I
wouldn't consider it "broken" for an arbitrary hypervisor to do
differently.
 
-Scott

[U-Boot] [PATCH v3 4/6] PPC: 85xx: Generalize DDR TLB mapping function

[Scott Wood]

On Thu, 2014-02-20 at 11:25 +0100, Alexander Graf wrote:
> On 19.02.2014, at 00:21, Scott Wood <scottwood@freescale.com> wrote:
> 
> > On Tue, 2014-02-11 at 01:10 +0100, Alexander Graf wrote:
> >> -	if (memsize)
> >> -		print_size(memsize, " left unmapped\n");
> >> +	if (size)
> >> +		print_size(size, " left unmapped\n");
> >> +}
> > 
> > The print_size should move to the caller, with some way to pass back the
> > amout left unmapped.  Non-RAM callers would treat a non-zero unmapped
> > value as an error.
> > 
> >> +unsigned int
> >> +setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
> >> +{
> >> +	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
> >> +	u64 memsize = (u64)memsize_in_meg << 20;
> >> +
> >> +	memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
> >> +	tlb_map_range(ram_tlb_address, p_addr, memsize, true);
> >> 	return memsize_in_meg;
> >> }
> > 
> > Here you seem to be hiding the message for RAM.
> 
> It could still fail if we're running out of TLB entries, no?

That's not the usual reason for that message to be printed.

> > York, are you OK with just removing the message altogether, and having
> > tlb_map_range return a normal error code if it can't map everything
> > (with DDR size reduced in advance as above)?
> 
> How about we just change the return value of tlb_map_range to uint64_t
> and return size? That way we can 1:1 move the print code out of the
> function into the RAM map code and IO callers can just call assert(r !=
> 0).

That's fine.  I was just wondering if the message had value at all,
given that it's expected if you have more than 2 GiB of RAM.
 
-Scott