* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-12 11:06 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: sebastian.hesselbarth
Cc: Antoine Ténart, alexandre.belloni, zmxu, jszhang,
linux-arm-kernel, linux-kernel
This serie adds the initial support for the Marvell BG2-Q DMP (part of the
Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
controllers, local timer, apb timers and uarts for now.
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
Antoine Ténart (2):
ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++
arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
5 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
--
1.8.3.2
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-12 11:06 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: linux-arm-kernel
This serie adds the initial support for the Marvell BG2-Q DMP (part of the
Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
controllers, local timer, apb timers and uarts for now.
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
Antoine T?nart (2):
ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++
arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
5 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
--
1.8.3.2
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 11:06 ` Antoine Ténart
-1 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: sebastian.hesselbarth
Cc: Antoine Ténart, alexandre.belloni, zmxu, jszhang,
linux-arm-kernel, linux-kernel
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
3 files changed, 173 insertions(+)
create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 5a930c1528ad..69ad05ea8ed8 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
+ 88DE3114, Armada 1500 Pro
+ Desgin name: BG2-Q
+ Core: Quad Core ARM CA9, PL310 L2CC
+ Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
+ Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
88DE????
Design name: BG3
Core: ARM Cortex-A15, CA15 integrated L2CC
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 737afa5f8148..25472b74218f 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+ "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
new file mode 100644
index 000000000000..f58c9c64c60e
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "Marvell Armada 1500 pro (BG2-Q) SoC";
+ compatible = "marvell,berlin2q", "marvell,berlin";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <3>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ smclk: sysmgr-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ sysclk: system-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xf7000000 0x1000000>;
+ interrupt-parent = <&gic>;
+
+ l2: l2-cache-controller@ac0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xac0000 0x1000>;
+ cache-level = <2>;
+ };
+
+ gic: interrupt-controller@ad1000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0xad1000 0x1000>, <0xad0100 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ local-timer@ad0600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xad0600 0x20>;
+ clocks = <&sysclk>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
+ apb@e80000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe80000 0x10000>;
+ interrupt-parent = <&aic>;
+
+ timer0: timer@2c00 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c00 0x14>;
+ interrupts = <8>;
+ clock-freq = <100000000>;
+ status = "okay";
+ };
+
+ timer1: timer@2c14 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c14 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ aic: interrupt-controller@3800 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x3800 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apb@fc0000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xfc0000 0x10000>;
+ interrupt-parent = <&sic>;
+
+ uart0: uart@9000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x9000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <8>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: uart@a000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xa000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <9>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sic: interrupt-controller@e000 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0xe000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-12 11:06 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
3 files changed, 173 insertions(+)
create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 5a930c1528ad..69ad05ea8ed8 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
+ 88DE3114, Armada 1500 Pro
+ Desgin name: BG2-Q
+ Core: Quad Core ARM CA9, PL310 L2CC
+ Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
+ Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
88DE????
Design name: BG3
Core: ARM Cortex-A15, CA15 integrated L2CC
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 737afa5f8148..25472b74218f 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+ "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
new file mode 100644
index 000000000000..f58c9c64c60e
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "Marvell Armada 1500 pro (BG2-Q) SoC";
+ compatible = "marvell,berlin2q", "marvell,berlin";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <2>;
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <3>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ smclk: sysmgr-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ sysclk: system-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xf7000000 0x1000000>;
+ interrupt-parent = <&gic>;
+
+ l2: l2-cache-controller at ac0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xac0000 0x1000>;
+ cache-level = <2>;
+ };
+
+ gic: interrupt-controller at ad1000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0xad1000 0x1000>, <0xad0100 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ local-timer at ad0600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xad0600 0x20>;
+ clocks = <&sysclk>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
+ apb at e80000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe80000 0x10000>;
+ interrupt-parent = <&aic>;
+
+ timer0: timer at 2c00 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c00 0x14>;
+ interrupts = <8>;
+ clock-freq = <100000000>;
+ status = "okay";
+ };
+
+ timer1: timer at 2c14 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c14 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ aic: interrupt-controller at 3800 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x3800 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apb at fc0000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xfc0000 0x10000>;
+ interrupt-parent = <&sic>;
+
+ uart0: uart at 9000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x9000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <8>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: uart at a000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xa000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <9>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sic: interrupt-controller at e000 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0xe000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 11:06 ` Antoine Ténart
-1 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: sebastian.hesselbarth
Cc: Antoine Ténart, alexandre.belloni, zmxu, jszhang,
linux-arm-kernel, linux-kernel
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 032030361bef..1a2adadfb962 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
- berlin2cd-google-chromecast.dtb
+ berlin2cd-google-chromecast.dtb \
+ berlin2q-dmp.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts b/arch/arm/boot/dts/berlin2q-dmp.dts
new file mode 100644
index 000000000000..6a98860e0251
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q-dmp.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "berlin2q.dtsi"
+
+/ {
+ model = "Marvell BG2-Q DMP";
+ compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ choosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ soc {
+ apb@fc0000 {
+ uart0: uart@9000 {
+ status = "okay";
+ };
+ };
+ };
+};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 11:06 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:06 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 032030361bef..1a2adadfb962 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
- berlin2cd-google-chromecast.dtb
+ berlin2cd-google-chromecast.dtb \
+ berlin2q-dmp.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts b/arch/arm/boot/dts/berlin2q-dmp.dts
new file mode 100644
index 000000000000..6a98860e0251
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q-dmp.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "berlin2q.dtsi"
+
+/ {
+ model = "Marvell BG2-Q DMP";
+ compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ choosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ soc {
+ apb at fc0000 {
+ uart0: uart at 9000 {
+ status = "okay";
+ };
+ };
+ };
+};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 11:20 ` Arnd Bergmann
-1 siblings, 0 replies; 42+ messages in thread
From: Arnd Bergmann @ 2014-03-12 11:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Antoine Ténart, sebastian.hesselbarth, zmxu, jszhang,
linux-kernel, alexandre.belloni
On Wednesday 12 March 2014 12:06:04 Antoine Ténart wrote:
> +
> + soc {
> + apb@fc0000 {
> + uart0: uart@9000 {
> + status = "okay";
> + };
> + };
> + };
> +};
No need to duplicate both the label and the hierarchy here. The easiest
way to do this is just
&uart0 {
status = "okay";
};
since you already have the label.
Arnd
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 11:20 ` Arnd Bergmann
0 siblings, 0 replies; 42+ messages in thread
From: Arnd Bergmann @ 2014-03-12 11:20 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 12 March 2014 12:06:04 Antoine T?nart wrote:
> +
> + soc {
> + apb at fc0000 {
> + uart0: uart at 9000 {
> + status = "okay";
> + };
> + };
> + };
> +};
No need to duplicate both the label and the hierarchy here. The easiest
way to do this is just
&uart0 {
status = "okay";
};
since you already have the label.
Arnd
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 11:20 ` Arnd Bergmann
@ 2014-03-12 11:30 ` Antoine Ténart
-1 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:30 UTC (permalink / raw)
To: Arnd Bergmann, linux-arm-kernel
Cc: zmxu, jszhang, linux-kernel, alexandre.belloni, sebastian.hesselbarth
On 12/03/2014 12:20, Arnd Bergmann wrote:
> On Wednesday 12 March 2014 12:06:04 Antoine Ténart wrote:
>> +
>> + soc {
>> + apb@fc0000 {
>> + uart0: uart@9000 {
>> + status = "okay";
>> + };
>> + };
>> + };
>> +};
>
>
> No need to duplicate both the label and the hierarchy here. The easiest
> way to do this is just
>
> &uart0 {
> status = "okay";
> };
>
> since you already have the label.
I'll change that.
Thanks for the feedback !
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 11:30 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-12 11:30 UTC (permalink / raw)
To: linux-arm-kernel
On 12/03/2014 12:20, Arnd Bergmann wrote:
> On Wednesday 12 March 2014 12:06:04 Antoine T?nart wrote:
>> +
>> + soc {
>> + apb at fc0000 {
>> + uart0: uart at 9000 {
>> + status = "okay";
>> + };
>> + };
>> + };
>> +};
>
>
> No need to duplicate both the label and the hierarchy here. The easiest
> way to do this is just
>
> &uart0 {
> status = "okay";
> };
>
> since you already have the label.
I'll change that.
Thanks for the feedback !
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 11:35 ` Alexandre Belloni
-1 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-12 11:35 UTC (permalink / raw)
To: Antoine Ténart
Cc: sebastian.hesselbarth, zmxu, jszhang, linux-arm-kernel, linux-kernel
Hi,
On 12/03/2014 at 12:06:02 +0100, Antoine Ténart wrote :
> This serie adds the initial support for the Marvell BG2-Q DMP (part of the
> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
> controllers, local timer, apb timers and uarts for now.
>
> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>
I would move that description to the commit logs. Else one would have to
lookup the mailing list archive to read it.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-12 11:35 ` Alexandre Belloni
0 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-12 11:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 12/03/2014 at 12:06:02 +0100, Antoine T?nart wrote :
> This serie adds the initial support for the Marvell BG2-Q DMP (part of the
> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
> controllers, local timer, apb timers and uarts for now.
>
> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>
I would move that description to the commit logs. Else one would have to
lookup the mailing list archive to read it.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 12:04 ` Jisheng Zhang
-1 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-12 12:04 UTC (permalink / raw)
To: Antoine Ténart, sebastian.hesselbarth
Cc: alexandre.belloni, Jimmy Xu, linux-arm-kernel, linux-kernel
Hi Antoine,
On Wed, 12 Mar 2014 04:06:04 -0700
Antoine Ténart <antoine.tenart@free-electrons.com> wrote:
> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 032030361bef..1a2adadfb962 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
> dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> - berlin2cd-google-chromecast.dtb
> + berlin2cd-google-chromecast.dtb \
> + berlin2q-dmp.dtb
> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
> da850-evm.dtb
> dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts
> b/arch/arm/boot/dts/berlin2q-dmp.dts new file mode 100644
> index 000000000000..6a98860e0251
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q-dmp.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "berlin2q.dtsi"
> +
> +/ {
> + model = "Marvell BG2-Q DMP";
> + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> "marvell,berlin"; +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>;
The memory size of BG2Q DMP is 2GB. And IIRC, all BG2Q boards have 2GB memory.
So would it be better to put memory dt node in berlin2q.dtsi?
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 12:04 ` Jisheng Zhang
0 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-12 12:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi Antoine,
On Wed, 12 Mar 2014 04:06:04 -0700
Antoine T?nart <antoine.tenart@free-electrons.com> wrote:
> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 032030361bef..1a2adadfb962 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
> dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> - berlin2cd-google-chromecast.dtb
> + berlin2cd-google-chromecast.dtb \
> + berlin2q-dmp.dtb
> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
> da850-evm.dtb
> dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts
> b/arch/arm/boot/dts/berlin2q-dmp.dts new file mode 100644
> index 000000000000..6a98860e0251
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q-dmp.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "berlin2q.dtsi"
> +
> +/ {
> + model = "Marvell BG2-Q DMP";
> + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> "marvell,berlin"; +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>;
The memory size of BG2Q DMP is 2GB. And IIRC, all BG2Q boards have 2GB memory.
So would it be better to put memory dt node in berlin2q.dtsi?
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-12 12:22 ` Alexandre Belloni
-1 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-12 12:22 UTC (permalink / raw)
To: Antoine Ténart
Cc: sebastian.hesselbarth, zmxu, jszhang, linux-kernel, linux-arm-kernel
On 12/03/2014 at 12:06:03 +0100, Antoine Ténart wrote :
> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Documentation/arm/Marvell/README | 5 +
> .../devicetree/bindings/arm/marvell,berlin.txt | 1 +
> arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
> 3 files changed, 173 insertions(+)
> create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
>
> diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
> index 5a930c1528ad..69ad05ea8ed8 100644
> --- a/Documentation/arm/Marvell/README
> +++ b/Documentation/arm/Marvell/README
> @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
> Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
> Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
> Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
> + 88DE3114, Armada 1500 Pro
> + Desgin name: BG2-Q
> + Core: Quad Core ARM CA9, PL310 L2CC
> + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
> + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
> 88DE????
> Design name: BG3
> Core: ARM Cortex-A15, CA15 integrated L2CC
> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> index 737afa5f8148..25472b74218f 100644
> --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
> SoC and board used. Currently known SoC compatibles are:
> "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
> "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
> "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
> "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> new file mode 100644
> index 000000000000..f58c9c64c60e
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
> + compatible = "marvell,berlin2q", "marvell,berlin";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <3>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + smclk: sysmgr-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
The 25MHz crystal is on the board, please move it to the board dts.
> + sysclk: system-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xf7000000 0x1000000>;
> + interrupt-parent = <&gic>;
> +
> + l2: l2-cache-controller@ac0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xac0000 0x1000>;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller@ad1000 {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0xad1000 0x1000>, <0xad0100 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + local-timer@ad0600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0xad0600 0x20>;
> + clocks = <&sysclk>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> + apb@e80000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xe80000 0x10000>;
> + interrupt-parent = <&aic>;
> +
> + timer0: timer@2c00 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c00 0x14>;
> + interrupts = <8>;
> + clock-freq = <100000000>;
> + status = "okay";
> + };
> +
> + timer1: timer@2c14 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c14 0x14>;
> + clock-freq = <100000000>;
> + status = "disabled";
> + };
> +
> + aic: interrupt-controller@3800 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0x3800 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + apb@fc0000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xfc0000 0x10000>;
> + interrupt-parent = <&sic>;
> +
> + uart0: uart@9000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x9000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <8>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: uart@a000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xa000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <9>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + sic: interrupt-controller@e000 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0xe000 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
> --
> 1.8.3.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-12 12:22 ` Alexandre Belloni
0 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-12 12:22 UTC (permalink / raw)
To: linux-arm-kernel
On 12/03/2014 at 12:06:03 +0100, Antoine T?nart wrote :
> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Documentation/arm/Marvell/README | 5 +
> .../devicetree/bindings/arm/marvell,berlin.txt | 1 +
> arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
> 3 files changed, 173 insertions(+)
> create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
>
> diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
> index 5a930c1528ad..69ad05ea8ed8 100644
> --- a/Documentation/arm/Marvell/README
> +++ b/Documentation/arm/Marvell/README
> @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
> Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
> Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
> Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
> + 88DE3114, Armada 1500 Pro
> + Desgin name: BG2-Q
> + Core: Quad Core ARM CA9, PL310 L2CC
> + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
> + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
> 88DE????
> Design name: BG3
> Core: ARM Cortex-A15, CA15 integrated L2CC
> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> index 737afa5f8148..25472b74218f 100644
> --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
> SoC and board used. Currently known SoC compatibles are:
> "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
> "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
> "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
> "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> new file mode 100644
> index 000000000000..f58c9c64c60e
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
> + compatible = "marvell,berlin2q", "marvell,berlin";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
> +
> + cpu at 1 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <1>;
> + };
> +
> + cpu at 2 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <2>;
> + };
> +
> + cpu at 3 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <3>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + smclk: sysmgr-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
The 25MHz crystal is on the board, please move it to the board dts.
> + sysclk: system-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xf7000000 0x1000000>;
> + interrupt-parent = <&gic>;
> +
> + l2: l2-cache-controller at ac0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xac0000 0x1000>;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller at ad1000 {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0xad1000 0x1000>, <0xad0100 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + local-timer at ad0600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0xad0600 0x20>;
> + clocks = <&sysclk>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> + apb at e80000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xe80000 0x10000>;
> + interrupt-parent = <&aic>;
> +
> + timer0: timer at 2c00 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c00 0x14>;
> + interrupts = <8>;
> + clock-freq = <100000000>;
> + status = "okay";
> + };
> +
> + timer1: timer at 2c14 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c14 0x14>;
> + clock-freq = <100000000>;
> + status = "disabled";
> + };
> +
> + aic: interrupt-controller at 3800 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0x3800 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + apb at fc0000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xfc0000 0x10000>;
> + interrupt-parent = <&sic>;
> +
> + uart0: uart at 9000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x9000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <8>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: uart at a000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xa000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <9>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + sic: interrupt-controller at e000 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0xe000 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
> --
> 1.8.3.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 12:04 ` Jisheng Zhang
@ 2014-03-12 12:37 ` Andrew Lunn
-1 siblings, 0 replies; 42+ messages in thread
From: Andrew Lunn @ 2014-03-12 12:37 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Antoine Ténart, sebastian.hesselbarth, Jimmy Xu,
alexandre.belloni, linux-kernel, linux-arm-kernel
> > +/dts-v1/;
> > +#include "berlin2q.dtsi"
> > +
> > +/ {
> > + model = "Marvell BG2-Q DMP";
> > + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> > "marvell,berlin"; +
> > + memory {
> > + device_type = "memory";
> > + reg = <0x00000000 0x40000000>;
>
> The memory size of BG2Q DMP is 2GB.
Jisheng
Does this imply that the RAM is inside the SoC package, and that
there is no external memory interface which can be used to add more
RAM?
Thanks
Andrew
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 12:37 ` Andrew Lunn
0 siblings, 0 replies; 42+ messages in thread
From: Andrew Lunn @ 2014-03-12 12:37 UTC (permalink / raw)
To: linux-arm-kernel
> > +/dts-v1/;
> > +#include "berlin2q.dtsi"
> > +
> > +/ {
> > + model = "Marvell BG2-Q DMP";
> > + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> > "marvell,berlin"; +
> > + memory {
> > + device_type = "memory";
> > + reg = <0x00000000 0x40000000>;
>
> The memory size of BG2Q DMP is 2GB.
Jisheng
Does this imply that the RAM is inside the SoC package, and that
there is no external memory interface which can be used to add more
RAM?
Thanks
Andrew
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 12:37 ` Andrew Lunn
@ 2014-03-12 12:44 ` Jisheng Zhang
-1 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-12 12:44 UTC (permalink / raw)
To: Andrew Lunn
Cc: Antoine Ténart, sebastian.hesselbarth, Jimmy Xu,
alexandre.belloni, linux-kernel, linux-arm-kernel
Hi Andrew,
On Wed, 12 Mar 2014 05:37:59 -0700
Andrew Lunn <andrew@lunn.ch> wrote:
> > > +/dts-v1/;
> > > +#include "berlin2q.dtsi"
> > > +
> > > +/ {
> > > + model = "Marvell BG2-Q DMP";
> > > + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> > > "marvell,berlin"; +
> > > + memory {
> > > + device_type = "memory";
> > > + reg = <0x00000000 0x40000000>;
> >
> > The memory size of BG2Q DMP is 2GB.
>
> Jisheng
>
> Does this imply that the RAM is inside the SoC package, and that
> there is no external memory interface which can be used to add more
> RAM?
Nope. The ram is on the board. After talking with Alex, I think it's
reasonable to put the memory node in dts as the original patch does.
However, we need to set the correct memory size of BG2Q DMP board.
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-12 12:44 ` Jisheng Zhang
0 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-12 12:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Andrew,
On Wed, 12 Mar 2014 05:37:59 -0700
Andrew Lunn <andrew@lunn.ch> wrote:
> > > +/dts-v1/;
> > > +#include "berlin2q.dtsi"
> > > +
> > > +/ {
> > > + model = "Marvell BG2-Q DMP";
> > > + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q",
> > > "marvell,berlin"; +
> > > + memory {
> > > + device_type = "memory";
> > > + reg = <0x00000000 0x40000000>;
> >
> > The memory size of BG2Q DMP is 2GB.
>
> Jisheng
>
> Does this imply that the RAM is inside the SoC package, and that
> there is no external memory interface which can be used to add more
> RAM?
Nope. The ram is on the board. After talking with Alex, I think it's
reasonable to put the memory node in dts as the original patch does.
However, we need to set the correct memory size of BG2Q DMP board.
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
2014-03-12 11:35 ` Alexandre Belloni
@ 2014-03-13 9:51 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 9:51 UTC (permalink / raw)
To: Alexandre Belloni, Antoine Ténart
Cc: zmxu, jszhang, linux-arm-kernel, linux-kernel
On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
> On 12/03/2014 at 12:06:02 +0100, Antoine Ténart wrote :
>> This serie adds the initial support for the Marvell BG2-Q DMP (part of the
>> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
>> controllers, local timer, apb timers and uarts for now.
>>
>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>>
>
> I would move that description to the commit logs. Else one would have to
> lookup the mailing list archive to read it.
Antoine,
thanks for posting this. I also prefer each patch to have a commit log
no matter how obvious the contents may be. Please have a simple commit
log for each of the single patches.
You can leave out the link to marvell.com in the commit log as you
update Marvell SoC documentation.
TBH, I haven't set up any mach-berlin branches, yet. Also it is very
late in the cycle. I'll setup proper branches and also a -next branch
for next release, maybe we can take your DT patches directly through
arm-soc this time. Otherwise, we'll have to postpone them for v3.16.
I have some comments on the single patches and will reply there.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-13 9:51 ` Sebastian Hesselbarth
0 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 9:51 UTC (permalink / raw)
To: linux-arm-kernel
On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
> On 12/03/2014 at 12:06:02 +0100, Antoine T?nart wrote :
>> This serie adds the initial support for the Marvell BG2-Q DMP (part of the
>> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
>> controllers, local timer, apb timers and uarts for now.
>>
>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>>
>
> I would move that description to the commit logs. Else one would have to
> lookup the mailing list archive to read it.
Antoine,
thanks for posting this. I also prefer each patch to have a commit log
no matter how obvious the contents may be. Please have a simple commit
log for each of the single patches.
You can leave out the link to marvell.com in the commit log as you
update Marvell SoC documentation.
TBH, I haven't set up any mach-berlin branches, yet. Also it is very
late in the cycle. I'll setup proper branches and also a -next branch
for next release, maybe we can take your DT patches directly through
arm-soc this time. Otherwise, we'll have to postpone them for v3.16.
I have some comments on the single patches and will reply there.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
2014-03-13 9:51 ` Sebastian Hesselbarth
@ 2014-03-13 9:56 ` Alexandre Belloni
-1 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 9:56 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Antoine Ténart, zmxu, jszhang, linux-arm-kernel, linux-kernel
Hi,
On 13/03/2014 at 09:51:29 +0000, Sebastian Hesselbarth wrote :
> thanks for posting this. I also prefer each patch to have a commit log
> no matter how obvious the contents may be. Please have a simple commit
> log for each of the single patches.
>
> You can leave out the link to marvell.com in the commit log as you
> update Marvell SoC documentation.
>
> TBH, I haven't set up any mach-berlin branches, yet. Also it is very
> late in the cycle. I'll setup proper branches and also a -next branch
> for next release, maybe we can take your DT patches directly through
> arm-soc this time. Otherwise, we'll have to postpone them for v3.16.
>
We were aiming at 3.16 anyway. No worries.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-13 9:56 ` Alexandre Belloni
0 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 9:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 13/03/2014 at 09:51:29 +0000, Sebastian Hesselbarth wrote :
> thanks for posting this. I also prefer each patch to have a commit log
> no matter how obvious the contents may be. Please have a simple commit
> log for each of the single patches.
>
> You can leave out the link to marvell.com in the commit log as you
> update Marvell SoC documentation.
>
> TBH, I haven't set up any mach-berlin branches, yet. Also it is very
> late in the cycle. I'll setup proper branches and also a -next branch
> for next release, maybe we can take your DT patches directly through
> arm-soc this time. Otherwise, we'll have to postpone them for v3.16.
>
We were aiming at 3.16 anyway. No worries.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-12 12:22 ` Alexandre Belloni
@ 2014-03-13 9:56 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 9:56 UTC (permalink / raw)
To: Alexandre Belloni, Antoine Ténart
Cc: zmxu, jszhang, linux-kernel, linux-arm-kernel
On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
> On 12/03/2014 at 12:06:03 +0100, Antoine Ténart wrote :
>> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
>> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>> ---
>> Documentation/arm/Marvell/README | 5 +
>> .../devicetree/bindings/arm/marvell,berlin.txt | 1 +
Please separate doc and dtsi changes into separate patches.
>> arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
>> 3 files changed, 173 insertions(+)
>> create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
>>
>> diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
>> index 5a930c1528ad..69ad05ea8ed8 100644
>> --- a/Documentation/arm/Marvell/README
>> +++ b/Documentation/arm/Marvell/README
>> @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
>> Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
>> Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
>> + 88DE3114, Armada 1500 Pro
>> + Desgin name: BG2-Q
s/Desgin/Design/
>> + Core: Quad Core ARM CA9, PL310 L2CC
s/ARM CA9/ARM Cortex-A9/
>> + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>> + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
>> 88DE????
>> Design name: BG3
>> Core: ARM Cortex-A15, CA15 integrated L2CC
>> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> index 737afa5f8148..25472b74218f 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
>> SoC and board used. Currently known SoC compatibles are:
>> "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
>> "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
>> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
Please add 88DE3114 above like there is already for the other SoCs.
>> "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
>> "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
>>
>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
>> new file mode 100644
>> index 000000000000..f58c9c64c60e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>> @@ -0,0 +1,167 @@
>> +/*
>> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
>> + compatible = "marvell,berlin2q", "marvell,berlin";
[...]
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + smclk: sysmgr-clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <25000000>;
>> + };
>> +
>
> The 25MHz crystal is on the board, please move it to the board dts.
If you can confirm that sysmgr clock comes directly from this crystal,
I agree. If it is fed into a pll and can possibly be modified or gated,
make it depend on a 25MHz board crystal. If 25MHz is the only option
for this clock input, I could also live with it being part of the SoC
description.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 9:56 ` Sebastian Hesselbarth
0 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 9:56 UTC (permalink / raw)
To: linux-arm-kernel
On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
> On 12/03/2014 at 12:06:03 +0100, Antoine T?nart wrote :
>> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
>> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>> ---
>> Documentation/arm/Marvell/README | 5 +
>> .../devicetree/bindings/arm/marvell,berlin.txt | 1 +
Please separate doc and dtsi changes into separate patches.
>> arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++
>> 3 files changed, 173 insertions(+)
>> create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
>>
>> diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
>> index 5a930c1528ad..69ad05ea8ed8 100644
>> --- a/Documentation/arm/Marvell/README
>> +++ b/Documentation/arm/Marvell/README
>> @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment)
>> Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
>> Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
>> + 88DE3114, Armada 1500 Pro
>> + Desgin name: BG2-Q
s/Desgin/Design/
>> + Core: Quad Core ARM CA9, PL310 L2CC
s/ARM CA9/ARM Cortex-A9/
>> + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>> + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
>> 88DE????
>> Design name: BG3
>> Core: ARM Cortex-A15, CA15 integrated L2CC
>> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> index 737afa5f8148..25472b74218f 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific
>> SoC and board used. Currently known SoC compatibles are:
>> "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
>> "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
>> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q)
Please add 88DE3114 above like there is already for the other SoCs.
>> "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
>> "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
>>
>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
>> new file mode 100644
>> index 000000000000..f58c9c64c60e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>> @@ -0,0 +1,167 @@
>> +/*
>> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
>> + compatible = "marvell,berlin2q", "marvell,berlin";
[...]
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + smclk: sysmgr-clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <25000000>;
>> + };
>> +
>
> The 25MHz crystal is on the board, please move it to the board dts.
If you can confirm that sysmgr clock comes directly from this crystal,
I agree. If it is fed into a pll and can possibly be modified or gated,
make it depend on a 25MHz board crystal. If 25MHz is the only option
for this clock input, I could also live with it being part of the SoC
description.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-13 10:05 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:05 UTC (permalink / raw)
To: Antoine Ténart
Cc: alexandre.belloni, zmxu, jszhang, linux-arm-kernel, linux-kernel
On 03/12/2014 11:06 AM, Antoine Ténart wrote:
> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
Missed some comments on the nodes below.
[...]
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> new file mode 100644
> index 000000000000..f58c9c64c60e
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
> + compatible = "marvell,berlin2q", "marvell,berlin";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <3>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
You are not numbering the clocks below. Shouldn't this be
#address-cells = <0>;
#size-cells = <0>;
then?
> +
> + smclk: sysmgr-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + sysclk: system-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xf7000000 0x1000000>;
> + interrupt-parent = <&gic>;
> +
> + l2: l2-cache-controller@ac0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xac0000 0x1000>;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller@ad1000 {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0xad1000 0x1000>, <0xad0100 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + local-timer@ad0600 {
Please keep nodes sorted by address.
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0xad0600 0x20>;
> + clocks = <&sysclk>;
Playing with Chromecast, I remember local-timer running at sysclk/3 or
something. I know berlin2/berlin2cd is wrong here. Can you check that
for berlin2q local-timer also runs at sysclk/n?
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> + apb@e80000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xe80000 0x10000>;
> + interrupt-parent = <&aic>;
> +
> + timer0: timer@2c00 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c00 0x14>;
> + interrupts = <8>;
> + clock-freq = <100000000>;
> + status = "okay";
> + };
> +
> + timer1: timer@2c14 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c14 0x14>;
> + clock-freq = <100000000>;
> + status = "disabled";
> + };
berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
here or did Marvell remove them?
> + aic: interrupt-controller@3800 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0x3800 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + apb@fc0000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xfc0000 0x10000>;
> + interrupt-parent = <&sic>;
> +
> + uart0: uart@9000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x9000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <8>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: uart@a000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xa000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <9>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
Also for uart, can you please double-check if there is no uart2?
Sebastian
> + sic: interrupt-controller@e000 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0xe000 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 10:05 ` Sebastian Hesselbarth
0 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:05 UTC (permalink / raw)
To: linux-arm-kernel
On 03/12/2014 11:06 AM, Antoine T?nart wrote:
> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
Missed some comments on the nodes below.
[...]
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> new file mode 100644
> index 000000000000..f58c9c64c60e
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + model = "Marvell Armada 1500 pro (BG2-Q) SoC";
> + compatible = "marvell,berlin2q", "marvell,berlin";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
> +
> + cpu at 1 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <1>;
> + };
> +
> + cpu at 2 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <2>;
> + };
> +
> + cpu at 3 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <3>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
You are not numbering the clocks below. Shouldn't this be
#address-cells = <0>;
#size-cells = <0>;
then?
> +
> + smclk: sysmgr-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + sysclk: system-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xf7000000 0x1000000>;
> + interrupt-parent = <&gic>;
> +
> + l2: l2-cache-controller at ac0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xac0000 0x1000>;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller at ad1000 {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0xad1000 0x1000>, <0xad0100 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + local-timer at ad0600 {
Please keep nodes sorted by address.
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0xad0600 0x20>;
> + clocks = <&sysclk>;
Playing with Chromecast, I remember local-timer running at sysclk/3 or
something. I know berlin2/berlin2cd is wrong here. Can you check that
for berlin2q local-timer also runs at sysclk/n?
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> + apb at e80000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xe80000 0x10000>;
> + interrupt-parent = <&aic>;
> +
> + timer0: timer at 2c00 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c00 0x14>;
> + interrupts = <8>;
> + clock-freq = <100000000>;
> + status = "okay";
> + };
> +
> + timer1: timer at 2c14 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0x2c14 0x14>;
> + clock-freq = <100000000>;
> + status = "disabled";
> + };
berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
here or did Marvell remove them?
> + aic: interrupt-controller at 3800 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0x3800 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + apb at fc0000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ranges = <0 0xfc0000 0x10000>;
> + interrupt-parent = <&sic>;
> +
> + uart0: uart at 9000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x9000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <8>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: uart at a000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xa000 0x100>;
> + interrupt-parent = <&sic>;
> + interrupts = <9>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
Also for uart, can you please double-check if there is no uart2?
Sebastian
> + sic: interrupt-controller at e000 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0xe000 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
2014-03-12 11:06 ` Antoine Ténart
@ 2014-03-13 10:08 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:08 UTC (permalink / raw)
To: Antoine Ténart
Cc: alexandre.belloni, zmxu, jszhang, linux-arm-kernel, linux-kernel
On 03/12/2014 11:06 AM, Antoine Ténart wrote:
> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 032030361bef..1a2adadfb962 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
> dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> - berlin2cd-google-chromecast.dtb
> + berlin2cd-google-chromecast.dtb \
> + berlin2q-dmp.dtb
If it is "the" Marvell reference board, the file should be named
berlin2q-marvell-dmp.dtb.
> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
> da850-evm.dtb
> dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts b/arch/arm/boot/dts/berlin2q-dmp.dts
> new file mode 100644
> index 000000000000..6a98860e0251
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q-dmp.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "berlin2q.dtsi"
> +
> +/ {
> + model = "Marvell BG2-Q DMP";
> + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>;
Please double-check Jisheng's comment about memory size.
> + };
> +
> + choosen {
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + soc {
> + apb@fc0000 {
> + uart0: uart@9000 {
> + status = "okay";
> + };
> + };
> + };
And Arnd's comment about using &uart0 instead.
Beside the comments made, this all looks fine.
Sebastian
> +};
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
@ 2014-03-13 10:08 ` Sebastian Hesselbarth
0 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:08 UTC (permalink / raw)
To: linux-arm-kernel
On 03/12/2014 11:06 AM, Antoine T?nart wrote:
> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/berlin2q-dmp.dts | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 032030361bef..1a2adadfb962 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
> dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> - berlin2cd-google-chromecast.dtb
> + berlin2cd-google-chromecast.dtb \
> + berlin2q-dmp.dtb
If it is "the" Marvell reference board, the file should be named
berlin2q-marvell-dmp.dtb.
> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
> da850-evm.dtb
> dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/berlin2q-dmp.dts b/arch/arm/boot/dts/berlin2q-dmp.dts
> new file mode 100644
> index 000000000000..6a98860e0251
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2q-dmp.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2014 Antoine T?nart <antoine.tenart@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "berlin2q.dtsi"
> +
> +/ {
> + model = "Marvell BG2-Q DMP";
> + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>;
Please double-check Jisheng's comment about memory size.
> + };
> +
> + choosen {
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + soc {
> + apb at fc0000 {
> + uart0: uart at 9000 {
> + status = "okay";
> + };
> + };
> + };
And Arnd's comment about using &uart0 instead.
Beside the comments made, this all looks fine.
Sebastian
> +};
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-13 9:56 ` Sebastian Hesselbarth
@ 2014-03-13 10:08 ` Alexandre Belloni
-1 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 10:08 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Antoine Ténart, zmxu, jszhang, linux-kernel, linux-arm-kernel
On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote :
> On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
> >
> >The 25MHz crystal is on the board, please move it to the board dts.
>
> If you can confirm that sysmgr clock comes directly from this crystal,
> I agree. If it is fed into a pll and can possibly be modified or gated,
> make it depend on a 25MHz board crystal. If 25MHz is the only option
> for this clock input, I could also live with it being part of the SoC
> description.
>
Yeah, after more discussion, the 25 MHz crystl is the only option and it
is fed to an oscillator that generate the reference clock for the PLLs.
It is probably fine to let it in the dtsi.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 10:08 ` Alexandre Belloni
0 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 10:08 UTC (permalink / raw)
To: linux-arm-kernel
On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote :
> On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
> >
> >The 25MHz crystal is on the board, please move it to the board dts.
>
> If you can confirm that sysmgr clock comes directly from this crystal,
> I agree. If it is fed into a pll and can possibly be modified or gated,
> make it depend on a 25MHz board crystal. If 25MHz is the only option
> for this clock input, I could also live with it being part of the SoC
> description.
>
Yeah, after more discussion, the 25 MHz crystl is the only option and it
is fed to an oscillator that generate the reference clock for the PLLs.
It is probably fine to let it in the dtsi.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-13 10:08 ` Alexandre Belloni
@ 2014-03-13 10:17 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:17 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Antoine Ténart, zmxu, jszhang, linux-kernel, linux-arm-kernel
On 03/13/2014 10:08 AM, Alexandre Belloni wrote:
> On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote :
>> On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
>>>
>>> The 25MHz crystal is on the board, please move it to the board dts.
>>
>> If you can confirm that sysmgr clock comes directly from this crystal,
>> I agree. If it is fed into a pll and can possibly be modified or gated,
>> make it depend on a 25MHz board crystal. If 25MHz is the only option
>> for this clock input, I could also live with it being part of the SoC
>> description.
>>
>
> Yeah, after more discussion, the 25 MHz crystl is the only option and it
> is fed to an oscillator that generate the reference clock for the PLLs.
> It is probably fine to let it in the dtsi.
>
Fine, I am planing to do more work on Berlin and especially clocks next
cycle. So most of the fixed-clocks will vanish anyway.
BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2.
I'll dig that patch out for you to re-test on Quad-core bg2q.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 10:17 ` Sebastian Hesselbarth
0 siblings, 0 replies; 42+ messages in thread
From: Sebastian Hesselbarth @ 2014-03-13 10:17 UTC (permalink / raw)
To: linux-arm-kernel
On 03/13/2014 10:08 AM, Alexandre Belloni wrote:
> On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote :
>> On 03/12/2014 12:22 PM, Alexandre Belloni wrote:
>>>
>>> The 25MHz crystal is on the board, please move it to the board dts.
>>
>> If you can confirm that sysmgr clock comes directly from this crystal,
>> I agree. If it is fed into a pll and can possibly be modified or gated,
>> make it depend on a 25MHz board crystal. If 25MHz is the only option
>> for this clock input, I could also live with it being part of the SoC
>> description.
>>
>
> Yeah, after more discussion, the 25 MHz crystl is the only option and it
> is fed to an oscillator that generate the reference clock for the PLLs.
> It is probably fine to let it in the dtsi.
>
Fine, I am planing to do more work on Berlin and especially clocks next
cycle. So most of the fixed-clocks will vanish anyway.
BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2.
I'll dig that patch out for you to re-test on Quad-core bg2q.
Sebastian
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-13 10:17 ` Sebastian Hesselbarth
@ 2014-03-13 10:27 ` Antoine Ténart
-1 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-13 10:27 UTC (permalink / raw)
To: Sebastian Hesselbarth, Alexandre Belloni
Cc: zmxu, jszhang, linux-kernel, linux-arm-kernel
On 13/03/2014 11:17, Sebastian Hesselbarth wrote:
> BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2.
> I'll dig that patch out for you to re-test on Quad-core bg2q.
I was just starting to work on the enabling the SMP. Please send me your
patch, I'll test it on the bg2q.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 10:27 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-13 10:27 UTC (permalink / raw)
To: linux-arm-kernel
On 13/03/2014 11:17, Sebastian Hesselbarth wrote:
> BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2.
> I'll dig that patch out for you to re-test on Quad-core bg2q.
I was just starting to work on the enabling the SMP. Please send me your
patch, I'll test it on the bg2q.
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
2014-03-13 9:51 ` Sebastian Hesselbarth
@ 2014-03-13 10:35 ` Antoine Ténart
-1 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-13 10:35 UTC (permalink / raw)
To: Sebastian Hesselbarth, Alexandre Belloni
Cc: zmxu, jszhang, linux-kernel, linux-arm-kernel
Hi Sebastian,
On 13/03/2014 10:51, Sebastian Hesselbarth wrote:
> On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
>> On 12/03/2014 at 12:06:02 +0100, Antoine Ténart wrote :
>>> This serie adds the initial support for the Marvell BG2-Q DMP (part
>>> of the
>>> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
>>> controllers, local timer, apb timers and uarts for now.
>>>
>>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>>>
>>
>> I would move that description to the commit logs. Else one would have to
>> lookup the mailing list archive to read it.
>
> Antoine,
>
> thanks for posting this. I also prefer each patch to have a commit log
> no matter how obvious the contents may be. Please have a simple commit
> log for each of the single patches.
>
> You can leave out the link to marvell.com in the commit log as you
> update Marvell SoC documentation.
I'll cook up a v2 today. Thanks for the feedback !
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP
@ 2014-03-13 10:35 ` Antoine Ténart
0 siblings, 0 replies; 42+ messages in thread
From: Antoine Ténart @ 2014-03-13 10:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sebastian,
On 13/03/2014 10:51, Sebastian Hesselbarth wrote:
> On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
>> On 12/03/2014 at 12:06:02 +0100, Antoine T?nart wrote :
>>> This serie adds the initial support for the Marvell BG2-Q DMP (part
>>> of the
>>> Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
>>> controllers, local timer, apb timers and uarts for now.
>>>
>>> Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
>>>
>>
>> I would move that description to the commit logs. Else one would have to
>> lookup the mailing list archive to read it.
>
> Antoine,
>
> thanks for posting this. I also prefer each patch to have a commit log
> no matter how obvious the contents may be. Please have a simple commit
> log for each of the single patches.
>
> You can leave out the link to marvell.com in the commit log as you
> update Marvell SoC documentation.
I'll cook up a v2 today. Thanks for the feedback !
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-13 10:05 ` Sebastian Hesselbarth
@ 2014-03-13 10:43 ` Alexandre Belloni
-1 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 10:43 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: Antoine Ténart, zmxu, jszhang, linux-arm-kernel, linux-kernel
On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote :
> On 03/12/2014 11:06 AM, Antoine Ténart wrote:
> >+ compatible = "arm,cortex-a9-twd-timer";
> >+ reg = <0xad0600 0x20>;
> >+ clocks = <&sysclk>;
>
> Playing with Chromecast, I remember local-timer running at sysclk/3 or
> something. I know berlin2/berlin2cd is wrong here. Can you check that
> for berlin2q local-timer also runs at sysclk/n?
>
Actually, what we have is sysclk = cpuclk/3 so I guess it depends on
what you call sysclk.
> >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> >+ status = "okay";
> >+ };
> >+
> >+ apb@e80000 {
> >+ compatible = "simple-bus";
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+
> >+ ranges = <0 0xe80000 0x10000>;
> >+ interrupt-parent = <&aic>;
> >+
> >+ timer0: timer@2c00 {
> >+ compatible = "snps,dw-apb-timer";
> >+ reg = <0x2c00 0x14>;
> >+ interrupts = <8>;
> >+ clock-freq = <100000000>;
> >+ status = "okay";
> >+ };
> >+
> >+ timer1: timer@2c14 {
> >+ compatible = "snps,dw-apb-timer";
> >+ reg = <0x2c14 0x14>;
> >+ clock-freq = <100000000>;
> >+ status = "disabled";
> >+ };
>
> berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
> here or did Marvell remove them?
>
>
> Also for uart, can you please double-check if there is no uart2?
>
We don't have those informations, maybe Jisheng can help ?
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 10:43 ` Alexandre Belloni
0 siblings, 0 replies; 42+ messages in thread
From: Alexandre Belloni @ 2014-03-13 10:43 UTC (permalink / raw)
To: linux-arm-kernel
On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote :
> On 03/12/2014 11:06 AM, Antoine T?nart wrote:
> >+ compatible = "arm,cortex-a9-twd-timer";
> >+ reg = <0xad0600 0x20>;
> >+ clocks = <&sysclk>;
>
> Playing with Chromecast, I remember local-timer running at sysclk/3 or
> something. I know berlin2/berlin2cd is wrong here. Can you check that
> for berlin2q local-timer also runs at sysclk/n?
>
Actually, what we have is sysclk = cpuclk/3 so I guess it depends on
what you call sysclk.
> >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> >+ status = "okay";
> >+ };
> >+
> >+ apb at e80000 {
> >+ compatible = "simple-bus";
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+
> >+ ranges = <0 0xe80000 0x10000>;
> >+ interrupt-parent = <&aic>;
> >+
> >+ timer0: timer at 2c00 {
> >+ compatible = "snps,dw-apb-timer";
> >+ reg = <0x2c00 0x14>;
> >+ interrupts = <8>;
> >+ clock-freq = <100000000>;
> >+ status = "okay";
> >+ };
> >+
> >+ timer1: timer at 2c14 {
> >+ compatible = "snps,dw-apb-timer";
> >+ reg = <0x2c14 0x14>;
> >+ clock-freq = <100000000>;
> >+ status = "disabled";
> >+ };
>
> berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
> here or did Marvell remove them?
>
>
> Also for uart, can you please double-check if there is no uart2?
>
We don't have those informations, maybe Jisheng can help ?
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
2014-03-13 10:43 ` Alexandre Belloni
@ 2014-03-13 11:02 ` Jisheng Zhang
-1 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-13 11:02 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Sebastian Hesselbarth, Antoine Ténart, Jimmy Xu,
linux-arm-kernel, linux-kernel
Hi,
On Thu, 13 Mar 2014 03:43:03 -0700
Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:
> On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote :
> > On 03/12/2014 11:06 AM, Antoine Ténart wrote:
> > >+ compatible = "arm,cortex-a9-twd-timer";
> > >+ reg = <0xad0600 0x20>;
> > >+ clocks = <&sysclk>;
> >
> > Playing with Chromecast, I remember local-timer running at sysclk/3 or
twdclk is running at cpuclk/3.
On chromecast, freq of cpuclk is the same as sysclk. But parent of twdclk
is cpuclk.
> > something. I know berlin2/berlin2cd is wrong here. Can you check that
> > for berlin2q local-timer also runs at sysclk/n?
> >
>
> Actually, what we have is sysclk = cpuclk/3 so I guess it depends on
> what you call sysclk.
>
> > >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > >+ status = "okay";
> > >+ };
> > >+
> > >+ apb@e80000 {
> > >+ compatible = "simple-bus";
> > >+ #address-cells = <1>;
> > >+ #size-cells = <1>;
> > >+
> > >+ ranges = <0 0xe80000 0x10000>;
> > >+ interrupt-parent = <&aic>;
> > >+
> > >+ timer0: timer@2c00 {
> > >+ compatible = "snps,dw-apb-timer";
> > >+ reg = <0x2c00 0x14>;
> > >+ interrupts = <8>;
> > >+ clock-freq = <100000000>;
> > >+ status = "okay";
> > >+ };
> > >+
> > >+ timer1: timer@2c14 {
> > >+ compatible = "snps,dw-apb-timer";
> > >+ reg = <0x2c14 0x14>;
> > >+ clock-freq = <100000000>;
> > >+ status = "disabled";
> > >+ };
> >
> > berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
> > here or did Marvell remove them?
We still have 8 apb timers
> >
> >
> > Also for uart, can you please double-check if there is no uart2?
> >
>
> We don't have those informations, maybe Jisheng can help ?
uart2 is removed
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree
@ 2014-03-13 11:02 ` Jisheng Zhang
0 siblings, 0 replies; 42+ messages in thread
From: Jisheng Zhang @ 2014-03-13 11:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Thu, 13 Mar 2014 03:43:03 -0700
Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:
> On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote :
> > On 03/12/2014 11:06 AM, Antoine T?nart wrote:
> > >+ compatible = "arm,cortex-a9-twd-timer";
> > >+ reg = <0xad0600 0x20>;
> > >+ clocks = <&sysclk>;
> >
> > Playing with Chromecast, I remember local-timer running at sysclk/3 or
twdclk is running at cpuclk/3.
On chromecast, freq of cpuclk is the same as sysclk. But parent of twdclk
is cpuclk.
> > something. I know berlin2/berlin2cd is wrong here. Can you check that
> > for berlin2q local-timer also runs at sysclk/n?
> >
>
> Actually, what we have is sysclk = cpuclk/3 so I guess it depends on
> what you call sysclk.
>
> > >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > >+ status = "okay";
> > >+ };
> > >+
> > >+ apb at e80000 {
> > >+ compatible = "simple-bus";
> > >+ #address-cells = <1>;
> > >+ #size-cells = <1>;
> > >+
> > >+ ranges = <0 0xe80000 0x10000>;
> > >+ interrupt-parent = <&aic>;
> > >+
> > >+ timer0: timer at 2c00 {
> > >+ compatible = "snps,dw-apb-timer";
> > >+ reg = <0x2c00 0x14>;
> > >+ interrupts = <8>;
> > >+ clock-freq = <100000000>;
> > >+ status = "okay";
> > >+ };
> > >+
> > >+ timer1: timer at 2c14 {
> > >+ compatible = "snps,dw-apb-timer";
> > >+ reg = <0x2c14 0x14>;
> > >+ clock-freq = <100000000>;
> > >+ status = "disabled";
> > >+ };
> >
> > berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing
> > here or did Marvell remove them?
We still have 8 apb timers
> >
> >
> > Also for uart, can you please double-check if there is no uart2?
> >
>
> We don't have those informations, maybe Jisheng can help ?
uart2 is removed
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2014-03-13 11:04 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-03-12 11:06 [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP Antoine Ténart
2014-03-12 11:06 ` Antoine Ténart
2014-03-12 11:06 ` [PATCH 1/2] ARM: dts: berlin2q: add the Marvell Armada 1500 pro (BG2Q) device tree Antoine Ténart
2014-03-12 11:06 ` Antoine Ténart
2014-03-12 12:22 ` Alexandre Belloni
2014-03-12 12:22 ` Alexandre Belloni
2014-03-13 9:56 ` Sebastian Hesselbarth
2014-03-13 9:56 ` Sebastian Hesselbarth
2014-03-13 10:08 ` Alexandre Belloni
2014-03-13 10:08 ` Alexandre Belloni
2014-03-13 10:17 ` Sebastian Hesselbarth
2014-03-13 10:17 ` Sebastian Hesselbarth
2014-03-13 10:27 ` Antoine Ténart
2014-03-13 10:27 ` Antoine Ténart
2014-03-13 10:05 ` Sebastian Hesselbarth
2014-03-13 10:05 ` Sebastian Hesselbarth
2014-03-13 10:43 ` Alexandre Belloni
2014-03-13 10:43 ` Alexandre Belloni
2014-03-13 11:02 ` Jisheng Zhang
2014-03-13 11:02 ` Jisheng Zhang
2014-03-12 11:06 ` [PATCH 2/2] ARM: dts: berlin2q: add the Marvell BG2-Q DMP " Antoine Ténart
2014-03-12 11:06 ` Antoine Ténart
2014-03-12 11:20 ` Arnd Bergmann
2014-03-12 11:20 ` Arnd Bergmann
2014-03-12 11:30 ` Antoine Ténart
2014-03-12 11:30 ` Antoine Ténart
2014-03-12 12:04 ` Jisheng Zhang
2014-03-12 12:04 ` Jisheng Zhang
2014-03-12 12:37 ` Andrew Lunn
2014-03-12 12:37 ` Andrew Lunn
2014-03-12 12:44 ` Jisheng Zhang
2014-03-12 12:44 ` Jisheng Zhang
2014-03-13 10:08 ` Sebastian Hesselbarth
2014-03-13 10:08 ` Sebastian Hesselbarth
2014-03-12 11:35 ` [PATCH 0/2] ARM: add initial support for the Marvell BG2-Q DMP Alexandre Belloni
2014-03-12 11:35 ` Alexandre Belloni
2014-03-13 9:51 ` Sebastian Hesselbarth
2014-03-13 9:51 ` Sebastian Hesselbarth
2014-03-13 9:56 ` Alexandre Belloni
2014-03-13 9:56 ` Alexandre Belloni
2014-03-13 10:35 ` Antoine Ténart
2014-03-13 10:35 ` Antoine Ténart
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