[PATCH 0/1] clk: mvebu: Core Divider fix for v3.15-rc1

[PATCH 0/1] clk: mvebu: Core Divider fix for v3.15-rc1

[Ezequiel Garcia]

Hi Mike, Jason:

While working on the Core Divider clock for A380, I spotted a small
bug introduced during the Armada 375 core divider clock submission.

The clock ratio register offset is set at 0x8, but the correct value
for this SoC is 0x4.

It's a tiny fix, but given v3.15-rc1 is just around the corner,
I think we can prepare it to be pushed for v3.15-rc2.

Thanks!

Ezequiel Garcia (1):
  clk: mvebu: Fix ratio register offset on A375 SoC

 drivers/clk/mvebu/clk-corediv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
1.9.0

[PATCH 1/1] clk: mvebu: Fix ratio register offset on A375 SoC

[Ezequiel Garcia]

This commit fixes the ratio register offset which is 0x4,
as per the Armada 375 SoC specification.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
 drivers/clk/mvebu/clk-corediv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 4da6076..4af33ba 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
 		.set_rate = clk_corediv_set_rate,
 	},
 	.ratio_reload = BIT(8),
-	.ratio_offset = 0x8,
+	.ratio_offset = 0x4,
 };
 
 static void __init
-- 
1.9.0

[PATCH 1/1] clk: mvebu: Fix ratio register offset on A375 SoC

[Jason Cooper]

On Wed, Mar 12, 2014 at 12:41:41PM -0300, Ezequiel Garcia wrote:
> This commit fixes the ratio register offset which is 0x4,
> as per the Armada 375 SoC specification.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> ---
>  drivers/clk/mvebu/clk-corediv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to mvebu/clk-3xx

thx,

Jason.