[PATCH v2 0/5] berlin: initial support for the clocks

[PATCH v2 0/5] berlin: initial support for the clocks

[Alexandre Belloni]

This series adds support for the berlin PLLs. This allows to remove the bogus
fixed clocks that are used in the SoCs dts includes.

For now, I have left out the AVPLL to ease reviewing.

This is tested on a BG2Q DMP.

Changes in v2:
 - reworked the DT bindings documentation
 - removed the cpuclk node
 - moved the pll node in the soc node and ordered them by address.
 - renamed clk.h => common.h and removed the stray #include
 - reordered the includes in pll-*.c
 - extended the vcodiv tables so that we can't overflow it
 - reordered the struct berlin_pllmap members assignements
 - replaced the void *data member of the struct berlin_pll by a
   struct berlin_pllmap *map

Alexandre Belloni (5):
  clk: berlin: add support for berlin plls
  clk: berlin: add berlin clocks DT bindings documentation
  ARM: berlin/dt: add cpupll and syspll support to BG2Q
  ARM: berlin/dt: add cpupll and syspll support to BG2CD
  ARM: berlin/dt: add cpupll and syspll support to BG2

 .../devicetree/bindings/clock/berlin-clock.txt     |  29 ++++++
 arch/arm/boot/dts/berlin2.dtsi                     |  48 +++++----
 arch/arm/boot/dts/berlin2cd.dtsi                   |  48 +++++----
 arch/arm/boot/dts/berlin2q.dtsi                    |  22 +++--
 drivers/clk/Makefile                               |   1 +
 drivers/clk/berlin/Makefile                        |   4 +
 drivers/clk/berlin/common.h                        |  35 +++++++
 drivers/clk/berlin/pll-berlin2.c                   |  42 ++++++++
 drivers/clk/berlin/pll-berlin2q.c                  |  42 ++++++++
 drivers/clk/berlin/pll.c                           | 107 +++++++++++++++++++++
 10 files changed, 337 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
 create mode 100644 drivers/clk/berlin/Makefile
 create mode 100644 drivers/clk/berlin/common.h
 create mode 100644 drivers/clk/berlin/pll-berlin2.c
 create mode 100644 drivers/clk/berlin/pll-berlin2q.c
 create mode 100644 drivers/clk/berlin/pll.c

-- 
1.8.3.2

[PATCH v2 0/5] berlin: initial support for the clocks

[Alexandre Belloni]

This series adds support for the berlin PLLs. This allows to remove the bogus
fixed clocks that are used in the SoCs dts includes.

For now, I have left out the AVPLL to ease reviewing.

This is tested on a BG2Q DMP.

Changes in v2:
 - reworked the DT bindings documentation
 - removed the cpuclk node
 - moved the pll node in the soc node and ordered them by address.
 - renamed clk.h => common.h and removed the stray #include
 - reordered the includes in pll-*.c
 - extended the vcodiv tables so that we can't overflow it
 - reordered the struct berlin_pllmap members assignements
 - replaced the void *data member of the struct berlin_pll by a
   struct berlin_pllmap *map

Alexandre Belloni (5):
  clk: berlin: add support for berlin plls
  clk: berlin: add berlin clocks DT bindings documentation
  ARM: berlin/dt: add cpupll and syspll support to BG2Q
  ARM: berlin/dt: add cpupll and syspll support to BG2CD
  ARM: berlin/dt: add cpupll and syspll support to BG2

 .../devicetree/bindings/clock/berlin-clock.txt     |  29 ++++++
 arch/arm/boot/dts/berlin2.dtsi                     |  48 +++++----
 arch/arm/boot/dts/berlin2cd.dtsi                   |  48 +++++----
 arch/arm/boot/dts/berlin2q.dtsi                    |  22 +++--
 drivers/clk/Makefile                               |   1 +
 drivers/clk/berlin/Makefile                        |   4 +
 drivers/clk/berlin/common.h                        |  35 +++++++
 drivers/clk/berlin/pll-berlin2.c                   |  42 ++++++++
 drivers/clk/berlin/pll-berlin2q.c                  |  42 ++++++++
 drivers/clk/berlin/pll.c                           | 107 +++++++++++++++++++++
 10 files changed, 337 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
 create mode 100644 drivers/clk/berlin/Makefile
 create mode 100644 drivers/clk/berlin/common.h
 create mode 100644 drivers/clk/berlin/pll-berlin2.c
 create mode 100644 drivers/clk/berlin/pll-berlin2q.c
 create mode 100644 drivers/clk/berlin/pll.c

-- 
1.8.3.2

[PATCH v2 1/5] clk: berlin: add support for berlin plls

[Alexandre Belloni]

This drivers allows to provide DT clocks for the cpu and system PLLs found on
Marvell Berlin SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 drivers/clk/Makefile              |   1 +
 drivers/clk/berlin/Makefile       |   4 ++
 drivers/clk/berlin/common.h       |  35 +++++++++++++
 drivers/clk/berlin/pll-berlin2.c  |  42 +++++++++++++++
 drivers/clk/berlin/pll-berlin2q.c |  42 +++++++++++++++
 drivers/clk/berlin/pll.c          | 107 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 231 insertions(+)
 create mode 100644 drivers/clk/berlin/Makefile
 create mode 100644 drivers/clk/berlin/common.h
 create mode 100644 drivers/clk/berlin/pll-berlin2.c
 create mode 100644 drivers/clk/berlin/pll-berlin2q.c
 create mode 100644 drivers/clk/berlin/pll.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a367a9831717..4a2602737c27 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
 obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
+obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_HI3xxx)		+= hisilicon/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/
 ifeq ($(CONFIG_COMMON_CLK), y)
diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
new file mode 100644
index 000000000000..94859513de90
--- /dev/null
+++ b/drivers/clk/berlin/Makefile
@@ -0,0 +1,4 @@
+obj-y += pll.o
+obj-$(CONFIG_MACH_BERLIN_BG2)   += pll-berlin2.o
+obj-$(CONFIG_MACH_BERLIN_BG2CD) += pll-berlin2.o
+obj-$(CONFIG_MACH_BERLIN_BG2Q)  += pll-berlin2q.o
diff --git a/drivers/clk/berlin/common.h b/drivers/clk/berlin/common.h
new file mode 100644
index 000000000000..8eb8a9f9aa30
--- /dev/null
+++ b/drivers/clk/berlin/common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __BERLIN_CLK_H
+#define __BERLIN_CLK_H
+
+struct device_node;
+
+struct berlin_pllmap {
+	const u8	*vcodiv;
+	u32		fbdiv_mask;
+	u32		rfdiv_mask;
+	u32		divsel_mask;
+	u8		fbdiv_shift;
+	u8		rfdiv_shift;
+	u8		divsel_shift;
+	u8		mult;
+};
+
+extern void __init berlin_pll_setup(struct device_node *np,
+				struct berlin_pllmap *map);
+
+#endif /* BERLIN_CLK_H */
diff --git a/drivers/clk/berlin/pll-berlin2.c b/drivers/clk/berlin/pll-berlin2.c
new file mode 100644
index 000000000000..3b2f5856442d
--- /dev/null
+++ b/drivers/clk/berlin/pll-berlin2.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include "common.h"
+
+static const u8 vcodiv_berlin2[] = {10, 15, 20, 25, 30, 40, 50, 60, 80,
+				    1, 1, 1, 1, 1, 1, 1};
+
+static struct berlin_pllmap berlin_pll_map = {
+	.vcodiv = vcodiv_berlin2,
+	.fbdiv_mask = 0x1FF,
+	.fbdiv_shift = 6,
+	.rfdiv_mask = 0x1F,
+	.rfdiv_shift = 1,
+	.divsel_mask = 0xF,
+	.divsel_shift = 7,
+	.mult = 10,
+};
+
+static void __init berlin2_pll_setup(struct device_node *np)
+{
+	berlin_pll_setup(np, &berlin_pll_map);
+}
+CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2-pll", berlin2_pll_setup);
+
diff --git a/drivers/clk/berlin/pll-berlin2q.c b/drivers/clk/berlin/pll-berlin2q.c
new file mode 100644
index 000000000000..0a2e9968cc09
--- /dev/null
+++ b/drivers/clk/berlin/pll-berlin2q.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include "common.h"
+
+static const u8 vcodiv_berlin2q[] = {1, 0, 2, 0, 3, 4, 0, 6, 8,
+				     1, 1, 1, 1, 1, 1, 1};
+
+static struct berlin_pllmap berlin2q_pll_map = {
+	.vcodiv = vcodiv_berlin2q,
+	.fbdiv_mask = 0x1FF,
+	.fbdiv_shift = 7,
+	.rfdiv_mask = 0x1F,
+	.rfdiv_shift = 2,
+	.divsel_mask = 0xF,
+	.divsel_shift = 9,
+	.mult = 1,
+};
+
+static void __init berlin2q_pll_setup(struct device_node *np)
+{
+	berlin_pll_setup(np, &berlin2q_pll_map);
+}
+CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2q-pll", berlin2q_pll_setup);
+
diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
new file mode 100644
index 000000000000..264c48d6e797
--- /dev/null
+++ b/drivers/clk/berlin/pll.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "common.h"
+
+struct berlin_pll {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	struct berlin_pllmap	*map;
+};
+
+#define to_berlin_pll(hw)	container_of(hw, struct berlin_pll, hw)
+
+#define PLL_CTRL0	0x00
+#define PLL_CTRL1	0x04
+
+static inline u32 berlin_pll_read(struct berlin_pll *pll, unsigned long offset)
+{
+	return readl_relaxed(pll->base + offset);
+}
+
+/*
+ * The output frequency formula for the pll is:
+ * clkout = fbdiv / refdiv * parent / vcodiv
+ * Note that for BG2, BG2CD and BG2Q, the parent clock is provided by the SM
+ * oscillator and is always 25MHz.
+ */
+static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	struct berlin_pll *pll = to_berlin_pll(hw);
+	struct berlin_pllmap *map = pll->map;
+	u32 val, fbdiv, rfdiv, vcodivsel;
+
+	val = berlin_pll_read(pll, PLL_CTRL0);
+	fbdiv = (val >> map->fbdiv_shift) & map->fbdiv_mask;
+	rfdiv = (val >> map->rfdiv_shift) & map->rfdiv_mask;
+	if (rfdiv == 0)
+		rfdiv = 1;
+
+	val = berlin_pll_read(pll, PLL_CTRL1);
+	vcodivsel = (val >> map->divsel_shift) & map->divsel_mask;
+
+	parent_rate *= fbdiv * map->mult;
+	parent_rate /= rfdiv;
+	return parent_rate / map->vcodiv[vcodivsel];
+}
+
+static const struct clk_ops berlin_pll_ops = {
+	.recalc_rate	= berlin_pll_recalc_rate,
+};
+
+void __init berlin_pll_setup(struct device_node *np,
+			struct berlin_pllmap *map)
+{
+	struct clk_init_data init;
+	struct berlin_pll *pll;
+	const char *parent_name;
+	struct clk *clk;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (WARN_ON(!pll))
+		return;
+
+	pll->base = of_iomap(np, 0);
+	if (WARN_ON(!pll->base))
+		return;
+
+	pll->map = map;
+
+	init.name = np->name;
+	init.ops = &berlin_pll_ops;
+	parent_name = of_clk_get_parent_name(np, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	pll->hw.init = &init;
+
+	clk = clk_register(NULL, &pll->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		return;
+}
+
-- 
1.8.3.2

[PATCH v2 1/5] clk: berlin: add support for berlin plls

[Alexandre Belloni]

This drivers allows to provide DT clocks for the cpu and system PLLs found on
Marvell Berlin SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 drivers/clk/Makefile              |   1 +
 drivers/clk/berlin/Makefile       |   4 ++
 drivers/clk/berlin/common.h       |  35 +++++++++++++
 drivers/clk/berlin/pll-berlin2.c  |  42 +++++++++++++++
 drivers/clk/berlin/pll-berlin2q.c |  42 +++++++++++++++
 drivers/clk/berlin/pll.c          | 107 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 231 insertions(+)
 create mode 100644 drivers/clk/berlin/Makefile
 create mode 100644 drivers/clk/berlin/common.h
 create mode 100644 drivers/clk/berlin/pll-berlin2.c
 create mode 100644 drivers/clk/berlin/pll-berlin2q.c
 create mode 100644 drivers/clk/berlin/pll.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a367a9831717..4a2602737c27 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
 obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
+obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_HI3xxx)		+= hisilicon/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/
 ifeq ($(CONFIG_COMMON_CLK), y)
diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
new file mode 100644
index 000000000000..94859513de90
--- /dev/null
+++ b/drivers/clk/berlin/Makefile
@@ -0,0 +1,4 @@
+obj-y += pll.o
+obj-$(CONFIG_MACH_BERLIN_BG2)   += pll-berlin2.o
+obj-$(CONFIG_MACH_BERLIN_BG2CD) += pll-berlin2.o
+obj-$(CONFIG_MACH_BERLIN_BG2Q)  += pll-berlin2q.o
diff --git a/drivers/clk/berlin/common.h b/drivers/clk/berlin/common.h
new file mode 100644
index 000000000000..8eb8a9f9aa30
--- /dev/null
+++ b/drivers/clk/berlin/common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __BERLIN_CLK_H
+#define __BERLIN_CLK_H
+
+struct device_node;
+
+struct berlin_pllmap {
+	const u8	*vcodiv;
+	u32		fbdiv_mask;
+	u32		rfdiv_mask;
+	u32		divsel_mask;
+	u8		fbdiv_shift;
+	u8		rfdiv_shift;
+	u8		divsel_shift;
+	u8		mult;
+};
+
+extern void __init berlin_pll_setup(struct device_node *np,
+				struct berlin_pllmap *map);
+
+#endif /* BERLIN_CLK_H */
diff --git a/drivers/clk/berlin/pll-berlin2.c b/drivers/clk/berlin/pll-berlin2.c
new file mode 100644
index 000000000000..3b2f5856442d
--- /dev/null
+++ b/drivers/clk/berlin/pll-berlin2.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include "common.h"
+
+static const u8 vcodiv_berlin2[] = {10, 15, 20, 25, 30, 40, 50, 60, 80,
+				    1, 1, 1, 1, 1, 1, 1};
+
+static struct berlin_pllmap berlin_pll_map = {
+	.vcodiv = vcodiv_berlin2,
+	.fbdiv_mask = 0x1FF,
+	.fbdiv_shift = 6,
+	.rfdiv_mask = 0x1F,
+	.rfdiv_shift = 1,
+	.divsel_mask = 0xF,
+	.divsel_shift = 7,
+	.mult = 10,
+};
+
+static void __init berlin2_pll_setup(struct device_node *np)
+{
+	berlin_pll_setup(np, &berlin_pll_map);
+}
+CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2-pll", berlin2_pll_setup);
+
diff --git a/drivers/clk/berlin/pll-berlin2q.c b/drivers/clk/berlin/pll-berlin2q.c
new file mode 100644
index 000000000000..0a2e9968cc09
--- /dev/null
+++ b/drivers/clk/berlin/pll-berlin2q.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include "common.h"
+
+static const u8 vcodiv_berlin2q[] = {1, 0, 2, 0, 3, 4, 0, 6, 8,
+				     1, 1, 1, 1, 1, 1, 1};
+
+static struct berlin_pllmap berlin2q_pll_map = {
+	.vcodiv = vcodiv_berlin2q,
+	.fbdiv_mask = 0x1FF,
+	.fbdiv_shift = 7,
+	.rfdiv_mask = 0x1F,
+	.rfdiv_shift = 2,
+	.divsel_mask = 0xF,
+	.divsel_shift = 9,
+	.mult = 1,
+};
+
+static void __init berlin2q_pll_setup(struct device_node *np)
+{
+	berlin_pll_setup(np, &berlin2q_pll_map);
+}
+CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2q-pll", berlin2q_pll_setup);
+
diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
new file mode 100644
index 000000000000..264c48d6e797
--- /dev/null
+++ b/drivers/clk/berlin/pll.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "common.h"
+
+struct berlin_pll {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	struct berlin_pllmap	*map;
+};
+
+#define to_berlin_pll(hw)	container_of(hw, struct berlin_pll, hw)
+
+#define PLL_CTRL0	0x00
+#define PLL_CTRL1	0x04
+
+static inline u32 berlin_pll_read(struct berlin_pll *pll, unsigned long offset)
+{
+	return readl_relaxed(pll->base + offset);
+}
+
+/*
+ * The output frequency formula for the pll is:
+ * clkout = fbdiv / refdiv * parent / vcodiv
+ * Note that for BG2, BG2CD and BG2Q, the parent clock is provided by the SM
+ * oscillator and is always 25MHz.
+ */
+static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	struct berlin_pll *pll = to_berlin_pll(hw);
+	struct berlin_pllmap *map = pll->map;
+	u32 val, fbdiv, rfdiv, vcodivsel;
+
+	val = berlin_pll_read(pll, PLL_CTRL0);
+	fbdiv = (val >> map->fbdiv_shift) & map->fbdiv_mask;
+	rfdiv = (val >> map->rfdiv_shift) & map->rfdiv_mask;
+	if (rfdiv == 0)
+		rfdiv = 1;
+
+	val = berlin_pll_read(pll, PLL_CTRL1);
+	vcodivsel = (val >> map->divsel_shift) & map->divsel_mask;
+
+	parent_rate *= fbdiv * map->mult;
+	parent_rate /= rfdiv;
+	return parent_rate / map->vcodiv[vcodivsel];
+}
+
+static const struct clk_ops berlin_pll_ops = {
+	.recalc_rate	= berlin_pll_recalc_rate,
+};
+
+void __init berlin_pll_setup(struct device_node *np,
+			struct berlin_pllmap *map)
+{
+	struct clk_init_data init;
+	struct berlin_pll *pll;
+	const char *parent_name;
+	struct clk *clk;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (WARN_ON(!pll))
+		return;
+
+	pll->base = of_iomap(np, 0);
+	if (WARN_ON(!pll->base))
+		return;
+
+	pll->map = map;
+
+	init.name = np->name;
+	init.ops = &berlin_pll_ops;
+	parent_name = of_clk_get_parent_name(np, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	pll->hw.init = &init;
+
+	clk = clk_register(NULL, &pll->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		return;
+}
+
-- 
1.8.3.2

[PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Alexandre Belloni]

Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.

Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
new file mode 100644
index 000000000000..49b7860bffb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -0,0 +1,29 @@
+Device Tree Clock bindings for Marvell Berlin clocks
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be one of the following:
+	"marvell,berlin2-pll",
+	"marvell,berlin2q-pll":
+		CPU PLL and System PLL
+- reg: Address and length of the clock register set.
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: from common clock binding
+
+smclk: sysmgr-clock {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <25000000>;
+};
+
+cpupll: cpupll@ea003c {
+	compatible = "marvell,berlin2-pll";
+	clocks = <&smclk>;
+	#clock-cells = <0>;
+	reg = <0xea003c 0x8>;
+};
+
+
-- 
1.8.3.2

[PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Alexandre Belloni]

Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.

Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
new file mode 100644
index 000000000000..49b7860bffb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -0,0 +1,29 @@
+Device Tree Clock bindings for Marvell Berlin clocks
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be one of the following:
+	"marvell,berlin2-pll",
+	"marvell,berlin2q-pll":
+		CPU PLL and System PLL
+- reg: Address and length of the clock register set.
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: from common clock binding
+
+smclk: sysmgr-clock {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <25000000>;
+};
+
+cpupll: cpupll@ea003c {
+	compatible = "marvell,berlin2-pll";
+	clocks = <&smclk>;
+	#clock-cells = <0>;
+	reg = <0xea003c 0x8>;
+};
+
+
-- 
1.8.3.2

[PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Alexandre Belloni]

Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.

Cc: devicetree at vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
new file mode 100644
index 000000000000..49b7860bffb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -0,0 +1,29 @@
+Device Tree Clock bindings for Marvell Berlin clocks
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be one of the following:
+	"marvell,berlin2-pll",
+	"marvell,berlin2q-pll":
+		CPU PLL and System PLL
+- reg: Address and length of the clock register set.
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: from common clock binding
+
+smclk: sysmgr-clock {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <25000000>;
+};
+
+cpupll: cpupll at ea003c {
+	compatible = "marvell,berlin2-pll";
+	clocks = <&smclk>;
+	#clock-cells = <0>;
+	reg = <0xea003c 0x8>;
+};
+
+
-- 
1.8.3.2

[PATCH v2 3/5] ARM: berlin/dt: add cpupll and syspll support to BG2Q

[Alexandre Belloni]

The Berlin BG2Q has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.

Note that support for the AVPLL is not yet available.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2q.dtsi | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 07452a7483fa..5925e6a16749 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -59,16 +59,10 @@
 		clock-frequency = <100000000>;
 	};
 
-	cpuclk: cpu-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1200000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
-		clocks = <&cpuclk>;
+		clocks = <&cpupll>;
 		clock-mult = <1>;
 		clock-div = <3>;
 	};
@@ -101,6 +95,20 @@
 			#interrupt-cells = <3>;
 		};
 
+		cpupll: cpupll@dd0170 {
+			compatible = "marvell,berlin2q-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xdd0170 0x8>;
+		};
+
+		syspll: syspll@ea0030 {
+			compatible = "marvell,berlin2q-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea0030 0x8>;
+		};
+
 		apb@e80000 {
 			compatible = "simple-bus";
 			#address-cells = <1>;
-- 
1.8.3.2

[PATCH v2 3/5] ARM: berlin/dt: add cpupll and syspll support to BG2Q

[Alexandre Belloni]

The Berlin BG2Q has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.

Note that support for the AVPLL is not yet available.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2q.dtsi | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 07452a7483fa..5925e6a16749 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -59,16 +59,10 @@
 		clock-frequency = <100000000>;
 	};
 
-	cpuclk: cpu-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1200000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
-		clocks = <&cpuclk>;
+		clocks = <&cpupll>;
 		clock-mult = <1>;
 		clock-div = <3>;
 	};
@@ -101,6 +95,20 @@
 			#interrupt-cells = <3>;
 		};
 
+		cpupll: cpupll at dd0170 {
+			compatible = "marvell,berlin2q-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xdd0170 0x8>;
+		};
+
+		syspll: syspll at ea0030 {
+			compatible = "marvell,berlin2q-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea0030 0x8>;
+		};
+
 		apb at e80000 {
 			compatible = "simple-bus";
 			#address-cells = <1>;
-- 
1.8.3.2

[PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Alexandre Belloni]

The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
the SoC device tree.

This also moves the remaining clocks from the clocks container node to the root.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 094968c27533..bd4e9dd4867e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -30,24 +30,24 @@
 		};
 	};
 
-	clocks {
-		smclk: sysmgr-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <25000000>;
-		};
+	smclk: sysmgr-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
 
-		cfgclk: cfg-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <75000000>;
-		};
+	cfgclk: cfg-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <75000000>;
+	};
 
-		sysclk: system-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <300000000>;
-		};
+	twdclk: twdclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&cpupll>;
+		clock-mult = <1>;
+		clock-div = <3>;
 	};
 
 	soc {
@@ -76,7 +76,21 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sysclk>;
+			clocks = <&twdclk>;
+		};
+
+		syspll: syspll@ea0014 {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xf7ea0014 8>;
+		};
+
+		cpupll: cpupll@ea003c {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xf7ea003c 8>;
 		};
 
 		apb@e80000 {
-- 
1.8.3.2

[PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Alexandre Belloni]

The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
the SoC device tree.

This also moves the remaining clocks from the clocks container node to the root.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 094968c27533..bd4e9dd4867e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -30,24 +30,24 @@
 		};
 	};
 
-	clocks {
-		smclk: sysmgr-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <25000000>;
-		};
+	smclk: sysmgr-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
 
-		cfgclk: cfg-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <75000000>;
-		};
+	cfgclk: cfg-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <75000000>;
+	};
 
-		sysclk: system-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <300000000>;
-		};
+	twdclk: twdclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&cpupll>;
+		clock-mult = <1>;
+		clock-div = <3>;
 	};
 
 	soc {
@@ -76,7 +76,21 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sysclk>;
+			clocks = <&twdclk>;
+		};
+
+		syspll: syspll at ea0014 {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xf7ea0014 8>;
+		};
+
+		cpupll: cpupll at ea003c {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xf7ea003c 8>;
 		};
 
 		apb at e80000 {
-- 
1.8.3.2

[PATCH v2 5/5] ARM: berlin/dt: add cpupll and syspll support to BG2

[Alexandre Belloni]

The Berlin BG2 has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.

This also moves the remaining clocks from the clocks container node to the root.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2.dtsi | 48 +++++++++++++++++++++++++++---------------
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f1052..6c080eb6242a 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -37,24 +37,24 @@
 		};
 	};
 
-	clocks {
-		smclk: sysmgr-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <25000000>;
-		};
+	smclk: sysmgr-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
 
-		cfgclk: cfg-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <100000000>;
-		};
+	cfgclk: cfg-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
 
-		sysclk: system-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <400000000>;
-		};
+	twdclk: twdclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&cpupll>;
+		clock-mult = <1>;
+		clock-div = <3>;
 	};
 
 	soc {
@@ -83,7 +83,21 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sysclk>;
+			clocks = <&twdclk>;
+		};
+
+		syspll: syspll@ea0014 {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea0014 8>;
+		};
+
+		cpupll: cpupll@ea003c {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea003c 8>;
 		};
 
 		apb@e80000 {
-- 
1.8.3.2

[PATCH v2 5/5] ARM: berlin/dt: add cpupll and syspll support to BG2

[Alexandre Belloni]

The Berlin BG2 has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.

This also moves the remaining clocks from the clocks container node to the root.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2.dtsi | 48 +++++++++++++++++++++++++++---------------
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f1052..6c080eb6242a 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -37,24 +37,24 @@
 		};
 	};
 
-	clocks {
-		smclk: sysmgr-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <25000000>;
-		};
+	smclk: sysmgr-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
 
-		cfgclk: cfg-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <100000000>;
-		};
+	cfgclk: cfg-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
 
-		sysclk: system-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <400000000>;
-		};
+	twdclk: twdclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&cpupll>;
+		clock-mult = <1>;
+		clock-div = <3>;
 	};
 
 	soc {
@@ -83,7 +83,21 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sysclk>;
+			clocks = <&twdclk>;
+		};
+
+		syspll: syspll at ea0014 {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea0014 8>;
+		};
+
+		cpupll: cpupll at ea003c {
+			compatible = "marvell,berlin2-pll";
+			clocks = <&smclk>;
+			#clock-cells = <0>;
+			reg = <0xea003c 8>;
 		};
 
 		apb at e80000 {
-- 
1.8.3.2

Re: [PATCH v2 1/5] clk: berlin: add support for berlin plls

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> This drivers allows to provide DT clocks for the cpu and system PLLs found on
> Marvell Berlin SoCs.

Alexandre,

as mentioned on IRC, I now had a closer look on it. Some minor
remarks below. Sorry, I didn't mention them earlier.

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
[...]
> --- /dev/null
> +++ b/drivers/clk/berlin/pll-berlin2.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +
> +#include "common.h"
> +
> +static const u8 vcodiv_berlin2[] = {10, 15, 20, 25, 30, 40, 50, 60, 80,
> +				    1, 1, 1, 1, 1, 1, 1};

As there are already zeroes in vcodiv_berlin2q below, we should rather
make the above

static const u8 vcodiv_berlin2[16] = {10, 15, 20, 25, 30, 40, 50, 60, 80};

And check for vcodiv == 0 in berlin_pll_recalc_rate below.

> +static struct berlin_pllmap berlin_pll_map = {
> +	.vcodiv = vcodiv_berlin2,
> +	.fbdiv_mask = 0x1FF,
> +	.fbdiv_shift = 6,
> +	.rfdiv_mask = 0x1F,
> +	.rfdiv_shift = 1,
> +	.divsel_mask = 0xF,
> +	.divsel_shift = 7,
> +	.mult = 10,
> +};
> +
> +static void __init berlin2_pll_setup(struct device_node *np)
> +{
> +	berlin_pll_setup(np, &berlin_pll_map);
> +}
> +CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2-pll", berlin2_pll_setup);

s/berlin2q_pll/berlin2_pll

> +

Remove empty line above.

> diff --git a/drivers/clk/berlin/pll-berlin2q.c b/drivers/clk/berlin/pll-berlin2q.c
> new file mode 100644
> index 000000000000..0a2e9968cc09
> --- /dev/null
> +++ b/drivers/clk/berlin/pll-berlin2q.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +
> +#include "common.h"
> +
> +static const u8 vcodiv_berlin2q[] = {1, 0, 2, 0, 3, 4, 0, 6, 8,
> +				     1, 1, 1, 1, 1, 1, 1};

Same comment as for vcodiv_berlin2.

> +static struct berlin_pllmap berlin2q_pll_map = {
> +	.vcodiv = vcodiv_berlin2q,
> +	.fbdiv_mask = 0x1FF,
> +	.fbdiv_shift = 7,
> +	.rfdiv_mask = 0x1F,
> +	.rfdiv_shift = 2,
> +	.divsel_mask = 0xF,
> +	.divsel_shift = 9,
> +	.mult = 1,
> +};
> +
> +static void __init berlin2q_pll_setup(struct device_node *np)
> +{
> +	berlin_pll_setup(np, &berlin2q_pll_map);
> +}
> +CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2q-pll", berlin2q_pll_setup);
> +

Remove empty line above.

> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 000000000000..264c48d6e797
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,107 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +
> +#include "common.h"
> +
> +struct berlin_pll {
> +	struct clk_hw		hw;
> +	void __iomem		*base;
> +	struct berlin_pllmap	*map;
> +};
> +
> +#define to_berlin_pll(hw)	container_of(hw, struct berlin_pll, hw)
> +
> +#define PLL_CTRL0	0x00
> +#define PLL_CTRL1	0x04
> +
> +static inline u32 berlin_pll_read(struct berlin_pll *pll, unsigned long offset)
> +{
> +	return readl_relaxed(pll->base + offset);
> +}
> +
> +/*
> + * The output frequency formula for the pll is:
> + * clkout = fbdiv / refdiv * parent / vcodiv

That comment is enough, remove the one below.

> + * Note that for BG2, BG2CD and BG2Q, the parent clock is provided by the SM
> + * oscillator and is always 25MHz.
> + */
> +static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
> +					unsigned long parent_rate)
> +{
> +	struct berlin_pll *pll = to_berlin_pll(hw);
> +	struct berlin_pllmap *map = pll->map;
> +	u32 val, fbdiv, rfdiv, vcodivsel;
> +
> +	val = berlin_pll_read(pll, PLL_CTRL0);
> +	fbdiv = (val >> map->fbdiv_shift) & map->fbdiv_mask;
> +	rfdiv = (val >> map->rfdiv_shift) & map->rfdiv_mask;
> +	if (rfdiv == 0)
> +		rfdiv = 1;

if (rfdiv) {
	pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
	rfdiv = 1;
}

> +
> +	val = berlin_pll_read(pll, PLL_CTRL1);
> +	vcodivsel = (val >> map->divsel_shift) & map->divsel_mask;

As map->vcodiv can contain zeros, we should rather do

vcodiv = map->vcodiv[vcodivsel];
if (vcodiv) {
	pr_warn("%s has zero vcodiv\n", __clk_get_name(hw->clk));
	vcodiv = 1;
}

> +	parent_rate *= fbdiv * map->mult;
> +	parent_rate /= rfdiv;
> +	return parent_rate / map->vcodiv[vcodivsel];

With parent_rate = 25M and max(fbdiv) == 511 we can possibly
exceed 32b range. So, we should rather switch to u64 here:

#include <asm/div64.h>

u64 rate = parent_rate;

...

rate *= fbdiv * map->mult;
do_div(rate, vcodiv * rfdiv);
return (unsigned long)rate;

Besides the comments, this really looks good to me. We may have
to rebase some of it onto v3.15-rc1 as soon as it drops, but I
can take care of it.

Sebastian

> +}
> +
> +static const struct clk_ops berlin_pll_ops = {
> +	.recalc_rate	= berlin_pll_recalc_rate,
> +};
> +
> +void __init berlin_pll_setup(struct device_node *np,
> +			struct berlin_pllmap *map)
> +{
> +	struct clk_init_data init;
> +	struct berlin_pll *pll;
> +	const char *parent_name;
> +	struct clk *clk;
> +	int ret;
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (WARN_ON(!pll))
> +		return;
> +
> +	pll->base = of_iomap(np, 0);
> +	if (WARN_ON(!pll->base))
> +		return;
> +
> +	pll->map = map;
> +
> +	init.name = np->name;
> +	init.ops = &berlin_pll_ops;
> +	parent_name = of_clk_get_parent_name(np, 0);
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +
> +	pll->hw.init = &init;
> +
> +	clk = clk_register(NULL, &pll->hw);
> +	if (WARN_ON(IS_ERR(clk)))
> +		return;
> +
> +	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +	if (WARN_ON(ret))
> +		return;
> +}
> +
>

[PATCH v2 1/5] clk: berlin: add support for berlin plls

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> This drivers allows to provide DT clocks for the cpu and system PLLs found on
> Marvell Berlin SoCs.

Alexandre,

as mentioned on IRC, I now had a closer look on it. Some minor
remarks below. Sorry, I didn't mention them earlier.

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
[...]
> --- /dev/null
> +++ b/drivers/clk/berlin/pll-berlin2.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +
> +#include "common.h"
> +
> +static const u8 vcodiv_berlin2[] = {10, 15, 20, 25, 30, 40, 50, 60, 80,
> +				    1, 1, 1, 1, 1, 1, 1};

As there are already zeroes in vcodiv_berlin2q below, we should rather
make the above

static const u8 vcodiv_berlin2[16] = {10, 15, 20, 25, 30, 40, 50, 60, 80};

And check for vcodiv == 0 in berlin_pll_recalc_rate below.

> +static struct berlin_pllmap berlin_pll_map = {
> +	.vcodiv = vcodiv_berlin2,
> +	.fbdiv_mask = 0x1FF,
> +	.fbdiv_shift = 6,
> +	.rfdiv_mask = 0x1F,
> +	.rfdiv_shift = 1,
> +	.divsel_mask = 0xF,
> +	.divsel_shift = 7,
> +	.mult = 10,
> +};
> +
> +static void __init berlin2_pll_setup(struct device_node *np)
> +{
> +	berlin_pll_setup(np, &berlin_pll_map);
> +}
> +CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2-pll", berlin2_pll_setup);

s/berlin2q_pll/berlin2_pll

> +

Remove empty line above.

> diff --git a/drivers/clk/berlin/pll-berlin2q.c b/drivers/clk/berlin/pll-berlin2q.c
> new file mode 100644
> index 000000000000..0a2e9968cc09
> --- /dev/null
> +++ b/drivers/clk/berlin/pll-berlin2q.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +
> +#include "common.h"
> +
> +static const u8 vcodiv_berlin2q[] = {1, 0, 2, 0, 3, 4, 0, 6, 8,
> +				     1, 1, 1, 1, 1, 1, 1};

Same comment as for vcodiv_berlin2.

> +static struct berlin_pllmap berlin2q_pll_map = {
> +	.vcodiv = vcodiv_berlin2q,
> +	.fbdiv_mask = 0x1FF,
> +	.fbdiv_shift = 7,
> +	.rfdiv_mask = 0x1F,
> +	.rfdiv_shift = 2,
> +	.divsel_mask = 0xF,
> +	.divsel_shift = 9,
> +	.mult = 1,
> +};
> +
> +static void __init berlin2q_pll_setup(struct device_node *np)
> +{
> +	berlin_pll_setup(np, &berlin2q_pll_map);
> +}
> +CLK_OF_DECLARE(berlin2q_pll, "marvell,berlin2q-pll", berlin2q_pll_setup);
> +

Remove empty line above.

> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 000000000000..264c48d6e797
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,107 @@
> +/*
> + * Copyright (c) 2014 Marvell Technology Group Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +
> +#include "common.h"
> +
> +struct berlin_pll {
> +	struct clk_hw		hw;
> +	void __iomem		*base;
> +	struct berlin_pllmap	*map;
> +};
> +
> +#define to_berlin_pll(hw)	container_of(hw, struct berlin_pll, hw)
> +
> +#define PLL_CTRL0	0x00
> +#define PLL_CTRL1	0x04
> +
> +static inline u32 berlin_pll_read(struct berlin_pll *pll, unsigned long offset)
> +{
> +	return readl_relaxed(pll->base + offset);
> +}
> +
> +/*
> + * The output frequency formula for the pll is:
> + * clkout = fbdiv / refdiv * parent / vcodiv

That comment is enough, remove the one below.

> + * Note that for BG2, BG2CD and BG2Q, the parent clock is provided by the SM
> + * oscillator and is always 25MHz.
> + */
> +static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
> +					unsigned long parent_rate)
> +{
> +	struct berlin_pll *pll = to_berlin_pll(hw);
> +	struct berlin_pllmap *map = pll->map;
> +	u32 val, fbdiv, rfdiv, vcodivsel;
> +
> +	val = berlin_pll_read(pll, PLL_CTRL0);
> +	fbdiv = (val >> map->fbdiv_shift) & map->fbdiv_mask;
> +	rfdiv = (val >> map->rfdiv_shift) & map->rfdiv_mask;
> +	if (rfdiv == 0)
> +		rfdiv = 1;

if (rfdiv) {
	pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
	rfdiv = 1;
}

> +
> +	val = berlin_pll_read(pll, PLL_CTRL1);
> +	vcodivsel = (val >> map->divsel_shift) & map->divsel_mask;

As map->vcodiv can contain zeros, we should rather do

vcodiv = map->vcodiv[vcodivsel];
if (vcodiv) {
	pr_warn("%s has zero vcodiv\n", __clk_get_name(hw->clk));
	vcodiv = 1;
}

> +	parent_rate *= fbdiv * map->mult;
> +	parent_rate /= rfdiv;
> +	return parent_rate / map->vcodiv[vcodivsel];

With parent_rate = 25M and max(fbdiv) == 511 we can possibly
exceed 32b range. So, we should rather switch to u64 here:

#include <asm/div64.h>

u64 rate = parent_rate;

...

rate *= fbdiv * map->mult;
do_div(rate, vcodiv * rfdiv);
return (unsigned long)rate;

Besides the comments, this really looks good to me. We may have
to rebase some of it onto v3.15-rc1 as soon as it drops, but I
can take care of it.

Sebastian

> +}
> +
> +static const struct clk_ops berlin_pll_ops = {
> +	.recalc_rate	= berlin_pll_recalc_rate,
> +};
> +
> +void __init berlin_pll_setup(struct device_node *np,
> +			struct berlin_pllmap *map)
> +{
> +	struct clk_init_data init;
> +	struct berlin_pll *pll;
> +	const char *parent_name;
> +	struct clk *clk;
> +	int ret;
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (WARN_ON(!pll))
> +		return;
> +
> +	pll->base = of_iomap(np, 0);
> +	if (WARN_ON(!pll->base))
> +		return;
> +
> +	pll->map = map;
> +
> +	init.name = np->name;
> +	init.ops = &berlin_pll_ops;
> +	parent_name = of_clk_get_parent_name(np, 0);
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +
> +	pll->hw.init = &init;
> +
> +	clk = clk_register(NULL, &pll->hw);
> +	if (WARN_ON(IS_ERR(clk)))
> +		return;
> +
> +	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +	if (WARN_ON(ret))
> +		return;
> +}
> +
>

Re: [PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.
>
> Cc: devicetree@vger.kernel.org

You forgot to add Mark Rutland's Reviewed-by. He didn't mentioned it
explicitly but his "Otherwise this looks fine to me" on v1, is as good
as a Reviewed-by. But, no need to resend, I'll fix it up.

Also, everything above the '---' will be part of your commit log. While
the Signed-off-by and Reviewed-by should be in there, Cc's really don't
need to.

You can add another '---' to separate commit message and some stuff
you want to have early in you email with:

Blablabla commit message.

Signed-off-by: ...
Reviewed-by: ...
---
Changelog:
- blabla

Cc: cc-me-recipient
...
---
    .../devicetree/bindings/clock/berlin-clock.txt     | 29 
++++++++++++++++++++++
    1 file changed, 29 insertions(+)
    create mode 100644 
Documentation/devicetree/bindings/clock/berlin-clock.txt

  diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt 
b/Documentation/devicetree/bindings/clock/berlin-clock.txt
...

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> new file mode 100644
> index 000000000000..49b7860bffb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> @@ -0,0 +1,29 @@
> +Device Tree Clock bindings for Marvell Berlin clocks
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible: shall be one of the following:
> +	"marvell,berlin2-pll",
> +	"marvell,berlin2q-pll":
> +		CPU PLL and System PLL
> +- reg: Address and length of the clock register set.
> +- #clock-cells: from common clock binding; shall be set to 0.
> +- clocks: from common clock binding
> +
> +smclk: sysmgr-clock {
> +	compatible = "fixed-clock";
> +	#clock-cells = <0>;
> +	clock-frequency = <25000000>;
> +};
> +
> +cpupll: cpupll@ea003c {
> +	compatible = "marvell,berlin2-pll";
> +	clocks = <&smclk>;
> +	#clock-cells = <0>;
> +	reg = <0xea003c 0x8>;
> +};
> +
> +
>

[PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.
>
> Cc: devicetree at vger.kernel.org

You forgot to add Mark Rutland's Reviewed-by. He didn't mentioned it
explicitly but his "Otherwise this looks fine to me" on v1, is as good
as a Reviewed-by. But, no need to resend, I'll fix it up.

Also, everything above the '---' will be part of your commit log. While
the Signed-off-by and Reviewed-by should be in there, Cc's really don't
need to.

You can add another '---' to separate commit message and some stuff
you want to have early in you email with:

Blablabla commit message.

Signed-off-by: ...
Reviewed-by: ...
---
Changelog:
- blabla

Cc: cc-me-recipient
...
---
    .../devicetree/bindings/clock/berlin-clock.txt     | 29 
++++++++++++++++++++++
    1 file changed, 29 insertions(+)
    create mode 100644 
Documentation/devicetree/bindings/clock/berlin-clock.txt

  diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt 
b/Documentation/devicetree/bindings/clock/berlin-clock.txt
...

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> new file mode 100644
> index 000000000000..49b7860bffb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> @@ -0,0 +1,29 @@
> +Device Tree Clock bindings for Marvell Berlin clocks
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible: shall be one of the following:
> +	"marvell,berlin2-pll",
> +	"marvell,berlin2q-pll":
> +		CPU PLL and System PLL
> +- reg: Address and length of the clock register set.
> +- #clock-cells: from common clock binding; shall be set to 0.
> +- clocks: from common clock binding
> +
> +smclk: sysmgr-clock {
> +	compatible = "fixed-clock";
> +	#clock-cells = <0>;
> +	clock-frequency = <25000000>;
> +};
> +
> +cpupll: cpupll at ea003c {
> +	compatible = "marvell,berlin2-pll";
> +	clocks = <&smclk>;
> +	#clock-cells = <0>;
> +	reg = <0xea003c 0x8>;
> +};
> +
> +
>

Re: [PATCH v2 3/5] ARM: berlin/dt: add cpupll and syspll support to BG2Q

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2Q has two supported PLLs: CPU PLL and System PLL, add those to the
> SoC device tree.
>
> Note that support for the AVPLL is not yet available.

Above should not be part of the commit message, no need to resend.
I can fix it up.

Sebastian

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2q.dtsi | 22 +++++++++++++++-------
>   1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 07452a7483fa..5925e6a16749 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -59,16 +59,10 @@
>   		clock-frequency = <100000000>;
>   	};
>
> -	cpuclk: cpu-clock {
> -		compatible = "fixed-clock";
> -		#clock-cells = <0>;
> -		clock-frequency = <1200000000>;
> -	};
> -
>   	twdclk: twdclk {
>   		compatible = "fixed-factor-clock";
>   		#clock-cells = <0>;
> -		clocks = <&cpuclk>;
> +		clocks = <&cpupll>;
>   		clock-mult = <1>;
>   		clock-div = <3>;
>   	};
> @@ -101,6 +95,20 @@
>   			#interrupt-cells = <3>;
>   		};
>
> +		cpupll: cpupll@dd0170 {
> +			compatible = "marvell,berlin2q-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xdd0170 0x8>;
> +		};
> +
> +		syspll: syspll@ea0030 {
> +			compatible = "marvell,berlin2q-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea0030 0x8>;
> +		};
> +
>   		apb@e80000 {
>   			compatible = "simple-bus";
>   			#address-cells = <1>;
>

[PATCH v2 3/5] ARM: berlin/dt: add cpupll and syspll support to BG2Q

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2Q has two supported PLLs: CPU PLL and System PLL, add those to the
> SoC device tree.
>
> Note that support for the AVPLL is not yet available.

Above should not be part of the commit message, no need to resend.
I can fix it up.

Sebastian

> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2q.dtsi | 22 +++++++++++++++-------
>   1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 07452a7483fa..5925e6a16749 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -59,16 +59,10 @@
>   		clock-frequency = <100000000>;
>   	};
>
> -	cpuclk: cpu-clock {
> -		compatible = "fixed-clock";
> -		#clock-cells = <0>;
> -		clock-frequency = <1200000000>;
> -	};
> -
>   	twdclk: twdclk {
>   		compatible = "fixed-factor-clock";
>   		#clock-cells = <0>;
> -		clocks = <&cpuclk>;
> +		clocks = <&cpupll>;
>   		clock-mult = <1>;
>   		clock-div = <3>;
>   	};
> @@ -101,6 +95,20 @@
>   			#interrupt-cells = <3>;
>   		};
>
> +		cpupll: cpupll at dd0170 {
> +			compatible = "marvell,berlin2q-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xdd0170 0x8>;
> +		};
> +
> +		syspll: syspll at ea0030 {
> +			compatible = "marvell,berlin2q-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea0030 0x8>;
> +		};
> +
>   		apb at e80000 {
>   			compatible = "simple-bus";
>   			#address-cells = <1>;
>

Re: [PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
> the SoC device tree.
>
> This also moves the remaining clocks from the clocks container node to the root.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
>   1 file changed, 31 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> index 094968c27533..bd4e9dd4867e 100644
> --- a/arch/arm/boot/dts/berlin2cd.dtsi
> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
> @@ -30,24 +30,24 @@
[...]
> @@ -76,7 +76,21 @@
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
>   			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&sysclk>;
> +			clocks = <&twdclk>;
> +		};
> +
> +		syspll: syspll@ea0014 {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xf7ea0014 8>;

nit: I prefer hex numbers all over for reg properties. berlin2q already
has them, and I'll fixup this and the one below myself.

> +		};
> +
> +		cpupll: cpupll@ea003c {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xf7ea003c 8>;

ditto.

Sebastian

>   		};
>
>   		apb@e80000 {
>

[PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
> the SoC device tree.
>
> This also moves the remaining clocks from the clocks container node to the root.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
>   1 file changed, 31 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> index 094968c27533..bd4e9dd4867e 100644
> --- a/arch/arm/boot/dts/berlin2cd.dtsi
> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
> @@ -30,24 +30,24 @@
[...]
> @@ -76,7 +76,21 @@
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
>   			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&sysclk>;
> +			clocks = <&twdclk>;
> +		};
> +
> +		syspll: syspll at ea0014 {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xf7ea0014 8>;

nit: I prefer hex numbers all over for reg properties. berlin2q already
has them, and I'll fixup this and the one below myself.

> +		};
> +
> +		cpupll: cpupll at ea003c {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xf7ea003c 8>;

ditto.

Sebastian

>   		};
>
>   		apb at e80000 {
>

Re: [PATCH v2 5/5] ARM: berlin/dt: add cpupll and syspll support to BG2

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2 has two supported PLLs: CPU PLL and System PLL, add those to the
> SoC device tree.
>
> This also moves the remaining clocks from the clocks container node to the root.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2.dtsi | 48 +++++++++++++++++++++++++++---------------
>   1 file changed, 31 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 56a1af2f1052..6c080eb6242a 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
[...]
> @@ -83,7 +83,21 @@
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
>   			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&sysclk>;
> +			clocks = <&twdclk>;
> +		};
> +
> +		syspll: syspll@ea0014 {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea0014 8>;
> +		};
> +
> +		cpupll: cpupll@ea003c {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea003c 8>;

Same comment about hex numbers and I'll also fix it up.

Sebastian

>   		};
>
>   		apb@e80000 {
>

[PATCH v2 5/5] ARM: berlin/dt: add cpupll and syspll support to BG2

[Sebastian Hesselbarth]

On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> The Berlin BG2 has two supported PLLs: CPU PLL and System PLL, add those to the
> SoC device tree.
>
> This also moves the remaining clocks from the clocks container node to the root.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>   arch/arm/boot/dts/berlin2.dtsi | 48 +++++++++++++++++++++++++++---------------
>   1 file changed, 31 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 56a1af2f1052..6c080eb6242a 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
[...]
> @@ -83,7 +83,21 @@
>   			compatible = "arm,cortex-a9-twd-timer";
>   			reg = <0xad0600 0x20>;
>   			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&sysclk>;
> +			clocks = <&twdclk>;
> +		};
> +
> +		syspll: syspll at ea0014 {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea0014 8>;
> +		};
> +
> +		cpupll: cpupll at ea003c {
> +			compatible = "marvell,berlin2-pll";
> +			clocks = <&smclk>;
> +			#clock-cells = <0>;
> +			reg = <0xea003c 8>;

Same comment about hex numbers and I'll also fix it up.

Sebastian

>   		};
>
>   		apb at e80000 {
>

Re: [PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Alexandre Belloni]

On 21/03/2014 at 22:35:26 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
> >the SoC device tree.
> >
> >This also moves the remaining clocks from the clocks container node to the root.
> >
> >Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >---
> >  arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
> >  1 file changed, 31 insertions(+), 17 deletions(-)
> >
> >diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> >index 094968c27533..bd4e9dd4867e 100644
> >--- a/arch/arm/boot/dts/berlin2cd.dtsi
> >+++ b/arch/arm/boot/dts/berlin2cd.dtsi
> >@@ -30,24 +30,24 @@
> [...]
> >@@ -76,7 +76,21 @@
> >  			compatible = "arm,cortex-a9-twd-timer";
> >  			reg = <0xad0600 0x20>;
> >  			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> >-			clocks = <&sysclk>;
> >+			clocks = <&twdclk>;
> >+		};
> >+
> >+		syspll: syspll@ea0014 {
> >+			compatible = "marvell,berlin2-pll";
> >+			clocks = <&smclk>;
> >+			#clock-cells = <0>;
> >+			reg = <0xf7ea0014 8>;
> 
> nit: I prefer hex numbers all over for reg properties. berlin2q already
> has them, and I'll fixup this and the one below myself.
> 

Indeed, I did fix that for bg2q and documentation and forgot bg2 and
bg2cd.

> >+		};
> >+
> >+		cpupll: cpupll@ea003c {
> >+			compatible = "marvell,berlin2-pll";
> >+			clocks = <&smclk>;
> >+			#clock-cells = <0>;
> >+			reg = <0xf7ea003c 8>;
> 
> ditto.
> 
> Sebastian
> 
> >  		};
> >
> >  		apb@e80000 {
> >
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 4/5] ARM: berlin/dt: add cpupll and syspll support to BG2CD

[Alexandre Belloni]

On 21/03/2014 at 22:35:26 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
> >the SoC device tree.
> >
> >This also moves the remaining clocks from the clocks container node to the root.
> >
> >Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >---
> >  arch/arm/boot/dts/berlin2cd.dtsi | 48 ++++++++++++++++++++++++++--------------
> >  1 file changed, 31 insertions(+), 17 deletions(-)
> >
> >diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
> >index 094968c27533..bd4e9dd4867e 100644
> >--- a/arch/arm/boot/dts/berlin2cd.dtsi
> >+++ b/arch/arm/boot/dts/berlin2cd.dtsi
> >@@ -30,24 +30,24 @@
> [...]
> >@@ -76,7 +76,21 @@
> >  			compatible = "arm,cortex-a9-twd-timer";
> >  			reg = <0xad0600 0x20>;
> >  			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> >-			clocks = <&sysclk>;
> >+			clocks = <&twdclk>;
> >+		};
> >+
> >+		syspll: syspll at ea0014 {
> >+			compatible = "marvell,berlin2-pll";
> >+			clocks = <&smclk>;
> >+			#clock-cells = <0>;
> >+			reg = <0xf7ea0014 8>;
> 
> nit: I prefer hex numbers all over for reg properties. berlin2q already
> has them, and I'll fixup this and the one below myself.
> 

Indeed, I did fix that for bg2q and documentation and forgot bg2 and
bg2cd.

> >+		};
> >+
> >+		cpupll: cpupll at ea003c {
> >+			compatible = "marvell,berlin2-pll";
> >+			clocks = <&smclk>;
> >+			#clock-cells = <0>;
> >+			reg = <0xf7ea003c 8>;
> 
> ditto.
> 
> Sebastian
> 
> >  		};
> >
> >  		apb at e80000 {
> >
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Alexandre Belloni]

On 21/03/2014 at 22:31:09 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.
> >
> >Cc: devicetree@vger.kernel.org
> 
> You forgot to add Mark Rutland's Reviewed-by. He didn't mentioned it
> explicitly but his "Otherwise this looks fine to me" on v1, is as good
> as a Reviewed-by. But, no need to resend, I'll fix it up.
> 

Ok, I would have preferred an explicit one ;)

> Also, everything above the '---' will be part of your commit log. While
> the Signed-off-by and Reviewed-by should be in there, Cc's really don't
> need to.
> 

Ok, it seemed common practice to put it in the commit log:

$ git log | grep "    Cc:" | wc -l
157126

But I'll do as you suggest from now. Actually, I didn't know you could
do like that.

> You can add another '---' to separate commit message and some stuff
> you want to have early in you email with:
> 
> Blablabla commit message.
> 
> Signed-off-by: ...
> Reviewed-by: ...
> ---
> Changelog:
> - blabla
> 
> Cc: cc-me-recipient
> ...
> ---
>    .../devicetree/bindings/clock/berlin-clock.txt     | 29
> ++++++++++++++++++++++
>    1 file changed, 29 insertions(+)
>    create mode 100644
> Documentation/devicetree/bindings/clock/berlin-clock.txt
> 
>  diff --git
> a/Documentation/devicetree/bindings/clock/berlin-clock.txt
> b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> ...
> 
> >Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >---
> >  .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
> >
> >diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> >new file mode 100644
> >index 000000000000..49b7860bffb8
> >--- /dev/null
> >+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> >@@ -0,0 +1,29 @@
> >+Device Tree Clock bindings for Marvell Berlin clocks
> >+
> >+This binding uses the common clock binding[1].
> >+
> >+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >+
> >+Required properties:
> >+- compatible: shall be one of the following:
> >+	"marvell,berlin2-pll",
> >+	"marvell,berlin2q-pll":
> >+		CPU PLL and System PLL
> >+- reg: Address and length of the clock register set.
> >+- #clock-cells: from common clock binding; shall be set to 0.
> >+- clocks: from common clock binding
> >+
> >+smclk: sysmgr-clock {
> >+	compatible = "fixed-clock";
> >+	#clock-cells = <0>;
> >+	clock-frequency = <25000000>;
> >+};
> >+
> >+cpupll: cpupll@ea003c {
> >+	compatible = "marvell,berlin2-pll";
> >+	clocks = <&smclk>;
> >+	#clock-cells = <0>;
> >+	reg = <0xea003c 0x8>;
> >+};
> >+
> >+
> >
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 2/5] clk: berlin: add berlin clocks DT bindings documentation

[Alexandre Belloni]

On 21/03/2014 at 22:31:09 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.
> >
> >Cc: devicetree at vger.kernel.org
> 
> You forgot to add Mark Rutland's Reviewed-by. He didn't mentioned it
> explicitly but his "Otherwise this looks fine to me" on v1, is as good
> as a Reviewed-by. But, no need to resend, I'll fix it up.
> 

Ok, I would have preferred an explicit one ;)

> Also, everything above the '---' will be part of your commit log. While
> the Signed-off-by and Reviewed-by should be in there, Cc's really don't
> need to.
> 

Ok, it seemed common practice to put it in the commit log:

$ git log | grep "    Cc:" | wc -l
157126

But I'll do as you suggest from now. Actually, I didn't know you could
do like that.

> You can add another '---' to separate commit message and some stuff
> you want to have early in you email with:
> 
> Blablabla commit message.
> 
> Signed-off-by: ...
> Reviewed-by: ...
> ---
> Changelog:
> - blabla
> 
> Cc: cc-me-recipient
> ...
> ---
>    .../devicetree/bindings/clock/berlin-clock.txt     | 29
> ++++++++++++++++++++++
>    1 file changed, 29 insertions(+)
>    create mode 100644
> Documentation/devicetree/bindings/clock/berlin-clock.txt
> 
>  diff --git
> a/Documentation/devicetree/bindings/clock/berlin-clock.txt
> b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> ...
> 
> >Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >---
> >  .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/berlin-clock.txt
> >
> >diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> >new file mode 100644
> >index 000000000000..49b7860bffb8
> >--- /dev/null
> >+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> >@@ -0,0 +1,29 @@
> >+Device Tree Clock bindings for Marvell Berlin clocks
> >+
> >+This binding uses the common clock binding[1].
> >+
> >+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >+
> >+Required properties:
> >+- compatible: shall be one of the following:
> >+	"marvell,berlin2-pll",
> >+	"marvell,berlin2q-pll":
> >+		CPU PLL and System PLL
> >+- reg: Address and length of the clock register set.
> >+- #clock-cells: from common clock binding; shall be set to 0.
> >+- clocks: from common clock binding
> >+
> >+smclk: sysmgr-clock {
> >+	compatible = "fixed-clock";
> >+	#clock-cells = <0>;
> >+	clock-frequency = <25000000>;
> >+};
> >+
> >+cpupll: cpupll at ea003c {
> >+	compatible = "marvell,berlin2-pll";
> >+	clocks = <&smclk>;
> >+	#clock-cells = <0>;
> >+	reg = <0xea003c 0x8>;
> >+};
> >+
> >+
> >
> 

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 1/5] clk: berlin: add support for berlin plls

[Alexandre Belloni]

On 21/03/2014 at 22:22:33 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >This drivers allows to provide DT clocks for the cpu and system PLLs found on
> >Marvell Berlin SoCs.
> 
> Alexandre,
> 
> as mentioned on IRC, I now had a closer look on it. Some minor
> remarks below. Sorry, I didn't mention them earlier.
> 

To clarify things, I'll just resend patch 1 and you are ready to take
2-5, fixing up the remaining comments as soon as Mike takes it ?


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 1/5] clk: berlin: add support for berlin plls

[Alexandre Belloni]

On 21/03/2014 at 22:22:33 +0100, Sebastian Hesselbarth wrote :
> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
> >This drivers allows to provide DT clocks for the cpu and system PLLs found on
> >Marvell Berlin SoCs.
> 
> Alexandre,
> 
> as mentioned on IRC, I now had a closer look on it. Some minor
> remarks below. Sorry, I didn't mention them earlier.
> 

To clarify things, I'll just resend patch 1 and you are ready to take
2-5, fixing up the remaining comments as soon as Mike takes it ?


-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 1/5] clk: berlin: add support for berlin plls

[Sebastian Hesselbarth]

On 03/21/2014 11:22 PM, Alexandre Belloni wrote:
> On 21/03/2014 at 22:22:33 +0100, Sebastian Hesselbarth wrote :
>> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
>>> This drivers allows to provide DT clocks for the cpu and system PLLs found on
>>> Marvell Berlin SoCs.
>>
>> Alexandre,
>>
>> as mentioned on IRC, I now had a closer look on it. Some minor
>> remarks below. Sorry, I didn't mention them earlier.
>
> To clarify things, I'll just resend patch 1 and you are ready to take
> 2-5, fixing up the remaining comments as soon as Mike takes it ?

Yes, no need to resend 2-5. Just keep on incrementing version on 1/5.
If you send a v3 for patch 1, I can also prepare a topic branch that
we refer to until Mike either takes the single patch or pulls the topic
branch.

I'll work it out with Mike, but for a single patch, I guess he'll
take it through his tree.

As we target this all for v3.16, I'll get back to this, as soon as I
have proper branches on v3.15-rc1 and possibly also managed it to have
a for-next branch that gets pulled into linux-next.

Sebastian

[PATCH v2 1/5] clk: berlin: add support for berlin plls

[Sebastian Hesselbarth]

On 03/21/2014 11:22 PM, Alexandre Belloni wrote:
> On 21/03/2014 at 22:22:33 +0100, Sebastian Hesselbarth wrote :
>> On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
>>> This drivers allows to provide DT clocks for the cpu and system PLLs found on
>>> Marvell Berlin SoCs.
>>
>> Alexandre,
>>
>> as mentioned on IRC, I now had a closer look on it. Some minor
>> remarks below. Sorry, I didn't mention them earlier.
>
> To clarify things, I'll just resend patch 1 and you are ready to take
> 2-5, fixing up the remaining comments as soon as Mike takes it ?

Yes, no need to resend 2-5. Just keep on incrementing version on 1/5.
If you send a v3 for patch 1, I can also prepare a topic branch that
we refer to until Mike either takes the single patch or pulls the topic
branch.

I'll work it out with Mike, but for a single patch, I guess he'll
take it through his tree.

As we target this all for v3.16, I'll get back to this, as soon as I
have proper branches on v3.15-rc1 and possibly also managed it to have
a for-next branch that gets pulled into linux-next.

Sebastian