* [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature
@ 2014-04-12 9:43 Akshay Saraswat
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
` (4 more replies)
0 siblings, 5 replies; 19+ messages in thread
From: Akshay Saraswat @ 2014-04-12 9:43 UTC (permalink / raw)
To: u-boot
From: Akshay Saraswat <akshay.s@samsung.com>
Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions
to S5P_GPIO.
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks
are divided into different parts where ever they
have holes in them.
- Function and table to support gpio command moved
to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to
get bank.
- Added #define HAVE_GENERIC_GPIO in config file
to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.
Rajeshwari Shinde (4):
S5P: Rename GPIO definitions
EXYNOS5: Add gpio pin numbering feature
EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
Config: Exynos5: Enable Generic GPIO and CMD configs
arch/arm/cpu/armv7/exynos/pinmux.c | 355 ++++++--------
arch/arm/include/asm/arch-exynos/cpu.h | 17 +-
arch/arm/include/asm/arch-exynos/gpio.h | 796 ++++++++++++++++++++++++++++++-
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +-
board/samsung/goni/goni.c | 4 +-
board/samsung/smdk5250/exynos5-dt.c | 20 +-
board/samsung/smdk5250/smdk5250.c | 19 +-
board/samsung/smdk5420/smdk5420.c | 15 +-
board/samsung/smdkc100/smdkc100.c | 2 +-
board/samsung/smdkv310/smdkv310.c | 10 +-
board/samsung/trats/trats.c | 6 +-
board/samsung/universal_c210/universal.c | 34 +-
drivers/gpio/s5p_gpio.c | 169 ++++++-
include/configs/exynos5-dt.h | 3 +
14 files changed, 1157 insertions(+), 319 deletions(-)
--
1.8.3.2
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
@ 2014-04-12 9:43 ` Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
` (2 more replies)
2014-04-12 9:43 ` [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions Akshay Saraswat
` (3 subsequent siblings)
4 siblings, 3 replies; 19+ messages in thread
From: Akshay Saraswat @ 2014-04-12 9:43 UTC (permalink / raw)
To: u-boot
From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/pinmux.c | 287 +++++-------
arch/arm/include/asm/arch-exynos/cpu.h | 17 +-
arch/arm/include/asm/arch-exynos/gpio.h | 742 +++++++++++++++++++++++++++++++-
board/samsung/smdk5250/exynos5-dt.c | 20 +-
board/samsung/smdk5250/smdk5250.c | 19 +-
board/samsung/smdk5420/smdk5420.c | 15 +-
drivers/gpio/s5p_gpio.c | 44 +-
7 files changed, 923 insertions(+), 221 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 9edb475..34c24cd 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -13,30 +13,23 @@
static void exynos5_uart_config(int peripheral)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
- bank = &gpio1->a0;
- start = 0;
+ start = EXYNOS5_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->d0;
- start = 0;
+ start = EXYNOS5_GPIO_D00;
count = 4;
break;
case PERIPH_ID_UART2:
- bank = &gpio1->a1;
- start = 0;
+ start = EXYNOS5_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
- bank = &gpio1->a1;
- start = 4;
+ start = EXYNOS5_GPIO_A14;
count = 2;
break;
default:
@@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
return;
}
for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, GPIO_PULL_NONE);
+ gpio_cfg_pin(i, GPIO_FUNC(0x2));
}
}
static void exynos5420_uart_config(int peripheral)
{
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
- bank = &gpio1->a0;
- start = 0;
+ start = EXYNOS5420_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ start = EXYNOS5420_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
- bank = &gpio1->a1;
- start = 0;
+ start = EXYNOS5420_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
- bank = &gpio1->a1;
- start = 4;
+ start = EXYNOS5420_GPIO_A14;
count = 2;
break;
default:
@@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
}
for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, GPIO_PULL_NONE);
+ gpio_cfg_pin(i, GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct s5p_gpio_bank *bank, *bank_ext;
- int i, start = 0, gpio_func = 0;
+ int i, start, start_ext, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
- bank = &gpio1->c0;
- bank_ext = &gpio1->c1;
- start = 0;
+ start = EXYNOS5_GPIO_C00;
+ start_ext = EXYNOS5_GPIO_C10;
gpio_func = GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c2;
- bank_ext = NULL;
+ start = EXYNOS5_GPIO_C20;
+ start_ext = 0;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c3;
- bank_ext = &gpio1->c4;
- start = 3;
+ start = EXYNOS5_GPIO_C30;
+ start_ext = EXYNOS5_GPIO_C43;
gpio_func = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
- bank = &gpio1->c4;
- bank_ext = NULL;
+ start = EXYNOS5_GPIO_C40;
+ start_ext = 0;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = start; i <= (start + 3); i++) {
- s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ for (i = start_ext; i <= (start_ext + 3); i++) {
+ gpio_cfg_pin(i, gpio_func);
+ gpio_set_pull(i, GPIO_PULL_UP);
+ gpio_set_drv(i, GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, GPIO_PULL_NONE);
+ gpio_set_drv(start + i, GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, GPIO_PULL_UP);
+ gpio_set_drv(start + i, GPIO_DRV_4X);
}
return 0;
@@ -148,25 +129,22 @@ static int exynos5_mmc_config(int peripheral, int flags)
static int exynos5420_mmc_config(int peripheral, int flags)
{
- struct exynos5420_gpio_part3 *gpio3 =
- (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
- struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
- int i, start;
+ int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
- bank = &gpio3->c0;
- bank_ext = &gpio3->c3;
+ start = EXYNOS5420_GPIO_C00;
+ start_ext = EXYNOS5420_GPIO_C30;
start = 0;
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio3->c1;
- bank_ext = &gpio3->d1;
+ start = EXYNOS5420_GPIO_C10;
+ start_ext = EXYNOS5420_GPIO_D14;
start = 4;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio3->c2;
- bank_ext = NULL;
+ start = EXYNOS5420_GPIO_C20;
+ start_ext = 0;
start = 0;
break;
default:
@@ -175,7 +153,7 @@ static int exynos5420_mmc_config(int peripheral, int flags)
return -1;
}
- if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
@@ -183,9 +161,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ gpio_cfg_pin(i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, GPIO_PULL_UP);
+ gpio_set_drv(i, GPIO_DRV_4X);
}
}
@@ -197,19 +175,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)
* this same assumption.
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
- s5p_gpio_set_value(bank, i, 1);
- s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+ gpio_set_value(i, 1);
+ gpio_cfg_pin(i, GPIO_OUTPUT);
} else {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, GPIO_FUNC(0x2));
}
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_set_pull(i, GPIO_PULL_NONE);
+ gpio_set_drv(i, GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ gpio_cfg_pin(i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, GPIO_PULL_UP);
+ gpio_set_drv(i, GPIO_DRV_4X);
}
return 0;
@@ -217,8 +195,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
static void exynos5_sromc_config(int flags)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
@@ -236,13 +212,13 @@ static void exynos5_sromc_config(int flags)
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
- s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
- GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+ GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
for (i = 0; i < 4; i++)
- s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
@@ -277,108 +253,101 @@ static void exynos5_sromc_config(int flags)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
- s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
- s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
- s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
}
}
static void exynos5_i2c_config(int peripheral, int flags)
{
-
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
break;
}
}
static void exynos5420_i2c_config(int peripheral)
{
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B30, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B31, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B32, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B33, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A06, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A07, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A12, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A13, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A20, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A21, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A22, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A23, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B13, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B14, GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B22, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B23, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
- s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B34, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B35, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
- s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B36, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B37, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
- s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B40, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B41, GPIO_FUNC(0x2));
break;
}
}
@@ -386,19 +355,15 @@ static void exynos5420_i2c_config(int peripheral)
static void exynos5_i2s_config(int peripheral)
{
int i;
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
- struct exynos5_gpio_part4 *gpio4 =
- (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_I2S0:
for (i = 0; i < 5; i++)
- s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, GPIO_FUNC(0x02));
break;
case PERIPH_ID_I2S1:
for (i = 0; i < 5; i++)
- s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
break;
}
}
@@ -406,75 +371,57 @@ static void exynos5_i2s_config(int peripheral)
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;
- struct s5p_gpio_bank *bank = NULL;
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- struct exynos5_gpio_part2 *gpio2 =
- (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
switch (peripheral) {
case PERIPH_ID_SPI0:
- bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
- pin = 0;
+ pin = EXYNOS5_GPIO_A20;
break;
case PERIPH_ID_SPI1:
- bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
- pin = 4;
+ pin = EXYNOS5_GPIO_A24;
break;
case PERIPH_ID_SPI2:
- bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
- pin = 1;
+ pin = EXYNOS5_GPIO_B11;
break;
case PERIPH_ID_SPI3:
- bank = &gpio2->f1;
cfg = GPIO_FUNC(0x2);
- pin = 0;
+ pin = EXYNOS5_GPIO_F10;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
}
break;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
- s5p_gpio_cfg_pin(bank, i, cfg);
+ gpio_cfg_pin(i, cfg);
}
}
void exynos5420_spi_config(int peripheral)
{
int cfg, pin, i;
- struct s5p_gpio_bank *bank = NULL;
- struct exynos5420_gpio_part1 *gpio1 =
- (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
- struct exynos5420_gpio_part4 *gpio4 =
- (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_SPI0:
- bank = &gpio1->a2;
+ pin = EXYNOS5420_GPIO_A20;
cfg = GPIO_FUNC(0x2);
- pin = 0;
break;
case PERIPH_ID_SPI1:
- bank = &gpio1->a2;
+ pin = EXYNOS5420_GPIO_A24;
cfg = GPIO_FUNC(0x2);
- pin = 4;
break;
case PERIPH_ID_SPI2:
- bank = &gpio1->b1;
+ pin = EXYNOS5420_GPIO_B11;
cfg = GPIO_FUNC(0x5);
- pin = 1;
break;
case PERIPH_ID_SPI3:
- bank = &gpio4->f1;
+ pin = EXYNOS5420_GPIO_F10;
cfg = GPIO_FUNC(0x2);
- pin = 0;
break;
case PERIPH_ID_SPI4:
cfg = 0;
@@ -489,11 +436,13 @@ void exynos5420_spi_config(int peripheral)
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
- s5p_gpio_cfg_pin(bank, i, cfg);
+ gpio_cfg_pin(i, cfg);
} else {
for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+ GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+ GPIO_FUNC(0x4));
}
}
}
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index fdf73b5..ba71714 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -98,7 +98,7 @@
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
-#define EXYNOS5_GPIO_PART4_BASE 0x03860000
+#define EXYNOS5_GPIO_PART8_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
#define EXYNOS5_POWER_BASE 0x10040000
@@ -108,9 +108,13 @@
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
+#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
#define EXYNOS5_USB3PHY_BASE 0x12100000
@@ -125,7 +129,7 @@
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5_GPIO_PART4_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
@@ -135,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
@@ -158,8 +162,9 @@
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index d6868fa..211383d 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -141,14 +141,16 @@ struct exynos5420_gpio_part1 {
struct exynos5420_gpio_part2 {
struct s5p_gpio_bank y7; /* 0x1340_0000 */
- struct s5p_gpio_bank res[0x5f]; /* */
+};
+
+struct exynos5420_gpio_part3 {
struct s5p_gpio_bank x0; /* 0x1340_0C00 */
struct s5p_gpio_bank x1; /* 0x1340_0C20 */
struct s5p_gpio_bank x2; /* 0x1340_0C40 */
struct s5p_gpio_bank x3; /* 0x1340_0C60 */
};
-struct exynos5420_gpio_part3 {
+struct exynos5420_gpio_part4 {
struct s5p_gpio_bank c0;
struct s5p_gpio_bank c1;
struct s5p_gpio_bank c2;
@@ -164,7 +166,7 @@ struct exynos5420_gpio_part3 {
struct s5p_gpio_bank y6;
};
-struct exynos5420_gpio_part4 {
+struct exynos5420_gpio_part5 {
struct s5p_gpio_bank e0; /* 0x1400_0000 */
struct s5p_gpio_bank e1; /* 0x1400_0020 */
struct s5p_gpio_bank f0; /* 0x1400_0040 */
@@ -175,7 +177,7 @@ struct exynos5420_gpio_part4 {
struct s5p_gpio_bank j4; /* 0x1400_00E0 */
};
-struct exynos5420_gpio_part5 {
+struct exynos5420_gpio_part6 {
struct s5p_gpio_bank z0; /* 0x0386_0000 */
};
@@ -200,16 +202,20 @@ struct exynos5_gpio_part1 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x3];
+};
+
+struct exynos5_gpio_part2 {
struct s5p_gpio_bank c4;
- struct s5p_gpio_bank res2[0x48];
+};
+
+struct exynos5_gpio_part3 {
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
struct s5p_gpio_bank x3;
};
-struct exynos5_gpio_part2 {
+struct exynos5_gpio_part4 {
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
@@ -221,20 +227,25 @@ struct exynos5_gpio_part2 {
struct s5p_gpio_bank h1;
};
-struct exynos5_gpio_part3 {
+struct exynos5_gpio_part5 {
struct s5p_gpio_bank v0;
struct s5p_gpio_bank v1;
- struct s5p_gpio_bank res1[0x1];
+};
+
+struct exynos5_gpio_part6 {
struct s5p_gpio_bank v2;
struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res2[0x1];
+};
+
+struct exynos5_gpio_part7 {
struct s5p_gpio_bank v4;
};
-struct exynos5_gpio_part4 {
+struct exynos5_gpio_part8 {
struct s5p_gpio_bank z;
};
+
/* functions */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@@ -323,6 +334,715 @@ static inline unsigned int s5p_gpio_base(int gpio)
return 0;
}
}
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos5_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5_GPIO_A00, /* 0 */
+ EXYNOS5_GPIO_A01,
+ EXYNOS5_GPIO_A02,
+ EXYNOS5_GPIO_A03,
+ EXYNOS5_GPIO_A04,
+ EXYNOS5_GPIO_A05,
+ EXYNOS5_GPIO_A06,
+ EXYNOS5_GPIO_A07,
+ EXYNOS5_GPIO_A10, /* 8 */
+ EXYNOS5_GPIO_A11,
+ EXYNOS5_GPIO_A12,
+ EXYNOS5_GPIO_A13,
+ EXYNOS5_GPIO_A14,
+ EXYNOS5_GPIO_A15,
+ EXYNOS5_GPIO_A16,
+ EXYNOS5_GPIO_A17,
+ EXYNOS5_GPIO_A20, /* 16 0x10 */
+ EXYNOS5_GPIO_A21,
+ EXYNOS5_GPIO_A22,
+ EXYNOS5_GPIO_A23,
+ EXYNOS5_GPIO_A24,
+ EXYNOS5_GPIO_A25,
+ EXYNOS5_GPIO_A26,
+ EXYNOS5_GPIO_A27,
+ EXYNOS5_GPIO_B00, /* 24 0x18 */
+ EXYNOS5_GPIO_B01,
+ EXYNOS5_GPIO_B02,
+ EXYNOS5_GPIO_B03,
+ EXYNOS5_GPIO_B04,
+ EXYNOS5_GPIO_B05,
+ EXYNOS5_GPIO_B06,
+ EXYNOS5_GPIO_B07,
+ EXYNOS5_GPIO_B10, /* 32 0x20 */
+ EXYNOS5_GPIO_B11,
+ EXYNOS5_GPIO_B12,
+ EXYNOS5_GPIO_B13,
+ EXYNOS5_GPIO_B14,
+ EXYNOS5_GPIO_B15,
+ EXYNOS5_GPIO_B16,
+ EXYNOS5_GPIO_B17,
+ EXYNOS5_GPIO_B20, /* 40 0x28 */
+ EXYNOS5_GPIO_B21,
+ EXYNOS5_GPIO_B22,
+ EXYNOS5_GPIO_B23,
+ EXYNOS5_GPIO_B24,
+ EXYNOS5_GPIO_B25,
+ EXYNOS5_GPIO_B26,
+ EXYNOS5_GPIO_B27,
+ EXYNOS5_GPIO_B30, /* 48 0x39 */
+ EXYNOS5_GPIO_B31,
+ EXYNOS5_GPIO_B32,
+ EXYNOS5_GPIO_B33,
+ EXYNOS5_GPIO_B34,
+ EXYNOS5_GPIO_B35,
+ EXYNOS5_GPIO_B36,
+ EXYNOS5_GPIO_B37,
+ EXYNOS5_GPIO_C00, /* 56 0x38 */
+ EXYNOS5_GPIO_C01,
+ EXYNOS5_GPIO_C02,
+ EXYNOS5_GPIO_C03,
+ EXYNOS5_GPIO_C04,
+ EXYNOS5_GPIO_C05,
+ EXYNOS5_GPIO_C06,
+ EXYNOS5_GPIO_C07,
+ EXYNOS5_GPIO_C10, /* 64 0x40 */
+ EXYNOS5_GPIO_C11,
+ EXYNOS5_GPIO_C12,
+ EXYNOS5_GPIO_C13,
+ EXYNOS5_GPIO_C14,
+ EXYNOS5_GPIO_C15,
+ EXYNOS5_GPIO_C16,
+ EXYNOS5_GPIO_C17,
+ EXYNOS5_GPIO_C20, /* 72 0x48 */
+ EXYNOS5_GPIO_C21,
+ EXYNOS5_GPIO_C22,
+ EXYNOS5_GPIO_C23,
+ EXYNOS5_GPIO_C24,
+ EXYNOS5_GPIO_C25,
+ EXYNOS5_GPIO_C26,
+ EXYNOS5_GPIO_C27,
+ EXYNOS5_GPIO_C30, /* 80 0x50 */
+ EXYNOS5_GPIO_C31,
+ EXYNOS5_GPIO_C32,
+ EXYNOS5_GPIO_C33,
+ EXYNOS5_GPIO_C34,
+ EXYNOS5_GPIO_C35,
+ EXYNOS5_GPIO_C36,
+ EXYNOS5_GPIO_C37,
+ EXYNOS5_GPIO_D00, /* 88 0x58 */
+ EXYNOS5_GPIO_D01,
+ EXYNOS5_GPIO_D02,
+ EXYNOS5_GPIO_D03,
+ EXYNOS5_GPIO_D04,
+ EXYNOS5_GPIO_D05,
+ EXYNOS5_GPIO_D06,
+ EXYNOS5_GPIO_D07,
+ EXYNOS5_GPIO_D10, /* 96 0x60 */
+ EXYNOS5_GPIO_D11,
+ EXYNOS5_GPIO_D12,
+ EXYNOS5_GPIO_D13,
+ EXYNOS5_GPIO_D14,
+ EXYNOS5_GPIO_D15,
+ EXYNOS5_GPIO_D16,
+ EXYNOS5_GPIO_D17,
+ EXYNOS5_GPIO_Y00, /* 104 0x68 */
+ EXYNOS5_GPIO_Y01,
+ EXYNOS5_GPIO_Y02,
+ EXYNOS5_GPIO_Y03,
+ EXYNOS5_GPIO_Y04,
+ EXYNOS5_GPIO_Y05,
+ EXYNOS5_GPIO_Y06,
+ EXYNOS5_GPIO_Y07,
+ EXYNOS5_GPIO_Y10, /* 112 0x70 */
+ EXYNOS5_GPIO_Y11,
+ EXYNOS5_GPIO_Y12,
+ EXYNOS5_GPIO_Y13,
+ EXYNOS5_GPIO_Y14,
+ EXYNOS5_GPIO_Y15,
+ EXYNOS5_GPIO_Y16,
+ EXYNOS5_GPIO_Y17,
+ EXYNOS5_GPIO_Y20, /* 120 0x78 */
+ EXYNOS5_GPIO_Y21,
+ EXYNOS5_GPIO_Y22,
+ EXYNOS5_GPIO_Y23,
+ EXYNOS5_GPIO_Y24,
+ EXYNOS5_GPIO_Y25,
+ EXYNOS5_GPIO_Y26,
+ EXYNOS5_GPIO_Y27,
+ EXYNOS5_GPIO_Y30, /* 128 0x80 */
+ EXYNOS5_GPIO_Y31,
+ EXYNOS5_GPIO_Y32,
+ EXYNOS5_GPIO_Y33,
+ EXYNOS5_GPIO_Y34,
+ EXYNOS5_GPIO_Y35,
+ EXYNOS5_GPIO_Y36,
+ EXYNOS5_GPIO_Y37,
+ EXYNOS5_GPIO_Y40, /* 136 0x88 */
+ EXYNOS5_GPIO_Y41,
+ EXYNOS5_GPIO_Y42,
+ EXYNOS5_GPIO_Y43,
+ EXYNOS5_GPIO_Y44,
+ EXYNOS5_GPIO_Y45,
+ EXYNOS5_GPIO_Y46,
+ EXYNOS5_GPIO_Y47,
+ EXYNOS5_GPIO_Y50, /* 144 0x90 */
+ EXYNOS5_GPIO_Y51,
+ EXYNOS5_GPIO_Y52,
+ EXYNOS5_GPIO_Y53,
+ EXYNOS5_GPIO_Y54,
+ EXYNOS5_GPIO_Y55,
+ EXYNOS5_GPIO_Y56,
+ EXYNOS5_GPIO_Y57,
+ EXYNOS5_GPIO_Y60, /* 152 0x98 */
+ EXYNOS5_GPIO_Y61,
+ EXYNOS5_GPIO_Y62,
+ EXYNOS5_GPIO_Y63,
+ EXYNOS5_GPIO_Y64,
+ EXYNOS5_GPIO_Y65,
+ EXYNOS5_GPIO_Y66,
+ EXYNOS5_GPIO_Y67,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */
+ EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+ EXYNOS5_GPIO_C41,
+ EXYNOS5_GPIO_C42,
+ EXYNOS5_GPIO_C43,
+ EXYNOS5_GPIO_C44,
+ EXYNOS5_GPIO_C45,
+ EXYNOS5_GPIO_C46,
+ EXYNOS5_GPIO_C47,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */
+ EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+ EXYNOS5_GPIO_X01,
+ EXYNOS5_GPIO_X02,
+ EXYNOS5_GPIO_X03,
+ EXYNOS5_GPIO_X04,
+ EXYNOS5_GPIO_X05,
+ EXYNOS5_GPIO_X06,
+ EXYNOS5_GPIO_X07,
+ EXYNOS5_GPIO_X10, /* 176 0xb0 */
+ EXYNOS5_GPIO_X11,
+ EXYNOS5_GPIO_X12,
+ EXYNOS5_GPIO_X13,
+ EXYNOS5_GPIO_X14,
+ EXYNOS5_GPIO_X15,
+ EXYNOS5_GPIO_X16,
+ EXYNOS5_GPIO_X17,
+ EXYNOS5_GPIO_X20, /* 184 0xb8 */
+ EXYNOS5_GPIO_X21,
+ EXYNOS5_GPIO_X22,
+ EXYNOS5_GPIO_X23,
+ EXYNOS5_GPIO_X24,
+ EXYNOS5_GPIO_X25,
+ EXYNOS5_GPIO_X26,
+ EXYNOS5_GPIO_X27,
+ EXYNOS5_GPIO_X30, /* 192 0xc0 */
+ EXYNOS5_GPIO_X31,
+ EXYNOS5_GPIO_X32,
+ EXYNOS5_GPIO_X33,
+ EXYNOS5_GPIO_X34,
+ EXYNOS5_GPIO_X35,
+ EXYNOS5_GPIO_X36,
+ EXYNOS5_GPIO_X37,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */
+ EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+ EXYNOS5_GPIO_E01,
+ EXYNOS5_GPIO_E02,
+ EXYNOS5_GPIO_E03,
+ EXYNOS5_GPIO_E04,
+ EXYNOS5_GPIO_E05,
+ EXYNOS5_GPIO_E06,
+ EXYNOS5_GPIO_E07,
+ EXYNOS5_GPIO_E10, /* 208 0xd0 */
+ EXYNOS5_GPIO_E11,
+ EXYNOS5_GPIO_E12,
+ EXYNOS5_GPIO_E13,
+ EXYNOS5_GPIO_E14,
+ EXYNOS5_GPIO_E15,
+ EXYNOS5_GPIO_E16,
+ EXYNOS5_GPIO_E17,
+ EXYNOS5_GPIO_F00, /* 216 0xd8 */
+ EXYNOS5_GPIO_F01,
+ EXYNOS5_GPIO_F02,
+ EXYNOS5_GPIO_F03,
+ EXYNOS5_GPIO_F04,
+ EXYNOS5_GPIO_F05,
+ EXYNOS5_GPIO_F06,
+ EXYNOS5_GPIO_F07,
+ EXYNOS5_GPIO_F10, /* 224 0xe0 */
+ EXYNOS5_GPIO_F11,
+ EXYNOS5_GPIO_F12,
+ EXYNOS5_GPIO_F13,
+ EXYNOS5_GPIO_F14,
+ EXYNOS5_GPIO_F15,
+ EXYNOS5_GPIO_F16,
+ EXYNOS5_GPIO_F17,
+ EXYNOS5_GPIO_G00, /* 232 0xe8 */
+ EXYNOS5_GPIO_G01,
+ EXYNOS5_GPIO_G02,
+ EXYNOS5_GPIO_G03,
+ EXYNOS5_GPIO_G04,
+ EXYNOS5_GPIO_G05,
+ EXYNOS5_GPIO_G06,
+ EXYNOS5_GPIO_G07,
+ EXYNOS5_GPIO_G10, /* 240 0xf0 */
+ EXYNOS5_GPIO_G11,
+ EXYNOS5_GPIO_G12,
+ EXYNOS5_GPIO_G13,
+ EXYNOS5_GPIO_G14,
+ EXYNOS5_GPIO_G15,
+ EXYNOS5_GPIO_G16,
+ EXYNOS5_GPIO_G17,
+ EXYNOS5_GPIO_G20, /* 248 0xf8 */
+ EXYNOS5_GPIO_G21,
+ EXYNOS5_GPIO_G22,
+ EXYNOS5_GPIO_G23,
+ EXYNOS5_GPIO_G24,
+ EXYNOS5_GPIO_G25,
+ EXYNOS5_GPIO_G26,
+ EXYNOS5_GPIO_G27,
+ EXYNOS5_GPIO_H00, /* 256 0x100 */
+ EXYNOS5_GPIO_H01,
+ EXYNOS5_GPIO_H02,
+ EXYNOS5_GPIO_H03,
+ EXYNOS5_GPIO_H04,
+ EXYNOS5_GPIO_H05,
+ EXYNOS5_GPIO_H06,
+ EXYNOS5_GPIO_H07,
+ EXYNOS5_GPIO_H10, /* 264 0x108 */
+ EXYNOS5_GPIO_H11,
+ EXYNOS5_GPIO_H12,
+ EXYNOS5_GPIO_H13,
+ EXYNOS5_GPIO_H14,
+ EXYNOS5_GPIO_H15,
+ EXYNOS5_GPIO_H16,
+ EXYNOS5_GPIO_H17,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */
+ EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+ EXYNOS5_GPIO_V01,
+ EXYNOS5_GPIO_V02,
+ EXYNOS5_GPIO_V03,
+ EXYNOS5_GPIO_V04,
+ EXYNOS5_GPIO_V05,
+ EXYNOS5_GPIO_V06,
+ EXYNOS5_GPIO_V07,
+ EXYNOS5_GPIO_V10, /* 280 0x118 */
+ EXYNOS5_GPIO_V11,
+ EXYNOS5_GPIO_V12,
+ EXYNOS5_GPIO_V13,
+ EXYNOS5_GPIO_V14,
+ EXYNOS5_GPIO_V15,
+ EXYNOS5_GPIO_V16,
+ EXYNOS5_GPIO_V17,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */
+ EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+ EXYNOS5_GPIO_V21,
+ EXYNOS5_GPIO_V22,
+ EXYNOS5_GPIO_V23,
+ EXYNOS5_GPIO_V24,
+ EXYNOS5_GPIO_V25,
+ EXYNOS5_GPIO_V26,
+ EXYNOS5_GPIO_V27,
+ EXYNOS5_GPIO_V30, /* 296 0x128 */
+ EXYNOS5_GPIO_V31,
+ EXYNOS5_GPIO_V32,
+ EXYNOS5_GPIO_V33,
+ EXYNOS5_GPIO_V34,
+ EXYNOS5_GPIO_V35,
+ EXYNOS5_GPIO_V36,
+ EXYNOS5_GPIO_V37,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */
+ EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+ EXYNOS5_GPIO_V41,
+ EXYNOS5_GPIO_V42,
+ EXYNOS5_GPIO_V43,
+ EXYNOS5_GPIO_V44,
+ EXYNOS5_GPIO_V45,
+ EXYNOS5_GPIO_V46,
+ EXYNOS5_GPIO_V47,
+
+ /* GPIO_PART7_STARTS */ /* 312 0x138 */
+ EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+ EXYNOS5_GPIO_Z1,
+ EXYNOS5_GPIO_Z2,
+ EXYNOS5_GPIO_Z3,
+ EXYNOS5_GPIO_Z4,
+ EXYNOS5_GPIO_Z5,
+ EXYNOS5_GPIO_Z6,
+ EXYNOS5_GPIO_MAX_PORT
+};
+
+enum exynos5420_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS5420_GPIO_A00, /* 0 */
+ EXYNOS5420_GPIO_A01,
+ EXYNOS5420_GPIO_A02,
+ EXYNOS5420_GPIO_A03,
+ EXYNOS5420_GPIO_A04,
+ EXYNOS5420_GPIO_A05,
+ EXYNOS5420_GPIO_A06,
+ EXYNOS5420_GPIO_A07,
+ EXYNOS5420_GPIO_A10, /* 8 */
+ EXYNOS5420_GPIO_A11,
+ EXYNOS5420_GPIO_A12,
+ EXYNOS5420_GPIO_A13,
+ EXYNOS5420_GPIO_A14,
+ EXYNOS5420_GPIO_A15,
+ EXYNOS5420_GPIO_A16,
+ EXYNOS5420_GPIO_A17,
+ EXYNOS5420_GPIO_A20, /* 16 0x10 */
+ EXYNOS5420_GPIO_A21,
+ EXYNOS5420_GPIO_A22,
+ EXYNOS5420_GPIO_A23,
+ EXYNOS5420_GPIO_A24,
+ EXYNOS5420_GPIO_A25,
+ EXYNOS5420_GPIO_A26,
+ EXYNOS5420_GPIO_A27,
+ EXYNOS5420_GPIO_B00, /* 24 0x18 */
+ EXYNOS5420_GPIO_B01,
+ EXYNOS5420_GPIO_B02,
+ EXYNOS5420_GPIO_B03,
+ EXYNOS5420_GPIO_B04,
+ EXYNOS5420_GPIO_B05,
+ EXYNOS5420_GPIO_B06,
+ EXYNOS5420_GPIO_B07,
+ EXYNOS5420_GPIO_B10, /* 32 0x20 */
+ EXYNOS5420_GPIO_B11,
+ EXYNOS5420_GPIO_B12,
+ EXYNOS5420_GPIO_B13,
+ EXYNOS5420_GPIO_B14,
+ EXYNOS5420_GPIO_B15,
+ EXYNOS5420_GPIO_B16,
+ EXYNOS5420_GPIO_B17,
+ EXYNOS5420_GPIO_B20, /* 40 0x28 */
+ EXYNOS5420_GPIO_B21,
+ EXYNOS5420_GPIO_B22,
+ EXYNOS5420_GPIO_B23,
+ EXYNOS5420_GPIO_B24,
+ EXYNOS5420_GPIO_B25,
+ EXYNOS5420_GPIO_B26,
+ EXYNOS5420_GPIO_B27,
+ EXYNOS5420_GPIO_B30, /* 48 0x30 */
+ EXYNOS5420_GPIO_B31,
+ EXYNOS5420_GPIO_B32,
+ EXYNOS5420_GPIO_B33,
+ EXYNOS5420_GPIO_B34,
+ EXYNOS5420_GPIO_B35,
+ EXYNOS5420_GPIO_B36,
+ EXYNOS5420_GPIO_B37,
+ EXYNOS5420_GPIO_B40, /* 56 0x38 */
+ EXYNOS5420_GPIO_B41,
+ EXYNOS5420_GPIO_B42,
+ EXYNOS5420_GPIO_B43,
+ EXYNOS5420_GPIO_B44,
+ EXYNOS5420_GPIO_B45,
+ EXYNOS5420_GPIO_B46,
+ EXYNOS5420_GPIO_B47,
+ EXYNOS5420_GPIO_H00, /* 64 0x40 */
+ EXYNOS5420_GPIO_H01,
+ EXYNOS5420_GPIO_H02,
+ EXYNOS5420_GPIO_H03,
+ EXYNOS5420_GPIO_H04,
+ EXYNOS5420_GPIO_H05,
+ EXYNOS5420_GPIO_H06,
+ EXYNOS5420_GPIO_H07,
+
+ /* GPIO PART 2 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_1, /* 72 0x48 */
+ EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y71,
+ EXYNOS5420_GPIO_Y72,
+ EXYNOS5420_GPIO_Y73,
+ EXYNOS5420_GPIO_Y74,
+ EXYNOS5420_GPIO_Y75,
+ EXYNOS5420_GPIO_Y76,
+ EXYNOS5420_GPIO_Y77,
+
+ /* GPIO PART 3 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_2, /* 80 0x50 */
+ EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+ EXYNOS5420_GPIO_X01,
+ EXYNOS5420_GPIO_X02,
+ EXYNOS5420_GPIO_X03,
+ EXYNOS5420_GPIO_X04,
+ EXYNOS5420_GPIO_X05,
+ EXYNOS5420_GPIO_X06,
+ EXYNOS5420_GPIO_X07,
+ EXYNOS5420_GPIO_X10, /* 88 0x58 */
+ EXYNOS5420_GPIO_X11,
+ EXYNOS5420_GPIO_X12,
+ EXYNOS5420_GPIO_X13,
+ EXYNOS5420_GPIO_X14,
+ EXYNOS5420_GPIO_X15,
+ EXYNOS5420_GPIO_X16,
+ EXYNOS5420_GPIO_X17,
+ EXYNOS5420_GPIO_X20, /* 96 0x60 */
+ EXYNOS5420_GPIO_X21,
+ EXYNOS5420_GPIO_X22,
+ EXYNOS5420_GPIO_X23,
+ EXYNOS5420_GPIO_X24,
+ EXYNOS5420_GPIO_X25,
+ EXYNOS5420_GPIO_X26,
+ EXYNOS5420_GPIO_X27,
+ EXYNOS5420_GPIO_X30, /* 104 0x68 */
+ EXYNOS5420_GPIO_X31,
+ EXYNOS5420_GPIO_X32,
+ EXYNOS5420_GPIO_X33,
+ EXYNOS5420_GPIO_X34,
+ EXYNOS5420_GPIO_X35,
+ EXYNOS5420_GPIO_X36,
+ EXYNOS5420_GPIO_X37,
+
+ /* GPIO PART 4 STARTS*/
+ EXYNOS5420_GPIO_MAX_PORT_PART_3, /* 112 0x70 */
+ EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
+ EXYNOS5420_GPIO_C01,
+ EXYNOS5420_GPIO_C02,
+ EXYNOS5420_GPIO_C03,
+ EXYNOS5420_GPIO_C04,
+ EXYNOS5420_GPIO_C05,
+ EXYNOS5420_GPIO_C06,
+ EXYNOS5420_GPIO_C07,
+ EXYNOS5420_GPIO_C10, /* 120 0x78 */
+ EXYNOS5420_GPIO_C11,
+ EXYNOS5420_GPIO_C12,
+ EXYNOS5420_GPIO_C13,
+ EXYNOS5420_GPIO_C14,
+ EXYNOS5420_GPIO_C15,
+ EXYNOS5420_GPIO_C16,
+ EXYNOS5420_GPIO_C17,
+ EXYNOS5420_GPIO_C20, /* 128 0x80 */
+ EXYNOS5420_GPIO_C21,
+ EXYNOS5420_GPIO_C22,
+ EXYNOS5420_GPIO_C23,
+ EXYNOS5420_GPIO_C24,
+ EXYNOS5420_GPIO_C25,
+ EXYNOS5420_GPIO_C26,
+ EXYNOS5420_GPIO_C27,
+ EXYNOS5420_GPIO_C30, /* 136 0x88 */
+ EXYNOS5420_GPIO_C31,
+ EXYNOS5420_GPIO_C32,
+ EXYNOS5420_GPIO_C33,
+ EXYNOS5420_GPIO_C34,
+ EXYNOS5420_GPIO_C35,
+ EXYNOS5420_GPIO_C36,
+ EXYNOS5420_GPIO_C37,
+ EXYNOS5420_GPIO_C40, /* 144 0x90 */
+ EXYNOS5420_GPIO_C41,
+ EXYNOS5420_GPIO_C42,
+ EXYNOS5420_GPIO_C43,
+ EXYNOS5420_GPIO_C44,
+ EXYNOS5420_GPIO_C45,
+ EXYNOS5420_GPIO_C46,
+ EXYNOS5420_GPIO_C47,
+ EXYNOS5420_GPIO_D10, /* 152 0x98 */
+ EXYNOS5420_GPIO_D11,
+ EXYNOS5420_GPIO_D12,
+ EXYNOS5420_GPIO_D13,
+ EXYNOS5420_GPIO_D14,
+ EXYNOS5420_GPIO_D15,
+ EXYNOS5420_GPIO_D16,
+ EXYNOS5420_GPIO_D17,
+ EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
+ EXYNOS5420_GPIO_Y01,
+ EXYNOS5420_GPIO_Y02,
+ EXYNOS5420_GPIO_Y03,
+ EXYNOS5420_GPIO_Y04,
+ EXYNOS5420_GPIO_Y05,
+ EXYNOS5420_GPIO_Y06,
+ EXYNOS5420_GPIO_Y07,
+ EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
+ EXYNOS5420_GPIO_Y11,
+ EXYNOS5420_GPIO_Y12,
+ EXYNOS5420_GPIO_Y13,
+ EXYNOS5420_GPIO_Y14,
+ EXYNOS5420_GPIO_Y15,
+ EXYNOS5420_GPIO_Y16,
+ EXYNOS5420_GPIO_Y17,
+ EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
+ EXYNOS5420_GPIO_Y21,
+ EXYNOS5420_GPIO_Y22,
+ EXYNOS5420_GPIO_Y23,
+ EXYNOS5420_GPIO_Y24,
+ EXYNOS5420_GPIO_Y25,
+ EXYNOS5420_GPIO_Y26,
+ EXYNOS5420_GPIO_Y27,
+ EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
+ EXYNOS5420_GPIO_Y31,
+ EXYNOS5420_GPIO_Y32,
+ EXYNOS5420_GPIO_Y33,
+ EXYNOS5420_GPIO_Y34,
+ EXYNOS5420_GPIO_Y35,
+ EXYNOS5420_GPIO_Y36,
+ EXYNOS5420_GPIO_Y37,
+ EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
+ EXYNOS5420_GPIO_Y41,
+ EXYNOS5420_GPIO_Y42,
+ EXYNOS5420_GPIO_Y43,
+ EXYNOS5420_GPIO_Y44,
+ EXYNOS5420_GPIO_Y45,
+ EXYNOS5420_GPIO_Y46,
+ EXYNOS5420_GPIO_Y47,
+ EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
+ EXYNOS5420_GPIO_Y51,
+ EXYNOS5420_GPIO_Y52,
+ EXYNOS5420_GPIO_Y53,
+ EXYNOS5420_GPIO_Y54,
+ EXYNOS5420_GPIO_Y55,
+ EXYNOS5420_GPIO_Y56,
+ EXYNOS5420_GPIO_Y57,
+ EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
+ EXYNOS5420_GPIO_Y61,
+ EXYNOS5420_GPIO_Y62,
+ EXYNOS5420_GPIO_Y63,
+ EXYNOS5420_GPIO_Y64,
+ EXYNOS5420_GPIO_Y65,
+ EXYNOS5420_GPIO_Y66,
+ EXYNOS5420_GPIO_Y67,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_4, /* 216 0xd8 */
+ EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
+ EXYNOS5420_GPIO_E01,
+ EXYNOS5420_GPIO_E02,
+ EXYNOS5420_GPIO_E03,
+ EXYNOS5420_GPIO_E04,
+ EXYNOS5420_GPIO_E05,
+ EXYNOS5420_GPIO_E06,
+ EXYNOS5420_GPIO_E07,
+ EXYNOS5420_GPIO_E10, /* 224 0xe0 */
+ EXYNOS5420_GPIO_E11,
+ EXYNOS5420_GPIO_E12,
+ EXYNOS5420_GPIO_E13,
+ EXYNOS5420_GPIO_E14,
+ EXYNOS5420_GPIO_E15,
+ EXYNOS5420_GPIO_E16,
+ EXYNOS5420_GPIO_E17,
+ EXYNOS5420_GPIO_F00, /* 232 0xe8 */
+ EXYNOS5420_GPIO_F01,
+ EXYNOS5420_GPIO_F02,
+ EXYNOS5420_GPIO_F03,
+ EXYNOS5420_GPIO_F04,
+ EXYNOS5420_GPIO_F05,
+ EXYNOS5420_GPIO_F06,
+ EXYNOS5420_GPIO_F07,
+ EXYNOS5420_GPIO_F10, /* 240 0xf0 */
+ EXYNOS5420_GPIO_F11,
+ EXYNOS5420_GPIO_F12,
+ EXYNOS5420_GPIO_F13,
+ EXYNOS5420_GPIO_F14,
+ EXYNOS5420_GPIO_F15,
+ EXYNOS5420_GPIO_F16,
+ EXYNOS5420_GPIO_F17,
+ EXYNOS5420_GPIO_G00, /* 248 0xf8 */
+ EXYNOS5420_GPIO_G01,
+ EXYNOS5420_GPIO_G02,
+ EXYNOS5420_GPIO_G03,
+ EXYNOS5420_GPIO_G04,
+ EXYNOS5420_GPIO_G05,
+ EXYNOS5420_GPIO_G06,
+ EXYNOS5420_GPIO_G07,
+ EXYNOS5420_GPIO_G10, /* 256 0x100 */
+ EXYNOS5420_GPIO_G11,
+ EXYNOS5420_GPIO_G12,
+ EXYNOS5420_GPIO_G13,
+ EXYNOS5420_GPIO_G14,
+ EXYNOS5420_GPIO_G15,
+ EXYNOS5420_GPIO_G16,
+ EXYNOS5420_GPIO_G17,
+ EXYNOS5420_GPIO_G20, /* 264 0x108 */
+ EXYNOS5420_GPIO_G21,
+ EXYNOS5420_GPIO_G22,
+ EXYNOS5420_GPIO_G23,
+ EXYNOS5420_GPIO_G24,
+ EXYNOS5420_GPIO_G25,
+ EXYNOS5420_GPIO_G26,
+ EXYNOS5420_GPIO_G27,
+ EXYNOS5420_GPIO_J40, /* 272 0x110 */
+ EXYNOS5420_GPIO_J41,
+ EXYNOS5420_GPIO_J42,
+ EXYNOS5420_GPIO_J43,
+ EXYNOS5420_GPIO_J44,
+ EXYNOS5420_GPIO_J45,
+ EXYNOS5420_GPIO_J46,
+ EXYNOS5420_GPIO_J47,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS5420_GPIO_MAX_PORT_PART_5, /* 280 0x118 */
+ EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
+ EXYNOS5420_GPIO_Z1,
+ EXYNOS5420_GPIO_Z2,
+ EXYNOS5420_GPIO_Z3,
+ EXYNOS5420_GPIO_Z4,
+ EXYNOS5420_GPIO_Z5,
+ EXYNOS5420_GPIO_Z6,
+ EXYNOS5420_GPIO_MAX_PORT
+};
+struct gpio_info {
+ unsigned int reg_addr; /* Address of register for this part */
+ unsigned int max_gpio; /* Maximum GPIO in this part */
+};
+
+#define EXYNOS5_GPIO_NUM_PARTS 8
+static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+ { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+ { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+ { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define EXYNOS5420_GPIO_NUM_PARTS 6
+static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
+};
+
+static inline struct gpio_info *get_gpio_data(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_gpio_data;
+ else
+ return exynos5_gpio_data;
+ } else {
+ return NULL;
+ }
+}
+
+static inline unsigned int get_bank_num(void)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return EXYNOS5420_GPIO_NUM_PARTS;
+ else
+ return EXYNOS5_GPIO_NUM_PARTS;
+ } else {
+ return 0;
+ }
+}
+
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
#endif
/* Pin configurations */
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index 379a45c..58821c4 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable MAX98095 Codec */
- s5p_gpio_direction_output(&gpio1->x1, 7, 1);
- s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+ gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@@ -47,19 +44,16 @@ int exynos_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 28a6d9e..bdfb49f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable MAX98095 Codec */
- s5p_gpio_direction_output(&gpio1->x1, 7, 1);
- s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+ gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
}
#endif
@@ -275,19 +272,17 @@ int exynos_power_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
index e4606ec..fa3aa2c 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
static int board_usb_vbus_init(void)
{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
/* Enable VBUS power switch */
- s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+ gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
/* VBUS turn ON time */
mdelay(3);
@@ -49,15 +46,15 @@ void cfg_lcd_gpio(void)
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
- s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->b2, 0, 1);
+ gpio_cfg_pin(EXYNOS5420_GPIO_B10, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5420_GPIO_B20, 1);
/* LCD power on */
- s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
- s5p_gpio_set_value(&gpio1->x1, 5, 1);
+ gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5420_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
vidinfo_t panel_info = {
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 11a0472..c29a04a 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -12,7 +12,7 @@
#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \
& S5P_GPIO_BANK_MASK)
-#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x) ((x & S5P_GPIO_PIN_MASK) % GPIO_PER_BANK)
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
@@ -127,6 +127,29 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
writel(value, &bank->drv);
}
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+{
+ const struct gpio_info *data;
+ unsigned int upto;
+ int i, count;
+
+ data = get_gpio_data();
+ count = get_bank_num();
+ for (i = upto = 0; i < count;
+ i++, upto = data->max_gpio, data++) {
+ debug("i=%d, upto=%d\n", i, upto);
+ if (gpio < data->max_gpio) {
+ struct s5p_gpio_bank *bank;
+ bank = (struct s5p_gpio_bank *)data->reg_addr;
+ bank += (gpio - upto) / GPIO_PER_BANK;
+ debug("gpio=%d, bank=%p\n", gpio, bank);
+ return bank;
+ }
+ }
+ return NULL;
+}
+#else
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
unsigned bank = S5P_GPIO_GET_BANK(gpio);
@@ -134,6 +157,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
return (struct s5p_gpio_bank *)(base + bank);
}
+#endif
int s5p_gpio_get_pin(unsigned gpio)
{
@@ -179,3 +203,21 @@ int gpio_set_value(unsigned gpio, int value)
return 0;
}
+
+void gpio_set_pull(int gpio, int mode)
+{
+ s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+ s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+ s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), cfg);
+}
--
1.8.3.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
@ 2014-04-12 9:43 ` Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
2014-04-14 15:15 ` Przemyslaw Marczak
2014-04-12 9:43 ` [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5 Akshay Saraswat
` (2 subsequent siblings)
4 siblings, 2 replies; 19+ messages in thread
From: Akshay Saraswat @ 2014-04-12 9:43 UTC (permalink / raw)
To: u-boot
From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This patch rename GPIO definitions from GPIO_... to S5P_GPIO_...
This changes was done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.
Build tested for s5p_goni, origen, smdk5250, s5pc210_universal,
trats, smdkc100, smdkv310 config files.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/pinmux.c | 220 +++++++++++++++----------------
arch/arm/include/asm/arch-exynos/gpio.h | 26 ++--
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 ++--
board/samsung/goni/goni.c | 4 +-
board/samsung/smdk5250/smdk5250.c | 8 +-
board/samsung/smdkc100/smdkc100.c | 2 +-
board/samsung/smdkv310/smdkv310.c | 10 +-
board/samsung/trats/trats.c | 6 +-
board/samsung/universal_c210/universal.c | 34 ++---
drivers/gpio/s5p_gpio.c | 20 +--
10 files changed, 178 insertions(+), 178 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 34c24cd..9added6 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -37,8 +37,8 @@ static void exynos5_uart_config(int peripheral)
return;
}
for (i = start; i < start + count; i++) {
- gpio_set_pull(i, GPIO_PULL_NONE);
- gpio_cfg_pin(i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
@@ -69,8 +69,8 @@ static void exynos5420_uart_config(int peripheral)
}
for (i = start; i < start + count; i++) {
- gpio_set_pull(i, GPIO_PULL_NONE);
- gpio_cfg_pin(i, GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
@@ -82,7 +82,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
case PERIPH_ID_SDMMC0:
start = EXYNOS5_GPIO_C00;
start_ext = EXYNOS5_GPIO_C10;
- gpio_func = GPIO_FUNC(0x2);
+ gpio_func = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
start = EXYNOS5_GPIO_C20;
@@ -91,7 +91,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
case PERIPH_ID_SDMMC2:
start = EXYNOS5_GPIO_C30;
start_ext = EXYNOS5_GPIO_C43;
- gpio_func = GPIO_FUNC(0x3);
+ gpio_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
start = EXYNOS5_GPIO_C40;
@@ -109,19 +109,19 @@ static int exynos5_mmc_config(int peripheral, int flags)
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i <= (start_ext + 3); i++) {
gpio_cfg_pin(i, gpio_func);
- gpio_set_pull(i, GPIO_PULL_UP);
- gpio_set_drv(i, GPIO_DRV_4X);
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
- gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
- gpio_set_pull(start + i, GPIO_PULL_NONE);
- gpio_set_drv(start + i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
- gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
- gpio_set_pull(start + i, GPIO_PULL_UP);
- gpio_set_drv(start + i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
}
return 0;
@@ -161,9 +161,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
- gpio_cfg_pin(i, GPIO_FUNC(0x2));
- gpio_set_pull(i, GPIO_PULL_UP);
- gpio_set_drv(i, GPIO_DRV_4X);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
@@ -176,18 +176,18 @@ static int exynos5420_mmc_config(int peripheral, int flags)
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
gpio_set_value(i, 1);
- gpio_cfg_pin(i, GPIO_OUTPUT);
+ gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
} else {
- gpio_cfg_pin(i, GPIO_FUNC(0x2));
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
- gpio_set_pull(i, GPIO_PULL_NONE);
- gpio_set_drv(i, GPIO_DRV_4X);
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
- gpio_cfg_pin(i, GPIO_FUNC(0x2));
- gpio_set_pull(i, GPIO_PULL_UP);
- gpio_set_drv(i, GPIO_DRV_4X);
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
@@ -213,12 +213,12 @@ static void exynos5_sromc_config(int flags)
* GPY1[3] EBI_DATA_RDn(2)
*/
gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
- GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
- gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
+ S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
for (i = 0; i < 4; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
@@ -253,14 +253,14 @@ static void exynos5_sromc_config(int flags)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
- gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
- gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
- gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
+ gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+ gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
}
}
@@ -268,36 +268,36 @@ static void exynos5_i2c_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
}
}
@@ -306,48 +306,48 @@ static void exynos5420_i2c_config(int peripheral)
{
switch (peripheral) {
case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5420_GPIO_B30, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B31, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5420_GPIO_B32, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B33, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5420_GPIO_A06, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A07, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5420_GPIO_A12, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A13, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- gpio_cfg_pin(EXYNOS5420_GPIO_A20, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A21, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- gpio_cfg_pin(EXYNOS5420_GPIO_A22, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_A23, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- gpio_cfg_pin(EXYNOS5420_GPIO_B13, GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5420_GPIO_B14, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- gpio_cfg_pin(EXYNOS5420_GPIO_B22, GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5420_GPIO_B23, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
- gpio_cfg_pin(EXYNOS5420_GPIO_B34, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B35, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
- gpio_cfg_pin(EXYNOS5420_GPIO_B36, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B37, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
- gpio_cfg_pin(EXYNOS5420_GPIO_B40, GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5420_GPIO_B41, GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
break;
}
}
@@ -359,11 +359,11 @@ static void exynos5_i2s_config(int peripheral)
switch (peripheral) {
case PERIPH_ID_I2S0:
for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, S5P_GPIO_FUNC(0x02));
break;
case PERIPH_ID_I2S1:
for (i = 0; i < 5; i++)
- gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
+ gpio_cfg_pin(EXYNOS5_GPIO_B00+i, S5P_GPIO_FUNC(0x02));
break;
}
}
@@ -374,25 +374,25 @@ void exynos5_spi_config(int peripheral)
switch (peripheral) {
case PERIPH_ID_SPI0:
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A20;
break;
case PERIPH_ID_SPI1:
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A24;
break;
case PERIPH_ID_SPI2:
- cfg = GPIO_FUNC(0x5);
+ cfg = S5P_GPIO_FUNC(0x5);
pin = EXYNOS5_GPIO_B11;
break;
case PERIPH_ID_SPI3:
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_F10;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
- gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
- gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+ gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
}
break;
}
@@ -409,19 +409,19 @@ void exynos5420_spi_config(int peripheral)
switch (peripheral) {
case PERIPH_ID_SPI0:
pin = EXYNOS5420_GPIO_A20;
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI1:
pin = EXYNOS5420_GPIO_A24;
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI2:
pin = EXYNOS5420_GPIO_B11;
- cfg = GPIO_FUNC(0x5);
+ cfg = S5P_GPIO_FUNC(0x5);
break;
case PERIPH_ID_SPI3:
pin = EXYNOS5420_GPIO_F10;
- cfg = GPIO_FUNC(0x2);
+ cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI4:
cfg = 0;
@@ -440,9 +440,9 @@ void exynos5420_spi_config(int peripheral)
} else {
for (i = 0; i < 2; i++) {
gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
- GPIO_FUNC(0x4));
+ S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
- GPIO_FUNC(0x4));
+ S5P_GPIO_FUNC(0x4));
}
}
}
@@ -542,36 +542,36 @@ static void exynos4_i2c_config(int peripheral, int flags)
switch (peripheral) {
case PERIPH_ID_I2C0:
- s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, S5P_GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
- s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, S5P_GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
- s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
- s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
- s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 2, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
- s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 6, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
- s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
- s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, S5P_GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
- s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, S5P_GPIO_FUNC(0x3));
break;
}
}
@@ -598,15 +598,15 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = 0; i < 7; i++) {
if (i == 2)
continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ s5p_gpio_cfg_pin(bank, i, S5P_GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ s5p_gpio_cfg_pin(bank_ext, i, S5P_GPIO_FUNC(0x3));
+ s5p_gpio_set_pull(bank_ext, i, S5P_GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank_ext, i, S5P_GPIO_DRV_4X);
}
}
@@ -646,8 +646,8 @@ static void exynos4_uart_config(int peripheral)
return;
}
for (i = start; i < start + count; i++) {
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos4_pinmux_config(int peripheral, int flags)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 211383d..697e6f3 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1046,21 +1046,21 @@ int gpio_set_value(unsigned gpio, int value);
#endif
/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x3
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x3
/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index da8df74..dd94eb8 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -167,22 +167,22 @@ static inline unsigned int s5p_gpio_base(int nr)
#endif
/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x2
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x2
/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
#endif
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 61b9ece..b0563da 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -97,9 +97,9 @@ int board_mmc_init(bd_t *bis)
/* GPG0[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
/* GPG0[0:6] pull disable */
- s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&s5pc110_gpio->g0, i, S5P_GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
- s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+ s5p_gpio_set_drv(&s5pc110_gpio->g0, i, S5P_GPIO_DRV_4X);
}
ret = s5p_mmc_init(0, 4);
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index bdfb49f..014b7bd 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -31,7 +31,7 @@ static void board_enable_audio_codec(void)
{
/* Enable MAX98095 Codec */
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
- gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@@ -274,15 +274,15 @@ void exynos_cfg_lcd_gpio(void)
{
/* For Backlight */
- gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
- gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 860c851..e637b21 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -25,7 +25,7 @@ static void smc9115_pre_init(void)
(struct s5pc100_gpio *)samsung_get_base_gpio();
/* gpio configuration GPK0CON */
- s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index 81a3060..171a4a1 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -23,7 +23,7 @@ static void smc9115_pre_init(void)
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
- s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
@@ -105,19 +105,19 @@ int board_mmc_init(bd_t *bis)
*/
for (i = 0; i < 7; i++) {
/* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+ s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+ s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7c79e7b..701a48a 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -354,8 +354,8 @@ static unsigned int get_hw_revision(void)
/* hw_rev[3:0] == GPE1[3:0] */
for (i = 0; i < 4; i++) {
- s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
- s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio->e1, i, S5P_GPIO_INPUT);
+ s5p_gpio_set_pull(&gpio->e1, i, S5P_GPIO_PULL_NONE);
}
udelay(1);
@@ -448,7 +448,7 @@ static void pmic_reset(void)
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio->x0, 7, 1);
- s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio->x2, 7, S5P_GPIO_PULL_NONE);
}
static void board_clock_init(void)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index f9d71b6..e87e54c 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -312,35 +312,35 @@ void exynos_cfg_lcd_gpio(void)
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
- s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f0, i, S5P_GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f1, i, S5P_GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f2, i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
- s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
- s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
- s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f0, i, S5P_GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f1, i, S5P_GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f2, i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
- s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
- s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
- s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f0, i, S5P_GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f1, i, S5P_GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f1, i, S5P_GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f2, i, S5P_GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
}
for (i = 0; i < f3_end; i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
- s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f3, i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
- s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f3, i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
- s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
- s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+
+ s5p_gpio_set_rate(&gpio1->f3, i, S5P_GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
- s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+ s5p_gpio_cfg_pin(&gpio2->y4, 5, S5P_GPIO_OUTPUT);
spi_init();
}
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index c29a04a..b1b6fbe 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -40,13 +40,13 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
{
- s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+ s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
s5p_gpio_set_value(bank, gpio, en);
}
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
{
- s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+ s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
}
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
@@ -76,8 +76,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~PULL_MASK(gpio);
switch (mode) {
- case GPIO_PULL_DOWN:
- case GPIO_PULL_UP:
+ case S5P_GPIO_PULL_DOWN:
+ case S5P_GPIO_PULL_UP:
value |= PULL_MODE(gpio, mode);
break;
default:
@@ -95,10 +95,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~DRV_MASK(gpio);
switch (mode) {
- case GPIO_DRV_1X:
- case GPIO_DRV_2X:
- case GPIO_DRV_3X:
- case GPIO_DRV_4X:
+ case S5P_GPIO_DRV_1X:
+ case S5P_GPIO_DRV_2X:
+ case S5P_GPIO_DRV_3X:
+ case S5P_GPIO_DRV_4X:
value |= DRV_SET(gpio, mode);
break;
default:
@@ -116,8 +116,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
value &= ~RATE_MASK(gpio);
switch (mode) {
- case GPIO_DRV_FAST:
- case GPIO_DRV_SLOW:
+ case S5P_GPIO_DRV_FAST:
+ case S5P_GPIO_DRV_SLOW:
value |= RATE_SET(gpio);
break;
default:
--
1.8.3.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
2014-04-12 9:43 ` [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions Akshay Saraswat
@ 2014-04-12 9:43 ` Akshay Saraswat
2014-04-12 20:32 ` Simon Glass
2014-04-14 15:19 ` Przemyslaw Marczak
2014-04-12 9:43 ` [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs Akshay Saraswat
2014-04-14 9:31 ` [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Przemyslaw Marczak
4 siblings, 2 replies; 19+ messages in thread
From: Akshay Saraswat @ 2014-04-12 9:43 UTC (permalink / raw)
To: u-boot
From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This patch adds support for name to gpio conversion in s5p_gpio
to enable gpio command EXYNOS 5250 & 5420.
Function has been added to asm/gpio.h to decode the
input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
arch/arm/include/asm/arch-exynos/gpio.h | 28 +++++++++
drivers/gpio/s5p_gpio.c | 105 ++++++++++++++++++++++++++++++++
2 files changed, 133 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 697e6f3..3736a22 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1038,6 +1038,34 @@ static inline unsigned int get_bank_num(void)
}
}
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ * p is optional
+ * <bank> - a single character bank name, as defined by the SOC
+ * <set> - a single digit set number
+ * <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+ char bank; /* bank name symbol */
+ u8 bank_size; /* total number of pins in the bank */
+ char bank_offset; /* offset of the first bank's pin */
+ unsigned int base; /* index of the first bank's pin in the enum */
+};
+
+int s5p_name_to_gpio(const char *name);
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index b1b6fbe..9a80b0c 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -28,6 +28,111 @@
#define RATE_MASK(x) (0x1 << (x + 16))
#define RATE_SET(x) (0x1 << (x + 16))
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table exynos5_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
+ GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
+ GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
+ GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
+ GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+static const struct gpio_name_num_table exynos5420_gpio_table[] = {
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
+ GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+int s5p_name_to_gpio(const char *name)
+{
+ unsigned num, irregular_set_number, irregular_bank_base;
+ const struct gpio_name_num_table *tabp;
+ char this_bank, bank_name, irregular_bank_name;
+ char *endp;
+
+ /*
+ * The gpio name starts with either 'g' ot 'gp' followed by the bank
+ * name character. Skip one or two characters depending on the prefix.
+ */
+ if (name[1] == 'p')
+ name += 2;
+ else
+ name++;
+ bank_name = *name++;
+ if (!*name)
+ return -1; /* At least one digit is required/expected. */
+
+ /*
+ * On both exynos5 and exynos5420 architectures there is a bank of
+ * GPIOs which does not fall into the regular address pattern. Those
+ * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
+ * assignments help to handle these irregularities.
+ */
+ if (proid_is_exynos5420()) {
+ tabp = exynos5420_gpio_table;
+ irregular_bank_name = 'y';
+ irregular_set_number = '7';
+ irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else {
+ tabp = exynos5_gpio_table;
+ irregular_bank_name = 'c';
+ irregular_set_number = '4';
+ irregular_bank_base = EXYNOS5_GPIO_C40;
+ }
+
+ this_bank = tabp->bank;
+ do {
+ if (bank_name == this_bank) {
+ unsigned pin_index; /* pin number within the bank */
+ if ((bank_name == irregular_bank_name) &&
+ (name[0] == irregular_set_number)) {
+ pin_index = name[1] - '0';
+ /* Irregular sets have 8 pins. */
+ if (pin_index >= GPIO_PER_BANK)
+ return -1;
+ num = irregular_bank_base + pin_index;
+ } else {
+ pin_index = simple_strtoul(name, &endp, 8);
+ pin_index -= tabp->bank_offset;
+ /*
+ * Sanity check: bunk 'z' has no set number,
+ * for all other banks there must be exactly
+ * two octal digits, and the resulting number
+ * should not exceed the number of pins in the
+ * bank.
+ */
+ if (((bank_name != 'z') && !name[1]) ||
+ *endp ||
+ (pin_index >= tabp->bank_size))
+ return -1;
+ num = tabp->base + pin_index;
+ }
+ return num;
+ }
+ this_bank = (++tabp)->bank;
+ } while (this_bank);
+
+ return -1;
+}
+
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
{
unsigned int value;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
` (2 preceding siblings ...)
2014-04-12 9:43 ` [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5 Akshay Saraswat
@ 2014-04-12 9:43 ` Akshay Saraswat
2014-04-12 20:33 ` Simon Glass
2014-04-14 9:31 ` [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Przemyslaw Marczak
4 siblings, 1 reply; 19+ messages in thread
From: Akshay Saraswat @ 2014-04-12 9:43 UTC (permalink / raw)
To: u-boot
From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Enable configs for GPIO CMD and Generic GPIO.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
include/configs/exynos5-dt.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 414db42..e81b5cd 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -288,4 +288,7 @@
#define CONFIG_CMD_BOOTZ
+#define HAVE_GENERIC_GPIO
+#define CONFIG_CMD_GPIO
+
#endif /* __CONFIG_H */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
@ 2014-04-12 20:30 ` Simon Glass
2014-04-14 7:17 ` Lukasz Majewski
2014-04-14 15:15 ` Przemyslaw Marczak
2 siblings, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-12 20:30 UTC (permalink / raw)
To: u-boot
On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
> To have consistent 0..n-1 GPIO numbering the banks are divided
> into different parts where ever they have holes in them.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on snow with backlight GPIOs.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions
2014-04-12 9:43 ` [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions Akshay Saraswat
@ 2014-04-12 20:30 ` Simon Glass
2014-04-14 15:15 ` Przemyslaw Marczak
1 sibling, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-12 20:30 UTC (permalink / raw)
To: u-boot
On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch rename GPIO definitions from GPIO_... to S5P_GPIO_...
> This changes was done to enable cmd_gpio for EXYNOS and
> cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
> getting a error during compilation.
>
> Build tested for s5p_goni, origen, smdk5250, s5pc210_universal,
> trats, smdkc100, smdkv310 config files.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on snow with backlight GPIOs.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
2014-04-12 9:43 ` [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5 Akshay Saraswat
@ 2014-04-12 20:32 ` Simon Glass
2014-04-14 15:19 ` Przemyslaw Marczak
1 sibling, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-12 20:32 UTC (permalink / raw)
To: u-boot
On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds support for name to gpio conversion in s5p_gpio
> to enable gpio command EXYNOS 5250 & 5420.
> Function has been added to asm/gpio.h to decode the
> input gpio name to gpio number.
>
> Example: SMDK5420 # gpio set gpa00
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on snow with backlight GPIOs.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs
2014-04-12 9:43 ` [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs Akshay Saraswat
@ 2014-04-12 20:33 ` Simon Glass
2014-04-12 20:39 ` Simon Glass
0 siblings, 1 reply; 19+ messages in thread
From: Simon Glass @ 2014-04-12 20:33 UTC (permalink / raw)
To: u-boot
On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> Enable configs for GPIO CMD and Generic GPIO.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on snow with backlight GPIOs.
> ---
> include/configs/exynos5-dt.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
> index 414db42..e81b5cd 100644
> --- a/include/configs/exynos5-dt.h
> +++ b/include/configs/exynos5-dt.h
> @@ -288,4 +288,7 @@
>
> #define CONFIG_CMD_BOOTZ
>
> +#define HAVE_GENERIC_GPIO
>
Will someone be implementing this for other Samsung SoCs?
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs
2014-04-12 20:33 ` Simon Glass
@ 2014-04-12 20:39 ` Simon Glass
0 siblings, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-12 20:39 UTC (permalink / raw)
To: u-boot
Hi Akshay,
On 12 April 2014 13:33, Simon Glass <sjg@chromium.org> wrote:
> On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:
>
>> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>>
>> Enable configs for GPIO CMD and Generic GPIO.
>>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> Tested on snow with backlight GPIOs.
>
One more question - it looks like Pit doesn't boot on ToT. It is missing a
device tree file, but it seems to be more than that - have you had it
working?
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
@ 2014-04-14 7:17 ` Lukasz Majewski
2014-04-14 14:40 ` Simon Glass
2014-04-14 15:15 ` Przemyslaw Marczak
2 siblings, 1 reply; 19+ messages in thread
From: Lukasz Majewski @ 2014-04-14 7:17 UTC (permalink / raw)
To: u-boot
Hi Akshay,
I'm not Samsung tree maintainer, but by chance I've come across those
patches and...
First question - why have you omitted u-boot-samsung tree maintainer?
I've added Minkyu to CC.
Also in the cover letter you claim that this patch was "build tested"
for Exynos4 based boards. Why didn't you add at least one maintainer of
those boards to CC?
> +
> +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface
> */ +enum exynos5_gpio_pin {
> + /* GPIO_PART1_STARTS */
> + EXYNOS5_GPIO_A00, /* 0 */
> + EXYNOS5_GPIO_A01,
> + EXYNOS5_GPIO_A02,
> + EXYNOS5_GPIO_A03,
> + EXYNOS5_GPIO_A04,
According to the patch description, you had a compilation error when
were adding the support for Exynos 5250 and 5420. Why you fix the
problem by rewriting the whole framework?
IN the patch 2/4 you have:
- gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
- gpio_set_pull(start + i, GPIO_PULL_NONE);
- gpio_set_drv(start + i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
What is the rationale to change the name to S5P_GPIO and not stick to
GPIO_FUNC? In which way gpios for Exynos5 are different than for
Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
With the same patch:
- case PERIPH_ID_UART1:
- bank = &gpio1->d0;
- start = 0;
+ start = EXYNOS5_GPIO_D00;
What is wrong with specifying the bank field?
Why your gpio command cannot use the bank approach?
And one more question: Is this work compliant with new driver model,
which will be accepted at the merge window after the v2014.04 release?
If not, then there is no point to review this code, since GPIO would
need to be adjusted to use this framework.
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
` (3 preceding siblings ...)
2014-04-12 9:43 ` [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs Akshay Saraswat
@ 2014-04-14 9:31 ` Przemyslaw Marczak
4 siblings, 0 replies; 19+ messages in thread
From: Przemyslaw Marczak @ 2014-04-14 9:31 UTC (permalink / raw)
To: u-boot
Hello Akshay,
I tried to test your patches but build breaks for trats2 and trats
configs. You didn't change some old gpio code in those boards files.
Please fix this.
On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
> From: Akshay Saraswat <akshay.s@samsung.com>
>
> Changes in V2:
> - Enabled CMD_GPIO as suggested by Simon Glass
> and supported same for EXYNOS5.
> Changes in V3:
> - New patch added to rename S5P GPIO definitions
> to S5P_GPIO.
> - GPIO Table added to calculate the base address
> of input gpio bank.
> Changes in V4:
> - To have consistent 0..n-1 GPIO numbering the banks
> are divided into different parts where ever they
> have holes in them.
> - Function and table to support gpio command moved
> to s5p-gpio driver.
> - Rebased on latest u-boot-samsung tree.
> Changes in V5:
> - Rebased on latest u-boot-samsung tree.
> - Removed Exynos5 specific code in gpio driver api to
> get bank.
> - Added #define HAVE_GENERIC_GPIO in config file
> to remove conditinal CPU check in gpio driver.
> Changes in V6:
> - Isolated config changes in a new patch.
> - Updated patches with corresponding changes for Exynos 5420.
>
> Rajeshwari Shinde (4):
> S5P: Rename GPIO definitions
> EXYNOS5: Add gpio pin numbering feature
> EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
> Config: Exynos5: Enable Generic GPIO and CMD configs
>
> arch/arm/cpu/armv7/exynos/pinmux.c | 355 ++++++--------
> arch/arm/include/asm/arch-exynos/cpu.h | 17 +-
> arch/arm/include/asm/arch-exynos/gpio.h | 796 ++++++++++++++++++++++++++++++-
> arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +-
> board/samsung/goni/goni.c | 4 +-
> board/samsung/smdk5250/exynos5-dt.c | 20 +-
> board/samsung/smdk5250/smdk5250.c | 19 +-
> board/samsung/smdk5420/smdk5420.c | 15 +-
> board/samsung/smdkc100/smdkc100.c | 2 +-
> board/samsung/smdkv310/smdkv310.c | 10 +-
> board/samsung/trats/trats.c | 6 +-
> board/samsung/universal_c210/universal.c | 34 +-
> drivers/gpio/s5p_gpio.c | 169 ++++++-
> include/configs/exynos5-dt.h | 3 +
> 14 files changed, 1157 insertions(+), 319 deletions(-)
>
Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-14 7:17 ` Lukasz Majewski
@ 2014-04-14 14:40 ` Simon Glass
2014-04-15 6:25 ` Lukasz Majewski
0 siblings, 1 reply; 19+ messages in thread
From: Simon Glass @ 2014-04-14 14:40 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com> wrote:
[snip[
I think your questions are mostly answered but I wanted to chime in on a
few.
What is wrong with specifying the bank field?
> Why your gpio command cannot use the bank approach?
>
U-Boot has a generic GPIO API and we should try to use it where possible.
This has been a long-standing TODO for exynos.
>
> And one more question: Is this work compliant with new driver model,
> which will be accepted at the merge window after the v2014.04 release?
>
> If not, then there is no point to review this code, since GPIO would
> need to be adjusted to use this framework.
>
The driver model framework is already in mainline. At present only sandbox
uses it for GPIO. I started looking at exynos since I thought it might be
quite easy to convert, but found that the generic GPIO stuff was still not
merged.
This series will make it much easier to convert exynos GPIO to driver
model, since we can just change the driver.
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
2014-04-14 7:17 ` Lukasz Majewski
@ 2014-04-14 15:15 ` Przemyslaw Marczak
2014-04-14 15:59 ` Simon Glass
2 siblings, 1 reply; 19+ messages in thread
From: Przemyslaw Marczak @ 2014-04-14 15:15 UTC (permalink / raw)
To: u-boot
Hello,
I like this idea. This is a good feature for easy and fast gpio
maintaining. I have few comments to this.
On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
> To have consistent 0..n-1 GPIO numbering the banks are divided
> into different parts where ever they have holes in them.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---
You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05",
maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5.
So then we really know what we are using and I think this just looks better.
> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
> index d6868fa..211383d 100644
> --- a/arch/arm/include/asm/arch-exynos/gpio.h
> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
> @@ -141,14 +141,16 @@ struct exynos5420_gpio_part1 {
>
It seems that those all exynos5*_gpio_partX structures and also
exynos5*_gpio_get() macros can be removed now.
> struct exynos5420_gpio_part2 {
> struct s5p_gpio_bank y7; /* 0x1340_0000 */
> - struct s5p_gpio_bank res[0x5f]; /* */
> +};
> +
> +struct exynos5420_gpio_part3 {
> struct s5p_gpio_bank x0; /* 0x1340_0C00 */
> struct s5p_gpio_bank x1; /* 0x1340_0C20 */
> struct s5p_gpio_bank x2; /* 0x1340_0C40 */
> struct s5p_gpio_bank x3; /* 0x1340_0C60 */
> };
>
> -struct exynos5420_gpio_part3 {
> +struct exynos5420_gpio_part4 {
> struct s5p_gpio_bank c0;
> struct s5p_gpio_bank c1;
> struct s5p_gpio_bank c2;
> @@ -164,7 +166,7 @@ struct exynos5420_gpio_part3 {
> struct s5p_gpio_bank y6;
> };
>
> -struct exynos5420_gpio_part4 {
> +struct exynos5420_gpio_part5 {
> struct s5p_gpio_bank e0; /* 0x1400_0000 */
> struct s5p_gpio_bank e1; /* 0x1400_0020 */
> struct s5p_gpio_bank f0; /* 0x1400_0040 */
> @@ -175,7 +177,7 @@ struct exynos5420_gpio_part4 {
> struct s5p_gpio_bank j4; /* 0x1400_00E0 */
> };
>
> -struct exynos5420_gpio_part5 {
> +struct exynos5420_gpio_part6 {
> struct s5p_gpio_bank z0; /* 0x0386_0000 */
> };
>
> @@ -200,16 +202,20 @@ struct exynos5_gpio_part1 {
> struct s5p_gpio_bank y4;
> struct s5p_gpio_bank y5;
> struct s5p_gpio_bank y6;
> - struct s5p_gpio_bank res1[0x3];
> +};
> +
> +struct exynos5_gpio_part2 {
> struct s5p_gpio_bank c4;
> - struct s5p_gpio_bank res2[0x48];
> +};
> +
> +struct exynos5_gpio_part3 {
> struct s5p_gpio_bank x0;
> struct s5p_gpio_bank x1;
> struct s5p_gpio_bank x2;
> struct s5p_gpio_bank x3;
> };
>
> -struct exynos5_gpio_part2 {
> +struct exynos5_gpio_part4 {
> struct s5p_gpio_bank e0;
> struct s5p_gpio_bank e1;
> struct s5p_gpio_bank f0;
> @@ -221,20 +227,25 @@ struct exynos5_gpio_part2 {
> struct s5p_gpio_bank h1;
> };
>
> -struct exynos5_gpio_part3 {
> +struct exynos5_gpio_part5 {
> struct s5p_gpio_bank v0;
> struct s5p_gpio_bank v1;
> - struct s5p_gpio_bank res1[0x1];
> +};
> +
> +struct exynos5_gpio_part6 {
> struct s5p_gpio_bank v2;
> struct s5p_gpio_bank v3;
> - struct s5p_gpio_bank res2[0x1];
> +};
> +
> +struct exynos5_gpio_part7 {
> struct s5p_gpio_bank v4;
> };
>
> -struct exynos5_gpio_part4 {
> +struct exynos5_gpio_part8 {
> struct s5p_gpio_bank z;
> };
>
There are also unchanged gpios initializations in files:
- arndale/arndale.c line 19
- smdk5420/smdk5420.c line 45
Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions
2014-04-12 9:43 ` [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
@ 2014-04-14 15:15 ` Przemyslaw Marczak
1 sibling, 0 replies; 19+ messages in thread
From: Przemyslaw Marczak @ 2014-04-14 15:15 UTC (permalink / raw)
To: u-boot
Hi,
On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch rename GPIO definitions from GPIO_... to S5P_GPIO_...
> This changes was done to enable cmd_gpio for EXYNOS and
> cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
> getting a error during compilation.
>
> Build tested for s5p_goni, origen, smdk5250, s5pc210_universal,
> trats, smdkc100, smdkv310 config files.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Please check boards files: origen.c, trats.c and trats2.c,
there is still old gpio naming style.
Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
2014-04-12 9:43 ` [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5 Akshay Saraswat
2014-04-12 20:32 ` Simon Glass
@ 2014-04-14 15:19 ` Przemyslaw Marczak
1 sibling, 0 replies; 19+ messages in thread
From: Przemyslaw Marczak @ 2014-04-14 15:19 UTC (permalink / raw)
To: u-boot
Hi,
On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds support for name to gpio conversion in s5p_gpio
> to enable gpio command EXYNOS 5250 & 5420.
> Function has been added to asm/gpio.h to decode the
> input gpio name to gpio number.
>
> Example: SMDK5420 # gpio set gpa00
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---
> arch/arm/include/asm/arch-exynos/gpio.h | 28 +++++++++
> drivers/gpio/s5p_gpio.c | 105 ++++++++++++++++++++++++++++++++
> 2 files changed, 133 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
> index 697e6f3..3736a22 100644
> --- a/arch/arm/include/asm/arch-exynos/gpio.h
> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
> @@ -1038,6 +1038,34 @@ static inline unsigned int get_bank_num(void)
> }
> }
>
> +/*
> + * This structure helps mapping symbolic GPIO names into indices from
> + * exynos5_gpio_pin/exynos5420_gpio_pin enums.
> + *
> + * By convention, symbolic GPIO name is defined as follows:
> + *
> + * g[p]<bank><set><bit>, where
> + * p is optional
> + * <bank> - a single character bank name, as defined by the SOC
> + * <set> - a single digit set number
> + * <bit> - bit number within the set (in 0..7 range).
> + *
> + * <set><bit> essentially form an octal number of the GPIO pin within the bank
> + * space. On the 5420 architecture some banks' sets do not start not from zero
> + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
> + * maintain flat number space withoout holes, those banks use offsets to be
> + * deducted from the pin number.
> + */
> +struct gpio_name_num_table {
> + char bank; /* bank name symbol */
> + u8 bank_size; /* total number of pins in the bank */
> + char bank_offset; /* offset of the first bank's pin */
> + unsigned int base; /* index of the first bank's pin in the enum */
> +};
> +
> +int s5p_name_to_gpio(const char *name);
> +#define name_to_gpio(n) s5p_name_to_gpio(n)
> +
> void gpio_cfg_pin(int gpio, int cfg);
> void gpio_set_pull(int gpio, int mode);
> void gpio_set_drv(int gpio, int mode);
> diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
> index b1b6fbe..9a80b0c 100644
> --- a/drivers/gpio/s5p_gpio.c
> +++ b/drivers/gpio/s5p_gpio.c
> @@ -28,6 +28,111 @@
> #define RATE_MASK(x) (0x1 << (x + 16))
> #define RATE_SET(x) (0x1 << (x + 16))
>
This driver is common so you can't put here SOC specific code.
This is also the reason of build break for s5pc1xx architecture.
It should be initialized in arch/arm/include/asm/arch-exynos/gpio.h.
The same should be defined for Exynos4 and for s5pc1xx: in
arch/arm/include/asm/arch-s5pc1xx/gpio.h.
This also can require introduce a s5p_gpio.h header with structure
gpio_name_num_table. And maybe better name for this structure type is
gpio_name_to_num ?
> +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
> +static const struct gpio_name_num_table exynos5_gpio_table[] = {
> + GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
> + GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
> + GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
> + GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
> + GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
> + GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
> + GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
> + GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
> + GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
> + GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
> + GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
> + GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
> + { 0 }
> +};
> +
> +static const struct gpio_name_num_table exynos5420_gpio_table[] = {
> + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
> + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
> + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
> + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
> + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
> + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
> + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
> + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
> + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
> + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
> + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
> + GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
> + { 0 }
> +};
> +
> +int s5p_name_to_gpio(const char *name)
> +{
> + unsigned num, irregular_set_number, irregular_bank_base;
> + const struct gpio_name_num_table *tabp;
> + char this_bank, bank_name, irregular_bank_name;
> + char *endp;
> +
> + /*
> + * The gpio name starts with either 'g' ot 'gp' followed by the bank
> + * name character. Skip one or two characters depending on the prefix.
> + */
> + if (name[1] == 'p')
> + name += 2;
> + else
> + name++;
> + bank_name = *name++;
> + if (!*name)
> + return -1; /* At least one digit is required/expected. */
> +
> + /*
> + * On both exynos5 and exynos5420 architectures there is a bank of
> + * GPIOs which does not fall into the regular address pattern. Those
> + * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
> + * assignments help to handle these irregularities.
> + */
We can't check cpu id for s5pc1xx when exynos is compiled so you
shouldn't check proid in this driver, but you can do this in
arch-XXXX/gpio.h.
So then this is a still s5p common driver.
> + if (proid_is_exynos5420()) {
> + tabp = exynos5420_gpio_table;
> + irregular_bank_name = 'y';
> + irregular_set_number = '7';
> + irregular_bank_base = EXYNOS5420_GPIO_Y70;
> + } else {
> + tabp = exynos5_gpio_table;
> + irregular_bank_name = 'c';
> + irregular_set_number = '4';
> + irregular_bank_base = EXYNOS5_GPIO_C40;
> + }
> +
> + this_bank = tabp->bank;
> + do {
> + if (bank_name == this_bank) {
> + unsigned pin_index; /* pin number within the bank */
> + if ((bank_name == irregular_bank_name) &&
> + (name[0] == irregular_set_number)) {
> + pin_index = name[1] - '0';
> + /* Irregular sets have 8 pins. */
> + if (pin_index >= GPIO_PER_BANK)
> + return -1;
> + num = irregular_bank_base + pin_index;
> + } else {
> + pin_index = simple_strtoul(name, &endp, 8);
> + pin_index -= tabp->bank_offset;
> + /*
> + * Sanity check: bunk 'z' has no set number,
> + * for all other banks there must be exactly
> + * two octal digits, and the resulting number
> + * should not exceed the number of pins in the
> + * bank.
> + */
> + if (((bank_name != 'z') && !name[1]) ||
> + *endp ||
> + (pin_index >= tabp->bank_size))
> + return -1;
> + num = tabp->base + pin_index;
> + }
> + return num;
> + }
> + this_bank = (++tabp)->bank;
> + } while (this_bank);
> +
> + return -1;
> +}
> +
> void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
> {
> unsigned int value;
>
You made a lot of good job. Please just make this driver more common,
then I will implement and test this feature for exynos4 and s5pc1xx boards.
Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-14 15:15 ` Przemyslaw Marczak
@ 2014-04-14 15:59 ` Simon Glass
0 siblings, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-14 15:59 UTC (permalink / raw)
To: u-boot
Hi,
On 14 April 2014 09:15, Przemyslaw Marczak <p.marczak@samsung.com> wrote:
> Hello,
> I like this idea. This is a good feature for easy and fast gpio
> maintaining. I have few comments to this.
>
>
> On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
>
>> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>>
>> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
>> To have consistent 0..n-1 GPIO numbering the banks are divided
>> into different parts where ever they have holes in them.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> ---
>>
>
> You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05",
> maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5.
> So then we really know what we are using and I think this just looks
> better.
I'm not sure I agree with the idea of a more verbose naming. The naming in
this series fits better with the idea of numbered GPIOs. The bank number is
of limited interest to users of GPIOs anyway. Exynos is slightly odd in
that banks have both a letter and number (A0, A1), but that doesn't seem
like a reason to change.
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-14 14:40 ` Simon Glass
@ 2014-04-15 6:25 ` Lukasz Majewski
2014-04-17 4:21 ` Simon Glass
0 siblings, 1 reply; 19+ messages in thread
From: Lukasz Majewski @ 2014-04-15 6:25 UTC (permalink / raw)
To: u-boot
Hi Simon,
> Hi Lukasz,
>
> On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com>
> wrote:
>
> [snip[
>
> I think your questions are mostly answered but I wanted to chime in
> on a few.
>
> What is wrong with specifying the bank field?
> > Why your gpio command cannot use the bank approach?
> >
>
> U-Boot has a generic GPIO API and we should try to use it where
> possible. This has been a long-standing TODO for exynos.
I'm also fully aware that Exynos suffers from inconsistent gpio API.
However, I'm very glad that with Akshay's and our effort this goal
will be accomplished :-)
>
>
> >
> > And one more question: Is this work compliant with new driver model,
> > which will be accepted at the merge window after the v2014.04
> > release?
> >
> > If not, then there is no point to review this code, since GPIO would
> > need to be adjusted to use this framework.
> >
>
> The driver model framework is already in mainline.
I was rather thinking about the "big switch" as we did with KBUILD
after the v2014.01. Anyway, I'm looking forward to see the wide
deployment of device model in u-boot.
> At present only
> sandbox uses it for GPIO. I started looking at exynos since I thought
> it might be quite easy to convert, but found that the generic GPIO
> stuff was still not merged.
>
> This series will make it much easier to convert exynos GPIO to driver
> model, since we can just change the driver.
Thanks for clarification.
>
> Regards,
> Simon
>
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature
2014-04-15 6:25 ` Lukasz Majewski
@ 2014-04-17 4:21 ` Simon Glass
0 siblings, 0 replies; 19+ messages in thread
From: Simon Glass @ 2014-04-17 4:21 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
On 14 April 2014 23:25, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Hi Simon,
>
> > Hi Lukasz,
> >
> > On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com>
> > wrote:
> >
> > [snip[
> >
> > I think your questions are mostly answered but I wanted to chime in
> > on a few.
> >
> > What is wrong with specifying the bank field?
> > > Why your gpio command cannot use the bank approach?
> > >
> >
> > U-Boot has a generic GPIO API and we should try to use it where
> > possible. This has been a long-standing TODO for exynos.
>
> I'm also fully aware that Exynos suffers from inconsistent gpio API.
> However, I'm very glad that with Akshay's and our effort this goal
> will be accomplished :-)
>
> >
> >
> > >
> > > And one more question: Is this work compliant with new driver model,
> > > which will be accepted at the merge window after the v2014.04
> > > release?
> > >
> > > If not, then there is no point to review this code, since GPIO would
> > > need to be adjusted to use this framework.
> > >
> >
> > The driver model framework is already in mainline.
>
> I was rather thinking about the "big switch" as we did with KBUILD
> after the v2014.01. Anyway, I'm looking forward to see the wide
> deployment of device model in u-boot.
>
I don't expect a big switch. Each subsystem needs to add support for it,
and then (as a separate step) each driver needs to be ported into the new
uclass. So it will likely be an incremental effort.
> > At present only
> > sandbox uses it for GPIO. I started looking at exynos since I thought
> > it might be quite easy to convert, but found that the generic GPIO
> > stuff was still not merged.
> >
> > This series will make it much easier to convert exynos GPIO to driver
> > model, since we can just change the driver.
>
> Thanks for clarification.
>
I'm probably going to take a look at Tegra while waiting for this series to
land. Let's see how it goes.
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2014-04-17 4:21 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-04-12 9:43 [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Akshay Saraswat
2014-04-12 9:43 ` [U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin " Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
2014-04-14 7:17 ` Lukasz Majewski
2014-04-14 14:40 ` Simon Glass
2014-04-15 6:25 ` Lukasz Majewski
2014-04-17 4:21 ` Simon Glass
2014-04-14 15:15 ` Przemyslaw Marczak
2014-04-14 15:59 ` Simon Glass
2014-04-12 9:43 ` [U-Boot] [PATCH v6 2/4] S5P: Rename GPIO definitions Akshay Saraswat
2014-04-12 20:30 ` Simon Glass
2014-04-14 15:15 ` Przemyslaw Marczak
2014-04-12 9:43 ` [U-Boot] [PATCH v6 3/4] EXYNOS5: GPIO: Support GPIO Command for EXYNOS5 Akshay Saraswat
2014-04-12 20:32 ` Simon Glass
2014-04-14 15:19 ` Przemyslaw Marczak
2014-04-12 9:43 ` [U-Boot] [PATCH v6 4/4] Config: Exynos5: Enable Generic GPIO and CMD configs Akshay Saraswat
2014-04-12 20:33 ` Simon Glass
2014-04-12 20:39 ` Simon Glass
2014-04-14 9:31 ` [U-Boot] [PATCH v6 0/4] Exynos5: Add GPIO numbering feature Przemyslaw Marczak
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