[PATCH 00/29] ARM: orion5x: big step towards DT conversion

[PATCH 00/29] ARM: orion5x: big step towards DT conversion

[Thomas Petazzoni]

Hello,

This set of patches make a big step towards converting mach-orion5x to
use the Device Tree: one board (edmini_v2) is fully converted and two
other boards are almost fully converted (rd88f5182 and d2-net).

Summary of the patches:

 * PATCH 1 is a fix for a MBus window target ID that was wrong since
   v3.12, so it should be pushed to stable.

 * PATCH 2 adds the Orion pinctrl driver.

 * PATCH 3 adds the Orion clock driver.

 * PATCH 4 to 7 adds Orion support to the mvebu-devbus driver. PATCH 4
   was already sent as a fix for the mvebu-devbus driver.

 * PATCH 5 to 19 improve the DT conversion of Orion5x, by converting
   it to use the MBus DT binding, the pinctrl, timer described in the
   Device Tree, etc.

 * PATCH 20 to 25 finish the conversion of the edmini_v2 platform to
   Device Tree.

 * PATCH 26 and 27 convert two other platforms to the Device Tree.

 * PATCH 28 and 29 remove some code in plat-orion/ that is now useless
   after this patch series.

This code has been test on Marvell RD-88F5182 and LaCie edmini_v2. The
conversion of LaCie d2-net was done without testing, due to the lack
of hardware.

This set of patches is based on the latest Linus master (so it should
be closed to something based on the upcoming 3.15-rc1), and it also
available at:

  https://github.com/MISL-EBU-System-SW/mainline-public/tree/3.15/orion

Review, comments, testing welcome.

Thanks!

Thomas

Thomas Petazzoni (29):
  ARM: orion5x: fix target ID for crypto SRAM window
  pinctrl: mvebu: new driver for Orion platforms
  clk: mvebu: add Orion5x clock driver
  memory: mvebu-devbus: fix the conversion of the bus width
  memory: mvebu-devbus: use ARMADA_ prefix in defines
  memory: mvebu-devbus: split functions
  memory: mvebu-devbus: add Orion5x support
  ARM: orion5x: move interrupt controller node into ocp
  ARM: orion5x: switch to preprocessor includes in DT
  ARM: orion5x: use existing dt-bindings include for Device Tree files
  ARM: orion5x: convert DT to use the mvebu-mbus driver
  ARM: orion5x: add interrupt for Ethernet in Device Tree
  ARM: orion5x: switch to use the clock driver for DT platforms
  ARM: orion: switch to a per-platform handle_irq() function
  ARM: orion5x: switch to DT interrupts and timer
  ARM: orion5x: enable pinctrl driver at SoC level
  ARM: orion5x: update I2C description at SoC level
  ARM: orion5x: add Device Bus description at SoC level
  ARM: orion5x: add standard pinctrl configs for sata0 and sata1
  ARM: orion5x: convert edmini_v2 to DT pinctrl
  ARM: orion5x: use DT to describe I2C devices on edmini_v2
  ARM: orion5x: use DT to describe EHCI on edmini_v2
  ARM: orion5x: use DT to describe NOR on edmini_v2
  ARM: orion5x: keep TODO list in edmini_v2 DT
  ARM: orion5x: remove unneeded code for edmini_v2
  ARM: orion5x: convert RD-88F5182 to Device Tree
  ARM: orion5x: convert d2net to Device Tree
  ARM: orion: remove no longer needed DT IRQ code
  ARM: orion: remove no longer needed gpio DT code

 .../devicetree/bindings/clock/mvebu-core-clock.txt |   8 +
 .../bindings/memory-controllers/mvebu-devbus.txt   |  25 +-
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  91 +++++
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/orion5x-lacie-d2-network.dts     | 234 +++++++++++++
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 128 +++++++-
 arch/arm/boot/dts/orion5x-mv88f5182.dtsi           |  45 +++
 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts        | 155 +++++++++
 arch/arm/boot/dts/orion5x.dtsi                     | 287 +++++++++-------
 arch/arm/mach-dove/irq.c                           |  36 ++
 arch/arm/mach-kirkwood/irq.c                       |  36 ++
 arch/arm/mach-orion5x/Kconfig                      |  32 +-
 arch/arm/mach-orion5x/Makefile                     |   5 +-
 arch/arm/mach-orion5x/board-d2net.c                | 109 ++++++
 arch/arm/mach-orion5x/board-dt.c                   |  23 +-
 arch/arm/mach-orion5x/board-rd88f5182.c            | 116 +++++++
 arch/arm/mach-orion5x/common.h                     |   9 +-
 arch/arm/mach-orion5x/d2net-setup.c                | 365 ---------------------
 arch/arm/mach-orion5x/edmini_v2-setup.c            | 169 ----------
 arch/arm/mach-orion5x/irq.c                        |  28 ++
 arch/arm/plat-orion/gpio.c                         |  48 ---
 arch/arm/plat-orion/include/plat/irq.h             |   1 -
 arch/arm/plat-orion/include/plat/orion-gpio.h      |   1 -
 arch/arm/plat-orion/irq.c                          |  77 -----
 drivers/clk/mvebu/Kconfig                          |   4 +
 drivers/clk/mvebu/Makefile                         |   1 +
 drivers/clk/mvebu/orion.c                          | 212 ++++++++++++
 drivers/memory/mvebu-devbus.c                      | 209 ++++++++----
 drivers/pinctrl/mvebu/Kconfig                      |   4 +
 drivers/pinctrl/mvebu/Makefile                     |   1 +
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 261 +++++++++++++++
 31 files changed, 1830 insertions(+), 894 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/orion5x-lacie-d2-network.dts
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5182.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
 create mode 100644 arch/arm/mach-orion5x/board-d2net.c
 create mode 100644 arch/arm/mach-orion5x/board-rd88f5182.c
 delete mode 100644 arch/arm/mach-orion5x/d2net-setup.c
 delete mode 100644 arch/arm/mach-orion5x/edmini_v2-setup.c
 create mode 100644 drivers/clk/mvebu/orion.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-orion.c

-- 
1.8.3.2

[PATCH 01/29] ARM: orion5x: fix target ID for crypto SRAM window

[Thomas Petazzoni]

In commit 4ca2c04085a1caa903e92a5fc0da25362150aac2 ('ARM: orion5x:
Move to ID based window creation'), the mach-orion5x code was changed
to use the new mvebu-mbus API. However, in the process, a mistake was
made on the crypto SRAM window target ID: it should have been 0x9
(verified in the datasheet) and not 0x0.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: stable at vger.kernel.org
---
This should be backported to stable all the way to v3.12.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-orion5x/common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index f565f99..7548db2 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -21,7 +21,7 @@ struct mv_sata_platform_data;
 #define ORION_MBUS_DEVBUS_BOOT_ATTR   0x0f
 #define ORION_MBUS_DEVBUS_TARGET(cs)  0x01
 #define ORION_MBUS_DEVBUS_ATTR(cs)    (~(1 << cs))
-#define ORION_MBUS_SRAM_TARGET        0x00
+#define ORION_MBUS_SRAM_TARGET        0x09
 #define ORION_MBUS_SRAM_ATTR          0x00
 
 /*
-- 
1.8.3.2

[PATCH 02/29] pinctrl: mvebu: new driver for Orion platforms

[Thomas Petazzoni]

This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  91 +++++++
 drivers/pinctrl/mvebu/Kconfig                      |   4 +
 drivers/pinctrl/mvebu/Makefile                     |   1 +
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 261 +++++++++++++++++++++
 4 files changed, 357 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-orion.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
new file mode 100644
index 0000000..1748209
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -0,0 +1,91 @@
+* Marvell Orion SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
+              "marvell,88f5281-pinctrl"
+
+- reg: two register areas, the first one describing the first two
+  contiguous MPP registers, and the second one describing the single
+  final MPP register, separated from the previous one.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Orion 88f5181l
+
+name          pins     functions
+================================================================================
+mpp0          0        pci(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4)
+mpp5          5        gpio, pci(gnt4)
+mpp6          6        gpio, pci(req5), pci(clk)
+mpp7          7        gpio, pci(gnt5), pci(clk)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4)
+mpp13         13       gpio, ge(txd5)
+mpp14         14       gpio, ge(txd6)
+mpp15         15       gpio, ge(txd7)
+mpp16         16       ge(rxd4)
+mpp17         17       ge(rxd5)
+mpp18         18       ge(rxd6)
+mpp19         19       ge(rxd7)
+
+* Marvell Orion 88f5182
+
+name          pins     functions
+================================================================================
+mpp0          0        pci(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
+mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
+mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
+mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
+mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
+mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
+mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)
+mpp16         16       uart1(rxd), ge(rxd4), gpio
+mpp17         17       uart1(txd), ge(rxd5), gpio
+mpp18         18       uart1(cts), ge(rxd6), gpio
+mpp19         19       uart1(rts), ge(rxd7), gpio
+
+* Marvell Orion 88f5281
+
+name          pins     functions
+================================================================================
+mpp0          0        pci(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4), bootnand(re)
+mpp5          5        gpio, pci(gnt4), bootnand(we)
+mpp6          6        gpio, pci(req5), nand(re0)
+mpp7          7        gpio, pci(gnt5), nand(we0)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4), nand(re1)
+mpp13         13       gpio, ge(txd5), nand(we1)
+mpp14         14       gpio, ge(txd6), nand(re2)
+mpp15         15       gpio, ge(txd7), nand(we2)
+mpp16         16       uart1(rxd), ge(rxd4)
+mpp17         17       uart1(txd), ge(rxd5)
+mpp18         18       uart1(cts), ge(rxd6)
+mpp19         19       uart1(rts), ge(rxd7)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index cc298fad..d6dd835 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -30,4 +30,8 @@ config PINCTRL_ARMADA_XP
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ORION
+	bool
+	select PINCTRL_MVEBU
+
 endif
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index bc1b9f1..a0818e9 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
+obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
new file mode 100644
index 0000000..8312fb3
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -0,0 +1,261 @@
+/*
+ * Marvell Orion pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The first 16 MPP pins on Orion are easy to handle: they are
+ * configured through 2 consecutive registers, located at the base
+ * address of the MPP device.
+ *
+ * However the last 4 MPP pins are handled by a register at offset
+ * 0x50 from the base address, so it is not consecutive with the first
+ * two registers.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static void __iomem *mpp_base;
+static void __iomem *high_mpp_base;
+
+static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config)
+{
+	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+
+	if (pid < 16) {
+		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+		*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
+	}
+	else {
+		*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
+	}
+
+	return 0;
+}
+
+static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
+{
+	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+
+	if (pid < 16) {
+		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+		u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
+		writel(reg | (config << shift), mpp_base + off);
+	}
+	else {
+		u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
+		writel(reg | (config << shift), high_mpp_base);
+	}
+
+	return 0;
+}
+
+#define V(f5181l, f5182, f5281) \
+	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+
+enum orion_variant {
+	V_5181L = V(1, 0, 0),
+	V_5182  = V(0, 1, 0),
+	V_5281  = V(0, 0, 1),
+	V_ALL   = V(1, 1, 1),
+};
+
+static struct mvebu_mpp_mode orion_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0x0, "pci", "rstout",     V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req2",       V_ALL),
+		 MPP_VAR_FUNCTION(0x3, "gpio", NULL,        V_ALL)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt2",       V_ALL)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req3",       V_ALL),
+		 MPP_VAR_FUNCTION(0x3, "pci", "pme",        V_ALL)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt3",       V_ALL)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req4",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "bootnand", "re",    V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",    V_5182)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt4",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "bootnand", "we",    V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",    V_5182)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "pci", "clk",        V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "pci", "clk",        V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "col",         V_ALL)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxerr",       V_ALL)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "crs",         V_ALL)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txerr",       V_ALL)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd4",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re1",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd5",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we1",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd6",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re2",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "ledact",   V_5182)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd7",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we2",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "ledact",   V_5182)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "rxd",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd4",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "txd",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd5",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "cts",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd6",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "rts",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd7",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+};
+
+static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 16),
+};
+
+static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 19),
+};
+
+static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 16),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
+	.variant = V_5181L,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5181l_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5182_info = {
+	.variant = V_5182,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5182_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5281_info = {
+	.variant = V_5281,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5281_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
+};
+
+/*
+ * There are multiple variants of the Orion SoCs, but in terms of pin
+ * muxing, they are identical.
+ */
+static struct of_device_id orion_pinctrl_of_match[] = {
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
+	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
+	{ }
+};
+
+static int orion_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match =
+		of_match_device(orion_pinctrl_of_match, &pdev->dev);
+	struct resource *res;
+
+	pdev->dev.platform_data = (void*) match->data;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mpp_base))
+		return PTR_ERR(mpp_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(high_mpp_base))
+		return PTR_ERR(high_mpp_base);
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int orion_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver orion_pinctrl_driver = {
+	.driver = {
+		.name = "orion-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_pinctrl_of_match),
+	},
+	.probe = orion_pinctrl_probe,
+	.remove = orion_pinctrl_remove,
+};
+
+module_platform_driver(orion_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.8.3.2

[PATCH 03/29] clk: mvebu: add Orion5x clock driver

[Thomas Petazzoni]

This commit adds a core clock driver for the Orion5x SoC, with support
for the tclk, the CPU frequency and the DDR frequency. All the details
about the Sample-At-Reset register were extracted from the U-Boot
sources for Orion5x.

Note that Orion5x does not have gatable clocks, so this core clock
driver is sufficient to support clocking on Orion5x platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   8 +
 drivers/clk/mvebu/Kconfig                          |   4 +
 drivers/clk/mvebu/Makefile                         |   1 +
 drivers/clk/mvebu/orion.c                          | 212 +++++++++++++++++++++
 4 files changed, 225 insertions(+)
 create mode 100644 drivers/clk/mvebu/orion.c

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 307a503..dc5ea5b 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
  2 = l2clk  (L2 Cache clock derived from CPU0 clock)
  3 = ddrclk (DDR controller clock derived from CPU0 clock)
 
+The following is a list of provided IDs and clock names on Orion5x:
+ 0 = tclk   (Internal Bus clock)
+ 1 = cpuclk (CPU0 clock)
+ 2 = ddrclk (DDR controller clock derived from CPU0 clock)
+
 Required properties:
 - compatible : shall be one of the following:
 	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
@@ -38,6 +43,9 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
+	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
+	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
 - reg : shall be the register address of the Sample-At-Reset (SAR) register
 - #clock-cells : from common clock binding; shall be set to 1
 
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 693f7be..3b34dba 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -34,3 +34,7 @@ config DOVE_CLK
 config KIRKWOOD_CLK
 	bool
 	select MVEBU_CLK_COMMON
+
+config ORION_CLK
+	bool
+	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 4c66162..a9a56fc 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o
 obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
+obj-$(CONFIG_ORION_CLK)		+= orion.o
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
new file mode 100644
index 0000000..005aa2f
--- /dev/null
+++ b/drivers/clk/mvebu/orion.c
@@ -0,0 +1,212 @@
+/*
+ * Marvell Orion SoC clocks
+ *
+ * Copyright (C) 2014 Thomas Petazzoni
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
+	{ .id = 0, .name = "ddrclk", }
+};
+
+/*
+ * Orion 5182
+ */
+
+#define SAR_MV88F5182_TCLK_FREQ      0x8
+#define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
+		SAR_MV88F5182_TCLK_FREQ_MASK;
+	if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5182_CPU_FREQ       0x4
+#define SAR_MV88F5182_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
+		SAR_MV88F5182_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1)
+		return 400000000;
+	else if (opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
+		SAR_MV88F5182_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5182_coreclks = {
+	.get_tclk_freq = mv88f5182_get_tclk_freq,
+	.get_cpu_freq = mv88f5182_get_cpu_freq,
+	.get_clk_ratio = mv88f5182_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5182_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
+
+/*
+ * Orion 5281
+ */
+
+static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
+{
+	/* On 5281, tclk is always 166 Mhz */
+	return 166666667;
+}
+
+#define SAR_MV88F5281_CPU_FREQ       0x4
+#define SAR_MV88F5281_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
+		SAR_MV88F5281_CPU_FREQ_MASK;
+	if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
+		SAR_MV88F5281_CPU_FREQ_MASK;
+	if (opt == 1) {
+		*mult = 1;
+		*div = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div = 3;
+	} else {
+		*mult = 0;
+		*div = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5281_coreclks = {
+	.get_tclk_freq = mv88f5281_get_tclk_freq,
+	.get_cpu_freq = mv88f5281_get_cpu_freq,
+	.get_clk_ratio = mv88f5281_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5281_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
+
+/*
+ * Orion 6183
+ */
+
+#define SAR_MV88F6183_TCLK_FREQ      0x9
+#define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
+
+static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
+		SAR_MV88F6183_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F6183_CPU_FREQ       0x1
+#define SAR_MV88F6183_CPU_FREQ_MASK  0x3f
+
+static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
+		SAR_MV88F6183_CPU_FREQ_MASK;
+	if (opt == 9)
+		return 333333333;
+	else if (opt == 17)
+		return 400000000;
+	else
+		return 0;
+}
+
+static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
+		SAR_MV88F6183_CPU_FREQ_MASK;
+	if (opt == 9 || opt == 17) {
+		*mult = 1;
+		*div  = 2;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f6183_coreclks = {
+	.get_tclk_freq = mv88f6183_get_tclk_freq,
+	.get_cpu_freq = mv88f6183_get_cpu_freq,
+	.get_clk_ratio = mv88f6183_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+
+static void __init mv88f6183_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);
-- 
1.8.3.2

[PATCH 04/29] memory: mvebu-devbus: fix the conversion of the bus width

[Thomas Petazzoni]

According to the Armada 370 and Armada XP datasheets, the part of the
Device Bus register that configure the bus width should contain 0 for
a 8 bits bus width, and 1 for a 16 bits bus width (other values are
unsupported/reserved).

However, the current conversion done in the driver to convert from a
bus width in bits to the value expected by the register leads to
setting the register to 1 for a 8 bits bus, and 2 for a 16 bits bus.

This commit fixes that by adjusting the conversion logic.

This patch fixes a bug that was introduced in
3edad321b1bd2e6c8b5f38146c115c8982438f06 ('drivers: memory: Introduce
Marvell EBU Device Bus driver'), which was merged in v3.11.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: stable at vger.kernel.org
---
 drivers/memory/mvebu-devbus.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 110c036..b82cdf1 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -108,8 +108,12 @@ static int devbus_set_timing_params(struct devbus *devbus,
 			node->full_name);
 		return err;
 	}
-	/* Convert bit width to byte width */
-	r.bus_width /= 8;
+
+	/*
+	 * The bus width is encoded into the register as 0 for 8 bits,
+	 * and 1 for 16 bits, so we do the necessary conversion here.
+	 */
+	r.bus_width = (r.bus_width / 8) - 1;
 
 	err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
 				 &r.badr_skew);
-- 
1.8.3.2

[PATCH 05/29] memory: mvebu-devbus: use ARMADA_ prefix in defines

[Thomas Petazzoni]

The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the register. Therefore, in
preparation to the introduction of Orion5x support, we rename the
Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index b82cdf1..84746e3 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -30,19 +30,19 @@
 #include <linux/platform_device.h>
 
 /* Register definitions */
-#define DEV_WIDTH_BIT		30
-#define BADR_SKEW_BIT		28
-#define RD_HOLD_BIT		23
-#define ACC_NEXT_BIT		17
-#define RD_SETUP_BIT		12
-#define ACC_FIRST_BIT		6
+#define ARMADA_DEV_WIDTH_BIT		30
+#define ARMADA_BADR_SKEW_BIT		28
+#define ARMADA_RD_HOLD_BIT		23
+#define ARMADA_ACC_NEXT_BIT		17
+#define ARMADA_RD_SETUP_BIT		12
+#define ARMADA_ACC_FIRST_BIT		6
 
-#define SYNC_ENABLE_BIT		24
-#define WR_HIGH_BIT		16
-#define WR_LOW_BIT		8
+#define ARMADA_SYNC_ENABLE_BIT		24
+#define ARMADA_WR_HIGH_BIT		16
+#define ARMADA_WR_LOW_BIT		8
 
-#define READ_PARAM_OFFSET	0x0
-#define WRITE_PARAM_OFFSET	0x4
+#define ARMADA_READ_PARAM_OFFSET	0x0
+#define ARMADA_WRITE_PARAM_OFFSET	0x4
 
 struct devbus_read_params {
 	u32 bus_width;
@@ -171,31 +171,31 @@ static int devbus_set_timing_params(struct devbus *devbus,
 		return err;
 
 	/* Set read timings */
-	value = r.bus_width << DEV_WIDTH_BIT |
-		r.badr_skew << BADR_SKEW_BIT |
-		r.rd_hold   << RD_HOLD_BIT   |
-		r.acc_next  << ACC_NEXT_BIT  |
-		r.rd_setup  << RD_SETUP_BIT  |
-		r.acc_first << ACC_FIRST_BIT |
+	value = r.bus_width << ARMADA_DEV_WIDTH_BIT |
+		r.badr_skew << ARMADA_BADR_SKEW_BIT |
+		r.rd_hold   << ARMADA_RD_HOLD_BIT   |
+		r.acc_next  << ARMADA_ACC_NEXT_BIT  |
+		r.rd_setup  << ARMADA_RD_SETUP_BIT  |
+		r.acc_first << ARMADA_ACC_FIRST_BIT |
 		r.turn_off;
 
 	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
-		devbus->base + READ_PARAM_OFFSET,
+		devbus->base + ARMADA_READ_PARAM_OFFSET,
 		value);
 
-	writel(value, devbus->base + READ_PARAM_OFFSET);
+	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
 
 	/* Set write timings */
-	value = w.sync_enable  << SYNC_ENABLE_BIT |
-		w.wr_low       << WR_LOW_BIT      |
-		w.wr_high      << WR_HIGH_BIT     |
+	value = w.sync_enable  << ARMADA_SYNC_ENABLE_BIT |
+		w.wr_low       << ARMADA_WR_LOW_BIT      |
+		w.wr_high      << ARMADA_WR_HIGH_BIT     |
 		w.ale_wr;
 
 	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
-		devbus->base + WRITE_PARAM_OFFSET,
+		devbus->base + ARMADA_WRITE_PARAM_OFFSET,
 		value);
 
-	writel(value, devbus->base + WRITE_PARAM_OFFSET);
+	writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
 
 	return 0;
 }
-- 
1.8.3.2

[PATCH 06/29] memory: mvebu-devbus: split functions

[Thomas Petazzoni]

The mvebu-devbus driver currently only supports the Armada 370/XP
family, but it can also cover the Orion5x family. However, the Orion5x
family has a different organization of the registers.

Therefore, in preparation to the introduction of Orion5x support, we
separate into two functions the code that 1/ retrieves the timing
parameters from the Device Tree and 2/ applies those timings
parameters into the hardware registers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/memory/mvebu-devbus.c | 82 +++++++++++++++++++++++++------------------
 1 file changed, 47 insertions(+), 35 deletions(-)

diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 84746e3..8df5b2b 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -89,19 +89,15 @@ static int get_timing_param_ps(struct devbus *devbus,
 	return 0;
 }
 
-static int devbus_set_timing_params(struct devbus *devbus,
-				    struct device_node *node)
+static int devbus_get_timing_params(struct devbus *devbus,
+				    struct device_node *node,
+				    struct devbus_read_params *r,
+				    struct devbus_write_params *w)
 {
-	struct devbus_read_params r;
-	struct devbus_write_params w;
-	u32 value;
 	int err;
 
-	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
-		devbus->tick_ps);
-
 	/* Get read timings */
-	err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
+	err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
 	if (err < 0) {
 		dev_err(devbus->dev,
 			"%s has no 'devbus,bus-width' property\n",
@@ -113,41 +109,41 @@ static int devbus_set_timing_params(struct devbus *devbus,
 	 * The bus width is encoded into the register as 0 for 8 bits,
 	 * and 1 for 16 bits, so we do the necessary conversion here.
 	 */
-	r.bus_width = (r.bus_width / 8) - 1;
+	r->bus_width = (r->bus_width / 8) - 1;
 
 	err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
-				 &r.badr_skew);
+				 &r->badr_skew);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
-				 &r.turn_off);
+				 &r->turn_off);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
-				 &r.acc_first);
+				 &r->acc_first);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
-				 &r.acc_next);
+				 &r->acc_next);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
-				 &r.rd_setup);
+				 &r->rd_setup);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
-				 &r.rd_hold);
+				 &r->rd_hold);
 	if (err < 0)
 		return err;
 
 	/* Get write timings */
 	err = of_property_read_u32(node, "devbus,sync-enable",
-				  &w.sync_enable);
+				  &w->sync_enable);
 	if (err < 0) {
 		dev_err(devbus->dev,
 			"%s has no 'devbus,sync-enable' property\n",
@@ -156,28 +152,38 @@ static int devbus_set_timing_params(struct devbus *devbus,
 	}
 
 	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
-				 &w.ale_wr);
+				 &w->ale_wr);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
-				 &w.wr_low);
+				 &w->wr_low);
 	if (err < 0)
 		return err;
 
 	err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
-				 &w.wr_high);
+				 &w->wr_high);
 	if (err < 0)
 		return err;
 
+	return 0;
+}
+
+static void devbus_armada_set_timing_params(struct devbus *devbus,
+					   struct device_node *node,
+					   struct devbus_read_params *r,
+					   struct devbus_write_params *w)
+{
+	u32 value;
+
 	/* Set read timings */
-	value = r.bus_width << ARMADA_DEV_WIDTH_BIT |
-		r.badr_skew << ARMADA_BADR_SKEW_BIT |
-		r.rd_hold   << ARMADA_RD_HOLD_BIT   |
-		r.acc_next  << ARMADA_ACC_NEXT_BIT  |
-		r.rd_setup  << ARMADA_RD_SETUP_BIT  |
-		r.acc_first << ARMADA_ACC_FIRST_BIT |
-		r.turn_off;
+	value = r->bus_width << ARMADA_DEV_WIDTH_BIT |
+		r->badr_skew << ARMADA_BADR_SKEW_BIT |
+		r->rd_hold   << ARMADA_RD_HOLD_BIT   |
+		r->acc_next  << ARMADA_ACC_NEXT_BIT  |
+		r->rd_setup  << ARMADA_RD_SETUP_BIT  |
+		r->acc_first << ARMADA_ACC_FIRST_BIT |
+		r->turn_off;
 
 	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
 		devbus->base + ARMADA_READ_PARAM_OFFSET,
@@ -186,24 +192,24 @@ static int devbus_set_timing_params(struct devbus *devbus,
 	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
 
 	/* Set write timings */
-	value = w.sync_enable  << ARMADA_SYNC_ENABLE_BIT |
-		w.wr_low       << ARMADA_WR_LOW_BIT      |
-		w.wr_high      << ARMADA_WR_HIGH_BIT     |
-		w.ale_wr;
+	value = w->sync_enable  << ARMADA_SYNC_ENABLE_BIT |
+		w->wr_low       << ARMADA_WR_LOW_BIT      |
+		w->wr_high      << ARMADA_WR_HIGH_BIT     |
+		w->ale_wr;
 
 	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
 		devbus->base + ARMADA_WRITE_PARAM_OFFSET,
 		value);
 
 	writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
-
-	return 0;
 }
 
 static int mvebu_devbus_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *node = pdev->dev.of_node;
+	struct devbus_read_params r;
+	struct devbus_write_params w;
 	struct devbus *devbus;
 	struct resource *res;
 	struct clk *clk;
@@ -233,11 +239,17 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
 	rate = clk_get_rate(clk) / 1000;
 	devbus->tick_ps = 1000000000 / rate;
 
-	/* Read the device tree node and set the new timing parameters */
-	err = devbus_set_timing_params(devbus, node);
+	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
+		devbus->tick_ps);
+
+	/* Read the Device Tree node */
+	err = devbus_get_timing_params(devbus, node, &r, &w);
 	if (err < 0)
 		return err;
 
+	/* Set the new timing parameters */
+	devbus_armada_set_timing_params(devbus, node, &r, &w);
+
 	/*
 	 * We need to create a child device explicitly from here to
 	 * guarantee that the child will be probed after the timing
-- 
1.8.3.2

[PATCH 07/29] memory: mvebu-devbus: add Orion5x support

[Thomas Petazzoni]

This commit adds support for the Orion5x family of Marvell processors
into the mvebu-devbus driver. It differs from the already supported
Armada 370/XP by:

 * Having a single register (instead of two) for doing all the timing
   configuration.

 * Having a few less timing configuration parameters.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../bindings/memory-controllers/mvebu-devbus.txt   | 25 ++++--
 drivers/memory/mvebu-devbus.c                      | 95 +++++++++++++++++-----
 2 files changed, 94 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
index 653c90c..aff8e9e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
@@ -6,10 +6,11 @@ The actual devices are instantiated from the child nodes of a Device Bus node.
 
 Required properties:
 
- - compatible:          Currently only Armada 370/XP SoC are supported,
-                        with this compatible string:
+ - compatible:          Armada 370/XP SoC are supported using the
+                        "marvell,mvebu-devbus" compatible string.
 
-                        marvell,mvebu-devbus
+                        Orion5x SoC are supported using the
+                        "marvell,orion-devbus" compatible string.
 
  - reg:                 A resource specifier for the register space.
                         This is the base address of a chip select within
@@ -22,7 +23,7 @@ Required properties:
                         integer values for each chip-select line in use:
                         0 <physical address of mapping> <size>
 
-Mandatory timing properties for child nodes:
+Timing properties for child nodes:
 
 Read parameters:
 
@@ -30,21 +31,26 @@ Read parameters:
                         drive the AD bus after the completion of a device read.
                         This prevents contentions on the Device Bus after a read
                         cycle from a slow device.
+			Mandatory.
 
- - devbus,bus-width:    Defines the bus width (e.g. <16>)
+ - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
+   			Mandatory.
 
  - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
                         to read data sample. This parameter is useful for
                         synchronous pipelined devices, where the address
                         precedes the read data by one or two cycles.
+			Mandatory.
 
  - devbus,acc-first-ps: Defines the time delay from the negation of
                         ALE[0] to the cycle that the first read data is sampled
                         by the controller.
+			Mandatory.
 
  - devbus,acc-next-ps:  Defines the time delay between the cycle that
                         samples data N and the cycle that samples data N+1
                         (in burst accesses).
+			Mandaory.
 
  - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
 			DEV_OEn assertion. If set to 0 (default),
@@ -52,6 +58,8 @@ Read parameters:
                         This parameter has no affect on <acc-first-ps> parameter
                         (no affect on first data sample). Set <rd-setup-ps>
                         to a value smaller than <acc-first-ps>.
+			Mandatory with "mvebu-devbus" compatible string.
+			Ignored otherwise.
 
  - devbus,rd-hold-ps:   Defines the time between the last data sample to the
 			de-assertion of DEV_CSn. If set to 0 (default),
@@ -62,16 +70,20 @@ Read parameters:
                         last data sampled. Also this parameter has no
                         affect on <turn-off-ps> parameter.
                         Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
+			Mandatory with "mvebu-devbus" compatible string.
+			Ignored otherwise.
 
 Write parameters:
 
  - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
 			to the DEV_WEn assertion.
+			Mandatory.
 
  - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
                         A[2:0] and Data are kept valid as long as DEV_WEn
                         is active. This parameter defines the setup time of
                         address and data to DEV_WEn rise.
+			Mandatory.
 
  - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
                         inactive (high) between data beats of a burst write.
@@ -79,10 +91,13 @@ Write parameters:
                         <wr-high-ps> - <tick> ps.
 			This parameter defines the hold time of address and
 			data after DEV_WEn rise.
+			Mandatory.
 
  - devbus,sync-enable: Synchronous device enable.
                        1: True
                        0: False
+		       Mandatory with "mvebu-devbus" compatible string.
+		       Ignored otherwise.
 
 An example for an Armada XP GP board, with a 16 MiB NOR device as child
 is showed below. Note that the Device Bus driver is in charge of allocating
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 8df5b2b..59d8151 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -2,7 +2,7 @@
  * Marvell EBU SoC Device Bus Controller
  * (memory controller for NOR/NAND/SRAM/FPGA devices)
  *
- * Copyright (C) 2013 Marvell
+ * Copyright (C) 2013-2014 Marvell
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -44,6 +44,22 @@
 #define ARMADA_READ_PARAM_OFFSET	0x0
 #define ARMADA_WRITE_PARAM_OFFSET	0x4
 
+#define ORION_RESERVED			(0x2 << 30)
+#define ORION_BADR_SKEW_BIT		28
+#define ORION_WR_HIGH_EXT_BIT		27
+#define ORION_WR_LOW_EXT_BIT		26
+#define ORION_ALE_WR_EXT_BIT		25
+#define ORION_ACC_NEXT_EXT_BIT		24
+#define ORION_ACC_FIRST_EXT_BIT		23
+#define ORION_TURN_OFF_EXT_BIT		22
+#define ORION_DEV_WIDTH_BIT		20
+#define ORION_WR_HIGH_BIT		17
+#define ORION_WR_LOW_BIT		14
+#define ORION_ALE_WR_BIT		11
+#define ORION_ACC_NEXT_BIT		7
+#define ORION_ACC_FIRST_BIT		3
+#define ORION_TURN_OFF_BIT		0
+
 struct devbus_read_params {
 	u32 bus_width;
 	u32 badr_skew;
@@ -96,7 +112,6 @@ static int devbus_get_timing_params(struct devbus *devbus,
 {
 	int err;
 
-	/* Get read timings */
 	err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
 	if (err < 0) {
 		dev_err(devbus->dev,
@@ -131,24 +146,25 @@ static int devbus_get_timing_params(struct devbus *devbus,
 	if (err < 0)
 		return err;
 
-	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
-				 &r->rd_setup);
-	if (err < 0)
-		return err;
-
-	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
-				 &r->rd_hold);
-	if (err < 0)
-		return err;
-
-	/* Get write timings */
-	err = of_property_read_u32(node, "devbus,sync-enable",
-				  &w->sync_enable);
-	if (err < 0) {
-		dev_err(devbus->dev,
-			"%s has no 'devbus,sync-enable' property\n",
-			node->full_name);
-		return err;
+	if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
+		err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
+					  &r->rd_setup);
+		if (err < 0)
+			return err;
+
+		err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
+					  &r->rd_hold);
+		if (err < 0)
+			return err;
+
+		err = of_property_read_u32(node, "devbus,sync-enable",
+					   &w->sync_enable);
+		if (err < 0) {
+			dev_err(devbus->dev,
+				"%s has no 'devbus,sync-enable' property\n",
+				node->full_name);
+			return err;
+		}
 	}
 
 	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
@@ -169,6 +185,39 @@ static int devbus_get_timing_params(struct devbus *devbus,
 	return 0;
 }
 
+static void devbus_orion_set_timing_params(struct devbus *devbus,
+					  struct device_node *node,
+					  struct devbus_read_params *r,
+					  struct devbus_write_params *w)
+{
+	u32 value;
+
+	/*
+	 * The hardware designers found it would be a good idea to
+	 * split most of the values in the register into two fields:
+	 * one containing all the low-order bits, and another one
+	 * containing just the high-order bit. For all of those
+	 * fields, we have to split the value into these two parts.
+	 */
+	value = (r->turn_off   & 0x7) << ORION_TURN_OFF_BIT  |
+		(r->acc_first  & 0xF) << ORION_ACC_FIRST_BIT |
+		(r->acc_next   & 0xF) << ORION_ACC_NEXT_BIT  |
+		(w->ale_wr     & 0x7) << ORION_ALE_WR_BIT    |
+		(w->wr_low     & 0x7) << ORION_WR_LOW_BIT    |
+		(w->wr_high    & 0x7) << ORION_WR_HIGH_BIT   |
+		r->bus_width          << ORION_DEV_WIDTH_BIT |
+		((r->turn_off  & 0x8)  ? BIT(ORION_TURN_OFF_EXT_BIT)  : 0) |
+		((r->acc_first & 0x10) ? BIT(ORION_ACC_FIRST_EXT_BIT) : 0) |
+		((r->acc_next  & 0x10) ? BIT(ORION_ACC_NEXT_EXT_BIT)  : 0) |
+		((w->ale_wr    & 0x8)  ? BIT(ORION_ALE_WR_EXT_BIT)    : 0) |
+		((w->wr_low    & 0x8)  ? BIT(ORION_WR_LOW_EXT_BIT)    : 0) |
+		((w->wr_high   & 0x8)  ? BIT(ORION_WR_HIGH_EXT_BIT)   : 0) |
+		(r->badr_skew << ORION_BADR_SKEW_BIT) |
+		ORION_RESERVED;
+
+	writel(value, devbus->base);
+}
+
 static void devbus_armada_set_timing_params(struct devbus *devbus,
 					   struct device_node *node,
 					   struct devbus_read_params *r,
@@ -248,7 +297,10 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
 		return err;
 
 	/* Set the new timing parameters */
-	devbus_armada_set_timing_params(devbus, node, &r, &w);
+	if (of_device_is_compatible(node, "marvell,orion-devbus"))
+		devbus_orion_set_timing_params(devbus, node, &r, &w);
+	else
+		devbus_armada_set_timing_params(devbus, node, &r, &w);
 
 	/*
 	 * We need to create a child device explicitly from here to
@@ -264,6 +316,7 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
 
 static const struct of_device_id mvebu_devbus_of_match[] = {
 	{ .compatible = "marvell,mvebu-devbus" },
+	{ .compatible = "marvell,orion-devbus" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
-- 
1.8.3.2

[PATCH 08/29] ARM: orion5x: move interrupt controller node into ocp

[Thomas Petazzoni]

The interrupt controller node was located outside of the ocp at f1000000
node, which doesn't make much sense: like any other device, the
interrupt controller has registers located in the "Internal Registers
Window", so it is much more logical to have it under the ocp at f1000000
node.

It is even more important as we are going to move Orion5x to use the
Device Tree binding of the mvebu-mbus driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 174d892..da57fb9 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -17,13 +17,6 @@
 		gpio0 = &gpio0;
 	};
 
-	intc: interrupt-controller {
-		compatible = "marvell,orion-intc";
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		reg = <0xf1020200 0x08>;
-	};
-
 	ocp at f1000000 {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0xf1000000 0x4000000
@@ -79,6 +72,13 @@
 			status = "disabled";
 		};
 
+		intc: interrupt-controller@20200 {
+			compatible = "marvell,orion-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x20200 0x08>;
+		};
+
 		wdt at 20300 {
 			compatible = "marvell,orion-wdt";
 			reg = <0x20300 0x28>;
-- 
1.8.3.2

[PATCH 09/29] ARM: orion5x: switch to preprocessor includes in DT

[Thomas Petazzoni]

This commit switches the Orion5x Device Tree files to use C
preprocessor based includes, as it will allow us to use definitions
from header files in future commits.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 3 ++-
 arch/arm/boot/dts/orion5x.dtsi                            | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 5ed6c13..0245bb3 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -7,7 +7,8 @@
  */
 
 /dts-v1/;
-/include/ "orion5x.dtsi"
+
+#include "orion5x.dtsi"
 
 / {
 	model = "LaCie Ethernet Disk mini V2";
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index da57fb9..2364e3d 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -6,7 +6,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	model = "Marvell Orion5x SoC";
-- 
1.8.3.2

[PATCH 10/29] ARM: orion5x: use existing dt-bindings include for Device Tree files

[Thomas Petazzoni]

The orion5x-lacie-ethernet-disk-mini-v2.dts can benefit from using
gpio.h and input.h dt-bindings headers to replace hardcoded values by
more meaningful macros.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0245bb3..24f1ce7 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -8,6 +8,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include "orion5x.dtsi"
 
 / {
@@ -40,8 +42,8 @@
 		#size-cells = <0>;
 		button at 1 {
 			label = "Power-on Switch";
-			linux,code = <116>; /* KEY_POWER */
-			gpios = <&gpio0 18 0>;
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -50,7 +52,7 @@
 
 		led at 1 {
 			label = "power:blue";
-			gpios = <&gpio0 16 1>;
+			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
-- 
1.8.3.2

[PATCH 11/29] ARM: orion5x: convert DT to use the mvebu-mbus driver

[Thomas Petazzoni]

This commit switches the Orion5x Device Tree files to use the DT
representation and probing for the mvebu-mbus driver. The changes are
mainly:

 * Re-organize the DT to follow the same organization as the one used
   on Armada 370/XP, which is needed for mvebu-mbus to work: a
   top-level soc { ... } node, which corresponds to the MBus bus, and
   a sub-node internal-regs { ... } for all peripherals whose register
   sit only in the "Internal Register Window". This change re-indents
   by one level the definition of all nodes in the Device Tree, which
   explains the large change.

 * Use custom functions orion5x_dt_init_early() and
   orion5x_dt_init_time() instead of orion5x_init_early() and
   orion5x_timer_init() as we now want the MBus driver to be probed
   from the Device Tree. We still use the old-style timer
   initialization, but that will be changed in a followup commit.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |  23 +-
 arch/arm/boot/dts/orion5x-mv88f5182.dtsi           |  24 ++
 arch/arm/boot/dts/orion5x.dtsi                     | 245 +++++++++++----------
 arch/arm/mach-orion5x/board-dt.c                   |  19 +-
 4 files changed, 181 insertions(+), 130 deletions(-)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5182.dtsi

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 24f1ce7..d66d2fa 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -10,7 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "orion5x.dtsi"
+#include "orion5x-mv88f5182.dtsi"
 
 / {
 	model = "LaCie Ethernet Disk mini V2";
@@ -24,15 +24,20 @@
 		bootargs = "console=ttyS0,115200n8 earlyprintk";
 	};
 
-	ocp at f1000000 {
-		serial at 12000 {
-			clock-frequency = <166666667>;
-			status = "okay";
-		};
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
+
+		internal-regs {
+			serial at 12000 {
+				clock-frequency = <166666667>;
+				status = "okay";
+			};
 
-		sata at 80000 {
-			status = "okay";
-			nr-ports = <2>;
+			sata at 80000 {
+				status = "okay";
+				nr-ports = <2>;
+			};
 		};
 	};
 
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
new file mode 100644
index 0000000..ddfb4d1
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
+
+		internal-regs {
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 2364e3d..31d46e6 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -8,6 +8,8 @@
 
 #include "skeleton.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
 	model = "Marvell Orion5x SoC";
 	compatible = "marvell,orion5x";
@@ -17,149 +19,154 @@
 		gpio0 = &gpio0;
 	};
 
-	ocp@f1000000 {
-		compatible = "simple-bus";
-		ranges = <0x00000000 0xf1000000 0x4000000
-		          0xf2200000 0xf2200000 0x0000800>;
-		#address-cells = <1>;
+	soc {
+		#address-cells = <2>;
 		#size-cells = <1>;
+		controller = <&mbusc>;
 
-		gpio0: gpio at 10100 {
-			compatible = "marvell,orion-gpio";
-			#gpio-cells = <2>;
-			gpio-controller;
-			reg = <0x10100 0x40>;
-			ngpios = <32>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupts = <6>, <7>, <8>, <9>;
-		};
-
-		spi at 10600 {
-			compatible = "marvell,orion-spi";
+		internal-regs {
+			compatible = "simple-bus";
 			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <0>;
-			reg = <0x10600 0x28>;
-			status = "disabled";
-		};
-
-		i2c at 11000 {
-			compatible = "marvell,mv64xxx-i2c";
-			reg = <0x11000 0x20>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <5>;
-			clock-frequency = <100000>;
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			gpio0: gpio at 10100 {
+				compatible = "marvell,orion-gpio";
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <0x10100 0x40>;
+				ngpios = <32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <6>, <7>, <8>, <9>;
+			};
 
-		serial at 12000 {
-			compatible = "ns16550a";
-			reg = <0x12000 0x100>;
-			reg-shift = <2>;
-			interrupts = <3>;
-			/* set clock-frequency in board dts */
-			status = "disabled";
-		};
+			spi at 10600 {
+				compatible = "marvell,orion-spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				reg = <0x10600 0x28>;
+				status = "disabled";
+			};
 
-		serial at 12100 {
-			compatible = "ns16550a";
-			reg = <0x12100 0x100>;
-			reg-shift = <2>;
-			interrupts = <4>;
-			/* set clock-frequency in board dts */
-			status = "disabled";
-		};
+			i2c at 11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <5>;
+				clock-frequency = <100000>;
+				status = "disabled";
+			};
 
-		intc: interrupt-controller at 20200 {
-			compatible = "marvell,orion-intc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			reg = <0x20200 0x08>;
-		};
+			serial at 12000 {
+				compatible = "ns16550a";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <3>;
+				/* set clock-frequency in board dts */
+				status = "disabled";
+			};
 
-		wdt at 20300 {
-			compatible = "marvell,orion-wdt";
-			reg = <0x20300 0x28>;
-			status = "okay";
-		};
+			serial at 12100 {
+				compatible = "ns16550a";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <4>;
+				/* set clock-frequency in board dts */
+				status = "disabled";
+			};
 
-		ehci at 50000 {
-			compatible = "marvell,orion-ehci";
-			reg = <0x50000 0x1000>;
-			interrupts = <17>;
-			status = "disabled";
-		};
+			intc: interrupt-controller at 20200 {
+				compatible = "marvell,orion-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x20200 0x08>;
+			};
 
-		xor at 60900 {
-			compatible = "marvell,orion-xor";
-			reg = <0x60900 0x100
-			       0x60b00 0x100>;
-			status = "okay";
+			wdt at 20300 {
+				compatible = "marvell,orion-wdt";
+				reg = <0x20300 0x28>;
+				status = "okay";
+			};
 
-			xor00 {
-			      interrupts = <30>;
-			      dmacap,memcpy;
-			      dmacap,xor;
+			ehci at 50000 {
+				compatible = "marvell,orion-ehci";
+				reg = <0x50000 0x1000>;
+				interrupts = <17>;
+				status = "disabled";
 			};
-			xor01 {
-			      interrupts = <31>;
-			      dmacap,memcpy;
-			      dmacap,xor;
-			      dmacap,memset;
+
+			xor at 60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				status = "okay";
+
+				xor00 {
+				      interrupts = <30>;
+				      dmacap,memcpy;
+				      dmacap,xor;
+				};
+				xor01 {
+				      interrupts = <31>;
+				      dmacap,memcpy;
+				      dmacap,xor;
+				      dmacap,memset;
+				};
 			};
-		};
 
-		eth: ethernet-controller at 72000 {
-			compatible = "marvell,orion-eth";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x72000 0x4000>;
-			marvell,tx-checksum-limit = <1600>;
-			status = "disabled";
-
-			ethernet-port at 0 {
-				compatible = "marvell,orion-eth-port";
-				reg = <0>;
-				/* overwrite MAC address in bootloader */
-				local-mac-address = [00 00 00 00 00 00];
-				/* set phy-handle property in board file */
+			eth: ethernet-controller at 72000 {
+				compatible = "marvell,orion-eth";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72000 0x4000>;
+				marvell,tx-checksum-limit = <1600>;
+				status = "disabled";
+
+				ethernet-port at 0 {
+					compatible = "marvell,orion-eth-port";
+					reg = <0>;
+					/* overwrite MAC address in bootloader */
+					local-mac-address = [00 00 00 00 00 00];
+					/* set phy-handle property in board file */
+				};
 			};
-		};
 
-		mdio: mdio-bus at 72004 {
-			compatible = "marvell,orion-mdio";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x72004 0x84>;
-			interrupts = <22>;
-			status = "disabled";
+			mdio: mdio-bus at 72004 {
+				compatible = "marvell,orion-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72004 0x84>;
+				interrupts = <22>;
+				status = "disabled";
 
-			/* add phy nodes in board file */
-		};
+				/* add phy nodes in board file */
+			};
+
+			sata at 80000 {
+				compatible = "marvell,orion-sata";
+				reg = <0x80000 0x5000>;
+				interrupts = <29>;
+				status = "disabled";
+			};
 
-		sata at 80000 {
-			compatible = "marvell,orion-sata";
-			reg = <0x80000 0x5000>;
-			interrupts = <29>;
-			status = "disabled";
+			ehci at a0000 {
+				compatible = "marvell,orion-ehci";
+				reg = <0xa0000 0x1000>;
+				interrupts = <12>;
+				status = "disabled";
+			};
 		};
 
 		crypto at 90000 {
 			compatible = "marvell,orion-crypto";
-			reg = <0x90000 0x10000>,
-			      <0xf2200000 0x800>;
+			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
+			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;
 			reg-names = "regs", "sram";
 			interrupts = <28>;
 			status = "okay";
 		};
-
-		ehci at a0000 {
-			compatible = "marvell,orion-ehci";
-			reg = <0xa0000 0x1000>;
-			interrupts = <12>;
-			status = "disabled";
-		};
 	};
 };
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index c134a82..f6a388a 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -15,10 +15,14 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/cpu.h>
+#include <linux/mbus.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 
 static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
@@ -31,6 +35,17 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
 	{},
 };
 
+static void orion5x_dt_init_early(void)
+{
+	orion_time_set_base(TIMER_VIRT_BASE);
+}
+
+static void orion5x_dt_init_time(void)
+{
+	orion5x_timer_init();
+	BUG_ON(mvebu_mbus_dt_init());
+}
+
 static void __init orion5x_dt_init(void)
 {
 	char *dev_name;
@@ -71,9 +86,9 @@ static const char *orion5x_dt_compat[] = {
 DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
 	/* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
 	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
+	.init_early	= orion5x_dt_init_early,
 	.init_irq	= orion_dt_init_irq,
-	.init_time	= orion5x_timer_init,
+	.init_time	= orion5x_dt_init_time,
 	.init_machine	= orion5x_dt_init,
 	.restart	= orion5x_restart,
 	.dt_compat	= orion5x_dt_compat,
-- 
1.8.3.2

[PATCH 12/29] ARM: orion5x: add interrupt for Ethernet in Device Tree

[Thomas Petazzoni]

For some reason, the Ethernet interrupt was missing in the Orion5x
Device Tree definition.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 31d46e6..ac2ec8f 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -128,6 +128,7 @@
 				ethernet-port at 0 {
 					compatible = "marvell,orion-eth-port";
 					reg = <0>;
+					interrupts = <21>;
 					/* overwrite MAC address in bootloader */
 					local-mac-address = [00 00 00 00 00 00];
 					/* set phy-handle property in board file */
-- 
1.8.3.2

[PATCH 13/29] ARM: orion5x: switch to use the clock driver for DT platforms

[Thomas Petazzoni]

This commit moves the Orion5x platforms using the Device Tree to use
the recently introduced clock driver for Orion5x. To achieve that, it:

 * Adds the necessary DT description of the clock.

 * Selects ORION_CLK to enable the compilation of the clock driver.

 * Call of_clk_init() instead of the Orion5x-specific clock
   initialization function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 6 ++++++
 arch/arm/mach-orion5x/Kconfig            | 1 +
 arch/arm/mach-orion5x/board-dt.c         | 5 ++---
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
index ddfb4d1..a56f9c8 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -15,6 +15,12 @@
 		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
 
 		internal-regs {
+			core_clk: core-clocks at 10030 {
+				compatible = "marvell,mv88f5182-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
 			mbusc: mbus-controller at 20000 {
 				compatible = "marvell,mbus-controller";
 				reg = <0x20000 0x100>, <0x1500 0x20>;
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 14f2cae..4f51132 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -5,6 +5,7 @@ menu "Orion Implementations"
 config ARCH_ORION5X_DT
 	bool "Marvell Orion5x Flattened Device Tree"
 	select USE_OF
+	select ORION_CLK
 	help
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Orion5x using flattened device tree.
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index f6a388a..c489661 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -16,6 +16,7 @@
 #include <linux/of_platform.h>
 #include <linux/cpu.h>
 #include <linux/mbus.h>
+#include <linux/clk-provider.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -43,6 +44,7 @@ static void orion5x_dt_init_early(void)
 static void orion5x_dt_init_time(void)
 {
 	orion5x_timer_init();
+	of_clk_init(NULL);
 	BUG_ON(mvebu_mbus_dt_init());
 }
 
@@ -59,9 +61,6 @@ static void __init orion5x_dt_init(void)
 	 */
 	orion5x_setup_wins();
 
-	/* Setup root of clk tree */
-	clk_init();
-
 	/*
 	 * Don't issue "Wait for Interrupt" instruction if we are
 	 * running on D0 5281 silicon.
-- 
1.8.3.2

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Thomas Petazzoni]

Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER
enabled, even for non-DT platforms (if we want both DT and non-DT
platforms to be supported in a single kernel).

However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT
platforms in plat-orion/irq.c doesn't match the needs of
Orion5x. Also, it doesn't make much sense for orion_irq_init() to
register the multi-IRQ handler: orion_irq_init() is called once for
each IRQ cause/mask tuple, while the multi-IRQ handler only needs to
be registered once.

To solve this problem, we move the multi-IRQ handle in per-platform
code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant
will be introduced in a followup commit. Of course, this code will
ultimately be completely removed once all boards are converted to the
Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-dove/irq.c     | 36 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/irq.c | 36 +++++++++++++++++++++++++++++++++++
 arch/arm/plat-orion/irq.c    | 45 --------------------------------------------
 3 files changed, 72 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index bc4344a..4a5a7ae 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -108,6 +108,38 @@ static int __initdata gpio2_irqs[4] = {
 	0,
 };
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+
+static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
+
+static asmlinkage void
+__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
+{
+	u32 stat;
+
+	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
+	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
+	if (stat) {
+		unsigned int hwirq = __fls(stat);
+		handle_IRQ(hwirq, regs);
+		return;
+	}
+	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
+	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
+	if (stat) {
+		unsigned int hwirq = 32 + __fls(stat);
+		handle_IRQ(hwirq, regs);
+		return;
+	}
+}
+#endif
+
 void __init dove_init_irq(void)
 {
 	int i;
@@ -115,6 +147,10 @@ void __init dove_init_irq(void)
 	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
 	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+	set_handle_irq(dove_legacy_handle_irq);
+#endif
+
 	/*
 	 * Initialize gpiolib for GPIOs 0-71.
 	 */
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 2a97a2e..c9dd860 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -30,11 +30,47 @@ static int __initdata gpio1_irqs[4] = {
 	0,
 };
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+
+static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE;
+
+asmlinkage void
+__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs)
+{
+	u32 stat;
+
+	stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF);
+	stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF);
+	if (stat) {
+		unsigned int hwirq = __fls(stat);
+		handle_IRQ(hwirq, regs);
+		return;
+	}
+	stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF);
+	stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF);
+	if (stat) {
+		unsigned int hwirq = 32 + __fls(stat);
+		handle_IRQ(hwirq, regs);
+		return;
+	}
+}
+#endif
+
 void __init kirkwood_init_irq(void)
 {
 	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
 	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+	set_handle_irq(kirkwood_legacy_handle_irq);
+#endif
+
 	/*
 	 * Initialize gpiolib for GPIOs 0-49.
 	 */
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 807df14..27ec18b 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -20,47 +20,6 @@
 #include <plat/orion-gpio.h>
 #include <mach/bridge-regs.h>
 
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-/*
- * Compiling with both non-DT and DT support enabled, will
- * break asm irq handler used by non-DT boards. Therefore,
- * we provide a C-style irq handler even for non-DT boards,
- * if MULTI_IRQ_HANDLER is set.
- *
- * Notes:
- * - this is prepared for Kirkwood and Dove only, update
- *   accordingly if you add Orion5x or MV78x00.
- * - Orion5x uses different macro names and has only one
- *   set of CAUSE/MASK registers.
- * - MV78x00 uses the same macro names but has a third
- *   set of CAUSE/MASK registers.
- *
- */
-
-static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
-
-asmlinkage void
-__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
-{
-	u32 stat;
-
-	stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
-	stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
-	if (stat) {
-		unsigned int hwirq = __fls(stat);
-		handle_IRQ(hwirq, regs);
-		return;
-	}
-	stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
-	stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
-	if (stat) {
-		unsigned int hwirq = 32 + __fls(stat);
-		handle_IRQ(hwirq, regs);
-		return;
-	}
-}
-#endif
-
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
 	struct irq_chip_generic *gc;
@@ -78,10 +37,6 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
 	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
 			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
-
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-	set_handle_irq(orion_legacy_handle_irq);
-#endif
 }
 
 #ifdef CONFIG_OF
-- 
1.8.3.2

[PATCH 15/29] ARM: orion5x: switch to DT interrupts and timer

[Thomas Petazzoni]

This commit switches the Orion5x platforms described through DT to use
a DT-defined interrupt controller and timer.

This involves:

 * Describing in the DT the bridge interrupt controller, which is a
   child interrupt controller to the main one, which is used for timer
   and watchdog interrupts.

 * Describing in the DT the timer.

 * Adding in the DT the interrupt specifications for the watchdog.

 * Selecting the ORION_IRQCHIP and ORION_TIMER drivers to be compiled.

 * Change the timer initialization in board-dt.c to use
   clocksource_of_init().

 * Implement a multi-IRQ handler for non-DT platforms in
   mach-orion5x/irq.c.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x.dtsi   | 19 +++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig    |  2 ++
 arch/arm/mach-orion5x/board-dt.c | 10 ++--------
 arch/arm/mach-orion5x/irq.c      | 28 ++++++++++++++++++++++++++++
 4 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index ac2ec8f..f25ed91 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -78,6 +78,15 @@
 				status = "disabled";
 			};
 
+			bridge_intc: bridge-interrupt-ctrl at 20110 {
+				compatible = "marvell,orion-bridge-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x20110 0x8>;
+				interrupts = <0>;
+				marvell,#interrupts = <4>;
+			};
+
 			intc: interrupt-controller at 20200 {
 				compatible = "marvell,orion-intc";
 				interrupt-controller;
@@ -85,9 +94,19 @@
 				reg = <0x20200 0x08>;
 			};
 
+			timer at 20300 {
+				compatible = "marvell,orion-timer";
+				reg = <0x20300 0x20>;
+				interrupt-parent = <&bridge_intc>;
+				interrupts = <1>, <2>;
+				clocks = <&core_clk 0>;
+			};
+
 			wdt at 20300 {
 				compatible = "marvell,orion-wdt";
 				reg = <0x20300 0x28>;
+				interrupt-parent = <&bridge_intc>;
+				interrupts = <3>;
 				status = "okay";
 			};
 
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 4f51132..bd65872 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -6,6 +6,8 @@ config ARCH_ORION5X_DT
 	bool "Marvell Orion5x Flattened Device Tree"
 	select USE_OF
 	select ORION_CLK
+	select ORION_IRQCHIP
+	select ORION_TIMER
 	help
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Orion5x using flattened device tree.
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index c489661..38b54f1 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -17,6 +17,7 @@
 #include <linux/cpu.h>
 #include <linux/mbus.h>
 #include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -36,15 +37,10 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
 	{},
 };
 
-static void orion5x_dt_init_early(void)
-{
-	orion_time_set_base(TIMER_VIRT_BASE);
-}
-
 static void orion5x_dt_init_time(void)
 {
-	orion5x_timer_init();
 	of_clk_init(NULL);
+	clocksource_of_init();
 	BUG_ON(mvebu_mbus_dt_init());
 }
 
@@ -85,8 +81,6 @@ static const char *orion5x_dt_compat[] = {
 DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
 	/* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
 	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_dt_init_early,
-	.init_irq	= orion_dt_init_irq,
 	.init_time	= orion5x_dt_init_time,
 	.init_machine	= orion5x_dt_init,
 	.restart	= orion5x_restart,
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 9654b0c..cd4bac4 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -16,6 +16,7 @@
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
+#include <asm/exception.h>
 #include "common.h"
 
 static int __initdata gpio0_irqs[4] = {
@@ -25,10 +26,37 @@ static int __initdata gpio0_irqs[4] = {
 	IRQ_ORION5X_GPIO_24_31,
 };
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+
+asmlinkage void
+__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
+{
+	u32 stat;
+
+	stat = readl_relaxed(MAIN_IRQ_CAUSE);
+	stat &= readl_relaxed(MAIN_IRQ_MASK);
+	if (stat) {
+		unsigned int hwirq = __fls(stat);
+		handle_IRQ(hwirq, regs);
+		return;
+	}
+}
+#endif
+
 void __init orion5x_init_irq(void)
 {
 	orion_irq_init(0, MAIN_IRQ_MASK);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+	set_handle_irq(orion5x_legacy_handle_irq);
+#endif
+
 	/*
 	 * Initialize gpiolib for GPIOs 0-31.
 	 */
-- 
1.8.3.2

[PATCH 16/29] ARM: orion5x: enable pinctrl driver at SoC level

[Thomas Petazzoni]

This commit declares the pinctrl device in the Orion5x 5182 Device
Tree files, and ensures that the Orion pinctrl driver is compiled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 5 +++++
 arch/arm/mach-orion5x/Kconfig            | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
index a56f9c8..11b487c 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -15,6 +15,11 @@
 		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
 
 		internal-regs {
+			pinctrl at 10000 {
+				compatible = "marvell,88f5182-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
 			core_clk: core-clocks at 10030 {
 				compatible = "marvell,mv88f5182-core-clock";
 				reg = <0x10010 0x4>;
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index bd65872..3c69a3c 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -8,6 +8,8 @@ config ARCH_ORION5X_DT
 	select ORION_CLK
 	select ORION_IRQCHIP
 	select ORION_TIMER
+	select PINCTRL
+	select PINCTRL_ORION
 	help
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Orion5x using flattened device tree.
-- 
1.8.3.2

[PATCH 17/29] ARM: orion5x: update I2C description at SoC level

[Thomas Petazzoni]

This commit fixes the Orion5x SoC definition to:

 * Not define a clock-frequency, as it should be described on a
   per-board basis.

 * Declare the appropriate clock reference, so that the driver can do
   correct divisors calculations for the I2C bus.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index f25ed91..ea6ec83 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -56,7 +56,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				interrupts = <5>;
-				clock-frequency = <100000>;
+				clocks = <&core_clk 0>;
 				status = "disabled";
 			};
 
-- 
1.8.3.2

[PATCH 18/29] ARM: orion5x: add Device Bus description at SoC level

[Thomas Petazzoni]

This commit adds the necessary SoC-level Device Tree definitions to
describe the Device Bus of Orion5x SOCs. The Device Bus is mainly used
to connect NOR flashes to the system.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index ea6ec83..182682b 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -24,6 +24,46 @@
 		#size-cells = <1>;
 		controller = <&mbusc>;
 
+		devbus-bootcs {
+			compatible = "marvell,orion-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
+			ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs0 {
+			compatible = "marvell,orion-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
+			ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs1 {
+			compatible = "marvell,orion-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
+			ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs2 {
+			compatible = "marvell,orion-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
+			ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
 		internal-regs {
 			compatible = "simple-bus";
 			#address-cells = <1>;
-- 
1.8.3.2

[PATCH 19/29] ARM: orion5x: add standard pinctrl configs for sata0 and sata1

[Thomas Petazzoni]

Several platforms will most likely use similar pinctrl configurations
for SATA0 and SATA1, so we declare those common configurations in the
Orion5x DT file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
index 11b487c..096ab02 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -18,6 +18,16 @@
 			pinctrl at 10000 {
 				compatible = "marvell,88f5182-pinctrl";
 				reg = <0x10000 0x8>, <0x10050 0x4>;
+
+				pmx_sata0: pmx-sata0 {
+					marvell,pins = "mpp12", "mpp14";
+					marvell,function = "sata0";
+				};
+
+				pmx_sata1: pmx-sata1 {
+					marvell,pins = "mpp13", "mpp15";
+					marvell,function = "sata1";
+				};
 			};
 
 			core_clk: core-clocks at 10030 {
-- 
1.8.3.2

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Thomas Petazzoni]

This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for pinctrl.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 31 ++++++++++++++++++++++
 arch/arm/mach-orion5x/edmini_v2-setup.c            | 28 -------------------
 2 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index d66d2fa..eee42f7 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -29,12 +29,39 @@
 			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
 
 		internal-regs {
+			pinctrl at 10000 {
+				pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
+				pinctrl-names = "default";
+
+				pmx_rtc: pmx-rtc {
+					marvell,pins = "mpp3";
+					marvell,function = "gpio";
+				};
+
+				pmx_power_led: pmx-power-led {
+					marvell,pins = "mpp16";
+					marvell,function = "gpio";
+				};
+
+				pmx_power_led_ctrl: pmx-power-led-ctrl {
+					marvell,pins = "mpp17";
+					marvell,function = "gpio";
+				};
+
+				pmx_power_button: pmx-power-button {
+					marvell,pins = "mpp18";
+					marvell,function = "gpio";
+				};
+			};
+
 			serial at 12000 {
 				clock-frequency = <166666667>;
 				status = "okay";
 			};
 
 			sata at 80000 {
+				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+				pinctrl-names = "default";
 				status = "okay";
 				nr-ports = <2>;
 			};
@@ -43,6 +70,8 @@
 
 	gpio_keys {
 		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_power_button>;
+		pinctrl-names = "default";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		button at 1 {
@@ -54,6 +83,8 @@
 
 	gpio_leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led>;
+		pinctrl-names = "default";
 
 		led at 1 {
 			label = "power:blue";
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index f66c1b2..c50469e 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -109,37 +109,9 @@ static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static unsigned int edminiv2_mpp_modes[] __initdata = {
-	MPP0_UNUSED,
-	MPP1_UNUSED,
-	MPP2_UNUSED,
-	MPP3_GPIO,	/* RTC interrupt */
-	MPP4_UNUSED,
-	MPP5_UNUSED,
-	MPP6_UNUSED,
-	MPP7_UNUSED,
-	MPP8_UNUSED,
-	MPP9_UNUSED,
-	MPP10_UNUSED,
-	MPP11_UNUSED,
-	MPP12_SATA_LED,	/* SATA 0 presence */
-	MPP13_SATA_LED,	/* SATA 1 presence */
-	MPP14_SATA_LED,	/* SATA 0 active */
-	MPP15_SATA_LED,	/* SATA 1 active */
-	/* 16: Power LED control (0 = On, 1 = Off) */
-	MPP16_GPIO,
-	/* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
-	MPP17_GPIO,
-	/* 18: Power button status (0 = Released, 1 = Pressed) */
-	MPP18_GPIO,
-	MPP19_UNUSED,
-	0,
-};
 
 void __init edmini_v2_init(void)
 {
-	orion5x_mpp_conf(edminiv2_mpp_modes);
-
 	/*
 	 * Configure peripherals.
 	 */
-- 
1.8.3.2

[PATCH 21/29] ARM: orion5x: use DT to describe I2C devices on edmini_v2

[Thomas Petazzoni]

This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for I2C bus and devices.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 14 +++++++++++++
 arch/arm/mach-orion5x/edmini_v2-setup.c            | 24 ----------------------
 2 files changed, 14 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index eee42f7..f077b7b 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "orion5x-mv88f5182.dtsi"
 
 / {
@@ -54,6 +55,19 @@
 				};
 			};
 
+			i2c at 11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+				#address-cells = <1>;
+
+				rtc at 32 {
+					compatible = "rs5c372a";
+					reg = <0x32>;
+					interrupt-parent = <&gpio0>;
+					interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+				};
+			};
+
 			serial at 12000 {
 				clock-frequency = <166666667>;
 				status = "okay";
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index c50469e..75648ab 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -96,17 +96,6 @@ static struct platform_device edmini_v2_nor_flash = {
 };
 
 /*****************************************************************************
- * RTC 5C372a on I2C bus
- ****************************************************************************/
-
-#define EDMINIV2_RTC_GPIO	3
-
-static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
-	I2C_BOARD_INFO("rs5c372a", 0x32),
-	.irq = 0,
-};
-
-/*****************************************************************************
  * General Setup
  ****************************************************************************/
 
@@ -125,17 +114,4 @@ void __init edmini_v2_init(void)
 
 	pr_notice("edmini_v2: USB device port, flash write and power-off "
 		  "are not yet supported.\n");
-
-	/* Get RTC IRQ and register the chip */
-	if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) {
-		if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0)
-			edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO);
-		else
-			gpio_free(EDMINIV2_RTC_GPIO);
-	}
-
-	if (edmini_v2_i2c_rtc.irq == 0)
-		pr_warning("edmini_v2: failed to get RTC IRQ\n");
-
-	i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1);
 }
-- 
1.8.3.2

[PATCH 22/29] ARM: orion5x: use DT to describe EHCI on edmini_v2

[Thomas Petazzoni]

This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for USB.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 4 ++++
 arch/arm/mach-orion5x/edmini_v2-setup.c                   | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index f077b7b..ff90b01 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -73,6 +73,10 @@
 				status = "okay";
 			};
 
+			ehci at 50000 {
+				status = "okay";
+			};
+
 			sata at 80000 {
 				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
 				pinctrl-names = "default";
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 75648ab..2eebc0c 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -104,8 +104,6 @@ void __init edmini_v2_init(void)
 	/*
 	 * Configure peripherals.
 	 */
-	orion5x_ehci0_init();
-
 	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
 				    ORION_MBUS_DEVBUS_BOOT_ATTR,
 				    EDMINI_V2_NOR_BOOT_BASE,
-- 
1.8.3.2

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Thomas Petazzoni]

This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for NOR flash, using the Device Bus.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 46 +++++++++++++++-
 arch/arm/mach-orion5x/edmini_v2-setup.c            | 62 ----------------------
 2 files changed, 45 insertions(+), 63 deletions(-)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index ff90b01..44cc36a 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -27,7 +27,51 @@
 
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
-			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
+
+		devbus-bootcs {
+			status = "okay";
+
+			/* Read parameters */
+			devbus,bus-width    = <8>;
+			devbus,turn-off-ps  = <90000>;
+			devbus,badr-skew-ps = <0>;
+			devbus,acc-first-ps = <186000>;
+			devbus,acc-next-ps  = <186000>;
+
+			/* Write parameters */
+			devbus,wr-high-ps  = <90000>;
+			devbus,wr-low-ps   = <90000>;
+			devbus,ale-wr-ps   = <90000>;
+
+			/*
+			 * Currently the MTD code does not recognize
+			 * the MX29LV400CBCT as a bottom-type
+			 * device. This could cause risks of
+			 * accidentally erasing critical flash
+			 * sectors. We thus define a single,
+			 * write-protected partition covering the
+			 * whole flash.  TODO: once the flash part
+			 * TOP/BOTTOM detection issue is sorted out in
+			 * the MTD code, break this into at least
+			 * three partitions: 'u-boot code', 'u-boot
+			 * environment' and 'whatever is left'.
+			 */
+			nor at 0 {
+				compatible = "cfi-flash";
+				reg = <0 0x80000>;
+				bank-width = <1>;
+		                #address-cells = <1>;
+				#size-cells = <1>;
+
+				partition at 0 {
+					label = "Full512Kb";
+					reg = <0 0x80000>;
+					read-only;
+				};
+			};
+		};
 
 		internal-regs {
 			pinctrl at 10000 {
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 2eebc0c..6bef2d5 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -42,74 +42,12 @@
  * EDMINI_V2 Info
  ****************************************************************************/
 
-/*
- * 512KB NOR flash Device bus boot chip select
- */
-
-#define EDMINI_V2_NOR_BOOT_BASE		0xfff80000
-#define EDMINI_V2_NOR_BOOT_SIZE		SZ_512K
-
-/*****************************************************************************
- * 512KB NOR Flash on BOOT Device
- ****************************************************************************/
-
-/*
- * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
- * -type device. This could cause risks of accidentally erasing critical
- * flash sectors. We thus define a single, write-protected partition covering
- * the whole flash.
- * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
- * code, break this into at least three partitions: 'u-boot code', 'u-boot
- * environment' and 'whatever is left'.
- */
-
-static struct mtd_partition edmini_v2_partitions[] = {
-	{
-		.name		= "Full512kb",
-		.size		= 0x00080000,
-		.offset		= 0x00000000,
-		.mask_flags	= MTD_WRITEABLE,
-	},
-};
-
-static struct physmap_flash_data edmini_v2_nor_flash_data = {
-	.width		= 1,
-	.parts		= edmini_v2_partitions,
-	.nr_parts	= ARRAY_SIZE(edmini_v2_partitions),
-};
-
-static struct resource edmini_v2_nor_flash_resource = {
-	.flags			= IORESOURCE_MEM,
-	.start			= EDMINI_V2_NOR_BOOT_BASE,
-	.end			= EDMINI_V2_NOR_BOOT_BASE
-		+ EDMINI_V2_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device edmini_v2_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &edmini_v2_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &edmini_v2_nor_flash_resource,
-};
-
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
 
 void __init edmini_v2_init(void)
 {
-	/*
-	 * Configure peripherals.
-	 */
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    EDMINI_V2_NOR_BOOT_BASE,
-				    EDMINI_V2_NOR_BOOT_SIZE);
-	platform_device_register(&edmini_v2_nor_flash);
-
 	pr_notice("edmini_v2: USB device port, flash write and power-off "
 		  "are not yet supported.\n");
 }
-- 
1.8.3.2

[PATCH 24/29] ARM: orion5x: keep TODO list in edmini_v2 DT

[Thomas Petazzoni]

In preparation to the complete removal of non-DT support for
edmini_v2, this commit copies the TODO list of things to support from
the old-style board file into the Device Tree of edmini_v2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 44cc36a..ffa0fc5 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -6,6 +6,13 @@
  * warranty of any kind, whether express or implied.
  */
 
+/*
+ * TODO: add Orion USB device port init when kernel.org support is added.
+ * TODO: add flash write support: see below.
+ * TODO: add power-off support.
+ * TODO: add I2C EEPROM support.
+ */
+
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
-- 
1.8.3.2

[PATCH 25/29] ARM: orion5x: remove unneeded code for edmini_v2

[Thomas Petazzoni]

The edmini_v2 platform is now fully converted to the Device Tree, so
we can get rid of the old style board-file and the related Kconfig
option.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-orion5x/Kconfig           |  8 -----
 arch/arm/mach-orion5x/Makefile          |  1 -
 arch/arm/mach-orion5x/board-dt.c        |  3 --
 arch/arm/mach-orion5x/common.h          |  7 -----
 arch/arm/mach-orion5x/edmini_v2-setup.c | 53 ---------------------------------
 5 files changed, 72 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/edmini_v2-setup.c

diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 3c69a3c..928f4cb 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -107,14 +107,6 @@ config MACH_MV2120
 	  Say 'Y' here if you want your kernel to support the
 	  HP Media Vault mv2120 or mv5100.
 
-config MACH_EDMINI_V2_DT
-	bool "LaCie Ethernet Disk mini V2 (Flattened Device Tree)"
-	select I2C_BOARDINFO
-	select ARCH_ORION5X_DT
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  LaCie Ethernet Disk mini V2 (Flattened Device Tree).
-
 config MACH_D2NET
 	bool "LaCie d2 Network"
 	select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 45da805..e8fdbdd 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -23,4 +23,3 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_LSCHL)	+= ls-chl-setup.o
 
 obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
-obj-$(CONFIG_MACH_EDMINI_V2_DT)	+= edmini_v2-setup.o
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 38b54f1..c621f37 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -66,9 +66,6 @@ static void __init orion5x_dt_init(void)
 		cpu_idle_poll_ctrl(true);
 	}
 
-	if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2"))
-		edmini_v2_init();
-
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     orion5x_auxdata_lookup, NULL);
 }
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 7548db2..4470e31 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -64,13 +64,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
 int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 
-/* board init functions for boards not fully converted to fdt */
-#ifdef CONFIG_MACH_EDMINI_V2_DT
-void edmini_v2_init(void);
-#else
-static inline void edmini_v2_init(void) {};
-#endif
-
 struct meminfo;
 struct tag;
 extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
deleted file mode 100644
index 6bef2d5..0000000
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-orion5x/edmini_v2-setup.c
- *
- * LaCie Ethernet Disk mini V2 Setup
- *
- * Copyright (C) 2008 Christopher Moore <moore@free.fr>
- * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/*
- * TODO: add Orion USB device port init when kernel.org support is added.
- * TODO: add flash write support: see below.
- * TODO: add power-off support.
- * TODO: add I2C EEPROM support.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mbus.h>
-#include <linux/mtd/physmap.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/orion5x.h>
-#include "common.h"
-#include "mpp.h"
-
-/*****************************************************************************
- * EDMINI_V2 Info
- ****************************************************************************/
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-void __init edmini_v2_init(void)
-{
-	pr_notice("edmini_v2: USB device port, flash write and power-off "
-		  "are not yet supported.\n");
-}
-- 
1.8.3.2

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Thomas Petazzoni]

This commit converts the RD-88F5182 platform to the Device Tree. All
devices except the PCI are converted to the Device Tree.

It is worth noting that:

 * The PCI description for the DT case is kept in board-rd88f5182.c.

 * The existing non-DT support in rd88f5182-setup.c is kept as is, in
   order to allow testing of a given platform in both DT and non-DT
   cases. It will ultimately be removed, once we no longer care about
   non-DT support for Orion5x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile                  |   3 +-
 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 153 ++++++++++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig               |   8 ++
 arch/arm/mach-orion5x/Makefile              |   1 +
 arch/arm/mach-orion5x/board-rd88f5182.c     | 116 +++++++++++++++++++++
 5 files changed, 280 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
 create mode 100644 arch/arm/mach-orion5x/board-rd88f5182.c

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..f7943a8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	am43x-epos-evm.dtb \
 	am437x-gp-evm.dtb \
 	dra7-evm.dtb
-dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
+dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \
+	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
 	qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
new file mode 100644
index 0000000..b5fd087
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "orion5x-mv88f5182.dtsi"
+
+/ {
+	model = "Marvell Reference Design 88F5182 NAS";
+	compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x4000000>; /* 64 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+		         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
+			 <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
+
+		devbus-bootcs {
+			status = "okay";
+			/* TODO: Device Bus parameters */
+			nor at 0 {
+				compatible = "cfi-flash";
+				reg = <0 0x80000>;
+				bank-width = <1>;
+			};
+		};
+
+		devbus-cs1 {
+			status = "okay";
+			/* TODO: Device Bus parameters */
+			nor at 0 {
+				compatible = "cfi-flash";
+				reg = <0 0x1000000>;
+				bank-width = <1>;
+			};
+		};
+
+		internal-regs {
+			pinctrl at 10000 {
+				pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
+					     &pmx_pci_gpios>;
+				pinctrl-names = "default";
+
+				/*
+				 * MPP[20] PCI Clock to MV88F5182
+				 * MPP[21] PCI Clock to mini PCI CON11
+				 * MPP[22] USB 0 over current indication
+				 * MPP[23] USB 1 over current indication
+				 * MPP[24] USB 1 over current enable
+				 * MPP[25] USB 0 over current enable
+				 */
+
+				pmx_debug_led: pmx-debug_led {
+					marvell,pins = "mpp0";
+					marvell,function = "gpio";
+				};
+
+				pmx_reset_switch: pmx-reset-switch {
+					marvell,pins = "mpp1";
+					marvell,function = "gpio";
+				};
+
+				pmx_rtc: pmx-rtc {
+					marvell,pins = "mpp3";
+					marvell,function = "gpio";
+				};
+
+				pmx_misc_gpios: pmx-misc-gpios {
+					marvell,pins = "mpp4", "mpp5";
+					marvell,function = "gpio";
+				};
+
+				pmx_pci_gpios: pmx-pci-gpios {
+					marvell,pins = "mpp6", "mpp7";
+					marvell,function = "gpio";
+				};
+			};
+
+			i2c at 11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+				#address-cells = <1>;
+
+				rtc at 68 {
+					pinctrl-0 = <&pmx_rtc>;
+					pinctrl-names = "default";
+					compatible = "ds1338";
+					reg = <0x68>;
+				};
+			};
+
+			serial at 12000 {
+				clock-frequency = <166666667>;
+				status = "okay";
+			};
+
+			ehci at 50000 {
+				status = "okay";
+			};
+
+			sata at 80000 {
+				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+				pinctrl-names = "default";
+				status = "okay";
+				nr-ports = <2>;
+			};
+
+			ehci at a0000 {
+				status = "okay";
+			};
+		};
+	};
+
+	gpio_leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_debug_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "rd88f5182:cpu";
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio0 0 0>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy: ethernet-phy {
+		reg = <8>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		phy-handle = <&ethphy>;
+	};
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 928f4cb..11b0c7e 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -28,6 +28,14 @@ config MACH_RD88F5182
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell Orion-NAS (88F5182) RD2
 
+config MACH_RD88F5182_DT
+	bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)"
+	select ARCH_ORION5X_DT
+	select I2C_BOARDINFO
+	help
+	  Say 'Y' here if you want your kernel to support the Marvell
+	  Orion-NAS (88F5182) RD2, Flattened Device Tree.
+
 config MACH_KUROBOX_PRO
 	bool "KuroBox Pro"
 	select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index e8fdbdd..f405894 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_LSCHL)	+= ls-chl-setup.o
 
 obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
+obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c
new file mode 100644
index 0000000..270824b
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-rd88f5182.c
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5182-setup.c
+ *
+ * Marvell Orion-NAS Reference Design Setup
+ *
+ * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+
+/*****************************************************************************
+ * RD-88F5182 Info
+ ****************************************************************************/
+
+/*
+ * PCI
+ */
+
+#define RD88F5182_PCI_SLOT0_OFFS	7
+#define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
+#define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6
+
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+
+static void __init rd88f5182_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
+	if (gpio_request(pin, "PCI IntA") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
+					"set_irq_type pin %d\n", pin);
+			gpio_free(pin);
+		}
+	} else {
+		printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
+	}
+
+	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
+	if (gpio_request(pin, "PCI IntB") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
+					"set_irq_type pin %d\n", pin);
+			gpio_free(pin);
+		}
+	} else {
+		printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
+	}
+}
+
+static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
+	case 0:
+		if (pin == 1)
+			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
+		else
+			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci rd88f5182_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= rd88f5182_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= rd88f5182_pci_map_irq,
+};
+
+static int __init rd88f5182_pci_init(void)
+{
+	if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
+		pci_common_init(&rd88f5182_pci);
+
+	return 0;
+}
+
+subsys_initcall(rd88f5182_pci_init);
-- 
1.8.3.2

[PATCH 27/29] ARM: orion5x: convert d2net to Device Tree

[Thomas Petazzoni]

This commit converts the LaCie d2 Network platform to the Device Tree.

All devices except LEDs are converted, because the LED code needs a
non-LED GPIO to be set to a given value for the LEDs to work, and this
cannot yet be easily represented in DT.

Also, references to the LaCie Big Disk Network platform are lost,
because this platform apparently has exactly the same hardware support
as the LaCie d2 Network, so their Device Tree files would be
identical.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile                     |   3 +-
 arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 234 ++++++++++++++++
 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts    |   4 +-
 arch/arm/mach-orion5x/Kconfig                  |  13 +-
 arch/arm/mach-orion5x/Makefile                 |   3 +-
 arch/arm/mach-orion5x/board-d2net.c            | 109 ++++++++
 arch/arm/mach-orion5x/d2net-setup.c            | 365 -------------------------
 7 files changed, 352 insertions(+), 379 deletions(-)
 create mode 100644 arch/arm/boot/dts/orion5x-lacie-d2-network.dts
 create mode 100644 arch/arm/mach-orion5x/board-d2net.c
 delete mode 100644 arch/arm/mach-orion5x/d2net-setup.c

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f7943a8..59397c2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 	am43x-epos-evm.dtb \
 	am437x-gp-evm.dtb \
 	dra7-evm.dtb
-dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \
+dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
+	orion5x-lacie-ethernet-disk-mini-v2.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
new file mode 100644
index 0000000..bb67ddd
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "orion5x-mv88f5182.dtsi"
+
+/ {
+	model = "LaCie d2 Network";
+	compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
+
+		devbus-bootcs {
+			status = "okay";
+
+			devbus,keep-config;
+
+			/*
+			 * Currently the MTD code does not recognize
+			 * the MX29LV400CBCT as a bottom-type
+			 * device. This could cause risks of
+			 * accidentally erasing critical flash
+			 * sectors. We thus define a single,
+			 * write-protected partition covering the
+			 * whole flash.  TODO: once the flash part
+			 * TOP/BOTTOM detection issue is sorted out in
+			 * the MTD code, break this into at least
+			 * three partitions: 'u-boot code', 'u-boot
+			 * environment' and 'whatever is left'.
+			 */
+			nor at 0 {
+				compatible = "cfi-flash";
+				reg = <0 0x80000>;
+				bank-width = <1>;
+		                #address-cells = <1>;
+				#size-cells = <1>;
+
+				partition at 0 {
+					label = "Full512Kb";
+					reg = <0 0x80000>;
+					read-only;
+				};
+			};
+		};
+
+		internal-regs {
+			pinctrl at 10000 {
+				pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>;
+				pinctrl-names = "default";
+
+				pmx_buttons: pmx-buttons {
+					marvell,pins = "mpp8", "mpp9", "mpp18";
+					marvell,function = "gpio";
+				};
+
+				/*
+				 * MPP6: Red front LED
+				 * MPP16: Blue front LED blink control
+				 */
+				pmx_leds: pmx-leds {
+					marvell,pins = "mpp6", "mpp16";
+					marvell,function = "gpio";
+				};
+
+				pmx_board_id: pmx-board-id {
+					marvell,pins = "mpp0", "mpp1", "mpp2";
+					marvell,function = "gpio";
+				};
+
+				pmx_sata0_power: pmx-sata0-power {
+					marvell,pins = "mpp3";
+					marvell,function = "gpio";
+				};
+
+				pmx_sata1_power: pmx-sata1-power {
+					marvell,pins = "mpp12";
+					marvell,function = "gpio";
+				};
+
+				pmx_sata0_led_active: pmx-sata0-led-active {
+					marvell,pins = "mpp14";
+					marvell,function = "sata0";
+				};
+
+				pmx_sata1_led_active: pmx-sata1-led-active {
+					marvell,pins = "mpp15";
+					marvell,function = "sata1";
+				};
+
+				pmx_fan_fail: pmx-fan-fail {
+					marvell,pins = "mpp5";
+					marvell,function = "gpio";
+				};
+
+				/*
+				 * Non MPP GPIOs:
+				 *  GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
+				 *  GPIO 23: Blue front LED off
+				 *  GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
+				 */
+			};
+
+
+			i2c at 11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+				#address-cells = <1>;
+
+				rtc at 32 {
+					compatible = "rs5c372b";
+					reg = <0x32>;
+				};
+
+				fan at 3e {
+					compatible = "gmt,g762";
+					reg = <0x3e>;
+
+					/* Not enough HW info */
+					status = "disabled";
+				};
+
+				eeprom at 50 {
+					compatible = "24c08";
+					reg = <0x50>;
+				};
+			};
+
+			serial at 12000 {
+				clock-frequency = <166666667>;
+				status = "okay";
+			};
+
+			ehci at 50000 {
+				status = "okay";
+			};
+
+			sata at 80000 {
+				pinctrl-0 = <&pmx_sata0_led_active
+					     &pmx_sata1_led_active>;
+				pinctrl-names = "default";
+				status = "okay";
+				nr-ports = <2>;
+			};
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_buttons>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		front_button {
+			label = "Front Push Button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+		};
+
+		power_rocker_sw_on {
+			label = "Power rocker switch (on|auto)";
+			linux,input-type = <5>; /* EV_SW */
+			linux,code = <1>; /* D2NET_SWITCH_POWER_ON */
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		power_rocker_sw_off {
+			label = "Power rocker switch (auto|off)";
+			linux,input-type = <5>; /* EV_SW */
+			linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */
+			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>;
+		pinctrl-names = "default";
+
+		sata0_power: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "SATA0 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata1_power: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy: ethernet-phy {
+		reg = <8>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		phy-handle = <&ethphy>;
+	};
+};
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index b5fd087..b1a8330 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -7,6 +7,8 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
 #include "orion5x-mv88f5182.dtsi"
 
 / {
@@ -131,7 +133,7 @@
 		led at 0 {
 			label = "rd88f5182:cpu";
 			linux,default-trigger = "heartbeat";
-			gpios = <&gpio0 0 0>;
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 11b0c7e..3c4ad83 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -115,20 +115,13 @@ config MACH_MV2120
 	  Say 'Y' here if you want your kernel to support the
 	  HP Media Vault mv2120 or mv5100.
 
-config MACH_D2NET
-	bool "LaCie d2 Network"
-	select I2C_BOARDINFO
+config MACH_D2NET_DT
+	bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)"
+	select ARCH_ORION5X_DT
 	help
 	  Say 'Y' here if you want your kernel to support the
 	  LaCie d2 Network NAS.
 
-config MACH_BIGDISK
-	bool "LaCie Big Disk Network"
-	select I2C_BOARDINFO
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  LaCie Big Disk Network NAS.
-
 config MACH_NET2BIG
 	bool "LaCie 2Big Network"
 	select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index f405894..787dcee 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,8 +12,6 @@ obj-$(CONFIG_MACH_TS409)	+= ts409-setup.o tsx09-common.o
 obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
-obj-$(CONFIG_MACH_D2NET)	+= d2net-setup.o
-obj-$(CONFIG_MACH_BIGDISK)	+= d2net-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
 obj-$(CONFIG_MACH_MSS2)		+= mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
@@ -23,4 +21,5 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_LSCHL)	+= ls-chl-setup.o
 
 obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
+obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c
new file mode 100644
index 0000000..8a72841
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-d2net.c
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/mach-orion5x/board-d2net.c
+ *
+ * LaCie d2Network and Big Disk Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
+#include "common.h"
+
+/*****************************************************************************
+ * LaCie d2 Network Info
+ ****************************************************************************/
+
+/*****************************************************************************
+ * GPIO LED's
+ ****************************************************************************/
+
+/*
+ * The blue front LED is wired to the CPLD and can blink in relation with the
+ * SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ * led_off   | blink_ctrl | SATA active | LED state
+ *           |            |             |
+ *    1      |     x      |      x      |  off
+ *    0      |     0      |      0      |  off
+ *    0      |     1      |      0      |  blink (rate 300ms)
+ *    0      |     x      |      1      |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Red LED have priority.
+ */
+
+#define D2NET_GPIO_RED_LED		6
+#define D2NET_GPIO_BLUE_LED_BLINK_CTRL	16
+#define D2NET_GPIO_BLUE_LED_OFF		23
+
+static struct gpio_led d2net_leds[] = {
+	{
+		.name = "d2net:blue:sata",
+		.default_trigger = "default-on",
+		.gpio = D2NET_GPIO_BLUE_LED_OFF,
+		.active_low = 1,
+	},
+	{
+		.name = "d2net:red:fail",
+		.gpio = D2NET_GPIO_RED_LED,
+	},
+};
+
+static struct gpio_led_platform_data d2net_led_data = {
+	.num_leds = ARRAY_SIZE(d2net_leds),
+	.leds = d2net_leds,
+};
+
+static struct platform_device d2net_gpio_leds = {
+	.name           = "leds-gpio",
+	.id             = -1,
+	.dev            = {
+		.platform_data  = &d2net_led_data,
+	},
+};
+
+static void __init d2net_gpio_leds_init(void)
+{
+	int err;
+
+	/* Configure register blink_ctrl to allow SATA activity LED blinking. */
+	err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink");
+	if (err == 0) {
+		err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1);
+		if (err)
+			gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL);
+	}
+	if (err)
+		pr_err("d2net: failed to configure blue LED blink GPIO\n");
+
+	platform_device_register(&d2net_gpio_leds);
+}
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+void __init d2net_init(void)
+{
+	d2net_gpio_leds_init();
+
+	pr_notice("d2net: Flash write are not yet supported.\n");
+}
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
deleted file mode 100644
index 8f68b74..0000000
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * arch/arm/mach-orion5x/d2net-setup.c
- *
- * LaCie d2Network and Big Disk Network NAS setup
- *
- * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/orion5x.h>
-#include <plat/orion-gpio.h>
-#include "common.h"
-#include "mpp.h"
-
-/*****************************************************************************
- * LaCie d2 Network Info
- ****************************************************************************/
-
-/*
- * 512KB NOR flash Device bus boot chip select
- */
-
-#define D2NET_NOR_BOOT_BASE		0xfff80000
-#define D2NET_NOR_BOOT_SIZE		SZ_512K
-
-/*****************************************************************************
- * 512KB NOR Flash on Boot Device
- ****************************************************************************/
-
-/*
- * TODO: Check write support on flash MX29LV400CBTC-70G
- */
-
-static struct mtd_partition d2net_partitions[] = {
-	{
-		.name		= "Full512kb",
-		.size		= MTDPART_SIZ_FULL,
-		.offset		= 0,
-		.mask_flags	= MTD_WRITEABLE,
-	},
-};
-
-static struct physmap_flash_data d2net_nor_flash_data = {
-	.width		= 1,
-	.parts		= d2net_partitions,
-	.nr_parts	= ARRAY_SIZE(d2net_partitions),
-};
-
-static struct resource d2net_nor_flash_resource = {
-	.flags			= IORESOURCE_MEM,
-	.start			= D2NET_NOR_BOOT_BASE,
-	.end			= D2NET_NOR_BOOT_BASE
-					+ D2NET_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device d2net_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &d2net_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &d2net_nor_flash_resource,
-};
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data d2net_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-/*
- * i2c addr | chip         | description
- * 0x32     | Ricoh 5C372b | RTC
- * 0x3e     | GMT G762     | PWM fan controller
- * 0x50     | HT24LC08     | eeprom (1kB)
- *
- * TODO: Add G762 support to the g760a driver.
- */
-static struct i2c_board_info __initdata d2net_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("rs5c372b", 0x32),
-	}, {
-		I2C_BOARD_INFO("24c08", 0x50),
-	},
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-
-static struct mv_sata_platform_data d2net_sata_data = {
-	.n_ports	= 2,
-};
-
-#define D2NET_GPIO_SATA0_POWER	3
-#define D2NET_GPIO_SATA1_POWER	12
-
-static void __init d2net_sata_power_init(void)
-{
-	int err;
-
-	err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power");
-	if (err == 0) {
-		err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1);
-		if (err)
-			gpio_free(D2NET_GPIO_SATA0_POWER);
-	}
-	if (err)
-		pr_err("d2net: failed to configure SATA0 power GPIO\n");
-
-	err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power");
-	if (err == 0) {
-		err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1);
-		if (err)
-			gpio_free(D2NET_GPIO_SATA1_POWER);
-	}
-	if (err)
-		pr_err("d2net: failed to configure SATA1 power GPIO\n");
-}
-
-/*****************************************************************************
- * GPIO LED's
- ****************************************************************************/
-
-/*
- * The blue front LED is wired to the CPLD and can blink in relation with the
- * SATA activity.
- *
- * The following array detail the different LED registers and the combination
- * of their possible values:
- *
- * led_off   | blink_ctrl | SATA active | LED state
- *           |            |             |
- *    1      |     x      |      x      |  off
- *    0      |     0      |      0      |  off
- *    0      |     1      |      0      |  blink (rate 300ms)
- *    0      |     x      |      1      |  on
- *
- * Notes: The blue and the red front LED's can't be on at the same time.
- *        Red LED have priority.
- */
-
-#define D2NET_GPIO_RED_LED		6
-#define D2NET_GPIO_BLUE_LED_BLINK_CTRL	16
-#define D2NET_GPIO_BLUE_LED_OFF		23
-
-static struct gpio_led d2net_leds[] = {
-	{
-		.name = "d2net:blue:sata",
-		.default_trigger = "default-on",
-		.gpio = D2NET_GPIO_BLUE_LED_OFF,
-		.active_low = 1,
-	},
-	{
-		.name = "d2net:red:fail",
-		.gpio = D2NET_GPIO_RED_LED,
-	},
-};
-
-static struct gpio_led_platform_data d2net_led_data = {
-	.num_leds = ARRAY_SIZE(d2net_leds),
-	.leds = d2net_leds,
-};
-
-static struct platform_device d2net_gpio_leds = {
-	.name           = "leds-gpio",
-	.id             = -1,
-	.dev            = {
-		.platform_data  = &d2net_led_data,
-	},
-};
-
-static void __init d2net_gpio_leds_init(void)
-{
-	int err;
-
-	/* Configure GPIO over MPP max number. */
-	orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1);
-
-	/* Configure register blink_ctrl to allow SATA activity LED blinking. */
-	err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink");
-	if (err == 0) {
-		err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1);
-		if (err)
-			gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL);
-	}
-	if (err)
-		pr_err("d2net: failed to configure blue LED blink GPIO\n");
-
-	platform_device_register(&d2net_gpio_leds);
-}
-
-/****************************************************************************
- * GPIO keys
- ****************************************************************************/
-
-#define D2NET_GPIO_PUSH_BUTTON		18
-#define D2NET_GPIO_POWER_SWITCH_ON	8
-#define D2NET_GPIO_POWER_SWITCH_OFF	9
-
-#define D2NET_SWITCH_POWER_ON		0x1
-#define D2NET_SWITCH_POWER_OFF		0x2
-
-static struct gpio_keys_button d2net_buttons[] = {
-	{
-		.type		= EV_SW,
-		.code		= D2NET_SWITCH_POWER_OFF,
-		.gpio		= D2NET_GPIO_POWER_SWITCH_OFF,
-		.desc		= "Power rocker switch (auto|off)",
-		.active_low	= 0,
-	},
-	{
-		.type		= EV_SW,
-		.code		= D2NET_SWITCH_POWER_ON,
-		.gpio		= D2NET_GPIO_POWER_SWITCH_ON,
-		.desc		= "Power rocker switch (on|auto)",
-		.active_low	= 0,
-	},
-	{
-		.type		= EV_KEY,
-		.code		= KEY_POWER,
-		.gpio		= D2NET_GPIO_PUSH_BUTTON,
-		.desc		= "Front Push Button",
-		.active_low	= 0,
-	},
-};
-
-static struct gpio_keys_platform_data d2net_button_data = {
-	.buttons	= d2net_buttons,
-	.nbuttons	= ARRAY_SIZE(d2net_buttons),
-};
-
-static struct platform_device d2net_gpio_buttons = {
-	.name		= "gpio-keys",
-	.id		= -1,
-	.dev		= {
-		.platform_data	= &d2net_button_data,
-	},
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-static unsigned int d2net_mpp_modes[] __initdata = {
-	MPP0_GPIO,	/* Board ID (bit 0) */
-	MPP1_GPIO,	/* Board ID (bit 1) */
-	MPP2_GPIO,	/* Board ID (bit 2) */
-	MPP3_GPIO,	/* SATA 0 power */
-	MPP4_UNUSED,
-	MPP5_GPIO,	/* Fan fail detection */
-	MPP6_GPIO,	/* Red front LED */
-	MPP7_UNUSED,
-	MPP8_GPIO,	/* Rear power switch (on|auto) */
-	MPP9_GPIO,	/* Rear power switch (auto|off) */
-	MPP10_UNUSED,
-	MPP11_UNUSED,
-	MPP12_GPIO,	/* SATA 1 power */
-	MPP13_UNUSED,
-	MPP14_SATA_LED,	/* SATA 0 active */
-	MPP15_SATA_LED,	/* SATA 1 active */
-	MPP16_GPIO,	/* Blue front LED blink control */
-	MPP17_UNUSED,
-	MPP18_GPIO,	/* Front button (0 = Released, 1 = Pushed ) */
-	MPP19_UNUSED,
-	0,
-	/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
-	/* 23: Blue front LED off */
-	/* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
-};
-
-#define D2NET_GPIO_INHIBIT_POWER_OFF    24
-
-static void __init d2net_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(d2net_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_ehci0_init();
-	orion5x_eth_init(&d2net_eth_data);
-	orion5x_i2c_init();
-	orion5x_uart0_init();
-
-	d2net_sata_power_init();
-	orion5x_sata_init(&d2net_sata_data);
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    D2NET_NOR_BOOT_BASE,
-				    D2NET_NOR_BOOT_SIZE);
-	platform_device_register(&d2net_nor_flash);
-
-	platform_device_register(&d2net_gpio_buttons);
-
-	d2net_gpio_leds_init();
-
-	pr_notice("d2net: Flash write are not yet supported.\n");
-
-	i2c_register_board_info(0, d2net_i2c_devices,
-				ARRAY_SIZE(d2net_i2c_devices));
-
-	orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1);
-}
-
-/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
-
-#ifdef CONFIG_MACH_D2NET
-MACHINE_START(D2NET, "LaCie d2 Network")
-	.atag_offset	= 0x100,
-	.init_machine	= d2net_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_BIGDISK
-MACHINE_START(BIGDISK, "LaCie Big Disk Network")
-	.atag_offset	= 0x100,
-	.init_machine	= d2net_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-#endif
-
-- 
1.8.3.2

[PATCH 28/29] ARM: orion: remove no longer needed DT IRQ code

[Thomas Petazzoni]

Following the move of the Orion5x Device Tree support to use
irqchip_init() for the interrupt controller probing, the
plat-orion/irq.c code for DT-probing of the interrupt controller is no
longer necessary, so we can get rid of it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/plat-orion/include/plat/irq.h |  1 -
 arch/arm/plat-orion/irq.c              | 32 --------------------------------
 2 files changed, 33 deletions(-)

diff --git a/arch/arm/plat-orion/include/plat/irq.h b/arch/arm/plat-orion/include/plat/irq.h
index 50547e4..96be19e 100644
--- a/arch/arm/plat-orion/include/plat/irq.h
+++ b/arch/arm/plat-orion/include/plat/irq.h
@@ -12,5 +12,4 @@
 #define __PLAT_IRQ_H
 
 void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
-void __init orion_dt_init_irq(void);
 #endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 27ec18b..8c1fc06 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -38,35 +38,3 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
 			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
-
-#ifdef CONFIG_OF
-static int __init orion_add_irq_domain(struct device_node *np,
-				       struct device_node *interrupt_parent)
-{
-	int i = 0;
-	void __iomem *base;
-
-	do {
-		base = of_iomap(np, i);
-		if (base) {
-			orion_irq_init(i * 32, base + 0x04);
-			i++;
-		}
-	} while (base);
-
-	irq_domain_add_legacy(np, i * 32, 0, 0,
-			      &irq_domain_simple_ops, NULL);
-	return 0;
-}
-
-static const struct of_device_id orion_irq_match[] = {
-	{ .compatible = "marvell,orion-intc",
-	  .data = orion_add_irq_domain, },
-	{},
-};
-
-void __init orion_dt_init_irq(void)
-{
-	of_irq_init(orion_irq_match);
-}
-#endif
-- 
1.8.3.2

[PATCH 29/29] ARM: orion: remove no longer needed gpio DT code

[Thomas Petazzoni]

Following the move to pure DT-based probing of the GPIO controllers on
Orion5x, some code in plat-orion/orion-gpio.c can be removed as it is
no longer used.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/plat-orion/gpio.c                    | 48 ---------------------------
 arch/arm/plat-orion/include/plat/orion-gpio.h |  1 -
 2 files changed, 49 deletions(-)

diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 6816192..b61a3bc 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -597,51 +597,3 @@ void __init orion_gpio_init(struct device_node *np,
 
 	orion_gpio_chip_count++;
 }
-
-#ifdef CONFIG_OF
-static void __init orion_gpio_of_init_one(struct device_node *np,
-					  int irq_gpio_base)
-{
-	int ngpio, gpio_base, mask_offset;
-	void __iomem *base;
-	int ret, i;
-	int irqs[4];
-	int secondary_irq_base;
-
-	ret = of_property_read_u32(np, "ngpio", &ngpio);
-	if (ret)
-		goto out;
-	ret = of_property_read_u32(np, "mask-offset", &mask_offset);
-	if (ret == -EINVAL)
-		mask_offset = 0;
-	else
-		goto out;
-	base = of_iomap(np, 0);
-	if (!base)
-		goto out;
-
-	secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count);
-	gpio_base = 32 * orion_gpio_chip_count;
-
-	/* Get the interrupt numbers. Each chip can have up to 4
-	 * interrupt handlers, with each handler dealing with 8 GPIO
-	 * pins. */
-
-	for (i = 0; i < 4; i++)
-		irqs[i] = irq_of_parse_and_map(np, i);
-
-	orion_gpio_init(np, gpio_base, ngpio, base, mask_offset,
-			secondary_irq_base, irqs);
-	return;
-out:
-	pr_err("%s: %s: missing mandatory property\n", __func__, np->name);
-}
-
-void __init orion_gpio_of_init(int irq_gpio_base)
-{
-	struct device_node *np;
-
-	for_each_compatible_node(np, NULL, "marvell,orion-gpio")
-		orion_gpio_of_init_one(np, irq_gpio_base);
-}
-#endif
diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h
index 614dcac..e763988 100644
--- a/arch/arm/plat-orion/include/plat/orion-gpio.h
+++ b/arch/arm/plat-orion/include/plat/orion-gpio.h
@@ -33,5 +33,4 @@ void __init orion_gpio_init(struct device_node *np,
 			    int secondary_irq_base,
 			    int irq[4]);
 
-void __init orion_gpio_of_init(int irq_gpio_base);
 #endif
-- 
1.8.3.2

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Andrew Lunn]

On Sun, Apr 13, 2014 at 04:39:57PM +0200, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for pinctrl.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 31 ++++++++++++++++++++++
>  arch/arm/mach-orion5x/edmini_v2-setup.c            | 28 -------------------
>  2 files changed, 31 insertions(+), 28 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index d66d2fa..eee42f7 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -29,12 +29,39 @@
>  			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
>  
>  		internal-regs {
> +			pinctrl at 10000 {
> +				pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
> +				pinctrl-names = "default";
> +
> +				pmx_rtc: pmx-rtc {
> +					marvell,pins = "mpp3";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_led: pmx-power-led {
> +					marvell,pins = "mpp16";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_led_ctrl: pmx-power-led-ctrl {
> +					marvell,pins = "mpp17";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_button: pmx-power-button {
> +					marvell,pins = "mpp18";
> +					marvell,function = "gpio";
> +				};
> +			};

Hi Thomas

One of the things Sebastian did as part of his Kirkwood DT cleanup was
sort pinctrl nodes by label, instead of mpp number. We should probably
discuss this and come to a conclusion before converting Orion5x
platforms.

	Andrew

[PATCH 21/29] ARM: orion5x: use DT to describe I2C devices on edmini_v2

[Andrew Lunn]

On Sun, Apr 13, 2014 at 04:39:58PM +0200, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for I2C bus and devices.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 14 +++++++++++++
>  arch/arm/mach-orion5x/edmini_v2-setup.c            | 24 ----------------------
>  2 files changed, 14 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index eee42f7..f077b7b 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -10,6 +10,7 @@
>  
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>  #include "orion5x-mv88f5182.dtsi"
>  
>  / {
> @@ -54,6 +55,19 @@
>  				};
>  			};
>  
> +			i2c at 11000 {
> +				status = "okay";
> +				clock-frequency = <100000>;
> +				#address-cells = <1>;
> +
> +				rtc at 32 {
> +					compatible = "rs5c372a";

Hi Thomas

This should have a vendor prefix.

     Andrew

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Andrew Lunn]

On Sun, Apr 13, 2014 at 04:40:00PM +0200, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for NOR flash, using the Device Bus.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 46 +++++++++++++++-
>  arch/arm/mach-orion5x/edmini_v2-setup.c            | 62 ----------------------
>  2 files changed, 45 insertions(+), 63 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index ff90b01..44cc36a 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -27,7 +27,51 @@
>  
>  	soc {
>  		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> -			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
> +
> +		devbus-bootcs {
> +			status = "okay";
> +
> +			/* Read parameters */
> +			devbus,bus-width    = <8>;
> +			devbus,turn-off-ps  = <90000>;
> +			devbus,badr-skew-ps = <0>;
> +			devbus,acc-first-ps = <186000>;
> +			devbus,acc-next-ps  = <186000>;
> +
> +			/* Write parameters */
> +			devbus,wr-high-ps  = <90000>;
> +			devbus,wr-low-ps   = <90000>;
> +			devbus,ale-wr-ps   = <90000>;
> +
> +			/*
> +			 * Currently the MTD code does not recognize
> +			 * the MX29LV400CBCT as a bottom-type
> +			 * device. This could cause risks of
> +			 * accidentally erasing critical flash
> +			 * sectors. We thus define a single,
> +			 * write-protected partition covering the
> +			 * whole flash.  TODO: once the flash part
> +			 * TOP/BOTTOM detection issue is sorted out in
> +			 * the MTD code, break this into at least
> +			 * three partitions: 'u-boot code', 'u-boot
> +			 * environment' and 'whatever is left'.
> +			 */
> +			nor at 0 {
> +				compatible = "cfi-flash";
> +				reg = <0 0x80000>;
> +				bank-width = <1>;
> +		                #address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				partition at 0 {
> +					label = "Full512Kb";
> +					reg = <0 0x80000>;
> +					read-only;
> +				};
> +			};
> +		};
>  
>  		internal-regs {
>  			pinctrl at 10000 {
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> index 2eebc0c..6bef2d5 100644
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
> @@ -42,74 +42,12 @@
>   * EDMINI_V2 Info
>   ****************************************************************************/
>  
> -/*
> - * 512KB NOR flash Device bus boot chip select
> - */
> -
> -#define EDMINI_V2_NOR_BOOT_BASE		0xfff80000
> -#define EDMINI_V2_NOR_BOOT_SIZE		SZ_512K
> -
> -/*****************************************************************************
> - * 512KB NOR Flash on BOOT Device
> - ****************************************************************************/
> -
> -/*
> - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
> - * -type device. This could cause risks of accidentally erasing critical
> - * flash sectors. We thus define a single, write-protected partition covering
> - * the whole flash.
> - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
> - * code, break this into at least three partitions: 'u-boot code', 'u-boot
> - * environment' and 'whatever is left'.
> - */

Hi Thomas

Did you check if this is still true? If it is fixed, maybe now would
be a good time to swap to three partitions?

   Andrew

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Thomas Petazzoni]

Dear Andrew Lunn,

On Sun, 13 Apr 2014 17:26:05 +0200, Andrew Lunn wrote:

> One of the things Sebastian did as part of his Kirkwood DT cleanup was
> sort pinctrl nodes by label, instead of mpp number. We should probably
> discuss this and come to a conclusion before converting Orion5x
> platforms.

Sorting by label may be a good idea, because sorting by MPP does not
necessarily make a lot of sense when some pinctrl configurations
include several pins. Like how would you sort:

config-foo {
	marvell,pins = "mpp2";
	...
};

config-bar {
	marvell,pins = "mpp1", "mpp13";
	...
};

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 21/29] ARM: orion5x: use DT to describe I2C devices on edmini_v2

[Thomas Petazzoni]

Dear Andrew Lunn,

On Sun, 13 Apr 2014 17:28:40 +0200, Andrew Lunn wrote:

> > +			i2c at 11000 {
> > +				status = "okay";
> > +				clock-frequency = <100000>;
> > +				#address-cells = <1>;
> > +
> > +				rtc at 32 {
> > +					compatible = "rs5c372a";
> 
> Hi Thomas
> 
> This should have a vendor prefix.

Ok, I was afraid this would have required adding an explicit DT binding
to the RTC driver, but that's not the case: of_modalias_node() strips
the vendor part of the compatible string.

Will fix for the next version, thanks.

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Thomas Petazzoni]

Dear Andrew Lunn,

On Sun, 13 Apr 2014 17:31:50 +0200, Andrew Lunn wrote:

> > -/*****************************************************************************
> > - * 512KB NOR Flash on BOOT Device
> > - ****************************************************************************/
> > -
> > -/*
> > - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
> > - * -type device. This could cause risks of accidentally erasing critical
> > - * flash sectors. We thus define a single, write-protected partition covering
> > - * the whole flash.
> > - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
> > - * code, break this into at least three partitions: 'u-boot code', 'u-boot
> > - * environment' and 'whatever is left'.
> > - */
> 
> Hi Thomas
> 
> Did you check if this is still true? If it is fixed, maybe now would
> be a good time to swap to three partitions?

I don't know, and since the NOR contains the bootloader, and I'm not
sure those Orion devices support UART booting, I clearly don't want to
play too much with NOR writing, as I don't want to brick the only two
Orion platforms that I have. So I'd prefer to leave the functionality
as it was, and leave it to other more adventurous and interested people
the work on improving this.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Andrew Lunn]

On Sun, Apr 13, 2014 at 04:40:03PM +0200, Thomas Petazzoni wrote:
> This commit converts the RD-88F5182 platform to the Device Tree. All
> devices except the PCI are converted to the Device Tree.
> 
> It is worth noting that:
> 
>  * The PCI description for the DT case is kept in board-rd88f5182.c.
> 
>  * The existing non-DT support in rd88f5182-setup.c is kept as is, in
>    order to allow testing of a given platform in both DT and non-DT
>    cases. It will ultimately be removed, once we no longer care about
>    non-DT support for Orion5x.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/Makefile                  |   3 +-
>  arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 153 ++++++++++++++++++++++++++++
>  arch/arm/mach-orion5x/Kconfig               |   8 ++
>  arch/arm/mach-orion5x/Makefile              |   1 +
>  arch/arm/mach-orion5x/board-rd88f5182.c     | 116 +++++++++++++++++++++
>  5 files changed, 280 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
>  create mode 100644 arch/arm/mach-orion5x/board-rd88f5182.c
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 35c146f..f7943a8 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
>  	am43x-epos-evm.dtb \
>  	am437x-gp-evm.dtb \
>  	dra7-evm.dtb
> -dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
> +dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \
> +	orion5x-rd88f5182-nas.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
>  dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
>  	qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
> new file mode 100644
> index 0000000..b5fd087
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
> @@ -0,0 +1,153 @@
> +/*
> + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "orion5x-mv88f5182.dtsi"
> +
> +/ {
> +	model = "Marvell Reference Design 88F5182 NAS";
> +	compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x4000000>; /* 64 MB */
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +		         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
> +			 <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
> +
> +		devbus-bootcs {
> +			status = "okay";
> +			/* TODO: Device Bus parameters */
> +			nor at 0 {
> +				compatible = "cfi-flash";
> +				reg = <0 0x80000>;
> +				bank-width = <1>;
> +			};
> +		};
> +
> +		devbus-cs1 {
> +			status = "okay";
> +			/* TODO: Device Bus parameters */
> +			nor at 0 {
> +				compatible = "cfi-flash";
> +				reg = <0 0x1000000>;
> +				bank-width = <1>;
> +			};
> +		};
> +
> +		internal-regs {
> +			pinctrl at 10000 {
> +				pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
> +					     &pmx_pci_gpios>;
> +				pinctrl-names = "default";
> +
> +				/*
> +				 * MPP[20] PCI Clock to MV88F5182
> +				 * MPP[21] PCI Clock to mini PCI CON11
> +				 * MPP[22] USB 0 over current indication
> +				 * MPP[23] USB 1 over current indication
> +				 * MPP[24] USB 1 over current enable
> +				 * MPP[25] USB 0 over current enable
> +				 */
> +
> +				pmx_debug_led: pmx-debug_led {
> +					marvell,pins = "mpp0";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_reset_switch: pmx-reset-switch {
> +					marvell,pins = "mpp1";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_rtc: pmx-rtc {
> +					marvell,pins = "mpp3";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_misc_gpios: pmx-misc-gpios {
> +					marvell,pins = "mpp4", "mpp5";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_pci_gpios: pmx-pci-gpios {
> +					marvell,pins = "mpp6", "mpp7";
> +					marvell,function = "gpio";
> +				};
> +			};
> +
> +			i2c at 11000 {
> +				status = "okay";
> +				clock-frequency = <100000>;
> +				#address-cells = <1>;
> +
> +				rtc at 68 {
> +					pinctrl-0 = <&pmx_rtc>;
> +					pinctrl-names = "default";
> +					compatible = "ds1338";

Hi Thomas

Vendor prefix again.

> +					reg = <0x68>;
> +				};
> +			};
> +
> +			serial at 12000 {
> +				clock-frequency = <166666667>;

I don't think you need this, so long as there is tclk in the node.


> +	gpio_leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_debug_led>;
> +		pinctrl-names = "default";
> +
> +		led at 0 {
> +			label = "rd88f5182:cpu";
> +			linux,default-trigger = "heartbeat";

Jason probably won't like that.

> +			gpios = <&gpio0 0 0>;

gpio.h defines?

> +static int __init rd88f5182_pci_init(void)
> +{
> +	if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
> +		pci_common_init(&rd88f5182_pci);
> +
> +	return 0;
> +}
> +
> +subsys_initcall(rd88f5182_pci_init);

Nice to see you are checking for compatibility in the initcall. How
far do you think this from a multi_v5 kernel?

    Andrew

[PATCH 21/29] ARM: orion5x: use DT to describe I2C devices on edmini_v2

[Andrew Lunn]

On Sun, Apr 13, 2014 at 05:43:41PM +0200, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
> 
> On Sun, 13 Apr 2014 17:28:40 +0200, Andrew Lunn wrote:
> 
> > > +			i2c at 11000 {
> > > +				status = "okay";
> > > +				clock-frequency = <100000>;
> > > +				#address-cells = <1>;
> > > +
> > > +				rtc at 32 {
> > > +					compatible = "rs5c372a";
> > 
> > Hi Thomas
> > 
> > This should have a vendor prefix.
> 
> Ok, I was afraid this would have required adding an explicit DT binding
> to the RTC driver, but that's not the case: of_modalias_node() strips
> the vendor part of the compatible string.

Yep, the vendor prefix is totally ignored, except by checkpatch, which
i guess is giving you a warning. It is also nice to have the prefix
just to be consistent, and maybe *BSD wants the prefix?

     Andrew

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Thomas Petazzoni]

Dear Andrew Lunn,

On Sun, 13 Apr 2014 17:47:15 +0200, Andrew Lunn wrote:

> > +				rtc at 68 {
> > +					pinctrl-0 = <&pmx_rtc>;
> > +					pinctrl-names = "default";
> > +					compatible = "ds1338";
> 
> Hi Thomas
> 
> Vendor prefix again.

Will do.

> > +					reg = <0x68>;
> > +				};
> > +			};
> > +
> > +			serial at 12000 {
> > +				clock-frequency = <166666667>;
> 
> I don't think you need this, so long as there is tclk in the node.

Ah, right, the 8250 driver is now capable of getting the clock rate
using a proper clock. Will fix that.

> > +	gpio_leds {
> > +		compatible = "gpio-leds";
> > +		pinctrl-0 = <&pmx_debug_led>;
> > +		pinctrl-names = "default";
> > +
> > +		led at 0 {
> > +			label = "rd88f5182:cpu";
> > +			linux,default-trigger = "heartbeat";
> 
> Jason probably won't like that.

I'm just doing a 1:1 functional conversion here.

> 
> > +			gpios = <&gpio0 0 0>;
> 
> gpio.h defines?

Indeed. Missed that one it seems, as I used them pretty much everywhere
else.

> > +static int __init rd88f5182_pci_init(void)
> > +{
> > +	if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
> > +		pci_common_init(&rd88f5182_pci);
> > +
> > +	return 0;
> > +}
> > +
> > +subsys_initcall(rd88f5182_pci_init);
> 
> Nice to see you are checking for compatibility in the initcall. How
> far do you think this from a multi_v5 kernel?

I haven't thought too much about this yet. I'm hoping to do more
Orion5x DT conversion once this patch series is done, and then think
about multiplatform support.

To be honest, I find it pretty useless to have half of the Kirkwood
and Dove support in mach-mvebu, and half still in
mach-kirkwood/mach-dove, because it doesn't allow to remove any of the
legacy code in mach-kirkwood and mach-dove. But oh, well, I guess it's
only a temporary situation, until more boards are converted, or their
support simply removed.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Andrew Lunn]

> To be honest, I find it pretty useless to have half of the Kirkwood
> and Dove support in mach-mvebu, and half still in
> mach-kirkwood/mach-dove, because it doesn't allow to remove any of the
> legacy code in mach-kirkwood and mach-dove. But oh, well, I guess it's
> only a temporary situation, until more boards are converted, or their
> support simply removed.

I hope kirkwood will complete its move soon. I have Openrd in a state
it can move to mvebu, So that only leaves netxbig_v2.c.

   Andrew

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Thomas Petazzoni]

Dear Andrew Lunn,

On Sun, 13 Apr 2014 17:59:49 +0200, Andrew Lunn wrote:

> I hope kirkwood will complete its move soon. I have Openrd in a state
> it can move to mvebu, So that only leaves netxbig_v2.c.

Nice, that would be a good move. Regarding netxbig_v2.c, looks like I
need to revive
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/188443.html.

On the mach-dove front, what is preventing the removal of the old style
cm-a510.c and dove-db-setup.c, since I see there are Device Tree for
those platforms? Maybe they are not complete? Maybe the biggest problem
is testing PCIe?

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Sebastian Hesselbarth]

On 04/13/2014 06:53 PM, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
> 
> On Sun, 13 Apr 2014 17:59:49 +0200, Andrew Lunn wrote:
> 
>> I hope kirkwood will complete its move soon. I have Openrd in a state
>> it can move to mvebu, So that only leaves netxbig_v2.c.
> 
> Nice, that would be a good move. Regarding netxbig_v2.c, looks like I
> need to revive
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/188443.html.
> 
> On the mach-dove front, what is preventing the removal of the old style
> cm-a510.c and dove-db-setup.c, since I see there are Device Tree for
> those platforms? Maybe they are not complete? Maybe the biggest problem
> is testing PCIe?

cm-a510 and dove-db have never seen any love since we moved to DT. The
board files basically only add serial devices nothing more. Nobody
complained about it and I guess we'll just drop support for them.

Consider mach-dove deprecated and dying.

Sebastian

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Arnd Bergmann]

On Sunday 13 April 2014 17:56:58 Thomas Petazzoni wrote:
> On Sun, 13 Apr 2014 17:47:15 +0200, Andrew Lunn wrote:

> > Nice to see you are checking for compatibility in the initcall. How
> > far do you think this from a multi_v5 kernel?
> 
> I haven't thought too much about this yet. I'm hoping to do more
> Orion5x DT conversion once this patch series is done, and then think
> about multiplatform support.

I've been building orion as part of my randconfig build tests
in ARCH_MULTIPLATFORM for while now, but haven't tried actually
running it. See the patch below for the very simple things I had
to change to get things to build. The Makefile hack in plat-orion
only works as long you don't try to do the same thing in any of the
other ARMv5 (kirkwood or mv78xx0) platforms as well.

The main thing missing here is support for MULTI_IRQ_HANDLER for
the ATAGS based board files. I assume you need the same thing to
let DT and ATAGS coexist within Orion already?

Other than that, I guess it's just a couple of runtime bugs like
the one Andrew pointed out here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>


diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 09bba01..d0c37e5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -563,20 +563,6 @@ config ARCH_MV78XX0
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.
 
-config ARCH_ORION5X
-	bool "Marvell Orion"
-	depends on MMU
-	select ARCH_REQUIRE_GPIOLIB
-	select CPU_FEROCEON
-	select GENERIC_CLOCKEVENTS
-	select MVEBU_MBUS
-	select PCI
-	select PLAT_ORION_LEGACY
-	help
-	  Support for the following Marvell Orion 5x series SoCs:
-	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
-	  Orion-2 (5281), Orion-1-90 (6183).
-
 config ARCH_MMP
 	bool "Marvell PXA168/910/MMP2"
 	depends on MMU
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 14f2cae..62b560e 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -1,3 +1,17 @@
+config ARCH_ORION5X
+	bool "Marvell Orion"
+	depends on MMU && ARCH_MULTI_V5
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_FEROCEON
+	select GENERIC_CLOCKEVENTS
+	select MVEBU_MBUS
+	select PCI
+	select PLAT_ORION_LEGACY
+	help
+	  Support for the following Marvell Orion 5x series SoCs:
+	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
+	  Orion-2 (5281), Orion-1-90 (6183).
+
 if ARCH_ORION5X
 
 menu "Orion Implementations"
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 45da805..c91a41d 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,3 +1,6 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+	-I$(srctree)/arch/arm/plat-orion/include
+
 obj-y				+= common.o pci.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)	+= db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)	+= rd88f5182-setup.o
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h
index a6fa9d8..a0d2887 100644
--- a/arch/arm/mach-orion5x/include/mach/irqs.h
+++ b/arch/arm/mach-orion5x/include/mach/irqs.h
@@ -54,7 +54,7 @@
 #define IRQ_ORION5X_GPIO_START	32
 #define NR_GPIO_IRQS		32
 
-#define NR_IRQS			(IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+#define ORION_IRQS		(IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
 
 
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index b78ff32..7be7c2e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARCH_ORION5X_H
 #define __ASM_ARCH_ORION5X_H
 
+#include <mach/irqs.h>
+
 /*****************************************************************************
  * Orion Address Maps
  *
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 9433605..bb17664 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,7 +1,8 @@
 #
 # Makefile for the linux kernel.
 #
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+	-I$(srctree)/arch/arm/mach-orion5x/include
 
 orion-gpio-$(CONFIG_GPIOLIB)      += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 807df14..a62b980 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -18,6 +18,7 @@
 #include <asm/exception.h>
 #include <plat/irq.h>
 #include <plat/orion-gpio.h>
+#include <mach/hardware.h>
 #include <mach/bridge-regs.h>
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Chris Moore]

Hi,

Le 13/04/2014 17:45, Thomas Petazzoni a ?crit :
> Dear Andrew Lunn,
>
> On Sun, 13 Apr 2014 17:31:50 +0200, Andrew Lunn wrote:
>
>>> -/*****************************************************************************
>>> - * 512KB NOR Flash on BOOT Device
>>> - ****************************************************************************/
>>> -
>>> -/*
>>> - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
>>> - * -type device. This could cause risks of accidentally erasing critical
>>> - * flash sectors. We thus define a single, write-protected partition covering
>>> - * the whole flash.
>>> - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
>>> - * code, break this into at least three partitions: 'u-boot code', 'u-boot
>>> - * environment' and 'whatever is left'.
>>> - */
>> Hi Thomas
>>
>> Did you check if this is still true? If it is fixed, maybe now would
>> be a good time to swap to three partitions?
> I don't know, and since the NOR contains the bootloader, and I'm not
> sure those Orion devices support UART booting, I clearly don't want to
> play too much with NOR writing, as I don't want to brick the only two
> Orion platforms that I have. So I'd prefer to leave the functionality
> as it was, and leave it to other more adventurous and interested people
> the work on improving this.
>

I subsequently added a fixup todrivers 
<http://lxr.free-electrons.com/source/drivers/>/mtd 
<http://lxr.free-electrons.com/source/drivers/mtd/>/chips 
<http://lxr.free-electrons.com/source/drivers/mtd/chips/>/cfi_cmdset_0002.c 
to correct top/bottom detection for many Macronix devices including the 
MX29LV400CBCT.
(Commit 87e92c062b19eea6054532f8143a91242f104a6f see 
http://lists.infradead.org/pipermail/linux-mtd/2008-October/023307.html)

Like Thomas, I was afraid of bricking my device so I didn't dare to 
modify and test the partitioning.
(Unfortunately I don't have working JTAG.)

Cheers,
Chris

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Chris Moore]

Sorry, my first sentence should have read:
I subsequently added a fixup to drivers/mtd/chips/cfi_cmdset_0002.c to 
correct top/bottom detection for many Macronix devices including the 
MX29LV400CBCT.

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Andrew Lunn]

> Other than that, I guess it's just a couple of runtime bugs like
> the one Andrew pointed out here.

Hi Arnd

I didn't point out a bug, i complimented Thomas in doing the right
thing with respect to multi platform.

      Andrew

[PATCH 01/29] ARM: orion5x: fix target ID for crypto SRAM window

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> In commit 4ca2c04085a1caa903e92a5fc0da25362150aac2 ('ARM: orion5x:
> Move to ID based window creation'), the mach-orion5x code was changed
> to use the new mvebu-mbus API. However, in the process, a mistake was
> made on the crypto SRAM window target ID: it should have been 0x9
> (verified in the datasheet) and not 0x0.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: stable at vger.kernel.org
> ---
> This should be backported to stable all the way to v3.12.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/mach-orion5x/common.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
> index f565f99..7548db2 100644
> --- a/arch/arm/mach-orion5x/common.h
> +++ b/arch/arm/mach-orion5x/common.h
> @@ -21,7 +21,7 @@ struct mv_sata_platform_data;
>   #define ORION_MBUS_DEVBUS_BOOT_ATTR   0x0f
>   #define ORION_MBUS_DEVBUS_TARGET(cs)  0x01
>   #define ORION_MBUS_DEVBUS_ATTR(cs)    (~(1 << cs))
> -#define ORION_MBUS_SRAM_TARGET        0x00
> +#define ORION_MBUS_SRAM_TARGET        0x09
>   #define ORION_MBUS_SRAM_ATTR          0x00
>
>   /*
>

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Arnd Bergmann]

On Monday 14 April 2014 10:01:26 Andrew Lunn wrote:
> > Other than that, I guess it's just a couple of runtime bugs like
> > the one Andrew pointed out here.
> 
> Hi Arnd
> 
> I didn't point out a bug, i complimented Thomas in doing the right
> thing with respect to multi platform.

I'm very sorry, I completely misunderstood both the code and your
comment from looking too briefly.

	Arnd

[PATCH 02/29] pinctrl: mvebu: new driver for Orion platforms

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit extends the pinctrl mvebu logic with a new driver to cover
> Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
> variants of Orion5x, which are the three ones supported by the old
> style MPP code in arch/arm/mach-orion5x/.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  91 +++++++
>   drivers/pinctrl/mvebu/Kconfig                      |   4 +
>   drivers/pinctrl/mvebu/Makefile                     |   1 +
>   drivers/pinctrl/mvebu/pinctrl-orion.c              | 261 +++++++++++++++++++++
>   4 files changed, 357 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
>   create mode 100644 drivers/pinctrl/mvebu/pinctrl-orion.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> new file mode 100644
> index 0000000..1748209
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> @@ -0,0 +1,91 @@
> +* Marvell Orion SoC pinctrl driver for mpp
> +
> +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
> +part and usage.
> +
> +Required properties:
> +- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
> +              "marvell,88f5281-pinctrl"
> +
> +- reg: two register areas, the first one describing the first two
> +  contiguous MPP registers, and the second one describing the single
> +  final MPP register, separated from the previous one.
> +
> +Available mpp pins/groups and functions:
> +Note: brackets (x) are not part of the mpp name for marvell,function and given
> +only for more detailed description in this document.
> +
> +* Marvell Orion 88f5181l
> +
> +name          pins     functions
> +================================================================================
> +mpp0          0        pci(rstout), pci(req2), gpio
> +mpp1          1        gpio, pci(gnt2)
> +mpp2          2        gpio, pci(req3), pci(pme)
> +mpp3          3        gpio, pci(gnt3)
> +mpp4          4        gpio, pci(req4)
> +mpp5          5        gpio, pci(gnt4)
> +mpp6          6        gpio, pci(req5), pci(clk)
> +mpp7          7        gpio, pci(gnt5), pci(clk)
> +mpp8          8        gpio, ge(col)
> +mpp9          9        gpio, ge(rxerr)
> +mpp10         10       gpio, ge(crs)
> +mpp11         11       gpio, ge(txerr)
> +mpp12         12       gpio, ge(txd4)
> +mpp13         13       gpio, ge(txd5)
> +mpp14         14       gpio, ge(txd6)
> +mpp15         15       gpio, ge(txd7)
> +mpp16         16       ge(rxd4)
> +mpp17         17       ge(rxd5)
> +mpp18         18       ge(rxd6)
> +mpp19         19       ge(rxd7)
> +
> +* Marvell Orion 88f5182
> +
> +name          pins     functions
> +================================================================================
> +mpp0          0        pci(rstout), pci(req2), gpio

Shouldn't the above pcie(rstout)?

The one available datasheet I have for 5182 names the function
PEX_RST_OUTn, which is PCIexpress then.

> +mpp1          1        gpio, pci(gnt2)
> +mpp2          2        gpio, pci(req3), pci(pme)

pinctrl-mvebu isn't that good with identically named functions.
You need to rename one of the "pci" functions to e.g. "pci-1".

> +mpp3          3        gpio, pci(gnt3)
> +mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
> +mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
> +mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
> +mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
> +mpp8          8        gpio, ge(col)
> +mpp9          9        gpio, ge(rxerr)
> +mpp10         10       gpio, ge(crs)
> +mpp11         11       gpio, ge(txerr)
> +mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
> +mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
> +mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
> +mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)

Four "led" prefixes above should be removed.

I guess the above comments are also valid for the other
two SoCs.

> +mpp16         16       uart1(rxd), ge(rxd4), gpio
> +mpp17         17       uart1(txd), ge(rxd5), gpio
> +mpp18         18       uart1(cts), ge(rxd6), gpio
> +mpp19         19       uart1(rts), ge(rxd7), gpio
> +
> +* Marvell Orion 88f5281
> +
> +name          pins     functions
> +================================================================================
> +mpp0          0        pci(rstout), pci(req2), gpio
> +mpp1          1        gpio, pci(gnt2)
> +mpp2          2        gpio, pci(req3), pci(pme)
> +mpp3          3        gpio, pci(gnt3)
> +mpp4          4        gpio, pci(req4), bootnand(re)
> +mpp5          5        gpio, pci(gnt4), bootnand(we)
> +mpp6          6        gpio, pci(req5), nand(re0)
> +mpp7          7        gpio, pci(gnt5), nand(we0)
> +mpp8          8        gpio, ge(col)
> +mpp9          9        gpio, ge(rxerr)
> +mpp10         10       gpio, ge(crs)
> +mpp11         11       gpio, ge(txerr)
> +mpp12         12       gpio, ge(txd4), nand(re1)
> +mpp13         13       gpio, ge(txd5), nand(we1)
> +mpp14         14       gpio, ge(txd6), nand(re2)
> +mpp15         15       gpio, ge(txd7), nand(we2)
> +mpp16         16       uart1(rxd), ge(rxd4)
> +mpp17         17       uart1(txd), ge(rxd5)
> +mpp18         18       uart1(cts), ge(rxd6)
> +mpp19         19       uart1(rts), ge(rxd7)
> diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
> index cc298fad..d6dd835 100644
> --- a/drivers/pinctrl/mvebu/Kconfig
> +++ b/drivers/pinctrl/mvebu/Kconfig
> @@ -30,4 +30,8 @@ config PINCTRL_ARMADA_XP
>   	bool
>   	select PINCTRL_MVEBU
>
> +config PINCTRL_ORION
> +	bool
> +	select PINCTRL_MVEBU
> +
>   endif
> diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
> index bc1b9f1..a0818e9 100644
> --- a/drivers/pinctrl/mvebu/Makefile
> +++ b/drivers/pinctrl/mvebu/Makefile
> @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
>   obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
>   obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
>   obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
> +obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
> diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
> new file mode 100644
> index 0000000..8312fb3
> --- /dev/null
> +++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
> @@ -0,0 +1,261 @@
> +/*
> + * Marvell Orion pinctrl driver based on mvebu pinctrl core
> + *
> + * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * The first 16 MPP pins on Orion are easy to handle: they are
> + * configured through 2 consecutive registers, located at the base
> + * address of the MPP device.
> + *
> + * However the last 4 MPP pins are handled by a register at offset
> + * 0x50 from the base address, so it is not consecutive with the first
> + * two registers.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-mvebu.h"
> +
> +static void __iomem *mpp_base;
> +static void __iomem *high_mpp_base;
> +
> +static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config)
> +{
> +	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
> +
> +	if (pid < 16) {
> +		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
> +		*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
> +	}
> +	else {
> +		*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
> +	}
> +
> +	return 0;
> +}
> +
> +static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
> +{
> +	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
> +
> +	if (pid < 16) {
> +		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
> +		u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
> +		writel(reg | (config << shift), mpp_base + off);
> +	}
> +	else {
> +		u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
> +		writel(reg | (config << shift), high_mpp_base);
> +	}
> +
> +	return 0;
> +}
> +
> +#define V(f5181l, f5182, f5281) \
> +	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
> +
> +enum orion_variant {
> +	V_5181L = V(1, 0, 0),
> +	V_5182  = V(0, 1, 0),
> +	V_5281  = V(0, 0, 1),
> +	V_ALL   = V(1, 1, 1),
> +};
> +
> +static struct mvebu_mpp_mode orion_mpp_modes[] = {
> +	MPP_MODE(0,
> +		 MPP_VAR_FUNCTION(0x0, "pci", "rstout",     V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "req2",       V_ALL),

Same comment about identically named functions.

> +		 MPP_VAR_FUNCTION(0x3, "gpio", NULL,        V_ALL)),
> +	MPP_MODE(1,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "gnt2",       V_ALL)),
> +	MPP_MODE(2,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "req3",       V_ALL),
> +		 MPP_VAR_FUNCTION(0x3, "pci", "pme",        V_ALL)),
> +	MPP_MODE(3,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "gnt3",       V_ALL)),
> +	MPP_MODE(4,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "req4",       V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "bootnand", "re",    V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",    V_5182)),
> +	MPP_MODE(5,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "gnt4",       V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "bootnand", "we",    V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",    V_5182)),
> +	MPP_MODE(6,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "pci", "clk",        V_5181L),
> +		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
> +	MPP_MODE(7,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "pci", "clk",        V_5181L),
> +		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
> +	MPP_MODE(8,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "col",         V_ALL)),
> +	MPP_MODE(9,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "rxerr",       V_ALL)),
> +	MPP_MODE(10,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "crs",         V_ALL)),
> +	MPP_MODE(11,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "txerr",       V_ALL)),
> +	MPP_MODE(12,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "txd4",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "re1",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),

...and "led" prefix, too.

> +	MPP_MODE(13,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "txd5",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "we1",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
> +	MPP_MODE(14,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "txd6",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "re2",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata0", "ledact",   V_5182)),
> +	MPP_MODE(15,
> +		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "txd7",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x4, "nand", "we2",       V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x5, "sata1", "ledact",   V_5182)),
> +	MPP_MODE(16,
> +		 MPP_VAR_FUNCTION(0x0, "uart1", "rxd",      V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "rxd4",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
> +	MPP_MODE(17,
> +		 MPP_VAR_FUNCTION(0x0, "uart1", "txd",      V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "rxd5",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
> +	MPP_MODE(18,
> +		 MPP_VAR_FUNCTION(0x0, "uart1", "cts",      V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "rxd6",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
> +	MPP_MODE(19,
> +		 MPP_VAR_FUNCTION(0x0, "uart1", "rts",      V_5182 | V_5281),
> +		 MPP_VAR_FUNCTION(0x1, "ge", "rxd7",        V_ALL),
> +		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
> +};
> +
> +static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
> +	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
> +};
> +
> +static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
> +	MPP_GPIO_RANGE(0, 0, 0, 16),
> +};
> +
> +static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
> +	MPP_GPIO_RANGE(0, 0, 0, 19),
> +};
> +
> +static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
> +	MPP_GPIO_RANGE(0, 0, 0, 16),
> +};

mv88f5181l_gpio_ranges == mv88f5281_gpio_ranges.

You can possibly join them to mv88f5x81_gpio ranges, but I have
no strong opinion about it.

> +
> +static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
> +	.variant = V_5181L,
> +	.controls = orion_mpp_controls,
> +	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
> +	.modes = orion_mpp_modes,
> +	.nmodes = ARRAY_SIZE(orion_mpp_modes),
> +	.gpioranges = mv88f5181l_gpio_ranges,
> +	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
> +};
> +
> +static struct mvebu_pinctrl_soc_info mv88f5182_info = {
> +	.variant = V_5182,
> +	.controls = orion_mpp_controls,
> +	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
> +	.modes = orion_mpp_modes,
> +	.nmodes = ARRAY_SIZE(orion_mpp_modes),
> +	.gpioranges = mv88f5182_gpio_ranges,
> +	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
> +};
> +
> +static struct mvebu_pinctrl_soc_info mv88f5281_info = {
> +	.variant = V_5281,
> +	.controls = orion_mpp_controls,
> +	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
> +	.modes = orion_mpp_modes,
> +	.nmodes = ARRAY_SIZE(orion_mpp_modes),
> +	.gpioranges = mv88f5281_gpio_ranges,
> +	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
> +};
> +
> +/*
> + * There are multiple variants of the Orion SoCs, but in terms of pin
> + * muxing, they are identical.
> + */
> +static struct of_device_id orion_pinctrl_of_match[] = {
> +	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
> +	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
> +	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
> +	{ }
> +};
> +
> +static int orion_pinctrl_probe(struct platform_device *pdev)
> +{
> +	const struct of_device_id *match =
> +		of_match_device(orion_pinctrl_of_match, &pdev->dev);
> +	struct resource *res;
> +
> +	pdev->dev.platform_data = (void*) match->data;

Useless (void *) cast?

Sebastian

> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	mpp_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(mpp_base))
> +		return PTR_ERR(mpp_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(high_mpp_base))
> +		return PTR_ERR(high_mpp_base);
> +
> +	return mvebu_pinctrl_probe(pdev);
> +}
> +
> +static int orion_pinctrl_remove(struct platform_device *pdev)
> +{
> +	return mvebu_pinctrl_remove(pdev);
> +}
> +
> +static struct platform_driver orion_pinctrl_driver = {
> +	.driver = {
> +		.name = "orion-pinctrl",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_match_ptr(orion_pinctrl_of_match),
> +	},
> +	.probe = orion_pinctrl_probe,
> +	.remove = orion_pinctrl_remove,
> +};
> +
> +module_platform_driver(orion_pinctrl_driver);
> +
> +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
> +MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
> +MODULE_LICENSE("GPL v2");
>

[PATCH 03/29] clk: mvebu: add Orion5x clock driver

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit adds a core clock driver for the Orion5x SoC, with support
> for the tclk, the CPU frequency and the DDR frequency. All the details
> about the Sample-At-Reset register were extracted from the U-Boot
> sources for Orion5x.
>
> Note that Orion5x does not have gatable clocks, so this core clock
> driver is sufficient to support clocking on Orion5x platforms.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../devicetree/bindings/clock/mvebu-core-clock.txt |   8 +
>   drivers/clk/mvebu/Kconfig                          |   4 +
>   drivers/clk/mvebu/Makefile                         |   1 +
>   drivers/clk/mvebu/orion.c                          | 212 +++++++++++++++++++++
>   4 files changed, 225 insertions(+)
>   create mode 100644 drivers/clk/mvebu/orion.c
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
> index 307a503..dc5ea5b 100644
> --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
> @@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
>    2 = l2clk  (L2 Cache clock derived from CPU0 clock)
>    3 = ddrclk (DDR controller clock derived from CPU0 clock)
>
> +The following is a list of provided IDs and clock names on Orion5x:
> + 0 = tclk   (Internal Bus clock)
> + 1 = cpuclk (CPU0 clock)
> + 2 = ddrclk (DDR controller clock derived from CPU0 clock)
> +

Maybe it is time to introduce a dt-binding include to remember
us to provide the same for the other SoCs, too?

>   Required properties:
>   - compatible : shall be one of the following:
>   	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
> @@ -38,6 +43,9 @@ Required properties:
>   	"marvell,dove-core-clock" - for Dove SoC core clocks
>   	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
>   	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
> +	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC

Do you know how different 5182 and 5182L are? In the pinctrl driver
there was an additional L at the end, here it is missing.

The 5182 datasheet I am looking at, is titled "88F5182L Datasheet" but
uses 88F5182 all over. Maybe we can drop the L entirely.

> +	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
> +	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
>   - reg : shall be the register address of the Sample-At-Reset (SAR) register
>   - #clock-cells : from common clock binding; shall be set to 1
[...]
> diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
> new file mode 100644
> index 0000000..005aa2f
> --- /dev/null
> +++ b/drivers/clk/mvebu/orion.c
> @@ -0,0 +1,212 @@
> +/*
> + * Marvell Orion SoC clocks
> + *
> + * Copyright (C) 2014 Thomas Petazzoni
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include "common.h"
> +
> +static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
> +	{ .id = 0, .name = "ddrclk", }
> +};
> +
> +/*
> + * Orion 5182
> + */
> +
> +#define SAR_MV88F5182_TCLK_FREQ      0x8

nit: as this is a shift, I'd use decimal values.

> +#define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
> +
> +static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
> +		SAR_MV88F5182_TCLK_FREQ_MASK;
> +	if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;
> +	else
> +		return 0;
> +}
> +
> +#define SAR_MV88F5182_CPU_FREQ       0x4

ditto.

> +#define SAR_MV88F5182_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
> +		SAR_MV88F5182_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1)
> +		return 400000000;
> +	else if (opt == 2)
> +		return 400000000;

join the two above...

> +	else if (opt == 3)
> +		return 500000000;
> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
> +		SAR_MV88F5182_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;

.. like you did here.

> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}
> +}
> +
> +static const struct coreclk_soc_desc mv88f5182_coreclks = {
> +	.get_tclk_freq = mv88f5182_get_tclk_freq,
> +	.get_cpu_freq = mv88f5182_get_cpu_freq,
> +	.get_clk_ratio = mv88f5182_get_clk_ratio,
> +	.ratios = orion_coreclk_ratios,
> +	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
> +};
> +
> +static void __init mv88f5182_clk_init(struct device_node *np)
> +{
> +	return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
> +}
> +
> +CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
> +
> +/*
> + * Orion 5281
> + */
> +
> +static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
> +{
> +	/* On 5281, tclk is always 166 Mhz */
> +	return 166666667;
> +}
> +
> +#define SAR_MV88F5281_CPU_FREQ       0x4

same nit for the hex/decimal value.

> +#define SAR_MV88F5281_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
> +		SAR_MV88F5281_CPU_FREQ_MASK;
> +	if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;
> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
> +		SAR_MV88F5281_CPU_FREQ_MASK;
> +	if (opt == 1) {
> +		*mult = 1;
> +		*div = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div = 3;
> +	} else {
> +		*mult = 0;
> +		*div = 1;
> +	}
> +}
> +
> +static const struct coreclk_soc_desc mv88f5281_coreclks = {
> +	.get_tclk_freq = mv88f5281_get_tclk_freq,
> +	.get_cpu_freq = mv88f5281_get_cpu_freq,
> +	.get_clk_ratio = mv88f5281_get_clk_ratio,
> +	.ratios = orion_coreclk_ratios,
> +	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
> +};
> +
> +static void __init mv88f5281_clk_init(struct device_node *np)
> +{
> +	return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
> +}
> +
> +CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
> +
> +/*
> + * Orion 6183
> + */
> +
> +#define SAR_MV88F6183_TCLK_FREQ      0x9

ditto.

> +#define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
> +
> +static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
> +		SAR_MV88F6183_TCLK_FREQ_MASK;
> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 166666667;
> +	else
> +		return 0;
> +}
> +
> +#define SAR_MV88F6183_CPU_FREQ       0x1

ditto.

Besides the dt-include and nits,

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> +#define SAR_MV88F6183_CPU_FREQ_MASK  0x3f
> +
> +static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
> +		SAR_MV88F6183_CPU_FREQ_MASK;
> +	if (opt == 9)
> +		return 333333333;
> +	else if (opt == 17)
> +		return 400000000;
> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
> +		SAR_MV88F6183_CPU_FREQ_MASK;
> +	if (opt == 9 || opt == 17) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}
> +}
> +
> +static const struct coreclk_soc_desc mv88f6183_coreclks = {
> +	.get_tclk_freq = mv88f6183_get_tclk_freq,
> +	.get_cpu_freq = mv88f6183_get_cpu_freq,
> +	.get_clk_ratio = mv88f6183_get_clk_ratio,
> +	.ratios = orion_coreclk_ratios,
> +	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
> +};
> +
> +
> +static void __init mv88f6183_clk_init(struct device_node *np)
> +{
> +	return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
> +}
> +
> +CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);
>

[PATCH 04/29] memory: mvebu-devbus: fix the conversion of the bus width

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> According to the Armada 370 and Armada XP datasheets, the part of the
> Device Bus register that configure the bus width should contain 0 for
> a 8 bits bus width, and 1 for a 16 bits bus width (other values are
> unsupported/reserved).
>
> However, the current conversion done in the driver to convert from a
> bus width in bits to the value expected by the register leads to
> setting the register to 1 for a 8 bits bus, and 2 for a 16 bits bus.
>
> This commit fixes that by adjusting the conversion logic.
>
> This patch fixes a bug that was introduced in
> 3edad321b1bd2e6c8b5f38146c115c8982438f06 ('drivers: memory: Introduce
> Marvell EBU Device Bus driver'), which was merged in v3.11.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: stable at vger.kernel.org
> ---
>   drivers/memory/mvebu-devbus.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
> index 110c036..b82cdf1 100644
> --- a/drivers/memory/mvebu-devbus.c
> +++ b/drivers/memory/mvebu-devbus.c
> @@ -108,8 +108,12 @@ static int devbus_set_timing_params(struct devbus *devbus,
>   			node->full_name);
>   		return err;
>   	}
> -	/* Convert bit width to byte width */
> -	r.bus_width /= 8;
> +
> +	/*
> +	 * The bus width is encoded into the register as 0 for 8 bits,
> +	 * and 1 for 16 bits, so we do the necessary conversion here.
> +	 */
> +	r.bus_width = (r.bus_width / 8) - 1;

I guess the next larger register value would be 0x2 for 32b? I cannot
tell, if there is any SoC spending 32 pins on this, but the correct
formula would possibly include ld().

Sebastian

>
>   	err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
>   				 &r.badr_skew);
>

[PATCH 05/29] memory: mvebu-devbus: use ARMADA_ prefix in defines

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> The mvebu-devbus driver currently only supports the Armada 370/XP
> family, but it can also cover the Orion5x family. However, the Orion5x
> family has a different organization of the register. Therefore, in
> preparation to the introduction of Orion5x support, we rename the
> Armada 370/XP specific definitions to have an ARMADA_ prefix.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
>   1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
> index b82cdf1..84746e3 100644
> --- a/drivers/memory/mvebu-devbus.c
> +++ b/drivers/memory/mvebu-devbus.c
> @@ -30,19 +30,19 @@
>   #include <linux/platform_device.h>
>
>   /* Register definitions */
> -#define DEV_WIDTH_BIT		30
> -#define BADR_SKEW_BIT		28
> -#define RD_HOLD_BIT		23
> -#define ACC_NEXT_BIT		17
> -#define RD_SETUP_BIT		12
> -#define ACC_FIRST_BIT		6
> +#define ARMADA_DEV_WIDTH_BIT		30
> +#define ARMADA_BADR_SKEW_BIT		28
> +#define ARMADA_RD_HOLD_BIT		23
> +#define ARMADA_ACC_NEXT_BIT		17
> +#define ARMADA_RD_SETUP_BIT		12
> +#define ARMADA_ACC_FIRST_BIT		6

I guess the correct terminology would be _SHIFT.
Also, if it is a single bit, I'd expect BIT(x)
instead of shifting a one.

Anyway, you are not directly responsible for it.

Sebastian

>
> -#define SYNC_ENABLE_BIT		24
> -#define WR_HIGH_BIT		16
> -#define WR_LOW_BIT		8
> +#define ARMADA_SYNC_ENABLE_BIT		24
> +#define ARMADA_WR_HIGH_BIT		16
> +#define ARMADA_WR_LOW_BIT		8
>
> -#define READ_PARAM_OFFSET	0x0
> -#define WRITE_PARAM_OFFSET	0x4
> +#define ARMADA_READ_PARAM_OFFSET	0x0
> +#define ARMADA_WRITE_PARAM_OFFSET	0x4
>
>   struct devbus_read_params {
>   	u32 bus_width;
> @@ -171,31 +171,31 @@ static int devbus_set_timing_params(struct devbus *devbus,
>   		return err;
>
>   	/* Set read timings */
> -	value = r.bus_width << DEV_WIDTH_BIT |
> -		r.badr_skew << BADR_SKEW_BIT |
> -		r.rd_hold   << RD_HOLD_BIT   |
> -		r.acc_next  << ACC_NEXT_BIT  |
> -		r.rd_setup  << RD_SETUP_BIT  |
> -		r.acc_first << ACC_FIRST_BIT |
> +	value = r.bus_width << ARMADA_DEV_WIDTH_BIT |
> +		r.badr_skew << ARMADA_BADR_SKEW_BIT |
> +		r.rd_hold   << ARMADA_RD_HOLD_BIT   |
> +		r.acc_next  << ARMADA_ACC_NEXT_BIT  |
> +		r.rd_setup  << ARMADA_RD_SETUP_BIT  |
> +		r.acc_first << ARMADA_ACC_FIRST_BIT |
>   		r.turn_off;
>
>   	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
> -		devbus->base + READ_PARAM_OFFSET,
> +		devbus->base + ARMADA_READ_PARAM_OFFSET,
>   		value);
>
> -	writel(value, devbus->base + READ_PARAM_OFFSET);
> +	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
>
>   	/* Set write timings */
> -	value = w.sync_enable  << SYNC_ENABLE_BIT |
> -		w.wr_low       << WR_LOW_BIT      |
> -		w.wr_high      << WR_HIGH_BIT     |
> +	value = w.sync_enable  << ARMADA_SYNC_ENABLE_BIT |
> +		w.wr_low       << ARMADA_WR_LOW_BIT      |
> +		w.wr_high      << ARMADA_WR_HIGH_BIT     |
>   		w.ale_wr;
>
>   	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
> -		devbus->base + WRITE_PARAM_OFFSET,
> +		devbus->base + ARMADA_WRITE_PARAM_OFFSET,
>   		value);
>
> -	writel(value, devbus->base + WRITE_PARAM_OFFSET);
> +	writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
>
>   	return 0;
>   }
>

[PATCH 06/29] memory: mvebu-devbus: split functions

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> The mvebu-devbus driver currently only supports the Armada 370/XP
> family, but it can also cover the Orion5x family. However, the Orion5x
> family has a different organization of the registers.
>
> Therefore, in preparation to the introduction of Orion5x support, we
> separate into two functions the code that 1/ retrieves the timing
> parameters from the Device Tree and 2/ applies those timings
> parameters into the hardware registers.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

If you change the formula in patch 4/29, the same applies here.

Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

[PATCH 07/29] memory: mvebu-devbus: add Orion5x support

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit adds support for the Orion5x family of Marvell processors
> into the mvebu-devbus driver. It differs from the already supported
> Armada 370/XP by:
>
>   * Having a single register (instead of two) for doing all the timing
>     configuration.
>
>   * Having a few less timing configuration parameters.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../bindings/memory-controllers/mvebu-devbus.txt   | 25 ++++--
>   drivers/memory/mvebu-devbus.c                      | 95 +++++++++++++++++-----
>   2 files changed, 94 insertions(+), 26 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
> index 653c90c..aff8e9e 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
> @@ -6,10 +6,11 @@ The actual devices are instantiated from the child nodes of a Device Bus node.
>
>   Required properties:
>
> - - compatible:          Currently only Armada 370/XP SoC are supported,
> -                        with this compatible string:
> + - compatible:          Armada 370/XP SoC are supported using the
> +                        "marvell,mvebu-devbus" compatible string.
>
> -                        marvell,mvebu-devbus
> +                        Orion5x SoC are supported using the
> +                        "marvell,orion-devbus" compatible string.
>
>    - reg:                 A resource specifier for the register space.
>                           This is the base address of a chip select within
> @@ -22,7 +23,7 @@ Required properties:
>                           integer values for each chip-select line in use:
>                           0 <physical address of mapping> <size>
>
> -Mandatory timing properties for child nodes:
> +Timing properties for child nodes:
>
>   Read parameters:
>
> @@ -30,21 +31,26 @@ Read parameters:
>                           drive the AD bus after the completion of a device read.
>                           This prevents contentions on the Device Bus after a read
>                           cycle from a slow device.
> +			Mandatory.
>
> - - devbus,bus-width:    Defines the bus width (e.g. <16>)
> + - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
> +   			Mandatory.
>
>    - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
>                           to read data sample. This parameter is useful for
>                           synchronous pipelined devices, where the address
>                           precedes the read data by one or two cycles.
> +			Mandatory.
>
>    - devbus,acc-first-ps: Defines the time delay from the negation of
>                           ALE[0] to the cycle that the first read data is sampled
>                           by the controller.
> +			Mandatory.
>
>    - devbus,acc-next-ps:  Defines the time delay between the cycle that
>                           samples data N and the cycle that samples data N+1
>                           (in burst accesses).
> +			Mandaory.
>
>    - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
>   			DEV_OEn assertion. If set to 0 (default),
> @@ -52,6 +58,8 @@ Read parameters:
>                           This parameter has no affect on <acc-first-ps> parameter
>                           (no affect on first data sample). Set <rd-setup-ps>
>                           to a value smaller than <acc-first-ps>.
> +			Mandatory with "mvebu-devbus" compatible string.
> +			Ignored otherwise.

nit:

Mandatory for "mvebu-devbus" compatible string,
ignored otherwise.

>    - devbus,rd-hold-ps:   Defines the time between the last data sample to the
>   			de-assertion of DEV_CSn. If set to 0 (default),
> @@ -62,16 +70,20 @@ Read parameters:
>                           last data sampled. Also this parameter has no
>                           affect on <turn-off-ps> parameter.
>                           Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
> +			Mandatory with "mvebu-devbus" compatible string.
> +			Ignored otherwise.

ditto.

>
>   Write parameters:
>
>    - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
>   			to the DEV_WEn assertion.
> +			Mandatory.
>
>    - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
>                           A[2:0] and Data are kept valid as long as DEV_WEn
>                           is active. This parameter defines the setup time of
>                           address and data to DEV_WEn rise.
> +			Mandatory.
>
>    - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
>                           inactive (high) between data beats of a burst write.
> @@ -79,10 +91,13 @@ Write parameters:
>                           <wr-high-ps> - <tick> ps.
>   			This parameter defines the hold time of address and
>   			data after DEV_WEn rise.
> +			Mandatory.
>
>    - devbus,sync-enable: Synchronous device enable.
>                          1: True
>                          0: False
> +		       Mandatory with "mvebu-devbus" compatible string.
> +		       Ignored otherwise.

ditto.

>   An example for an Armada XP GP board, with a 16 MiB NOR device as child
>   is showed below. Note that the Device Bus driver is in charge of allocating
> diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
> index 8df5b2b..59d8151 100644
> --- a/drivers/memory/mvebu-devbus.c
> +++ b/drivers/memory/mvebu-devbus.c
> @@ -2,7 +2,7 @@
>    * Marvell EBU SoC Device Bus Controller
>    * (memory controller for NOR/NAND/SRAM/FPGA devices)
>    *
> - * Copyright (C) 2013 Marvell
> + * Copyright (C) 2013-2014 Marvell
>    *
>    * This program is free software: you can redistribute it and/or modify
>    * it under the terms of the GNU General Public License as published by
> @@ -44,6 +44,22 @@
>   #define ARMADA_READ_PARAM_OFFSET	0x0
>   #define ARMADA_WRITE_PARAM_OFFSET	0x4
>
> +#define ORION_RESERVED			(0x2 << 30)
> +#define ORION_BADR_SKEW_BIT		28
> +#define ORION_WR_HIGH_EXT_BIT		27
> +#define ORION_WR_LOW_EXT_BIT		26
> +#define ORION_ALE_WR_EXT_BIT		25
> +#define ORION_ACC_NEXT_EXT_BIT		24
> +#define ORION_ACC_FIRST_EXT_BIT		23
> +#define ORION_TURN_OFF_EXT_BIT		22
> +#define ORION_DEV_WIDTH_BIT		20
> +#define ORION_WR_HIGH_BIT		17
> +#define ORION_WR_LOW_BIT		14
> +#define ORION_ALE_WR_BIT		11
> +#define ORION_ACC_NEXT_BIT		7
> +#define ORION_ACC_FIRST_BIT		3
> +#define ORION_TURN_OFF_BIT		0

Same comment about _BIT instead of _SHIFT and not using BIT().

> +
>   struct devbus_read_params {
>   	u32 bus_width;
>   	u32 badr_skew;
> @@ -96,7 +112,6 @@ static int devbus_get_timing_params(struct devbus *devbus,
>   {
>   	int err;
>
> -	/* Get read timings */
>   	err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
>   	if (err < 0) {
>   		dev_err(devbus->dev,
> @@ -131,24 +146,25 @@ static int devbus_get_timing_params(struct devbus *devbus,
>   	if (err < 0)
>   		return err;
>
> -	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
> -				 &r->rd_setup);
> -	if (err < 0)
> -		return err;
> -
> -	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
> -				 &r->rd_hold);
> -	if (err < 0)
> -		return err;
> -
> -	/* Get write timings */
> -	err = of_property_read_u32(node, "devbus,sync-enable",
> -				  &w->sync_enable);
> -	if (err < 0) {
> -		dev_err(devbus->dev,
> -			"%s has no 'devbus,sync-enable' property\n",
> -			node->full_name);
> -		return err;
> +	if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
> +		err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
> +					  &r->rd_setup);
> +		if (err < 0)
> +			return err;
> +
> +		err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
> +					  &r->rd_hold);
> +		if (err < 0)
> +			return err;
> +
> +		err = of_property_read_u32(node, "devbus,sync-enable",
> +					   &w->sync_enable);
> +		if (err < 0) {
> +			dev_err(devbus->dev,
> +				"%s has no 'devbus,sync-enable' property\n",
> +				node->full_name);
> +			return err;
> +		}
>   	}
>
>   	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
> @@ -169,6 +185,39 @@ static int devbus_get_timing_params(struct devbus *devbus,
>   	return 0;
>   }
>
> +static void devbus_orion_set_timing_params(struct devbus *devbus,
> +					  struct device_node *node,
> +					  struct devbus_read_params *r,
> +					  struct devbus_write_params *w)
> +{
> +	u32 value;
> +
> +	/*
> +	 * The hardware designers found it would be a good idea to
> +	 * split most of the values in the register into two fields:
> +	 * one containing all the low-order bits, and another one
> +	 * containing just the high-order bit. For all of those
> +	 * fields, we have to split the value into these two parts.
> +	 */
> +	value = (r->turn_off   & 0x7) << ORION_TURN_OFF_BIT  |
> +		(r->acc_first  & 0xF) << ORION_ACC_FIRST_BIT |
> +		(r->acc_next   & 0xF) << ORION_ACC_NEXT_BIT  |
> +		(w->ale_wr     & 0x7) << ORION_ALE_WR_BIT    |
> +		(w->wr_low     & 0x7) << ORION_WR_LOW_BIT    |
> +		(w->wr_high    & 0x7) << ORION_WR_HIGH_BIT   |
> +		r->bus_width          << ORION_DEV_WIDTH_BIT |
> +		((r->turn_off  & 0x8)  ? BIT(ORION_TURN_OFF_EXT_BIT)  : 0) |
> +		((r->acc_first & 0x10) ? BIT(ORION_ACC_FIRST_EXT_BIT) : 0) |
> +		((r->acc_next  & 0x10) ? BIT(ORION_ACC_NEXT_EXT_BIT)  : 0) |
> +		((w->ale_wr    & 0x8)  ? BIT(ORION_ALE_WR_EXT_BIT)    : 0) |
> +		((w->wr_low    & 0x8)  ? BIT(ORION_WR_LOW_EXT_BIT)    : 0) |
> +		((w->wr_high   & 0x8)  ? BIT(ORION_WR_HIGH_EXT_BIT)   : 0) |

I know you will scream in pain, but there should be _MASK for the magic
numbers above :P

> +		(r->badr_skew << ORION_BADR_SKEW_BIT) |
> +		ORION_RESERVED;
> +
> +	writel(value, devbus->base);
> +}
> +
>   static void devbus_armada_set_timing_params(struct devbus *devbus,
>   					   struct device_node *node,
>   					   struct devbus_read_params *r,
> @@ -248,7 +297,10 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
>   		return err;
>
>   	/* Set the new timing parameters */
> -	devbus_armada_set_timing_params(devbus, node, &r, &w);
> +	if (of_device_is_compatible(node, "marvell,orion-devbus"))
> +		devbus_orion_set_timing_params(devbus, node, &r, &w);
> +	else
> +		devbus_armada_set_timing_params(devbus, node, &r, &w);
>
>   	/*
>   	 * We need to create a child device explicitly from here to
> @@ -264,6 +316,7 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
>
>   static const struct of_device_id mvebu_devbus_of_match[] = {
>   	{ .compatible = "marvell,mvebu-devbus" },
> +	{ .compatible = "marvell,orion-devbus" },
>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
>

[PATCH 08/29] ARM: orion5x: move interrupt controller node into ocp

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> The interrupt controller node was located outside of the ocp at f1000000
> node, which doesn't make much sense: like any other device, the
> interrupt controller has registers located in the "Internal Registers
> Window", so it is much more logical to have it under the ocp at f1000000
> node.
>
> It is even more important as we are going to move Orion5x to use the
> Device Tree binding of the mvebu-mbus driver.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x.dtsi | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index 174d892..da57fb9 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -17,13 +17,6 @@
>   		gpio0 = &gpio0;
>   	};
>
> -	intc: interrupt-controller {
> -		compatible = "marvell,orion-intc";
> -		interrupt-controller;
> -		#interrupt-cells = <1>;
> -		reg = <0xf1020200 0x08>;
> -	};
> -
>   	ocp at f1000000 {
>   		compatible = "simple-bus";
>   		ranges = <0x00000000 0xf1000000 0x4000000
> @@ -79,6 +72,13 @@
>   			status = "disabled";
>   		};
>
> +		intc: interrupt-controller at 20200 {
> +			compatible = "marvell,orion-intc";
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			reg = <0x20200 0x08>;
> +		};
> +
>   		wdt at 20300 {
>   			compatible = "marvell,orion-wdt";
>   			reg = <0x20300 0x28>;
>

[PATCH 09/29] ARM: orion5x: switch to preprocessor includes in DT

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit switches the Orion5x Device Tree files to use C
> preprocessor based includes, as it will allow us to use definitions
> from header files in future commits.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 3 ++-
>   arch/arm/boot/dts/orion5x.dtsi                            | 2 +-
>   2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index 5ed6c13..0245bb3 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -7,7 +7,8 @@
>    */
>
>   /dts-v1/;
> -/include/ "orion5x.dtsi"
> +
> +#include "orion5x.dtsi"
>
>   / {
>   	model = "LaCie Ethernet Disk mini V2";
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index da57fb9..2364e3d 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -6,7 +6,7 @@
>    * warranty of any kind, whether express or implied.
>    */
>
> -/include/ "skeleton.dtsi"
> +#include "skeleton.dtsi"
>
>   / {
>   	model = "Marvell Orion5x SoC";
>

[PATCH 10/29] ARM: orion5x: use existing dt-bindings include for Device Tree files

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> The orion5x-lacie-ethernet-disk-mini-v2.dts can benefit from using
> gpio.h and input.h dt-bindings headers to replace hardcoded values by
> more meaningful macros.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index 0245bb3..24f1ce7 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -8,6 +8,8 @@
>
>   /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
>   #include "orion5x.dtsi"
>
>   / {
> @@ -40,8 +42,8 @@
>   		#size-cells = <0>;
>   		button at 1 {
>   			label = "Power-on Switch";
> -			linux,code = <116>; /* KEY_POWER */
> -			gpios = <&gpio0 18 0>;
> +			linux,code = <KEY_POWER>;
> +			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
>   		};
>   	};
>
> @@ -50,7 +52,7 @@
>
>   		led at 1 {
>   			label = "power:blue";
> -			gpios = <&gpio0 16 1>;
> +			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
>   		};
>   	};
>   };
>

[PATCH 11/29] ARM: orion5x: convert DT to use the mvebu-mbus driver

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit switches the Orion5x Device Tree files to use the DT
> representation and probing for the mvebu-mbus driver. The changes are
> mainly:
>
>   * Re-organize the DT to follow the same organization as the one used
>     on Armada 370/XP, which is needed for mvebu-mbus to work: a
>     top-level soc { ... } node, which corresponds to the MBus bus, and
>     a sub-node internal-regs { ... } for all peripherals whose register
>     sit only in the "Internal Register Window". This change re-indents
>     by one level the definition of all nodes in the Device Tree, which
>     explains the large change.
>
>   * Use custom functions orion5x_dt_init_early() and
>     orion5x_dt_init_time() instead of orion5x_init_early() and
>     orion5x_timer_init() as we now want the MBus driver to be probed
>     from the Device Tree. We still use the old-style timer
>     initialization, but that will be changed in a followup commit.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |  23 +-
>   arch/arm/boot/dts/orion5x-mv88f5182.dtsi           |  24 ++
>   arch/arm/boot/dts/orion5x.dtsi                     | 245 +++++++++++----------
>   arch/arm/mach-orion5x/board-dt.c                   |  19 +-
>   4 files changed, 181 insertions(+), 130 deletions(-)
>   create mode 100644 arch/arm/boot/dts/orion5x-mv88f5182.dtsi
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index 24f1ce7..d66d2fa 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -10,7 +10,7 @@
>
>   #include <dt-bindings/gpio/gpio.h>
>   #include <dt-bindings/input/input.h>
> -#include "orion5x.dtsi"
> +#include "orion5x-mv88f5182.dtsi"
>
>   / {
>   	model = "LaCie Ethernet Disk mini V2";
> @@ -24,15 +24,20 @@
>   		bootargs = "console=ttyS0,115200n8 earlyprintk";

+ linux,stdout-path = &uart0;

You need labels for it in the SoC dtsi and probably the "linux,"
prefix has already been removed.

I am having a hard time with this and missing node labels on
barebox for kirkwood already. So it would be good to not make
the same mistakes on Orion5x again.

>   	};
>
> -	ocp at f1000000 {
> -		serial at 12000 {
> -			clock-frequency = <166666667>;
> -			status = "okay";
> -		};
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
> +
> +		internal-regs {
> +			serial at 12000 {
> +				clock-frequency = <166666667>;

With node labels, you don't have to replay bus nodes here again
but can just do

&uart0 {
	status = "okay";
};

Also, the clock-frequency property should rather been clocks
and part of SoC dtsi. IIRC, Andrew already mentioned it.

> +				status = "okay";
> +			};
>
> -		sata at 80000 {
> -			status = "okay";
> -			nr-ports = <2>;
> +			sata at 80000 {

Same comment about node labels for sata.

> +				status = "okay";
> +				nr-ports = <2>;

Not your problem right now, but sata binding and nr-ports
property is broken. It doesn't allow us to distinguish
clocks, sata-phys, and most important does not allow to
disable port0 while using port1.

We should really have a look at it soon.

> +			};
>   		};
>   	};
>
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> new file mode 100644
> index 0000000..ddfb4d1
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include "orion5x.dtsi"
> +
> +/ {
> +	compatible = "marvell,orion5x-88f5182", "marvell,orion5x";
> +
> +	soc {
> +		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
> +
> +		internal-regs {
> +			mbusc: mbus-controller at 20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x1500 0x20>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index 2364e3d..31d46e6 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -8,6 +8,8 @@
>
>   #include "skeleton.dtsi"
>
> +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
> +
>   / {
>   	model = "Marvell Orion5x SoC";
>   	compatible = "marvell,orion5x";
> @@ -17,149 +19,154 @@
>   		gpio0 = &gpio0;
>   	};
>
> -	ocp at f1000000 {
> -		compatible = "simple-bus";
> -		ranges = <0x00000000 0xf1000000 0x4000000
> -		          0xf2200000 0xf2200000 0x0000800>;
> -		#address-cells = <1>;
> +	soc {
> +		#address-cells = <2>;
>   		#size-cells = <1>;
> +		controller = <&mbusc>;
>
> -		gpio0: gpio at 10100 {
> -			compatible = "marvell,orion-gpio";
> -			#gpio-cells = <2>;
> -			gpio-controller;
> -			reg = <0x10100 0x40>;
> -			ngpios = <32>;
> -			interrupt-controller;
> -			#interrupt-cells = <2>;
> -			interrupts = <6>, <7>, <8>, <9>;
> -		};
> -
> -		spi at 10600 {
> -			compatible = "marvell,orion-spi";
> +		internal-regs {
> +			compatible = "simple-bus";
>   			#address-cells = <1>;
> -			#size-cells = <0>;
> -			cell-index = <0>;
> -			reg = <0x10600 0x28>;
> -			status = "disabled";
> -		};
> -
> -		i2c at 11000 {
> -			compatible = "marvell,mv64xxx-i2c";
> -			reg = <0x11000 0x20>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			interrupts = <5>;
> -			clock-frequency = <100000>;
> -			status = "disabled";
> -		};
> +			#size-cells = <1>;
> +			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
> +
> +			gpio0: gpio at 10100 {
> +				compatible = "marvell,orion-gpio";
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				reg = <0x10100 0x40>;
> +				ngpios = <32>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <6>, <7>, <8>, <9>;
> +			};
>
> -		serial at 12000 {
> -			compatible = "ns16550a";
> -			reg = <0x12000 0x100>;
> -			reg-shift = <2>;
> -			interrupts = <3>;
> -			/* set clock-frequency in board dts */
> -			status = "disabled";
> -		};
> +			spi at 10600 {

Please add a node label.

> +				compatible = "marvell,orion-spi";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				cell-index = <0>;
> +				reg = <0x10600 0x28>;
> +				status = "disabled";
> +			};
>
> -		serial at 12100 {
> -			compatible = "ns16550a";
> -			reg = <0x12100 0x100>;
> -			reg-shift = <2>;
> -			interrupts = <4>;
> -			/* set clock-frequency in board dts */
> -			status = "disabled";
> -		};
> +			i2c at 11000 {

ditto.

> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11000 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <5>;
> +				clock-frequency = <100000>;
> +				status = "disabled";
> +			};
>
> -		intc: interrupt-controller at 20200 {
> -			compatible = "marvell,orion-intc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> -			reg = <0x20200 0x08>;
> -		};
> +			serial at 12000 {

ditto.

> +				compatible = "ns16550a";
> +				reg = <0x12000 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <3>;
> +				/* set clock-frequency in board dts */

clocks = <&reference-to-tclk>;

> +				status = "disabled";
> +			};
>
> -		wdt at 20300 {
> -			compatible = "marvell,orion-wdt";
> -			reg = <0x20300 0x28>;
> -			status = "okay";
> -		};
> +			serial at 12100 {

ditto.

> +				compatible = "ns16550a";
> +				reg = <0x12100 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <4>;
> +				/* set clock-frequency in board dts */

clocks = <&reference-to-tclk>;

> +				status = "disabled";
> +			};
>
> -		ehci at 50000 {
> -			compatible = "marvell,orion-ehci";
> -			reg = <0x50000 0x1000>;
> -			interrupts = <17>;
> -			status = "disabled";
> -		};
> +			intc: interrupt-controller at 20200 {
> +				compatible = "marvell,orion-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x20200 0x08>;
> +			};
>
> -		xor at 60900 {
> -			compatible = "marvell,orion-xor";
> -			reg = <0x60900 0x100
> -			       0x60b00 0x100>;
> -			status = "okay";
> +			wdt at 20300 {

I suggest to keep on adding node labels for everything.

> +				compatible = "marvell,orion-wdt";
> +				reg = <0x20300 0x28>;
> +				status = "okay";
> +			};
>
> -			xor00 {
> -			      interrupts = <30>;
> -			      dmacap,memcpy;
> -			      dmacap,xor;
> +			ehci at 50000 {

Please add a node label.

> +				compatible = "marvell,orion-ehci";
> +				reg = <0x50000 0x1000>;
> +				interrupts = <17>;
> +				status = "disabled";
>   			};
> -			xor01 {
> -			      interrupts = <31>;
> -			      dmacap,memcpy;
> -			      dmacap,xor;
> -			      dmacap,memset;
> +
> +			xor at 60900 {

ditto, also ePAPR suggests "dma-controller" as node name,
so this should become:

xor0: dma-controller at 60900 {
	...
};

> +				compatible = "marvell,orion-xor";
> +				reg = <0x60900 0x100
> +				       0x60b00 0x100>;
> +				status = "okay";
> +
> +				xor00 {
> +				      interrupts = <30>;
> +				      dmacap,memcpy;
> +				      dmacap,xor;
> +				};
> +				xor01 {
> +				      interrupts = <31>;
> +				      dmacap,memcpy;
> +				      dmacap,xor;
> +				      dmacap,memset;
> +				};
>   			};
> -		};
>
> -		eth: ethernet-controller at 72000 {
> -			compatible = "marvell,orion-eth";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			reg = <0x72000 0x4000>;
> -			marvell,tx-checksum-limit = <1600>;
> -			status = "disabled";
> -
> -			ethernet-port at 0 {
> -				compatible = "marvell,orion-eth-port";
> -				reg = <0>;
> -				/* overwrite MAC address in bootloader */
> -				local-mac-address = [00 00 00 00 00 00];
> -				/* set phy-handle property in board file */
> +			eth: ethernet-controller at 72000 {
> +				compatible = "marvell,orion-eth";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0x72000 0x4000>;
> +				marvell,tx-checksum-limit = <1600>;
> +				status = "disabled";
> +
> +				ethernet-port at 0 {

Please add a node label for the port, too.

> +					compatible = "marvell,orion-eth-port";
> +					reg = <0>;
> +					/* overwrite MAC address in bootloader */
> +					local-mac-address = [00 00 00 00 00 00];
> +					/* set phy-handle property in board file */
> +				};
>   			};
> -		};
>
> -		mdio: mdio-bus at 72004 {
> -			compatible = "marvell,orion-mdio";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			reg = <0x72004 0x84>;
> -			interrupts = <22>;
> -			status = "disabled";
> +			mdio: mdio-bus at 72004 {
> +				compatible = "marvell,orion-mdio";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0x72004 0x84>;
> +				interrupts = <22>;
> +				status = "disabled";
>
> -			/* add phy nodes in board file */
> -		};
> +				/* add phy nodes in board file */
> +			};
> +
> +			sata at 80000 {

ditto.

> +				compatible = "marvell,orion-sata";
> +				reg = <0x80000 0x5000>;
> +				interrupts = <29>;
> +				status = "disabled";
> +			};
>
> -		sata at 80000 {
> -			compatible = "marvell,orion-sata";
> -			reg = <0x80000 0x5000>;
> -			interrupts = <29>;
> -			status = "disabled";
> +			ehci at a0000 {
> +				compatible = "marvell,orion-ehci";
> +				reg = <0xa0000 0x1000>;
> +				interrupts = <12>;
> +				status = "disabled";
> +			};
>   		};
>
>   		crypto at 90000 {

ditto, something like "cesa: crypto at 90000 {"

Sebastian

>   			compatible = "marvell,orion-crypto";
> -			reg = <0x90000 0x10000>,
> -			      <0xf2200000 0x800>;
> +			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
> +			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;
>   			reg-names = "regs", "sram";
>   			interrupts = <28>;
>   			status = "okay";
>   		};
> -
> -		ehci at a0000 {
> -			compatible = "marvell,orion-ehci";
> -			reg = <0xa0000 0x1000>;
> -			interrupts = <12>;
> -			status = "disabled";
> -		};
>   	};
>   };
> diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
> index c134a82..f6a388a 100644
> --- a/arch/arm/mach-orion5x/board-dt.c
> +++ b/arch/arm/mach-orion5x/board-dt.c
> @@ -15,10 +15,14 @@
>   #include <linux/of.h>
>   #include <linux/of_platform.h>
>   #include <linux/cpu.h>
> +#include <linux/mbus.h>
>   #include <asm/system_misc.h>
>   #include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
>   #include <mach/orion5x.h>
> +#include <mach/bridge-regs.h>
>   #include <plat/irq.h>
> +#include <plat/time.h>
>   #include "common.h"
>
>   static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
> @@ -31,6 +35,17 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
>   	{},
>   };
>
> +static void orion5x_dt_init_early(void)
> +{
> +	orion_time_set_base(TIMER_VIRT_BASE);
> +}
> +
> +static void orion5x_dt_init_time(void)
> +{
> +	orion5x_timer_init();
> +	BUG_ON(mvebu_mbus_dt_init());
> +}
> +
>   static void __init orion5x_dt_init(void)
>   {
>   	char *dev_name;
> @@ -71,9 +86,9 @@ static const char *orion5x_dt_compat[] = {
>   DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
>   	/* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
>   	.map_io		= orion5x_map_io,
> -	.init_early	= orion5x_init_early,
> +	.init_early	= orion5x_dt_init_early,
>   	.init_irq	= orion_dt_init_irq,
> -	.init_time	= orion5x_timer_init,
> +	.init_time	= orion5x_dt_init_time,
>   	.init_machine	= orion5x_dt_init,
>   	.restart	= orion5x_restart,
>   	.dt_compat	= orion5x_dt_compat,
>

[PATCH 12/29] ARM: orion5x: add interrupt for Ethernet in Device Tree

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> For some reason, the Ethernet interrupt was missing in the Orion5x
> Device Tree definition.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x.dtsi | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index 31d46e6..ac2ec8f 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -128,6 +128,7 @@
>   				ethernet-port at 0 {
>   					compatible = "marvell,orion-eth-port";
>   					reg = <0>;
> +					interrupts = <21>;
>   					/* overwrite MAC address in bootloader */
>   					local-mac-address = [00 00 00 00 00 00];
>   					/* set phy-handle property in board file */
>

[PATCH 13/29] ARM: orion5x: switch to use the clock driver for DT platforms

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit moves the Orion5x platforms using the Device Tree to use
> the recently introduced clock driver for Orion5x. To achieve that, it:
>
>   * Adds the necessary DT description of the clock.
>
>   * Selects ORION_CLK to enable the compilation of the clock driver.
>
>   * Call of_clk_init() instead of the Orion5x-specific clock
>     initialization function.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

I guess either this or a follow-up patch should introduce the
clocks = <&reference-to-tclk> properties mentioned earlier.

Otherwise,

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 6 ++++++
>   arch/arm/mach-orion5x/Kconfig            | 1 +
>   arch/arm/mach-orion5x/board-dt.c         | 5 ++---
>   3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> index ddfb4d1..a56f9c8 100644
> --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> @@ -15,6 +15,12 @@
>   		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
>
>   		internal-regs {
> +			core_clk: core-clocks at 10030 {
> +				compatible = "marvell,mv88f5182-core-clock";
> +				reg = <0x10010 0x4>;
> +				#clock-cells = <1>;
> +			};
> +
>   			mbusc: mbus-controller at 20000 {
>   				compatible = "marvell,mbus-controller";
>   				reg = <0x20000 0x100>, <0x1500 0x20>;
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 14f2cae..4f51132 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -5,6 +5,7 @@ menu "Orion Implementations"
>   config ARCH_ORION5X_DT
>   	bool "Marvell Orion5x Flattened Device Tree"
>   	select USE_OF
> +	select ORION_CLK
>   	help
>   	  Say 'Y' here if you want your kernel to support the
>   	  Marvell Orion5x using flattened device tree.
> diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
> index f6a388a..c489661 100644
> --- a/arch/arm/mach-orion5x/board-dt.c
> +++ b/arch/arm/mach-orion5x/board-dt.c
> @@ -16,6 +16,7 @@
>   #include <linux/of_platform.h>
>   #include <linux/cpu.h>
>   #include <linux/mbus.h>
> +#include <linux/clk-provider.h>
>   #include <asm/system_misc.h>
>   #include <asm/mach/arch.h>
>   #include <asm/mach/map.h>
> @@ -43,6 +44,7 @@ static void orion5x_dt_init_early(void)
>   static void orion5x_dt_init_time(void)
>   {
>   	orion5x_timer_init();
> +	of_clk_init(NULL);
>   	BUG_ON(mvebu_mbus_dt_init());
>   }
>
> @@ -59,9 +61,6 @@ static void __init orion5x_dt_init(void)
>   	 */
>   	orion5x_setup_wins();
>
> -	/* Setup root of clk tree */
> -	clk_init();
> -
>   	/*
>   	 * Don't issue "Wait for Interrupt" instruction if we are
>   	 * running on D0 5281 silicon.
>

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER
> enabled, even for non-DT platforms (if we want both DT and non-DT
> platforms to be supported in a single kernel).
>
> However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT
> platforms in plat-orion/irq.c doesn't match the needs of
> Orion5x. Also, it doesn't make much sense for orion_irq_init() to
> register the multi-IRQ handler: orion_irq_init() is called once for
> each IRQ cause/mask tuple, while the multi-IRQ handler only needs to
> be registered once.
>
> To solve this problem, we move the multi-IRQ handle in per-platform
> code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant
> will be introduced in a followup commit. Of course, this code will
> ultimately be completely removed once all boards are converted to the
> Device Tree.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/mach-dove/irq.c     | 36 +++++++++++++++++++++++++++++++++++
>   arch/arm/mach-kirkwood/irq.c | 36 +++++++++++++++++++++++++++++++++++
>   arch/arm/plat-orion/irq.c    | 45 --------------------------------------------
>   3 files changed, 72 insertions(+), 45 deletions(-)
>
> diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
> index bc4344a..4a5a7ae 100644
> --- a/arch/arm/mach-dove/irq.c
> +++ b/arch/arm/mach-dove/irq.c
> @@ -108,6 +108,38 @@ static int __initdata gpio2_irqs[4] = {
>   	0,
>   };
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +/*
> + * Compiling with both non-DT and DT support enabled, will
> + * break asm irq handler used by non-DT boards. Therefore,
> + * we provide a C-style irq handler even for non-DT boards,
> + * if MULTI_IRQ_HANDLER is set.
> + */
> +
> +static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
> +
> +static asmlinkage void
> +__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
> +{
> +	u32 stat;
> +
> +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
> +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
> +	if (stat) {
> +		unsigned int hwirq = __fls(stat);
> +		handle_IRQ(hwirq, regs);
> +		return;
> +	}

I remember we talked about it already, but IMHO copying the multi-irq
handler to mach-{kirkwood,dove} isn't necessary. The only situation we
need this is when you compile _one_ mach-{kirkwood,dove,orion5x} with
both DT and non-DT.

So, I think it is fine to just add

#if !defined(CONFIG_MACH_ORION5X)
> +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
> +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
> +	if (stat) {
> +		unsigned int hwirq = 32 + __fls(stat);
> +		handle_IRQ(hwirq, regs);
> +		return;
> +	}
#endif

in the original handler?

Sebastian

> +}
> +#endif
> +
>   void __init dove_init_irq(void)
>   {
>   	int i;
> @@ -115,6 +147,10 @@ void __init dove_init_irq(void)
>   	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
>   	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +	set_handle_irq(dove_legacy_handle_irq);
> +#endif
> +
>   	/*
>   	 * Initialize gpiolib for GPIOs 0-71.
>   	 */
> diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
> index 2a97a2e..c9dd860 100644
> --- a/arch/arm/mach-kirkwood/irq.c
> +++ b/arch/arm/mach-kirkwood/irq.c
> @@ -30,11 +30,47 @@ static int __initdata gpio1_irqs[4] = {
>   	0,
>   };
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +/*
> + * Compiling with both non-DT and DT support enabled, will
> + * break asm irq handler used by non-DT boards. Therefore,
> + * we provide a C-style irq handler even for non-DT boards,
> + * if MULTI_IRQ_HANDLER is set.
> + */
> +
> +static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE;
> +
> +asmlinkage void
> +__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs)
> +{
> +	u32 stat;
> +
> +	stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF);
> +	stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF);
> +	if (stat) {
> +		unsigned int hwirq = __fls(stat);
> +		handle_IRQ(hwirq, regs);
> +		return;
> +	}
> +	stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF);
> +	stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF);
> +	if (stat) {
> +		unsigned int hwirq = 32 + __fls(stat);
> +		handle_IRQ(hwirq, regs);
> +		return;
> +	}
> +}
> +#endif
> +
>   void __init kirkwood_init_irq(void)
>   {
>   	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
>   	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +	set_handle_irq(kirkwood_legacy_handle_irq);
> +#endif
> +
>   	/*
>   	 * Initialize gpiolib for GPIOs 0-49.
>   	 */
> diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
> index 807df14..27ec18b 100644
> --- a/arch/arm/plat-orion/irq.c
> +++ b/arch/arm/plat-orion/irq.c
> @@ -20,47 +20,6 @@
>   #include <plat/orion-gpio.h>
>   #include <mach/bridge-regs.h>
>
> -#ifdef CONFIG_MULTI_IRQ_HANDLER
> -/*
> - * Compiling with both non-DT and DT support enabled, will
> - * break asm irq handler used by non-DT boards. Therefore,
> - * we provide a C-style irq handler even for non-DT boards,
> - * if MULTI_IRQ_HANDLER is set.
> - *
> - * Notes:
> - * - this is prepared for Kirkwood and Dove only, update
> - *   accordingly if you add Orion5x or MV78x00.
> - * - Orion5x uses different macro names and has only one
> - *   set of CAUSE/MASK registers.
> - * - MV78x00 uses the same macro names but has a third
> - *   set of CAUSE/MASK registers.
> - *
> - */
> -
> -static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
> -
> -asmlinkage void
> -__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
> -{
> -	u32 stat;
> -
> -	stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
> -	stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
> -	if (stat) {
> -		unsigned int hwirq = __fls(stat);
> -		handle_IRQ(hwirq, regs);
> -		return;
> -	}
> -	stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
> -	stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
> -	if (stat) {
> -		unsigned int hwirq = 32 + __fls(stat);
> -		handle_IRQ(hwirq, regs);
> -		return;
> -	}
> -}
> -#endif
> -
>   void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
>   {
>   	struct irq_chip_generic *gc;
> @@ -78,10 +37,6 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
>   	ct->chip.irq_unmask = irq_gc_mask_set_bit;
>   	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
>   			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
> -
> -#ifdef CONFIG_MULTI_IRQ_HANDLER
> -	set_handle_irq(orion_legacy_handle_irq);
> -#endif
>   }
>
>   #ifdef CONFIG_OF
>

[PATCH 15/29] ARM: orion5x: switch to DT interrupts and timer

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit switches the Orion5x platforms described through DT to use
> a DT-defined interrupt controller and timer.
>
> This involves:
>
>   * Describing in the DT the bridge interrupt controller, which is a
>     child interrupt controller to the main one, which is used for timer
>     and watchdog interrupts.
>
>   * Describing in the DT the timer.
>
>   * Adding in the DT the interrupt specifications for the watchdog.
>
>   * Selecting the ORION_IRQCHIP and ORION_TIMER drivers to be compiled.
>
>   * Change the timer initialization in board-dt.c to use
>     clocksource_of_init().
>
>   * Implement a multi-IRQ handler for non-DT platforms in
>     mach-orion5x/irq.c.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x.dtsi   | 19 +++++++++++++++++++
>   arch/arm/mach-orion5x/Kconfig    |  2 ++
>   arch/arm/mach-orion5x/board-dt.c | 10 ++--------
>   arch/arm/mach-orion5x/irq.c      | 28 ++++++++++++++++++++++++++++
>   4 files changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index ac2ec8f..f25ed91 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -78,6 +78,15 @@
>   				status = "disabled";
>   			};
>
> +			bridge_intc: bridge-interrupt-ctrl at 20110 {
> +				compatible = "marvell,orion-bridge-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x20110 0x8>;
> +				interrupts = <0>;
> +				marvell,#interrupts = <4>;
> +			};
> +
>   			intc: interrupt-controller at 20200 {
>   				compatible = "marvell,orion-intc";
>   				interrupt-controller;
> @@ -85,9 +94,19 @@
>   				reg = <0x20200 0x08>;
>   			};
>
> +			timer at 20300 {
> +				compatible = "marvell,orion-timer";
> +				reg = <0x20300 0x20>;
> +				interrupt-parent = <&bridge_intc>;
> +				interrupts = <1>, <2>;
> +				clocks = <&core_clk 0>;
> +			};
> +
>   			wdt at 20300 {
>   				compatible = "marvell,orion-wdt";
>   				reg = <0x20300 0x28>;
> +				interrupt-parent = <&bridge_intc>;
> +				interrupts = <3>;
>   				status = "okay";
>   			};
>
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 4f51132..bd65872 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -6,6 +6,8 @@ config ARCH_ORION5X_DT
>   	bool "Marvell Orion5x Flattened Device Tree"
>   	select USE_OF
>   	select ORION_CLK
> +	select ORION_IRQCHIP
> +	select ORION_TIMER
>   	help
>   	  Say 'Y' here if you want your kernel to support the
>   	  Marvell Orion5x using flattened device tree.
> diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
> index c489661..38b54f1 100644
> --- a/arch/arm/mach-orion5x/board-dt.c
> +++ b/arch/arm/mach-orion5x/board-dt.c
> @@ -17,6 +17,7 @@
>   #include <linux/cpu.h>
>   #include <linux/mbus.h>
>   #include <linux/clk-provider.h>
> +#include <linux/clocksource.h>
>   #include <asm/system_misc.h>
>   #include <asm/mach/arch.h>
>   #include <asm/mach/map.h>
> @@ -36,15 +37,10 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
>   	{},
>   };
>
> -static void orion5x_dt_init_early(void)
> -{
> -	orion_time_set_base(TIMER_VIRT_BASE);
> -}
> -
>   static void orion5x_dt_init_time(void)
>   {
> -	orion5x_timer_init();
>   	of_clk_init(NULL);
> +	clocksource_of_init();
>   	BUG_ON(mvebu_mbus_dt_init());

If you move the mvebu_mbus_dt_init() to .init_machine callback, you
can also drop .init_time callback.

Sebastian

>   }
>
> @@ -85,8 +81,6 @@ static const char *orion5x_dt_compat[] = {
>   DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
>   	/* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
>   	.map_io		= orion5x_map_io,
> -	.init_early	= orion5x_dt_init_early,
> -	.init_irq	= orion_dt_init_irq,
>   	.init_time	= orion5x_dt_init_time,
>   	.init_machine	= orion5x_dt_init,
>   	.restart	= orion5x_restart,
> diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
> index 9654b0c..cd4bac4 100644
> --- a/arch/arm/mach-orion5x/irq.c
> +++ b/arch/arm/mach-orion5x/irq.c
> @@ -16,6 +16,7 @@
>   #include <mach/bridge-regs.h>
>   #include <plat/orion-gpio.h>
>   #include <plat/irq.h>
> +#include <asm/exception.h>
>   #include "common.h"
>
>   static int __initdata gpio0_irqs[4] = {
> @@ -25,10 +26,37 @@ static int __initdata gpio0_irqs[4] = {
>   	IRQ_ORION5X_GPIO_24_31,
>   };
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +/*
> + * Compiling with both non-DT and DT support enabled, will
> + * break asm irq handler used by non-DT boards. Therefore,
> + * we provide a C-style irq handler even for non-DT boards,
> + * if MULTI_IRQ_HANDLER is set.
> + */
> +
> +asmlinkage void
> +__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
> +{
> +	u32 stat;
> +
> +	stat = readl_relaxed(MAIN_IRQ_CAUSE);
> +	stat &= readl_relaxed(MAIN_IRQ_MASK);
> +	if (stat) {
> +		unsigned int hwirq = __fls(stat);
> +		handle_IRQ(hwirq, regs);
> +		return;
> +	}
> +}
> +#endif
> +
>   void __init orion5x_init_irq(void)
>   {
>   	orion_irq_init(0, MAIN_IRQ_MASK);
>
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +	set_handle_irq(orion5x_legacy_handle_irq);
> +#endif
> +
>   	/*
>   	 * Initialize gpiolib for GPIOs 0-31.
>   	 */
>

[PATCH 16/29] ARM: orion5x: enable pinctrl driver at SoC level

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit declares the pinctrl device in the Orion5x 5182 Device
> Tree files, and ensures that the Orion pinctrl driver is compiled.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 5 +++++
>   arch/arm/mach-orion5x/Kconfig            | 2 ++
>   2 files changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> index a56f9c8..11b487c 100644
> --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> @@ -15,6 +15,11 @@
>   		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
>
>   		internal-regs {
> +			pinctrl at 10000 {

Please add a node label.

Otherwise,

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> +				compatible = "marvell,88f5182-pinctrl";
> +				reg = <0x10000 0x8>, <0x10050 0x4>;
> +			};
> +
>   			core_clk: core-clocks at 10030 {
>   				compatible = "marvell,mv88f5182-core-clock";
>   				reg = <0x10010 0x4>;
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index bd65872..3c69a3c 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -8,6 +8,8 @@ config ARCH_ORION5X_DT
>   	select ORION_CLK
>   	select ORION_IRQCHIP
>   	select ORION_TIMER
> +	select PINCTRL
> +	select PINCTRL_ORION
>   	help
>   	  Say 'Y' here if you want your kernel to support the
>   	  Marvell Orion5x using flattened device tree.
>

[PATCH 17/29] ARM: orion5x: update I2C description at SoC level

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit fixes the Orion5x SoC definition to:
>
>   * Not define a clock-frequency, as it should be described on a
>     per-board basis.
>
>   * Declare the appropriate clock reference, so that the driver can do
>     correct divisors calculations for the I2C bus.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index f25ed91..ea6ec83 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -56,7 +56,7 @@
>   				#address-cells = <1>;
>   				#size-cells = <0>;
>   				interrupts = <5>;
> -				clock-frequency = <100000>;
> +				clocks = <&core_clk 0>;

I guess the 100kHz (<100000>) has been a bug? Please mention that in
the commit log, too.

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

>   				status = "disabled";
>   			};
>
>

[PATCH 18/29] ARM: orion5x: add Device Bus description at SoC level

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit adds the necessary SoC-level Device Tree definitions to
> describe the Device Bus of Orion5x SOCs. The Device Bus is mainly used
> to connect NOR flashes to the system.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index ea6ec83..182682b 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -24,6 +24,46 @@
>   		#size-cells = <1>;
>   		controller = <&mbusc>;
>
> +		devbus-bootcs {

To be consitent, please add node labels for this and below nodes.

Otherwise,

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> +			compatible = "marvell,orion-devbus";
> +			reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
> +			ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&core_clk 0>;
> +			status = "disabled";
> +		};
> +
> +		devbus-cs0 {
> +			compatible = "marvell,orion-devbus";
> +			reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
> +			ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&core_clk 0>;
> +			status = "disabled";
> +		};
> +
> +		devbus-cs1 {
> +			compatible = "marvell,orion-devbus";
> +			reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
> +			ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&core_clk 0>;
> +			status = "disabled";
> +		};
> +
> +		devbus-cs2 {
> +			compatible = "marvell,orion-devbus";
> +			reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
> +			ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&core_clk 0>;
> +			status = "disabled";
> +		};
> +
>   		internal-regs {
>   			compatible = "simple-bus";
>   			#address-cells = <1>;
>

[PATCH 19/29] ARM: orion5x: add standard pinctrl configs for sata0 and sata1

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> Several platforms will most likely use similar pinctrl configurations
> for SATA0 and SATA1, so we declare those common configurations in the
> Orion5x DT file.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Besides that orion5x-mv885182.dtsi should already use the pinctrl node
label reference,

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> index 11b487c..096ab02 100644
> --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
> @@ -18,6 +18,16 @@
>   			pinctrl at 10000 {
>   				compatible = "marvell,88f5182-pinctrl";
>   				reg = <0x10000 0x8>, <0x10050 0x4>;
> +
> +				pmx_sata0: pmx-sata0 {
> +					marvell,pins = "mpp12", "mpp14";
> +					marvell,function = "sata0";
> +				};
> +
> +				pmx_sata1: pmx-sata1 {
> +					marvell,pins = "mpp13", "mpp15";
> +					marvell,function = "sata1";
> +				};
>   			};
>
>   			core_clk: core-clocks at 10030 {
>

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for pinctrl.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 31 ++++++++++++++++++++++
>   arch/arm/mach-orion5x/edmini_v2-setup.c            | 28 -------------------
>   2 files changed, 31 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index d66d2fa..eee42f7 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -29,12 +29,39 @@
>   			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
>
>   		internal-regs {
> +			pinctrl at 10000 {

Use node label reference:

&pinctrl {
	...
};

> +				pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
> +				pinctrl-names = "default";
> +
> +				pmx_rtc: pmx-rtc {

Andrew already mentioned, please sort by node labels.

> +					marvell,pins = "mpp3";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_led: pmx-power-led {
> +					marvell,pins = "mpp16";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_led_ctrl: pmx-power-led-ctrl {
> +					marvell,pins = "mpp17";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_power_button: pmx-power-button {
> +					marvell,pins = "mpp18";
> +					marvell,function = "gpio";
> +				};
> +			};
> +
>   			serial at 12000 {
>   				clock-frequency = <166666667>;
>   				status = "okay";
>   			};
>
>   			sata at 80000 {
> +				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
> +				pinctrl-names = "default";
>   				status = "okay";
>   				nr-ports = <2>;
>   			};
> @@ -43,6 +70,8 @@
>
>   	gpio_keys {

ePAPR does allow _ in node names, but it seems to be more common
(or at least we should pick one) to use gpio-keys instead.

>   		compatible = "gpio-keys";
> +		pinctrl-0 = <&pmx_power_button>;
> +		pinctrl-names = "default";
>   		#address-cells = <1>;
>   		#size-cells = <0>;
>   		button at 1 {
> @@ -54,6 +83,8 @@
>
>   	gpio_leds {

ditto.

Sebastian

>   		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led>;
> +		pinctrl-names = "default";
>
>   		led at 1 {
>   			label = "power:blue";
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> index f66c1b2..c50469e 100644
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
> @@ -109,37 +109,9 @@ static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
>   /*****************************************************************************
>    * General Setup
>    ****************************************************************************/
> -static unsigned int edminiv2_mpp_modes[] __initdata = {
> -	MPP0_UNUSED,
> -	MPP1_UNUSED,
> -	MPP2_UNUSED,
> -	MPP3_GPIO,	/* RTC interrupt */
> -	MPP4_UNUSED,
> -	MPP5_UNUSED,
> -	MPP6_UNUSED,
> -	MPP7_UNUSED,
> -	MPP8_UNUSED,
> -	MPP9_UNUSED,
> -	MPP10_UNUSED,
> -	MPP11_UNUSED,
> -	MPP12_SATA_LED,	/* SATA 0 presence */
> -	MPP13_SATA_LED,	/* SATA 1 presence */
> -	MPP14_SATA_LED,	/* SATA 0 active */
> -	MPP15_SATA_LED,	/* SATA 1 active */
> -	/* 16: Power LED control (0 = On, 1 = Off) */
> -	MPP16_GPIO,
> -	/* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
> -	MPP17_GPIO,
> -	/* 18: Power button status (0 = Released, 1 = Pressed) */
> -	MPP18_GPIO,
> -	MPP19_UNUSED,
> -	0,
> -};
>
>   void __init edmini_v2_init(void)
>   {
> -	orion5x_mpp_conf(edminiv2_mpp_modes);
> -
>   	/*
>   	 * Configure peripherals.
>   	 */
>

[PATCH 21/29] ARM: orion5x: use DT to describe I2C devices on edmini_v2

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for I2C bus and devices.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 14 +++++++++++++
>   arch/arm/mach-orion5x/edmini_v2-setup.c            | 24 ----------------------
>   2 files changed, 14 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index eee42f7..f077b7b 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -10,6 +10,7 @@
>
>   #include <dt-bindings/gpio/gpio.h>
>   #include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>   #include "orion5x-mv88f5182.dtsi"
>
>   / {
> @@ -54,6 +55,19 @@
>   				};
>   			};
>
> +			i2c at 11000 {

Please use the to-be-introduced node label references.

Sebastian

> +				status = "okay";
> +				clock-frequency = <100000>;
> +				#address-cells = <1>;
> +
> +				rtc at 32 {
> +					compatible = "rs5c372a";
> +					reg = <0x32>;
> +					interrupt-parent = <&gpio0>;
> +					interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> +				};
> +			};
> +
>   			serial at 12000 {
>   				clock-frequency = <166666667>;
>   				status = "okay";
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> index c50469e..75648ab 100644
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
> @@ -96,17 +96,6 @@ static struct platform_device edmini_v2_nor_flash = {
>   };
>
>   /*****************************************************************************
> - * RTC 5C372a on I2C bus
> - ****************************************************************************/
> -
> -#define EDMINIV2_RTC_GPIO	3
> -
> -static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
> -	I2C_BOARD_INFO("rs5c372a", 0x32),
> -	.irq = 0,
> -};
> -
> -/*****************************************************************************
>    * General Setup
>    ****************************************************************************/
>
> @@ -125,17 +114,4 @@ void __init edmini_v2_init(void)
>
>   	pr_notice("edmini_v2: USB device port, flash write and power-off "
>   		  "are not yet supported.\n");
> -
> -	/* Get RTC IRQ and register the chip */
> -	if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) {
> -		if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0)
> -			edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO);
> -		else
> -			gpio_free(EDMINIV2_RTC_GPIO);
> -	}
> -
> -	if (edmini_v2_i2c_rtc.irq == 0)
> -		pr_warning("edmini_v2: failed to get RTC IRQ\n");
> -
> -	i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1);
>   }
>

[PATCH 22/29] ARM: orion5x: use DT to describe EHCI on edmini_v2

[Sebastian Hesselbarth]

On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for USB.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 4 ++++
>   arch/arm/mach-orion5x/edmini_v2-setup.c                   | 2 --
>   2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index f077b7b..ff90b01 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -73,6 +73,10 @@
>   				status = "okay";
>   			};
>
> +			ehci at 50000 {

Node label reference again.

If you wonder why I insist on it, if you ever realize there is
something wrong with the original bus node structure in orion5x.dtsi,
you don't have to change 40+ board files, too. This is what makes
cleaning up kirkwood.dtsi so tricky ;)

Sebastian

> +				status = "okay";
> +			};
> +
>   			sata at 80000 {
>   				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
>   				pinctrl-names = "default";
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> index 75648ab..2eebc0c 100644
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
> @@ -104,8 +104,6 @@ void __init edmini_v2_init(void)
>   	/*
>   	 * Configure peripherals.
>   	 */
> -	orion5x_ehci0_init();
> -
>   	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
>   				    ORION_MBUS_DEVBUS_BOOT_ATTR,
>   				    EDMINI_V2_NOR_BOOT_BASE,
>

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Sebastian Hesselbarth]

On 04/13/2014 04:40 PM, Thomas Petazzoni wrote:
> This commit converts the already partially DT-converted edmini_v2
> platform to use the Device Tree for NOR flash, using the Device Bus.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 46 +++++++++++++++-
>   arch/arm/mach-orion5x/edmini_v2-setup.c            | 62 ----------------------
>   2 files changed, 45 insertions(+), 63 deletions(-)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index ff90b01..44cc36a 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -27,7 +27,51 @@
>
>   	soc {
>   		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> -			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
> +
> +		devbus-bootcs {

Node label reference?

> +			status = "okay";
> +
> +			/* Read parameters */
> +			devbus,bus-width    = <8>;
> +			devbus,turn-off-ps  = <90000>;
> +			devbus,badr-skew-ps = <0>;
> +			devbus,acc-first-ps = <186000>;
> +			devbus,acc-next-ps  = <186000>;
> +
> +			/* Write parameters */
> +			devbus,wr-high-ps  = <90000>;
> +			devbus,wr-low-ps   = <90000>;
> +			devbus,ale-wr-ps   = <90000>;
> +
> +			/*
> +			 * Currently the MTD code does not recognize
> +			 * the MX29LV400CBCT as a bottom-type
> +			 * device. This could cause risks of
> +			 * accidentally erasing critical flash
> +			 * sectors. We thus define a single,
> +			 * write-protected partition covering the
> +			 * whole flash.  TODO: once the flash part
> +			 * TOP/BOTTOM detection issue is sorted out in
> +			 * the MTD code, break this into at least
> +			 * three partitions: 'u-boot code', 'u-boot
> +			 * environment' and 'whatever is left'.
> +			 */
> +			nor at 0 {

ePAPR suggests a generic node name. I talked to Olof on IRC, he prefers
generic names all over. I confirmed that this means "flash" node name
for both the controller _and_ the device.

We have never been very strict about the node names, but if we add one,
we should follow the suggestions.

Sebastian

> +				compatible = "cfi-flash";
> +				reg = <0 0x80000>;
> +				bank-width = <1>;
> +		                #address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				partition at 0 {
> +					label = "Full512Kb";
> +					reg = <0 0x80000>;
> +					read-only;
> +				};
> +			};
> +		};
>
>   		internal-regs {
>   			pinctrl at 10000 {
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> index 2eebc0c..6bef2d5 100644
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
> @@ -42,74 +42,12 @@
>    * EDMINI_V2 Info
>    ****************************************************************************/
>
> -/*
> - * 512KB NOR flash Device bus boot chip select
> - */
> -
> -#define EDMINI_V2_NOR_BOOT_BASE		0xfff80000
> -#define EDMINI_V2_NOR_BOOT_SIZE		SZ_512K
> -
> -/*****************************************************************************
> - * 512KB NOR Flash on BOOT Device
> - ****************************************************************************/
> -
> -/*
> - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
> - * -type device. This could cause risks of accidentally erasing critical
> - * flash sectors. We thus define a single, write-protected partition covering
> - * the whole flash.
> - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
> - * code, break this into at least three partitions: 'u-boot code', 'u-boot
> - * environment' and 'whatever is left'.
> - */
> -
> -static struct mtd_partition edmini_v2_partitions[] = {
> -	{
> -		.name		= "Full512kb",
> -		.size		= 0x00080000,
> -		.offset		= 0x00000000,
> -		.mask_flags	= MTD_WRITEABLE,
> -	},
> -};
> -
> -static struct physmap_flash_data edmini_v2_nor_flash_data = {
> -	.width		= 1,
> -	.parts		= edmini_v2_partitions,
> -	.nr_parts	= ARRAY_SIZE(edmini_v2_partitions),
> -};
> -
> -static struct resource edmini_v2_nor_flash_resource = {
> -	.flags			= IORESOURCE_MEM,
> -	.start			= EDMINI_V2_NOR_BOOT_BASE,
> -	.end			= EDMINI_V2_NOR_BOOT_BASE
> -		+ EDMINI_V2_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device edmini_v2_nor_flash = {
> -	.name			= "physmap-flash",
> -	.id			= 0,
> -	.dev		= {
> -		.platform_data	= &edmini_v2_nor_flash_data,
> -	},
> -	.num_resources		= 1,
> -	.resource		= &edmini_v2_nor_flash_resource,
> -};
> -
>   /*****************************************************************************
>    * General Setup
>    ****************************************************************************/
>
>   void __init edmini_v2_init(void)
>   {
> -	/*
> -	 * Configure peripherals.
> -	 */
> -	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> -				    ORION_MBUS_DEVBUS_BOOT_ATTR,
> -				    EDMINI_V2_NOR_BOOT_BASE,
> -				    EDMINI_V2_NOR_BOOT_SIZE);
> -	platform_device_register(&edmini_v2_nor_flash);
> -
>   	pr_notice("edmini_v2: USB device port, flash write and power-off "
>   		  "are not yet supported.\n");
>   }
>

[PATCH 24/29] ARM: orion5x: keep TODO list in edmini_v2 DT

[Sebastian Hesselbarth]

On 04/13/2014 04:40 PM, Thomas Petazzoni wrote:
> In preparation to the complete removal of non-DT support for
> edmini_v2, this commit copies the TODO list of things to support from
> the old-style board file into the Device Tree of edmini_v2.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> index 44cc36a..ffa0fc5 100644
> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
> @@ -6,6 +6,13 @@
>    * warranty of any kind, whether express or implied.
>    */
>
> +/*
> + * TODO: add Orion USB device port init when kernel.org support is added.

I had a great time lately to look up usb phy init for all MVEBU SoCs.
Expect barebox usb-phy code first, then later proper init for Linux,
too.

> + * TODO: add flash write support: see below.
> + * TODO: add power-off support.
> + * TODO: add I2C EEPROM support.

Have you evaluated, what is blocking i2c eeprom?

Sebastian

> + */
> +
>   /dts-v1/;
>
>   #include <dt-bindings/gpio/gpio.h>
>

[PATCH 25/29] ARM: orion5x: remove unneeded code for edmini_v2

[Sebastian Hesselbarth]

On 04/13/2014 04:40 PM, Thomas Petazzoni wrote:
> The edmini_v2 platform is now fully converted to the Device Tree, so
> we can get rid of the old style board-file and the related Kconfig
> option.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

I love code removal ;)

Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

> ---
>   arch/arm/mach-orion5x/Kconfig           |  8 -----
>   arch/arm/mach-orion5x/Makefile          |  1 -
>   arch/arm/mach-orion5x/board-dt.c        |  3 --
>   arch/arm/mach-orion5x/common.h          |  7 -----
>   arch/arm/mach-orion5x/edmini_v2-setup.c | 53 ---------------------------------
>   5 files changed, 72 deletions(-)
>   delete mode 100644 arch/arm/mach-orion5x/edmini_v2-setup.c
>
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 3c69a3c..928f4cb 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -107,14 +107,6 @@ config MACH_MV2120
>   	  Say 'Y' here if you want your kernel to support the
>   	  HP Media Vault mv2120 or mv5100.
>
> -config MACH_EDMINI_V2_DT
> -	bool "LaCie Ethernet Disk mini V2 (Flattened Device Tree)"
> -	select I2C_BOARDINFO
> -	select ARCH_ORION5X_DT
> -	help
> -	  Say 'Y' here if you want your kernel to support the
> -	  LaCie Ethernet Disk mini V2 (Flattened Device Tree).
> -
>   config MACH_D2NET
>   	bool "LaCie d2 Network"
>   	select I2C_BOARDINFO
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index 45da805..e8fdbdd 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -23,4 +23,3 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
>   obj-$(CONFIG_MACH_LINKSTATION_LSCHL)	+= ls-chl-setup.o
>
>   obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
> -obj-$(CONFIG_MACH_EDMINI_V2_DT)	+= edmini_v2-setup.o
> diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
> index 38b54f1..c621f37 100644
> --- a/arch/arm/mach-orion5x/board-dt.c
> +++ b/arch/arm/mach-orion5x/board-dt.c
> @@ -66,9 +66,6 @@ static void __init orion5x_dt_init(void)
>   		cpu_idle_poll_ctrl(true);
>   	}
>
> -	if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2"))
> -		edmini_v2_init();
> -
>   	of_platform_populate(NULL, of_default_bus_match_table,
>   			     orion5x_auxdata_lookup, NULL);
>   }
> diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
> index 7548db2..4470e31 100644
> --- a/arch/arm/mach-orion5x/common.h
> +++ b/arch/arm/mach-orion5x/common.h
> @@ -64,13 +64,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
>   struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
>   int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
>
> -/* board init functions for boards not fully converted to fdt */
> -#ifdef CONFIG_MACH_EDMINI_V2_DT
> -void edmini_v2_init(void);
> -#else
> -static inline void edmini_v2_init(void) {};
> -#endif
> -
>   struct meminfo;
>   struct tag;
>   extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
> diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
> deleted file mode 100644
> index 6bef2d5..0000000
> --- a/arch/arm/mach-orion5x/edmini_v2-setup.c
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -/*
> - * arch/arm/mach-orion5x/edmini_v2-setup.c
> - *
> - * LaCie Ethernet Disk mini V2 Setup
> - *
> - * Copyright (C) 2008 Christopher Moore <moore@free.fr>
> - * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -/*
> - * TODO: add Orion USB device port init when kernel.org support is added.
> - * TODO: add flash write support: see below.
> - * TODO: add power-off support.
> - * TODO: add I2C EEPROM support.
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/pci.h>
> -#include <linux/irq.h>
> -#include <linux/mbus.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/ata_platform.h>
> -#include <linux/gpio.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/pci.h>
> -#include <mach/orion5x.h>
> -#include "common.h"
> -#include "mpp.h"
> -
> -/*****************************************************************************
> - * EDMINI_V2 Info
> - ****************************************************************************/
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -
> -void __init edmini_v2_init(void)
> -{
> -	pr_notice("edmini_v2: USB device port, flash write and power-off "
> -		  "are not yet supported.\n");
> -}
>

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Mon, 14 Apr 2014 12:51:24 +0200, Sebastian Hesselbarth wrote:

> >   		internal-regs {
> > +			pinctrl at 10000 {
> 
> Use node label reference:
> 
> &pinctrl {
> 	...
> };

I personally dislike using node label references. I know they are used
for Ethernet because it has been done by someone else for Orion
platforms. But on all Armada 370/XP platforms, we don't use node label
references, and I'd prefer to do it the same way for Orion5x platforms
if possible.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Mon, 14 Apr 2014 13:14:56 +0200, Sebastian Hesselbarth wrote:

> > +		devbus-bootcs {
> 
> Node label reference?
> 
> > +			status = "okay";
> > +
> > +			/* Read parameters */
> > +			devbus,bus-width    = <8>;
> > +			devbus,turn-off-ps  = <90000>;
> > +			devbus,badr-skew-ps = <0>;
> > +			devbus,acc-first-ps = <186000>;
> > +			devbus,acc-next-ps  = <186000>;
> > +
> > +			/* Write parameters */
> > +			devbus,wr-high-ps  = <90000>;
> > +			devbus,wr-low-ps   = <90000>;
> > +			devbus,ale-wr-ps   = <90000>;
> > +
> > +			/*
> > +			 * Currently the MTD code does not recognize
> > +			 * the MX29LV400CBCT as a bottom-type
> > +			 * device. This could cause risks of
> > +			 * accidentally erasing critical flash
> > +			 * sectors. We thus define a single,
> > +			 * write-protected partition covering the
> > +			 * whole flash.  TODO: once the flash part
> > +			 * TOP/BOTTOM detection issue is sorted out in
> > +			 * the MTD code, break this into at least
> > +			 * three partitions: 'u-boot code', 'u-boot
> > +			 * environment' and 'whatever is left'.
> > +			 */
> > +			nor at 0 {
> 
> ePAPR suggests a generic node name. I talked to Olof on IRC, he prefers
> generic names all over. I confirmed that this means "flash" node name
> for both the controller _and_ the device.

While I'm fine with changing the nor at 0 node name to flash at 0, I'm
clearly not ok with changing devbus-bootcs to something that refers to
a "flash", because the Device Bus controller is not only a flash
controller. It can be used for many other memory mapped devices, such
as FPGAs and so on.

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Sebastian Hesselbarth]

On 04/13/2014 04:40 PM, Thomas Petazzoni wrote:
> This commit converts the RD-88F5182 platform to the Device Tree. All
> devices except the PCI are converted to the Device Tree.
>
> It is worth noting that:
>
>   * The PCI description for the DT case is kept in board-rd88f5182.c.
>
>   * The existing non-DT support in rd88f5182-setup.c is kept as is, in
>     order to allow testing of a given platform in both DT and non-DT
>     cases. It will ultimately be removed, once we no longer care about
>     non-DT support for Orion5x.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>   arch/arm/boot/dts/Makefile                  |   3 +-
>   arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 153 ++++++++++++++++++++++++++++
>   arch/arm/mach-orion5x/Kconfig               |   8 ++
>   arch/arm/mach-orion5x/Makefile              |   1 +
>   arch/arm/mach-orion5x/board-rd88f5182.c     | 116 +++++++++++++++++++++
>   5 files changed, 280 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
>   create mode 100644 arch/arm/mach-orion5x/board-rd88f5182.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 35c146f..f7943a8 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
>   	am43x-epos-evm.dtb \
>   	am437x-gp-evm.dtb \
>   	dra7-evm.dtb
> -dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
> +dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \
> +	orion5x-rd88f5182-nas.dtb
>   dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
>   dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
>   	qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
> new file mode 100644
> index 0000000..b5fd087
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
> @@ -0,0 +1,153 @@
> +/*
> + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +#include "orion5x-mv88f5182.dtsi"
> +
> +/ {
> +	model = "Marvell Reference Design 88F5182 NAS";
> +	compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x4000000>; /* 64 MB */
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";

+ [linux,]stdout-path = &uart0;

> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +		         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
> +			 <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
> +
> +		devbus-bootcs {

Use node label references where applicable.

> +			status = "okay";
> +			/* TODO: Device Bus parameters */
> +			nor at 0 {
> +				compatible = "cfi-flash";
> +				reg = <0 0x80000>;
> +				bank-width = <1>;
> +			};
> +		};
> +
> +		devbus-cs1 {
> +			status = "okay";
> +			/* TODO: Device Bus parameters */
> +			nor at 0 {
> +				compatible = "cfi-flash";
> +				reg = <0 0x1000000>;
> +				bank-width = <1>;
> +			};
> +		};
> +
> +		internal-regs {
> +			pinctrl at 10000 {
> +				pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
> +					     &pmx_pci_gpios>;
> +				pinctrl-names = "default";
> +
> +				/*
> +				 * MPP[20] PCI Clock to MV88F5182
> +				 * MPP[21] PCI Clock to mini PCI CON11
> +				 * MPP[22] USB 0 over current indication
> +				 * MPP[23] USB 1 over current indication
> +				 * MPP[24] USB 1 over current enable
> +				 * MPP[25] USB 0 over current enable
> +				 */
> +
> +				pmx_debug_led: pmx-debug_led {
> +					marvell,pins = "mpp0";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_reset_switch: pmx-reset-switch {
> +					marvell,pins = "mpp1";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_rtc: pmx-rtc {
> +					marvell,pins = "mpp3";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_misc_gpios: pmx-misc-gpios {

Sort alphabetically by node label.

> +					marvell,pins = "mpp4", "mpp5";
> +					marvell,function = "gpio";
> +				};
> +
> +				pmx_pci_gpios: pmx-pci-gpios {
> +					marvell,pins = "mpp6", "mpp7";
> +					marvell,function = "gpio";
> +				};
> +			};
> +
> +			i2c at 11000 {
> +				status = "okay";
> +				clock-frequency = <100000>;
> +				#address-cells = <1>;
> +
> +				rtc at 68 {
> +					pinctrl-0 = <&pmx_rtc>;
> +					pinctrl-names = "default";
> +					compatible = "ds1338";
> +					reg = <0x68>;
> +				};
> +			};
> +
> +			serial at 12000 {
> +				clock-frequency = <166666667>;
> +				status = "okay";
> +			};
> +
> +			ehci at 50000 {
> +				status = "okay";
> +			};
> +
> +			sata at 80000 {
> +				pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +				nr-ports = <2>;
> +			};
> +
> +			ehci at a0000 {
> +				status = "okay";
> +			};
> +		};
> +	};
> +
> +	gpio_leds {

s/gpio_leds/gpio-leds/

> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_debug_led>;
> +		pinctrl-names = "default";
> +
> +		led at 0 {
> +			label = "rd88f5182:cpu";
> +			linux,default-trigger = "heartbeat";
> +			gpios = <&gpio0 0 0>;

Use gpio.h dt-include?

> +		};
> +	};
> +};
> +
> +&mdio {
> +	status = "okay";
> +
> +	ethphy: ethernet-phy {
> +		reg = <8>;

Can you evaluate if it is GMII or RGMII[-id] and add a
phy-connection-type property now? This is something that
bothers me already on kirkwood.

> +	};
> +};
> +
> +&eth {
> +	status = "okay";
> +
> +	ethernet-port at 0 {
> +		phy-handle = <&ethphy>;
> +	};
> +};
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 928f4cb..11b0c7e 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -28,6 +28,14 @@ config MACH_RD88F5182
>   	  Say 'Y' here if you want your kernel to support the
>   	  Marvell Orion-NAS (88F5182) RD2
>
> +config MACH_RD88F5182_DT
> +	bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)"
> +	select ARCH_ORION5X_DT
> +	select I2C_BOARDINFO
> +	help
> +	  Say 'Y' here if you want your kernel to support the Marvell
> +	  Orion-NAS (88F5182) RD2, Flattened Device Tree.
> +
>   config MACH_KUROBOX_PRO
>   	bool "KuroBox Pro"
>   	select I2C_BOARDINFO
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index e8fdbdd..f405894 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -23,3 +23,4 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
>   obj-$(CONFIG_MACH_LINKSTATION_LSCHL)	+= ls-chl-setup.o
>
>   obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
> +obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
> diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c
> new file mode 100644
> index 0000000..270824b
> --- /dev/null
> +++ b/arch/arm/mach-orion5x/board-rd88f5182.c
> @@ -0,0 +1,116 @@
> +/*
> + * arch/arm/mach-orion5x/rd88f5182-setup.c
> + *
> + * Marvell Orion-NAS Reference Design Setup
> + *
> + * Maintainer: Ronen Shitrit <rshitrit@marvell.com>

Maybe add Ronen to the Signed-off tag, too? Or at least put him
on Cc?

> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/gpio.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/pci.h>
> +#include <mach/orion5x.h>
> +#include "common.h"
> +
> +/*****************************************************************************
> + * RD-88F5182 Info
> + ****************************************************************************/
> +
> +/*
> + * PCI
> + */
> +
> +#define RD88F5182_PCI_SLOT0_OFFS	7
> +#define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
> +#define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6
> +
> +/*****************************************************************************
> + * PCI
> + ****************************************************************************/
> +
> +static void __init rd88f5182_pci_preinit(void)
> +{
> +	int pin;
> +
> +	/*
> +	 * Configure PCI GPIO IRQ pins
> +	 */
> +	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
> +	if (gpio_request(pin, "PCI IntA") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			printk(KERN_ERR "rd88f5182_pci_preinit failed to "

I am not sure, what is the correct way of using it, but maybe it is
pr_err()? I'd also be interested in the latest policy of using it.

Sebastian

> +					"set_irq_type pin %d\n", pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
> +	}
> +
> +	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
> +	if (gpio_request(pin, "PCI IntB") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
> +					"set_irq_type pin %d\n", pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
> +	}
> +}
> +
> +static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
> +	u8 pin)
> +{
> +	int irq;
> +
> +	/*
> +	 * Check for devices with hard-wired IRQs.
> +	 */
> +	irq = orion5x_pci_map_irq(dev, slot, pin);
> +	if (irq != -1)
> +		return irq;
> +
> +	/*
> +	 * PCI IRQs are connected via GPIOs
> +	 */
> +	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
> +	case 0:
> +		if (pin == 1)
> +			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
> +		else
> +			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
> +	default:
> +		return -1;
> +	}
> +}
> +
> +static struct hw_pci rd88f5182_pci __initdata = {
> +	.nr_controllers	= 2,
> +	.preinit	= rd88f5182_pci_preinit,
> +	.setup		= orion5x_pci_sys_setup,
> +	.scan		= orion5x_pci_sys_scan_bus,
> +	.map_irq	= rd88f5182_pci_map_irq,
> +};
> +
> +static int __init rd88f5182_pci_init(void)
> +{
> +	if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
> +		pci_common_init(&rd88f5182_pci);
> +
> +	return 0;
> +}
> +
> +subsys_initcall(rd88f5182_pci_init);
>

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Sebastian Hesselbarth]

On 04/14/2014 01:23 PM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
>
> On Mon, 14 Apr 2014 12:51:24 +0200, Sebastian Hesselbarth wrote:
>
>>>    		internal-regs {
>>> +			pinctrl at 10000 {
>>
>> Use node label reference:
>>
>> &pinctrl {
>> 	...
>> };
>
> I personally dislike using node label references. I know they are used
> for Ethernet because it has been done by someone else for Orion
> platforms. But on all Armada 370/XP platforms, we don't use node label
> references, and I'd prefer to do it the same way for Orion5x platforms
> if possible.

Well, I definitely disagree and would like to _enforce_ using node
label references. Anyway, if there is a strong reason for not using
them, I'd be fine too.

Sebastian

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Sebastian Hesselbarth]

On 04/14/2014 01:24 PM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
>
> On Mon, 14 Apr 2014 13:14:56 +0200, Sebastian Hesselbarth wrote:
>
>>> +		devbus-bootcs {
>>
>> Node label reference?
>>
>>> +			status = "okay";
>>> +
>>> +			/* Read parameters */
>>> +			devbus,bus-width    = <8>;
>>> +			devbus,turn-off-ps  = <90000>;
>>> +			devbus,badr-skew-ps = <0>;
>>> +			devbus,acc-first-ps = <186000>;
>>> +			devbus,acc-next-ps  = <186000>;
>>> +
>>> +			/* Write parameters */
>>> +			devbus,wr-high-ps  = <90000>;
>>> +			devbus,wr-low-ps   = <90000>;
>>> +			devbus,ale-wr-ps   = <90000>;
>>> +
>>> +			/*
>>> +			 * Currently the MTD code does not recognize
>>> +			 * the MX29LV400CBCT as a bottom-type
>>> +			 * device. This could cause risks of
>>> +			 * accidentally erasing critical flash
>>> +			 * sectors. We thus define a single,
>>> +			 * write-protected partition covering the
>>> +			 * whole flash.  TODO: once the flash part
>>> +			 * TOP/BOTTOM detection issue is sorted out in
>>> +			 * the MTD code, break this into at least
>>> +			 * three partitions: 'u-boot code', 'u-boot
>>> +			 * environment' and 'whatever is left'.
>>> +			 */
>>> +			nor at 0 {
>>
>> ePAPR suggests a generic node name. I talked to Olof on IRC, he prefers
>> generic names all over. I confirmed that this means "flash" node name
>> for both the controller _and_ the device.
>
> While I'm fine with changing the nor at 0 node name to flash at 0, I'm
> clearly not ok with changing devbus-bootcs to something that refers to
> a "flash", because the Device Bus controller is not only a flash
> controller. It can be used for many other memory mapped devices, such
> as FPGAs and so on.

No, I didn't mean to rename devbus-foo nodes, just the flash.

devbus-foo was the reason I pointed out that we have never been
very strict with node names.

Sebastian

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Andrew Lunn]

On Mon, Apr 14, 2014 at 01:27:41PM +0200, Sebastian Hesselbarth wrote:
> On 04/14/2014 01:23 PM, Thomas Petazzoni wrote:
> >Dear Sebastian Hesselbarth,
> >
> >On Mon, 14 Apr 2014 12:51:24 +0200, Sebastian Hesselbarth wrote:
> >
> >>>   		internal-regs {
> >>>+			pinctrl at 10000 {
> >>
> >>Use node label reference:
> >>
> >>&pinctrl {
> >>	...
> >>};
> >
> >I personally dislike using node label references. I know they are used
> >for Ethernet because it has been done by someone else for Orion
> >platforms. But on all Armada 370/XP platforms, we don't use node label
> >references, and I'd prefer to do it the same way for Orion5x platforms
> >if possible.
> 
> Well, I definitely disagree and would like to _enforce_ using node
> label references. Anyway, if there is a strong reason for not using
> them, I'd be fine too.
 
Hi Sebastian, Thomas

Could you both explain your like/dislike for using node labels.

Thanks
	Andrew

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Ezequiel Garcia]

On Apr 14, Andrew Lunn wrote:
> On Mon, Apr 14, 2014 at 01:27:41PM +0200, Sebastian Hesselbarth wrote:
> > On 04/14/2014 01:23 PM, Thomas Petazzoni wrote:
> > >Dear Sebastian Hesselbarth,
> > >
> > >On Mon, 14 Apr 2014 12:51:24 +0200, Sebastian Hesselbarth wrote:
> > >
> > >>>   		internal-regs {
> > >>>+			pinctrl at 10000 {
> > >>
> > >>Use node label reference:
> > >>
> > >>&pinctrl {
> > >>	...
> > >>};
> > >
> > >I personally dislike using node label references. I know they are used
> > >for Ethernet because it has been done by someone else for Orion
> > >platforms. But on all Armada 370/XP platforms, we don't use node label
> > >references, and I'd prefer to do it the same way for Orion5x platforms
> > >if possible.
> > 
> > Well, I definitely disagree and would like to _enforce_ using node
> > label references. Anyway, if there is a strong reason for not using
> > them, I'd be fine too.
>  
> Hi Sebastian, Thomas
> 
> Could you both explain your like/dislike for using node labels.
> 

Aside from aesthetical reasons, let me add a fact in favor of node labels.
When we added the MBus devicetree we had to do some intrusive and error-prone
node relocations, such as:

de1af8d486ae05922efbb69b93b902b197dfaca9

These changes would have been much simpler by using node labels, probably
one-liners.
-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com

[PATCH 20/29] ARM: orion5x: convert edmini_v2 to DT pinctrl

[Sebastian Hesselbarth]

On 04/14/2014 02:06 PM, Andrew Lunn wrote:
> On Mon, Apr 14, 2014 at 01:27:41PM +0200, Sebastian Hesselbarth wrote:
>> On 04/14/2014 01:23 PM, Thomas Petazzoni wrote:
>>> Dear Sebastian Hesselbarth,
>>>
>>> On Mon, 14 Apr 2014 12:51:24 +0200, Sebastian Hesselbarth wrote:
>>>
>>>>>    		internal-regs {
>>>>> +			pinctrl at 10000 {
>>>>
>>>> Use node label reference:
>>>>
>>>> &pinctrl {
>>>> 	...
>>>> };
>>>
>>> I personally dislike using node label references. I know they are used
>>> for Ethernet because it has been done by someone else for Orion
>>> platforms. But on all Armada 370/XP platforms, we don't use node label
>>> references, and I'd prefer to do it the same way for Orion5x platforms
>>> if possible.
>>
>> Well, I definitely disagree and would like to _enforce_ using node
>> label references. Anyway, if there is a strong reason for not using
>> them, I'd be fine too.
>
> Could you both explain your like/dislike for using node labels.

My personal preferences are

(a) you cannot add any typos in nodes already existing, e.g.
     while copying serial at 11000 you have serial at 11100, or
     clock-frequency = <100000000>; becomes
     clock-frequency = <10000000>;.

(b) any mistake in toplevel includes gets multiplied by
     board dts files using the include.

Best example is kirkwood.dtsi which grew incrementally of
course. There are some issues with it and each of it is
replicated in up to ~40 board files.

For example, moving ocp at f1000000 for kirkwood will be a
real pain in the ass. Thomas can do it for orion5x.dtsi
because there is only one board using it, dove.dtsi was
already painful with only 3 boards.. but kirkwood.. don't
even think of it ;)

Also, I found two or three board files for kirkwood that
still have their pcie nodes sitting in ocp at f100000 because
we missed them when moving the nodes. With node label
references, this wouldn't be a problem at all.

The only drawback for node label references is, they have
to be known at dtc link time. I already mentioned it in
our internal mail, but if you have

kirkwood.dtsi
   +- kirkwood-6281.dtsi adds sata, sdio, ...
   +- kirkwood-6282.dtsi adds sata, sdio, ..., i2c1

You cannot have another set of dts[i] files doing

kirkwood-db.dtsi
   +- kirkwood-db-88f6281.dts
   +- kirkwood-db-88f6282.dts

with:

kirkwood-db.dtsi:
#include <kirkwood.dtsi>

&sdio {...};

because kirkwood.dtsi does not know about &sdio.

One way of solving this would be to include e.g.
kirkwood-6281.dtsi and overwrite what was added
in the corresponding board files again.

But again, this really is my personal preference.
If there are other good reasons not to do it, I'll agree.

Sebastian

[PATCH 23/29] ARM: orion5x: use DT to describe NOR on edmini_v2

[Andrew Lunn]

> > Hi Thomas
> > 
> > Did you check if this is still true? If it is fixed, maybe now would
> > be a good time to swap to three partitions?
> 
> I don't know, and since the NOR contains the bootloader, and I'm not
> sure those Orion devices support UART booting

Hi Thomas

I had a quick look at the datasheet. I could not find any mention of
booting from Serial. So i agree, without having a tested JTAG setup,
play safe and leave the partitions alone.

	Andrew

[PATCH 24/29] ARM: orion5x: keep TODO list in edmini_v2 DT

[Chris Moore]

Hi,

Le 14/04/2014 13:17, Sebastian Hesselbarth a ?crit :
> On 04/13/2014 04:40 PM, Thomas Petazzoni wrote:
>> In preparation to the complete removal of non-DT support for
>> edmini_v2, this commit copies the TODO list of things to support from
>> the old-style board file into the Device Tree of edmini_v2.
>>
>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> ---
>>   arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git 
>> a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts 
>> b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
>> index 44cc36a..ffa0fc5 100644
>> --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
>> +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
>> @@ -6,6 +6,13 @@
>>    * warranty of any kind, whether express or implied.
>>    */
>>
>> +/*
>> + * TODO: add Orion USB device port init when kernel.org support is 
>> added.
>
> I had a great time lately to look up usb phy init for all MVEBU SoCs.
> Expect barebox usb-phy code first, then later proper init for Linux,
> too.
>
>> + * TODO: add flash write support: see below.
>> + * TODO: add power-off support.
>> + * TODO: add I2C EEPROM support.
>
> Have you evaluated, what is blocking i2c eeprom?
>

 From memory:

I2C access from user space is no problem using the generic I2C driver.
I had I2C access from kernel space working in a personal branch but 
unfortunately my way of doing this was very messy.
I therefore never dared submit my version.

I also had power-off working but, to be persistent across a power 
outage, the edmini_v2 driver needs to modify a flag in the I2C EEPROM.
In fact the LaCie EDmini V2 never really powers-off, it starts a reboot 
then loops in U-Boot.
If this flag indicates a power-off state, U-Boot waits for the power-on 
button to be pressed before booting Linux.
This was actually the main reason for needing I2C access from kernel space.

If anyone can show me how to cleanly access the generic I2C driver from 
the edmini_v2 driver, I could try again.

Cheers,
Chris

[PATCH 01/29] ARM: orion5x: fix target ID for crypto SRAM window

[Jason Cooper]

On Sun, Apr 13, 2014 at 04:39:38PM +0200, Thomas Petazzoni wrote:
> In commit 4ca2c04085a1caa903e92a5fc0da25362150aac2 ('ARM: orion5x:
> Move to ID based window creation'), the mach-orion5x code was changed
> to use the new mvebu-mbus API. However, in the process, a mistake was
> made on the crypto SRAM window target ID: it should have been 0x9
> (verified in the datasheet) and not 0x0.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: stable at vger.kernel.org
> ---
> This should be backported to stable all the way to v3.12.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/mach-orion5x/common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to mvebu/fixes with Sebastian's Ack.

thx,

Jason.

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Mon, 14 Apr 2014 12:40:48 +0200, Sebastian Hesselbarth wrote:

> > +static asmlinkage void
> > +__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
> > +{
> > +	u32 stat;
> > +
> > +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
> > +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
> > +	if (stat) {
> > +		unsigned int hwirq = __fls(stat);
> > +		handle_IRQ(hwirq, regs);
> > +		return;
> > +	}
> 
> I remember we talked about it already, but IMHO copying the multi-irq
> handler to mach-{kirkwood,dove} isn't necessary. The only situation we
> need this is when you compile _one_ mach-{kirkwood,dove,orion5x} with
> both DT and non-DT.
> 
> So, I think it is fine to just add
> 
> #if !defined(CONFIG_MACH_ORION5X)
> > +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
> > +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
> > +	if (stat) {
> > +		unsigned int hwirq = 32 + __fls(stat);
> > +		handle_IRQ(hwirq, regs);
> > +		return;
> > +	}
> #endif
> 
> in the original handler?

Nope, it doesn't work, because mach-orion5x doesn't define
IRQ_VIRT_BASE, IRQ_CAUSE_LOW_OFF and IRQ_MASK_LOW_OFF, so the common
handler does not build, even after compiling-out the part you mention
here.

Of course, Orion5x code can be changed to define those values, but I
found it was not worth the effort, and Arnd Bergmann during an IRC
discussion, also suggested to move the handle_irq() function to each
individual mach-<foo> directory. And it actually makes sense, because
it's only the same between Kirkwood and Dove: Orion5x and mv78xx0 need
different implementations.

Also, this approach goes towards the goal of reducing plat-orion/ code.
Having the code closer to each SoC is going to make it easier to
progressively get rid of it I believe.

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 17/29] ARM: orion5x: update I2C description at SoC level

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Mon, 14 Apr 2014 12:45:38 +0200, Sebastian Hesselbarth wrote:
> On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
> > This commit fixes the Orion5x SoC definition to:
> >
> >   * Not define a clock-frequency, as it should be described on a
> >     per-board basis.
> >
> >   * Declare the appropriate clock reference, so that the driver can do
> >     correct divisors calculations for the I2C bus.
> >
> > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > ---
> >   arch/arm/boot/dts/orion5x.dtsi | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> > index f25ed91..ea6ec83 100644
> > --- a/arch/arm/boot/dts/orion5x.dtsi
> > +++ b/arch/arm/boot/dts/orion5x.dtsi
> > @@ -56,7 +56,7 @@
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> >   				interrupts = <5>;
> > -				clock-frequency = <100000>;
> > +				clocks = <&core_clk 0>;
> 
> I guess the 100kHz (<100000>) has been a bug? Please mention that in
> the commit log, too.

Hum, the commit log already mentions that this property is typically
place at the board level. What other information do you think should be
present in the commit log?

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Mon, 14 Apr 2014 13:26:18 +0200, Sebastian Hesselbarth wrote:

> > +	chosen {
> > +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> 
> + [linux,]stdout-path = &uart0;

Done. Should it be linux,stdout-path, or stdout-path? As of 3.15-rc1,
it seems that only linux,stdout-path is being used.

> > +		devbus-bootcs {
> 
> Use node label references where applicable.

Ok. Which node labels do you suggest for the devbus-* nodes?

> > +				pmx_misc_gpios: pmx-misc-gpios {
> 
> Sort alphabetically by node label.

Will do, thanks.


> > +	gpio_leds {
> 
> s/gpio_leds/gpio-leds/

Will do.

> 
> > +		compatible = "gpio-leds";
> > +		pinctrl-0 = <&pmx_debug_led>;
> > +		pinctrl-names = "default";
> > +
> > +		led at 0 {
> > +			label = "rd88f5182:cpu";
> > +			linux,default-trigger = "heartbeat";
> > +			gpios = <&gpio0 0 0>;
> 
> Use gpio.h dt-include?

Sure, I missed that one.


> > +&mdio {
> > +	status = "okay";
> > +
> > +	ethphy: ethernet-phy {
> > +		reg = <8>;
> 
> Can you evaluate if it is GMII or RGMII[-id] and add a
> phy-connection-type property now? This is something that
> bothers me already on kirkwood.

I'll try to do this for this board for which I believe I have the
schematics, but for edmini_v2 or d2net, I don't have the schematics.
I'll see if I can infer the information from some U-Boot output, or by
dumping some register.


> > + * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
> 
> Maybe add Ronen to the Signed-off tag, too? Or at least put him
> on Cc?

Signed-off-by looks a bit strong, because Ronen has never seen this
patch nor been involved in writing it. I'll Cc him.


> > +	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
> > +	if (gpio_request(pin, "PCI IntA") == 0) {
> > +		if (gpio_direction_input(pin) == 0) {
> > +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> > +		} else {
> > +			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
> 
> I am not sure, what is the correct way of using it, but maybe it is
> pr_err()? I'd also be interested in the latest policy of using it.

Indeed pr_err() is the right thing to use now. However here I'm just
replicating existing code, so I'd prefer to keep it as is in this
commit, if possible. I'm anyway planning on removing this PCI platform
code soon, but this is going to be for after this series is merged.

Thanks for the review!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Sebastian Hesselbarth]

On 04/19/2014 09:27 AM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
> 
> On Mon, 14 Apr 2014 12:40:48 +0200, Sebastian Hesselbarth wrote:
> 
>>> +static asmlinkage void
>>> +__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
>>> +{
>>> +	u32 stat;
>>> +
>>> +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
>>> +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
>>> +	if (stat) {
>>> +		unsigned int hwirq = __fls(stat);
>>> +		handle_IRQ(hwirq, regs);
>>> +		return;
>>> +	}
>>
>> I remember we talked about it already, but IMHO copying the multi-irq
>> handler to mach-{kirkwood,dove} isn't necessary. The only situation we
>> need this is when you compile _one_ mach-{kirkwood,dove,orion5x} with
>> both DT and non-DT.
>>
>> So, I think it is fine to just add
>>
>> #if !defined(CONFIG_MACH_ORION5X)
>>> +	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
>>> +	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
>>> +	if (stat) {
>>> +		unsigned int hwirq = 32 + __fls(stat);
>>> +		handle_IRQ(hwirq, regs);
>>> +		return;
>>> +	}
>> #endif
>>
>> in the original handler?
> 
> Nope, it doesn't work, because mach-orion5x doesn't define
> IRQ_VIRT_BASE, IRQ_CAUSE_LOW_OFF and IRQ_MASK_LOW_OFF, so the common
> handler does not build, even after compiling-out the part you mention
> here.
> 
> Of course, Orion5x code can be changed to define those values, but I
> found it was not worth the effort, and Arnd Bergmann during an IRC
> discussion, also suggested to move the handle_irq() function to each
> individual mach-<foo> directory. And it actually makes sense, because
> it's only the same between Kirkwood and Dove: Orion5x and mv78xx0 need
> different implementations.
> 
> Also, this approach goes towards the goal of reducing plat-orion/ code.
> Having the code closer to each SoC is going to make it easier to
> progressively get rid of it I believe.

Ok, I agree. But IIRC the multi-irq handler is only needed, if you
compile both DT and non-DT in one kernel, right?

Dove DT just left mach-dove, so there is no way you can compile both.
For the sake of simplicity, I'd even agree on adding it now and
remove it later again. But at least for Dove, the move is bogus.

Sebastian

[PATCH 17/29] ARM: orion5x: update I2C description at SoC level

[Sebastian Hesselbarth]

On 04/19/2014 09:38 AM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
> 
> On Mon, 14 Apr 2014 12:45:38 +0200, Sebastian Hesselbarth wrote:
>> On 04/13/2014 04:39 PM, Thomas Petazzoni wrote:
>>> This commit fixes the Orion5x SoC definition to:
>>>
>>>   * Not define a clock-frequency, as it should be described on a
>>>     per-board basis.
>>>
>>>   * Declare the appropriate clock reference, so that the driver can do
>>>     correct divisors calculations for the I2C bus.
>>>
>>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>>> ---
>>>   arch/arm/boot/dts/orion5x.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
>>> index f25ed91..ea6ec83 100644
>>> --- a/arch/arm/boot/dts/orion5x.dtsi
>>> +++ b/arch/arm/boot/dts/orion5x.dtsi
>>> @@ -56,7 +56,7 @@
>>>   				#address-cells = <1>;
>>>   				#size-cells = <0>;
>>>   				interrupts = <5>;
>>> -				clock-frequency = <100000>;
>>> +				clocks = <&core_clk 0>;
>>
>> I guess the 100kHz (<100000>) has been a bug? Please mention that in
>> the commit log, too.
> 
> Hum, the commit log already mentions that this property is typically
> place at the board level. What other information do you think should be
> present in the commit log?

Yeah, I realized that reading through on of the later patches.
clock-frequency above does not match clocks in this case. Please ignore
my comment about it.

Sebastian

Re: [PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Sebastian Hesselbarth]

[added devtree ML and Sascha Hauer]

On 04/19/2014 09:46 AM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
> 
> On Mon, 14 Apr 2014 13:26:18 +0200, Sebastian Hesselbarth wrote:
> 
>>> +	chosen {
>>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>>
>> + [linux,]stdout-path = &uart0;
> 
> Done. Should it be linux,stdout-path, or stdout-path? As of 3.15-rc1,
> it seems that only linux,stdout-path is being used.

I remember some discussion on devtree ML that mentioned stdout-path as
possibly generic enough to loose its "linux," prefix.

Maybe Sascha can give a comment on this.

>>> +		devbus-bootcs {
>>
>> Use node label references where applicable.
> 
> Ok. Which node labels do you suggest for the devbus-* nodes?

I'd say, just pick the foo in devbus-foo, e.g. "bootcs" for the
one above. Or "devbus_bootcs" if you like.

[...]
>>> +&mdio {
>>> +	status = "okay";
>>> +
>>> +	ethphy: ethernet-phy {
>>> +		reg = <8>;
>>
>> Can you evaluate if it is GMII or RGMII[-id] and add a
>> phy-connection-type property now? This is something that
>> bothers me already on kirkwood.
> 
> I'll try to do this for this board for which I believe I have the
> schematics, but for edmini_v2 or d2net, I don't have the schematics.
> I'll see if I can infer the information from some U-Boot output, or by
> dumping some register.

If you find it out now, great. If not just leave it that way.

>>> + * Maintainer: Ronen Shitrit <rshitrit-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
>>
>> Maybe add Ronen to the Signed-off tag, too? Or at least put him
>> on Cc?
> 
> Signed-off-by looks a bit strong, because Ronen has never seen this
> patch nor been involved in writing it. I'll Cc him.

Well, you make him the number one person to ask if there is something
wrong with the DT ;) Cc is ok.

>>> +	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
>>> +	if (gpio_request(pin, "PCI IntA") == 0) {
>>> +		if (gpio_direction_input(pin) == 0) {
>>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>>> +		} else {
>>> +			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
>>
>> I am not sure, what is the correct way of using it, but maybe it is
>> pr_err()? I'd also be interested in the latest policy of using it.
> 
> Indeed pr_err() is the right thing to use now. However here I'm just
> replicating existing code, so I'd prefer to keep it as is in this
> commit, if possible. I'm anyway planning on removing this PCI platform
> code soon, but this is going to be for after this series is merged.

Ok, makes sense to me, feel free to leave it that way it is.

Sebastian

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[PATCH 26/29] ARM: orion5x: convert RD-88F5182 to Device Tree

[Sebastian Hesselbarth]

[added devtree ML and Sascha Hauer]

On 04/19/2014 09:46 AM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
> 
> On Mon, 14 Apr 2014 13:26:18 +0200, Sebastian Hesselbarth wrote:
> 
>>> +	chosen {
>>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>>
>> + [linux,]stdout-path = &uart0;
> 
> Done. Should it be linux,stdout-path, or stdout-path? As of 3.15-rc1,
> it seems that only linux,stdout-path is being used.

I remember some discussion on devtree ML that mentioned stdout-path as
possibly generic enough to loose its "linux," prefix.

Maybe Sascha can give a comment on this.

>>> +		devbus-bootcs {
>>
>> Use node label references where applicable.
> 
> Ok. Which node labels do you suggest for the devbus-* nodes?

I'd say, just pick the foo in devbus-foo, e.g. "bootcs" for the
one above. Or "devbus_bootcs" if you like.

[...]
>>> +&mdio {
>>> +	status = "okay";
>>> +
>>> +	ethphy: ethernet-phy {
>>> +		reg = <8>;
>>
>> Can you evaluate if it is GMII or RGMII[-id] and add a
>> phy-connection-type property now? This is something that
>> bothers me already on kirkwood.
> 
> I'll try to do this for this board for which I believe I have the
> schematics, but for edmini_v2 or d2net, I don't have the schematics.
> I'll see if I can infer the information from some U-Boot output, or by
> dumping some register.

If you find it out now, great. If not just leave it that way.

>>> + * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
>>
>> Maybe add Ronen to the Signed-off tag, too? Or at least put him
>> on Cc?
> 
> Signed-off-by looks a bit strong, because Ronen has never seen this
> patch nor been involved in writing it. I'll Cc him.

Well, you make him the number one person to ask if there is something
wrong with the DT ;) Cc is ok.

>>> +	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
>>> +	if (gpio_request(pin, "PCI IntA") == 0) {
>>> +		if (gpio_direction_input(pin) == 0) {
>>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>>> +		} else {
>>> +			printk(KERN_ERR "rd88f5182_pci_preinit failed to "
>>
>> I am not sure, what is the correct way of using it, but maybe it is
>> pr_err()? I'd also be interested in the latest policy of using it.
> 
> Indeed pr_err() is the right thing to use now. However here I'm just
> replicating existing code, so I'd prefer to keep it as is in this
> commit, if possible. I'm anyway planning on removing this PCI platform
> code soon, but this is going to be for after this series is merged.

Ok, makes sense to me, feel free to leave it that way it is.

Sebastian

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

On Sat, 19 Apr 2014 11:09:20 +0200, Sebastian Hesselbarth wrote:

> > Also, this approach goes towards the goal of reducing plat-orion/ code.
> > Having the code closer to each SoC is going to make it easier to
> > progressively get rid of it I believe.
> 
> Ok, I agree. But IIRC the multi-irq handler is only needed, if you
> compile both DT and non-DT in one kernel, right?

Correct.

> Dove DT just left mach-dove, so there is no way you can compile both.
> For the sake of simplicity, I'd even agree on adding it now and
> remove it later again. But at least for Dove, the move is bogus.

I think there's a lot of possible following clean up to be made. But we
have to define some limits to the current patch series, otherwise it's
going to grow to a 50+ patches monster that will be very hard to merge.
I clearly agree some of things are not in their final ideal state, but
I believe, overall, this patch series for Orion5x is pushing things in
the right direction, no?

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 14/29] ARM: orion: switch to a per-platform handle_irq() function

[Sebastian Hesselbarth]

On 04/19/2014 02:04 PM, Thomas Petazzoni wrote:
> Dear Sebastian Hesselbarth,
>>> Also, this approach goes towards the goal of reducing plat-orion/ code.
>>> Having the code closer to each SoC is going to make it easier to
>>> progressively get rid of it I believe.
>>
>> Ok, I agree. But IIRC the multi-irq handler is only needed, if you
>> compile both DT and non-DT in one kernel, right?
> 
> Correct.
> 
>> Dove DT just left mach-dove, so there is no way you can compile both.
>> For the sake of simplicity, I'd even agree on adding it now and
>> remove it later again. But at least for Dove, the move is bogus.
> 
> I think there's a lot of possible following clean up to be made. But we
> have to define some limits to the current patch series, otherwise it's
> going to grow to a 50+ patches monster that will be very hard to merge.
> I clearly agree some of things are not in their final ideal state, but
> I believe, overall, this patch series for Orion5x is pushing things in
> the right direction, no?

Agreed, the patch set is a great step for Orion5x. Let's do proper
cleanup afterwards. Thanks for working on it!

Sebastian

[PATCH 02/29] pinctrl: mvebu: new driver for Orion platforms

[Thomas Petazzoni]

Sebastian,

Thanks for your review!

On Mon, 14 Apr 2014 11:15:17 +0200, Sebastian Hesselbarth wrote:

> > +* Marvell Orion 88f5182
> > +
> > +name          pins     functions
> > +================================================================================
> > +mpp0          0        pci(rstout), pci(req2), gpio
> 
> Shouldn't the above pcie(rstout)?
> 
> The one available datasheet I have for 5182 names the function
> PEX_RST_OUTn, which is PCIexpress then.

Indeed, fixed.

> > +mpp1          1        gpio, pci(gnt2)
> > +mpp2          2        gpio, pci(req3), pci(pme)
> 
> pinctrl-mvebu isn't that good with identically named functions.
> You need to rename one of the "pci" functions to e.g. "pci-1".

Done.

> > +mpp3          3        gpio, pci(gnt3)
> > +mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
> > +mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
> > +mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
> > +mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
> > +mpp8          8        gpio, ge(col)
> > +mpp9          9        gpio, ge(rxerr)
> > +mpp10         10       gpio, ge(crs)
> > +mpp11         11       gpio, ge(txerr)
> > +mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
> > +mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
> > +mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
> > +mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)
> 
> Four "led" prefixes above should be removed.

I don't agree, because there would then be no difference between
sata0(act) and sata0(ledact), even if in the datasheet, their
description is different:

 * SATA 0 active indication (for which I've used "sata0(act)")
 * SATA 0 presence LED indication (Active Low) (for which I've used
   "sata0(ledact)")

Do you have another suggestion?


> > +static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
> > +	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
> > +};
> > +
> > +static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
> > +	MPP_GPIO_RANGE(0, 0, 0, 16),
> > +};
> > +
> > +static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
> > +	MPP_GPIO_RANGE(0, 0, 0, 19),
> > +};
> > +
> > +static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
> > +	MPP_GPIO_RANGE(0, 0, 0, 16),
> > +};
> 
> mv88f5181l_gpio_ranges == mv88f5281_gpio_ranges.
> 
> You can possibly join them to mv88f5x81_gpio ranges, but I have
> no strong opinion about it.

I prefer to have them all for each SoC, for consistency.


> > +static int orion_pinctrl_probe(struct platform_device *pdev)
> > +{
> > +	const struct of_device_id *match =
> > +		of_match_device(orion_pinctrl_of_match, &pdev->dev);
> > +	struct resource *res;
> > +
> > +	pdev->dev.platform_data = (void*) match->data;
> 
> Useless (void *) cast?

No: there is the same cast in pinctrl-dove.c and pinctrl-kirkwood.c.
The reason is a bit ugly: match->data is "const" but
pdev->dev.platform_data is not. Certainly something to fix at some
point, but probably not as part of this patch series, since Dove and
Kirkwood are already doing the bad thing :)

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 02/29] pinctrl: mvebu: new driver for Orion platforms

[Sebastian Hesselbarth]

On 04/19/2014 07:28 PM, Thomas Petazzoni wrote:
> On Mon, 14 Apr 2014 11:15:17 +0200, Sebastian Hesselbarth wrote:
>>> +mpp3          3        gpio, pci(gnt3)
>>> +mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
>>> +mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
>>> +mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
>>> +mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
>>> +mpp8          8        gpio, ge(col)
>>> +mpp9          9        gpio, ge(rxerr)
>>> +mpp10         10       gpio, ge(crs)
>>> +mpp11         11       gpio, ge(txerr)
>>> +mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
>>> +mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
>>> +mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
>>> +mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)
>>
>> Four "led" prefixes above should be removed.
> 
> I don't agree, because there would then be no difference between
> sata0(act) and sata0(ledact), even if in the datasheet, their
> description is different:
> 
>  * SATA 0 active indication (for which I've used "sata0(act)")
>  * SATA 0 presence LED indication (Active Low) (for which I've used
>    "sata0(ledact)")
> 
> Do you have another suggestion?

No, I thought that "led" prefix would be a typo in the DS already.
The other SoCs have one pin to indicate SATA activity (act) and one
to indicate SATA presence (prnst). If there is really two different
functions on Orion5x, then there should be two different names, of
course.

>>> +static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
>>> +	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
>>> +};
>>> +
>>> +static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
>>> +	MPP_GPIO_RANGE(0, 0, 0, 16),
>>> +};
>>> +
>>> +static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
>>> +	MPP_GPIO_RANGE(0, 0, 0, 19),
>>> +};
>>> +
>>> +static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
>>> +	MPP_GPIO_RANGE(0, 0, 0, 16),
>>> +};
>>
>> mv88f5181l_gpio_ranges == mv88f5281_gpio_ranges.
>>
>> You can possibly join them to mv88f5x81_gpio ranges, but I have
>> no strong opinion about it.
> 
> I prefer to have them all for each SoC, for consistency.

Ok.

>>> +static int orion_pinctrl_probe(struct platform_device *pdev)
>>> +{
>>> +	const struct of_device_id *match =
>>> +		of_match_device(orion_pinctrl_of_match, &pdev->dev);
>>> +	struct resource *res;
>>> +
>>> +	pdev->dev.platform_data = (void*) match->data;
>>
>> Useless (void *) cast?
> 
> No: there is the same cast in pinctrl-dove.c and pinctrl-kirkwood.c.
> The reason is a bit ugly: match->data is "const" but
> pdev->dev.platform_data is not. Certainly something to fix at some
> point, but probably not as part of this patch series, since Dove and
> Kirkwood are already doing the bad thing :)

Ach, dammit you are right. Thanks for reminding me about the pending
second round of mvebu/pinctrl cleanup ;)

Sebastian