[RFC 0/5] berlin: add support for clocks sharing registers

[RFC 0/5] berlin: add support for clocks sharing registers

[Alexandre Belloni]

Some clock on the berlin are sharing registers, this is an attempt at supporting
them.

I think there is a third set of regiters to enable/disable the clocks but I
don't have any information on that.

I'm also not completely sure of the DT bindings and I know that this is not the
way Sebastian was envisionning it.

Alexandre Belloni (5):
  clk: berlin: add support for clock groups
  clk: berlin: add berlin clock groups DT bindings documentation
  ARM: berlin/dt: add support for the clock group to BG2
  ARM: berlin/dt: add support for the clock group to BG2D
  ARM: berlin/dt: add support for the clock group to BG2Q

 .../devicetree/bindings/clock/berlin-clock.txt     |  29 +++
 arch/arm/boot/dts/berlin2.dtsi                     |  30 ++-
 arch/arm/boot/dts/berlin2cd.dtsi                   |  36 +++-
 arch/arm/boot/dts/berlin2q.dtsi                    |  24 ++-
 drivers/clk/berlin/Makefile                        |   2 +-
 drivers/clk/berlin/grp.c                           | 208 +++++++++++++++++++++
 6 files changed, 310 insertions(+), 19 deletions(-)
 create mode 100644 drivers/clk/berlin/grp.c

-- 
1.9.1

[RFC 0/5] berlin: add support for clocks sharing registers

[Alexandre Belloni]

Some clock on the berlin are sharing registers, this is an attempt at supporting
them.

I think there is a third set of regiters to enable/disable the clocks but I
don't have any information on that.

I'm also not completely sure of the DT bindings and I know that this is not the
way Sebastian was envisionning it.

Alexandre Belloni (5):
  clk: berlin: add support for clock groups
  clk: berlin: add berlin clock groups DT bindings documentation
  ARM: berlin/dt: add support for the clock group to BG2
  ARM: berlin/dt: add support for the clock group to BG2D
  ARM: berlin/dt: add support for the clock group to BG2Q

 .../devicetree/bindings/clock/berlin-clock.txt     |  29 +++
 arch/arm/boot/dts/berlin2.dtsi                     |  30 ++-
 arch/arm/boot/dts/berlin2cd.dtsi                   |  36 +++-
 arch/arm/boot/dts/berlin2q.dtsi                    |  24 ++-
 drivers/clk/berlin/Makefile                        |   2 +-
 drivers/clk/berlin/grp.c                           | 208 +++++++++++++++++++++
 6 files changed, 310 insertions(+), 19 deletions(-)
 create mode 100644 drivers/clk/berlin/grp.c

-- 
1.9.1

[RFC 1/5] clk: berlin: add support for clock groups

[Alexandre Belloni]

Add support for clocks sharing the same register set.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 drivers/clk/berlin/Makefile |   2 +-
 drivers/clk/berlin/grp.c    | 208 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/berlin/grp.c

diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 9bfa58eaf25a..893b2f2ba4fa 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -1,4 +1,4 @@
-obj-y += pll.o clk.o
+obj-y += pll.o clk.o grp.o
 obj-$(CONFIG_MACH_BERLIN_BG2)   += pll-berlin2.o
 obj-$(CONFIG_MACH_BERLIN_BG2CD) += pll-berlin2.o
 obj-$(CONFIG_MACH_BERLIN_BG2Q)  += pll-berlin2q.o
diff --git a/drivers/clk/berlin/grp.c b/drivers/clk/berlin/grp.c
new file mode 100644
index 000000000000..9e11e634ae20
--- /dev/null
+++ b/drivers/clk/berlin/grp.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * Based on code from Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "common.h"
+
+/*
+ * The clocks are sharing two kind of registers, the switch registers and the
+ * selection registers.
+ *
+ * The berlin_clkgrp struct has an offset (in bits) to the first bit related to
+ * the clock, from the start of the switch or selection region.
+ *
+ * The layout in the switch register is:
+ *        2         1        0
+ *  +----------+--------+--------+
+ *  | DIV3 SW  | DIV SW | PLL SW |
+ *  +----------+--------+--------+
+ *
+ *
+ * The layout in the selection register is:
+ *    5   4   3   2   1   0
+ *  +---+---+---+---+---+---+
+ *  |  DIVISOR  |    PLL    |
+ *  +---+---+---+---+---+---+
+ *
+ */
+
+#define CLK_PLL_SWITCH		BIT(0)
+#define CLK_SWITCH		BIT(1)
+#define CLK_DIV3_SWITCH		BIT(2)
+
+#define CLK_PLLSEL_MASK		7
+#define CLK_SEL_MASK		7
+#define CLK_SEL_SHIFT		3
+
+struct berlin_clkgrp_regs {
+	void __iomem *switch_base;
+	void __iomem *select_base;
+};
+
+struct berlin_clkgrp {
+	struct clk_hw hw;
+	struct berlin_clkgrp_regs *regs;
+	u32 switch_offset;
+	u32 select_offset;
+};
+
+#define to_berlin_clkgrp(hw) container_of(hw, struct berlin_clkgrp, hw)
+
+static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
+
+static u32 berlin_clkgrp_read(void __iomem *base, u32 offset)
+{
+	u32 offset_bytes = offset / 32;
+	u32 reg_offset = offset_bytes * 4;
+	u32 reg_shift = offset - (offset_bytes * 32);
+
+	return readl_relaxed(base + reg_offset) >> reg_shift;
+}
+
+static unsigned long berlin_clkgrp_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	u32 val, divider;
+	struct berlin_clkgrp *clk = to_berlin_clkgrp(hw);
+
+	val = berlin_clkgrp_read(clk->regs->switch_base, clk->switch_offset);
+	divider = 1;
+	if (val & CLK_DIV3_SWITCH) {
+		divider = 3;
+	} else if (val & CLK_SWITCH) {
+		val = berlin_clkgrp_read(clk->regs->select_base,
+					 clk->select_offset + CLK_SEL_SHIFT);
+		val &= CLK_SEL_MASK;
+		divider = clk_div[val];
+	}
+
+	return parent_rate / divider;
+}
+
+static u8 berlin_clkgrp_get_parent(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clkgrp *clk = to_berlin_clkgrp(hw);
+
+	val = berlin_clkgrp_read(clk->regs->switch_base, clk->switch_offset);
+	if (val & CLK_PLL_SWITCH) {
+		val = berlin_clkgrp_read(clk->regs->select_base,
+					 clk->select_offset);
+		return val & CLK_PLLSEL_MASK;
+	}
+
+	return 0;
+}
+
+static const struct clk_ops berlin_clkgrp_ops = {
+	.recalc_rate	= berlin_clkgrp_recalc_rate,
+	.get_parent	= berlin_clkgrp_get_parent,
+};
+
+static struct clk * __init berlin_clkgrp_register(struct device_node *np,
+		const char **parent_names, int num_parents,
+		struct berlin_clkgrp_regs *regs)
+{
+	struct berlin_clkgrp *bclk;
+	struct clk *clk;
+	struct clk_init_data init;
+	u32 switch_offset, select_offset;
+	int ret;
+
+	ret = of_property_read_u32(np, "marvell,clk-switch-offset",
+				   &switch_offset);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+	ret = of_property_read_u32(np, "marvell,clk-select-offset",
+				   &select_offset);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+
+	bclk = kzalloc(sizeof(*bclk), GFP_KERNEL);
+	if (WARN_ON(!bclk))
+		return ERR_PTR(-ENOMEM);
+
+	init.name = np->name;
+	init.ops = &berlin_clkgrp_ops;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	bclk->regs = regs;
+	bclk->switch_offset = switch_offset;
+	bclk->select_offset = select_offset;
+	bclk->hw.init = &init;
+
+	clk = clk_register(NULL, &bclk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return clk;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+
+	return clk;
+}
+
+void __init berlin_clkgrp_setup(struct device_node *np)
+{
+	struct device_node *childnp;
+	struct berlin_clkgrp_regs *regs;
+	const char **parent_names;
+	int nparents;
+	int i;
+
+	regs = kzalloc(sizeof(*regs), GFP_KERNEL);
+	if (WARN_ON(!regs))
+		return;
+
+	regs->switch_base = of_iomap(np, 0);
+	if (WARN_ON(!regs->switch_base))
+		goto exit;
+
+	regs->select_base = of_iomap(np, 1);
+	if (WARN_ON(!regs->select_base))
+		goto exit;
+
+	nparents = of_clk_get_parent_count(np);
+	if (WARN_ON(!nparents))
+		goto exit;
+
+	parent_names = kzalloc(nparents * sizeof(char *), GFP_KERNEL);
+	if (WARN_ON(!parent_names))
+		goto exit;
+
+	for (i = 0; i < nparents; i++) {
+		parent_names[i] = of_clk_get_parent_name(np, i);
+		if (!parent_names[i])
+			break;
+	}
+
+	for_each_child_of_node(np, childnp) {
+		berlin_clkgrp_register(childnp, parent_names, nparents,
+				       regs);
+	}
+
+	kfree(parent_names);
+exit:
+	kfree(regs);
+}
+CLK_OF_DECLARE(berlin_clk, "marvell,berlin2-clkgrp", berlin_clkgrp_setup);
-- 
1.9.1

[RFC 1/5] clk: berlin: add support for clock groups

[Alexandre Belloni]

Add support for clocks sharing the same register set.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 drivers/clk/berlin/Makefile |   2 +-
 drivers/clk/berlin/grp.c    | 208 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/berlin/grp.c

diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 9bfa58eaf25a..893b2f2ba4fa 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -1,4 +1,4 @@
-obj-y += pll.o clk.o
+obj-y += pll.o clk.o grp.o
 obj-$(CONFIG_MACH_BERLIN_BG2)   += pll-berlin2.o
 obj-$(CONFIG_MACH_BERLIN_BG2CD) += pll-berlin2.o
 obj-$(CONFIG_MACH_BERLIN_BG2Q)  += pll-berlin2q.o
diff --git a/drivers/clk/berlin/grp.c b/drivers/clk/berlin/grp.c
new file mode 100644
index 000000000000..9e11e634ae20
--- /dev/null
+++ b/drivers/clk/berlin/grp.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2014 Marvell Technology Group Ltd.
+ *
+ * Based on code from Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "common.h"
+
+/*
+ * The clocks are sharing two kind of registers, the switch registers and the
+ * selection registers.
+ *
+ * The berlin_clkgrp struct has an offset (in bits) to the first bit related to
+ * the clock, from the start of the switch or selection region.
+ *
+ * The layout in the switch register is:
+ *        2         1        0
+ *  +----------+--------+--------+
+ *  | DIV3 SW  | DIV SW | PLL SW |
+ *  +----------+--------+--------+
+ *
+ *
+ * The layout in the selection register is:
+ *    5   4   3   2   1   0
+ *  +---+---+---+---+---+---+
+ *  |  DIVISOR  |    PLL    |
+ *  +---+---+---+---+---+---+
+ *
+ */
+
+#define CLK_PLL_SWITCH		BIT(0)
+#define CLK_SWITCH		BIT(1)
+#define CLK_DIV3_SWITCH		BIT(2)
+
+#define CLK_PLLSEL_MASK		7
+#define CLK_SEL_MASK		7
+#define CLK_SEL_SHIFT		3
+
+struct berlin_clkgrp_regs {
+	void __iomem *switch_base;
+	void __iomem *select_base;
+};
+
+struct berlin_clkgrp {
+	struct clk_hw hw;
+	struct berlin_clkgrp_regs *regs;
+	u32 switch_offset;
+	u32 select_offset;
+};
+
+#define to_berlin_clkgrp(hw) container_of(hw, struct berlin_clkgrp, hw)
+
+static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
+
+static u32 berlin_clkgrp_read(void __iomem *base, u32 offset)
+{
+	u32 offset_bytes = offset / 32;
+	u32 reg_offset = offset_bytes * 4;
+	u32 reg_shift = offset - (offset_bytes * 32);
+
+	return readl_relaxed(base + reg_offset) >> reg_shift;
+}
+
+static unsigned long berlin_clkgrp_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	u32 val, divider;
+	struct berlin_clkgrp *clk = to_berlin_clkgrp(hw);
+
+	val = berlin_clkgrp_read(clk->regs->switch_base, clk->switch_offset);
+	divider = 1;
+	if (val & CLK_DIV3_SWITCH) {
+		divider = 3;
+	} else if (val & CLK_SWITCH) {
+		val = berlin_clkgrp_read(clk->regs->select_base,
+					 clk->select_offset + CLK_SEL_SHIFT);
+		val &= CLK_SEL_MASK;
+		divider = clk_div[val];
+	}
+
+	return parent_rate / divider;
+}
+
+static u8 berlin_clkgrp_get_parent(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clkgrp *clk = to_berlin_clkgrp(hw);
+
+	val = berlin_clkgrp_read(clk->regs->switch_base, clk->switch_offset);
+	if (val & CLK_PLL_SWITCH) {
+		val = berlin_clkgrp_read(clk->regs->select_base,
+					 clk->select_offset);
+		return val & CLK_PLLSEL_MASK;
+	}
+
+	return 0;
+}
+
+static const struct clk_ops berlin_clkgrp_ops = {
+	.recalc_rate	= berlin_clkgrp_recalc_rate,
+	.get_parent	= berlin_clkgrp_get_parent,
+};
+
+static struct clk * __init berlin_clkgrp_register(struct device_node *np,
+		const char **parent_names, int num_parents,
+		struct berlin_clkgrp_regs *regs)
+{
+	struct berlin_clkgrp *bclk;
+	struct clk *clk;
+	struct clk_init_data init;
+	u32 switch_offset, select_offset;
+	int ret;
+
+	ret = of_property_read_u32(np, "marvell,clk-switch-offset",
+				   &switch_offset);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+	ret = of_property_read_u32(np, "marvell,clk-select-offset",
+				   &select_offset);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+
+	bclk = kzalloc(sizeof(*bclk), GFP_KERNEL);
+	if (WARN_ON(!bclk))
+		return ERR_PTR(-ENOMEM);
+
+	init.name = np->name;
+	init.ops = &berlin_clkgrp_ops;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	bclk->regs = regs;
+	bclk->switch_offset = switch_offset;
+	bclk->select_offset = select_offset;
+	bclk->hw.init = &init;
+
+	clk = clk_register(NULL, &bclk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return clk;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		return ERR_PTR(ret);
+
+	return clk;
+}
+
+void __init berlin_clkgrp_setup(struct device_node *np)
+{
+	struct device_node *childnp;
+	struct berlin_clkgrp_regs *regs;
+	const char **parent_names;
+	int nparents;
+	int i;
+
+	regs = kzalloc(sizeof(*regs), GFP_KERNEL);
+	if (WARN_ON(!regs))
+		return;
+
+	regs->switch_base = of_iomap(np, 0);
+	if (WARN_ON(!regs->switch_base))
+		goto exit;
+
+	regs->select_base = of_iomap(np, 1);
+	if (WARN_ON(!regs->select_base))
+		goto exit;
+
+	nparents = of_clk_get_parent_count(np);
+	if (WARN_ON(!nparents))
+		goto exit;
+
+	parent_names = kzalloc(nparents * sizeof(char *), GFP_KERNEL);
+	if (WARN_ON(!parent_names))
+		goto exit;
+
+	for (i = 0; i < nparents; i++) {
+		parent_names[i] = of_clk_get_parent_name(np, i);
+		if (!parent_names[i])
+			break;
+	}
+
+	for_each_child_of_node(np, childnp) {
+		berlin_clkgrp_register(childnp, parent_names, nparents,
+				       regs);
+	}
+
+	kfree(parent_names);
+exit:
+	kfree(regs);
+}
+CLK_OF_DECLARE(berlin_clk, "marvell,berlin2-clkgrp", berlin_clkgrp_setup);
-- 
1.9.1

[RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Alexandre Belloni]

Document the device tree for the clocks sharing a common set of registers

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: devicetree@vger.kernel.org
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
index 49bc229827a0..6d374066d6b9 100644
--- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -11,10 +11,18 @@ Required properties:
 		CPU PLL and System PLL
 	"marvell,berlin2-clk":
 		simple clocks
+	"marvell,berlin2-clkgrp":
+		clocks sharing a common set of registers
 - reg: Address and length of the clock register set.
 - #clock-cells: from common clock binding; shall be set to 0.
 - clocks: from common clock binding
 
+For the clock groups:
+- marvell,clk-switch-offset: offset in bits to the first bit related to the
+  clock in the switch registers
+- marvell,clk-select-offset: offset in bits to the first bit related to the
+  clock in the selection registers.
+
 smclk: sysmgr-clock {
 	compatible = "fixed-clock";
 	#clock-cells = <0>;
@@ -34,3 +42,24 @@ sdio0xinclk: sdio0xinclk@ea023c {
 	#clock-cells = <0>;
 	reg = <0xea023c 0x4>;
 };
+
+
+grpclk: grpclk@ea00ec {
+	compatible = "marvell,berlin-clkgrp";
+	clocks = <&syspll>;
+	reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+	cfgclk: cfgclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <9>;
+		marvell,clk-select-offset = <12>;
+	};
+
+	nfcecccclk: nfcecccclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <27>;
+		marvell,clk-select-offset = <50>;
+	};
+};
+
+
-- 
1.9.1

[RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Alexandre Belloni]

Document the device tree for the clocks sharing a common set of registers

Signed-off-by: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
index 49bc229827a0..6d374066d6b9 100644
--- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -11,10 +11,18 @@ Required properties:
 		CPU PLL and System PLL
 	"marvell,berlin2-clk":
 		simple clocks
+	"marvell,berlin2-clkgrp":
+		clocks sharing a common set of registers
 - reg: Address and length of the clock register set.
 - #clock-cells: from common clock binding; shall be set to 0.
 - clocks: from common clock binding
 
+For the clock groups:
+- marvell,clk-switch-offset: offset in bits to the first bit related to the
+  clock in the switch registers
+- marvell,clk-select-offset: offset in bits to the first bit related to the
+  clock in the selection registers.
+
 smclk: sysmgr-clock {
 	compatible = "fixed-clock";
 	#clock-cells = <0>;
@@ -34,3 +42,24 @@ sdio0xinclk: sdio0xinclk@ea023c {
 	#clock-cells = <0>;
 	reg = <0xea023c 0x4>;
 };
+
+
+grpclk: grpclk@ea00ec {
+	compatible = "marvell,berlin-clkgrp";
+	clocks = <&syspll>;
+	reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+	cfgclk: cfgclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <9>;
+		marvell,clk-select-offset = <12>;
+	};
+
+	nfcecccclk: nfcecccclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <27>;
+		marvell,clk-select-offset = <50>;
+	};
+};
+
+
-- 
1.9.1

--
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[RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Alexandre Belloni]

Document the device tree for the clocks sharing a common set of registers

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: devicetree at vger.kernel.org
 .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
index 49bc229827a0..6d374066d6b9 100644
--- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
+++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
@@ -11,10 +11,18 @@ Required properties:
 		CPU PLL and System PLL
 	"marvell,berlin2-clk":
 		simple clocks
+	"marvell,berlin2-clkgrp":
+		clocks sharing a common set of registers
 - reg: Address and length of the clock register set.
 - #clock-cells: from common clock binding; shall be set to 0.
 - clocks: from common clock binding
 
+For the clock groups:
+- marvell,clk-switch-offset: offset in bits to the first bit related to the
+  clock in the switch registers
+- marvell,clk-select-offset: offset in bits to the first bit related to the
+  clock in the selection registers.
+
 smclk: sysmgr-clock {
 	compatible = "fixed-clock";
 	#clock-cells = <0>;
@@ -34,3 +42,24 @@ sdio0xinclk: sdio0xinclk at ea023c {
 	#clock-cells = <0>;
 	reg = <0xea023c 0x4>;
 };
+
+
+grpclk: grpclk at ea00ec {
+	compatible = "marvell,berlin-clkgrp";
+	clocks = <&syspll>;
+	reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+	cfgclk: cfgclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <9>;
+		marvell,clk-select-offset = <12>;
+	};
+
+	nfcecccclk: nfcecccclk {
+		#clock-cells = <0>;
+		marvell,clk-switch-offset = <27>;
+		marvell,clk-select-offset = <50>;
+	};
+};
+
+
-- 
1.9.1

[RFC 3/5] ARM: berlin/dt: add support for the clock group to BG2

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the cpu0 and perif clocks.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2.dtsi | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 2604c8692b77..589a71472e2e 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -43,12 +43,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: cfg-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -190,6 +184,30 @@
 			reg = <0xea003c 0x8>;
 		};
 
+		grpclk: grpclk@ea0154 {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+			cpu0clk: cpu0clk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <6>;
+				marvell,clk-select-offset = <6>;
+			};
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <15>;
+				marvell,clk-select-offset = <23>;
+			};
+
+			perifclk: perifclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <24>;
+				marvell,clk-select-offset = <41>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk@ea023c {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

[RFC 3/5] ARM: berlin/dt: add support for the clock group to BG2

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the cpu0 and perif clocks.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2.dtsi | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 2604c8692b77..589a71472e2e 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -43,12 +43,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: cfg-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -190,6 +184,30 @@
 			reg = <0xea003c 0x8>;
 		};
 
+		grpclk: grpclk at ea0154 {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+			cpu0clk: cpu0clk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <6>;
+				marvell,clk-select-offset = <6>;
+			};
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <15>;
+				marvell,clk-select-offset = <23>;
+			};
+
+			perifclk: perifclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <24>;
+				marvell,clk-select-offset = <41>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk at ea023c {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

[RFC 4/5] ARM: berlin/dt: add support for the clock group to BG2D

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the cpu0, perif and nfcecc clocks.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 36 ++++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index b05d32bf70e0..fe5a332908c9 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -36,12 +36,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: cfg-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <75000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -183,6 +177,36 @@
 			reg = <0xea003c 0x8>;
 		};
 
+		grpclk: grpclk@ea0154 {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea0164 0x8>, <0xea0154 0x8>;
+
+			cpu0clk: cpu0clk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <6>;
+				marvell,clk-select-offset = <6>;
+			};
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <15>;
+				marvell,clk-select-offset = <23>;
+			};
+
+			perifclk: perifclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <24>;
+				marvell,clk-select-offset = <41>;
+			};
+
+			nfceccclk: nfceccclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <33>;
+				marvell,clk-select-offset = <61>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk@ea023c {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

[RFC 4/5] ARM: berlin/dt: add support for the clock group to BG2D

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the cpu0, perif and nfcecc clocks.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 36 ++++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index b05d32bf70e0..fe5a332908c9 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -36,12 +36,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: cfg-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <75000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -183,6 +177,36 @@
 			reg = <0xea003c 0x8>;
 		};
 
+		grpclk: grpclk at ea0154 {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea0164 0x8>, <0xea0154 0x8>;
+
+			cpu0clk: cpu0clk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <6>;
+				marvell,clk-select-offset = <6>;
+			};
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <15>;
+				marvell,clk-select-offset = <23>;
+			};
+
+			perifclk: perifclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <24>;
+				marvell,clk-select-offset = <41>;
+			};
+
+			nfceccclk: nfceccclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <33>;
+				marvell,clk-select-offset = <61>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk at ea023c {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

[RFC 5/5] ARM: berlin/dt: add support for the clock group to BG2Q

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the nfcecc clock.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2q.dtsi | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 559819b89ea1..169c783ef262 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -53,12 +53,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: config-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -191,6 +185,24 @@
 			reg = <0xea0030 0x8>;
 		};
 
+		grpclk: grpclk@ea00ec {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <9>;
+				marvell,clk-select-offset = <12>;
+			};
+
+			nfceccclk: nfceccclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <27>;
+				marvell,clk-select-offset = <50>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk@ea0158 {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

[RFC 5/5] ARM: berlin/dt: add support for the clock group to BG2Q

[Alexandre Belloni]

Use the newly added marvell,berlin2-clkgrp driver, add real support for cfgclk
and add the nfcecc clock.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
 arch/arm/boot/dts/berlin2q.dtsi | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 559819b89ea1..169c783ef262 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -53,12 +53,6 @@
 		clock-frequency = <25000000>;
 	};
 
-	cfgclk: config-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
 	twdclk: twdclk {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
@@ -191,6 +185,24 @@
 			reg = <0xea0030 0x8>;
 		};
 
+		grpclk: grpclk at ea00ec {
+			compatible = "marvell,berlin2-clkgrp";
+			clocks = <&syspll>;
+			reg = <0xea00f8 0x4>, <0xea00ec 0xc>;
+
+			cfgclk: cfgclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <9>;
+				marvell,clk-select-offset = <12>;
+			};
+
+			nfceccclk: nfceccclk {
+				#clock-cells = <0>;
+				marvell,clk-switch-offset = <27>;
+				marvell,clk-select-offset = <50>;
+			};
+		};
+
 		sdio0xinclk: sdio0xinclk at ea0158 {
 			compatible = "marvell,berlin-clk";
 			clocks = <&syspll>;
-- 
1.9.1

Re: [RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1807 bytes --]

On Fri, Apr 25, 2014 at 10:00:21PM +0200, Alexandre Belloni wrote:
> Document the device tree for the clocks sharing a common set of registers
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Cc: devicetree@vger.kernel.org
>  .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> index 49bc229827a0..6d374066d6b9 100644
> --- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> @@ -11,10 +11,18 @@ Required properties:
>  		CPU PLL and System PLL
>  	"marvell,berlin2-clk":
>  		simple clocks
> +	"marvell,berlin2-clkgrp":
> +		clocks sharing a common set of registers
>  - reg: Address and length of the clock register set.

Judging from your code, you expect two arrays in reg. You should
document it and in which order you expect them.

Also, you'd probably want to use reg-names, which is much more
flexible from a DT point of view.

>  - #clock-cells: from common clock binding; shall be set to 0.
>  - clocks: from common clock binding
>  
> +For the clock groups:
> +- marvell,clk-switch-offset: offset in bits to the first bit related to the
> +  clock in the switch registers
> +- marvell,clk-select-offset: offset in bits to the first bit related to the
> +  clock in the selection registers.

Encoding bit offsets and/or register addresses in the DT is usually a
bad idea. You should more likely use different compatibles here.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1862 bytes --]

On Fri, Apr 25, 2014 at 10:00:21PM +0200, Alexandre Belloni wrote:
> Document the device tree for the clocks sharing a common set of registers
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>  .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> index 49bc229827a0..6d374066d6b9 100644
> --- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> @@ -11,10 +11,18 @@ Required properties:
>  		CPU PLL and System PLL
>  	"marvell,berlin2-clk":
>  		simple clocks
> +	"marvell,berlin2-clkgrp":
> +		clocks sharing a common set of registers
>  - reg: Address and length of the clock register set.

Judging from your code, you expect two arrays in reg. You should
document it and in which order you expect them.

Also, you'd probably want to use reg-names, which is much more
flexible from a DT point of view.

>  - #clock-cells: from common clock binding; shall be set to 0.
>  - clocks: from common clock binding
>  
> +For the clock groups:
> +- marvell,clk-switch-offset: offset in bits to the first bit related to the
> +  clock in the switch registers
> +- marvell,clk-select-offset: offset in bits to the first bit related to the
> +  clock in the selection registers.

Encoding bit offsets and/or register addresses in the DT is usually a
bad idea. You should more likely use different compatibles here.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[RFC 2/5] clk: berlin: add berlin clock groups DT bindings documentation

[Maxime Ripard]

On Fri, Apr 25, 2014 at 10:00:21PM +0200, Alexandre Belloni wrote:
> Document the device tree for the clocks sharing a common set of registers
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Cc: devicetree at vger.kernel.org
>  .../devicetree/bindings/clock/berlin-clock.txt     | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/berlin-clock.txt b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> index 49bc229827a0..6d374066d6b9 100644
> --- a/Documentation/devicetree/bindings/clock/berlin-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/berlin-clock.txt
> @@ -11,10 +11,18 @@ Required properties:
>  		CPU PLL and System PLL
>  	"marvell,berlin2-clk":
>  		simple clocks
> +	"marvell,berlin2-clkgrp":
> +		clocks sharing a common set of registers
>  - reg: Address and length of the clock register set.

Judging from your code, you expect two arrays in reg. You should
document it and in which order you expect them.

Also, you'd probably want to use reg-names, which is much more
flexible from a DT point of view.

>  - #clock-cells: from common clock binding; shall be set to 0.
>  - clocks: from common clock binding
>  
> +For the clock groups:
> +- marvell,clk-switch-offset: offset in bits to the first bit related to the
> +  clock in the switch registers
> +- marvell,clk-select-offset: offset in bits to the first bit related to the
> +  clock in the selection registers.

Encoding bit offsets and/or register addresses in the DT is usually a
bad idea. You should more likely use different compatibles here.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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