From: Gabriel FERNANDEZ <gabriel.fernandez@st.com> To: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>, Maxime Coquelin <maxime.coquelin@st.com>, Patrice Chotard <patrice.chotard@st.com>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones <lee.jones@linaro.org>, Gabriel Fernandez <gabriel.fernandez@linaro.org>, Pankaj Dev <pankaj.dev@st.com> Subject: [PATCH 4/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F Date: Mon, 5 May 2014 17:53:38 +0200 [thread overview] Message-ID: <1399305223-18703-5-git-send-email-gabriel.fernandez@linaro.org> (raw) In-Reply-To: <1399305223-18703-1-git-send-email-gabriel.fernandez@linaro.org> Patch adds DT entries for clockgen B/C/D/E/F Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih416-clock.dtsi | 189 +++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi index fdb5654..7ff107b 100644 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -503,5 +503,194 @@ /* Remaining outputs unused */ }; }; + + /* + * Frequency synthesizers on the SASG2 + */ + CLOCKGEN_B0: CLOCKGEN_B0 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee108b4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_USB48", + "CLK_S_DSS", + "CLK_S_STFE_FRC_2", + "CLK_S_THSENS_SCARD"; + }; + + CLOCKGEN_B1: CLOCKGEN_B1 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfe8308c4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_PCM_0", + "CLK_S_PCM_1", + "CLK_S_PCM_2", + "CLK_S_PCM_3"; + }; + + CLOCKGEN_C: CLOCKGEN_C { + #clock-cells = <1>; + compatible = "st,stih416-quadfs432", "st,quadfs"; + reg = <0xfe8307d0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_C_FS0_CH0", + "CLK_S_C_VCC_SD", + "CLK_S_C_FS0_CH2"; + }; + + CLK_S_VCC_HD: CLK_S_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; + reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ + + clocks = <&CLK_SYSIN>, + <&CLOCKGEN_C 0>; + }; + + /* + * Add a dummy clock for the HDMI PHY for the VCC input mux + */ + CLK_S_TMDS_FROMPHY: CLK_S_TMDS_FROMPHY { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_C_VCC: CLOCKGEN_C_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; + reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ + + clocks = <&CLK_S_VCC_HD>, + <&CLOCKGEN_C 1>, + <&CLK_S_TMDS_FROMPHY>, + <&CLOCKGEN_C 2>; + + clock-output-names = "CLK_S_PIX_HDMI", + "CLK_S_PIX_DVO", + "CLK_S_OUT_DVO", + "CLK_S_PIX_HD", + "CLK_S_HDDAC", + "CLK_S_DENC", + "CLK_S_SDDAC", + "CLK_S_PIX_MAIN", + "CLK_S_PIX_AUX", + "CLK_S_STFE_FRC_0", + "CLK_S_REF_MCRU", + "CLK_S_SLAVE_MCRU", + "CLK_S_TMDS_HDMI", + "CLK_S_HDMI_REJECT_PLL", + "CLK_S_THSENS"; + }; + + CLOCKGEN_D: CLOCKGEN_D { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee107e0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_CCSC", + "CLK_S_STFE_FRC_1", + "CLK_S_TSOUT_1", + "CLK_S_MCHI"; + }; + + /* + * Frequency synthesizers on the MPE42 + */ + CLOCKGEN_E: CLOCKGEN_E { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-E", "st,quadfs"; + reg = <0xfd3208bc 0xb0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_PIX_MDTP_0", + "CLK_M_PIX_MDTP_1", + "CLK_M_PIX_MDTP_2", + "CLK_M_MPELPC"; + }; + + CLOCKGEN_F: CLOCKGEN_F { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-F", "st,quadfs"; + reg = <0xfd320878 0xf0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_MAIN_VIDFS", + "CLK_M_HVA_FS", + "CLK_M_FVDP_VCPU", + "CLK_M_FVDP_PROC_FS"; + }; + + CLK_M_FVDP_PROC: CLK_M_FVDP_PROC { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; + reg = <0xfd320910 0x4>; /* SYSCFG8580 */ + + clocks = <&CLK_M_A1_DIV2 0>, + <&CLOCKGEN_F 3>; + }; + + CLK_M_HVA: CLK_M_HVA { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; + reg = <0xfd690868 0x4>; /* SYSCFG9538 */ + + clocks = <&CLOCKGEN_F 1>, + <&CLK_M_A1_DIV0 3>; + }; + + CLK_M_F_VCC_HD: CLK_M_F_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 7>, + <&CLOCKGEN_F 0>; + }; + + CLK_M_F_VCC_SD: CLK_M_F_VCC_SD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 8>, + <&CLOCKGEN_F 1>; + }; + + /* + * Add a dummy clock for the HDMIRx external signal clock + */ + CLK_M_PIX_HDMIRX_SAS: CLK_M_PIX_HDMIRX_SAS { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_F_VCC: CLOCKGEN_F_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; + reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ + + clocks = <&CLK_M_F_VCC_HD>, + <&CLK_M_F_VCC_SD>, + <&CLOCKGEN_F 0>, + <&CLK_M_PIX_HDMIRX_SAS>; + + clock-output-names = "CLK_M_PIX_MAIN_PIPE", + "CLK_M_PIX_AUX_PIPE", + "CLK_M_PIX_MAIN_CRU", + "CLK_M_PIX_AUX_CRU", + "CLK_M_XFER_BE_COMPO", + "CLK_M_XFER_PIP_COMPO", + "CLK_M_XFER_AUX_COMPO", + "CLK_M_VSENS", + "CLK_M_PIX_HDMIRX_0", + "CLK_M_PIX_HDMIRX_1"; + }; }; }; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: gabriel.fernandez@st.com (Gabriel FERNANDEZ) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F Date: Mon, 5 May 2014 17:53:38 +0200 [thread overview] Message-ID: <1399305223-18703-5-git-send-email-gabriel.fernandez@linaro.org> (raw) In-Reply-To: <1399305223-18703-1-git-send-email-gabriel.fernandez@linaro.org> Patch adds DT entries for clockgen B/C/D/E/F Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih416-clock.dtsi | 189 +++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi index fdb5654..7ff107b 100644 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -503,5 +503,194 @@ /* Remaining outputs unused */ }; }; + + /* + * Frequency synthesizers on the SASG2 + */ + CLOCKGEN_B0: CLOCKGEN_B0 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee108b4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_USB48", + "CLK_S_DSS", + "CLK_S_STFE_FRC_2", + "CLK_S_THSENS_SCARD"; + }; + + CLOCKGEN_B1: CLOCKGEN_B1 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfe8308c4 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_PCM_0", + "CLK_S_PCM_1", + "CLK_S_PCM_2", + "CLK_S_PCM_3"; + }; + + CLOCKGEN_C: CLOCKGEN_C { + #clock-cells = <1>; + compatible = "st,stih416-quadfs432", "st,quadfs"; + reg = <0xfe8307d0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_C_FS0_CH0", + "CLK_S_C_VCC_SD", + "CLK_S_C_FS0_CH2"; + }; + + CLK_S_VCC_HD: CLK_S_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; + reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ + + clocks = <&CLK_SYSIN>, + <&CLOCKGEN_C 0>; + }; + + /* + * Add a dummy clock for the HDMI PHY for the VCC input mux + */ + CLK_S_TMDS_FROMPHY: CLK_S_TMDS_FROMPHY { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_C_VCC: CLOCKGEN_C_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; + reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ + + clocks = <&CLK_S_VCC_HD>, + <&CLOCKGEN_C 1>, + <&CLK_S_TMDS_FROMPHY>, + <&CLOCKGEN_C 2>; + + clock-output-names = "CLK_S_PIX_HDMI", + "CLK_S_PIX_DVO", + "CLK_S_OUT_DVO", + "CLK_S_PIX_HD", + "CLK_S_HDDAC", + "CLK_S_DENC", + "CLK_S_SDDAC", + "CLK_S_PIX_MAIN", + "CLK_S_PIX_AUX", + "CLK_S_STFE_FRC_0", + "CLK_S_REF_MCRU", + "CLK_S_SLAVE_MCRU", + "CLK_S_TMDS_HDMI", + "CLK_S_HDMI_REJECT_PLL", + "CLK_S_THSENS"; + }; + + CLOCKGEN_D: CLOCKGEN_D { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee107e0 0x44>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_S_CCSC", + "CLK_S_STFE_FRC_1", + "CLK_S_TSOUT_1", + "CLK_S_MCHI"; + }; + + /* + * Frequency synthesizers on the MPE42 + */ + CLOCKGEN_E: CLOCKGEN_E { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-E", "st,quadfs"; + reg = <0xfd3208bc 0xb0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_PIX_MDTP_0", + "CLK_M_PIX_MDTP_1", + "CLK_M_PIX_MDTP_2", + "CLK_M_MPELPC"; + }; + + CLOCKGEN_F: CLOCKGEN_F { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-F", "st,quadfs"; + reg = <0xfd320878 0xf0>; + + clocks = <&CLK_SYSIN>; + clock-output-names = "CLK_M_MAIN_VIDFS", + "CLK_M_HVA_FS", + "CLK_M_FVDP_VCPU", + "CLK_M_FVDP_PROC_FS"; + }; + + CLK_M_FVDP_PROC: CLK_M_FVDP_PROC { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; + reg = <0xfd320910 0x4>; /* SYSCFG8580 */ + + clocks = <&CLK_M_A1_DIV2 0>, + <&CLOCKGEN_F 3>; + }; + + CLK_M_HVA: CLK_M_HVA { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; + reg = <0xfd690868 0x4>; /* SYSCFG9538 */ + + clocks = <&CLOCKGEN_F 1>, + <&CLK_M_A1_DIV0 3>; + }; + + CLK_M_F_VCC_HD: CLK_M_F_VCC_HD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 7>, + <&CLOCKGEN_F 0>; + }; + + CLK_M_F_VCC_SD: CLK_M_F_VCC_SD { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&CLOCKGEN_C_VCC 8>, + <&CLOCKGEN_F 1>; + }; + + /* + * Add a dummy clock for the HDMIRx external signal clock + */ + CLK_M_PIX_HDMIRX_SAS: CLK_M_PIX_HDMIRX_SAS { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + CLOCKGEN_F_VCC: CLOCKGEN_F_VCC { + #clock-cells = <1>; + compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; + reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ + + clocks = <&CLK_M_F_VCC_HD>, + <&CLK_M_F_VCC_SD>, + <&CLOCKGEN_F 0>, + <&CLK_M_PIX_HDMIRX_SAS>; + + clock-output-names = "CLK_M_PIX_MAIN_PIPE", + "CLK_M_PIX_AUX_PIPE", + "CLK_M_PIX_MAIN_CRU", + "CLK_M_PIX_AUX_CRU", + "CLK_M_XFER_BE_COMPO", + "CLK_M_XFER_PIP_COMPO", + "CLK_M_XFER_AUX_COMPO", + "CLK_M_VSENS", + "CLK_M_PIX_HDMIRX_0", + "CLK_M_PIX_HDMIRX_1"; + }; }; }; -- 1.9.1
next prev parent reply other threads:[~2014-05-05 15:55 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-05-05 15:53 [PATCH 0/9] ARM: STi: Add Clock driver support STiH415 & STiH416 Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 1/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-06 7:18 ` Lee Jones 2014-05-06 7:18 ` Lee Jones 2014-05-06 8:20 ` Gabriel Fernandez 2014-05-06 8:20 ` Gabriel Fernandez 2014-05-06 8:20 ` Gabriel Fernandez 2014-05-08 8:03 ` Lee Jones 2014-05-08 8:03 ` Lee Jones 2014-05-08 8:03 ` Lee Jones 2014-05-14 11:50 ` Maxime Coquelin 2014-05-14 11:50 ` Maxime Coquelin 2014-05-14 11:50 ` Maxime Coquelin 2014-05-19 9:30 ` Lee Jones 2014-05-19 9:30 ` Lee Jones 2014-05-05 15:53 ` [PATCH 2/9] ARM: STi: DT: STiH416: Remove unused CLK_S_ICN_REG_0 fixed clock Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 3/9] ARM: STi: DT: STiH416: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ [this message] 2014-05-05 15:53 ` [PATCH 4/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 5/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 6/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-06 7:20 ` Lee Jones 2014-05-06 7:20 ` Lee Jones 2014-05-05 15:53 ` [PATCH 7/9] ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clock Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 8/9] ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-05 15:53 ` [PATCH 9/9] ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9 Gabriel FERNANDEZ 2014-05-05 15:53 ` Gabriel FERNANDEZ 2014-05-14 11:46 ` [PATCH 0/9] ARM: STi: Add Clock driver support STiH415 & STiH416 Maxime Coquelin 2014-05-14 11:46 ` Maxime Coquelin 2014-05-14 11:46 ` Maxime Coquelin -- strict thread matches above, loose matches on Subject: below -- 2014-04-11 13:19 Gabriel FERNANDEZ 2014-04-11 13:19 ` [PATCH 4/9] ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F Gabriel FERNANDEZ
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1399305223-18703-5-git-send-email-gabriel.fernandez@linaro.org \ --to=gabriel.fernandez@st.com \ --cc=devicetree@vger.kernel.org \ --cc=gabriel.fernandez@linaro.org \ --cc=galak@codeaurora.org \ --cc=ijc+devicetree@hellion.org.uk \ --cc=kernel@stlinux.com \ --cc=lee.jones@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux@arm.linux.org.uk \ --cc=mark.rutland@arm.com \ --cc=maxime.coquelin@st.com \ --cc=pankaj.dev@st.com \ --cc=patrice.chotard@st.com \ --cc=pawel.moll@arm.com \ --cc=robh+dt@kernel.org \ --cc=srinivas.kandagatla@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.