[PATCH RFC 0/4] Add QCOM DML support to MMCI driver.

[PATCH RFC 0/4] Add QCOM DML support to MMCI driver.

[srinivas.kandagatla]

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

DML hardware is a glue in between SD Card Controller and DMA engine,
this hardware needs to be setup before and during any dma transfers.
This patchset adds DML support to the mmci driver.

This patchset is a very early version of adding Qualcomm DMA support to
generic mmci driver. There are two bits of changes which are done in 
a bit of hacky way. 

First one: Is DML code as part of MMCI driver?

Second one: Accessing BAM specific functions from generic mmci driver.
Ideally BAM descriptor flags need to be exposed in more generic way 
so that generic drivers could use it without much dependency on SOC specifics.


Having said this, these patches are published on request by Andy Gross for
testing purpose only.

This patches are tested on IFC8064 board with both eMMC and external SD card.
I would appreciate any feedback/suggestions on the overall approach. 

Srinivas Kandagatla (4):
  ARM: DT: QCOM: apq8064: fix the memory range for sdcc node.
  ARM: DT: QCOM: apq8064: Add dma support for sdcc node
  mmc: mmci: Add qcom dml support to the driver.
  mmc: mmci: do an EOT for write DMA requests.

 arch/arm/boot/dts/qcom-apq8064.dtsi |  30 ++++++-
 drivers/mmc/host/Kconfig            |  11 +++
 drivers/mmc/host/Makefile           |   1 +
 drivers/mmc/host/mmci.c             |  16 ++++
 drivers/mmc/host/qcom_dml.c         | 170 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/qcom_dml.h         |  17 ++++
 6 files changed, 243 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/qcom_dml.c
 create mode 100644 drivers/mmc/host/qcom_dml.h

-- 
1.9.1

[PATCH RFC 1/4] ARM: DT: QCOM: apq8064: fix the memory range for sdcc node.

[srinivas.kandagatla]

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch fixes the range of iomemory for sdcc controller, it is now
set to 0x2000 so that the mmci driver could talk to dml hardware as well.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 640fb1d..2a6cd09 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -167,7 +167,7 @@
 				status		= "disabled";
 				compatible	= "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00051180>;
-				reg		= <0x12400000 0x8000>;
+				reg		= <0x12400000 0x2000>;
 				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names	= "cmd_irq";
 				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
@@ -184,7 +184,7 @@
 				compatible	= "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00051180>;
 				status		= "disabled";
-				reg		= <0x12180000 0x8000>;
+				reg		= <0x12180000 0x2000>;
 				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names	= "cmd_irq";
 				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
-- 
1.9.1

[PATCH RFC 2/4] ARM: DT: QCOM: apq8064: Add dma support for sdcc node

[srinivas.kandagatla]

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds dma support in both sdcc1 and sdcc3 device node.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 2a6cd09..24d6dd7 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -158,6 +158,28 @@
 			regulator-always-on;
 		};
 
+		sdcc1bam:dma@12402000{
+			compatible = "qcom,bam-v1.3.0";
+			reg = <0x12402000 0x8000>, <0x12400800 0x800>;
+			reg-names = "bam", "dml";
+			interrupts = <0 98 0>;
+			clocks = <&gcc SDC1_H_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
+		sdcc3bam:dma@12182000{
+			compatible = "qcom,bam-v1.3.0";
+			reg = <0x12182000 0x8000>, <0x12180800 0x800>;
+			reg-names = "bam", "dml";
+			interrupts = <0 96 0>;
+			clocks = <&gcc SDC3_H_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+		};
+
 		amba {
 			compatible = "arm,amba-bus";
 			#address-cells = <1>;
@@ -178,6 +200,8 @@
 				cap-sd-highspeed;
 				cap-mmc-highspeed;
 				vmmc-supply = <&vsdcc_fixed>;
+				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+				dma-names = "tx", "rx";
 			};
 
 			sdcc3: sdcc@12180000 {
@@ -195,6 +219,8 @@
 				max-frequency	= <192000000>;
 				no-1-8-v;
 				vmmc-supply = <&vsdcc_fixed>;
+				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+				dma-names = "tx", "rx";
 			};
 		};
 	};
-- 
1.9.1

[PATCH RFC 3/4] mmc: mmci: Add qcom dml support to the driver.

[srinivas.kandagatla]

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to do dma transfers between
Controller and DMA engine. This hardware needs to be setup before any
dma transfer is requested.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.

Please Note: this is a just a first version of the patch, so there is a
scope of improvement on this.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/mmc/host/Kconfig    |  11 +++
 drivers/mmc/host/Makefile   |   1 +
 drivers/mmc/host/mmci.c     |  12 ++++
 drivers/mmc/host/qcom_dml.c | 170 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/qcom_dml.h |  17 +++++
 5 files changed, 211 insertions(+)
 create mode 100644 drivers/mmc/host/qcom_dml.c
 create mode 100644 drivers/mmc/host/qcom_dml.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8aaf8c1..55cb57b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -14,6 +14,17 @@ config MMC_ARMMMCI
 
 	  If unsure, say N.
 
+config MMC_QCOM_DML
+	tristate "Qualcomm Data Mover for SD Card Controller"
+	depends on MMC_ARMMMCI
+	default y
+	help
+	  This selects the Qualcomm Data Mover lite/local on SD Card controller.
+	  This option will enable the dma to work correctly, if you are using
+	  Qcom SOCs and MMC, you would probably need this option to get DMA working.
+
+	  if unsure, say N.
+
 config MMC_PXA
 	tristate "Intel PXA25x/26x/27x Multimedia Card Interface support"
 	depends on ARCH_PXA
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 0c8aa5e..07ea02a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o
+obj-$(CONFIG_MMC_QCOM_DML)	+= qcom_dml.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
 obj-$(CONFIG_MMC_MXC)		+= mxcmmc.o
 obj-$(CONFIG_MMC_MXS)		+= mxs-mmc.o
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 94b99d6..847a4ba 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -43,6 +43,7 @@
 #include <asm/sizes.h>
 
 #include "mmci.h"
+#include "qcom_dml.h"
 
 #define DRIVER_NAME "mmci-pl18x"
 
@@ -78,6 +79,7 @@ static unsigned int fmax = 515633;
  * @explicit_mclk_control: enable explicit mclk control in driver.
  * @qcom_cclk_is_mclk: enable iff card clock is multimedia card adapter clock.
  * @qcom_fifo: enables qcom specific fifo pio read function.
+ * @qcom_dml: enables qcom specific dml glue for dma transfers.
  */
 struct variant_data {
 	unsigned int		clkreg;
@@ -103,6 +105,7 @@ struct variant_data {
 	bool			explicit_mclk_control;
 	bool			qcom_cclk_is_mclk;
 	bool			qcom_fifo;
+	bool			qcom_dml;
 };
 
 static struct variant_data variant_arm = {
@@ -214,6 +217,7 @@ static struct variant_data variant_qcom = {
 	.explicit_mclk_control	= true,
 	.qcom_cclk_is_mclk	= true,
 	.qcom_fifo		= true,
+	.qcom_dml		= true,
 };
 
 static inline u32 mmci_readl(struct mmci_host *host, u32 off)
@@ -664,6 +668,9 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 	dmaengine_submit(host->dma_desc_current);
 	dma_async_issue_pending(host->dma_current);
 
+	if (host->variant->qcom_dml)
+		dml_start_xfer(host, data);
+
 	datactrl |= MCI_DPSM_DMAENABLE;
 
 	/* Trigger the DMA transfer */
@@ -1702,6 +1709,11 @@ static int mmci_probe(struct amba_device *dev,
 
 	mmci_dma_setup(host);
 
+	if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) {
+		if (dml_hw_init(host, np))
+			variant->qcom_dml = false;
+	}
+
 	pm_runtime_set_autosuspend_delay(&dev->dev, 50);
 	pm_runtime_use_autosuspend(&dev->dev);
 	pm_runtime_put(&dev->dev);
diff --git a/drivers/mmc/host/qcom_dml.c b/drivers/mmc/host/qcom_dml.c
new file mode 100644
index 0000000..5d61e4c
--- /dev/null
+++ b/drivers/mmc/host/qcom_dml.c
@@ -0,0 +1,170 @@
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include "mmci.h"
+
+/* DML config register defination */
+#define DML_CONFIG			0x00
+#define PRODUCER_CRCI_DIS		0x00
+#define PRODUCER_CRCI_X_SEL		0x01
+#define PRODUCER_CRCI_Y_SEL		0x02
+#define PRODUCER_CRCI_MSK		0x3
+#define CONSUMER_CRCI_DIS		(0x00 << 2)
+#define CONSUMER_CRCI_X_SEL		(0x01 << 2)
+#define CONSUMER_CRCI_Y_SEL		(0x02 << 2)
+#define CONSUMER_CRCI_MSK		(0x3 << 2)
+#define PRODUCER_TRANS_END_EN		(1 << 4)
+#define BYPASS				(1 << 16)
+#define DIRECT_MODE			(1 << 17)
+#define INFINITE_CONS_TRANS		(1 << 18)
+
+#define DML_SW_RESET			0x08
+#define DML_PRODUCER_START		0x0C
+#define DML_CONSUMER_START		0x10
+#define DML_PRODUCER_PIPE_LOGICAL_SIZE	0x14
+#define DML_CONSUMER_PIPE_LOGICAL_SIZE	0x18
+#define DML_PIPE_ID			0x1C
+#define DML_PRODUCER_BAM_BLOCK_SIZE	0x24
+#define DML_PRODUCER_BAM_TRANS_SIZE	0x28
+#define PRODUCER_PIPE_ID_SHFT		0
+#define PRODUCER_PIPE_ID_MSK		0x1f
+#define CONSUMER_PIPE_ID_SHFT		16
+#define CONSUMER_PIPE_ID_MSK		(0x1f << 16)
+/* other definations */
+#define PRODUCER_PIPE_LOGICAL_SIZE	4096
+#define CONSUMER_PIPE_LOGICAL_SIZE	4096
+
+#define DML_OFFSET			0x800
+
+void dml_start_xfer(struct mmci_host *host, struct mmc_data *data)
+{
+	u32 config;
+	void __iomem *dml_base;
+	dml_base = host->base + DML_OFFSET;
+
+	if (data->flags & MMC_DATA_READ) {
+		/* Read operation: configure DML for producer operation */
+		/* Set producer CRCI-x and disable consumer CRCI */
+		config = readl(dml_base + DML_CONFIG);
+		config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_X_SEL;
+		config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_DIS;
+		writel(config, (dml_base + DML_CONFIG));
+
+		/* Set the Producer BAM block size */
+		writel(data->blksz, (dml_base +
+					DML_PRODUCER_BAM_BLOCK_SIZE));
+
+		/* Set Producer BAM Transaction size */
+		writel(data->blocks * data->blksz,
+			(dml_base + DML_PRODUCER_BAM_TRANS_SIZE));
+		/* Set Producer Transaction End bit */
+		writel((readl_relaxed(dml_base + DML_CONFIG)
+			| PRODUCER_TRANS_END_EN),
+			(dml_base + DML_CONFIG));
+		/* Trigger producer */
+		writel(1, (dml_base + DML_PRODUCER_START));
+	} else {
+		/* Write operation: configure DML for consumer operation */
+		/* Set consumer CRCI-x and disable producer CRCI*/
+		config = readl(dml_base + DML_CONFIG);
+		config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_X_SEL;
+		config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_DIS;
+
+		config = 0x4;
+		writel(config, (dml_base + DML_CONFIG));
+		/* Clear Producer Transaction End bit */
+		writel((readl_relaxed(dml_base + DML_CONFIG)
+			& ~PRODUCER_TRANS_END_EN),
+			(dml_base + DML_CONFIG));
+		/* Trigger consumer */
+		writel(1, (dml_base + DML_CONSUMER_START));
+	}
+}
+
+static int of_get_dml_pipe_index(struct device_node *np, const char *name)
+{
+	int count, i;
+	const char *s;
+	struct of_phandle_args	dma_spec;
+
+	if (!np || !name)
+		return -ENODEV;
+
+	count = of_property_count_strings(np, "dma-names");
+	if (count < 0)
+		return -ENODEV;
+
+	for (i = 0; i < count; i++) {
+
+		if (of_property_read_string_index(np, "dma-names", i, &s))
+			continue;
+
+		if (strcmp(name, s))
+			continue;
+
+		if (of_parse_phandle_with_args(np, "dmas", "#dma-cells", i,
+				       &dma_spec))
+			continue;
+
+		if (dma_spec.args_count)
+			return dma_spec.args[0];
+	}
+
+	return -ENODEV;
+}
+
+/* Initialize the dml hardware connectd to SD Card controller */
+int dml_hw_init(struct mmci_host *host, struct device_node *np)
+{
+	u32 config = 0;
+	void __iomem *dml_base;
+	u32 consumer_id = 0, producer_id = 0;
+
+	consumer_id = of_get_dml_pipe_index(np, "tx");
+	producer_id = of_get_dml_pipe_index(np, "rx");
+
+	if (IS_ERR_VALUE(producer_id) || IS_ERR_VALUE(consumer_id))
+		return -ENODEV;
+
+	dml_base = host->base + DML_OFFSET;
+
+	/* Reset the DML block */
+	writel(1, (dml_base + DML_SW_RESET));
+
+	/* Disable the producer and consumer CRCI */
+	config = (PRODUCER_CRCI_DIS | CONSUMER_CRCI_DIS);
+	/*
+	 * Disable the bypass mode. Bypass mode will only be used
+	 * if data transfer is to happen in PIO mode and don't
+	 * want the BAM interface to connect with SDCC-DML.
+	 */
+	config &= ~BYPASS;
+	/*
+	 * Disable direct mode as we don't DML to MASTER the AHB bus.
+	 * BAM connected with DML should MASTER the AHB bus.
+	 */
+	config &= ~DIRECT_MODE;
+	/*
+	 * Disable infinite mode transfer as we won't be doing any
+	 * infinite size data transfers. All data transfer will be
+	 * of finite data size.
+	 */
+	config &= ~INFINITE_CONS_TRANS;
+	writel(config, (dml_base + DML_CONFIG));
+
+	/*
+	 * Initialize the logical BAM pipe size for producer
+	 * and consumer.
+	 */
+	writel(PRODUCER_PIPE_LOGICAL_SIZE,
+		(dml_base + DML_PRODUCER_PIPE_LOGICAL_SIZE));
+	writel(CONSUMER_PIPE_LOGICAL_SIZE,
+		(dml_base + DML_CONSUMER_PIPE_LOGICAL_SIZE));
+
+	/* Initialize Producer/consumer pipe id */
+	writel(producer_id | (consumer_id << CONSUMER_PIPE_ID_SHFT),
+		(dml_base + DML_PIPE_ID));
+
+	return 0;
+}
diff --git a/drivers/mmc/host/qcom_dml.h b/drivers/mmc/host/qcom_dml.h
new file mode 100644
index 0000000..d2c5aa45
--- /dev/null
+++ b/drivers/mmc/host/qcom_dml.h
@@ -0,0 +1,17 @@
+#ifndef __MMC_QCOM_DML_H__
+#define __MMC_QCOM_DML_H__
+
+#ifdef CONFIG_MMC_QCOM_DML
+int dml_hw_init(struct mmci_host *host, struct device_node *np);
+void dml_start_xfer(struct mmci_host *host, struct mmc_data *data);
+#else
+static inline int dml_hw_init(struct mmci_host *host, struct device_node *np)
+{
+	return -ENOSYS;
+}
+static inline void dml_start_xfer(struct mmci_host *host, struct mmc_data *data)
+{
+}
+#endif /* CONFIG_MMC_QCOM_DML */
+
+#endif /* __MMC_QCOM_DML_H__ */
-- 
1.9.1

[PATCH RFC 4/4] mmc: mmci: do an EOT for write DMA requests.

[srinivas.kandagatla]

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds an hack to get the BAM working. In general generic
drivers are not allowed to call SOC specific functions, but as this is
just an hack for demo.

Currently, Andy Gross is looking at, how to expose this function in more
generic way.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/mmc/host/mmci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 847a4ba..5ba8c80 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -652,6 +652,7 @@ static inline int mmci_dma_prep_next(struct mmci_host *host,
 	return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
 }
 
+extern void qcom_bam_set_desc_eot(struct dma_async_tx_descriptor *txd);
 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 {
 	int ret;
@@ -661,6 +662,9 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 	if (ret)
 		return ret;
 
+	if (data->flags & MMC_DATA_WRITE)
+		qcom_bam_set_desc_eot(host->dma_desc_current);
+
 	/* Okay, go for it. */
 	dev_vdbg(mmc_dev(host->mmc),
 		 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
-- 
1.9.1

Re: [PATCH RFC 2/4] ARM: DT: QCOM: apq8064: Add dma support for sdcc node

[Srinivas Kandagatla]

On 16/05/14 20:45, srinivas.kandagatla@linaro.org wrote:
> +			reg = <0x12402000 0x8000>, <0x12400800 0x800>;


I think the second entry is just a leftover from my previous patch, this 
should not hurt the testing.. but I will remove it in next version.

Thanks,
srini