[U-Boot] [PATCH][v2] driver/nand: Add support of 16K SRAM for IFC 2.0

[U-Boot] [PATCH][v2] driver/nand: Add support of 16K SRAM for IFC 2.0

[Prabhakar Kushwaha]

Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: rebased the patch

 drivers/mtd/nand/fsl_ifc_nand.c |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 280e14e..fd5f536 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -24,6 +24,7 @@
 #endif
 
 #define FSL_IFC_V1_1_0	0x01010000
+#define FSL_IFC_V2_0_0	0x02000000
 #define MAX_BANKS	CONFIG_SYS_FSL_IFC_BANK_COUNT
 #define ERR_BYTE	0xFF /* Value returned for read bytes
 				when read failed */
@@ -1040,6 +1041,30 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
+	if (ver >= FSL_IFC_V2_0_0) {
+		switch (csor & CSOR_NAND_PGS_MASK) {
+		case CSOR_NAND_PGS_512:
+			priv->bufnum_mask = 31;
+		break;
+
+		case CSOR_NAND_PGS_2K:
+		priv->bufnum_mask = 7;
+		break;
+
+		case CSOR_NAND_PGS_4K:
+		priv->bufnum_mask = 3;
+		break;
+
+		case CSOR_NAND_PGS_8K:
+		priv->bufnum_mask = 1;
+		break;
+
+		default:
+			printf("ifc nand: bad csor %#x: bad page size\n", csor);
+			return -ENODEV;
+		}
+	}
+
 	ret = nand_scan_ident(mtd, 1, NULL);
 	if (ret)
 		return ret;
-- 
1.7.9.5

[U-Boot] [PATCH][v2] driver/nand: Add support of 16K SRAM for IFC 2.0

[Scott Wood]

On Thu, 2014-06-12 at 12:14 +0530, Prabhakar Kushwaha wrote:
> Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.
> 
> Update the page offset calculation logic to support the same.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Changes for v2: rebased the patch
> 
>  drivers/mtd/nand/fsl_ifc_nand.c |   25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 280e14e..fd5f536 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -24,6 +24,7 @@
>  #endif
>  
>  #define FSL_IFC_V1_1_0	0x01010000
> +#define FSL_IFC_V2_0_0	0x02000000
>  #define MAX_BANKS	CONFIG_SYS_FSL_IFC_BANK_COUNT
>  #define ERR_BYTE	0xFF /* Value returned for read bytes
>  				when read failed */
> @@ -1040,6 +1041,30 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
>  	if (ret)
>  		return ret;
>  
> +	if (ver >= FSL_IFC_V2_0_0) {
> +		switch (csor & CSOR_NAND_PGS_MASK) {
> +		case CSOR_NAND_PGS_512:
> +			priv->bufnum_mask = 31;
> +		break;
> +
> +		case CSOR_NAND_PGS_2K:
> +		priv->bufnum_mask = 7;
> +		break;
> +
> +		case CSOR_NAND_PGS_4K:
> +		priv->bufnum_mask = 3;
> +		break;
> +
> +		case CSOR_NAND_PGS_8K:
> +		priv->bufnum_mask = 1;
> +		break;

Whitespace

Instead of this, how about:

	if (ver >= FSL_IFC_V2_0_0)
		priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;

-Scott