* [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set @ 2014-05-21 11:10 Vandana Kannan 2014-05-21 11:10 ` [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 Vandana Kannan 2014-06-18 14:17 ` [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan 0 siblings, 2 replies; 10+ messages in thread From: Vandana Kannan @ 2014-05-21 11:10 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter For Gen < 8, set M2_N2 registers on every mode set. This is required to make sure M2_N2 registers are set during boot, resume from sleep for cross- checking the state. The register is set only if DRRS is supported. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_dp.c | 14 -------------- drivers/gpu/drm/i915/intel_drv.h | 1 + 4 files changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6b0e174..b82f157 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1956,6 +1956,9 @@ struct drm_i915_cmd_table { #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ + to_i915(dev)->drrs.connector-> \ + panel.downclock_mode) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 767ca96..cf3ad87 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5278,6 +5278,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); } +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder transcoder = crtc->config.cpu_transcoder; + + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); +} + static void vlv_update_pll(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -5872,8 +5884,12 @@ skip_dpll: dspcntr |= DISPPLANE_SEL_PIPE_B; } - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -6881,8 +6897,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } else intel_put_shared_dpll(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } if (is_lvds && has_reduced_clock && i915.powersave) intel_crtc->lowfreq_avail = true; @@ -7377,8 +7397,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, return -EINVAL; intel_ddi_pll_enable(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_crtc->lowfreq_avail = false; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9f67b72..bcab4ea 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, } } -static void -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder transcoder = crtc->config.cpu_transcoder; - - I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); -} - bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index acfc5c8..5233a3d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -792,6 +792,7 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv); void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_config *pipe_config); int intel_format_to_fourcc(int format); +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); /* intel_dp.c */ void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); -- 1.9.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 2014-05-21 11:10 [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan @ 2014-05-21 11:10 ` Vandana Kannan 2014-05-21 12:33 ` Daniel Vetter 2014-06-18 14:17 ` [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan 1 sibling, 1 reply; 10+ messages in thread From: Vandana Kannan @ 2014-05-21 11:10 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter Adding relevant read out comparison code, in check_crtc_state, for the new member of crtc_config, dp_m2_n2, which was introduced to store link_m_n values for a DP downclock mode (if available). Suggested by Daniel. v2: Changed patch title. Daniel's review comments incorporated. Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done only when high RR is not in use (This is because alternate m_n register programming will be done only when low RR is being used). v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake. Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures based on DRRS state for gen 8 and above. Save and restore M2 N2 registers for gen 7 and below v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is only one set of M_N registers Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 8 ++++ drivers/gpu/drm/i915/i915_ums.c | 26 +++++++++++ drivers/gpu/drm/i915/intel_ddi.c | 1 + drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_dp.c | 2 + drivers/gpu/drm/i915/intel_drv.h | 2 + 6 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b82f157..a06551a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -815,6 +815,14 @@ struct i915_suspend_saved_registers { u32 savePIPEB_DATA_N1; u32 savePIPEB_LINK_M1; u32 savePIPEB_LINK_N1; + u32 savePIPEA_DATA_M2; + u32 savePIPEA_DATA_N2; + u32 savePIPEA_LINK_M2; + u32 savePIPEA_LINK_N2; + u32 savePIPEB_DATA_M2; + u32 savePIPEB_DATA_N2; + u32 savePIPEB_LINK_M2; + u32 savePIPEB_LINK_N2; u32 saveMCHBAR_RENDER_STANDBY; u32 savePCH_PORT_HOTPLUG; }; diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c index 480da59..82fc08f 100644 --- a/drivers/gpu/drm/i915/i915_ums.c +++ b/drivers/gpu/drm/i915/i915_ums.c @@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev) dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); + /* Saving M2_N2 registers only for Gen7 because DRRS will be + * used only from Gen7 and for Gen8 & above there is no + * M2_N2 register. + */ + if (INTEL_INFO(dev)->gen == 7) { + dev_priv->regfile.savePIPEA_DATA_M2 = + I915_READ(_PIPEA_DATA_M2); + dev_priv->regfile.savePIPEA_DATA_N2 = + I915_READ(_PIPEA_DATA_N2); + dev_priv->regfile.savePIPEA_LINK_M2 = + I915_READ(_PIPEA_LINK_M2); + dev_priv->regfile.savePIPEA_LINK_N2 = + I915_READ(_PIPEA_LINK_N2); + } + dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); @@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev) I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1); I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1); + if (INTEL_INFO(dev)->gen == 7) { + I915_WRITE(_PIPEA_DATA_M2, + dev_priv->regfile.savePIPEA_DATA_M2); + I915_WRITE(_PIPEA_DATA_N2, + dev_priv->regfile.savePIPEA_DATA_N2); + I915_WRITE(_PIPEA_LINK_M2, + dev_priv->regfile.savePIPEA_LINK_M2); + I915_WRITE(_PIPEA_LINK_N2, + dev_priv->regfile.savePIPEA_LINK_N2); + } + I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL); I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0ad4e96..6784f0b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->has_dp_encoder = true; intel_dp_get_m_n(intel_crtc, pipe_config); + intel_dp_get_m2_n2(intel_crtc, pipe_config); break; default: break; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cf3ad87..09fc286 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6980,6 +6980,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, &pipe_config->dp_m_n); } +void intel_dp_get_m2_n2(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder transcoder = pipe_config->cpu_transcoder; + + if (INTEL_INFO(dev)->gen >= 8) { + intel_cpu_transcoder_get_m_n(crtc, transcoder, + &pipe_config->dp_m2_n2); + } else if (INTEL_INFO(dev)->gen > 6) { + pipe_config->dp_m2_n2.link_m = + I915_READ(PIPE_LINK_M2(transcoder)); + pipe_config->dp_m2_n2.link_n = + I915_READ(PIPE_LINK_N2(transcoder)); + pipe_config->dp_m2_n2.gmch_m = + I915_READ(PIPE_DATA_M2(transcoder)) + & ~TU_SIZE_MASK; + pipe_config->dp_m2_n2.gmch_n = + I915_READ(PIPE_DATA_N2(transcoder)); + pipe_config->dp_m2_n2.tu = + ((I915_READ(PIPE_DATA_M2(transcoder)) + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; + } + +} + + static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { @@ -9485,6 +9513,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, pipe_config->dp_m_n.tu); + + DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", + pipe_config->has_dp_encoder, + pipe_config->dp_m2_n2.gmch_m, + pipe_config->dp_m2_n2.gmch_n, + pipe_config->dp_m2_n2.link_m, + pipe_config->dp_m2_n2.link_n, + pipe_config->dp_m2_n2.tu); + DRM_DEBUG_KMS("requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->requested_mode); DRM_DEBUG_KMS("adjusted mode:\n"); @@ -9867,6 +9904,26 @@ intel_pipe_config_compare(struct drm_device *dev, return false; \ } +/* This is required for BDW+ where there is only one set of registers for + * switching between high and low RR. + * This macro can be used whenever a comparison has to be made between one + * hw state and multiple sw state variables. + */ +#define PIPE_CONF_CHECK_I_I(name1, name2) \ + if (current_config->name1 != pipe_config->name1) { \ + DRM_ERROR("mismatch in " #name1 " " \ + "(expected %i, found %i)\n", \ + current_config->name1, \ + pipe_config->name1); \ + if (current_config->name2 != pipe_config->name2) { \ + DRM_ERROR("mismatch in " #name2 " " \ + "(expected %i, found %i)\n", \ + current_config->name2, \ + pipe_config->name2); \ + return false; \ + } \ + } + #define PIPE_CONF_CHECK_FLAGS(name, mask) \ if ((current_config->name ^ pipe_config->name) & (mask)) { \ DRM_ERROR("mismatch in " #name "(" #mask ") " \ @@ -9899,11 +9956,26 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(fdi_m_n.tu); PIPE_CONF_CHECK_I(has_dp_encoder); - PIPE_CONF_CHECK_I(dp_m_n.gmch_m); - PIPE_CONF_CHECK_I(dp_m_n.gmch_n); - PIPE_CONF_CHECK_I(dp_m_n.link_m); - PIPE_CONF_CHECK_I(dp_m_n.link_n); - PIPE_CONF_CHECK_I(dp_m_n.tu); + + if (INTEL_INFO(dev)->gen < 8) { + PIPE_CONF_CHECK_I(dp_m_n.gmch_m); + PIPE_CONF_CHECK_I(dp_m_n.gmch_n); + PIPE_CONF_CHECK_I(dp_m_n.link_m); + PIPE_CONF_CHECK_I(dp_m_n.link_n); + PIPE_CONF_CHECK_I(dp_m_n.tu); + + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); + PIPE_CONF_CHECK_I(dp_m2_n2.link_m); + PIPE_CONF_CHECK_I(dp_m2_n2.link_n); + PIPE_CONF_CHECK_I(dp_m2_n2.tu); + } else { + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_m, dp_m2_n2.gmch_m); + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_n, dp_m2_n2.gmch_n); + PIPE_CONF_CHECK_I_I(dp_m_n.link_m, dp_m2_n2.link_m); + PIPE_CONF_CHECK_I_I(dp_m_n.link_n, dp_m2_n2.link_n); + PIPE_CONF_CHECK_I_I(dp_m_n.tu, dp_m2_n2.tu); + } PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); @@ -9980,6 +10052,7 @@ intel_pipe_config_compare(struct drm_device *dev, #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_I_I #undef PIPE_CONF_CHECK_FLAGS #undef PIPE_CONF_CHECK_CLOCK_FUZZY #undef PIPE_CONF_QUIRK diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bcab4ea..c55f827 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1555,6 +1555,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, intel_dp_get_m_n(crtc, pipe_config); + intel_dp_get_m2_n2(crtc, pipe_config); + if (port == PORT_A) { if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) pipe_config->port_clock = 162000; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5233a3d..2b4cd30 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -778,6 +778,8 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config); +void intel_dp_get_m2_n2(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config); int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, -- 1.9.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 2014-05-21 11:10 ` [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 Vandana Kannan @ 2014-05-21 12:33 ` Daniel Vetter 2014-05-22 5:50 ` Vandana Kannan 0 siblings, 1 reply; 10+ messages in thread From: Daniel Vetter @ 2014-05-21 12:33 UTC (permalink / raw) To: Vandana Kannan; +Cc: Daniel Vetter, intel-gfx On Wed, May 21, 2014 at 04:40:04PM +0530, Vandana Kannan wrote: > Adding relevant read out comparison code, in check_crtc_state, for the new > member of crtc_config, dp_m2_n2, which was introduced to store link_m_n > values for a DP downclock mode (if available). Suggested by Daniel. > > v2: Changed patch title. > Daniel's review comments incorporated. > Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done > only when high RR is not in use (This is because alternate m_n register > programming will be done only when low RR is being used). > > v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake. > Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures > based on DRRS state for gen 8 and above. > Save and restore M2 N2 registers for gen 7 and below > > v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is > only one set of M_N registers > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Some comments below. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.h | 8 ++++ > drivers/gpu/drm/i915/i915_ums.c | 26 +++++++++++ > drivers/gpu/drm/i915/intel_ddi.c | 1 + > drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++++++--- > drivers/gpu/drm/i915/intel_dp.c | 2 + > drivers/gpu/drm/i915/intel_drv.h | 2 + > 6 files changed, 117 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index b82f157..a06551a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -815,6 +815,14 @@ struct i915_suspend_saved_registers { > u32 savePIPEB_DATA_N1; > u32 savePIPEB_LINK_M1; > u32 savePIPEB_LINK_N1; > + u32 savePIPEA_DATA_M2; > + u32 savePIPEA_DATA_N2; > + u32 savePIPEA_LINK_M2; > + u32 savePIPEA_LINK_N2; > + u32 savePIPEB_DATA_M2; > + u32 savePIPEB_DATA_N2; > + u32 savePIPEB_LINK_M2; > + u32 savePIPEB_LINK_N2; > u32 saveMCHBAR_RENDER_STANDBY; > u32 savePCH_PORT_HOTPLUG; > }; > diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c > index 480da59..82fc08f 100644 > --- a/drivers/gpu/drm/i915/i915_ums.c > +++ b/drivers/gpu/drm/i915/i915_ums.c > @@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev) > dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); > dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); > > + /* Saving M2_N2 registers only for Gen7 because DRRS will be > + * used only from Gen7 and for Gen8 & above there is no > + * M2_N2 register. > + */ > + if (INTEL_INFO(dev)->gen == 7) { > + dev_priv->regfile.savePIPEA_DATA_M2 = > + I915_READ(_PIPEA_DATA_M2); > + dev_priv->regfile.savePIPEA_DATA_N2 = > + I915_READ(_PIPEA_DATA_N2); > + dev_priv->regfile.savePIPEA_LINK_M2 = > + I915_READ(_PIPEA_LINK_M2); > + dev_priv->regfile.savePIPEA_LINK_N2 = > + I915_READ(_PIPEA_LINK_N2); > + } > + > dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); > dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); > > @@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev) > I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1); > I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1); > > + if (INTEL_INFO(dev)->gen == 7) { > + I915_WRITE(_PIPEA_DATA_M2, > + dev_priv->regfile.savePIPEA_DATA_M2); > + I915_WRITE(_PIPEA_DATA_N2, > + dev_priv->regfile.savePIPEA_DATA_N2); > + I915_WRITE(_PIPEA_LINK_M2, > + dev_priv->regfile.savePIPEA_LINK_M2); > + I915_WRITE(_PIPEA_LINK_N2, > + dev_priv->regfile.savePIPEA_LINK_N2); > + } These three hunks shouldn't be required since we restore the full mode in the crtc_enable callback. We should _never_ add new register restore code to this since maintaining such code is a major pain. > + > I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL); > I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL); > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 0ad4e96..6784f0b 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > case TRANS_DDI_MODE_SELECT_DP_MST: > pipe_config->has_dp_encoder = true; > intel_dp_get_m_n(intel_crtc, pipe_config); > + intel_dp_get_m2_n2(intel_crtc, pipe_config); > break; > default: > break; > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index cf3ad87..09fc286 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6980,6 +6980,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, > &pipe_config->dp_m_n); > } > > +void intel_dp_get_m2_n2(struct intel_crtc *crtc, > + struct intel_crtc_config *pipe_config) > +{ Imo simpler if you just move the code into intel_dp_get_m_n instead. > + struct drm_device *dev = crtc->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + enum transcoder transcoder = pipe_config->cpu_transcoder; > + > + if (INTEL_INFO(dev)->gen >= 8) { > + intel_cpu_transcoder_get_m_n(crtc, transcoder, > + &pipe_config->dp_m2_n2); We shouldn't fake dp M2/N2 on bdw like this - they just don't exist. > + } else if (INTEL_INFO(dev)->gen > 6) { These registers exists since ilk, so the check here should be gen >= 5. Also please check the situation on vlv, I don't have the latest docs handy for those. > + pipe_config->dp_m2_n2.link_m = > + I915_READ(PIPE_LINK_M2(transcoder)); > + pipe_config->dp_m2_n2.link_n = > + I915_READ(PIPE_LINK_N2(transcoder)); > + pipe_config->dp_m2_n2.gmch_m = > + I915_READ(PIPE_DATA_M2(transcoder)) > + & ~TU_SIZE_MASK; > + pipe_config->dp_m2_n2.gmch_n = > + I915_READ(PIPE_DATA_N2(transcoder)); > + pipe_config->dp_m2_n2.tu = > + ((I915_READ(PIPE_DATA_M2(transcoder)) > + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; > + } > + > +} > + > + > static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config) > { > @@ -9485,6 +9513,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, > pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, > pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, > pipe_config->dp_m_n.tu); > + > + DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", > + pipe_config->has_dp_encoder, > + pipe_config->dp_m2_n2.gmch_m, > + pipe_config->dp_m2_n2.gmch_n, > + pipe_config->dp_m2_n2.link_m, > + pipe_config->dp_m2_n2.link_n, > + pipe_config->dp_m2_n2.tu); > + > DRM_DEBUG_KMS("requested mode:\n"); > drm_mode_debug_printmodeline(&pipe_config->requested_mode); > DRM_DEBUG_KMS("adjusted mode:\n"); > @@ -9867,6 +9904,26 @@ intel_pipe_config_compare(struct drm_device *dev, > return false; \ > } > > +/* This is required for BDW+ where there is only one set of registers for > + * switching between high and low RR. > + * This macro can be used whenever a comparison has to be made between one > + * hw state and multiple sw state variables. > + */ > +#define PIPE_CONF_CHECK_I_I(name1, name2) \ > + if (current_config->name1 != pipe_config->name1) { \ > + DRM_ERROR("mismatch in " #name1 " " \ > + "(expected %i, found %i)\n", \ > + current_config->name1, \ > + pipe_config->name1); \ The DRM_ERROR here is wrong, you should only warn if neither of them match. Also I with the bdw readout for m2/n2 removed this won't work. And I think we need a better name for this macro. What about # define PIPE_CONF_CHECK_I_ALT(name, alternate_name) \ if ((current_config->name != pipe_config->name) && \ (current_config->name != pipe_config->alternate_name) { \ ... error stuff ... \ } > + if (current_config->name2 != pipe_config->name2) { \ > + DRM_ERROR("mismatch in " #name2 " " \ > + "(expected %i, found %i)\n", \ > + current_config->name2, \ > + pipe_config->name2); \ > + return false; \ > + } \ > + } > + > #define PIPE_CONF_CHECK_FLAGS(name, mask) \ > if ((current_config->name ^ pipe_config->name) & (mask)) { \ > DRM_ERROR("mismatch in " #name "(" #mask ") " \ > @@ -9899,11 +9956,26 @@ intel_pipe_config_compare(struct drm_device *dev, > PIPE_CONF_CHECK_I(fdi_m_n.tu); > > PIPE_CONF_CHECK_I(has_dp_encoder); > - PIPE_CONF_CHECK_I(dp_m_n.gmch_m); > - PIPE_CONF_CHECK_I(dp_m_n.gmch_n); > - PIPE_CONF_CHECK_I(dp_m_n.link_m); > - PIPE_CONF_CHECK_I(dp_m_n.link_n); > - PIPE_CONF_CHECK_I(dp_m_n.tu); > + > + if (INTEL_INFO(dev)->gen < 8) { > + PIPE_CONF_CHECK_I(dp_m_n.gmch_m); > + PIPE_CONF_CHECK_I(dp_m_n.gmch_n); > + PIPE_CONF_CHECK_I(dp_m_n.link_m); > + PIPE_CONF_CHECK_I(dp_m_n.link_n); > + PIPE_CONF_CHECK_I(dp_m_n.tu); > + > + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); > + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); > + PIPE_CONF_CHECK_I(dp_m2_n2.link_m); > + PIPE_CONF_CHECK_I(dp_m2_n2.link_n); > + PIPE_CONF_CHECK_I(dp_m2_n2.tu); > + } else { > + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_m, dp_m2_n2.gmch_m); > + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_n, dp_m2_n2.gmch_n); > + PIPE_CONF_CHECK_I_I(dp_m_n.link_m, dp_m2_n2.link_m); > + PIPE_CONF_CHECK_I_I(dp_m_n.link_n, dp_m2_n2.link_n); > + PIPE_CONF_CHECK_I_I(dp_m_n.tu, dp_m2_n2.tu); > + } > > PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); > PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); > @@ -9980,6 +10052,7 @@ intel_pipe_config_compare(struct drm_device *dev, > > #undef PIPE_CONF_CHECK_X > #undef PIPE_CONF_CHECK_I > +#undef PIPE_CONF_CHECK_I_I > #undef PIPE_CONF_CHECK_FLAGS > #undef PIPE_CONF_CHECK_CLOCK_FUZZY > #undef PIPE_CONF_QUIRK > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index bcab4ea..c55f827 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1555,6 +1555,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, > > intel_dp_get_m_n(crtc, pipe_config); > > + intel_dp_get_m2_n2(crtc, pipe_config); > + > if (port == PORT_A) { > if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) > pipe_config->port_clock = 162000; > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 5233a3d..2b4cd30 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -778,6 +778,8 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); > void hsw_disable_pc8(struct drm_i915_private *dev_priv); > void intel_dp_get_m_n(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config); > +void intel_dp_get_m2_n2(struct intel_crtc *crtc, > + struct intel_crtc_config *pipe_config); > int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); > void > ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, > -- > 1.9.3 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 2014-05-21 12:33 ` Daniel Vetter @ 2014-05-22 5:50 ` Vandana Kannan 0 siblings, 0 replies; 10+ messages in thread From: Vandana Kannan @ 2014-05-22 5:50 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On May-21-2014 6:03 PM, Daniel Vetter wrote: > On Wed, May 21, 2014 at 04:40:04PM +0530, Vandana Kannan wrote: >> Adding relevant read out comparison code, in check_crtc_state, for the new >> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n >> values for a DP downclock mode (if available). Suggested by Daniel. >> >> v2: Changed patch title. >> Daniel's review comments incorporated. >> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done >> only when high RR is not in use (This is because alternate m_n register >> programming will be done only when low RR is being used). >> >> v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake. >> Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures >> based on DRRS state for gen 8 and above. >> Save and restore M2 N2 registers for gen 7 and below >> >> v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is >> only one set of M_N registers >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > > Some comments below. > -Daniel Thanks for your inputs. I will resend the patch with all review comments incorporated.. -Vandana >> --- >> drivers/gpu/drm/i915/i915_drv.h | 8 ++++ >> drivers/gpu/drm/i915/i915_ums.c | 26 +++++++++++ >> drivers/gpu/drm/i915/intel_ddi.c | 1 + >> drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++++++--- >> drivers/gpu/drm/i915/intel_dp.c | 2 + >> drivers/gpu/drm/i915/intel_drv.h | 2 + >> 6 files changed, 117 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index b82f157..a06551a 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -815,6 +815,14 @@ struct i915_suspend_saved_registers { >> u32 savePIPEB_DATA_N1; >> u32 savePIPEB_LINK_M1; >> u32 savePIPEB_LINK_N1; >> + u32 savePIPEA_DATA_M2; >> + u32 savePIPEA_DATA_N2; >> + u32 savePIPEA_LINK_M2; >> + u32 savePIPEA_LINK_N2; >> + u32 savePIPEB_DATA_M2; >> + u32 savePIPEB_DATA_N2; >> + u32 savePIPEB_LINK_M2; >> + u32 savePIPEB_LINK_N2; >> u32 saveMCHBAR_RENDER_STANDBY; >> u32 savePCH_PORT_HOTPLUG; >> }; >> diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c >> index 480da59..82fc08f 100644 >> --- a/drivers/gpu/drm/i915/i915_ums.c >> +++ b/drivers/gpu/drm/i915/i915_ums.c >> @@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev) >> dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); >> dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); >> >> + /* Saving M2_N2 registers only for Gen7 because DRRS will be >> + * used only from Gen7 and for Gen8 & above there is no >> + * M2_N2 register. >> + */ >> + if (INTEL_INFO(dev)->gen == 7) { >> + dev_priv->regfile.savePIPEA_DATA_M2 = >> + I915_READ(_PIPEA_DATA_M2); >> + dev_priv->regfile.savePIPEA_DATA_N2 = >> + I915_READ(_PIPEA_DATA_N2); >> + dev_priv->regfile.savePIPEA_LINK_M2 = >> + I915_READ(_PIPEA_LINK_M2); >> + dev_priv->regfile.savePIPEA_LINK_N2 = >> + I915_READ(_PIPEA_LINK_N2); >> + } >> + >> dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); >> dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); >> >> @@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev) >> I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1); >> I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1); >> >> + if (INTEL_INFO(dev)->gen == 7) { >> + I915_WRITE(_PIPEA_DATA_M2, >> + dev_priv->regfile.savePIPEA_DATA_M2); >> + I915_WRITE(_PIPEA_DATA_N2, >> + dev_priv->regfile.savePIPEA_DATA_N2); >> + I915_WRITE(_PIPEA_LINK_M2, >> + dev_priv->regfile.savePIPEA_LINK_M2); >> + I915_WRITE(_PIPEA_LINK_N2, >> + dev_priv->regfile.savePIPEA_LINK_N2); >> + } > > These three hunks shouldn't be required since we restore the full mode in > the crtc_enable callback. We should _never_ add new register restore code > to this since maintaining such code is a major pain. > >> + >> I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL); >> I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL); >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 0ad4e96..6784f0b 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, >> case TRANS_DDI_MODE_SELECT_DP_MST: >> pipe_config->has_dp_encoder = true; >> intel_dp_get_m_n(intel_crtc, pipe_config); >> + intel_dp_get_m2_n2(intel_crtc, pipe_config); >> break; >> default: >> break; >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index cf3ad87..09fc286 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -6980,6 +6980,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, >> &pipe_config->dp_m_n); >> } >> >> +void intel_dp_get_m2_n2(struct intel_crtc *crtc, >> + struct intel_crtc_config *pipe_config) >> +{ > > Imo simpler if you just move the code into intel_dp_get_m_n instead. > >> + struct drm_device *dev = crtc->base.dev; >> + struct drm_i915_private *dev_priv = dev->dev_private; >> + enum transcoder transcoder = pipe_config->cpu_transcoder; >> + >> + if (INTEL_INFO(dev)->gen >= 8) { >> + intel_cpu_transcoder_get_m_n(crtc, transcoder, >> + &pipe_config->dp_m2_n2); > > We shouldn't fake dp M2/N2 on bdw like this - they just don't exist. > >> + } else if (INTEL_INFO(dev)->gen > 6) { > > These registers exists since ilk, so the check here should be gen >= 5. > Also please check the situation on vlv, I don't have the latest docs handy > for those. > >> + pipe_config->dp_m2_n2.link_m = >> + I915_READ(PIPE_LINK_M2(transcoder)); >> + pipe_config->dp_m2_n2.link_n = >> + I915_READ(PIPE_LINK_N2(transcoder)); >> + pipe_config->dp_m2_n2.gmch_m = >> + I915_READ(PIPE_DATA_M2(transcoder)) >> + & ~TU_SIZE_MASK; >> + pipe_config->dp_m2_n2.gmch_n = >> + I915_READ(PIPE_DATA_N2(transcoder)); >> + pipe_config->dp_m2_n2.tu = >> + ((I915_READ(PIPE_DATA_M2(transcoder)) >> + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; >> + } >> + >> +} >> + >> + >> static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, >> struct intel_crtc_config *pipe_config) >> { >> @@ -9485,6 +9513,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, >> pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, >> pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, >> pipe_config->dp_m_n.tu); >> + >> + DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", >> + pipe_config->has_dp_encoder, >> + pipe_config->dp_m2_n2.gmch_m, >> + pipe_config->dp_m2_n2.gmch_n, >> + pipe_config->dp_m2_n2.link_m, >> + pipe_config->dp_m2_n2.link_n, >> + pipe_config->dp_m2_n2.tu); >> + >> DRM_DEBUG_KMS("requested mode:\n"); >> drm_mode_debug_printmodeline(&pipe_config->requested_mode); >> DRM_DEBUG_KMS("adjusted mode:\n"); >> @@ -9867,6 +9904,26 @@ intel_pipe_config_compare(struct drm_device *dev, >> return false; \ >> } >> >> +/* This is required for BDW+ where there is only one set of registers for >> + * switching between high and low RR. >> + * This macro can be used whenever a comparison has to be made between one >> + * hw state and multiple sw state variables. >> + */ >> +#define PIPE_CONF_CHECK_I_I(name1, name2) \ >> + if (current_config->name1 != pipe_config->name1) { \ >> + DRM_ERROR("mismatch in " #name1 " " \ >> + "(expected %i, found %i)\n", \ >> + current_config->name1, \ >> + pipe_config->name1); \ > > The DRM_ERROR here is wrong, you should only warn if neither of them > match. Also I with the bdw readout for m2/n2 removed this won't work. And > I think we need a better name for this macro. What about > > # define PIPE_CONF_CHECK_I_ALT(name, alternate_name) \ > if ((current_config->name != pipe_config->name) && \ > (current_config->name != pipe_config->alternate_name) { \ > ... error stuff ... \ > } > >> + if (current_config->name2 != pipe_config->name2) { \ >> + DRM_ERROR("mismatch in " #name2 " " \ >> + "(expected %i, found %i)\n", \ >> + current_config->name2, \ >> + pipe_config->name2); \ >> + return false; \ >> + } \ >> + } >> + >> #define PIPE_CONF_CHECK_FLAGS(name, mask) \ >> if ((current_config->name ^ pipe_config->name) & (mask)) { \ >> DRM_ERROR("mismatch in " #name "(" #mask ") " \ >> @@ -9899,11 +9956,26 @@ intel_pipe_config_compare(struct drm_device *dev, >> PIPE_CONF_CHECK_I(fdi_m_n.tu); >> >> PIPE_CONF_CHECK_I(has_dp_encoder); >> - PIPE_CONF_CHECK_I(dp_m_n.gmch_m); >> - PIPE_CONF_CHECK_I(dp_m_n.gmch_n); >> - PIPE_CONF_CHECK_I(dp_m_n.link_m); >> - PIPE_CONF_CHECK_I(dp_m_n.link_n); >> - PIPE_CONF_CHECK_I(dp_m_n.tu); >> + >> + if (INTEL_INFO(dev)->gen < 8) { >> + PIPE_CONF_CHECK_I(dp_m_n.gmch_m); >> + PIPE_CONF_CHECK_I(dp_m_n.gmch_n); >> + PIPE_CONF_CHECK_I(dp_m_n.link_m); >> + PIPE_CONF_CHECK_I(dp_m_n.link_n); >> + PIPE_CONF_CHECK_I(dp_m_n.tu); >> + >> + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); >> + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); >> + PIPE_CONF_CHECK_I(dp_m2_n2.link_m); >> + PIPE_CONF_CHECK_I(dp_m2_n2.link_n); >> + PIPE_CONF_CHECK_I(dp_m2_n2.tu); >> + } else { >> + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_m, dp_m2_n2.gmch_m); >> + PIPE_CONF_CHECK_I_I(dp_m_n.gmch_n, dp_m2_n2.gmch_n); >> + PIPE_CONF_CHECK_I_I(dp_m_n.link_m, dp_m2_n2.link_m); >> + PIPE_CONF_CHECK_I_I(dp_m_n.link_n, dp_m2_n2.link_n); >> + PIPE_CONF_CHECK_I_I(dp_m_n.tu, dp_m2_n2.tu); >> + } >> >> PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); >> PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); >> @@ -9980,6 +10052,7 @@ intel_pipe_config_compare(struct drm_device *dev, >> >> #undef PIPE_CONF_CHECK_X >> #undef PIPE_CONF_CHECK_I >> +#undef PIPE_CONF_CHECK_I_I >> #undef PIPE_CONF_CHECK_FLAGS >> #undef PIPE_CONF_CHECK_CLOCK_FUZZY >> #undef PIPE_CONF_QUIRK >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index bcab4ea..c55f827 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -1555,6 +1555,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, >> >> intel_dp_get_m_n(crtc, pipe_config); >> >> + intel_dp_get_m2_n2(crtc, pipe_config); >> + >> if (port == PORT_A) { >> if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) >> pipe_config->port_clock = 162000; >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> index 5233a3d..2b4cd30 100644 >> --- a/drivers/gpu/drm/i915/intel_drv.h >> +++ b/drivers/gpu/drm/i915/intel_drv.h >> @@ -778,6 +778,8 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); >> void hsw_disable_pc8(struct drm_i915_private *dev_priv); >> void intel_dp_get_m_n(struct intel_crtc *crtc, >> struct intel_crtc_config *pipe_config); >> +void intel_dp_get_m2_n2(struct intel_crtc *crtc, >> + struct intel_crtc_config *pipe_config); >> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); >> void >> ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, >> -- >> 1.9.3 >> > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set 2014-05-21 11:10 [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan 2014-05-21 11:10 ` [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 Vandana Kannan @ 2014-06-18 14:17 ` Vandana Kannan 2014-06-18 15:52 ` Daniel Vetter 1 sibling, 1 reply; 10+ messages in thread From: Vandana Kannan @ 2014-06-18 14:17 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter For Gen < 8, set M2_N2 registers on every mode set. This is required to make sure M2_N2 registers are set during boot, resume from sleep for cross- checking the state. The register is set only if DRRS is supported. v2: Patch rebased Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_dp.c | 14 -------------- drivers/gpu/drm/i915/intel_drv.h | 1 + 4 files changed, 36 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0640071..6bf6e00 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table { #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ + to_i915(dev)->drrs.connector-> \ + panel.downclock_mode) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5e8e711..fca5e02 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->config.has_pch_encoder) intel_prepare_shared_dpll(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->active) return; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) else dspcntr |= DISPPLANE_SEL_PIPE_B; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); } +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder transcoder = crtc->config.cpu_transcoder; + + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); +} + static void vlv_update_pll(struct intel_crtc *crtc) { u32 dpll, dpll_md; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 912e9c4..3394615 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, } } -static void -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder transcoder = crtc->config.cpu_transcoder; - - I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); -} - bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ab5962b..cbdb71e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_config *pipe_config); int intel_format_to_fourcc(int format); void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); /* intel_dp.c */ -- 1.9.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set 2014-06-18 14:17 ` [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan @ 2014-06-18 15:52 ` Daniel Vetter 2014-06-23 10:53 ` [PATCH v3 " Vandana Kannan 2014-07-01 5:09 ` [PATCH v2 " Vandana Kannan 0 siblings, 2 replies; 10+ messages in thread From: Daniel Vetter @ 2014-06-18 15:52 UTC (permalink / raw) To: Vandana Kannan; +Cc: Daniel Vetter, intel-gfx On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote: > For Gen < 8, set M2_N2 registers on every mode set. This is required to make > sure M2_N2 registers are set during boot, resume from sleep for cross- > checking the state. The register is set only if DRRS is supported. > > v2: Patch rebased > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/intel_dp.c | 14 -------------- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 4 files changed, 36 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 0640071..6bf6e00 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table { > #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) > #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ > IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) > +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ > + to_i915(dev)->drrs.connector-> \ > + panel.downclock_mode) Didn't spot this the first time around, but HAS_* macros should be chip invariants, so no runtime-dependent pointer chasing and similar things here. Which also means you can't use this in the pipe config checks. Solution for that is to set pipe_config->has_drrs bool when you set the 2nd set of dp m/n values in the pipe_config in intel_dp_compute config. My apologies that this takes so long and that the documentation for our pipe-config infrastructure is so bad (= doesn't exist). I'm slowly working towards the goal of document all the different subsystems in our driver. Thanks, Daniel > > #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 5e8e711..fca5e02 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > if (intel_crtc->config.has_pch_encoder) > intel_prepare_shared_dpll(intel_crtc); > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config.has_dp_encoder) { > intel_dp_set_m_n(intel_crtc); > + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > + intel_dp_set_m2_n2(intel_crtc, > + &intel_crtc->config.dp_m2_n2); > + } > > intel_set_pipe_timings(intel_crtc); > > @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > if (intel_crtc->active) > return; > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config.has_dp_encoder) { > intel_dp_set_m_n(intel_crtc); > + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > + intel_dp_set_m2_n2(intel_crtc, > + &intel_crtc->config.dp_m2_n2); > + } > > intel_set_pipe_timings(intel_crtc); > > @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > /* Set up the display plane register */ > dspcntr = DISPPLANE_GAMMA_ENABLE; > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config.has_dp_encoder) { > intel_dp_set_m_n(intel_crtc); > + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > + intel_dp_set_m2_n2(intel_crtc, > + &intel_crtc->config.dp_m2_n2); > + } > > intel_set_pipe_timings(intel_crtc); > > @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > else > dspcntr |= DISPPLANE_SEL_PIPE_B; > > - if (intel_crtc->config.has_dp_encoder) > + if (intel_crtc->config.has_dp_encoder) { > intel_dp_set_m_n(intel_crtc); > + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > + intel_dp_set_m2_n2(intel_crtc, > + &intel_crtc->config.dp_m2_n2); > + } > > intel_set_pipe_timings(intel_crtc); > > @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) > intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); > } > > +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > +{ > + struct drm_device *dev = crtc->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + enum transcoder transcoder = crtc->config.cpu_transcoder; > + > + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); > + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > +} > + > static void vlv_update_pll(struct intel_crtc *crtc) > { > u32 dpll, dpll_md; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 912e9c4..3394615 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, > } > } > > -static void > -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > -{ > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder transcoder = crtc->config.cpu_transcoder; > - > - I915_WRITE(PIPE_DATA_M2(transcoder), > - TU_SIZE(m_n->tu) | m_n->gmch_m); > - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > -} > - > bool > intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc_config *pipe_config) > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index ab5962b..cbdb71e 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, > struct intel_crtc_config *pipe_config); > int intel_format_to_fourcc(int format); > void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); > +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); > > > /* intel_dp.c */ > -- > 1.9.3 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/2] drm/i915: Set M2_N2 registers during mode set 2014-06-18 15:52 ` Daniel Vetter @ 2014-06-23 10:53 ` Vandana Kannan 2014-07-01 5:09 ` [PATCH v2 " Vandana Kannan 1 sibling, 0 replies; 10+ messages in thread From: Vandana Kannan @ 2014-06-23 10:53 UTC (permalink / raw) To: intel-gfx; +Cc: Daniel Vetter For Gen < 8, set M2_N2 registers on every mode set. This is required to make sure M2_N2 registers are set during boot, resume from sleep for cross- checking the state. The register is set only if DRRS is supported. v2: Patch rebased v3: Daniel's review comments - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to track drrs support Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_dp.c | 16 ++-------------- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5e8e711..2759be5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->config.has_pch_encoder) intel_prepare_shared_dpll(intel_crtc); - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->active) return; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) else dspcntr |= DISPPLANE_SEL_PIPE_B; - if (intel_crtc->config.has_dp_encoder) + if (intel_crtc->config.has_dp_encoder) { intel_dp_set_m_n(intel_crtc); + if (INTEL_INFO(dev)->gen < 8 && intel_crtc->config.has_drrs) + intel_dp_set_m2_n2(intel_crtc, + &intel_crtc->config.dp_m2_n2); + } intel_set_pipe_timings(intel_crtc); @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); } +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder transcoder = crtc->config.cpu_transcoder; + + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); +} + static void vlv_update_pll(struct intel_crtc *crtc) { u32 dpll, dpll_md; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 912e9c4..963ca49 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, } } -static void -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - enum transcoder transcoder = crtc->config.cpu_transcoder; - - I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); -} - bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) @@ -819,6 +805,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, pipe_config->has_pch_encoder = true; pipe_config->has_dp_encoder = true; + pipe_config->has_drrs = false; pipe_config->has_audio = intel_dp->has_audio; if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { @@ -922,6 +909,7 @@ found: if (intel_connector->panel.downclock_mode != NULL && intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { + pipe_config->has_drrs = true; intel_link_compute_m_n(bpp, lane_count, intel_connector->panel.downclock_mode->clock, pipe_config->port_clock, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ab5962b..eed0b74 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -315,6 +315,7 @@ struct intel_crtc_config { /* m2_n2 for eDP downclock */ struct intel_link_m_n dp_m2_n2; + bool has_drrs; /* * Frequence the dpll for the port should run at. Differs from the @@ -811,6 +812,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_config *pipe_config); int intel_format_to_fourcc(int format); void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); /* intel_dp.c */ -- 1.9.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set 2014-06-18 15:52 ` Daniel Vetter 2014-06-23 10:53 ` [PATCH v3 " Vandana Kannan @ 2014-07-01 5:09 ` Vandana Kannan 2014-07-07 8:41 ` Daniel Vetter 1 sibling, 1 reply; 10+ messages in thread From: Vandana Kannan @ 2014-07-01 5:09 UTC (permalink / raw) To: Daniel Vetter; +Cc: Daniel Vetter, intel-gfx On Jun-18-2014 9:22 PM, Daniel Vetter wrote: > On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote: >> For Gen < 8, set M2_N2 registers on every mode set. This is required to make >> sure M2_N2 registers are set during boot, resume from sleep for cross- >> checking the state. The register is set only if DRRS is supported. >> >> v2: Patch rebased >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 3 +++ >> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- >> drivers/gpu/drm/i915/intel_dp.c | 14 -------------- >> drivers/gpu/drm/i915/intel_drv.h | 1 + >> 4 files changed, 36 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 0640071..6bf6e00 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table { >> #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) >> #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ >> IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) >> +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ >> + to_i915(dev)->drrs.connector-> \ >> + panel.downclock_mode) > > Didn't spot this the first time around, but HAS_* macros should be chip > invariants, so no runtime-dependent pointer chasing and similar things > here. Which also means you can't use this in the pipe config checks. > Solution for that is to set pipe_config->has_drrs bool when you set the > 2nd set of dp m/n values in the pipe_config in intel_dp_compute config. > > My apologies that this takes so long and that the documentation for our > pipe-config infrastructure is so bad (= doesn't exist). I'm slowly working > towards the goal of document all the different subsystems in our driver. > > Thanks, Daniel > Hi Daniel, I have addressed the review comments and resent the patches.. http://lists.freedesktop.org/archives/intel-gfx/2014-June/047862.html and http://lists.freedesktop.org/archives/intel-gfx/2014-June/047863.html Please help review the patches.. Thanks, Vandana >> >> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 >> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 5e8e711..fca5e02 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) >> if (intel_crtc->config.has_pch_encoder) >> intel_prepare_shared_dpll(intel_crtc); >> >> - if (intel_crtc->config.has_dp_encoder) >> + if (intel_crtc->config.has_dp_encoder) { >> intel_dp_set_m_n(intel_crtc); >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >> + intel_dp_set_m2_n2(intel_crtc, >> + &intel_crtc->config.dp_m2_n2); >> + } >> >> intel_set_pipe_timings(intel_crtc); >> >> @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) >> if (intel_crtc->active) >> return; >> >> - if (intel_crtc->config.has_dp_encoder) >> + if (intel_crtc->config.has_dp_encoder) { >> intel_dp_set_m_n(intel_crtc); >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >> + intel_dp_set_m2_n2(intel_crtc, >> + &intel_crtc->config.dp_m2_n2); >> + } >> >> intel_set_pipe_timings(intel_crtc); >> >> @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) >> /* Set up the display plane register */ >> dspcntr = DISPPLANE_GAMMA_ENABLE; >> >> - if (intel_crtc->config.has_dp_encoder) >> + if (intel_crtc->config.has_dp_encoder) { >> intel_dp_set_m_n(intel_crtc); >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >> + intel_dp_set_m2_n2(intel_crtc, >> + &intel_crtc->config.dp_m2_n2); >> + } >> >> intel_set_pipe_timings(intel_crtc); >> >> @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) >> else >> dspcntr |= DISPPLANE_SEL_PIPE_B; >> >> - if (intel_crtc->config.has_dp_encoder) >> + if (intel_crtc->config.has_dp_encoder) { >> intel_dp_set_m_n(intel_crtc); >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >> + intel_dp_set_m2_n2(intel_crtc, >> + &intel_crtc->config.dp_m2_n2); >> + } >> >> intel_set_pipe_timings(intel_crtc); >> >> @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) >> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); >> } >> >> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >> +{ >> + struct drm_device *dev = crtc->base.dev; >> + struct drm_i915_private *dev_priv = dev->dev_private; >> + enum transcoder transcoder = crtc->config.cpu_transcoder; >> + >> + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); >> + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); >> + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); >> + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); >> +} >> + >> static void vlv_update_pll(struct intel_crtc *crtc) >> { >> u32 dpll, dpll_md; >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 912e9c4..3394615 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, >> } >> } >> >> -static void >> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >> -{ >> - struct drm_device *dev = crtc->base.dev; >> - struct drm_i915_private *dev_priv = dev->dev_private; >> - enum transcoder transcoder = crtc->config.cpu_transcoder; >> - >> - I915_WRITE(PIPE_DATA_M2(transcoder), >> - TU_SIZE(m_n->tu) | m_n->gmch_m); >> - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); >> - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); >> - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); >> -} >> - >> bool >> intel_dp_compute_config(struct intel_encoder *encoder, >> struct intel_crtc_config *pipe_config) >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> index ab5962b..cbdb71e 100644 >> --- a/drivers/gpu/drm/i915/intel_drv.h >> +++ b/drivers/gpu/drm/i915/intel_drv.h >> @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, >> struct intel_crtc_config *pipe_config); >> int intel_format_to_fourcc(int format); >> void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); >> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); >> >> >> /* intel_dp.c */ >> -- >> 1.9.3 >> > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set 2014-07-01 5:09 ` [PATCH v2 " Vandana Kannan @ 2014-07-07 8:41 ` Daniel Vetter 2014-07-07 9:06 ` Vandana Kannan 0 siblings, 1 reply; 10+ messages in thread From: Daniel Vetter @ 2014-07-07 8:41 UTC (permalink / raw) To: Vandana Kannan; +Cc: Daniel Vetter, intel-gfx On Tue, Jul 01, 2014 at 10:39:52AM +0530, Vandana Kannan wrote: > On Jun-18-2014 9:22 PM, Daniel Vetter wrote: > > On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote: > >> For Gen < 8, set M2_N2 registers on every mode set. This is required to make > >> sure M2_N2 registers are set during boot, resume from sleep for cross- > >> checking the state. The register is set only if DRRS is supported. > >> > >> v2: Patch rebased > >> > >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > >> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 3 +++ > >> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- > >> drivers/gpu/drm/i915/intel_dp.c | 14 -------------- > >> drivers/gpu/drm/i915/intel_drv.h | 1 + > >> 4 files changed, 36 insertions(+), 18 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> index 0640071..6bf6e00 100644 > >> --- a/drivers/gpu/drm/i915/i915_drv.h > >> +++ b/drivers/gpu/drm/i915/i915_drv.h > >> @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table { > >> #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) > >> #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ > >> IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) > >> +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ > >> + to_i915(dev)->drrs.connector-> \ > >> + panel.downclock_mode) > > > > Didn't spot this the first time around, but HAS_* macros should be chip > > invariants, so no runtime-dependent pointer chasing and similar things > > here. Which also means you can't use this in the pipe config checks. > > Solution for that is to set pipe_config->has_drrs bool when you set the > > 2nd set of dp m/n values in the pipe_config in intel_dp_compute config. > > > > My apologies that this takes so long and that the documentation for our > > pipe-config infrastructure is so bad (= doesn't exist). I'm slowly working > > towards the goal of document all the different subsystems in our driver. > > > > Thanks, Daniel > > > Hi Daniel, > > I have addressed the review comments and resent the patches.. > > http://lists.freedesktop.org/archives/intel-gfx/2014-June/047862.html > and > http://lists.freedesktop.org/archives/intel-gfx/2014-June/047863.html > > Please help review the patches.. Can you please start a new thread with both patches? They're splattered a bit badly over the m-l ... Thanks, Daniel > > Thanks, > Vandana > >> > >> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > >> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >> index 5e8e711..fca5e02 100644 > >> --- a/drivers/gpu/drm/i915/intel_display.c > >> +++ b/drivers/gpu/drm/i915/intel_display.c > >> @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > >> if (intel_crtc->config.has_pch_encoder) > >> intel_prepare_shared_dpll(intel_crtc); > >> > >> - if (intel_crtc->config.has_dp_encoder) > >> + if (intel_crtc->config.has_dp_encoder) { > >> intel_dp_set_m_n(intel_crtc); > >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > >> + intel_dp_set_m2_n2(intel_crtc, > >> + &intel_crtc->config.dp_m2_n2); > >> + } > >> > >> intel_set_pipe_timings(intel_crtc); > >> > >> @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > >> if (intel_crtc->active) > >> return; > >> > >> - if (intel_crtc->config.has_dp_encoder) > >> + if (intel_crtc->config.has_dp_encoder) { > >> intel_dp_set_m_n(intel_crtc); > >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > >> + intel_dp_set_m2_n2(intel_crtc, > >> + &intel_crtc->config.dp_m2_n2); > >> + } > >> > >> intel_set_pipe_timings(intel_crtc); > >> > >> @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > >> /* Set up the display plane register */ > >> dspcntr = DISPPLANE_GAMMA_ENABLE; > >> > >> - if (intel_crtc->config.has_dp_encoder) > >> + if (intel_crtc->config.has_dp_encoder) { > >> intel_dp_set_m_n(intel_crtc); > >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > >> + intel_dp_set_m2_n2(intel_crtc, > >> + &intel_crtc->config.dp_m2_n2); > >> + } > >> > >> intel_set_pipe_timings(intel_crtc); > >> > >> @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > >> else > >> dspcntr |= DISPPLANE_SEL_PIPE_B; > >> > >> - if (intel_crtc->config.has_dp_encoder) > >> + if (intel_crtc->config.has_dp_encoder) { > >> intel_dp_set_m_n(intel_crtc); > >> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) > >> + intel_dp_set_m2_n2(intel_crtc, > >> + &intel_crtc->config.dp_m2_n2); > >> + } > >> > >> intel_set_pipe_timings(intel_crtc); > >> > >> @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) > >> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); > >> } > >> > >> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > >> +{ > >> + struct drm_device *dev = crtc->base.dev; > >> + struct drm_i915_private *dev_priv = dev->dev_private; > >> + enum transcoder transcoder = crtc->config.cpu_transcoder; > >> + > >> + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); > >> + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > >> + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > >> + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > >> +} > >> + > >> static void vlv_update_pll(struct intel_crtc *crtc) > >> { > >> u32 dpll, dpll_md; > >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >> index 912e9c4..3394615 100644 > >> --- a/drivers/gpu/drm/i915/intel_dp.c > >> +++ b/drivers/gpu/drm/i915/intel_dp.c > >> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, > >> } > >> } > >> > >> -static void > >> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > >> -{ > >> - struct drm_device *dev = crtc->base.dev; > >> - struct drm_i915_private *dev_priv = dev->dev_private; > >> - enum transcoder transcoder = crtc->config.cpu_transcoder; > >> - > >> - I915_WRITE(PIPE_DATA_M2(transcoder), > >> - TU_SIZE(m_n->tu) | m_n->gmch_m); > >> - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > >> - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > >> - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > >> -} > >> - > >> bool > >> intel_dp_compute_config(struct intel_encoder *encoder, > >> struct intel_crtc_config *pipe_config) > >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >> index ab5962b..cbdb71e 100644 > >> --- a/drivers/gpu/drm/i915/intel_drv.h > >> +++ b/drivers/gpu/drm/i915/intel_drv.h > >> @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, > >> struct intel_crtc_config *pipe_config); > >> int intel_format_to_fourcc(int format); > >> void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); > >> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); > >> > >> > >> /* intel_dp.c */ > >> -- > >> 1.9.3 > >> > > > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set 2014-07-07 8:41 ` Daniel Vetter @ 2014-07-07 9:06 ` Vandana Kannan 0 siblings, 0 replies; 10+ messages in thread From: Vandana Kannan @ 2014-07-07 9:06 UTC (permalink / raw) To: Daniel Vetter; +Cc: Daniel Vetter, intel-gfx On Jul-07-2014 2:11 PM, Daniel Vetter wrote: > On Tue, Jul 01, 2014 at 10:39:52AM +0530, Vandana Kannan wrote: >> On Jun-18-2014 9:22 PM, Daniel Vetter wrote: >>> On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote: >>>> For Gen < 8, set M2_N2 registers on every mode set. This is required to make >>>> sure M2_N2 registers are set during boot, resume from sleep for cross- >>>> checking the state. The register is set only if DRRS is supported. >>>> >>>> v2: Patch rebased >>>> >>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >>>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> >>>> --- >>>> drivers/gpu/drm/i915/i915_drv.h | 3 +++ >>>> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++---- >>>> drivers/gpu/drm/i915/intel_dp.c | 14 -------------- >>>> drivers/gpu/drm/i915/intel_drv.h | 1 + >>>> 4 files changed, 36 insertions(+), 18 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >>>> index 0640071..6bf6e00 100644 >>>> --- a/drivers/gpu/drm/i915/i915_drv.h >>>> +++ b/drivers/gpu/drm/i915/i915_drv.h >>>> @@ -1989,6 +1989,9 @@ struct drm_i915_cmd_table { >>>> #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) >>>> #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ >>>> IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) >>>> +#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \ >>>> + to_i915(dev)->drrs.connector-> \ >>>> + panel.downclock_mode) >>> >>> Didn't spot this the first time around, but HAS_* macros should be chip >>> invariants, so no runtime-dependent pointer chasing and similar things >>> here. Which also means you can't use this in the pipe config checks. >>> Solution for that is to set pipe_config->has_drrs bool when you set the >>> 2nd set of dp m/n values in the pipe_config in intel_dp_compute config. >>> >>> My apologies that this takes so long and that the documentation for our >>> pipe-config infrastructure is so bad (= doesn't exist). I'm slowly working >>> towards the goal of document all the different subsystems in our driver. >>> >>> Thanks, Daniel >>> >> Hi Daniel, >> >> I have addressed the review comments and resent the patches.. >> >> http://lists.freedesktop.org/archives/intel-gfx/2014-June/047862.html >> and >> http://lists.freedesktop.org/archives/intel-gfx/2014-June/047863.html >> >> Please help review the patches.. > > Can you please start a new thread with both patches? They're splattered a > bit badly over the m-l ... > > Thanks, Daniel Sure.. I will resend them now.. - Vandana >> >> Thanks, >> Vandana >>>> >>>> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 >>>> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 >>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >>>> index 5e8e711..fca5e02 100644 >>>> --- a/drivers/gpu/drm/i915/intel_display.c >>>> +++ b/drivers/gpu/drm/i915/intel_display.c >>>> @@ -3987,8 +3987,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) >>>> if (intel_crtc->config.has_pch_encoder) >>>> intel_prepare_shared_dpll(intel_crtc); >>>> >>>> - if (intel_crtc->config.has_dp_encoder) >>>> + if (intel_crtc->config.has_dp_encoder) { >>>> intel_dp_set_m_n(intel_crtc); >>>> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >>>> + intel_dp_set_m2_n2(intel_crtc, >>>> + &intel_crtc->config.dp_m2_n2); >>>> + } >>>> >>>> intel_set_pipe_timings(intel_crtc); >>>> >>>> @@ -4097,8 +4101,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) >>>> if (intel_crtc->active) >>>> return; >>>> >>>> - if (intel_crtc->config.has_dp_encoder) >>>> + if (intel_crtc->config.has_dp_encoder) { >>>> intel_dp_set_m_n(intel_crtc); >>>> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >>>> + intel_dp_set_m2_n2(intel_crtc, >>>> + &intel_crtc->config.dp_m2_n2); >>>> + } >>>> >>>> intel_set_pipe_timings(intel_crtc); >>>> >>>> @@ -4614,8 +4622,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) >>>> /* Set up the display plane register */ >>>> dspcntr = DISPPLANE_GAMMA_ENABLE; >>>> >>>> - if (intel_crtc->config.has_dp_encoder) >>>> + if (intel_crtc->config.has_dp_encoder) { >>>> intel_dp_set_m_n(intel_crtc); >>>> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >>>> + intel_dp_set_m2_n2(intel_crtc, >>>> + &intel_crtc->config.dp_m2_n2); >>>> + } >>>> >>>> intel_set_pipe_timings(intel_crtc); >>>> >>>> @@ -4706,8 +4718,12 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) >>>> else >>>> dspcntr |= DISPPLANE_SEL_PIPE_B; >>>> >>>> - if (intel_crtc->config.has_dp_encoder) >>>> + if (intel_crtc->config.has_dp_encoder) { >>>> intel_dp_set_m_n(intel_crtc); >>>> + if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev)) >>>> + intel_dp_set_m2_n2(intel_crtc, >>>> + &intel_crtc->config.dp_m2_n2); >>>> + } >>>> >>>> intel_set_pipe_timings(intel_crtc); >>>> >>>> @@ -5494,6 +5510,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc) >>>> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); >>>> } >>>> >>>> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >>>> +{ >>>> + struct drm_device *dev = crtc->base.dev; >>>> + struct drm_i915_private *dev_priv = dev->dev_private; >>>> + enum transcoder transcoder = crtc->config.cpu_transcoder; >>>> + >>>> + I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); >>>> + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); >>>> + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); >>>> + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); >>>> +} >>>> + >>>> static void vlv_update_pll(struct intel_crtc *crtc) >>>> { >>>> u32 dpll, dpll_md; >>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >>>> index 912e9c4..3394615 100644 >>>> --- a/drivers/gpu/drm/i915/intel_dp.c >>>> +++ b/drivers/gpu/drm/i915/intel_dp.c >>>> @@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, >>>> } >>>> } >>>> >>>> -static void >>>> -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >>>> -{ >>>> - struct drm_device *dev = crtc->base.dev; >>>> - struct drm_i915_private *dev_priv = dev->dev_private; >>>> - enum transcoder transcoder = crtc->config.cpu_transcoder; >>>> - >>>> - I915_WRITE(PIPE_DATA_M2(transcoder), >>>> - TU_SIZE(m_n->tu) | m_n->gmch_m); >>>> - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); >>>> - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); >>>> - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); >>>> -} >>>> - >>>> bool >>>> intel_dp_compute_config(struct intel_encoder *encoder, >>>> struct intel_crtc_config *pipe_config) >>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >>>> index ab5962b..cbdb71e 100644 >>>> --- a/drivers/gpu/drm/i915/intel_drv.h >>>> +++ b/drivers/gpu/drm/i915/intel_drv.h >>>> @@ -811,6 +811,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, >>>> struct intel_crtc_config *pipe_config); >>>> int intel_format_to_fourcc(int format); >>>> void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); >>>> +void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); >>>> >>>> >>>> /* intel_dp.c */ >>>> -- >>>> 1.9.3 >>>> >>> >> > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2014-07-07 9:07 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-05-21 11:10 [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan 2014-05-21 11:10 ` [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2 Vandana Kannan 2014-05-21 12:33 ` Daniel Vetter 2014-05-22 5:50 ` Vandana Kannan 2014-06-18 14:17 ` [PATCH v2 1/2] drm/i915: Set M2_N2 registers during mode set Vandana Kannan 2014-06-18 15:52 ` Daniel Vetter 2014-06-23 10:53 ` [PATCH v3 " Vandana Kannan 2014-07-01 5:09 ` [PATCH v2 " Vandana Kannan 2014-07-07 8:41 ` Daniel Vetter 2014-07-07 9:06 ` Vandana Kannan
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