* [PATCH] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces
@ 2014-06-24 13:21 Shobhit Kumar
2014-06-24 13:45 ` Ville Syrjälä
0 siblings, 1 reply; 3+ messages in thread
From: Shobhit Kumar @ 2014-06-24 13:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter
For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
during the DSI enable sequence
Causing WARN dump otherwise in dpio_reads
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa77557..2fa7152 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4629,7 +4629,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->active)
return;
- vlv_prepare_pll(intel_crtc);
+ is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+ if (!is_dsi)
+ vlv_prepare_pll(intel_crtc);
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4663,8 +4666,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
-
if (!is_dsi) {
if (IS_CHERRYVIEW(dev))
chv_enable_pll(intel_crtc);
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces
2014-06-24 13:21 [PATCH] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces Shobhit Kumar
@ 2014-06-24 13:45 ` Ville Syrjälä
2014-06-25 6:50 ` [v2] " Shobhit Kumar
0 siblings, 1 reply; 3+ messages in thread
From: Ville Syrjälä @ 2014-06-24 13:45 UTC (permalink / raw)
To: Shobhit Kumar; +Cc: Jani Nikula, Daniel Vetter, intel-gfx
On Tue, Jun 24, 2014 at 06:51:39PM +0530, Shobhit Kumar wrote:
> For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
> during the DSI enable sequence
>
> Causing WARN dump otherwise in dpio_reads
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Yeah, the DPIO power wells might be down when enabling a DSI display so
we shouldn't go poking at DPIO registers.
But please add a !IS_CHERRYVIEW check there also, and then you can add:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks like I need to split up chv_update_pll() in a similar fasion.
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fa77557..2fa7152 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4629,7 +4629,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->active)
> return;
>
> - vlv_prepare_pll(intel_crtc);
> + is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
> +
> + if (!is_dsi)
> + vlv_prepare_pll(intel_crtc);
>
> /* Set up the display plane register */
> dspcntr = DISPPLANE_GAMMA_ENABLE;
> @@ -4663,8 +4666,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
>
> - is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
> -
> if (!is_dsi) {
> if (IS_CHERRYVIEW(dev))
> chv_enable_pll(intel_crtc);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 3+ messages in thread* [v2] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces
2014-06-24 13:45 ` Ville Syrjälä
@ 2014-06-25 6:50 ` Shobhit Kumar
0 siblings, 0 replies; 3+ messages in thread
From: Shobhit Kumar @ 2014-06-25 6:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter
For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
during the DSI enable sequence
Causing WARN dump otherwise in dpio_reads
v2: Add IS_CHERRYVIEW check as suggested by Ville
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa77557..2af7b6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4629,7 +4629,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->active)
return;
- vlv_prepare_pll(intel_crtc);
+ is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+ if (!is_dsi && !IS_CHERRYVIEW(dev))
+ vlv_prepare_pll(intel_crtc);
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4663,8 +4666,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
-
if (!is_dsi) {
if (IS_CHERRYVIEW(dev))
chv_enable_pll(intel_crtc);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2014-06-24 13:21 [PATCH] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces Shobhit Kumar
2014-06-24 13:45 ` Ville Syrjälä
2014-06-25 6:50 ` [v2] " Shobhit Kumar
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