* [PATCH v6a 00/17] GIC and VGIC code refactoring
@ 2014-06-26 5:33 vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 01/17] xen/arm: move io.h as mmio.h to include folder vijay.kilari
` (17 more replies)
0 siblings, 18 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Made changes to existing gic and vgic drivers to make it
generic and added support for GIC v3 hw version.
The complete GICv3 patch series
"[PATCH v5 00/21] xen/arm: Add GICv3 support" is split
into two patch series version v6a and v6.
The 17 patches of v6a series is posted here which contains
refactoring of existing GIC and VGIC drivers to accomodate
GICv3 series (v6)
Tested with ARM64 simulator with multicore core
and booted Dom0 kernel.
Major changes in v6a:
- Changed send_SGI parameters ordering
- coding styles and missing comments
- New patch (17) to check for idle domain before saving GIC context
- Introduced new callback in vgic handler for handling SGI
Major changes in v5:
- Introduced new patch for checking platform capability for gicv3
- Introduced more patches for vgic clean up and code movement
- Added synchronization barriers and clean up in GICv3 driver
- Rebase on top of master branch +
remotes/origin/no_maintenance_interrupts-v8 patch set
- Code base available in github
git clone https://github.com/vijaykilari/Xen-GICv3.git
- Fixed comments and coding style
Major changes in v4:
- Changed io handlers to take mmio address and size as
parameters
- ioremap is used instead of fixmap to map GICv2 address
space. Removed /4 in GICv2 register definitions
- vGIC driver now uses register size to calculate IRQ rank
- GICv2 LR register definitions are declared locally in GICv2 driver
- GICR & GICD common register handling in vgic-v3 driver are segregated
in one common function
- irq_hw_controller definition is managed in GICv2 and GICv3 drivers
- Made irq_ops const
- GIC DT node is updated in respective drivers
- Comments and coding style fixes
- Rebased on remotes/origin/no_maintenance_interrupts-v8 + Julien's
patch set
Major changes in v3:
- Moved io.h from xen/arch/arm to xen/include/asm-arm
and renamed as mmio.h
- Made all the io handlers as domain specific and removed
check handlers. Instead address and size are passed
- Cleaned up sgi handling functions in V2 gic driver and
made generic
- Removed unused parameters in do_sgi call
- VGIC driver is chosen based on GIC driver initialized
- Implemented SGI handling for GICv3 to boot multicore
- Missing coding style fixes
- Rebased to remotes/origin/no_maintenance_interrupts-v6
branch of Stephano's unstable tree
Major Changes in v2:
- Added per domain io handler
- Use device api to initialize gic driver
- Avoid use of void pointer to access common data
- Moved vgic address information data from domain.h
- Coding style
Vijaya Kumar K (17):
xen/arm: move io.h as mmio.h to include folder
xen/arm: make mmio handlers domain specific
xen/arm: make sgi handling generic
xen/arm: remove unused parameter in do_sgi call
xen/arm: use ioremap to map gic-v2 registers
xen/arm: segregate and split GIC low level functionality
arm/xen: move GIC context data structure to gic driver
xen/arm: use device api to detect GIC version
xen/arm: switch to dynamic allocation of vgic rank
xen/arm: prefix byte_read and byte_write functions with vgic
xen/arm: move vgic defines to vgic header file
xen/arm: move and rename is_vcpu_running function to sched.h
xen/arm: move pending_irq structure to vgic header file
xen/arm: calculate vgic irq rank based on register size
xen/arm: Remove REG macro in vgic driver
xen/arm: split vgic driver into generic and vgic-v2 driver
xen/arm: Restrict saving of gic register for idle domain
xen/arch/arm/Makefile | 4 +-
xen/arch/arm/domain.c | 5 +
xen/arch/arm/domain_build.c | 2 +-
xen/arch/arm/gic-v2.c | 692 +++++++++++++++++++++++++
xen/arch/arm/gic.c | 537 ++++---------------
xen/arch/arm/io.c | 59 ++-
xen/arch/arm/irq.c | 1 +
xen/arch/arm/time.c | 1 +
xen/arch/arm/traps.c | 2 +-
xen/arch/arm/vgic-v2.c | 507 ++++++++++++++++++
xen/arch/arm/vgic.c | 570 +++-----------------
xen/arch/arm/vpsci.c | 1 +
xen/arch/arm/vtimer.c | 1 +
xen/arch/arm/vuart.c | 28 +-
xen/include/asm-arm/device.h | 1 +
xen/include/asm-arm/domain.h | 77 +--
xen/include/asm-arm/gic.h | 250 ++++++---
xen/{arch/arm/io.h => include/asm-arm/mmio.h} | 30 +-
xen/include/asm-arm/processor.h | 8 +
xen/include/asm-arm/vgic.h | 179 +++++++
xen/include/xen/sched.h | 16 +
21 files changed, 1835 insertions(+), 1136 deletions(-)
create mode 100644 xen/arch/arm/gic-v2.c
create mode 100644 xen/arch/arm/vgic-v2.c
rename xen/{arch/arm/io.h => include/asm-arm/mmio.h} (66%)
create mode 100644 xen/include/asm-arm/vgic.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v6a 01/17] xen/arm: move io.h as mmio.h to include folder
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 02/17] xen/arm: make mmio handlers domain specific vijay.kilari
` (16 subsequent siblings)
17 siblings, 0 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
io.h is local to arch/arm folder. move this file as mmio.h
file to include/asm-arm folder as it might be
required for inclusion in other header files in future.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/io.c | 3 +--
xen/arch/arm/traps.c | 2 +-
xen/arch/arm/vgic.c | 2 +-
xen/arch/arm/vuart.c | 2 +-
xen/{arch/arm/io.h => include/asm-arm/mmio.h} | 8 ++++----
5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
index a6db00b..ada1918 100644
--- a/xen/arch/arm/io.c
+++ b/xen/arch/arm/io.c
@@ -19,8 +19,7 @@
#include <xen/config.h>
#include <xen/lib.h>
#include <asm/current.h>
-
-#include "io.h"
+#include <asm/mmio.h>
static const struct mmio_handler *const mmio_handlers[] =
{
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 7f77c56..7c8b2dd 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -36,9 +36,9 @@
#include <asm/regs.h>
#include <asm/cpregs.h>
#include <asm/psci.h>
+#include <asm/mmio.h>
#include "decode.h"
-#include "io.h"
#include "vtimer.h"
#include <asm/gic.h>
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 757707e..155aed8 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,7 +27,7 @@
#include <asm/current.h>
-#include "io.h"
+#include <asm/mmio.h>
#include <asm/gic.h>
#define REG(n) (n/4)
diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
index c02a8a9..953cd46 100644
--- a/xen/arch/arm/vuart.c
+++ b/xen/arch/arm/vuart.c
@@ -38,9 +38,9 @@
#include <xen/errno.h>
#include <xen/ctype.h>
#include <xen/serial.h>
+#include <asm/mmio.h>
#include "vuart.h"
-#include "io.h"
#define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
diff --git a/xen/arch/arm/io.h b/xen/include/asm-arm/mmio.h
similarity index 91%
rename from xen/arch/arm/io.h
rename to xen/include/asm-arm/mmio.h
index 8d252c0..5870985 100644
--- a/xen/arch/arm/io.h
+++ b/xen/include/asm-arm/mmio.h
@@ -1,5 +1,5 @@
/*
- * xen/arch/arm/io.h
+ * xen/include/asm-arm/mmio.h
*
* ARM I/O handlers
*
@@ -16,8 +16,8 @@
* GNU General Public License for more details.
*/
-#ifndef __ARCH_ARM_IO_H__
-#define __ARCH_ARM_IO_H__
+#ifndef __ASM_ARM_MMIO_H__
+#define __ASM_ARM_MMIO_H__
#include <xen/lib.h>
#include <asm/processor.h>
@@ -45,7 +45,7 @@ extern const struct mmio_handler vuart_mmio_handler;
extern int handle_mmio(mmio_info_t *info);
-#endif
+#endif /* __ASM_ARM_MMIO_H__ */
/*
* Local variables:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 02/17] xen/arm: make mmio handlers domain specific
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 01/17] xen/arm: move io.h as mmio.h to include folder vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 03/17] xen/arm: make sgi handling generic vijay.kilari
` (15 subsequent siblings)
17 siblings, 0 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
register mmio handlers at runtime and make mmio handlers
domain specific and check handlers are removed.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/domain.c | 3 +++
xen/arch/arm/io.c | 56 +++++++++++++++++++++++++++++++++---------
xen/arch/arm/vgic.c | 28 +++++++++++----------
xen/arch/arm/vuart.c | 26 +++++++++-----------
xen/include/asm-arm/domain.h | 2 ++
xen/include/asm-arm/mmio.h | 22 ++++++++++++++---
6 files changed, 94 insertions(+), 43 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index e20ba0b..01d2fd9 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -512,6 +512,9 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags)
share_xen_page_with_guest(
virt_to_page(d->shared_info), d, XENSHARE_writable);
+ if ( (rc = domain_io_init(d)) != 0 )
+ goto fail;
+
if ( (rc = p2m_alloc_table(d)) != 0 )
goto fail;
diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
index ada1918..8e55d49 100644
--- a/xen/arch/arm/io.c
+++ b/xen/arch/arm/io.c
@@ -1,5 +1,5 @@
/*
- * xen/arch/arm/io.h
+ * xen/arch/arm/io.c
*
* ARM I/O handlers
*
@@ -18,29 +18,61 @@
#include <xen/config.h>
#include <xen/lib.h>
+#include <xen/spinlock.h>
+#include <xen/sched.h>
#include <asm/current.h>
#include <asm/mmio.h>
-static const struct mmio_handler *const mmio_handlers[] =
-{
- &vgic_distr_mmio_handler,
- &vuart_mmio_handler,
-};
-#define MMIO_HANDLER_NR ARRAY_SIZE(mmio_handlers)
-
int handle_mmio(mmio_info_t *info)
{
struct vcpu *v = current;
int i;
+ const struct mmio_handler *mmio_handler;
+ const struct io_handler *io_handlers = &v->domain->arch.io_handlers;
- for ( i = 0; i < MMIO_HANDLER_NR; i++ )
- if ( mmio_handlers[i]->check_handler(v, info->gpa) )
+ for ( i = 0; i < io_handlers->num_entries; i++ )
+ {
+ mmio_handler = &io_handlers->mmio_handlers[i];
+
+ if ( (info->gpa >= mmio_handler->addr) &&
+ (info->gpa < (mmio_handler->addr + mmio_handler->size)) )
+ {
return info->dabt.write ?
- mmio_handlers[i]->write_handler(v, info) :
- mmio_handlers[i]->read_handler(v, info);
+ mmio_handler->mmio_handler_ops->write_handler(v, info) :
+ mmio_handler->mmio_handler_ops->read_handler(v, info);
+ }
+ }
return 0;
}
+
+void register_mmio_handler(struct domain *d,
+ const struct mmio_handler_ops *handle,
+ paddr_t addr, paddr_t size)
+{
+ struct io_handler *handler = &d->arch.io_handlers;
+
+ BUG_ON(handler->num_entries >= MAX_IO_HANDLER);
+
+ spin_lock(&handler->lock);
+
+ handler->mmio_handlers[handler->num_entries].mmio_handler_ops = handle;
+ handler->mmio_handlers[handler->num_entries].addr = addr;
+ handler->mmio_handlers[handler->num_entries].size = size;
+ dsb(ish);
+ handler->num_entries++;
+
+ spin_unlock(&handler->lock);
+}
+
+int domain_io_init(struct domain *d)
+{
+ spin_lock_init(&d->arch.io_handlers.lock);
+ d->arch.io_handlers.num_entries = 0;
+
+ return 0;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 155aed8..074d2f3 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -35,6 +35,9 @@
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
+static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
+static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
+
/*
* Rank containing GICD_<FOO><n> for GICD_<FOO> with
* <b>-bits-per-interrupt
@@ -78,6 +81,11 @@ static struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
return vgic_rank_offset(v, 8, irq >> 2);
}
+static const struct mmio_handler_ops vgic_distr_mmio_handler = {
+ .read_handler = vgic_distr_mmio_read,
+ .write_handler = vgic_distr_mmio_write,
+};
+
int domain_vgic_init(struct domain *d)
{
int i;
@@ -112,6 +120,13 @@ int domain_vgic_init(struct domain *d)
}
for (i=0; i<DOMAIN_NR_RANKS(d); i++)
spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
+
+ /*
+ * We rely on gicv_setup() to initialize dbase(vGIC distributor base)
+ */
+ register_mmio_handler(d, &vgic_distr_mmio_handler,
+ d->arch.vgic.dbase, PAGE_SIZE);
+
return 0;
}
@@ -684,19 +699,6 @@ write_ignore:
return 1;
}
-static int vgic_distr_mmio_check(struct vcpu *v, paddr_t addr)
-{
- struct domain *d = v->domain;
-
- return (addr >= (d->arch.vgic.dbase)) && (addr < (d->arch.vgic.dbase + PAGE_SIZE));
-}
-
-const struct mmio_handler vgic_distr_mmio_handler = {
- .check_handler = vgic_distr_mmio_check,
- .read_handler = vgic_distr_mmio_read,
- .write_handler = vgic_distr_mmio_write,
-};
-
struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
{
struct pending_irq *n;
diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
index 953cd46..e327c15 100644
--- a/xen/arch/arm/vuart.c
+++ b/xen/arch/arm/vuart.c
@@ -44,6 +44,14 @@
#define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
+static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info);
+static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info);
+
+static const struct mmio_handler_ops vuart_mmio_handler = {
+ .read_handler = vuart_mmio_read,
+ .write_handler = vuart_mmio_write,
+};
+
int domain_vuart_init(struct domain *d)
{
ASSERT( is_hardware_domain(d) );
@@ -59,6 +67,10 @@ int domain_vuart_init(struct domain *d)
if ( !d->arch.vuart.buf )
return -ENOMEM;
+ register_mmio_handler(d, &vuart_mmio_handler,
+ d->arch.vuart.info->base_addr,
+ d->arch.vuart.info->size);
+
return 0;
}
@@ -92,14 +104,6 @@ static void vuart_print_char(struct vcpu *v, char c)
spin_unlock(&uart->lock);
}
-static int vuart_mmio_check(struct vcpu *v, paddr_t addr)
-{
- const struct vuart_info *info = v->domain->arch.vuart.info;
-
- return (domain_has_vuart(v->domain) && addr >= info->base_addr &&
- addr <= (info->base_addr + info->size));
-}
-
static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info)
{
struct domain *d = v->domain;
@@ -133,12 +137,6 @@ static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info)
return 1;
}
-const struct mmio_handler vuart_mmio_handler = {
- .check_handler = vuart_mmio_check,
- .read_handler = vuart_mmio_read,
- .write_handler = vuart_mmio_write,
-};
-
/*
* Local variables:
* mode: C
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 2cb6837..046362c 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -7,6 +7,7 @@
#include <asm/page.h>
#include <asm/p2m.h>
#include <asm/vfp.h>
+#include <asm/mmio.h>
#include <public/hvm/params.h>
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
@@ -119,6 +120,7 @@ struct arch_domain
struct hvm_domain hvm_domain;
xen_pfn_t *grant_table_gpfn;
+ struct io_handler io_handlers;
/* Continuable domain_relinquish_resources(). */
enum {
RELMEM_not_started,
diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h
index 5870985..0160f09 100644
--- a/xen/include/asm-arm/mmio.h
+++ b/xen/include/asm-arm/mmio.h
@@ -23,6 +23,8 @@
#include <asm/processor.h>
#include <asm/regs.h>
+#define MAX_IO_HANDLER 16
+
typedef struct
{
struct hsr_dabt dabt;
@@ -34,16 +36,28 @@ typedef int (*mmio_read_t)(struct vcpu *v, mmio_info_t *info);
typedef int (*mmio_write_t)(struct vcpu *v, mmio_info_t *info);
typedef int (*mmio_check_t)(struct vcpu *v, paddr_t addr);
-struct mmio_handler {
- mmio_check_t check_handler;
+struct mmio_handler_ops {
mmio_read_t read_handler;
mmio_write_t write_handler;
};
-extern const struct mmio_handler vgic_distr_mmio_handler;
-extern const struct mmio_handler vuart_mmio_handler;
+struct mmio_handler {
+ paddr_t addr;
+ paddr_t size;
+ const struct mmio_handler_ops *mmio_handler_ops;
+};
+
+struct io_handler {
+ int num_entries;
+ spinlock_t lock;
+ struct mmio_handler mmio_handlers[MAX_IO_HANDLER];
+};
extern int handle_mmio(mmio_info_t *info);
+void register_mmio_handler(struct domain *d,
+ const struct mmio_handler_ops *handle,
+ paddr_t addr, paddr_t size);
+int domain_io_init(struct domain *d);
#endif /* __ASM_ARM_MMIO_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 03/17] xen/arm: make sgi handling generic
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 01/17] xen/arm: move io.h as mmio.h to include folder vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 02/17] xen/arm: make mmio handlers domain specific vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 11:47 ` Julien Grall
2014-06-27 12:42 ` Ian Campbell
2014-06-26 5:33 ` [PATCH v6a 04/17] xen/arm: remove unused parameter in do_sgi call vijay.kilari
` (14 subsequent siblings)
17 siblings, 2 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
move all the hw specific sgi handling functionality
to one function and use it.
changes in v6a: change send_SGI() parameter order
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/gic.c | 37 ++++++++++++++++++++++++++++---------
xen/include/asm-arm/gic.h | 8 ++++++++
2 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 4d2a92d..df7462d 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -483,21 +483,40 @@ void __init gic_init(void)
spin_unlock(&gic.lock);
}
-void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
+static void send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
+ const cpumask_t *cpu_mask)
{
unsigned int mask = 0;
+
+ switch ( irqmode )
+ {
+ case SGI_TARGET_OTHERS:
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
+ break;
+ case SGI_TARGET_SELF:
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
+ break;
+ case SGI_TARGET_LIST:
+ mask = gic_cpu_mask(cpu_mask);
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi;
+ break;
+ default:
+ BUG();
+ }
+}
+
+void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
+{
cpumask_t online_mask;
ASSERT(sgi < 16); /* There are only 16 SGIs */
cpumask_and(&online_mask, cpumask, &cpu_online_map);
- mask = gic_cpu_mask(&online_mask);
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST
- | (mask<<GICD_SGI_TARGET_SHIFT)
- | sgi;
+ send_SGI(sgi, SGI_TARGET_LIST, &online_mask);
}
void send_SGI_one(unsigned int cpu, enum gic_sgi sgi)
@@ -512,18 +531,18 @@ void send_SGI_self(enum gic_sgi sgi)
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF
- | sgi;
+ send_SGI(sgi, SGI_TARGET_SELF, cpumask_of(smp_processor_id()));
}
void send_SGI_allbutself(enum gic_sgi sgi)
{
+ cpumask_t all_others_mask;
ASSERT(sgi < 16); /* There are only 16 SGIs */
+ cpumask_andnot(&all_others_mask, &cpu_possible_map, cpumask_of(smp_processor_id()));
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS
- | sgi;
+ send_SGI(sgi, SGI_TARGET_OTHERS, &all_others_mask);
}
void smp_send_state_dump(unsigned int cpu)
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 8e37ccf..c7b7368 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -210,6 +210,14 @@ enum gic_sgi {
GIC_SGI_DUMP_STATE = 1,
GIC_SGI_CALL_FUNCTION = 2,
};
+
+/* SGI irq mode types */
+enum gic_sgi_mode {
+ SGI_TARGET_LIST,
+ SGI_TARGET_OTHERS,
+ SGI_TARGET_SELF,
+};
+
extern void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi);
extern void send_SGI_one(unsigned int cpu, enum gic_sgi sgi);
extern void send_SGI_self(enum gic_sgi sgi);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 04/17] xen/arm: remove unused parameter in do_sgi call
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (2 preceding siblings ...)
2014-06-26 5:33 ` [PATCH v6a 03/17] xen/arm: make sgi handling generic vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
` (13 subsequent siblings)
17 siblings, 0 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
othercpu parameter in do_sgi is unused
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/gic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index df7462d..aabb2d1 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -848,7 +848,7 @@ void gic_inject(void)
}
-static void do_sgi(struct cpu_user_regs *regs, int othercpu, enum gic_sgi sgi)
+static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
GICC[GICC_EOIR] = sgi;
@@ -892,8 +892,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
}
else if (unlikely(irq < 16))
{
- unsigned int cpu = (intack & GICC_IA_CPU_MASK) >> GICC_IA_CPU_SHIFT;
- do_sgi(regs, cpu, irq);
+ do_sgi(regs, irq);
}
else
{
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (3 preceding siblings ...)
2014-06-26 5:33 ` [PATCH v6a 04/17] xen/arm: remove unused parameter in do_sgi call vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 12:07 ` Julien Grall
2014-06-26 5:33 ` [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality vijay.kilari
` (12 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic-v2 driver uses fixmap to map the registers.
Instead use ioremap to access mmio registers.
With this patch, gic-v2 register definitions are updated
to use absolute offset address instead of dividing the
register offset by 4.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/gic.c | 177 ++++++++++++++++++++++++++-------------------
xen/arch/arm/vgic.c | 15 ++--
xen/include/asm-arm/gic.h | 104 +++++++++++++-------------
3 files changed, 160 insertions(+), 136 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index aabb2d1..5aebbf5 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -31,20 +31,23 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
-
+#include <asm/io.h>
#include <asm/gic.h>
-/* Access to the GIC Distributor registers through the fixmap */
-#define GICD ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICD))
-#define GICC ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICC1))
-#define GICH ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICH))
+#define GICD (gic.map_dbase)
+#define GICC (gic.map_cbase)
+#define GICH (gic.map_hbase)
+
static void gic_restore_pending_irqs(struct vcpu *v);
/* Global state */
static struct {
paddr_t dbase; /* Address of distributor registers */
+ void __iomem * map_dbase; /* IO mapped Address of distributor registers */
paddr_t cbase; /* Address of CPU interface registers */
+ void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
paddr_t hbase; /* Address of virtual interface registers */
+ void __iomem * map_hbase; /* IO Address of virtual interface registers */
paddr_t vbase; /* Address of virtual cpu interface registers */
unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
unsigned int maintenance_irq; /* IRQ maintenance */
@@ -101,12 +104,12 @@ void gic_save_state(struct vcpu *v)
* accessed simultaneously by another pCPU.
*/
for ( i=0; i<nr_lrs; i++)
- v->arch.gic_lr[i] = GICH[GICH_LR + i];
+ v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
v->arch.lr_mask = this_cpu(lr_mask);
- v->arch.gic_apr = GICH[GICH_APR];
- v->arch.gic_vmcr = GICH[GICH_VMCR];
+ v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
/* Disable until next VCPU scheduled */
- GICH[GICH_HCR] = 0;
+ writel_relaxed(0, GICH + GICH_HCR);
isb();
}
@@ -120,10 +123,10 @@ void gic_restore_state(struct vcpu *v)
this_cpu(lr_mask) = v->arch.lr_mask;
for ( i=0; i<nr_lrs; i++)
- GICH[GICH_LR + i] = v->arch.gic_lr[i];
- GICH[GICH_APR] = v->arch.gic_apr;
- GICH[GICH_VMCR] = v->arch.gic_vmcr;
- GICH[GICH_HCR] = GICH_HCR_EN;
+ writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+ writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
isb();
gic_restore_pending_irqs(v);
@@ -137,10 +140,10 @@ static void gic_irq_enable(struct irq_desc *desc)
ASSERT(spin_is_locked(&desc->lock));
spin_lock_irqsave(&gic.lock, flags);
+ /* Enable routing */
desc->status &= ~IRQ_DISABLED;
dsb(sy);
- /* Enable routing */
- GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32));
+ writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
spin_unlock_irqrestore(&gic.lock, flags);
}
@@ -153,7 +156,7 @@ static void gic_irq_disable(struct irq_desc *desc)
spin_lock_irqsave(&gic.lock, flags);
/* Disable routing */
- GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32));
+ writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
desc->status |= IRQ_DISABLED;
spin_unlock_irqrestore(&gic.lock, flags);
}
@@ -179,16 +182,16 @@ static void gic_host_irq_end(struct irq_desc *desc)
{
int irq = desc->irq;
/* Lower the priority */
- GICC[GICC_EOIR] = irq;
+ writel_relaxed(irq, GICC + GICC_EOIR);
/* Deactivate */
- GICC[GICC_DIR] = irq;
+ writel_relaxed(irq, GICC + GICC_DIR);
}
static void gic_guest_irq_end(struct irq_desc *desc)
{
int irq = desc->irq;
/* Lower the priority of the IRQ */
- GICC[GICC_EOIR] = irq;
+ writel_relaxed(irq, GICC + GICC_EOIR);
/* Deactivation happens in maintenance interrupt / via GICV */
}
@@ -229,8 +232,7 @@ static void gic_set_irq_properties(struct irq_desc *desc,
const cpumask_t *cpu_mask,
unsigned int priority)
{
- volatile unsigned char *bytereg;
- uint32_t cfg, edgebit;
+ uint32_t cfg, edgebit, itarget, ipriority;
unsigned int mask;
unsigned int irq = desc->irq;
unsigned int type = desc->arch.type;
@@ -243,21 +245,28 @@ static void gic_set_irq_properties(struct irq_desc *desc,
mask = gic_cpu_mask(cpu_mask);
/* Set edge / level */
- cfg = GICD[GICD_ICFGR + irq / 16];
+ cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
edgebit = 2u << (2 * (irq % 16));
if ( type & DT_IRQ_TYPE_LEVEL_MASK )
cfg &= ~edgebit;
else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
cfg |= edgebit;
- GICD[GICD_ICFGR + irq / 16] = cfg;
+ writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
/* Set target CPU mask (RAZ/WI on uniprocessor) */
- bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
- bytereg[irq] = mask;
-
+ itarget = readl_relaxed(GICD + GICD_ITARGETSR + (irq / 4) * 4);
+ /* Clear mask */
+ itarget &= ~(0xffu << (8 * (irq % 4)));
+ /* Set mask */
+ itarget |= mask << (8 * (irq % 4));
+ writel_relaxed(itarget, GICD + GICD_ITARGETSR + (irq / 4) * 4);
+
+ ipriority = readl_relaxed(GICD + GICD_IPRIORITYR + (irq / 4) * 4);
+ /* Clear priority */
+ ipriority &= ~(0xffu << (8 * (irq % 4)));
/* Set priority */
- bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR);
- bytereg[irq] = priority;
+ ipriority |= priority << (8 * (irq % 4));
+ writel_relaxed(ipriority, GICD + GICD_IPRIORITYR + (irq / 4) * 4);
spin_unlock(&gic.lock);
}
@@ -303,87 +312,94 @@ static void __init gic_dist_init(void)
uint32_t cpumask;
int i;
- cpumask = GICD[GICD_ITARGETSR] & 0xff;
+ cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
/* Disable the distributor */
- GICD[GICD_CTLR] = 0;
+ writel_relaxed(0, GICD + GICD_CTLR);
- type = GICD[GICD_TYPER];
+ type = readl_relaxed(GICD + GICD_TYPER);
gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
(type & GICD_TYPE_SEC) ? ", secure" : "",
- GICD[GICD_IIDR]);
+ readl_relaxed(GICD + GICD_IIDR));
/* Default all global IRQs to level, active low */
for ( i = 32; i < gic.lines; i += 16 )
- GICD[GICD_ICFGR + i / 16] = 0x0;
+ writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
/* Route all global IRQs to this CPU */
for ( i = 32; i < gic.lines; i += 4 )
- GICD[GICD_ITARGETSR + i / 4] = cpumask;
+ writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
/* Default priority for global interrupts */
for ( i = 32; i < gic.lines; i += 4 )
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
+ writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Disable all global interrupts */
for ( i = 32; i < gic.lines; i += 32 )
- GICD[GICD_ICENABLER + i / 32] = (uint32_t)~0ul;
+ writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
/* Turn on the distributor */
- GICD[GICD_CTLR] = GICD_CTL_ENABLE;
+ writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
}
static void __cpuinit gic_cpu_init(void)
{
int i;
- this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff;
+ this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
/* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
* even though they are controlled with GICD registers, they must
* be set up here with the other per-cpu state. */
- GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
- GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
+ writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
+ writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
+
/* Set SGI priorities */
for (i = 0; i < 16; i += 4)
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IPI<<24 | GIC_PRI_IPI<<16 | GIC_PRI_IPI<<8 | GIC_PRI_IPI;
+ writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
+ GIC_PRI_IPI << 8 | GIC_PRI_IPI,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Set PPI priorities */
for (i = 16; i < 32; i += 4)
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
+ writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Local settings: interface controller */
- GICC[GICC_PMR] = 0xff; /* Don't mask by priority */
- GICC[GICC_BPR] = 0; /* Finest granularity of priority */
- GICC[GICC_CTLR] = GICC_CTL_ENABLE|GICC_CTL_EOI; /* Turn on delivery */
+ /* Don't mask by priority */
+ writel_relaxed(0xff, GICC + GICC_PMR);
+ /* Finest granularity of priority */
+ writel_relaxed(0x0, GICC + GICC_BPR);
+ /* Turn on delivery */
+ writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
}
static void gic_cpu_disable(void)
{
- GICC[GICC_CTLR] = 0;
+ writel_relaxed(0x0, GICC + GICC_CTLR);
}
static void __cpuinit gic_hyp_init(void)
{
uint32_t vtr;
- vtr = GICH[GICH_VTR];
+ vtr = readl_relaxed(GICH + GICH_VTR);
nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
- GICH[GICH_MISR] = GICH_MISR_EOI;
+ writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
this_cpu(lr_mask) = 0ULL;
}
static void __cpuinit gic_hyp_disable(void)
{
- GICH[GICH_HCR] = 0;
+ writel_relaxed(0, GICH + GICH_HCR);
}
int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
@@ -462,15 +478,21 @@ void __init gic_init(void)
(gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
panic("GIC interfaces not page aligned");
- set_fixmap(FIXMAP_GICD, gic.dbase >> PAGE_SHIFT, DEV_SHARED);
- BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
- FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
- set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
+ gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
+ if ( !gic.map_dbase )
+ panic("Failed to ioremap for GIC distributor\n");
+
if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
+ gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
else
- set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
- set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
+ gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
+
+ if ( !gic.map_cbase )
+ panic("Failed to ioremap for GIC CPU interface\n");
+
+ gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
+ if ( !gic.map_hbase )
+ panic("Failed to ioremap for GIC Virtual interface\n");
/* Global settings: interrupt distributor */
spin_lock_init(&gic.lock);
@@ -491,15 +513,16 @@ static void send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
switch ( irqmode )
{
case SGI_TARGET_OTHERS:
- GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
+ writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
break;
case SGI_TARGET_SELF:
- GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
+ writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
break;
case SGI_TARGET_LIST:
mask = gic_cpu_mask(cpu_mask);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
- (mask << GICD_SGI_TARGET_SHIFT) | sgi;
+ writel_relaxed(GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi,
+ GICD + GICD_SGIR);
break;
default:
BUG();
@@ -585,7 +608,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p,
if ( p->desc != NULL )
lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
- GICH[GICH_LR + lr] = lr_val;
+ writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
@@ -670,7 +693,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
ASSERT(spin_is_locked(&v->arch.vgic.lock));
ASSERT(!local_irq_is_enabled());
- lr = GICH[GICH_LR + i];
+ lr = readl_relaxed(GICH + GICH_LR + i * 4);
irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
p = irq_to_pending(v, irq);
if ( lr & GICH_LR_ACTIVE )
@@ -680,7 +703,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
{
if ( p->desc == NULL )
- GICH[GICH_LR + i] = lr | GICH_LR_PENDING;
+ writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
else
gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
@@ -693,7 +716,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
irq, v->domain->domain_id, v->vcpu_id, i);
#endif
} else {
- GICH[GICH_LR + i] = 0;
+ writel_relaxed(0, GICH + GICH_LR + i * 4);
clear_bit(i, &this_cpu(lr_mask));
if ( p->desc != NULL )
@@ -801,12 +824,13 @@ int gic_events_need_delivery(void)
struct vcpu *v = current;
struct pending_irq *p;
unsigned long flags;
- const unsigned long apr = GICH[GICH_APR];
+ const unsigned long apr = readl_relaxed(GICH + GICH_APR);
int mask_priority;
int active_priority;
int rc = 0;
- mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
+ mask_priority = (readl_relaxed(GICH + GICH_VMCR)
+ >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
active_priority = find_next_bit(&apr, 32, 0);
spin_lock_irqsave(&v->arch.vgic.lock, flags);
@@ -836,22 +860,23 @@ out:
void gic_inject(void)
{
+ uint32_t hcr;
ASSERT(!local_irq_is_enabled());
gic_restore_pending_irqs(current);
+ hcr = readl_relaxed(GICH + GICH_HCR);
if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
- GICH[GICH_HCR] |= GICH_HCR_UIE;
+ writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
else
- GICH[GICH_HCR] &= ~GICH_HCR_UIE;
-
+ writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
}
static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
- GICC[GICC_EOIR] = sgi;
+ writel_relaxed(sgi, GICC + GICC_EOIR);
switch (sgi)
{
@@ -870,7 +895,7 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
}
/* Deactivate */
- GICC[GICC_DIR] = sgi;
+ writel_relaxed(sgi, GICC + GICC_DIR);
}
/* Accept an interrupt from the GIC and dispatch its handler */
@@ -881,7 +906,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
do {
- intack = GICC[GICC_IAR];
+ intack = readl_relaxed(GICC + GICC_IAR);
irq = intack & GICC_IA_IRQ;
if ( likely(irq >= 16 && irq < 1021) )
@@ -968,7 +993,7 @@ void gic_dump_info(struct vcpu *v)
if ( v == current )
{
for ( i = 0; i < nr_lrs; i++ )
- printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
+ printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
} else {
for ( i = 0; i < nr_lrs; i++ )
printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 074d2f3..139c2e9 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -30,7 +30,7 @@
#include <asm/mmio.h>
#include <asm/gic.h>
-#define REG(n) (n/4)
+#define REG(n) (n)
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
@@ -58,7 +58,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
* Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
* <b>-bits-per-interrupt.
*/
-#define REG_RANK_INDEX(b, n) ((n) & ((b)-1))
+#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
/*
* Returns rank corresponding to a GICD_<FOO><n> register for
@@ -66,7 +66,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
*/
static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n)
{
- int rank = REG_RANK_NR(b, n);
+ int rank = REG_RANK_NR(b, (n >> 2));
if ( rank == 0 )
return &v->arch.vgic.private_irqs;
@@ -78,7 +78,7 @@ static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n)
static struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
{
- return vgic_rank_offset(v, 8, irq >> 2);
+ return vgic_rank_offset(v, 8, irq);
}
static const struct mmio_handler_ops vgic_distr_mmio_handler = {
@@ -552,7 +552,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
tr = rank->ienable;
rank->ienable |= *r;
vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr), gicd_reg - GICD_ISENABLER);
+ vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
@@ -563,7 +563,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
tr = rank->ienable;
rank->ienable &= ~*r;
vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr, gicd_reg - GICD_ICENABLER);
+ vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
@@ -725,7 +725,6 @@ void vgic_clear_pending_irqs(struct vcpu *v)
void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
{
- int idx = irq >> 2, byte = irq & 0x3;
uint8_t priority;
struct vgic_irq_rank *rank = vgic_rank_irq(v, irq);
struct pending_irq *iter, *n = irq_to_pending(v, irq);
@@ -748,7 +747,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte);
+ priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index c7b7368..7fa3b95 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -18,37 +18,37 @@
#ifndef __ASM_ARM_GIC_H__
#define __ASM_ARM_GIC_H__
-#define GICD_CTLR (0x000/4)
-#define GICD_TYPER (0x004/4)
-#define GICD_IIDR (0x008/4)
-#define GICD_IGROUPR (0x080/4)
-#define GICD_IGROUPRN (0x0FC/4)
-#define GICD_ISENABLER (0x100/4)
-#define GICD_ISENABLERN (0x17C/4)
-#define GICD_ICENABLER (0x180/4)
-#define GICD_ICENABLERN (0x1fC/4)
-#define GICD_ISPENDR (0x200/4)
-#define GICD_ISPENDRN (0x27C/4)
-#define GICD_ICPENDR (0x280/4)
-#define GICD_ICPENDRN (0x2FC/4)
-#define GICD_ISACTIVER (0x300/4)
-#define GICD_ISACTIVERN (0x37C/4)
-#define GICD_ICACTIVER (0x380/4)
-#define GICD_ICACTIVERN (0x3FC/4)
-#define GICD_IPRIORITYR (0x400/4)
-#define GICD_IPRIORITYRN (0x7F8/4)
-#define GICD_ITARGETSR (0x800/4)
-#define GICD_ITARGETSRN (0xBF8/4)
-#define GICD_ICFGR (0xC00/4)
-#define GICD_ICFGRN (0xCFC/4)
-#define GICD_NSACR (0xE00/4)
-#define GICD_NSACRN (0xEFC/4)
-#define GICD_SGIR (0xF00/4)
-#define GICD_CPENDSGIR (0xF10/4)
-#define GICD_CPENDSGIRN (0xF1C/4)
-#define GICD_SPENDSGIR (0xF20/4)
-#define GICD_SPENDSGIRN (0xF2C/4)
-#define GICD_ICPIDR2 (0xFE8/4)
+#define GICD_CTLR (0x000)
+#define GICD_TYPER (0x004)
+#define GICD_IIDR (0x008)
+#define GICD_IGROUPR (0x080)
+#define GICD_IGROUPRN (0x0FC)
+#define GICD_ISENABLER (0x100)
+#define GICD_ISENABLERN (0x17C)
+#define GICD_ICENABLER (0x180)
+#define GICD_ICENABLERN (0x1fC)
+#define GICD_ISPENDR (0x200)
+#define GICD_ISPENDRN (0x27C)
+#define GICD_ICPENDR (0x280)
+#define GICD_ICPENDRN (0x2FC)
+#define GICD_ISACTIVER (0x300)
+#define GICD_ISACTIVERN (0x37C)
+#define GICD_ICACTIVER (0x380)
+#define GICD_ICACTIVERN (0x3FC)
+#define GICD_IPRIORITYR (0x400)
+#define GICD_IPRIORITYRN (0x7F8)
+#define GICD_ITARGETSR (0x800)
+#define GICD_ITARGETSRN (0xBF8)
+#define GICD_ICFGR (0xC00)
+#define GICD_ICFGRN (0xCFC)
+#define GICD_NSACR (0xE00)
+#define GICD_NSACRN (0xEFC)
+#define GICD_SGIR (0xF00)
+#define GICD_CPENDSGIR (0xF10)
+#define GICD_CPENDSGIRN (0xF1C)
+#define GICD_SPENDSGIR (0xF20)
+#define GICD_SPENDSGIRN (0xF2C)
+#define GICD_ICPIDR2 (0xFE8)
#define GICD_SGI_TARGET_LIST_SHIFT (24)
#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
@@ -60,27 +60,27 @@
#define GICD_SGI_GROUP1 (1UL<<15)
#define GICD_SGI_INTID_MASK (0xFUL)
-#define GICC_CTLR (0x0000/4)
-#define GICC_PMR (0x0004/4)
-#define GICC_BPR (0x0008/4)
-#define GICC_IAR (0x000C/4)
-#define GICC_EOIR (0x0010/4)
-#define GICC_RPR (0x0014/4)
-#define GICC_HPPIR (0x0018/4)
-#define GICC_APR (0x00D0/4)
-#define GICC_NSAPR (0x00E0/4)
-#define GICC_DIR (0x1000/4)
-
-#define GICH_HCR (0x00/4)
-#define GICH_VTR (0x04/4)
-#define GICH_VMCR (0x08/4)
-#define GICH_MISR (0x10/4)
-#define GICH_EISR0 (0x20/4)
-#define GICH_EISR1 (0x24/4)
-#define GICH_ELSR0 (0x30/4)
-#define GICH_ELSR1 (0x34/4)
-#define GICH_APR (0xF0/4)
-#define GICH_LR (0x100/4)
+#define GICC_CTLR (0x0000)
+#define GICC_PMR (0x0004)
+#define GICC_BPR (0x0008)
+#define GICC_IAR (0x000C)
+#define GICC_EOIR (0x0010)
+#define GICC_RPR (0x0014)
+#define GICC_HPPIR (0x0018)
+#define GICC_APR (0x00D0)
+#define GICC_NSAPR (0x00E0)
+#define GICC_DIR (0x1000)
+
+#define GICH_HCR (0x00)
+#define GICH_VTR (0x04)
+#define GICH_VMCR (0x08)
+#define GICH_MISR (0x10)
+#define GICH_EISR0 (0x20)
+#define GICH_EISR1 (0x24)
+#define GICH_ELSR0 (0x30)
+#define GICH_ELSR1 (0x34)
+#define GICH_APR (0xF0)
+#define GICH_LR (0x100)
/* Register bits */
#define GICD_CTL_ENABLE 0x1
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (4 preceding siblings ...)
2014-06-26 5:33 ` [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 12:21 ` Julien Grall
2014-06-26 5:33 ` [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver vijay.kilari
` (11 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
GIC driver contains both generic and hardware specific low
level functionality in gic.c file.
With this patch, low level functionality is moved to separate
file gic-v2.c and generic code is kept in gic.c file
Callbacks are registered by low level driver with generic driver
and are called wherever required.
The locking mechanism is not changed.
This helps to separate generic and hardware functionality
and implement future hardware version drivers.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/Makefile | 2 +-
xen/arch/arm/gic-v2.c | 687 +++++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/gic.c | 554 +++++-------------------------------
xen/include/asm-arm/gic.h | 107 +++++--
4 files changed, 845 insertions(+), 505 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 63e0460..969ee52 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -10,7 +10,7 @@ obj-y += vpsci.o
obj-y += domctl.o
obj-y += sysctl.o
obj-y += domain_build.o
-obj-y += gic.o
+obj-y += gic.o gic-v2.o
obj-y += io.o
obj-y += irq.o
obj-y += kernel.o
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
new file mode 100644
index 0000000..fb579d2
--- /dev/null
+++ b/xen/arch/arm/gic-v2.c
@@ -0,0 +1,687 @@
+/*
+ * xen/arch/arm/gic-v2.c
+ *
+ * ARM Generic Interrupt Controller support v2
+ *
+ * Tim Deegan <tim@xen.org>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/mm.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+#include <xen/errno.h>
+#include <xen/softirq.h>
+#include <xen/list.h>
+#include <xen/device_tree.h>
+#include <asm/p2m.h>
+#include <asm/domain.h>
+#include <asm/platform.h>
+
+#include <asm/io.h>
+#include <asm/gic.h>
+
+/*
+ * LR register definitions are GIC v2 specific.
+ * Moved these definitions from header file to here
+ */
+#define GICH_V2_LR_VIRTUAL_MASK 0x3ff
+#define GICH_V2_LR_VIRTUAL_SHIFT 0
+#define GICH_V2_LR_PHYSICAL_MASK 0x3ff
+#define GICH_V2_LR_PHYSICAL_SHIFT 10
+#define GICH_V2_LR_STATE_MASK 0x3
+#define GICH_V2_LR_STATE_SHIFT 28
+#define GICH_V2_LR_PRIORITY_SHIFT 23
+#define GICH_V2_LR_PRIORITY_MASK 0x1f
+#define GICH_V2_LR_HW_SHIFT 31
+#define GICH_V2_LR_HW_MASK 0x1
+#define GICH_V2_LR_GRP_SHIFT 30
+#define GICH_V2_LR_GRP_MASK 0x1
+#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19)
+#define GICH_V2_LR_GRP1 (1<<30)
+#define GICH_V2_LR_HW (1<<31)
+#define GICH_V2_LR_CPUID_SHIFT 9
+#define GICH_V2_VTR_NRLRGS 0x3f
+
+#define GICH_V2_VMCR_PRIORITY_MASK 0x1f
+#define GICH_V2_VMCR_PRIORITY_SHIFT 27
+
+#define GICD (gicv2.map_dbase)
+#define GICC (gicv2.map_cbase)
+#define GICH (gicv2.map_hbase)
+
+/* Global state */
+static struct {
+ paddr_t dbase; /* Address of distributor registers */
+ void __iomem * map_dbase; /* IO mapped Address of distributor registers */
+ paddr_t cbase; /* Address of CPU interface registers */
+ void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
+ paddr_t hbase; /* Address of virtual interface registers */
+ void __iomem * map_hbase; /* IO Address of virtual interface registers */
+ paddr_t vbase; /* Address of virtual cpu interface registers */
+ spinlock_t lock;
+} gicv2;
+
+static struct gic_info gicv2_info;
+
+/* The GIC mapping of CPU interfaces does not necessarily match the
+ * logical CPU numbering. Let's use mapping as returned by the GIC
+ * itself
+ */
+static DEFINE_PER_CPU(u8, gic_cpu_id);
+
+/* Maximum cpu interface per GIC */
+#define NR_GIC_CPU_IF 8
+
+static unsigned int gicv2_cpu_mask(const cpumask_t *cpumask)
+{
+ unsigned int cpu;
+ unsigned int mask = 0;
+ cpumask_t possible_mask;
+
+ cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
+ for_each_cpu( cpu, &possible_mask )
+ {
+ ASSERT(cpu < NR_GIC_CPU_IF);
+ mask |= per_cpu(gic_cpu_id, cpu);
+ }
+
+ return mask;
+}
+
+static void gicv2_save_state(struct vcpu *v)
+{
+ int i;
+
+ /* No need for spinlocks here because interrupts are disabled around
+ * this call and it only accesses struct vcpu fields that cannot be
+ * accessed simultaneously by another pCPU.
+ */
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
+
+ v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
+ /* Disable until next VCPU scheduled */
+ writel_relaxed(0, GICH + GICH_HCR);
+}
+
+static void gicv2_restore_state(const struct vcpu *v)
+{
+ int i;
+
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+
+ writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
+}
+
+static void gicv2_dump_state(const struct vcpu *v)
+{
+ int i;
+
+ if ( v == current )
+ {
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ printk(" HW_LR[%d]=%x\n", i,
+ readl_relaxed(GICH + GICH_LR + i * 4));
+ }
+ else
+ {
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ }
+}
+
+static void gicv2_eoi_irq(struct irq_desc *irqd)
+{
+ int irq = irqd->irq;
+ /* Lower the priority */
+ writel_relaxed(irq, GICC + GICC_EOIR);
+}
+
+static void gicv2_dir_irq(struct irq_desc *irqd)
+{
+ /* Deactivate */
+ writel_relaxed(irqd->irq, GICC + GICC_DIR);
+}
+
+static unsigned int gicv2_read_irq(void)
+{
+ return (readl_relaxed(GICC + GICC_IAR) & GICC_IA_IRQ);
+}
+
+/*
+ * needs to be called with a valid cpu_mask, ie each cpu in the mask has
+ * already called gic_cpu_init
+ */
+static void gicv2_set_irq_properties(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority)
+{
+ uint32_t cfg, edgebit, itarget, ipriority;
+ unsigned int mask = gicv2_cpu_mask(cpu_mask);
+ unsigned int irq = desc->irq;
+ unsigned int type = desc->arch.type;
+
+ ASSERT(type != DT_IRQ_TYPE_INVALID);
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock(&gicv2.lock);
+ /* Set edge / level */
+ cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
+ edgebit = 2u << (2 * (irq % 16));
+ if ( type & DT_IRQ_TYPE_LEVEL_MASK )
+ cfg &= ~edgebit;
+ else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
+ cfg |= edgebit;
+ writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
+
+ /* Set target CPU mask (RAZ/WI on uniprocessor) */
+ itarget = readl_relaxed(GICD + GICD_ITARGETSR + (irq / 4) * 4);
+ /* Clear mask */
+ itarget &= ~(0xffu << (8 * (irq % 4)));
+ /* Set mask */
+ itarget |= mask << (8 * (irq % 4));
+ writel_relaxed(itarget, GICD + GICD_ITARGETSR + (irq / 4) * 4);
+
+ ipriority = readl_relaxed(GICD + GICD_IPRIORITYR + (irq / 4) * 4);
+ /* Clear priority */
+ ipriority &= ~(0xffu << (8 * (irq % 4)));
+ /* Set priority */
+ ipriority |= priority << (8 * (irq % 4));
+ writel_relaxed(ipriority, GICD + GICD_IPRIORITYR + (irq / 4) * 4);
+
+ spin_unlock(&gicv2.lock);
+}
+
+static void __init gicv2_dist_init(void)
+{
+ uint32_t type;
+ uint32_t cpumask;
+ uint32_t gic_cpus;
+ int i;
+
+ cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
+ cpumask |= cpumask << 8;
+ cpumask |= cpumask << 16;
+
+ /* Disable the distributor */
+ writel_relaxed(0, GICD + GICD_CTLR);
+
+ type = readl_relaxed(GICD + GICD_TYPER);
+ gicv2_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
+ gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
+ printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n",
+ gicv2_info.nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s",
+ (type & GICD_TYPE_SEC) ? ", secure" : "",
+ readl_relaxed(GICD + GICD_IIDR));
+
+ /* Default all global IRQs to level, active low */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 16 )
+ writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
+
+ /* Route all global IRQs to this CPU */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
+ writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
+
+ /* Default priority for global interrupts */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
+ writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Disable all global interrupts */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 32 )
+ writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
+
+ /* Turn on the distributor */
+ writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
+}
+
+static void __cpuinit gicv2_cpu_init(void)
+{
+ int i;
+
+ this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
+
+ /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
+ * even though they are controlled with GICD registers, they must
+ * be set up here with the other per-cpu state. */
+ writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
+ writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
+
+ /* Set SGI priorities */
+ for ( i = 0; i < 16; i += 4 )
+ writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
+ GIC_PRI_IPI << 8 | GIC_PRI_IPI,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Set PPI priorities */
+ for ( i = 16; i < 32; i += 4 )
+ writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Local settings: interface controller */
+ /* Don't mask by priority */
+ writel_relaxed(0xff, GICC + GICC_PMR);
+ /* Finest granularity of priority */
+ writel_relaxed(0x0, GICC + GICC_BPR);
+ /* Turn on delivery */
+ writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
+}
+
+static void gicv2_cpu_disable(void)
+{
+ writel_relaxed(0x0, GICC + GICC_CTLR);
+}
+
+static void __cpuinit gicv2_hyp_init(void)
+{
+ uint32_t vtr;
+ uint8_t nr_lrs;
+
+ vtr = readl_relaxed(GICH + GICH_VTR);
+ nr_lrs = (vtr & GICH_V2_VTR_NRLRGS) + 1;
+ gicv2_info.nr_lrs = nr_lrs;
+
+ writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
+}
+
+static void __cpuinit gicv2_hyp_disable(void)
+{
+ writel_relaxed(0, GICH + GICH_HCR);
+}
+
+static int gicv2_secondary_cpu_init(void)
+{
+ spin_lock(&gicv2.lock);
+
+ gicv2_cpu_init();
+ gicv2_hyp_init();
+
+ spin_unlock(&gicv2.lock);
+
+ return 0;
+}
+
+static void gicv2_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
+ const cpumask_t *cpu_mask)
+{
+ unsigned int mask = 0;
+
+ switch ( irqmode )
+ {
+ case SGI_TARGET_OTHERS:
+ writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
+ break;
+ case SGI_TARGET_SELF:
+ writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
+ break;
+ case SGI_TARGET_LIST:
+ mask = gicv2_cpu_mask(cpu_mask);
+ writel_relaxed(GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi,
+ GICD + GICD_SGIR);
+ break;
+ default:
+ BUG();
+ }
+}
+
+/* Shut down the per-CPU GIC interface */
+static void gicv2_disable_interface(void)
+{
+ spin_lock(&gicv2.lock);
+ gicv2_cpu_disable();
+ gicv2_hyp_disable();
+ spin_unlock(&gicv2.lock);
+}
+
+static void gicv2_update_lr(int lr, const struct pending_irq *p,
+ unsigned int state)
+{
+ uint32_t lr_reg;
+
+ BUG_ON(lr >= gicv2_info.nr_lrs);
+ BUG_ON(lr < 0);
+
+ lr_reg = (((state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) |
+ ((GIC_PRI_TO_GUEST(p->priority) & GICH_V2_LR_PRIORITY_MASK)
+ << GICH_V2_LR_PRIORITY_SHIFT) |
+ ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT));
+
+ if ( p->desc != NULL )
+ lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK )
+ << GICH_V2_LR_PHYSICAL_SHIFT);
+
+ writel_relaxed(lr_reg, GICH + GICH_LR + lr * 4);
+}
+
+static void gicv2_clear_lr(int lr)
+{
+ writel_relaxed(0, GICH + GICH_LR + lr * 4);
+}
+
+static int gicv_v2_init(struct domain *d)
+{
+ int ret;
+
+ /*
+ * Domain 0 gets the hardware address.
+ * Guests get the virtual platform layout.
+ */
+ if ( is_hardware_domain(d) )
+ {
+ d->arch.vgic.dbase = gicv2.dbase;
+ d->arch.vgic.cbase = gicv2.cbase;
+ }
+ else
+ {
+ d->arch.vgic.dbase = GUEST_GICD_BASE;
+ d->arch.vgic.cbase = GUEST_GICC_BASE;
+ }
+
+ d->arch.vgic.nr_lines = 0;
+
+ /*
+ * Map the gic virtual cpu interface in the gic cpu interface
+ * region of the guest.
+ *
+ * The second page is always mapped at +4K irrespective of the
+ * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
+ */
+ ret = map_mmio_regions(d, d->arch.vgic.cbase,
+ d->arch.vgic.cbase + PAGE_SIZE - 1,
+ gicv2.vbase);
+ if ( ret )
+ return ret;
+
+ if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+ ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+ d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+ gicv2.vbase + PAGE_SIZE);
+ else
+ ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+ d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+ gicv2.vbase + 16*PAGE_SIZE);
+
+ return ret;
+}
+
+static void gicv2_read_lr(int lr, struct gic_lr *lr_reg)
+{
+ uint32_t lrv;
+
+ lrv = readl_relaxed(GICH + GICH_LR + lr * 4);
+ lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK;
+ lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK;
+ lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK;
+ lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK;
+ lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK;
+ lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK;
+}
+
+static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg)
+{
+ uint32_t lrv = 0;
+
+ lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) |
+ ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) |
+ ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK)
+ << GICH_V2_LR_PRIORITY_SHIFT) |
+ ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK)
+ << GICH_V2_LR_STATE_SHIFT) |
+ ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK)
+ << GICH_V2_LR_HW_SHIFT) |
+ ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) );
+
+ writel_relaxed(lrv, GICH + GICH_LR + lr * 4);
+}
+
+static void gicv2_hcr_status(uint32_t flag, bool_t status)
+{
+ uint32_t hcr = readl_relaxed(GICH + GICH_HCR);
+
+ if ( status )
+ hcr |= flag;
+ else
+ hcr &= (~flag);
+
+ writel_relaxed(hcr, GICH + GICH_HCR);
+}
+
+static unsigned int gicv2_read_vmcr_priority(void)
+{
+ return ((readl_relaxed(GICH + GICH_VMCR) >> GICH_V2_VMCR_PRIORITY_SHIFT)
+ & GICH_V2_VMCR_PRIORITY_MASK);
+}
+
+static unsigned int gicv2_read_apr(int apr_reg)
+{
+ return readl_relaxed(GICH + GICH_APR);
+}
+
+static void gicv2_irq_enable(struct irq_desc *desc)
+{
+ unsigned long flags;
+ int irq = desc->irq;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&gicv2.lock, flags);
+ desc->status &= ~IRQ_DISABLED;
+ dsb(sy);
+ /* Enable routing */
+ writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
+ spin_unlock_irqrestore(&gicv2.lock, flags);
+}
+
+static void gicv2_irq_disable(struct irq_desc *desc)
+{
+ unsigned long flags;
+ int irq = desc->irq;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&gicv2.lock, flags);
+ /* Disable routing */
+ writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
+ desc->status |= IRQ_DISABLED;
+ spin_unlock_irqrestore(&gicv2.lock, flags);
+}
+
+static unsigned int gicv2_irq_startup(struct irq_desc *desc)
+{
+ gicv2_irq_enable(desc);
+
+ return 0;
+}
+
+static void gicv2_irq_shutdown(struct irq_desc *desc)
+{
+ gicv2_irq_disable(desc);
+}
+
+static void gicv2_irq_ack(struct irq_desc *desc)
+{
+ /* No ACK -- reading IAR has done this for us */
+}
+
+static void gicv2_host_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority */
+ gicv2_eoi_irq(desc);
+ /* Deactivate */
+ gicv2_dir_irq(desc);
+}
+
+static void gicv2_guest_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority of the IRQ */
+ gicv2_eoi_irq(desc);
+ /* Deactivation happens in maintenance interrupt / via GICV */
+}
+
+static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
+{
+ BUG();
+}
+
+/* XXX different for level vs edge */
+static hw_irq_controller gicv2_host_irq_type = {
+ .typename = "gic-v2",
+ .startup = gicv2_irq_startup,
+ .shutdown = gicv2_irq_shutdown,
+ .enable = gicv2_irq_enable,
+ .disable = gicv2_irq_disable,
+ .ack = gicv2_irq_ack,
+ .end = gicv2_host_irq_end,
+ .set_affinity = gicv2_irq_set_affinity,
+};
+
+static hw_irq_controller gicv2_guest_irq_type = {
+ .typename = "gic-v2",
+ .startup = gicv2_irq_startup,
+ .shutdown = gicv2_irq_shutdown,
+ .enable = gicv2_irq_enable,
+ .disable = gicv2_irq_disable,
+ .ack = gicv2_irq_ack,
+ .end = gicv2_guest_irq_end,
+ .set_affinity = gicv2_irq_set_affinity,
+};
+
+const static struct gic_hw_operations gicv2_ops = {
+ .info = &gicv2_info,
+ .secondary_init = gicv2_secondary_cpu_init,
+ .save_state = gicv2_save_state,
+ .restore_state = gicv2_restore_state,
+ .dump_state = gicv2_dump_state,
+ .gicv_setup = gicv_v2_init,
+ .gic_host_irq_type = &gicv2_host_irq_type,
+ .gic_guest_irq_type = &gicv2_guest_irq_type,
+ .eoi_irq = gicv2_eoi_irq,
+ .deactivate_irq = gicv2_dir_irq,
+ .read_irq = gicv2_read_irq,
+ .set_irq_properties = gicv2_set_irq_properties,
+ .send_SGI = gicv2_send_SGI,
+ .disable_interface = gicv2_disable_interface,
+ .update_lr = gicv2_update_lr,
+ .update_hcr_status = gicv2_hcr_status,
+ .clear_lr = gicv2_clear_lr,
+ .read_lr = gicv2_read_lr,
+ .write_lr = gicv2_write_lr,
+ .read_vmcr_priority = gicv2_read_vmcr_priority,
+ .read_apr = gicv2_read_apr,
+};
+
+/* Set up the GIC */
+void __init gicv2_init(void)
+{
+ static const struct dt_device_match gic_ids[] __initconst =
+ {
+ DT_MATCH_GIC,
+ { /* sentinel */ },
+ };
+ struct dt_device_node *node;
+ int res;
+
+ node = dt_find_interrupt_controller(gic_ids);
+ if ( !node )
+ panic("GICv2: Unable to find compatible GIC in the device tree");
+
+ dt_device_set_used_by(node, DOMID_XEN);
+
+ res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
+ if ( res || !gicv2.dbase || (gicv2.dbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the distributor");
+
+ res = dt_device_get_address(node, 1, &gicv2.cbase, NULL);
+ if ( res || !gicv2.cbase || (gicv2.cbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the CPU");
+
+ res = dt_device_get_address(node, 2, &gicv2.hbase, NULL);
+ if ( res || !gicv2.hbase || (gicv2.hbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the hypervisor");
+
+ res = dt_device_get_address(node, 3, &gicv2.vbase, NULL);
+ if ( res || !gicv2.vbase || (gicv2.vbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the virtual CPU");
+
+ res = platform_get_irq(node, 0);
+ if ( res < 0 )
+ panic("GICv2: Cannot find the maintenance IRQ");
+ gicv2_info.maintenance_irq = res;
+
+ /* Set the GIC as the primary interrupt controller */
+ dt_interrupt_controller = node;
+
+ /* TODO: Add check on distributor, cpu size */
+
+ printk("GICv2 initialization:\n"
+ " gic_dist_addr=%"PRIpaddr"\n"
+ " gic_cpu_addr=%"PRIpaddr"\n"
+ " gic_hyp_addr=%"PRIpaddr"\n"
+ " gic_vcpu_addr=%"PRIpaddr"\n"
+ " gic_maintenance_irq=%u\n",
+ gicv2.dbase, gicv2.cbase, gicv2.hbase, gicv2.vbase,
+ gicv2_info.maintenance_irq);
+
+ if ( (gicv2.dbase & ~PAGE_MASK) || (gicv2.cbase & ~PAGE_MASK) ||
+ (gicv2.hbase & ~PAGE_MASK) || (gicv2.vbase & ~PAGE_MASK) )
+ panic("GICv2 interfaces not page aligned");
+
+ gicv2.map_dbase = ioremap_nocache(gicv2.dbase, PAGE_SIZE);
+ if ( !gicv2.map_dbase )
+ panic("GICv2: Failed to ioremap for GIC distributor\n");
+
+ if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+ gicv2.map_cbase = ioremap_nocache(gicv2.cbase, PAGE_SIZE * 0x10);
+ else
+ gicv2.map_cbase = ioremap_nocache(gicv2.cbase, PAGE_SIZE * 2);
+
+ if ( !gicv2.map_cbase )
+ panic("GICv2: Failed to ioremap for GIC CPU interface\n");
+
+ gicv2.map_hbase = ioremap_nocache(gicv2.hbase, PAGE_SIZE);
+ if ( !gicv2.map_hbase )
+ panic("GICv2: Failed to ioremap for GIC Virtual interface\n");
+
+ /* Global settings: interrupt distributor */
+ spin_lock_init(&gicv2.lock);
+ spin_lock(&gicv2.lock);
+
+ gicv2_dist_init();
+ gicv2_cpu_init();
+ gicv2_hyp_init();
+
+ spin_unlock(&gicv2.lock);
+
+ gicv2_info.hw_version = GIC_V2;
+ register_gic_ops(&gicv2_ops);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 5aebbf5..49b9360 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -24,7 +24,6 @@
#include <xen/irq.h>
#include <xen/sched.h>
#include <xen/errno.h>
-#include <xen/serial.h>
#include <xen/softirq.h>
#include <xen/list.h>
#include <xen/device_tree.h>
@@ -34,196 +33,68 @@
#include <asm/io.h>
#include <asm/gic.h>
-#define GICD (gic.map_dbase)
-#define GICC (gic.map_cbase)
-#define GICH (gic.map_hbase)
-
static void gic_restore_pending_irqs(struct vcpu *v);
-/* Global state */
-static struct {
- paddr_t dbase; /* Address of distributor registers */
- void __iomem * map_dbase; /* IO mapped Address of distributor registers */
- paddr_t cbase; /* Address of CPU interface registers */
- void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
- paddr_t hbase; /* Address of virtual interface registers */
- void __iomem * map_hbase; /* IO Address of virtual interface registers */
- paddr_t vbase; /* Address of virtual cpu interface registers */
- unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
- unsigned int maintenance_irq; /* IRQ maintenance */
- unsigned int cpus;
- spinlock_t lock;
-} gic;
-
static DEFINE_PER_CPU(uint64_t, lr_mask);
-static uint8_t nr_lrs;
-#define lr_all_full() (this_cpu(lr_mask) == ((1 << nr_lrs) - 1))
-
-/* The GIC mapping of CPU interfaces does not necessarily match the
- * logical CPU numbering. Let's use mapping as returned by the GIC
- * itself
- */
-static DEFINE_PER_CPU(u8, gic_cpu_id);
-
-/* Maximum cpu interface per GIC */
-#define NR_GIC_CPU_IF 8
+#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1))
#undef GIC_DEBUG
static void gic_update_one_lr(struct vcpu *v, int i);
-static unsigned int gic_cpu_mask(const cpumask_t *cpumask)
+static const struct gic_hw_operations *gic_hw_ops;
+
+void register_gic_ops(const struct gic_hw_operations *ops)
{
- unsigned int cpu;
- unsigned int mask = 0;
- cpumask_t possible_mask;
+ gic_hw_ops = ops;
+}
- cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
- for_each_cpu(cpu, &possible_mask)
- {
- ASSERT(cpu < NR_GIC_CPU_IF);
- mask |= per_cpu(gic_cpu_id, cpu);
- }
+static void update_cpu_lr_mask(void)
+{
+ this_cpu(lr_mask) = 0ULL;
+}
- return mask;
+enum gic_version gic_hw_version(void)
+{
+ return gic_hw_ops->info->hw_version;
}
unsigned int gic_number_lines(void)
{
- return gic.lines;
+ return gic_hw_ops->info->nr_lines;
}
void gic_save_state(struct vcpu *v)
{
- int i;
ASSERT(!local_irq_is_enabled());
/* No need for spinlocks here because interrupts are disabled around
* this call and it only accesses struct vcpu fields that cannot be
* accessed simultaneously by another pCPU.
*/
- for ( i=0; i<nr_lrs; i++)
- v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
v->arch.lr_mask = this_cpu(lr_mask);
- v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
- v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
- /* Disable until next VCPU scheduled */
- writel_relaxed(0, GICH + GICH_HCR);
+ gic_hw_ops->save_state(v);
isb();
}
void gic_restore_state(struct vcpu *v)
{
- int i;
ASSERT(!local_irq_is_enabled());
if ( is_idle_vcpu(v) )
return;
this_cpu(lr_mask) = v->arch.lr_mask;
- for ( i=0; i<nr_lrs; i++)
- writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
- writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
- writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
- writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
+ gic_hw_ops->restore_state(v);
+
isb();
gic_restore_pending_irqs(v);
}
-static void gic_irq_enable(struct irq_desc *desc)
-{
- int irq = desc->irq;
- unsigned long flags;
-
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock_irqsave(&gic.lock, flags);
- /* Enable routing */
- desc->status &= ~IRQ_DISABLED;
- dsb(sy);
- writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
- spin_unlock_irqrestore(&gic.lock, flags);
-}
-
-static void gic_irq_disable(struct irq_desc *desc)
-{
- int irq = desc->irq;
- unsigned long flags;
-
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock_irqsave(&gic.lock, flags);
- /* Disable routing */
- writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
- desc->status |= IRQ_DISABLED;
- spin_unlock_irqrestore(&gic.lock, flags);
-}
-
-static unsigned int gic_irq_startup(struct irq_desc *desc)
-{
- gic_irq_enable(desc);
-
- return 0;
-}
-
-static void gic_irq_shutdown(struct irq_desc *desc)
-{
- gic_irq_disable(desc);
-}
-
-static void gic_irq_ack(struct irq_desc *desc)
-{
- /* No ACK -- reading IAR has done this for us */
-}
-
-static void gic_host_irq_end(struct irq_desc *desc)
-{
- int irq = desc->irq;
- /* Lower the priority */
- writel_relaxed(irq, GICC + GICC_EOIR);
- /* Deactivate */
- writel_relaxed(irq, GICC + GICC_DIR);
-}
-
-static void gic_guest_irq_end(struct irq_desc *desc)
-{
- int irq = desc->irq;
- /* Lower the priority of the IRQ */
- writel_relaxed(irq, GICC + GICC_EOIR);
- /* Deactivation happens in maintenance interrupt / via GICV */
-}
-
-static void gic_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
-{
- BUG();
-}
-
-/* XXX different for level vs edge */
-static hw_irq_controller gic_host_irq_type = {
- .typename = "gic",
- .startup = gic_irq_startup,
- .shutdown = gic_irq_shutdown,
- .enable = gic_irq_enable,
- .disable = gic_irq_disable,
- .ack = gic_irq_ack,
- .end = gic_host_irq_end,
- .set_affinity = gic_irq_set_affinity,
-};
-static hw_irq_controller gic_guest_irq_type = {
- .typename = "gic",
- .startup = gic_irq_startup,
- .shutdown = gic_irq_shutdown,
- .enable = gic_irq_enable,
- .disable = gic_irq_disable,
- .ack = gic_irq_ack,
- .end = gic_guest_irq_end,
- .set_affinity = gic_irq_set_affinity,
-};
-
/*
- * - needs to be called with a valid cpu_mask, ie each cpu in the mask has
+ * needs to be called with a valid cpu_mask, ie each cpu in the mask has
* already called gic_cpu_init
* - desc.lock must be held
* - arch.type must be valid (i.e != DT_IRQ_TYPE_INVALID)
@@ -232,43 +103,7 @@ static void gic_set_irq_properties(struct irq_desc *desc,
const cpumask_t *cpu_mask,
unsigned int priority)
{
- uint32_t cfg, edgebit, itarget, ipriority;
- unsigned int mask;
- unsigned int irq = desc->irq;
- unsigned int type = desc->arch.type;
-
- ASSERT(type != DT_IRQ_TYPE_INVALID);
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock(&gic.lock);
-
- mask = gic_cpu_mask(cpu_mask);
-
- /* Set edge / level */
- cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
- edgebit = 2u << (2 * (irq % 16));
- if ( type & DT_IRQ_TYPE_LEVEL_MASK )
- cfg &= ~edgebit;
- else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
- cfg |= edgebit;
- writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
-
- /* Set target CPU mask (RAZ/WI on uniprocessor) */
- itarget = readl_relaxed(GICD + GICD_ITARGETSR + (irq / 4) * 4);
- /* Clear mask */
- itarget &= ~(0xffu << (8 * (irq % 4)));
- /* Set mask */
- itarget |= mask << (8 * (irq % 4));
- writel_relaxed(itarget, GICD + GICD_ITARGETSR + (irq / 4) * 4);
-
- ipriority = readl_relaxed(GICD + GICD_IPRIORITYR + (irq / 4) * 4);
- /* Clear priority */
- ipriority &= ~(0xffu << (8 * (irq % 4)));
- /* Set priority */
- ipriority |= priority << (8 * (irq % 4));
- writel_relaxed(ipriority, GICD + GICD_IPRIORITYR + (irq / 4) * 4);
-
- spin_unlock(&gic.lock);
+ gic_hw_ops->set_irq_properties(desc, cpu_mask, priority);
}
/* Program the GIC to route an interrupt to the host (i.e. Xen)
@@ -278,11 +113,11 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask,
unsigned int priority)
{
ASSERT(priority <= 0xff); /* Only 8 bits of priority */
- ASSERT(desc->irq < gic.lines);/* Can't route interrupts that don't exist */
+ ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */
ASSERT(desc->status & IRQ_DISABLED);
ASSERT(spin_is_locked(&desc->lock));
- desc->handler = &gic_host_irq_type;
+ desc->handler = gic_hw_ops->gic_host_irq_type;
gic_set_irq_properties(desc, cpu_mask, priority);
}
@@ -296,7 +131,7 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc,
struct pending_irq *p;
ASSERT(spin_is_locked(&desc->lock));
- desc->handler = &gic_guest_irq_type;
+ desc->handler = gic_hw_ops->gic_guest_irq_type;
desc->status |= IRQ_GUEST;
gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ);
@@ -306,102 +141,6 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc,
p->desc = desc;
}
-static void __init gic_dist_init(void)
-{
- uint32_t type;
- uint32_t cpumask;
- int i;
-
- cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
- cpumask |= cpumask << 8;
- cpumask |= cpumask << 16;
-
- /* Disable the distributor */
- writel_relaxed(0, GICD + GICD_CTLR);
-
- type = readl_relaxed(GICD + GICD_TYPER);
- gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
- gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
- printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
- gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
- (type & GICD_TYPE_SEC) ? ", secure" : "",
- readl_relaxed(GICD + GICD_IIDR));
-
- /* Default all global IRQs to level, active low */
- for ( i = 32; i < gic.lines; i += 16 )
- writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
-
- /* Route all global IRQs to this CPU */
- for ( i = 32; i < gic.lines; i += 4 )
- writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
-
- /* Default priority for global interrupts */
- for ( i = 32; i < gic.lines; i += 4 )
- writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
- GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
-
- /* Disable all global interrupts */
- for ( i = 32; i < gic.lines; i += 32 )
- writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
-
- /* Turn on the distributor */
- writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
-}
-
-static void __cpuinit gic_cpu_init(void)
-{
- int i;
-
- this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
-
- /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
- * even though they are controlled with GICD registers, they must
- * be set up here with the other per-cpu state. */
- writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
- writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
-
- /* Set SGI priorities */
- for (i = 0; i < 16; i += 4)
- writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
- GIC_PRI_IPI << 8 | GIC_PRI_IPI,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
- /* Set PPI priorities */
- for (i = 16; i < 32; i += 4)
- writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
- GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
-
- /* Local settings: interface controller */
- /* Don't mask by priority */
- writel_relaxed(0xff, GICC + GICC_PMR);
- /* Finest granularity of priority */
- writel_relaxed(0x0, GICC + GICC_BPR);
- /* Turn on delivery */
- writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
-}
-
-static void gic_cpu_disable(void)
-{
- writel_relaxed(0x0, GICC + GICC_CTLR);
-}
-
-static void __cpuinit gic_hyp_init(void)
-{
- uint32_t vtr;
-
- vtr = readl_relaxed(GICH + GICH_VTR);
- nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
-
- writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
- this_cpu(lr_mask) = 0ULL;
-}
-
-static void __cpuinit gic_hyp_disable(void)
-{
- writel_relaxed(0, GICH + GICH_HCR);
-}
-
int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
unsigned int *out_hwirq,
unsigned int *out_type)
@@ -425,108 +164,9 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
/* Set up the GIC */
void __init gic_init(void)
{
- static const struct dt_device_match gic_ids[] __initconst =
- {
- DT_MATCH_GIC,
- { /* sentinel */ },
- };
- struct dt_device_node *node;
- int res;
-
- node = dt_find_interrupt_controller(gic_ids);
- if ( !node )
- panic("Unable to find compatible GIC in the device tree");
-
- dt_device_set_used_by(node, DOMID_XEN);
-
- res = dt_device_get_address(node, 0, &gic.dbase, NULL);
- if ( res || !gic.dbase || (gic.dbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the distributor");
-
- res = dt_device_get_address(node, 1, &gic.cbase, NULL);
- if ( res || !gic.cbase || (gic.cbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the CPU");
-
- res = dt_device_get_address(node, 2, &gic.hbase, NULL);
- if ( res || !gic.hbase || (gic.hbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the hypervisor");
-
- res = dt_device_get_address(node, 3, &gic.vbase, NULL);
- if ( res || !gic.vbase || (gic.vbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the virtual CPU");
-
- res = platform_get_irq(node, 0);
- if ( res < 0 )
- panic("GIC: Cannot find the maintenance IRQ");
- gic.maintenance_irq = res;
-
- /* Set the GIC as the primary interrupt controller */
- dt_interrupt_controller = node;
-
- /* TODO: Add check on distributor, cpu size */
-
- printk("GIC initialization:\n"
- " gic_dist_addr=%"PRIpaddr"\n"
- " gic_cpu_addr=%"PRIpaddr"\n"
- " gic_hyp_addr=%"PRIpaddr"\n"
- " gic_vcpu_addr=%"PRIpaddr"\n"
- " gic_maintenance_irq=%u\n",
- gic.dbase, gic.cbase, gic.hbase, gic.vbase,
- gic.maintenance_irq);
-
- if ( (gic.dbase & ~PAGE_MASK) || (gic.cbase & ~PAGE_MASK) ||
- (gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
- panic("GIC interfaces not page aligned");
-
- gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
- if ( !gic.map_dbase )
- panic("Failed to ioremap for GIC distributor\n");
-
- if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
- else
- gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
-
- if ( !gic.map_cbase )
- panic("Failed to ioremap for GIC CPU interface\n");
-
- gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
- if ( !gic.map_hbase )
- panic("Failed to ioremap for GIC Virtual interface\n");
-
- /* Global settings: interrupt distributor */
- spin_lock_init(&gic.lock);
- spin_lock(&gic.lock);
-
- gic_dist_init();
- gic_cpu_init();
- gic_hyp_init();
-
- spin_unlock(&gic.lock);
-}
-
-static void send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
- const cpumask_t *cpu_mask)
-{
- unsigned int mask = 0;
-
- switch ( irqmode )
- {
- case SGI_TARGET_OTHERS:
- writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
- break;
- case SGI_TARGET_SELF:
- writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
- break;
- case SGI_TARGET_LIST:
- mask = gic_cpu_mask(cpu_mask);
- writel_relaxed(GICD_SGI_TARGET_LIST |
- (mask << GICD_SGI_TARGET_SHIFT) | sgi,
- GICD + GICD_SGIR);
- break;
- default:
- BUG();
- }
+ gicv2_init();
+ /* Update cpu lr mask for cpu0 */
+ update_cpu_lr_mask();
}
void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
@@ -539,12 +179,11 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
dsb(sy);
- send_SGI(sgi, SGI_TARGET_LIST, &online_mask);
+ gic_hw_ops->send_SGI(sgi, SGI_TARGET_LIST, &online_mask);
}
void send_SGI_one(unsigned int cpu, enum gic_sgi sgi)
{
- ASSERT(cpu < NR_GIC_CPU_IF); /* Targets bitmap only supports 8 CPUs */
send_SGI_mask(cpumask_of(cpu), sgi);
}
@@ -554,7 +193,7 @@ void send_SGI_self(enum gic_sgi sgi)
dsb(sy);
- send_SGI(sgi, SGI_TARGET_SELF, cpumask_of(smp_processor_id()));
+ gic_hw_ops->send_SGI(sgi, SGI_TARGET_SELF, cpumask_of(smp_processor_id()));
}
void send_SGI_allbutself(enum gic_sgi sgi)
@@ -565,7 +204,7 @@ void send_SGI_allbutself(enum gic_sgi sgi)
cpumask_andnot(&all_others_mask, &cpu_possible_map, cpumask_of(smp_processor_id()));
dsb(sy);
- send_SGI(sgi, SGI_TARGET_OTHERS, &all_others_mask);
+ gic_hw_ops->send_SGI(sgi, SGI_TARGET_OTHERS, &all_others_mask);
}
void smp_send_state_dump(unsigned int cpu)
@@ -576,10 +215,9 @@ void smp_send_state_dump(unsigned int cpu)
/* Set up the per-CPU parts of the GIC for a secondary CPU */
void __cpuinit gic_init_secondary_cpu(void)
{
- spin_lock(&gic.lock);
- gic_cpu_init();
- gic_hyp_init();
- spin_unlock(&gic.lock);
+ gic_hw_ops->secondary_init();
+ /* Update lr mask for secondary cpus */
+ update_cpu_lr_mask();
}
/* Shut down the per-CPU GIC interface */
@@ -587,28 +225,15 @@ void gic_disable_cpu(void)
{
ASSERT(!local_irq_is_enabled());
- spin_lock(&gic.lock);
- gic_cpu_disable();
- gic_hyp_disable();
- spin_unlock(&gic.lock);
+ gic_hw_ops->disable_interface();
}
static inline void gic_set_lr(int lr, struct pending_irq *p,
- unsigned int state)
+ unsigned int state)
{
- uint32_t lr_val;
-
ASSERT(!local_irq_is_enabled());
- BUG_ON(lr >= nr_lrs);
- BUG_ON(lr < 0);
- BUG_ON(state & ~(GICH_LR_STATE_MASK<<GICH_LR_STATE_SHIFT));
-
- lr_val = state | (GIC_PRI_TO_GUEST(p->priority) << GICH_LR_PRIORITY_SHIFT) |
- ((p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT);
- if ( p->desc != NULL )
- lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
- writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
+ gic_hw_ops->update_lr(lr, p, state);
set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
@@ -668,6 +293,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq,
unsigned int priority)
{
int i;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
ASSERT(spin_is_locked(&v->arch.vgic.lock));
@@ -687,36 +313,43 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq,
static void gic_update_one_lr(struct vcpu *v, int i)
{
struct pending_irq *p;
- uint32_t lr;
int irq;
+ struct gic_lr lr_val;
ASSERT(spin_is_locked(&v->arch.vgic.lock));
ASSERT(!local_irq_is_enabled());
- lr = readl_relaxed(GICH + GICH_LR + i * 4);
- irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
+ gic_hw_ops->read_lr(i, &lr_val);
+ irq = lr_val.virq;
p = irq_to_pending(v, irq);
- if ( lr & GICH_LR_ACTIVE )
+ if ( lr_val.state & GICH_LR_ACTIVE )
{
set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status);
if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) &&
test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
{
if ( p->desc == NULL )
- writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
+ {
+ lr_val.state |= GICH_LR_PENDING;
+ gic_hw_ops->write_lr(i, &lr_val);
+ }
else
gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
}
- } else if ( lr & GICH_LR_PENDING ) {
+ }
+ else if ( lr_val.state & GICH_LR_PENDING )
+ {
int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
#ifdef GIC_DEBUG
if ( q )
gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
#endif
- } else {
- writel_relaxed(0, GICH + GICH_LR + i * 4);
+ }
+ else
+ {
+ gic_hw_ops->clear_lr(i);
clear_bit(i, &this_cpu(lr_mask));
if ( p->desc != NULL )
@@ -736,6 +369,7 @@ void gic_clear_lrs(struct vcpu *v)
{
int i = 0;
unsigned long flags;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
/* The idle domain has no LRs to be cleared. Since gic_restore_state
* doesn't write any LR registers for the idle domain they could be
@@ -756,10 +390,12 @@ void gic_clear_lrs(struct vcpu *v)
static void gic_restore_pending_irqs(struct vcpu *v)
{
- int lr = 0, lrs = nr_lrs;
+ int lr = 0;
struct pending_irq *p, *t, *p_r;
struct list_head *inflight_r;
unsigned long flags;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ int lrs = nr_lrs;
spin_lock_irqsave(&v->arch.vgic.lock, flags);
@@ -824,13 +460,12 @@ int gic_events_need_delivery(void)
struct vcpu *v = current;
struct pending_irq *p;
unsigned long flags;
- const unsigned long apr = readl_relaxed(GICH + GICH_APR);
+ const unsigned long apr = gic_hw_ops->read_apr(0);
int mask_priority;
int active_priority;
int rc = 0;
- mask_priority = (readl_relaxed(GICH + GICH_VMCR)
- >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
+ mask_priority = gic_hw_ops->read_vmcr_priority();
active_priority = find_next_bit(&apr, 32, 0);
spin_lock_irqsave(&v->arch.vgic.lock, flags);
@@ -860,23 +495,23 @@ out:
void gic_inject(void)
{
- uint32_t hcr;
ASSERT(!local_irq_is_enabled());
gic_restore_pending_irqs(current);
- hcr = readl_relaxed(GICH + GICH_HCR);
-
if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
- writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
+ gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1);
else
- writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
+ gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 0);
}
static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
- writel_relaxed(sgi, GICC + GICC_EOIR);
+ struct irq_desc *desc = irq_to_desc(sgi);
+
+ /* Lower the priority */
+ gic_hw_ops->eoi_irq(desc);
switch (sgi)
{
@@ -895,19 +530,17 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
}
/* Deactivate */
- writel_relaxed(sgi, GICC + GICC_DIR);
+ gic_hw_ops->deactivate_irq(desc);
}
/* Accept an interrupt from the GIC and dispatch its handler */
void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
{
- uint32_t intack;
unsigned int irq;
-
do {
- intack = readl_relaxed(GICC + GICC_IAR);
- irq = intack & GICC_IA_IRQ;
+ /* Reading IRQ will ACK it */
+ irq = gic_hw_ops->read_irq();
if ( likely(irq >= 16 && irq < 1021) )
{
@@ -929,49 +562,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
int gicv_setup(struct domain *d)
{
- int ret;
-
- /*
- * The hardware domain gets the hardware address.
- * Guests get the virtual platform layout.
- */
- if ( is_hardware_domain(d) )
- {
- d->arch.vgic.dbase = gic.dbase;
- d->arch.vgic.cbase = gic.cbase;
- }
- else
- {
- d->arch.vgic.dbase = GUEST_GICD_BASE;
- d->arch.vgic.cbase = GUEST_GICC_BASE;
- }
-
- d->arch.vgic.nr_lines = 0;
-
- /*
- * Map the gic virtual cpu interface in the gic cpu interface
- * region of the guest.
- *
- * The second page is always mapped at +4K irrespective of the
- * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
- */
- ret = map_mmio_regions(d, d->arch.vgic.cbase,
- d->arch.vgic.cbase + PAGE_SIZE - 1,
- gic.vbase);
- if (ret)
- return ret;
-
- if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
- d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
- gic.vbase + PAGE_SIZE);
- else
- ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
- d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
- gic.vbase + 16*PAGE_SIZE);
-
- return ret;
-
+ return gic_hw_ops->gicv_setup(d);
}
static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
@@ -986,18 +577,10 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r
void gic_dump_info(struct vcpu *v)
{
- int i;
struct pending_irq *p;
printk("GICH_LRs (vcpu %d) mask=%"PRIx64"\n", v->vcpu_id, v->arch.lr_mask);
- if ( v == current )
- {
- for ( i = 0; i < nr_lrs; i++ )
- printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
- } else {
- for ( i = 0; i < nr_lrs; i++ )
- printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
- }
+ gic_hw_ops->dump_state(v);
list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight )
{
@@ -1008,12 +591,11 @@ void gic_dump_info(struct vcpu *v)
{
printk("Pending irq=%d\n", p->irq);
}
-
}
void __cpuinit init_maintenance_interrupt(void)
{
- request_irq(gic.maintenance_irq, 0, maintenance_interrupt,
+ request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_interrupt,
"irq-maintenance", NULL);
}
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 7fa3b95..9a85633 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -114,24 +114,6 @@
#define GICH_MISR_VGRP1E (1 << 6)
#define GICH_MISR_VGRP1D (1 << 7)
-#define GICH_LR_VIRTUAL_MASK 0x3ff
-#define GICH_LR_VIRTUAL_SHIFT 0
-#define GICH_LR_PHYSICAL_MASK 0x3ff
-#define GICH_LR_PHYSICAL_SHIFT 10
-#define GICH_LR_STATE_MASK 0x3
-#define GICH_LR_STATE_SHIFT 28
-#define GICH_LR_PRIORITY_SHIFT 23
-#define GICH_LR_MAINTENANCE_IRQ (1<<19)
-#define GICH_LR_PENDING (1<<28)
-#define GICH_LR_ACTIVE (1<<29)
-#define GICH_LR_GRP1 (1<<30)
-#define GICH_LR_HW (1<<31)
-#define GICH_LR_CPUID_SHIFT 9
-#define GICH_VTR_NRLRGS 0x3f
-
-#define GICH_VMCR_PRIORITY_MASK 0x1f
-#define GICH_VMCR_PRIORITY_SHIFT 27
-
/*
* The minimum GICC_BPR is required to be in the range 0-3. We set
* GICC_BPR to 0 but we must expect that it might be 3. This means we
@@ -155,6 +137,8 @@
#define GIC_PRI_TO_GUEST(pri) (pri >> 3) /* GICH_LR and GICH_VMCR only support
5 bits for guest irq priority */
+#define GICH_LR_PENDING 1
+#define GICH_LR_ACTIVE 2
#ifndef __ASSEMBLY__
#include <xen/device_tree.h>
@@ -163,6 +147,28 @@
#define DT_MATCH_GIC DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), \
DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
+/*
+ * Decode LR register content.
+ * The LR register format is different for GIC HW version
+ */
+struct gic_lr {
+ /* Physical IRQ */
+ uint32_t pirq;
+ /* Virtual IRQ */
+ uint32_t virq;
+ uint8_t priority;
+ uint8_t state;
+ uint8_t hw_status;
+ uint8_t grp;
+};
+
+enum gic_version {
+ GIC_V2,
+};
+
+extern enum gic_version gic_hw_version(void);
+extern void gicv2_init(void);
+
extern int domain_vgic_init(struct domain *d);
extern void domain_vgic_free(struct domain *d);
@@ -234,6 +240,71 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
unsigned int *out_hwirq, unsigned int *out_type);
void gic_clear_lrs(struct vcpu *v);
+struct gic_info {
+ /* GIC version */
+ enum gic_version hw_version;
+ /* Number of GIC lines supported */
+ unsigned int nr_lines;
+ /* Number of LR registers */
+ uint8_t nr_lrs;
+ /* Maintenance irq number */
+ unsigned int maintenance_irq;
+};
+
+struct gic_hw_operations {
+ /* Hold GIC HW information */
+ const struct gic_info *info;
+ /* Save GIC registers */
+ void (*save_state)(struct vcpu *);
+ /* Restore GIC registers */
+ void (*restore_state)(const struct vcpu *);
+ /* Dump GIC LR register information */
+ void (*dump_state)(const struct vcpu *);
+ /* Map MMIO region of GIC */
+ int (*gicv_setup)(struct domain *);
+
+ /* hw_irq_controller to enable/disable/eoi host irq */
+ hw_irq_controller *gic_host_irq_type;
+
+ /* hw_irq_controller to enable/disable/eoi guest irq */
+ hw_irq_controller *gic_guest_irq_type;
+
+ /* End of Interrupt */
+ void (*eoi_irq)(struct irq_desc *irqd);
+ /* Deactivate/reduce priority of irq */
+ void (*deactivate_irq)(struct irq_desc *irqd);
+ /* Read IRQ id and Ack */
+ unsigned int (*read_irq)(void);
+ /* Set IRQ property */
+ void (*set_irq_properties)(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority);
+ /* Send SGI */
+ void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
+ const cpumask_t *online_mask);
+ /* Disable CPU physical and virtual interfaces */
+ void (*disable_interface)(void);
+ /* Update LR register with state and priority */
+ void (*update_lr)(int lr, const struct pending_irq *pending_irq,
+ unsigned int state);
+ /* Update HCR status register */
+ void (*update_hcr_status)(uint32_t flag, bool_t set);
+ /* Clear LR register */
+ void (*clear_lr)(int lr);
+ /* Read LR register and populate gic_lr structure */
+ void (*read_lr)(int lr, struct gic_lr *);
+ /* Write LR register from gic_lr structure */
+ void (*write_lr)(int lr, const struct gic_lr *);
+ /* Read VMCR priority */
+ unsigned int (*read_vmcr_priority)(void);
+ /* Read APRn register */
+ unsigned int (*read_apr)(int apr_reg);
+ /* Secondary CPU init */
+ int (*secondary_init)(void);
+};
+
+void register_gic_ops(const struct gic_hw_operations *ops);
+
#endif /* __ASSEMBLY__ */
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (5 preceding siblings ...)
2014-06-26 5:33 ` [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality vijay.kilari
@ 2014-06-26 5:33 ` vijay.kilari
2014-06-26 12:26 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 08/17] xen/arm: use device api to detect GIC version vijay.kilari
` (10 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:33 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
arch_domain in domain.h defines all the GIC registers
that needs to be saved/restored directly.
These GIC registers are GIC HW version specific. The number
of registers and size of registers varies with GIC version.
So move these registers to gic.h file and make a union of these
registers. This helps to define GIC HW version specific
structure to this union for later GIC versions.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/gic-v2.c | 14 +++++++-------
xen/include/asm-arm/domain.h | 5 +++--
xen/include/asm-arm/gic.h | 18 ++++++++++++++++++
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index fb579d2..66e11eb 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -111,10 +111,10 @@ static void gicv2_save_state(struct vcpu *v)
* accessed simultaneously by another pCPU.
*/
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
+ v->arch.gic.v2.lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
- v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
- v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
+ v->arch.gic.v2.apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic.v2.vmcr = readl_relaxed(GICH + GICH_VMCR);
/* Disable until next VCPU scheduled */
writel_relaxed(0, GICH + GICH_HCR);
}
@@ -124,10 +124,10 @@ static void gicv2_restore_state(const struct vcpu *v)
int i;
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+ writel_relaxed(v->arch.gic.v2.lr[i], GICH + GICH_LR + i * 4);
- writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
- writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(v->arch.gic.v2.apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic.v2.vmcr, GICH + GICH_VMCR);
writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
}
@@ -144,7 +144,7 @@ static void gicv2_dump_state(const struct vcpu *v)
else
{
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic.v2.lr[i]);
}
}
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 046362c..bfd462c 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -8,6 +8,7 @@
#include <asm/p2m.h>
#include <asm/vfp.h>
#include <asm/mmio.h>
+#include <asm/gic.h>
#include <public/hvm/params.h>
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
@@ -263,8 +264,8 @@ struct arch_vcpu
uint32_t csselr;
register_t vmpidr;
- uint32_t gic_hcr, gic_vmcr, gic_apr;
- uint32_t gic_lr[64];
+ /* Holds gic context data */
+ union gic_state_data gic;
uint64_t lr_mask;
struct {
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 9a85633..a3c5f3d 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -148,6 +148,24 @@
DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
/*
+ * GICv2 register that needs to be saved/restored
+ * on VCPU context switch
+ */
+struct gic_v2 {
+ uint32_t hcr;
+ uint32_t vmcr;
+ uint32_t apr;
+ uint32_t lr[64];
+};
+
+/*
+ * Union to hold underlying hw version context information
+ */
+union gic_state_data {
+ struct gic_v2 v2;
+};
+
+/*
* Decode LR register content.
* The LR register format is different for GIC HW version
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 08/17] xen/arm: use device api to detect GIC version
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (6 preceding siblings ...)
2014-06-26 5:33 ` [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 12:29 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 09/17] xen/arm: switch to dynamic allocation of vgic rank vijay.kilari
` (9 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Run through the device tree to detect
compatible GIC version and initialize GIC driver
Also change DT_MATCH_GIC to DT_MATCH_GIC_V2 to point
the GIC HW version to add later GIC versions
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/domain_build.c | 2 +-
xen/arch/arm/gic-v2.c | 27 ++++++++++++++++-----------
xen/arch/arm/gic.c | 25 ++++++++++++++++++++++++-
xen/include/asm-arm/device.h | 1 +
xen/include/asm-arm/gic.h | 9 +++++----
5 files changed, 47 insertions(+), 17 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 9d9cba9..8c850ca 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -804,7 +804,7 @@ static int handle_node(struct domain *d, struct kernel_info *kinfo,
};
static const struct dt_device_match gic_matches[] __initconst =
{
- DT_MATCH_GIC,
+ DT_MATCH_GIC_V2,
{ /* sentinel */ },
};
static const struct dt_device_match timer_matches[] __initconst =
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 66e11eb..981ae2e 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -30,6 +30,7 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
+#include <asm/device.h>
#include <asm/io.h>
#include <asm/gic.h>
@@ -592,20 +593,10 @@ const static struct gic_hw_operations gicv2_ops = {
};
/* Set up the GIC */
-void __init gicv2_init(void)
+static int __init gicv2_init(struct dt_device_node *node, const void *data)
{
- static const struct dt_device_match gic_ids[] __initconst =
- {
- DT_MATCH_GIC,
- { /* sentinel */ },
- };
- struct dt_device_node *node;
int res;
- node = dt_find_interrupt_controller(gic_ids);
- if ( !node )
- panic("GICv2: Unable to find compatible GIC in the device tree");
-
dt_device_set_used_by(node, DOMID_XEN);
res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
@@ -675,8 +666,22 @@ void __init gicv2_init(void)
gicv2_info.hw_version = GIC_V2;
register_gic_ops(&gicv2_ops);
+
+ return 0;
}
+static const char * const gicv2_dt_compat[] __initconst =
+{
+ DT_COMPAT_GIC_CORTEX_A15,
+ DT_COMPAT_GIC_CORTEX_A7,
+ NULL
+};
+
+DT_DEVICE_START(gicv2, "GICv2:", DEVICE_GIC)
+ .compatible = gicv2_dt_compat,
+ .init = gicv2_init,
+DT_DEVICE_END
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 49b9360..4746f89 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -30,6 +30,7 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
+#include <asm/device.h>
#include <asm/io.h>
#include <asm/gic.h>
@@ -164,7 +165,29 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
/* Set up the GIC */
void __init gic_init(void)
{
- gicv2_init();
+ int rc;
+ struct dt_device_node *node;
+ bool_t num_gics = 0;
+
+ dt_for_each_device_node( dt_host, node )
+ {
+ if ( !dt_get_property(node, "interrupt-controller", NULL) )
+ continue;
+
+ if ( !dt_get_parent(node) )
+ continue;
+
+ rc = device_init(node, DEVICE_GIC, NULL);
+ if ( !rc )
+ {
+ /* NOTE: Only one GIC is supported */
+ num_gics = 1;
+ break;
+ }
+ }
+ if ( !num_gics )
+ panic("Unable to find compatible GIC in the device tree");
+
/* Update cpu lr mask for cpu0 */
update_cpu_lr_mask();
}
diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h
index 60109cc..74a80c6 100644
--- a/xen/include/asm-arm/device.h
+++ b/xen/include/asm-arm/device.h
@@ -8,6 +8,7 @@ enum device_type
{
DEVICE_SERIAL,
DEVICE_IOMMU,
+ DEVICE_GIC,
/* Use for error */
DEVICE_UNKNOWN,
};
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index a3c5f3d..5ff4477 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -144,8 +144,11 @@
#include <xen/device_tree.h>
#include <xen/irq.h>
-#define DT_MATCH_GIC DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), \
- DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
+#define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic"
+#define DT_COMPAT_GIC_CORTEX_A7 "arm,cortex-a7-gic"
+
+#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
+ DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7)
/*
* GICv2 register that needs to be saved/restored
@@ -185,8 +188,6 @@ enum gic_version {
};
extern enum gic_version gic_hw_version(void);
-extern void gicv2_init(void);
-
extern int domain_vgic_init(struct domain *d);
extern void domain_vgic_free(struct domain *d);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 09/17] xen/arm: switch to dynamic allocation of vgic rank
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (7 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 08/17] xen/arm: use device api to detect GIC version vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 5:34 ` [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
` (8 subsequent siblings)
17 siblings, 0 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
vgic_irq_rank structure contains gic specific data elements.
Move this out of domain.h to new vgic header file vgic.h
Allocate memory dynamically in vgic driver.
This patch reduces the size of domain struct and helps to
keep domain struct within PAGE_SIZE when future GIC hw versions
are added
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/domain.c | 2 ++
xen/arch/arm/vgic.c | 18 ++++++++++++++----
xen/include/asm-arm/domain.h | 11 +----------
xen/include/asm-arm/vgic.h | 40 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 01d2fd9..5ed3b55 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -31,6 +31,7 @@
#include <asm/procinfo.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/platform.h>
#include "vtimer.h"
#include "vuart.h"
@@ -485,6 +486,7 @@ fail:
void vcpu_destroy(struct vcpu *v)
{
vcpu_timer_destroy(v);
+ vcpu_vgic_free(v);
free_xenheap_pages(v->arch.stack, STACK_ORDER);
}
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 139c2e9..088ded3 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -29,6 +29,7 @@
#include <asm/mmio.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#define REG(n) (n)
@@ -69,7 +70,7 @@ static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n)
int rank = REG_RANK_NR(b, (n >> 2));
if ( rank == 0 )
- return &v->arch.vgic.private_irqs;
+ return v->arch.vgic.private_irqs;
else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
return &v->domain->arch.vgic.shared_irqs[rank - 1];
else
@@ -139,9 +140,12 @@ void domain_vgic_free(struct domain *d)
int vcpu_vgic_init(struct vcpu *v)
{
int i;
- memset(&v->arch.vgic.private_irqs, 0, sizeof(v->arch.vgic.private_irqs));
- spin_lock_init(&v->arch.vgic.private_irqs.lock);
+ v->arch.vgic.private_irqs = xzalloc(struct vgic_irq_rank);
+ if ( v->arch.vgic.private_irqs == NULL )
+ return -ENOMEM;
+
+ spin_lock_init(&v->arch.vgic.private_irqs->lock);
memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs));
for (i = 0; i < 32; i++)
@@ -152,7 +156,7 @@ int vcpu_vgic_init(struct vcpu *v)
/* For SGI and PPI the target is always this CPU */
for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs.itargets[i] =
+ v->arch.vgic.private_irqs->itargets[i] =
(1<<(v->vcpu_id+0))
| (1<<(v->vcpu_id+8))
| (1<<(v->vcpu_id+16))
@@ -164,6 +168,12 @@ int vcpu_vgic_init(struct vcpu *v)
return 0;
}
+int vcpu_vgic_free(struct vcpu *v)
+{
+ xfree(v->arch.vgic.private_irqs);
+ return 0;
+}
+
#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index bfd462c..077ac1e 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -13,15 +13,6 @@
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
-/* Represents state corresponding to a block of 32 interrupts */
-struct vgic_irq_rank {
- spinlock_t lock; /* Covers access to all other members of this struct */
- uint32_t ienable, iactive, ipend, pendsgi;
- uint32_t icfg[2];
- uint32_t ipriority[8];
- uint32_t itargets[8];
-};
-
struct pending_irq
{
/*
@@ -274,7 +265,7 @@ struct arch_vcpu
* struct arch_domain.
*/
struct pending_irq pending_irqs[32];
- struct vgic_irq_rank private_irqs;
+ struct vgic_irq_rank *private_irqs;
/* This list is ordered by IRQ priority and it is used to keep
* track of the IRQs that the VGIC injected into the guest.
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
new file mode 100644
index 0000000..0fd5b41
--- /dev/null
+++ b/xen/include/asm-arm/vgic.h
@@ -0,0 +1,40 @@
+/*
+ * ARM Virtual Generic Interrupt Controller support
+ *
+ * Ian Campbell <ian.campbell@citrix.com>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_VGIC_H__
+#define __ASM_ARM_VGIC_H__
+
+/* Represents state corresponding to a block of 32 interrupts */
+struct vgic_irq_rank {
+ spinlock_t lock; /* Covers access to all other members of this struct */
+ uint32_t ienable, iactive, ipend, pendsgi;
+ uint32_t icfg[2];
+ uint32_t ipriority[8];
+ uint32_t itargets[8];
+};
+
+extern int vcpu_vgic_free(struct vcpu *v);
+#endif /* __ASM_ARM_VGIC_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (8 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 09/17] xen/arm: switch to dynamic allocation of vgic rank vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 12:37 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file vijay.kilari
` (7 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
prefix byte_read and byte_write vgic functions with vgic_
to make these function vgic specific.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/vgic.c | 30 +++++++++++++++++-------------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 088ded3..d01f1d9 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -180,7 +180,7 @@ int vcpu_vgic_free(struct vcpu *v)
#define vgic_lock_rank(v, r) spin_lock(&(r)->lock)
#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock)
-static uint32_t byte_read(uint32_t val, int sign, int offset)
+static uint32_t vgic_byte_read(uint32_t val, int sign, int offset)
{
int byte = offset & 0x3;
@@ -192,7 +192,7 @@ static uint32_t byte_read(uint32_t val, int sign, int offset)
return val;
}
-static void byte_write(uint32_t *reg, uint32_t var, int offset)
+static void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
{
int byte = offset & 0x3;
@@ -267,7 +267,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -276,7 +276,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -306,7 +306,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_lock_rank(v, rank);
*r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)];
if ( dabt.size == 0 )
- *r = byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -318,7 +318,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_lock_rank(v, rank);
*r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)];
if ( dabt.size == 0 )
- *r = byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -346,7 +346,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -355,7 +355,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -618,8 +618,10 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( dabt.size == 2 )
rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
else
- byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
- *r, offset);
+ {
+ tr = REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR);
+ vgic_byte_write(&rank->itargets[tr], *r, offset);
+ }
vgic_unlock_rank(v, rank);
return 1;
@@ -631,8 +633,10 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( dabt.size == 2 )
rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
else
- byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
- *r, offset);
+ {
+ tr = REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR);
+ vgic_byte_write(&rank->ipriority[tr], *r, offset);
+ }
vgic_unlock_rank(v, rank);
return 1;
@@ -757,7 +761,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
+ priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (9 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 12:40 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h vijay.kilari
` (6 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic.h contains defines of vgic. Move these to vgic
header file. Also move inline functions and defines/macros
in vgic.c to vgic.h. These vgic functions and macros
can be used by other GIC HW specific VGIC drivers,
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/irq.c | 1 +
xen/arch/arm/time.c | 1 +
xen/arch/arm/vgic.c | 53 --------------------------------------
xen/arch/arm/vpsci.c | 1 +
xen/arch/arm/vtimer.c | 1 +
xen/include/asm-arm/gic.h | 7 -----
xen/include/asm-arm/vgic.h | 61 ++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 65 insertions(+), 60 deletions(-)
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 9c141bc..3a8acbf 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -26,6 +26,7 @@
#include <xen/sched.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
static unsigned int local_irqs_type[NR_LOCAL_IRQS];
static DEFINE_SPINLOCK(local_irqs_type_lock);
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index 06cc709..4c3e1a6 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -32,6 +32,7 @@
#include <asm/system.h>
#include <asm/time.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/cpufeature.h>
#include <asm/platform.h>
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index d01f1d9..96bd7c1 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -33,35 +33,10 @@
#define REG(n) (n)
-/* Number of ranks of interrupt registers for a domain */
-#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
/*
- * Rank containing GICD_<FOO><n> for GICD_<FOO> with
- * <b>-bits-per-interrupt
- */
-static inline int REG_RANK_NR(int b, uint32_t n)
-{
- switch ( b )
- {
- case 8: return n >> 3;
- case 4: return n >> 2;
- case 2: return n >> 1;
- case 1: return n;
- default: BUG();
- }
-}
-
-/*
- * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
- * <b>-bits-per-interrupt.
- */
-#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
-
-/*
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
@@ -174,34 +149,6 @@ int vcpu_vgic_free(struct vcpu *v)
return 0;
}
-#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
-#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
-
-#define vgic_lock_rank(v, r) spin_lock(&(r)->lock)
-#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock)
-
-static uint32_t vgic_byte_read(uint32_t val, int sign, int offset)
-{
- int byte = offset & 0x3;
-
- val = val >> (8*byte);
- if ( sign && (val & 0x80) )
- val |= 0xffffff00;
- else
- val &= 0x000000ff;
- return val;
-}
-
-static void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
-{
- int byte = offset & 0x3;
-
- var &= (0xff << (8*byte));
-
- *reg &= ~(0xff << (8*byte));
- *reg |= var;
-}
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
{
struct hsr_dabt dabt = info->dabt;
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 1ceb8cb..80678f6 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -16,6 +16,7 @@
#include <asm/current.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/psci.h>
int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c
index c268873..690657b 100644
--- a/xen/arch/arm/vtimer.c
+++ b/xen/arch/arm/vtimer.c
@@ -24,6 +24,7 @@
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/regs.h>
extern s_time_t ticks_to_ns(uint64_t ticks);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 5ff4477..ed610cb 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -188,13 +188,6 @@ enum gic_version {
};
extern enum gic_version gic_hw_version(void);
-extern int domain_vgic_init(struct domain *d);
-extern void domain_vgic_free(struct domain *d);
-
-extern int vcpu_vgic_init(struct vcpu *v);
-
-extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
-extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
/* Program the GIC to route an interrupt */
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 0fd5b41..92f1e86 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -18,6 +18,8 @@
#ifndef __ASM_ARM_VGIC_H__
#define __ASM_ARM_VGIC_H__
+#include <xen/bitops.h>
+
/* Represents state corresponding to a block of 32 interrupts */
struct vgic_irq_rank {
spinlock_t lock; /* Covers access to all other members of this struct */
@@ -27,6 +29,65 @@ struct vgic_irq_rank {
uint32_t itargets[8];
};
+/* Number of ranks of interrupt registers for a domain */
+#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
+
+#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
+#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
+
+#define vgic_lock_rank(v, r) spin_lock(&(r)->lock)
+#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock)
+
+/*
+ * Rank containing GICD_<FOO><n> for GICD_<FOO> with
+ * <b>-bits-per-interrupt
+ */
+static inline int REG_RANK_NR(int b, uint32_t n)
+{
+ switch ( b )
+ {
+ case 8: return n >> 3;
+ case 4: return n >> 2;
+ case 2: return n >> 1;
+ case 1: return n;
+ default: BUG();
+ }
+}
+
+static inline uint32_t vgic_byte_read(uint32_t val, int sign, int offset)
+{
+ int byte = offset & 0x3;
+
+ val = val >> (8*byte);
+ if ( sign && (val & 0x80) )
+ val |= 0xffffff00;
+ else
+ val &= 0x000000ff;
+ return val;
+}
+
+static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
+{
+ int byte = offset & 0x3;
+
+ var &= (0xff << (8*byte));
+
+ *reg &= ~(0xff << (8*byte));
+ *reg |= var;
+}
+
+/*
+ * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
+ * <b>-bits-per-interrupt.
+ */
+#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
+
+extern int domain_vgic_init(struct domain *d);
+extern void domain_vgic_free(struct domain *d);
+extern int vcpu_vgic_init(struct vcpu *v);
+extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
+extern void vgic_clear_pending_irqs(struct vcpu *v);
+
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (10 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 9:41 ` Jan Beulich
2014-06-26 5:34 ` [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file vijay.kilari
` (5 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: keir, vijay.kilari, Prasun.Kapoor, Vijaya Kumar K, george.dunlap,
jbeulich
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
is_vcpu_running function in vgic driver is generic. So move
this to sched.h and rename it as is_vcpu_online
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
CC: jbeulich@suse.com
CC: keir@xen.org
CC: george.dunlap@citrix.com
---
xen/arch/arm/vgic.c | 20 ++------------------
xen/include/xen/sched.h | 16 ++++++++++++++++
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 96bd7c1..d29474b 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -405,22 +405,6 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static inline int is_vcpu_running(struct domain *d, int vcpuid)
-{
- struct vcpu *v;
-
- if ( vcpuid >= d->max_vcpus )
- return 0;
-
- v = d->vcpu[vcpuid];
- if ( v == NULL )
- return 0;
- if (test_bit(_VPF_down, &v->pause_flags) )
- return 0;
-
- return 1;
-}
-
static int vgic_to_sgi(struct vcpu *v, register_t sgir)
{
struct domain *d = v->domain;
@@ -444,7 +428,7 @@ static int vgic_to_sgi(struct vcpu *v, register_t sgir)
case GICD_SGI_TARGET_OTHERS:
for ( i = 0; i < d->max_vcpus; i++ )
{
- if ( i != current->vcpu_id && is_vcpu_running(d, i) )
+ if ( i != current->vcpu_id && is_vcpu_online(d, i) )
set_bit(i, &vcpu_mask);
}
break;
@@ -459,7 +443,7 @@ static int vgic_to_sgi(struct vcpu *v, register_t sgir)
for_each_set_bit( vcpuid, &vcpu_mask, d->max_vcpus )
{
- if ( !is_vcpu_running(d, vcpuid) )
+ if ( !is_vcpu_online(d, vcpuid) )
{
gdprintk(XENLOG_WARNING, "vGICD: GICD_SGIR write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
sgir, vcpu_mask);
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index f920e1a..9750f33 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -829,6 +829,22 @@ void watchdog_domain_destroy(struct domain *d);
#define need_iommu(d) (0)
#endif
+static inline bool_t is_vcpu_online(const struct domain *d, int vcpuid)
+{
+ const struct vcpu *v;
+
+ if ( vcpuid >= d->max_vcpus || d->vcpu == NULL )
+ return 0;
+
+ v = d->vcpu[vcpuid];
+ if ( v == NULL )
+ return 0;
+ if ( test_bit(_VPF_down, &v->pause_flags) )
+ return 0;
+
+ return 1;
+}
+
void set_vcpu_migration_delay(unsigned int delay);
unsigned int get_vcpu_migration_delay(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (11 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 12:46 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size vijay.kilari
` (4 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic.h requires definition of pending_irq structure defined
in domain.h and domain.h requires gic_state structure defined
in gic.h and hence there is inter-dependency between domain.h
and gic.h files.
So move pending_irq to vgic.h which is relevant place for this
structure and break domain.h and gic.h interdependency
By this move irq_to_pending function declaration from gic.h
to vgic.h
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/include/asm-arm/domain.h | 57 -----------------------------------------
xen/include/asm-arm/gic.h | 2 +-
xen/include/asm-arm/vgic.h | 58 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 59 insertions(+), 58 deletions(-)
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 077ac1e..2a1e976 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -13,63 +13,6 @@
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
-struct pending_irq
-{
- /*
- * The following two states track the lifecycle of the guest irq.
- * However because we are not sure and we don't want to track
- * whether an irq added to an LR register is PENDING or ACTIVE, the
- * following states are just an approximation.
- *
- * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
- * injection into the guest's LRs.
- *
- * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
- * therefore the guest is aware of it. From the guest point of view
- * the irq can be pending (if the guest has not acked the irq yet)
- * or active (after acking the irq).
- *
- * In order for the state machine to be fully accurate, for level
- * interrupts, we should keep the interrupt's pending state until
- * the guest deactivates the irq. However because we are not sure
- * when that happens, we instead track whether there is an interrupt
- * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
- * an LR register. We set it when we receive another interrupt
- * notification. Therefore it is possible to set
- * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
- * could also change the state of the guest irq in the LR register
- * from active to active and pending, but for simplicity we simply
- * inject a second irq after the guest EOIs the first one.
- *
- *
- * An additional state is used to keep track of whether the guest
- * irq is enabled at the vgicd level:
- *
- * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
- * level (GICD_ICENABLER/GICD_ISENABLER).
- *
- */
-#define GIC_IRQ_GUEST_QUEUED 0
-#define GIC_IRQ_GUEST_ACTIVE 1
-#define GIC_IRQ_GUEST_VISIBLE 2
-#define GIC_IRQ_GUEST_ENABLED 3
- unsigned long status;
- struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */
- int irq;
-#define GIC_INVALID_LR ~(uint8_t)0
- uint8_t lr;
- uint8_t priority;
- /* inflight is used to append instances of pending_irq to
- * vgic.inflight_irqs */
- struct list_head inflight;
- /* lr_queue is used to append instances of pending_irq to
- * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
- * accesses are protected with the vgic lock.
- * TODO: when implementing irq migration, taking only the current
- * vgic lock is not going to be enough. */
- struct list_head lr_queue;
-};
-
struct hvm_domain
{
uint64_t params[HVM_NR_PARAMS];
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index ed610cb..875729e 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -143,6 +143,7 @@
#ifndef __ASSEMBLY__
#include <xen/device_tree.h>
#include <xen/irq.h>
+#include <asm-arm/vgic.h>
#define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic"
#define DT_COMPAT_GIC_CORTEX_A7 "arm,cortex-a7-gic"
@@ -188,7 +189,6 @@ enum gic_version {
};
extern enum gic_version gic_hw_version(void);
-extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
/* Program the GIC to route an interrupt */
extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask,
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 92f1e86..003c3e9 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,63 @@
#include <xen/bitops.h>
+struct pending_irq
+{
+ /*
+ * The following two states track the lifecycle of the guest irq.
+ * However because we are not sure and we don't want to track
+ * whether an irq added to an LR register is PENDING or ACTIVE, the
+ * following states are just an approximation.
+ *
+ * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
+ * injection into the guest's LRs.
+ *
+ * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
+ * therefore the guest is aware of it. From the guest point of view
+ * the irq can be pending (if the guest has not acked the irq yet)
+ * or active (after acking the irq).
+ *
+ * In order for the state machine to be fully accurate, for level
+ * interrupts, we should keep the interrupt's pending state until
+ * the guest deactivates the irq. However because we are not sure
+ * when that happens, we instead track whether there is an interrupt
+ * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
+ * an LR register. We set it when we receive another interrupt
+ * notification. Therefore it is possible to set
+ * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
+ * could also change the state of the guest irq in the LR register
+ * from active to active and pending, but for simplicity we simply
+ * inject a second irq after the guest EOIs the first one.
+ *
+ *
+ * An additional state is used to keep track of whether the guest
+ * irq is enabled at the vgicd level:
+ *
+ * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
+ * level (GICD_ICENABLER/GICD_ISENABLER).
+ *
+ */
+#define GIC_IRQ_GUEST_QUEUED 0
+#define GIC_IRQ_GUEST_ACTIVE 1
+#define GIC_IRQ_GUEST_VISIBLE 2
+#define GIC_IRQ_GUEST_ENABLED 3
+ unsigned long status;
+ struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */
+ int irq;
+#define GIC_INVALID_LR ~(uint8_t)0
+ uint8_t lr;
+ uint8_t priority;
+ /* inflight is used to append instances of pending_irq to
+ * vgic.inflight_irqs */
+ struct list_head inflight;
+ /* lr_queue is used to append instances of pending_irq to
+ * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
+ * accesses are protected with the vgic lock.
+ * TODO: when implementing irq migration, taking only the current
+ * vgic lock is not going to be enough. */
+ struct list_head lr_queue;
+};
+
/* Represents state corresponding to a block of 32 interrupts */
struct vgic_irq_rank {
spinlock_t lock; /* Covers access to all other members of this struct */
@@ -87,6 +144,7 @@ extern void domain_vgic_free(struct domain *d);
extern int vcpu_vgic_init(struct vcpu *v);
extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
+extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (12 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 12:58 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 15/17] xen/arm: Remove REG macro in vgic driver vijay.kilari
` (3 subsequent siblings)
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
vGIC irq rank was computed assuming the register offset is byte
size.Use the HSR abort address size in calculating register size.
So, with this patch following are acheived
(1) In the code 'dabt.size != number' this number is always
BYTE/HALF_WORD/WORD/DOUBLE defined by hsr registers.
Instead of checking for hard coded values use HSR abort
address size values.
(2) The vgic_irq_rank also depends on the same HSR defined
values to calculate irq rank.
This make vgic_irq_rank generic as it takes register
size as parameter to calculate irq rank instead of hard coding to
value 2 in previous patches
Also, output of REG_RANK_INDEX macro is modulo by 32 to make
sure register index is always within irq rank
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/vgic.c | 139 ++++++++++++++++++++-------------------
xen/include/asm-arm/processor.h | 8 +++
xen/include/asm-arm/vgic.h | 4 +-
3 files changed, 83 insertions(+), 68 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index d29474b..ca9eeda 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -40,9 +40,10 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
-static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n)
+static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n,
+ int s)
{
- int rank = REG_RANK_NR(b, (n >> 2));
+ int rank = REG_RANK_NR(b, (n >> s));
if ( rank == 0 )
return v->arch.vgic.private_irqs;
@@ -54,7 +55,7 @@ static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n)
static struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
{
- return vgic_rank_offset(v, 8, irq);
+ return vgic_rank_offset(v, 8, irq, DABT_WORD);
}
static const struct mmio_handler_ops vgic_distr_mmio_handler = {
@@ -161,13 +162,13 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
switch ( gicd_reg )
{
case GICD_CTLR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
vgic_lock(v);
*r = v->domain->arch.vgic.ctlr;
vgic_unlock(v);
return 1;
case GICD_TYPER:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* No secure world support for guests. */
vgic_lock(v);
*r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
@@ -175,7 +176,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_unlock(v);
return 1;
case GICD_IIDR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/*
* XXX Do we need a JEP106 manufacturer ID?
* Just use the physical h/w value for now
@@ -192,8 +193,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->ienable;
@@ -201,8 +202,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->ienable;
@@ -210,8 +211,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->ipend, dabt.sign, offset);
@@ -219,8 +220,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->ipend, dabt.sign, offset);
@@ -228,8 +229,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->iactive;
@@ -237,8 +238,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->iactive;
@@ -246,35 +247,37 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ITARGETSR ... GICD_ITARGETSRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)];
- if ( dabt.size == 0 )
+ *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR);
+ if ( dabt.size != 0 && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)];
- if ( dabt.size == 0 )
+ *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
case GICD_ICFGR ... GICD_ICFGRN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR)];
+ *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
vgic_unlock_rank(v, rank);
return 1;
@@ -283,14 +286,14 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_SGIR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* Write only -- read unknown */
*r = 0xdeadbeef;
return 1;
case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
@@ -298,8 +301,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
@@ -311,7 +314,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_ICPIDR2:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled read from ICPIDR2\n");
return 0;
@@ -341,7 +344,7 @@ bad_width:
return 0;
read_as_zero:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
*r = 0;
return 1;
}
@@ -467,7 +470,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
switch ( gicd_reg )
{
case GICD_CTLR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* Ignore all but the enable bit */
v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
return 1;
@@ -486,42 +489,44 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
tr = rank->ienable;
rank->ienable |= *r;
vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
+ vgic_enable_irqs(v, (*r) & (~tr),
+ (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
tr = rank->ienable;
rank->ienable &= ~*r;
vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
+ vgic_disable_irqs(v, (*r) & tr,
+ (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
return 0;
case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
return 0;
case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
rank->iactive &= ~*r;
@@ -529,8 +534,8 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
rank->iactive &= ~*r;
@@ -542,30 +547,32 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- if ( dabt.size == 2 )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
+ if ( dabt.size == DABT_WORD )
+ rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)] = *r;
else
{
- tr = REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR);
+ tr = REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
vgic_byte_write(&rank->itargets[tr], *r, offset);
}
vgic_unlock_rank(v, rank);
return 1;
case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- if ( dabt.size == 2 )
- rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
else
{
- tr = REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR);
+ tr = REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
vgic_byte_write(&rank->ipriority[tr], *r, offset);
}
vgic_unlock_rank(v, rank);
@@ -577,11 +584,11 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
/* It is implementation defined if these are writeable. We chose not */
goto write_ignore;
case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR)] = *r;
+ rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
vgic_unlock_rank(v, rank);
return 1;
@@ -595,13 +602,13 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return vgic_to_sgi(v, *r);
case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
return 0;
case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
return 0;
@@ -640,7 +647,7 @@ bad_width:
return 0;
write_ignore:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
return 1;
}
@@ -692,7 +699,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
+ priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq, DABT_WORD)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index ebc683d..22a1998 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -251,6 +251,14 @@ extern struct cpuinfo_arm cpu_data[];
extern u32 __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
+/* HSR data abort size definition */
+enum dabt_size {
+ DABT_BYTE = 0,
+ DABT_HALF_WORD = 1,
+ DABT_WORD = 2,
+ DABT_DOUBLE_WORD = 3,
+};
+
union hsr {
uint32_t bits;
struct {
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 003c3e9..7c71d16 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -134,10 +134,10 @@ static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
}
/*
- * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
+ * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> size <s> with
* <b>-bits-per-interrupt.
*/
-#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
+#define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32)
extern int domain_vgic_init(struct domain *d);
extern void domain_vgic_free(struct domain *d);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 15/17] xen/arm: Remove REG macro in vgic driver
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (13 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 5:34 ` [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
` (2 subsequent siblings)
17 siblings, 0 replies; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
REG macro does not compute any value and offset
variable is no more required. Hence removed
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/vgic.c | 68 ++++++++++++++++++++++++---------------------------
1 file changed, 32 insertions(+), 36 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index ca9eeda..78004b0 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -31,8 +31,6 @@
#include <asm/gic.h>
#include <asm/vgic.h>
-#define REG(n) (n)
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
@@ -156,8 +154,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
struct cpu_user_regs *regs = guest_cpu_user_regs();
register_t *r = select_user_reg(regs, dabt.reg);
struct vgic_irq_rank *rank;
- int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
- int gicd_reg = REG(offset);
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
switch ( gicd_reg )
{
@@ -185,7 +182,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
/* Implementation defined -- read as zero */
- case REG(0x020) ... REG(0x03c):
+ case 0x020 ... 0x03c:
goto read_as_zero;
case GICD_IGROUPR ... GICD_IGROUPRN:
@@ -215,7 +212,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -224,7 +221,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -255,7 +252,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
*r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -268,7 +265,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
*r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -296,7 +293,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -305,12 +302,12 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
/* Implementation defined -- read as zero */
- case REG(0xfd0) ... REG(0xfe4):
+ case 0xfd0 ... 0xfe4:
goto read_as_zero;
case GICD_ICPIDR2:
@@ -319,27 +316,27 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 0;
/* Implementation defined -- read as zero */
- case REG(0xfec) ... REG(0xffc):
+ case 0xfec ... 0xffc:
goto read_as_zero;
/* Reserved -- read as zero */
- case REG(0x00c) ... REG(0x01c):
- case REG(0x040) ... REG(0x07c):
- case REG(0x7fc):
- case REG(0xbfc):
- case REG(0xf04) ... REG(0xf0c):
- case REG(0xf30) ... REG(0xfcc):
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
goto read_as_zero;
default:
printk("vGICD: unhandled read r%d offset %#08x\n",
- dabt.reg, offset);
+ dabt.reg, gicd_reg);
return 0;
}
bad_width:
printk("vGICD: bad read width %d r%d offset %#08x\n",
- dabt.size, dabt.reg, offset);
+ dabt.size, dabt.reg, gicd_reg);
domain_crash_synchronous();
return 0;
@@ -463,8 +460,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
struct cpu_user_regs *regs = guest_cpu_user_regs();
register_t *r = select_user_reg(regs, dabt.reg);
struct vgic_irq_rank *rank;
- int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
- int gicd_reg = REG(offset);
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
uint32_t tr;
switch ( gicd_reg )
@@ -481,7 +477,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
/* Implementation defined -- write ignored */
- case REG(0x020) ... REG(0x03c):
+ case 0x020 ... 0x03c:
goto write_ignore;
case GICD_IGROUPR ... GICD_IGROUPRN:
@@ -557,7 +553,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
else
{
tr = REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- vgic_byte_write(&rank->itargets[tr], *r, offset);
+ vgic_byte_write(&rank->itargets[tr], *r, gicd_reg);
}
vgic_unlock_rank(v, rank);
return 1;
@@ -573,7 +569,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
else
{
tr = REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- vgic_byte_write(&rank->ipriority[tr], *r, offset);
+ vgic_byte_write(&rank->ipriority[tr], *r, gicd_reg);
}
vgic_unlock_rank(v, rank);
return 1;
@@ -614,7 +610,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return 0;
/* Implementation defined -- write ignored */
- case REG(0xfd0) ... REG(0xfe4):
+ case 0xfd0 ... 0xfe4:
goto write_ignore;
/* R/O -- write ignore */
@@ -622,27 +618,27 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
/* Implementation defined -- write ignored */
- case REG(0xfec) ... REG(0xffc):
+ case 0xfec ... 0xffc:
goto write_ignore;
/* Reserved -- write ignored */
- case REG(0x00c) ... REG(0x01c):
- case REG(0x040) ... REG(0x07c):
- case REG(0x7fc):
- case REG(0xbfc):
- case REG(0xf04) ... REG(0xf0c):
- case REG(0xf30) ... REG(0xfcc):
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
goto write_ignore;
default:
printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
- dabt.reg, *r, offset);
+ dabt.reg, *r, gicd_reg);
return 0;
}
bad_width:
printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
- dabt.size, dabt.reg, *r, offset);
+ dabt.size, dabt.reg, *r, gicd_reg);
domain_crash_synchronous();
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (14 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 15/17] xen/arm: Remove REG macro in vgic driver vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 14:30 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain vijay.kilari
2014-06-27 13:40 ` [PATCH v6a 00/17] GIC and VGIC code refactoring Ian Campbell
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Existing vGIC driver has both generic code and hw specific
code. Segregate vGIC low level driver into vgic-v2.c and
keep generic code in existing vgic.c file
some static generic functions in vgic.c is made as non-static
so that these generic functions can be used in vGIC v2 driver.
vGIC v2 driver registers required callbacks to generic vGIC
driver. This helps to plug in next version of vGIC drivers
like vGIC v3. These callbacks are registered per domain
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/Makefile | 2 +-
xen/arch/arm/vgic-v2.c | 507 ++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 487 ++++------------------------------------
xen/include/asm-arm/domain.h | 2 +
xen/include/asm-arm/gic.h | 3 +
xen/include/asm-arm/vgic.h | 20 ++
6 files changed, 582 insertions(+), 439 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 969ee52..20f59f4 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -26,7 +26,7 @@ obj-y += smpboot.o
obj-y += smp.o
obj-y += shutdown.o
obj-y += traps.o
-obj-y += vgic.o
+obj-y += vgic.o vgic-v2.o
obj-y += vtimer.o
obj-y += vuart.o
obj-y += hvm.o
diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
new file mode 100644
index 0000000..3484d57
--- /dev/null
+++ b/xen/arch/arm/vgic-v2.c
@@ -0,0 +1,507 @@
+/*
+ * xen/arch/arm/vgic-v2.c
+ *
+ * ARM Virtual Generic Interrupt Controller support v2
+ *
+ * Ian Campbell <ian.campbell@citrix.com>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/bitops.h>
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/softirq.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+
+#include <asm/current.h>
+#include <asm/device.h>
+
+#include <asm/mmio.h>
+#include <asm/gic.h>
+#include <asm/vgic.h>
+
+static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vgic_lock(v);
+ *r = v->domain->arch.vgic.ctlr;
+ vgic_unlock(v);
+ return 1;
+ case GICD_TYPER:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* No secure world support for guests. */
+ vgic_lock(v);
+ *r = ( (v->domain->max_vcpus << 5) & GICD_TYPE_CPUS )
+ |( ((v->domain->arch.vgic.nr_lines / 32)) & GICD_TYPE_LINES );
+ vgic_unlock(v);
+ return 1;
+ case GICD_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /*
+ * XXX Do we need a JEP106 manufacturer ID?
+ * Just use the physical h/w value for now
+ */
+ *r = 0x0000043b;
+ return 1;
+
+ /* Implementation defined -- read as zero */
+ case 0x020 ... 0x03c:
+ goto read_as_zero;
+
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ITARGETSR ... GICD_ITARGETSRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICFGR ... GICD_ICFGRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+
+ case GICD_SGIR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Write only -- read unknown */
+ *r = 0xdeadbeef;
+ return 1;
+
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ /* Implementation defined -- read as zero */
+ case 0xfd0 ... 0xfe4:
+ goto read_as_zero;
+
+ case GICD_ICPIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled read from ICPIDR2\n");
+ return 0;
+
+ /* Implementation defined -- read as zero */
+ case 0xfec ... 0xffc:
+ goto read_as_zero;
+
+ /* Reserved -- read as zero */
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
+ goto read_as_zero;
+
+ default:
+ printk("vGICD: unhandled read r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICD: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v2_to_sgi(struct vcpu *v, register_t sgir)
+{
+
+ int virq;
+ int irqmode;
+ enum gic_sgi_mode sgi_mode;
+ unsigned long vcpu_mask = 0;
+
+ irqmode = (sgir & GICD_SGI_TARGET_LIST_MASK) >> GICD_SGI_TARGET_LIST_SHIFT;
+ virq = (sgir & GICD_SGI_INTID_MASK);
+ vcpu_mask = (sgir & GICD_SGI_TARGET_MASK) >> GICD_SGI_TARGET_SHIFT;
+
+ /* Map GIC sgi value to enum value */
+ switch ( irqmode )
+ {
+ case GICD_SGI_TARGET_LIST_VAL:
+ sgi_mode = SGI_TARGET_LIST;
+ break;
+ case GICD_SGI_TARGET_OTHERS_VAL:
+ sgi_mode = SGI_TARGET_OTHERS;
+ break;
+ case GICD_SGI_TARGET_SELF_VAL:
+ sgi_mode = SGI_TARGET_SELF;
+ break;
+ default:
+ BUG();
+ }
+
+ return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
+}
+
+static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+ uint32_t tr;
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Ignore all but the enable bit */
+ v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
+ return 1;
+
+ /* R/O -- write ignored */
+ case GICD_TYPER:
+ case GICD_IIDR:
+ goto write_ignore;
+
+ /* Implementation defined -- write ignored */
+ case 0x020 ... 0x03c:
+ goto write_ignore;
+
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable |= *r;
+ vgic_unlock_rank(v, rank);
+ /* The virtual irq is derived from register offset.
+ * The register difference is word difference. So divide by 2(DABT_WORD)
+ * to get Virtual irq number */
+ vgic_enable_irqs(v, (*r) & (~tr),
+ (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
+ return 1;
+
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable &= ~*r;
+ vgic_unlock_rank(v, rank);
+ /* The virtual irq is derived from register offset.
+ * The register difference is word difference. So divide by 2(DABT_WORD)
+ * to get Virtual irq number */
+ vgic_disable_irqs(v, (*r) & tr,
+ (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
+ return 1;
+
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
+ return 0;
+
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
+ return 0;
+
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ITARGETSR ... GICD_ITARGETSR + 7:
+ /* SGI/PPI target is read only */
+ goto write_ignore;
+
+ case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
+ gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
+ gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICFGR: /* SGIs */
+ goto write_ignore;
+ case GICD_ICFGR + 1: /* PPIs */
+ /* It is implementation defined if these are writeable. We chose not */
+ goto write_ignore;
+ case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+
+ case GICD_SGIR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return vgic_send_sgi(v, *r);
+
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
+ return 0;
+
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
+ return 0;
+
+ /* Implementation defined -- write ignored */
+ case 0xfd0 ... 0xfe4:
+ goto write_ignore;
+
+ /* R/O -- write ignore */
+ case GICD_ICPIDR2:
+ goto write_ignore;
+
+ /* Implementation defined -- write ignored */
+ case 0xfec ... 0xffc:
+ goto write_ignore;
+
+ /* Reserved -- write ignored */
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
+ goto write_ignore;
+
+ default:
+ printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
+ dabt.reg, *r, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+const struct mmio_handler_ops vgic_v2_distr_mmio_handler = {
+ .read_handler = vgic_v2_distr_mmio_read,
+ .write_handler = vgic_v2_distr_mmio_write,
+};
+
+static int vgic_v2_vcpu_init(struct vcpu *v)
+{
+ int i;
+
+ /* For SGI and PPI the target is always this CPU */
+ for ( i = 0 ; i < 8 ; i++ )
+ v->arch.vgic.private_irqs->itargets[i] =
+ (1<<(v->vcpu_id+0))
+ | (1<<(v->vcpu_id+8))
+ | (1<<(v->vcpu_id+16))
+ | (1<<(v->vcpu_id+24));
+
+ return 0;
+}
+
+static int vgic_v2_domain_init(struct domain *d)
+{
+ /* We rely on gicv_setup() to initialize dbase(vGIC distributor base) */
+ register_mmio_handler(d, &vgic_v2_distr_mmio_handler, d->arch.vgic.dbase,
+ PAGE_SIZE);
+
+ return 0;
+}
+
+const static struct vgic_ops vgic_v2_ops = {
+ .vcpu_init = vgic_v2_vcpu_init,
+ .domain_init = vgic_v2_domain_init,
+ .send_sgi = vgic_v2_to_sgi,
+};
+
+int vgic_v2_init(struct domain *d)
+{
+ register_vgic_ops(d, &vgic_v2_ops);
+
+ return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 78004b0..9f18347 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -31,14 +31,11 @@
#include <asm/gic.h>
#include <asm/vgic.h>
-static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
-static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
-
/*
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
-static struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n,
+struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n,
int s)
{
int rank = REG_RANK_NR(b, (n >> s));
@@ -56,11 +53,6 @@ static struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
return vgic_rank_offset(v, 8, irq, DABT_WORD);
}
-static const struct mmio_handler_ops vgic_distr_mmio_handler = {
- .read_handler = vgic_distr_mmio_read,
- .write_handler = vgic_distr_mmio_write,
-};
-
int domain_vgic_init(struct domain *d)
{
int i;
@@ -75,6 +67,15 @@ int domain_vgic_init(struct domain *d)
else
d->arch.vgic.nr_lines = 0; /* We don't need SPIs for the guest */
+ switch ( gic_hw_version() )
+ {
+ case GIC_V2:
+ vgic_v2_init(d);
+ break;
+ default:
+ return -ENODEV;
+ }
+
d->arch.vgic.shared_irqs =
xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_RANKS(d));
if ( d->arch.vgic.shared_irqs == NULL )
@@ -96,15 +97,16 @@ int domain_vgic_init(struct domain *d)
for (i=0; i<DOMAIN_NR_RANKS(d); i++)
spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
- /*
- * We rely on gicv_setup() to initialize dbase(vGIC distributor base)
- */
- register_mmio_handler(d, &vgic_distr_mmio_handler,
- d->arch.vgic.dbase, PAGE_SIZE);
+ d->arch.vgic.handler->domain_init(d);
return 0;
}
+void register_vgic_ops(struct domain *d, const struct vgic_ops *ops)
+{
+ d->arch.vgic.handler = ops;
+}
+
void domain_vgic_free(struct domain *d)
{
xfree(d->arch.vgic.shared_irqs);
@@ -121,6 +123,8 @@ int vcpu_vgic_init(struct vcpu *v)
spin_lock_init(&v->arch.vgic.private_irqs->lock);
+ v->domain->arch.vgic.handler->vcpu_init(v);
+
memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs));
for (i = 0; i < 32; i++)
{
@@ -128,13 +132,6 @@ int vcpu_vgic_init(struct vcpu *v)
INIT_LIST_HEAD(&v->arch.vgic.pending_irqs[i].lr_queue);
}
- /* For SGI and PPI the target is always this CPU */
- for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs->itargets[i] =
- (1<<(v->vcpu_id+0))
- | (1<<(v->vcpu_id+8))
- | (1<<(v->vcpu_id+16))
- | (1<<(v->vcpu_id+24));
INIT_LIST_HEAD(&v->arch.vgic.inflight_irqs);
INIT_LIST_HEAD(&v->arch.vgic.lr_pending);
spin_lock_init(&v->arch.vgic.lock);
@@ -148,205 +145,7 @@ int vcpu_vgic_free(struct vcpu *v)
return 0;
}
-static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
-{
- struct hsr_dabt dabt = info->dabt;
- struct cpu_user_regs *regs = guest_cpu_user_regs();
- register_t *r = select_user_reg(regs, dabt.reg);
- struct vgic_irq_rank *rank;
- int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
-
- switch ( gicd_reg )
- {
- case GICD_CTLR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- vgic_lock(v);
- *r = v->domain->arch.vgic.ctlr;
- vgic_unlock(v);
- return 1;
- case GICD_TYPER:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* No secure world support for guests. */
- vgic_lock(v);
- *r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
- |( ((v->domain->arch.vgic.nr_lines/32)) & GICD_TYPE_LINES );
- vgic_unlock(v);
- return 1;
- case GICD_IIDR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /*
- * XXX Do we need a JEP106 manufacturer ID?
- * Just use the physical h/w value for now
- */
- *r = 0x0000043b;
- return 1;
-
- /* Implementation defined -- read as zero */
- case 0x020 ... 0x03c:
- goto read_as_zero;
-
- case GICD_IGROUPR ... GICD_IGROUPRN:
- /* We do not implement security extensions for guests, read zero */
- goto read_as_zero;
-
- case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->ienable;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->ienable;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->iactive;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->iactive;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ITARGETSR ... GICD_ITARGETSRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
-
- vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
- DABT_WORD)];
- if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
-
- vgic_lock_rank(v, rank);
- *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
- DABT_WORD)];
- if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICFGR ... GICD_ICFGRN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_NSACR ... GICD_NSACRN:
- /* We do not implement security extensions for guests, read zero */
- goto read_as_zero;
-
- case GICD_SGIR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* Write only -- read unknown */
- *r = 0xdeadbeef;
- return 1;
-
- case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- /* Implementation defined -- read as zero */
- case 0xfd0 ... 0xfe4:
- goto read_as_zero;
-
- case GICD_ICPIDR2:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled read from ICPIDR2\n");
- return 0;
-
- /* Implementation defined -- read as zero */
- case 0xfec ... 0xffc:
- goto read_as_zero;
-
- /* Reserved -- read as zero */
- case 0x00c ... 0x01c:
- case 0x040 ... 0x07c:
- case 0x7fc:
- case 0xbfc:
- case 0xf04 ... 0xf0c:
- case 0xf30 ... 0xfcc:
- goto read_as_zero;
-
- default:
- printk("vGICD: unhandled read r%d offset %#08x\n",
- dabt.reg, gicd_reg);
- return 0;
- }
-
-bad_width:
- printk("vGICD: bad read width %d r%d offset %#08x\n",
- dabt.size, dabt.reg, gicd_reg);
- domain_crash_synchronous();
- return 0;
-
-read_as_zero:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- *r = 0;
- return 1;
-}
-
-static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
+void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
{
const unsigned long mask = r;
struct pending_irq *p;
@@ -369,7 +168,7 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
+void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
{
const unsigned long mask = r;
struct pending_irq *p;
@@ -405,246 +204,58 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static int vgic_to_sgi(struct vcpu *v, register_t sgir)
+/* TODO: unsigned long is used to fit vcpu_mask. Change to cpu_mask */
+int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
+ unsigned long vcpu_mask)
{
struct domain *d = v->domain;
- int virtual_irq;
- int filter;
int vcpuid;
int i;
- unsigned long vcpu_mask = 0;
ASSERT(d->max_vcpus < 8*sizeof(vcpu_mask));
- filter = (sgir & GICD_SGI_TARGET_LIST_MASK);
- virtual_irq = (sgir & GICD_SGI_INTID_MASK);
- ASSERT( virtual_irq < 16 );
+ ASSERT( virq < 16 );
- switch ( filter )
+ switch ( irqmode )
{
- case GICD_SGI_TARGET_LIST:
- vcpu_mask = (sgir & GICD_SGI_TARGET_MASK) >> GICD_SGI_TARGET_SHIFT;
- break;
- case GICD_SGI_TARGET_OTHERS:
- for ( i = 0; i < d->max_vcpus; i++ )
- {
- if ( i != current->vcpu_id && is_vcpu_online(d, i) )
- set_bit(i, &vcpu_mask);
- }
- break;
- case GICD_SGI_TARGET_SELF:
- set_bit(current->vcpu_id, &vcpu_mask);
- break;
- default:
- gdprintk(XENLOG_WARNING, "vGICD: unhandled GICD_SGIR write %"PRIregister" with wrong TargetListFilter field\n",
- sgir);
- return 0;
+ case SGI_TARGET_LIST:
+ break;
+ case SGI_TARGET_OTHERS:
+ for ( i = 0; i < d->max_vcpus; i++ )
+ {
+ if ( i != current->vcpu_id && is_vcpu_online(d, i) )
+ set_bit(i, &vcpu_mask);
+ }
+ break;
+ case SGI_TARGET_SELF:
+ set_bit(current->vcpu_id, &vcpu_mask);
+ break;
+ default:
+ gdprintk(XENLOG_WARNING,
+ "vGICD:unhandled GICD_SGIR write %"PRIregister" \
+ with wrong mode\n", sgir);
+ return 0;
}
for_each_set_bit( vcpuid, &vcpu_mask, d->max_vcpus )
{
if ( !is_vcpu_online(d, vcpuid) )
{
- gdprintk(XENLOG_WARNING, "vGICD: GICD_SGIR write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
- sgir, vcpu_mask);
+ gdprintk(XENLOG_WARNING, "VGIC: write r=%"PRIregister" \
+ vcpu_mask=%lx, wrong CPUTargetList\n", sgir, vcpu_mask);
continue;
}
- vgic_vcpu_inject_irq(d->vcpu[vcpuid], virtual_irq);
+ vgic_vcpu_inject_irq(d->vcpu[vcpuid], virq);
}
+
return 1;
}
-static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+int vgic_send_sgi(struct vcpu *v, register_t sgir)
{
- struct hsr_dabt dabt = info->dabt;
- struct cpu_user_regs *regs = guest_cpu_user_regs();
- register_t *r = select_user_reg(regs, dabt.reg);
- struct vgic_irq_rank *rank;
- int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
- uint32_t tr;
-
- switch ( gicd_reg )
- {
- case GICD_CTLR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* Ignore all but the enable bit */
- v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
- return 1;
-
- /* R/O -- write ignored */
- case GICD_TYPER:
- case GICD_IIDR:
- goto write_ignore;
-
- /* Implementation defined -- write ignored */
- case 0x020 ... 0x03c:
- goto write_ignore;
-
- case GICD_IGROUPR ... GICD_IGROUPRN:
- /* We do not implement security extensions for guests, write ignore */
- goto write_ignore;
-
- case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- tr = rank->ienable;
- rank->ienable |= *r;
- vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr),
- (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
- return 1;
-
- case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- tr = rank->ienable;
- rank->ienable &= ~*r;
- vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr,
- (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
- return 1;
-
- case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
- return 0;
-
- case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
- return 0;
-
- case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->iactive &= ~*r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->iactive &= ~*r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ITARGETSR ... GICD_ITARGETSR + 7:
- /* SGI/PPI target is read only */
- goto write_ignore;
-
- case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- if ( dabt.size == DABT_WORD )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
- DABT_WORD)] = *r;
- else
- {
- tr = REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- vgic_byte_write(&rank->itargets[tr], *r, gicd_reg);
- }
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- if ( dabt.size == DABT_WORD )
- rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
- DABT_WORD)] = *r;
- else
- {
- tr = REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- vgic_byte_write(&rank->ipriority[tr], *r, gicd_reg);
- }
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICFGR: /* SGIs */
- goto write_ignore;
- case GICD_ICFGR + 1: /* PPIs */
- /* It is implementation defined if these are writeable. We chose not */
- goto write_ignore;
- case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_NSACR ... GICD_NSACRN:
- /* We do not implement security extensions for guests, write ignore */
- goto write_ignore;
-
- case GICD_SGIR:
- if ( dabt.size != 2 )
- goto bad_width;
- return vgic_to_sgi(v, *r);
-
- case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
- return 0;
-
- case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
- return 0;
-
- /* Implementation defined -- write ignored */
- case 0xfd0 ... 0xfe4:
- goto write_ignore;
-
- /* R/O -- write ignore */
- case GICD_ICPIDR2:
- goto write_ignore;
-
- /* Implementation defined -- write ignored */
- case 0xfec ... 0xffc:
- goto write_ignore;
-
- /* Reserved -- write ignored */
- case 0x00c ... 0x01c:
- case 0x040 ... 0x07c:
- case 0x7fc:
- case 0xbfc:
- case 0xf04 ... 0xf0c:
- case 0xf30 ... 0xfcc:
- goto write_ignore;
+ const struct domain *d = v->domain;
- default:
- printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
- dabt.reg, *r, gicd_reg);
- return 0;
- }
-
-bad_width:
- printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
- dabt.size, dabt.reg, *r, gicd_reg);
- domain_crash_synchronous();
- return 0;
-
-write_ignore:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- return 1;
+ return d->arch.vgic.handler->send_sgi(v, sgir);
}
struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 2a1e976..32d0554 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -76,6 +76,8 @@ struct arch_domain
} virt_timer_base;
struct {
+ /* GIC HW version specific vGIC driver handler */
+ const struct vgic_ops *handler;
/*
* Covers access to other members of this struct _except_ for
* shared_irqs where each member contains its own locking.
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 875729e..a0c07bf 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -53,8 +53,11 @@
#define GICD_SGI_TARGET_LIST_SHIFT (24)
#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
#define GICD_SGI_TARGET_LIST (0UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_LIST_VAL (0)
#define GICD_SGI_TARGET_OTHERS (1UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_OTHERS_VAL (1)
#define GICD_SGI_TARGET_SELF (2UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_SELF_VAL (2)
#define GICD_SGI_TARGET_SHIFT (16)
#define GICD_SGI_TARGET_MASK (0xFFUL<<GICD_SGI_TARGET_SHIFT)
#define GICD_SGI_GROUP1 (1UL<<15)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 7c71d16..b5c75a3 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -86,6 +86,15 @@ struct vgic_irq_rank {
uint32_t itargets[8];
};
+struct vgic_ops {
+ /* Initialize vGIC */
+ int (*vcpu_init)(struct vcpu *v);
+ /* Domain specific initialization of vGIC */
+ int (*domain_init)(struct domain *d);
+ /* SGI handler of vGIC */
+ int (*send_sgi)(struct vcpu *v, register_t sgir);
+};
+
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
@@ -133,6 +142,8 @@ static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
*reg |= var;
}
+extern enum gic_sgi_mode irqmode;
+
/*
* Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> size <s> with
* <b>-bits-per-interrupt.
@@ -145,8 +156,17 @@ extern int vcpu_vgic_init(struct vcpu *v);
extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
+extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s);
+extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
+extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
+extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
+int vgic_v2_init(struct domain *d);
extern int vcpu_vgic_free(struct vcpu *v);
+extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
+ enum gic_sgi_mode irqmode, int virq,
+ unsigned long vcpu_mask);
+extern int vgic_send_sgi(struct vcpu *v, register_t sgir);
#endif /* __ASM_ARM_VGIC_H__ */
/*
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (15 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
@ 2014-06-26 5:34 ` vijay.kilari
2014-06-26 14:33 ` Julien Grall
2014-06-27 13:40 ` [PATCH v6a 00/17] GIC and VGIC code refactoring Ian Campbell
17 siblings, 1 reply; 43+ messages in thread
From: vijay.kilari @ 2014-06-26 5:34 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Check for idle domain is missing before saving gic context
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/gic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 4746f89..a683440 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -70,6 +70,9 @@ void gic_save_state(struct vcpu *v)
{
ASSERT(!local_irq_is_enabled());
+ if ( is_idle_vcpu(v) )
+ return;
+
/* No need for spinlocks here because interrupts are disabled around
* this call and it only accesses struct vcpu fields that cannot be
* accessed simultaneously by another pCPU.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h
2014-06-26 5:34 ` [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h vijay.kilari
@ 2014-06-26 9:41 ` Jan Beulich
2014-06-27 13:55 ` Ian Campbell
0 siblings, 1 reply; 43+ messages in thread
From: Jan Beulich @ 2014-06-26 9:41 UTC (permalink / raw)
To: vijay.kilari
Cc: keir, Ian.Campbell, stefano.stabellini, Prasun.Kapoor,
Vijaya Kumar K, julien.grall, tim, george.dunlap, xen-devel,
stefano.stabellini
>>> On 26.06.14 at 07:34, <vijay.kilari@gmail.com> wrote:
> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -829,6 +829,22 @@ void watchdog_domain_destroy(struct domain *d);
> #define need_iommu(d) (0)
> #endif
>
> +static inline bool_t is_vcpu_online(const struct domain *d, int vcpuid)
unsigned int please.
> +{
> + const struct vcpu *v;
> +
> + if ( vcpuid >= d->max_vcpus || d->vcpu == NULL )
> + return 0;
> +
> + v = d->vcpu[vcpuid];
> + if ( v == NULL )
> + return 0;
> + if ( test_bit(_VPF_down, &v->pause_flags) )
> + return 0;
> +
> + return 1;
I'd prefer the simpler "return !test_bit()".
Jan
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 03/17] xen/arm: make sgi handling generic
2014-06-26 5:33 ` [PATCH v6a 03/17] xen/arm: make sgi handling generic vijay.kilari
@ 2014-06-26 11:47 ` Julien Grall
2014-06-26 11:51 ` Ian Campbell
2014-06-27 12:42 ` Ian Campbell
1 sibling, 1 reply; 43+ messages in thread
From: Julien Grall @ 2014-06-26 11:47 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:33 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> move all the hw specific sgi handling functionality
> to one function and use it.
>
> changes in v6a: change send_SGI() parameter order
You have to add --- and a newline before it.
When a commiters (such as Ian) will apply your patch, everything written
after --- will be striped.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 03/17] xen/arm: make sgi handling generic
2014-06-26 11:47 ` Julien Grall
@ 2014-06-26 11:51 ` Ian Campbell
0 siblings, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-26 11:51 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-26 at 12:47 +0100, Julien Grall wrote:
> Hi Vijay,
>
> On 06/26/2014 06:33 AM, vijay.kilari@gmail.com wrote:
> > From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >
> > move all the hw specific sgi handling functionality
> > to one function and use it.
> >
> > changes in v6a: change send_SGI() parameter order
>
> You have to add --- and a newline before it.
> When a commiters (such as Ian) will apply your patch, everything written
> after --- will be striped.
Please do it next time. No need to resend just for this.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers
2014-06-26 5:33 ` [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
@ 2014-06-26 12:07 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:07 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:33 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic-v2 driver uses fixmap to map the registers.
> Instead use ioremap to access mmio registers.
>
> With this patch, gic-v2 register definitions are updated
> to use absolute offset address instead of dividing the
> register offset by 4.
I remembered I requested to made some changes in this patch. I saw you
did it but you didn't specify in the changelog. People may not be agree
with your new changes and you should notifying about any change in the code!
[..]
> @@ -229,8 +232,7 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> const cpumask_t *cpu_mask,
> unsigned int priority)
> {
> - volatile unsigned char *bytereg;
> - uint32_t cfg, edgebit;
> + uint32_t cfg, edgebit, itarget, ipriority;
> unsigned int mask;
> unsigned int irq = desc->irq;
> unsigned int type = desc->arch.type;
> @@ -243,21 +245,28 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> mask = gic_cpu_mask(cpu_mask);
>
> /* Set edge / level */
> - cfg = GICD[GICD_ICFGR + irq / 16];
> + cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
> edgebit = 2u << (2 * (irq % 16));
> if ( type & DT_IRQ_TYPE_LEVEL_MASK )
> cfg &= ~edgebit;
> else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
> cfg |= edgebit;
> - GICD[GICD_ICFGR + irq / 16] = cfg;
> + writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
>
> /* Set target CPU mask (RAZ/WI on uniprocessor) */
> - bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
> - bytereg[irq] = mask;
> -
> + itarget = readl_relaxed(GICD + GICD_ITARGETSR + (irq / 4) * 4);
> + /* Clear mask */
> + itarget &= ~(0xffu << (8 * (irq % 4)));
> + /* Set mask */
> + itarget |= mask << (8 * (irq % 4));
> + writel_relaxed(itarget, GICD + GICD_ITARGETSR + (irq / 4) * 4);
Why didn't you use writeb_relaxed? This change is complex for nothing.
writeb_relaxed(mask, GICD + GICD_ITARGETSR + irq);
> +
> + ipriority = readl_relaxed(GICD + GICD_IPRIORITYR + (irq / 4) * 4);
> + /* Clear priority */
> + ipriority &= ~(0xffu << (8 * (irq % 4)));
> /* Set priority */
> - bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR);
> - bytereg[irq] = priority;
> + ipriority |= priority << (8 * (irq % 4));
> + writel_relaxed(ipriority, GICD + GICD_IPRIORITYR + (irq / 4) * 4);
writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality
2014-06-26 5:33 ` [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality vijay.kilari
@ 2014-06-26 12:21 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:21 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:33 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> GIC driver contains both generic and hardware specific low
> level functionality in gic.c file.
>
> With this patch, low level functionality is moved to separate
> file gic-v2.c and generic code is kept in gic.c file
>
> Callbacks are registered by low level driver with generic driver
> and are called wherever required.
>
> The locking mechanism is not changed.
>
> This helps to separate generic and hardware functionality
> and implement future hardware version drivers.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
I never acked this patch...
[..]
> +static void update_cpu_lr_mask(void)
Even if you made this function static, the function name still not match
what it does...
This function clear the LRs mask, I would call it:
clear_cpu_lr_mask(void)
> +{
> + this_cpu(lr_mask) = 0ULL;
> +}
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver
2014-06-26 5:33 ` [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver vijay.kilari
@ 2014-06-26 12:26 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:26 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
NIT on the commit title:
s#arm/xen#xen/arm# to stay to consistent with the rest of your series.
Regards,
On 06/26/2014 06:33 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> arch_domain in domain.h defines all the GIC registers
> that needs to be saved/restored directly.
>
> These GIC registers are GIC HW version specific. The number
> of registers and size of registers varies with GIC version.
> So move these registers to gic.h file and make a union of these
> registers. This helps to define GIC HW version specific
> structure to this union for later GIC versions.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> Acked-by: Ian Campbell <ian.campbell@citrix.com>
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 08/17] xen/arm: use device api to detect GIC version
2014-06-26 5:34 ` [PATCH v6a 08/17] xen/arm: use device api to detect GIC version vijay.kilari
@ 2014-06-26 12:29 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:29 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> @@ -164,7 +165,29 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
> /* Set up the GIC */
> void __init gic_init(void)
> {
> - gicv2_init();
> + int rc;
> + struct dt_device_node *node;
> + bool_t num_gics = 0;
Sorry I didn't catch it earlier. Naming a boolean num_gics is odd. I
would use unsigned int here, because the purpose of this variable is to
count the number of GICs.
Even though we support only 1 GIC for now.
> +
> + dt_for_each_device_node( dt_host, node )
> + {
> + if ( !dt_get_property(node, "interrupt-controller", NULL) )
> + continue;
> +
> + if ( !dt_get_parent(node) )
> + continue;
> +
> + rc = device_init(node, DEVICE_GIC, NULL);
> + if ( !rc )
> + {
> + /* NOTE: Only one GIC is supported */
> + num_gics = 1;
> + break;
> + }
> + }
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-26 5:34 ` [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
@ 2014-06-26 12:37 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:37 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> prefix byte_read and byte_write vgic functions with vgic_
> to make these function vgic specific.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
Another patch I've never acked...
For this patch, and only this one, you can keep my ack. Please avoid to
do a such thing next time.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file
2014-06-26 5:34 ` [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file vijay.kilari
@ 2014-06-26 12:40 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:40 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic.h contains defines of vgic. Move these to vgic
> header file. Also move inline functions and defines/macros
> in vgic.c to vgic.h. These vgic functions and macros
> can be used by other GIC HW specific VGIC drivers,
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> Acked-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file
2014-06-26 5:34 ` [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file vijay.kilari
@ 2014-06-26 12:46 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:46 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index ed610cb..875729e 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -143,6 +143,7 @@
> #ifndef __ASSEMBLY__
> #include <xen/device_tree.h>
> #include <xen/irq.h>
> +#include <asm-arm/vgic.h>
We usually use the directory asm rather than asm-arm.
With that change:
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size
2014-06-26 5:34 ` [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size vijay.kilari
@ 2014-06-26 12:58 ` Julien Grall
2014-06-27 13:57 ` Ian Campbell
0 siblings, 1 reply; 43+ messages in thread
From: Julien Grall @ 2014-06-26 12:58 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> vGIC irq rank was computed assuming the register offset is byte
> size.Use the HSR abort address size in calculating register size.
>
> So, with this patch following are acheived
s/acheived/achieved/
> (1) In the code 'dabt.size != number' this number is always
> BYTE/HALF_WORD/WORD/DOUBLE defined by hsr registers.
> Instead of checking for hard coded values use HSR abort
> address size values.
> (2) The vgic_irq_rank also depends on the same HSR defined
s/vgic_irq_rank/vgic_irq_rank_offset/
> values to calculate irq rank.
>
> This make vgic_irq_rank generic as it takes register
Same here.
> size as parameter to calculate irq rank instead of hard coding to
> value 2 in previous patches
>
> Also, output of REG_RANK_INDEX macro is modulo by 32 to make
> sure register index is always within irq rank
I though a bit more about this patch. You are using the value of
DABT_{WORD,...} for multiple things that have non-sense together.
While it's perfectly fine to use it to check dabt.size, the
vgic_rank_offset is using this value for shift. Assuming that DABT_*
will always contains the right shift is completely wrong.
You have either to explain it somewhere or define a new set of defines.
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index ebc683d..22a1998 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -251,6 +251,14 @@ extern struct cpuinfo_arm cpu_data[];
> extern u32 __cpu_logical_map[];
> #define cpu_logical_map(cpu) __cpu_logical_map[cpu]
>
> +/* HSR data abort size definition */
> +enum dabt_size {
> + DABT_BYTE = 0,
> + DABT_HALF_WORD = 1,
> + DABT_WORD = 2,
> + DABT_DOUBLE_WORD = 3,
> +};
> +
The enum looks like pointless here as you never use the defined type...
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-26 5:34 ` [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
@ 2014-06-26 14:30 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-26 14:30 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
[..]
> +const struct mmio_handler_ops vgic_v2_distr_mmio_handler = {
There was a static on the previous location of this code. You should
keep it.
[..]
> +const static struct vgic_ops vgic_v2_ops = {
static const
[..]
> int domain_vgic_init(struct domain *d)
> {
> int i;
> @@ -75,6 +67,15 @@ int domain_vgic_init(struct domain *d)
> else
> d->arch.vgic.nr_lines = 0; /* We don't need SPIs for the guest */
>
> + switch ( gic_hw_version() )
> + {
> + case GIC_V2:
> + vgic_v2_init(d);
vgic_v2_init is returning an int to indicate if initialization has
succeeded or not. Please check the return to see if there is an error.
[..]
> -static int vgic_to_sgi(struct vcpu *v, register_t sgir)
> +/* TODO: unsigned long is used to fit vcpu_mask. Change to cpu_mask */
> +int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
> + unsigned long vcpu_mask)
> {
[..]
> + case SGI_TARGET_OTHERS:
[..]
> + case SGI_TARGET_SELF:
> + set_bit(current->vcpu_id, &vcpu_mask);
I already said it on V4 and V5 and don't see any change here...
For SGI_TARGET_{OTHERS,SELF}, you can't assume that vcpu_mask will be
equal to 0...
it comes directly from GICD_SIGR. Please make sure to handle it or the
guest could send SGI to the wrong VCPUs.
[..]
> +struct vgic_ops {
> + /* Initialize vGIC */
> + int (*vcpu_init)(struct vcpu *v);
> + /* Domain specific initialization of vGIC */
> + int (*domain_init)(struct domain *d);
> + /* SGI handler of vGIC */
> + int (*send_sgi)(struct vcpu *v, register_t sgir);
You've introduce vgic_send_sgi here, I'm not sure to understand why...
Can you give a bit more input?
> +};
> +
> +extern enum gic_sgi_mode irqmode;
> +
Hu? What is used for?
Regards
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-26 5:34 ` [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain vijay.kilari
@ 2014-06-26 14:33 ` Julien Grall
2014-06-27 14:45 ` Ian Campbell
0 siblings, 1 reply; 43+ messages in thread
From: Julien Grall @ 2014-06-26 14:33 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Check for idle domain is missing before saving gic context
Can you be a bit more verbose to explain why we don't need to save
context for idle vcpu?
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 03/17] xen/arm: make sgi handling generic
2014-06-26 5:33 ` [PATCH v6a 03/17] xen/arm: make sgi handling generic vijay.kilari
2014-06-26 11:47 ` Julien Grall
@ 2014-06-27 12:42 ` Ian Campbell
1 sibling, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 12:42 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-26 at 11:03 +0530, vijay.kilari@gmail.com wrote:
> @@ -512,18 +531,18 @@ void send_SGI_self(enum gic_sgi sgi)
>
> dsb(sy);
>
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF
> - | sgi;
> + send_SGI(sgi, SGI_TARGET_SELF, cpumask_of(smp_processor_id()));
You should pass NULL here. As I said on v5 If the gicv3 code needs to
create a mask then it should do so based on gic_sgi_mode only.
> + send_SGI(sgi, SGI_TARGET_OTHERS, &all_others_mask);
Likewise here.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 00/17] GIC and VGIC code refactoring
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
` (16 preceding siblings ...)
2014-06-26 5:34 ` [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain vijay.kilari
@ 2014-06-27 13:40 ` Ian Campbell
17 siblings, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 13:40 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-26 at 11:03 +0530, vijay.kilari@gmail.com wrote:
> Vijaya Kumar K (17):
> xen/arm: move io.h as mmio.h to include folder
> xen/arm: make mmio handlers domain specific
Applied.
> xen/arm: make sgi handling generic
Commented.
> xen/arm: remove unused parameter in do_sgi call
Applied.
At which point Julien had comments on a few things. I didn't look
closely for things which could be cherry-picked further down.
> xen/arm: use ioremap to map gic-v2 registers
> xen/arm: segregate and split GIC low level functionality
> arm/xen: move GIC context data structure to gic driver
> xen/arm: use device api to detect GIC version
> xen/arm: switch to dynamic allocation of vgic rank
> xen/arm: prefix byte_read and byte_write functions with vgic
> xen/arm: move vgic defines to vgic header file
> xen/arm: move and rename is_vcpu_running function to sched.h
> xen/arm: move pending_irq structure to vgic header file
> xen/arm: calculate vgic irq rank based on register size
> xen/arm: Remove REG macro in vgic driver
> xen/arm: split vgic driver into generic and vgic-v2 driver
> xen/arm: Restrict saving of gic register for idle domain
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h
2014-06-26 9:41 ` Jan Beulich
@ 2014-06-27 13:55 ` Ian Campbell
2014-06-27 14:05 ` Jan Beulich
0 siblings, 1 reply; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 13:55 UTC (permalink / raw)
To: Jan Beulich
Cc: keir, vijay.kilari, stefano.stabellini, Prasun.Kapoor,
Vijaya Kumar K, julien.grall, tim, george.dunlap, xen-devel,
stefano.stabellini
On Thu, 2014-06-26 at 10:41 +0100, Jan Beulich wrote:
> >>> On 26.06.14 at 07:34, <vijay.kilari@gmail.com> wrote:
> > --- a/xen/include/xen/sched.h
> > +++ b/xen/include/xen/sched.h
> > @@ -829,6 +829,22 @@ void watchdog_domain_destroy(struct domain *d);
> > #define need_iommu(d) (0)
> > #endif
> >
> > +static inline bool_t is_vcpu_online(const struct domain *d, int vcpuid)
>
> unsigned int please.
OOI why the preference for that when the return is boolean?
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size
2014-06-26 12:58 ` Julien Grall
@ 2014-06-27 13:57 ` Ian Campbell
0 siblings, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 13:57 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-26 at 13:58 +0100, Julien Grall wrote:
> > +/* HSR data abort size definition */
> > +enum dabt_size {
> > + DABT_BYTE = 0,
> > + DABT_HALF_WORD = 1,
> > + DABT_WORD = 2,
> > + DABT_DOUBLE_WORD = 3,
> > +};
> > +
>
> The enum looks like pointless here as you never use the defined type...
Using an enum just to get named values like this is completely fine
though.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h
2014-06-27 13:55 ` Ian Campbell
@ 2014-06-27 14:05 ` Jan Beulich
2014-06-27 14:51 ` Ian Campbell
0 siblings, 1 reply; 43+ messages in thread
From: Jan Beulich @ 2014-06-27 14:05 UTC (permalink / raw)
To: Ian Campbell
Cc: keir, vijay.kilari, stefano.stabellini, Prasun.Kapoor,
Vijaya KumarK, julien.grall, tim, george.dunlap, xen-devel,
stefano.stabellini
>>> On 27.06.14 at 15:55, <Ian.Campbell@citrix.com> wrote:
> On Thu, 2014-06-26 at 10:41 +0100, Jan Beulich wrote:
>> >>> On 26.06.14 at 07:34, <vijay.kilari@gmail.com> wrote:
>> > --- a/xen/include/xen/sched.h
>> > +++ b/xen/include/xen/sched.h
>> > @@ -829,6 +829,22 @@ void watchdog_domain_destroy(struct domain *d);
>> > #define need_iommu(d) (0)
>> > #endif
>> >
>> > +static inline bool_t is_vcpu_online(const struct domain *d, int vcpuid)
>>
>> unsigned int please.
>
> OOI why the preference for that when the return is boolean?
Oh, I meant the plain int parameter, not the return value.
Jan
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-26 14:33 ` Julien Grall
@ 2014-06-27 14:45 ` Ian Campbell
2014-06-27 14:52 ` Ian Campbell
2014-06-27 14:58 ` Julien Grall
0 siblings, 2 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 14:45 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
> Hi Vijay,
>
> On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> > From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >
> > Check for idle domain is missing before saving gic context
>
> Can you be a bit more verbose to explain why we don't need to save
> context for idle vcpu?
There's lots of state you don't need to save for an idle domain, this
one seems pretty clear cut to me.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h
2014-06-27 14:05 ` Jan Beulich
@ 2014-06-27 14:51 ` Ian Campbell
0 siblings, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 14:51 UTC (permalink / raw)
To: Jan Beulich
Cc: keir, vijay.kilari, stefano.stabellini, Prasun.Kapoor,
Vijaya KumarK, julien.grall, tim, george.dunlap, xen-devel,
stefano.stabellini
On Fri, 2014-06-27 at 15:05 +0100, Jan Beulich wrote:
> >>> On 27.06.14 at 15:55, <Ian.Campbell@citrix.com> wrote:
> > On Thu, 2014-06-26 at 10:41 +0100, Jan Beulich wrote:
> >> >>> On 26.06.14 at 07:34, <vijay.kilari@gmail.com> wrote:
> >> > --- a/xen/include/xen/sched.h
> >> > +++ b/xen/include/xen/sched.h
> >> > @@ -829,6 +829,22 @@ void watchdog_domain_destroy(struct domain *d);
> >> > #define need_iommu(d) (0)
> >> > #endif
> >> >
> >> > +static inline bool_t is_vcpu_online(const struct domain *d, int vcpuid)
> >>
> >> unsigned int please.
> >
> > OOI why the preference for that when the return is boolean?
>
> Oh, I meant the plain int parameter, not the return value.
Ah. Yes, that makes sense!
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-27 14:45 ` Ian Campbell
@ 2014-06-27 14:52 ` Ian Campbell
2014-06-27 15:03 ` Julien Grall
2014-06-27 14:58 ` Julien Grall
1 sibling, 1 reply; 43+ messages in thread
From: Ian Campbell @ 2014-06-27 14:52 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Fri, 2014-06-27 at 15:45 +0100, Ian Campbell wrote:
> On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
> > Hi Vijay,
> >
> > On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> > > From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> > >
> > > Check for idle domain is missing before saving gic context
> >
> > Can you be a bit more verbose to explain why we don't need to save
> > context for idle vcpu?
>
> There's lots of state you don't need to save for an idle domain, this
> one seems pretty clear cut to me.
Although it might be useful to consider whether the tail:
/* Disable until next VCPU scheduled */
GICH[GICH_HCR] = 0;
isb();
should be done for idle domains too. I suspect yes.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-27 14:45 ` Ian Campbell
2014-06-27 14:52 ` Ian Campbell
@ 2014-06-27 14:58 ` Julien Grall
2014-07-01 6:24 ` Vijay Kilari
1 sibling, 1 reply; 43+ messages in thread
From: Julien Grall @ 2014-06-27 14:58 UTC (permalink / raw)
To: Ian Campbell
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On 27/06/14 15:45, Ian Campbell wrote:
> On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
>> Hi Vijay,
>>
>> On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>>
>>> Check for idle domain is missing before saving gic context
>>
>> Can you be a bit more verbose to explain why we don't need to save
>> context for idle vcpu?
>
> There's lots of state you don't need to save for an idle domain, this
> one seems pretty clear cut to me.
Right. Actually, for a lambda developer it's not clear why we add
non-stop is_idle_vcpu on every save/restore functions.
As the Xen will always stay to hyp mode when the idle VCPU is running,
why do we simply skip ctx_to/ctx_from?
It would make more sense and we will be able to put a big comment to
clearly explain how idle VCPU works.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-27 14:52 ` Ian Campbell
@ 2014-06-27 15:03 ` Julien Grall
0 siblings, 0 replies; 43+ messages in thread
From: Julien Grall @ 2014-06-27 15:03 UTC (permalink / raw)
To: Ian Campbell
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On 27/06/14 15:52, Ian Campbell wrote:
> On Fri, 2014-06-27 at 15:45 +0100, Ian Campbell wrote:
>> On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
>>> Hi Vijay,
>>>
>>> On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
>>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>>>
>>>> Check for idle domain is missing before saving gic context
>>>
>>> Can you be a bit more verbose to explain why we don't need to save
>>> context for idle vcpu?
>>
>> There's lots of state you don't need to save for an idle domain, this
>> one seems pretty clear cut to me.
>
> Although it might be useful to consider whether the tail:
> /* Disable until next VCPU scheduled */
> GICH[GICH_HCR] = 0;
> isb();
> should be done for idle domains too. I suspect yes.
I think we don't care as the virtual CPU interface will never used when
an idle VCPU is running.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-06-27 14:58 ` Julien Grall
@ 2014-07-01 6:24 ` Vijay Kilari
2014-07-02 9:43 ` Ian Campbell
0 siblings, 1 reply; 43+ messages in thread
From: Vijay Kilari @ 2014-07-01 6:24 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
Hi Julien,
On Fri, Jun 27, 2014 at 8:28 PM, Julien Grall <julien.grall@linaro.org> wrote:
> On 27/06/14 15:45, Ian Campbell wrote:
>>
>> On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
>>>
>>> Hi Vijay,
>>>
>>> On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
>>>>
>>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>>>
>>>> Check for idle domain is missing before saving gic context
>>>
>>>
>>> Can you be a bit more verbose to explain why we don't need to save
>>> context for idle vcpu?
>>
>>
>> There's lots of state you don't need to save for an idle domain, this
>> one seems pretty clear cut to me.
>
>
> Right. Actually, for a lambda developer it's not clear why we add non-stop
> is_idle_vcpu on every save/restore functions.
> As the Xen will always stay to hyp mode when the idle VCPU is running, why
> do we simply skip ctx_to/ctx_from?
>
> It would make more sense and we will be able to put a big comment to clearly
> explain how idle VCPU works.
My knowledge on this topic is limited to explain in detail how idle
VCPU works
in Xen.
>
> Regards,
>
> --
> Julien Grall
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain
2014-07-01 6:24 ` Vijay Kilari
@ 2014-07-02 9:43 ` Ian Campbell
0 siblings, 0 replies; 43+ messages in thread
From: Ian Campbell @ 2014-07-02 9:43 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel, Stefano Stabellini
On Tue, 2014-07-01 at 11:54 +0530, Vijay Kilari wrote:
> Hi Julien,
>
> On Fri, Jun 27, 2014 at 8:28 PM, Julien Grall <julien.grall@linaro.org> wrote:
> > On 27/06/14 15:45, Ian Campbell wrote:
> >>
> >> On Thu, 2014-06-26 at 15:33 +0100, Julien Grall wrote:
> >>>
> >>> Hi Vijay,
> >>>
> >>> On 06/26/2014 06:34 AM, vijay.kilari@gmail.com wrote:
> >>>>
> >>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >>>>
> >>>> Check for idle domain is missing before saving gic context
> >>>
> >>>
> >>> Can you be a bit more verbose to explain why we don't need to save
> >>> context for idle vcpu?
> >>
> >>
> >> There's lots of state you don't need to save for an idle domain, this
> >> one seems pretty clear cut to me.
> >
> >
> > Right. Actually, for a lambda developer it's not clear why we add non-stop
> > is_idle_vcpu on every save/restore functions.
> > As the Xen will always stay to hyp mode when the idle VCPU is running, why
> > do we simply skip ctx_to/ctx_from?
> >
> > It would make more sense and we will be able to put a big comment to clearly
> > explain how idle VCPU works.
>
> My knowledge on this topic is limited to explain in detail how idle
> VCPU worksin Xen.
I don't expect you to. What is needed is a more thorough check/cleanup
of the save/restore paths WRT the idle cpus and what needs to (not) be
saved. I don't expect you to do that either though.
Ian.
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2014-07-02 9:43 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-06-26 5:33 [PATCH v6a 00/17] GIC and VGIC code refactoring vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 01/17] xen/arm: move io.h as mmio.h to include folder vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 02/17] xen/arm: make mmio handlers domain specific vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 03/17] xen/arm: make sgi handling generic vijay.kilari
2014-06-26 11:47 ` Julien Grall
2014-06-26 11:51 ` Ian Campbell
2014-06-27 12:42 ` Ian Campbell
2014-06-26 5:33 ` [PATCH v6a 04/17] xen/arm: remove unused parameter in do_sgi call vijay.kilari
2014-06-26 5:33 ` [PATCH v6a 05/17] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
2014-06-26 12:07 ` Julien Grall
2014-06-26 5:33 ` [PATCH v6a 06/17] xen/arm: segregate and split GIC low level functionality vijay.kilari
2014-06-26 12:21 ` Julien Grall
2014-06-26 5:33 ` [PATCH v6a 07/17] arm/xen: move GIC context data structure to gic driver vijay.kilari
2014-06-26 12:26 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 08/17] xen/arm: use device api to detect GIC version vijay.kilari
2014-06-26 12:29 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 09/17] xen/arm: switch to dynamic allocation of vgic rank vijay.kilari
2014-06-26 5:34 ` [PATCH v6a 10/17] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
2014-06-26 12:37 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 11/17] xen/arm: move vgic defines to vgic header file vijay.kilari
2014-06-26 12:40 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 12/17] xen/arm: move and rename is_vcpu_running function to sched.h vijay.kilari
2014-06-26 9:41 ` Jan Beulich
2014-06-27 13:55 ` Ian Campbell
2014-06-27 14:05 ` Jan Beulich
2014-06-27 14:51 ` Ian Campbell
2014-06-26 5:34 ` [PATCH v6a 13/17] xen/arm: move pending_irq structure to vgic header file vijay.kilari
2014-06-26 12:46 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 14/17] xen/arm: calculate vgic irq rank based on register size vijay.kilari
2014-06-26 12:58 ` Julien Grall
2014-06-27 13:57 ` Ian Campbell
2014-06-26 5:34 ` [PATCH v6a 15/17] xen/arm: Remove REG macro in vgic driver vijay.kilari
2014-06-26 5:34 ` [PATCH v6a 16/17] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
2014-06-26 14:30 ` Julien Grall
2014-06-26 5:34 ` [PATCH v6a 17/17] xen/arm: Restrict saving of gic register for idle domain vijay.kilari
2014-06-26 14:33 ` Julien Grall
2014-06-27 14:45 ` Ian Campbell
2014-06-27 14:52 ` Ian Campbell
2014-06-27 15:03 ` Julien Grall
2014-06-27 14:58 ` Julien Grall
2014-07-01 6:24 ` Vijay Kilari
2014-07-02 9:43 ` Ian Campbell
2014-06-27 13:40 ` [PATCH v6a 00/17] GIC and VGIC code refactoring Ian Campbell
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