From: Marc Zyngier <marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: mark.rutland@arm.com, Will Deacon <will.deacon@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Christoffer Dall <christoffer.dall@linaro.org> Subject: [PATCH v6 04/21] arm64: boot protocol documentation update for GICv3 Date: Mon, 30 Jun 2014 16:01:33 +0100 [thread overview] Message-ID: <1404140510-5382-5-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1404140510-5382-1-git-send-email-marc.zyngier@arm.com> Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- Documentation/arm64/booting.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 37fc4f6..da1d4bf 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -141,6 +141,14 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. + For systems with a GICv3 interrupt controller: + - If EL3 is present: + ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. + ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. + - If the kernel is entered at EL1: + ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 + ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. -- 2.0.0
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 04/21] arm64: boot protocol documentation update for GICv3 Date: Mon, 30 Jun 2014 16:01:33 +0100 [thread overview] Message-ID: <1404140510-5382-5-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1404140510-5382-1-git-send-email-marc.zyngier@arm.com> Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- Documentation/arm64/booting.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 37fc4f6..da1d4bf 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -141,6 +141,14 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. + For systems with a GICv3 interrupt controller: + - If EL3 is present: + ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. + ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. + - If the kernel is entered at EL1: + ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 + ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. -- 2.0.0
next prev parent reply other threads:[~2014-06-30 15:01 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-06-30 15:01 [PATCH v6 00/21] arm64: GICv3 support Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 01/21] irqchip: ARM: GIC: Move some bits of GICv2 to a library-type file Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-07-08 22:31 ` Jason Cooper 2014-07-08 22:31 ` Jason Cooper 2014-07-11 16:15 ` Christoffer Dall 2014-07-11 16:15 ` Christoffer Dall 2014-07-11 20:47 ` Paolo Bonzini 2014-07-11 20:47 ` Paolo Bonzini 2014-07-11 21:41 ` Christoffer Dall 2014-07-11 21:41 ` Christoffer Dall 2014-06-30 15:01 ` [PATCH v6 02/21] irqchip: arm64: Initial support for GICv3 Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 17:58 ` Mark Rutland 2014-06-30 17:58 ` Mark Rutland 2014-06-30 15:01 ` [PATCH v6 03/21] arm64: GICv3 device tree binding documentation Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 16:09 ` Mark Rutland 2014-06-30 16:09 ` Mark Rutland 2014-06-30 15:01 ` Marc Zyngier [this message] 2014-06-30 15:01 ` [PATCH v6 04/21] arm64: boot protocol documentation update for GICv3 Marc Zyngier 2014-06-30 15:56 ` Mark Rutland 2014-06-30 15:56 ` Mark Rutland 2014-06-30 15:01 ` [PATCH v6 05/21] KVM: arm/arm64: vgic: move GICv2 registers to their own structure Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 06/21] KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 07/21] KVM: ARM: vgic: abstract access to the ELRSR bitmap Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 08/21] KVM: ARM: vgic: abstract EISR bitmap access Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 09/21] KVM: ARM: vgic: abstract MISR decoding Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 10/21] KVM: ARM: vgic: move underflow handling to vgic_ops Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 11/21] KVM: ARM: vgic: abstract VMCR access Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 12/21] KVM: ARM: vgic: introduce vgic_enable Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 13/21] KVM: ARM: introduce vgic_params structure Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 14/21] KVM: ARM: vgic: split GICv2 backend from the main vgic code Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 15/21] KVM: ARM: vgic: revisit implementation of irqchip_in_kernel Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 16/21] arm64: KVM: remove __kvm_hyp_code_{start,end} from hyp.S Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 16/21] arm64: KVM: remove __kvm_hyp_code_{start, end} " Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 17/21] arm64: KVM: split GICv2 world switch from hyp code Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 18/21] arm64: KVM: move HCR_EL2.{IMO,FMO} manipulation into the vgic switch code Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 18/21] arm64: KVM: move HCR_EL2.{IMO, FMO} " Marc Zyngier 2014-06-30 15:01 ` [PATCH v6 19/21] KVM: ARM: vgic: add the GICv3 backend Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-07-04 9:42 ` Christoffer Dall 2014-07-04 9:42 ` Christoffer Dall 2014-06-30 15:01 ` [PATCH v6 20/21] arm64: KVM: vgic: add GICv3 world switch Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-07-01 18:24 ` Will Deacon 2014-07-01 18:24 ` Will Deacon 2014-06-30 15:01 ` [PATCH v6 21/21] arm64: KVM: vgic: enable GICv2 emulation on top on GICv3 hardware Marc Zyngier 2014-06-30 15:01 ` Marc Zyngier 2014-07-04 9:58 ` Christoffer Dall 2014-07-04 9:58 ` Christoffer Dall 2014-06-30 15:43 ` [PATCH v6 00/21] arm64: GICv3 support Jason Cooper 2014-06-30 15:43 ` Jason Cooper 2014-06-30 15:50 ` Marc Zyngier 2014-06-30 15:50 ` Marc Zyngier 2014-07-03 17:45 ` Marc Zyngier 2014-07-03 17:45 ` Marc Zyngier 2014-07-08 21:44 ` Jason Cooper 2014-07-08 21:44 ` Jason Cooper
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